Obsolete Device
Please contact Microchip Sales for replacement information.
16 Mbit LPC Serial Flash
SST49LF016C
EOL Data Sheet
The SST49LF016C flash memory device is designed to interface with host controllers (chipsets) that support a low pin-count (LPC) interface for system firmware
applications. Complying with LPC Interface Specification 1.1, SST49LF016C supports a Burst-Read data transfer of 15.6 MBytes per second at 33 MHz clock
speed and 31.2 MBytes per second at 66 MHz clock speed, up to 128 bytes in a
single operation
Features
• Security ID Feature
• Operational Clock Frequency
– 33 MHz
– 66 MHz
– 256-bit Secure ID space
- 64-bit Unique Factory Pre-programmed Device Identifier
- 192-bit User-Programmable OTP
• Organized as 2M x8
• Superior Reliability
• Conforms to LPC Interface Specification v1.1
– Support Multi-Byte Firmware Memory Read/Write
Cycles
• Low Power Consumption
• Single 3.0-3.6V Read and Write Operations
– Active Read Current: 12 mA (typical)
– Standby Current: 10 µA (typical)
• LPC Mode
– 5-signal LPC bus interface for both in-system and factory programming using programmer equipment
– Multi-Byte Read data transfer rate
15.6 MB/s @ 33 MHz PCI clock and
31.2 MB/s @ 66 MHz clock
- Firmware Memory Read cycle supporting
1, 2, 4, 16, and 128 Byte Read
- Firmware Memory Write cycle supporting
1, 2, and 4 Byte Write
– 33 MHz/66 MHz clock frequency operation
– WP#/AAI and TBL# pins provide hardware Write protect
for entire chip and/or top Boot Block
– Block Locking Registers for individual block Read-Lock,
Write-Lock, and Lock-Down protection
– 5 GPI pins for system design flexibility
– 4 ID pins for multi-chip selection
– Multi-Byte capability registers
(read-only registers)
– Status register for End-of-Write detection
– Program-/Erase-Suspend
Read or Write to other blocks during
Program-/Erase-Suspend
• Two-cycle Command Set
©2016
– Endurance: 100,000 Cycles (typical)
– Greater than 100 years Data Retention
• Uniform 4 KByte sectors
– 35 Overlay Blocks: one 16-KByte Boot Block, two 8KByte Parameter Blocks, one 32-Kbyte Parameter
Block, thirty-one 64-KByte Main Blocks.
• Fast Sector-Erase/Program Operation
– Sector-Erase Time: 18 ms (typical)
– Block-Erase Time: 18 ms (typical)
– Program Time: 7 µs (typical)
• Auto Address Increment (AAI) for Rapid Factory
Programming (High Voltage Enabled)
– RY/BY# pin for End-of-Write detection
– Multi-Byte Program
– Chip Rewrite Time: 4 seconds (typical)
• Packages Available
– 32-lead PLCC
– 32-lead TSOP (8mm x 14mm)
– 40-lead TSOP (10mm x 20mm)
• All devices are RoHS compliant
www.microchip.com
DS20005029B
02/16
16 Mbit LPC Serial Flash
SST49LF016C
EOL Data Sheet
Product Description
The SST49LF016C flash memory device is designed to interface with host controllers (chipsets) that
support a low-pin-count (LPC) interface for system firmware applications. Complying with LPC Interface Specification 1.1, SST49LF016C supports a Burst-Read data transfer of 15.6 MBytes per second
at 33 MHz clock speed and 31.2 MBytes per second at 66 MHz clock speed, up to 128 bytes in a single operation.
The LPC interface operates with 5 signal pins versus 28 pins of a 8-bit parallel flash memory. This
frees up pins on the ASIC host controller resulting in lower ASIC costs and a reduction in overall system costs due to simplified signal routing. This 5-signal LPC interface supports both in-system and
rapid factory programming using programmer equipment. A high voltage pin (WP#/AAI) enables Auto
Address Increment (AAI) mode.
Via the software registers, the SST49LF016C offers hardware block protection and individual block
protection for critical system code and data. The 256-bit Security ID space is comprised of a 64-bit factory pre-programmed unique number and a 192-bit One-Time-Programmable (OTP) area. This Security ID permits the use of new security techniques and implementation of a new data protection
scheme. To protect against inadvertent write, the SST49LF016C device has on-chip hardware and
software write protection schemes. The SST49LF016C also provides general purpose inputs (GPI) for
system design flexibility.
Manufactured with SST proprietary, high-performance SuperFlash technology, SST49LF016C has a
split-gate cell design and thick-oxide tunneling injector for greater reliability and manufacturability compared with alternative technology approaches.
The SST49LF016C significantly improves performance and reliability, while lowering power consumption. The total energy consumed is a function of the applied voltage, current and time of application.
Because the SST49LF016C writes in-system with a single 3.0-3.6V power supply, the total energy
consumed during any Erase or Program operation is less than alternative flash memory technologies.
The SuperFlash technology provides fixed Erase and Program time, independent of the number of
Erase/Program cycles performed. This feature eliminates system software or hardware calibration or
erase cycle correlation which is necessary with alternative flash memory technologies, whose Erase
and Program time increase with accumulated Erase/Program cycles.
The SST49LF016C product provides a maximum program time of 10 µs per byte with a single-byte
Program operation; effectively 5 µs per byte with a dual-byte Program operation and 2.5 µs per byte
with a quad-byte Program operation.
The SST49LF016C is offered in 32-PLCC, 32-TSOP, and 40-TSOP packages. See Figures 3, 4, and 5
for pin assignments and Table 1 for pin descriptions.
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16 Mbit LPC Serial Flash
SST49LF016C
EOL Data Sheet
Functional Blocks
TBL#
WP#
INIT#
X-Decoder
SuperFlash
Memory
LAD[3:0]
LCLK
LFRAME#
LPC
Interface
Address Buffers & Latches
Y-Decoder
ID[3:0]
GPI[4:0]
AAI
Control Logic
I/O Buffers and Data Latches
AAI
Interface
RY/BY#
LD#
RST#
1237 B1.0
Figure 1: Functional Block Diagram
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16 Mbit LPC Serial Flash
SST49LF016C
EOL Data Sheet
Device Memory Map
1FFFFFH
Block 34
11FFFFH
Block 17
Boot Block
1FC000H
1FBFFFH
110000H
10FFFFH
Block 16
Block 33
1FA000H
1F9FFFH
100000H
0FFFFFH
Block 15
Block 32
1F8000H
1F7FFFH
0F0000H
0EFFFFH
Block 14
Block 31
1F0000H
1EFFFFH
0E0000H
0DFFFFH
Block 13
Block 30
1E0000H
1DFFFFH
Block 12
Block 29
1D0000H
1CFFFFH
Block 11
Block 28
Block 27
WP# for
Block 0~33
Block 26
Block 25
Block 24
Block 23
Block 22
Block 21
Block 20
Block 19
Block 18
1C0000H
1BFFFFH
Block 10
1B0000H
1AFFFFH
Block 9
1A0000H
19FFFFH
Block 8
190000H
18FFFFH
WP# for
Block 0~33
180000H
17FFFFH
Block 7
Block 6
170000H
16FFFFH
Block 5
160000H
15FFFFH
Block 4
150000H
14FFFFH
Block 3
140000H
13FFFFH
Block 2
130000H
12FFFFH
Block 1
120000H
Block 0
(64 KByte)
0D0000H
0CFFFFH
0C0000H
0BFFFFH
0B0000H
0AFFFFH
0A0000H
09FFFFH
090000H
08FFFFH
080000H
07FFFFH
070000H
06FFFFH
060000H
05FFFFH
050000H
04FFFFH
040000H
03FFFFH
030000H
02FFFFH
020000H
01FFFFH
010000H
00FFFFH
4 KByte Sector 15
002000H
4 KByte Sector 2
001000H
4 KByte Sector 1
000000H
4 KByte Sector 0
1237 F16.0
TBL#
Figure 2: Device Memory Map for SST49LF016C
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16 Mbit LPC Serial Flash
SST49LF016C
EOL Data Sheet
NC
2
1
GPI4
RST#
3
LCLK
GPI3
4
NC
GPI2
Pin Assignments
NC
6
28
NC
WP#/AAI
7
27
NC
TBL#
8
26
NC
ID3
9
25
VDD
ID2
10
24
INIT#
ID1
11
23
LFRAME#
ID0
12
22
NC
LAD0
13
21
14 15 16 17 18 19 20
NC
NC
NC
LAD3
( ) Designates AAI Mode
VSS
32-lead PLCC
Top View
LAD2
GPI0 (RY/BY#)
LAD1
5
NC
32 31 30
29
GPI1 (LD#)
1237 32-plcc P2.0
Figure 3: Pin Assignments for 32-lead PLCC
NC
NC
NC
NC
NC
GPI4
LCLK
NC
NC
RST#
GPI3
GPI2
GPI1 (LD#)
GPI0 (RY/BY#)
WP#/AAI
TBL#
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32-lead TSOP
Top View
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
INIT#
LFRAME#
VDD
NC
NC
NC
NC
LAD3
VSS
LAD2
LAD1
LAD0
ID0
ID1
ID2
ID3
( ) Designates AAI Mode
1237 32-tsop P1.0
Figure 4: Pin Assignments for 32-lead TSOP
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16 Mbit LPC Serial Flash
SST49LF016C
EOL Data Sheet
NC
NC
NC
NC
NC
NC
GPI4
NC
LCLK
NC
NC
RST#
NC
NC
GPI3
GPI2
GPI1 (LD#)
GPI0 (RY/BY#)
WP#/AAI
TBL#
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40-lead TSOP
Top View
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
NC
VDD
LFRAME#
INIT#
NC
NC
NC
NC
NC
NC
VSS
VSS
LAD3
LAD2
LAD1
LAD0
ID0
ID1
ID2
ID3
( ) Designates AAI Mode
1237 40-tsop P3.0
Figure 5: Pin Assignments for 40-lead TSOP
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16 Mbit LPC Serial Flash
SST49LF016C
EOL Data Sheet
Pin Descriptions
Table 1: Pin Description
Interface
Type1 AAI LPC Functions
I
X
X
To accept a clock input from the control unit
I/O
X
X
To provide LPC bus information, such as addresses and command Inputs/Outputs data.
I
X
X
To indicate the start of a data transfer operation; also used to
abort an LPC cycle in progress.
I
X
X
To reset the operation of the device
I
X
X
This is the second reset pin for in-system use. This pin is internally combined with the RST# pin. If this pin or RST# pin is
driven low, identical operation is exhibited.
ID[3:0]
Identification
I
X
X
These four pins are part of the mechanism that allows multiple
Inputs
parts to be attached to the same bus. The strapping of these
pins is used to identify the component. The boot device must
have ID[3:0]=0000, all subsequent devices should use sequential up-count strapping. These pins are internally pulled-down
with a resistor between 20-100 K. When in AAI mode, these
pins operate identically as in Firmware Memory cycles.
I
X
These individual inputs can be used for additional board flexibility.
GPI[4:0] General
Purpose
The state of these pins can be read through LPC registers. These
Inputs
inputs should be at their desired state before the start of the LPC
clock cycle during which the read is attempted, and should rem ain
in place until the end of the Read cycle. Unused GPI pins must not
be floated. GPI[2:4] are ignored when in AAI mode.
TBL#
Top Block Lock
I
X
When low, prevents programming to the boot block sectors at
top of device memory. When TBL# is high it disables hardware
write protection for the top block sectors. This pin cannot be left
unconnected. TBL# setting is ignored when in AAI mode.
WP#/AAI Write Protect
I
X
When low, prevents programming to all but the highest addressable
block (Boot Block). When WP# is high it disables hardware write
protection for these blocks. This pin cannot be left unconnected.
WP#/AAI AAI Enable
I
X
When set to the Supervoltage VH = 9V, configures the device to
program multiple bytes in AAI mode. When brought to VIL/VIH,
returns device to LPC mode.
RY/BY# Ready/Busy#
O
X
Open drain output that indicates the device is ready to accept
data in an AAI mode, or that the internal cycle is complete.
Used in conjunction with LD# pin to switch between these two
flag states.
LD#
Load-Enable#
I
X
Input pin which when low, indicates the host is loading data in
an AAI programming cycle. If LD# is high, the host signals the
AAI interface that it is terminating a command. LD# low/high
switches the RY/BY# output from a “buffer free” flag to a “programming complete” flag.
Power Supply PWR
X
X
To provide power supply (3.0-3.6V)
VDD
Ground
PWR
X
X
Circuit ground (0V reference)
VSS
NC
No Connection
N/A N/A Unconnected pins.
Symbol Pin Name
LCLK
Clock
LAD[3:0] Address
and Data
LFRAME Frame
#
RST#
Reset
INIT#
Initialize
T1.2 20005029
1. I=Input, O=Output
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16 Mbit LPC Serial Flash
SST49LF016C
EOL Data Sheet
Clock
The LCLK pin accepts a clock input from the host controller.
Input/Output Communications
The LAD[3:0] pins are used to serially communicate cycle information such as cycle type, cycle direction, ID selection, address, data, and sync fields.
Input Communication Frame
The LFRAME# pin is used to indicate start of a LPC bus cycle. The pin is also used to abort an LPC
bus cycle in progress.
Reset
A VIL on INIT# or RST# pin initiates a device reset. INIT# and RST# pins have the same function internally. It is required to drive INIT# or RST# pins low during a system reset to ensure proper CPU initialization. During a Read operation, driving INIT# or RST# pins low deselects the device and places the
output drivers, LAD[3:0], in a high impedance state. The reset signal must be held low for a minimum
of time TRSTP. A reset latency occurs if a reset procedure is performed during a Program or Erase operation. See Table 27, Reset Timing Parameters, for more information. A device reset during an active
Program or Erase operation will abort the operation and memory contents may become invalid due to
data being altered or corrupted from an incomplete Erase or Program operation.
Identification Inputs
These pins are part of a mechanism that allows multiple devices to be attached to the same bus. The
strapping of these pins is used to identify the component. The boot device must have ID[3:0] = 0; all
subsequent devices should use sequential count-up strapping. These pins are internally pulled-down
with a resistor between 20-100 K.
General Purpose Inputs
The General Purpose Inputs (GPI[4:0]) can be used as digital inputs for the CPU to read. The GPI register holds the values on these pins. The data on the GPI pins must be stable before the start of a GPI
register Read and remain stable until the Read cycle is complete. The pins must be driven low, VIL, or
high, VIH but not left unconnected (float).
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16 Mbit LPC Serial Flash
SST49LF016C
EOL Data Sheet
Write Protect / Top Block Lock
The Top Boot Lock (TBL#) and Write Protect (WP#/AAI) pins are provided for hardware write protection of device memory in the SST49LF016C. The TBL# pin is used to write protect 16 KByte at the
highest memory address range for the SST49LF016C. WP#/AAI pin write protects the remaining sectors in the flash memory. An active low signal at the TBL# pin prevents Program and Erase operations
of the top Boot Block. When TBL# pin is held high, write protection of the top Boot Block is then determined by the Boot Block Locking registers. The WP#/AAI pin serves the same function for the remaining sectors of the device memory. The TBL# and WP#/AAI pins write protection functions operate
independently of one another. Both TBL# and WP#/AAI pins must be set to their required protection
states prior to starting a Program or Erase operation. A logic level change occurring at the TBL# or
WP#/AAI pin during a Program or Erase operation could cause unpredictable results. TBL# and WP#/
AAI pins cannot be left unconnected.
TBL# is internally OR’ed with the top Boot Block Locking register. When TBL# is low, the top Boot
Block is hardware write protected regardless of the state of the Write-Lock bit for the Boot Block Locking register. Clearing the Write-Protect bit in the register when TBL# is low will have no functional
effect, even though the register may indicate that the block is no longer locked.
WP#/AAI is internally OR’ed with the Block Locking register. When WP#/AAI is low, the blocks are
hardware write protected regardless of the state of the Write-Lock bit for the corresponding Block
Locking registers. Clearing the Write-Protect bit in any register when WP#/AAI is low will have no functional effect, even though the register may indicate that the block is no longer locked.
AAI Enable
The AAI Enable pin (WP#/AAI) is used to enable the Auto Address Increment (AAI) mode. When the
WP#/AAI pin is set to the Supervoltage VH (9±0.5V), the device is in AAI mode with Multi-Byte programming. When the WP#/AAI pin is brought to VIL/VIH levels, the device returns to LPC mode.
Ready/Busy
The Ready/Busy pin (RY/BY#), is an open drain output which indicates the device is ready to accept
data in an AAI mode, or that the internal programming cycle is complete. The pin is used in conjunction
with the LD# pin to switch between these two flag states (see Table 18).
Load Enable
The Load Enable pin (LD#), is an input pin which when low, indicates the host is loading data in an AAI
programming cycle. Data is loaded in the SST49LF016C at the rising edge of the clock. If LD# is high,
it signals the AAI interface that the host is terminating the command. LD# low/high switches the RY/
BY# output from buffer free flag to programming complete flag (see Table 18).
No Connection (NC)
These pins are not connected internally.
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16 Mbit LPC Serial Flash
SST49LF016C
EOL Data Sheet
Design Considerations
SST recommends a high frequency 0.1 µF ceramic capacitor to be placed as close as possible
between VDD and VSS less than 1 cm away from the VDD pin of the device. Additionally, a low frequency 4.7 µF electrolytic capacitor from VDD to VSS should be placed within 1 cm of the VDD pin. If you
use a socket for programming purposes add an additional 1-10 µF next to each socket. The RST# pin
must remain stable at VIH for the entire duration of an Erase operation. WP#/AAI must remain stable at
VIH for the entire duration of the Erase and Program operations for non-Boot Block sectors. To write
data to the top Boot Block sectors, the TBL# pin must also remain stable at VIH for the entire duration
of the Erase and Program operations.
Mode Selection
The SST49LF016C flash memory device operates in two distinct interface modes: the LPC mode and
the Auto Address Increment (AAI) mode. The WP#/AAI pin is used to set the interface mode selection.
The device is in AAI mode when the WP#/AAI pin is set to the Supervoltage VH (9±0.5V), and in the
LPC mode when the WP#/AAI is set to VIL/VIH. The mode selection must be configured prior to device
operation.
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16 Mbit LPC Serial Flash
SST49LF016C
EOL Data Sheet
LPC Mode
Device Operation
The SST49LF016C supports Multi-Byte Firmware Memory Read and Write cycle types as defined in
Low Pin Count Interface Specification, Revision 1.1. Table 2 shows the size of transfer supported by
the SST49LF016C.
Table 2: Transfer Size Supported
Cycle Type
Size of Transfer
Firmware Memory Read
1, 2, 4, 16, 128 Bytes
Firmware Memory Write
1, 2, 4 Bytes
T2.1 20005029
The LPC mode uses a 5-signal communication interface: one control line, LFRAME#, which is driven
by the host to start or abort a bus cycle, a 4-bit data bus, LAD[3:0], used to communicate cycle type,
cycle direction, ID selection, address, data and sync fields. The device enters standby mode when
LFRAME# is taken high and no internal operation is in progress.
The host drives LFRAME# signal from low-to-high to capture the start field of a LPC cycle. On the
cycle in which LFRAME# goes inactive, the last latched value is taken as the START value. The START
value determines whether the SST49LF016C will respond to a Firmware Memory Read/Write cycle
type as defined in Table 3.
Table 3: Firmware Memory Cycles START Field Definition
START Value
Definition
1101
Start of a Firmware Memory Read cycle
1110
Start of a Firmware Memory Write cycle
T3.1 20005029
See following sections on details of Firmware Memory cycle types (Tables 4 and 5). Two-cycle Program
and Erase command sequences are used to initiate Firmware Memory Program and Erase operations. See
Table 8 for a listing of Program and Erase commands.
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16 Mbit LPC Serial Flash
SST49LF016C
EOL Data Sheet
Firmware Memory Cycles
Firmware Memory Read Cycle
Table 4: Firmware Memory Read Cycle Field Definitions
Field
Contents
LAD[3:0]1
1101
Clock
Cycle
1
Field
Name
START
2
IDSEL
0000 to
1111
3-9
MADD
R
YYYY
10
MSIZE
KKKK
11
TAR0
1111
12
TAR1
1111 (float)
13
RSYN
C
0000
(READY)
14-A
(A+1)
DATA
TAR0
ZZZZ
1111
(A+2)
TAR1
1111 (float)
LAD[3:0]
Direction Comments
IN
LFRAME# must be active (low) for the part to respond. Only the last
start field (before LFRAME# transitions high) will be recognized. The
START field contents (1101b) indicate a Firmware Memory Read
cycle.
IN
Indicates which SST49LF016C device should respond. If the
IDSEL (ID select) field matches the value of ID[3:0], then that particular device will respond to the LPC bus cycle.
IN
These seven clock cycles make up the 28-bit memory address.
YYYY is one nibble of the entire address. Addresses are transferred most-significant nibble first.
IN
The MSIZE field indicates how many bytes will be transferred
during multi-byte operations.
Device will execute multi-byte read of 2MSIZE bytes. SST49LF016C
supports only MSIZE = 0, 1, 2, 4, 7 (1, 2, 4, 16, 128 Bytes), with
KKKK=0000b, 0001b, 0010b, 0100b, or 0111b.
IN,
In this clock cycle, the master has driven the bus to all ‘1’s and then
then Float floats the bus, prior to the next clock cycle. This is the first part of the
bus “turnaround cycle.”
Float,
The SST49LF016C takes control of the bus during this cycle.
then OUT
OUT
During this clock cycle, the device generates a “ready sync”
(RSYNC) indicating that the device has received the input data.
The least-significant nibble of the least-significant byte will be
available during the next clock cycle.
OUT
A=(13+2n+1); n = MSIZE. Least significant nibbles outputs first.
OUT,
In this clock cycle, the SST49LF016C drives the bus to all ones
then Float and then floats the bus prior to the next clock cycle. This is the first
part of the bus “turnaround cycle.” A=(13+2n+1); n = MSIZE
Float,
The host resumes control of the bus during this cycle.
then IN
A=(13+2n+1); n = MSIZE
T4.0 20005029
1. Field contents are valid on the rising edge of the present clock cycle.
LCLK
LFRAME#
Start
LAD[3:0]
IDSEL
MADDR
1101b 0000b A[27:24] A[23:20] A[19:16] A[15:12] A[11:8]
A[7:4]
A[3:0]
MSIZE
TAR0
TAR1
KKKKb
1111b
Tri-State 0000b
DATA
RSYNC
D0[3:0]
D0[7:4]
Dn[3:0]
Dn[7:4]
TAR
1237 F03.0
Figure 6: Firmware Memory Read Cycle Waveform
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16 Mbit LPC Serial Flash
SST49LF016C
EOL Data Sheet
Firmware Memory Write Cycle
Table 5: Firmware Memory Write Cycle
Clock
Cycle
Field
Name
Field
Contents
LAD[3:0]1
LAD[3:0]
Direction
1
START
1110
IN
LFRAME# must be active (low) for the part to respond. Only the
last start field (before LFRAME# transitions high) will be recognized. The START field contents (1110b) indicate a Firmware
Memory Write cycle.
2
IDSEL
0000 to
1111
IN
Indicates which SST49LF016C device should respond. If the
IDSEL (ID select) field matches the value of ID[3:0], then that particular device will respond to the whole bus cycle.
3-9
MADDR
YYYY
IN
These seven clock cycles make up the 28-bit memory address.
YYYY is one nibble of the entire address. Addresses are transferred most-significant nibble first.
10
MSIZE
KKKK
IN
The MSIZE field indicates how many bytes will be transferred
during multi-byte operations.
Device supports 1, 2, and 4 Bytes write with MSIZE = 0, 1, or 2,
and KKKK=0000b, 0001b, or 0010b.
11-A
DATA
ZZZZ
IN
A=(10+2n+1); n = MSIZE
Least significant nibble entered first.
(A+1)
TAR0
1111
IN then
Float
(A+2)
TAR1
1111
(float)
(A+3)
RSYNC
0000
OUT
During this clock cycle, the SST49LF016C generates a “ready
sync” (RSYNC) and outputs the values 0000, indicating that it has
received data or a flash command. A=(10+2n+1); n = MSIZE
(A+4)
TAR0
1111
OUT then
Float
In this clock cycle, the SST49LF016C drives the bus to all ‘1’s and
then floats the bus prior to the next clock cycle. This is the first part
of the bus “turnaround cycle”. A=(10+2n+1); n = MSIZE
(A+5)
TAR1
1111
(float)
Float
then IN
Comments
In this clock cycle, the master has driven the bus to all ‘1’s and
then floats the bus prior to the next clock cycle. This is the first part
of the bus “turnaround cycle.” A=(10+2n+1); n = MSIZE
Float
The SST49LF016C takes control of the bus during this cycle.
then OUT A=(10+2n+1); n = MSIZE
The host resumes control of the bus during this cycle.
A=(10+2n+1); n = MSIZE
T5.0 20005029
1. Field contents are valid on the rising edge of the present clock cycle.
LCLK
LFRAME#
Start
LAD[3:0]
IDSEL
DATA
MSIZE
MADDR
1110b 0000b A[27:24] A[23:20] A[19:16] A[15:12] A[11:8]
A[7:4]
A[3:0]
KKKKb
D0[3:0]
D0[7:4]
Dn[3:0] Dn[7:4]
TAR0
TAR1
1111b
Tri-State 0000b
RSYNC
TAR
1237 F04.0
Figure 7: Firmware Memory Write Cycle Waveform
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16 Mbit LPC Serial Flash
SST49LF016C
EOL Data Sheet
Abort Mechanism
If LFRAME# is driven low for one or more clock cycles after the start of a bus cycle, the cycle will be
terminated. The host may drive the LAD[3:0] with ‘1111b’ (ABORT nibble) to return the interface to
ready mode. The ABORT only affects the current bus cycle. For a multi-cycle command sequence,
such as the Erase or Program commands, ABORT doesn’t interrupt the entire command sequence,
only the current bus cycle of the command sequence. The host can re-send the bus cycle for the
aborted command and continue the command sequence after the device is ready again.
Response to Invalid Fields for Firmware Memory Cycle
During an on-going Firmware Memory bus cycle, the SST49LF016C will not explicitly indicate that it
has received invalid field sequences. The response to specific invalid fields or sequences is described
as follows:
ID mismatch:
If the IDSEL field does not match ID[3:0], the device will ignore the cycle. See “Multiple Device Selection for Firmware Memory Cycle” on page 15 for details.
Address out of range:
The address sequence is 7 fields long (28 bits) with Firmware Memory bus cycles. Only some of the
address fields bits are decoded by the SST49LF016C. These are: A0 through A20 and A22. Address
A22 has the special function of directing reads and writes to the flash core (A22=1) or to the register
space (A22=0).
Invalid MSIZE field:
If the SST49LF016C receives an invalid size field during a Firmware Memory Read or Write operation,
the device will reset and no operation will be attempted. The device will not generate any kind of
response in this situation. The SST49LF016C will only respond to values listed in Table 6.
Table 6: Valid MSIZE field Values for Firmware Memory Cycles
MSIZE
Direction
Size of Transfer
0000
R/W
1 Byte
0001
R/W
2 Byte
0010
R/W
4 Byte
0100
R
16 Byte
0111
R
128 Byte
T6.0 20005029
Once valid START, IDSEL, and MSIZE are received, the SST49LF016C will always complete the bus
cycle. However, if the device is busy performing a flash Erase or Program operation, no new internal
memory Write will be executed. As long as the states of LAD[3:0] and LFRAME# are known, the
response of the ST49LF016C to signals received during the cycle is predictable.
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16 Mbit LPC Serial Flash
SST49LF016C
EOL Data Sheet
Non-boundary-aligned address:
The SST49LF016C accepts multi-byte transfers for both Read and Write operations. The device
address space is divided into uniform page sizes 2, 4, 16, or 128 bytes wide, according to the MSIZE
value (see Table 6). The host issues only one address in the MADDR field of the Firmware Memory
Cycle, but multiple bytes are read from or written to the device. For this reason the MADDR address
should be page boundary-aligned. This means the address should be aligned to a Word boundary (A0
= 0) for a 2-byte transfer, a double Word boundary (e.g. A0 = 0, A1 = 0) for a 4-byte transfer, and so on.
If the address supplied by the host is not page boundary-aligned, the SST49LF016C will force a
boundary alignment, starting the multi-byte Read or Write operation from the lower byte of the
addressed page.
Multiple Device Selection
Multiple LPC serial flash devices may be strapped to increase memory densities in a system. The four
ID pins, ID[3:0], allow up to 16 devices to be attached to the same bus by using different ID strapping in
a system. BIOS support, bus loading, or the attaching bridge may limit this number. The boot device
must have an ID of 0000b (determined by ID[3:0]); subsequent devices use incremental numbering.
Equal density must be used with multiple devices.
Multiple Device Selection for Firmware Memory Cycle
For Firmware Memory Read/Write cycles, hardware strapping values on ID[3:0] must match the values
in IDSEL field. The SST49LF016C will compare these bits with ID[3:0]’s strapping values. If there is a
mismatch, the device will ignore the remainder of the cycle. See Table 7 for Multiple Device Selection
Configuration.
Table 7: Firmware Memory Multiple Device Selection Configuration
Device #
ID[3:0]
IDSEL
0 (Boot device)
0000
0000
1
0001
0001
2
0010
0010
3
0011
0011
4
0100
0100
5
0101
0101
6
0110
0110
7
0111
0111
8
1000
1000
9
1001
1001
10
1010
1010
11
1011
1011
12
1100
1100
13
1101
1101
14
1110
1110
15
1111
1111
T7.0 20005029
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16 Mbit LPC Serial Flash
SST49LF016C
EOL Data Sheet
Device Commands
Device operation is controlled by commands written to the Command User Interface (CUI). Execution
of a specific command is handled by internal functions after a CUI receives and processes the command. After power-up or a Reset operation the device enters Read mode. Commands consist of one
or two sequential Bus-Write operations. The commands are summarized in Table 8, “Software Command Sequence”.
Table 8: Software Command Sequence
Bus Cycles
Required
First Bus Cycle
Oper
Addr1
Data
1
Write
X
FFH
2
Write
X
Read-Status-Register3
2
Write
Clear-Status-Register
1
Sector-Erase7
2
Block-Erase7
Program7,9
Second Bus Cycle
Oper
Addr1
Data
90H
Read
IA4
ID5
X
70H
Read
X
SRD6
Write
X
50H
Write
X
30H
Write
SAx8
D0H
2
Write
X
20H
Write
BAx
D0H
2
Write
X
40H
or
10H
Write
WA10
WD11
Program-/Erase-Suspend
1
Write
X
B0H
Program-/Erase-Resume
1
Write
X
D0H
User-Security-ID-Program12
2
Write
X
A5H
Write
WA10
Data
User-Security-ID-Program-Lockout
2
Write
X
85H
Write
X
Command
Read-Array/Reset
Read-Software-ID2/
Read-Security-ID3
00H
T8.0 20005029
1. This value must be a valid address within the device Memory Address Space. X can be VIH or VIL, but no other value.
2. SST Manufacturer’s ID = BFH, is read with A20-A0 = 0.
SST49LF016C Device ID = 5CH, is read with A20-A1 = 0, A0 = 1.
Following the Read-Software-ID/Read-Security-ID command,
Read operations access Manufacturer’s ID and Device ID or Security ID.
3. Following the Read-Software-ID/Read-Security-ID command, Read operations access manufacturer’s ID and Device ID
or Security ID. Read-Software-ID/Read-Security-ID and Read-Status-Register will return register data until another
valid command is written.
4. IA = Device Identification Address/Security ID Address.
5. ID = Data read from identifier codes/Data read from Security ID
6. SRD = Data read from Status register
7. The sector or block must not be write-locked when attempting Erase or Program operations.
Attempts to issue an Erase or Program command to a write-locked sector/block will fail.
8. SAX for Sector-Erase Address
BAX for Block-Erase Address
9. The Program command operates on multiple bytes.
10. WA = Address of memory location to be written
11. WD = Data to be written at location WA
12. Valid addresses for the User Security ID space are from FFFC 0188H to FFFC 019FH.
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16 Mbit LPC Serial Flash
SST49LF016C
EOL Data Sheet
Read-Array Command
Upon initial device power-up and after exit from reset, the device defaults to the read array mode. This
operation can also be initiated by writing the Read-Array command. (See Table 8.) The device remains
available for array reads until another command is written. Once an internal Program/Erase operation
starts, the device will not recognize the Read-Array command until the operation is completed, unless
the operation is suspended via a Program/Erase Suspend command.
Read-Software-ID Command
The Read-Software-ID operation is initiated by writing the Read-Software-ID command. Following the
command, the device will output the manufacturer’s ID and device ID from the addresses shown in
Table 9. Any other valid command will terminate the Read-Software-ID operation.
The Read-Software-ID command is the same as the Read-Security-ID command. See “Security ID
Commands” on page 19.
Table 9: Product Identification
Manufacturer’s ID
Address1
Data
FFFC 0000H
BFH
FFFC 0001H
5CH
Device ID
SST49LF016C
T9.1 20005029
1. Address shown in this column is for boot device only. Address locations should appear elsewhere in the 4 GByte system memory map depending on ID strapping values on ID[3:0] pins when multiple LPC memory devices are used in a
system.
Read-Status-Register Command
The Status register may be read to determine when a Sector-/Block-Erase or Program completes, and
whether the operation completed successfully. The Status register may be read at any time by writing
the Read-Status-Register command. After writing this command, all subsequent Read operations will
return data from the Status register until another valid command is written.
The default value of the Status register after device power-up or reset is 80H.
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16 Mbit LPC Serial Flash
SST49LF016C
EOL Data Sheet
Clear-Status-Register Command
The user can reset the Status register’s Block Protect Status (BPS) bit to 0 by issuing a Clear-StatusRegister command. Device power-up and hardware reset will also reset BPS to 0.
Table 10: Software Status Register
Bit
Name
Function
0
RES
Reserved for future use
1
BPS
Block Protect Status
The Block Write-Lock bit should be interrogated only after Erase or Program command is issued.
It informs the system whether or not the selected block is locked.
BPS does not provide a continuous indication of Write-Lock bit value.
0: Block Unlocked
1: Operation Aborted, Block Write-Lock bit set.
2:5
RES
Reserved for future use
6
ESS
Erase Suspend Status
0: Erase in progress/completed
1: Erase suspended
7
WSMS
Write State Machine Status
Check WSMS to determine erase or program completion.
0: Busy
1: Ready
T10.0 20005029
Sector-/Block-Erase Command
The Erase Command operates on one sector or block at a time. This command requires an (arbitrary)
address within the sector or block to be erased. Note that a Sector/Block Erase operation changes all
Sector/Block byte data to FFh. If a Read operation is performed after issuing the erase command, the
device will automatically output Status Register data. The system can poll the Status Register in order
to verify the completion of the Sector/Block Erase operation (please refer to Table 10, Status Register
Definition). If a Sector/Block Erase is attempted on a locked block, the operation will fail and the data in
the Sector/Block will not be changed. In this case, the Status Register will report the error (BPS=1).
Program Command
The Program command operates on multiple bytes (Refer to Table 5). This command specifies the
address and data to be programmed. During the Program operation the device automatically outputs
the Status Register data when read. The system can poll the Status Register in order to verify the completion of the Program operation (refer to Table 10, “Software Status Register”). If a Program operation
is attempted on a locked block, the operation will fail and the data in the addressed byte will not be
changed. In this case, the Status Register will report the error (BPS=1).
Program-/Erase-Suspend or Program-/Erase-Resume Operations
The Program-Suspend and Erase-Suspend operations share the same software command sequence
(B0H). The Program-Resume and Erase-Resume operations share the same software command
sequence (D0H). See Table 8, “Software Command Sequence” on page 16.
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16 Mbit LPC Serial Flash
SST49LF016C
EOL Data Sheet
Erase-Suspend/Erase-Resume Commands
The Erase Suspend command allows Sector-Erase or Block-Erase interruption in order to read or program data in another block of memory. Once the Erase-Suspend command is executed, the device will
suspend any on-going Erase operation within time TES (10 µs). The device outputs status register data
when read after the Erase-Suspend command is written. The system is able to determine when the
Erase operation has been completed (WSMS=1) by polling the status register. After an Erase-Suspend, the device will set the status register ESS bit (ESS=1) if the Erase has been successfully suspended (refer to Table 10, “Software Status Register”). The Erase-Resume command resumes the
Erase operation that had been previously suspended.
After a successful Erase-Suspend, a Read-Array command may be written to read data from a Sector/
Block other than the suspended Sector/Block. A Program command sequence may also be issued
during Erase Suspend to program data in memory locations other than the Sector/Block currently in
the Erase-Suspend mode. If a Read-Array command is written to an address within the suspended
Sector/Block this may result in reading invalid data. If a Program command is written to an address
within the suspended Sector/Block the command is acknowledged but rejected. Other valid commands
while erase is suspended include Read-Status-Register, Read-Device-ID, and Erase-Resume.
The Erase-Resume command resumes the Erase process in the suspended sector or block. After the
Erase-Resume command is written, the device will continue the Erase process. Erase cannot resume
until any Program operation initiated during Erase-Suspend has completed. Suspended operations
cannot be nested: the system needs to complete or resume any previously suspended operation
before a new operation can be suspended. See Figure 8 for flowchart.
Program-Suspend/Program-Resume Command
The Program-Suspend and Program-Resume commands have no influence on the device. Since the
device requires a maximum of TBP (10 µs) in order to program a byte (see Table 28), when a ProgramSuspend command is written, the suspended Byte Program operation will always be successfully completed within the suspend latency time (TES = TBP = 10 µs).
Security ID Commands
The SST49LF016C device offers a 256-bit Security ID space. The Security ID space is divided into two
parts. One 64-bit segment is programmed at SST with a unique 64-bit number: this number cannot be
changed by the user. The other segment is 192-bit wide and is left blank: this space is available for
customers and can be programmed as desired.
The User-Security-ID-Program command is shown in Table 8, “Software Command Sequence”. Use
the memory addresses specified in Table 11 for Security ID programming. Once the customer segment
is programmed, it can be locked to prevent any alteration. The User-Security-ID-Program-Lockout
command is shown in Table 8, “Software Command Sequence”.
In order to read the Security ID information, the user can issue a Read Security ID Command (90H) to
the device. At this point the device enters the Read-Software-ID/Read-Security-ID mode. The Security
ID information can be read at the memory addresses in Table 11.
A Read-Array/Reset command (FFH) must then be issued to the device in order to exit the Read-Software-ID/Read-Security-ID mode and return to Read-Array mode.
An alternate method to read the Security ID information is to read the Security ID registers located into
the register space as described in the “Security ID Registers” section.
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16 Mbit LPC Serial Flash
SST49LF016C
EOL Data Sheet
Erase Sector/Block
Write B0H to any valid
device memory address
Erase-Suspend
Command
Write 70H to any valid
device memory address
Read-Status-Register
Command
Read Status Register
No
WSMS = 1
Yes
ESS = 1
Erase Completed
No
Yes
Write the Read-Array
command to read from
another Sector/Block
or
Write the Program
command to program
another Sector/Block
No
Finished?
Yes
Write D0H to any valid
device memory address
Erase-Resume
Command
Erase Resumed
1237 FC_Erase-Sus.1
Figure 8: Erase-Suspend Flow Chart
Table 11: Security ID Addresses
Address Range
Security ID Segment
Size
FFFC 0180 to FFFC 0187
Factory-Programmed
8 bytes – 64 bit
FFFC 0188 to FFFC 019F
User-Programmed
24 bytes – 192 bit
T11.0 20005029
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16 Mbit LPC Serial Flash
SST49LF016C
EOL Data Sheet
Registers
There are five types of registers available on the SST49LF016C, the multi-byte Read/Write configuration registers (for Firmware Memory cycle), General Purpose Inputs registers, Block Locking registers,
Security ID register, and the JEDEC ID registers. These registers appear at their respective address
location in the 4 GByte system memory map. Unused register locations will read as 00H. Any attempt
to read or write any register during an internal Write operation will be ignored.
Read or write access to the register during an internal Program/Erase operation will be completed as
follows:
•
•
Multi-byte Read/Write Configuration registers, General Purpose Inputs register, and Block
Locking registers can be accessed normally
Security ID register and the JEDEC ID registers can not be accessed (reading these registers will return unused register data 00H).
Multi-Byte Read/Write Configuration Registers (Firmware Memory Cycle)
The multi-byte read/write configuration (MBR) registers are four 8-bit read-only registers located at
addresses FFBC0005-FFBC0008 for boot configured device (see Table 13). These registers are
accessible using Firmware Memory Read cycle only. These registers contain information about multibyte read and write access sizes that will be accepted for Firmware Memory multi-byte Read commands. The registers are not available in AAI mode.
In case of multi-byte Firmware Memory register reads, the device will return register data for the
addressed register until the command finishes, or is aborted.
General Purpose Inputs Register
The General Purpose Inputs register (GPI_REG) passes the state of GPI[4:0] pins on the
SST49LF016C. It is recommended that the GPI[4:0] pins be in the desired state before LFRAME# is
brought low for the beginning of the bus cycle, and remain in that state until the end of the cycle. There
is no default value since this is a pass-through register. The GPI_REG register for the boot device
appears at FFBC0100H in the 4 GByte system memory map, and will appear elsewhere if the device is
not the boot device (see Table 12). This register is not available to be read when the device is in an
Erase/Program operation. In case of multi-byte Firmware Memory cycle register reads, the device will
return register data for the addressed register until the command finishes, or is aborted.
Table 12: General Purpose Register
Register
Register Address1
Default
Value
GPI_REG
FFBC 0100H
N/A
Access
R
T12.0 20005029
1. Address shown in this column is for boot device only. Address locations should appear elsewhere in the 4 GByte system
memory map depending on ID strapping values on ID[3:0] pins when multiple LPC memory devices are used in a system.
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16 Mbit LPC Serial Flash
SST49LF016C
EOL Data Sheet
Table 13: Multi-byte Read/Write Configuration Registers (Firmware Memory Cycle Only)
Register
Address1
Data
MULTI_BYTE_READ_L
FFBC 0005H
0100 1011b
R
Device supports 1,2,4, 16, 128 Byte reads
MULTI_BYTE_READ_H
FFBC 0006H
0000 0000b
R
Future Expansion for Read
MULTI_BYTE_WRITE_L
FFBC 0007H
0000 0011b
R
Device supports 1, 2, 4 Byte Write
MULTI_BYTE_WRITE_H
FFBC 0008H
0000 0000b
R
Future Expansion for Write
Register
Access Description
T13.0 20005029
1. Address shown in this column is for boot device only. Address locations should appear elsewhere in the 4 GByte system memory map depending on ID strapping values on ID[3:0] pins when multiple LPC memory devices are used in a
system.
Block Locking Registers
SST49LF016C provides software controlled lock protection through a set of Block Locking registers.
The Block Locking Registers are read/write registers and they are accessible through standard
addressable memory locations specified in Table 14. Unused register locations will return 00H if read.
In case of multi-byte register reads with Firmware Memory cycle, the device will return register data for
the addressed register until the command finishes, or is aborted.
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16 Mbit LPC Serial Flash
SST49LF016C
EOL Data Sheet
Table 14: Block Locking Registers
Register
SST49LF016C Protected Memory
Block Size Address1 Range
Memory Map Register Address1
T_BLOCK_LK
16K
1FFFFFH-1FC000H
FFBFC002H
T_MINUS01_LK
8K
1FBFFFH-1FA000H
FFBFA002H
T_MINUS02_LK
8K
1F9FFFH-1F8000H
FFBF8002H
T_MINUS03_LK
32K
1F7FFFH-1F0000H
FFBF0002H
T_MINUS04_LK
64K
1EFFFFH-1E0000H
FFBE0002H
T_MINUS05_LK
64K
1DFFFFH-1D0000H
FFBD0002H
T_MINUS06_LK
64K
1CFFFFH-1C0000H
FFBC0002H
T_MINUS07_LK
64K
1BFFFFH-1B0000H
FFBB0002H
T_MINUS08_LK
64K
1AFFFFH-1A0000H
FFBA0002H
T_MINUS09_LK
64K
19FFFFH-190000H
FFB90002H
T_MINUS10_LK
64K
18FFFFH-180000H
FFB80002H
T_MINUS11_LK
64K
17FFFFH-170000H
FFB70002H
T_MINUS12_LK
64K
16FFFFH-160000H
FFB60002H
T_MINUS13_LK
64K
15FFFFH-150000H
FFB50002H
T_MINUS14_LK
64K
14FFFFH-140000H
FFB40002H
T_MINUS15_LK
64K
13FFFFH-130000H
FFB30002H
T_MINUS16_LK
64K
12FFFFH-120000H
FFB20002H
T_MINUS17_LK
64K
11FFFFH-110000H
FFB10002H
T_MINUS18_LK
64K
10FFFFH-100000H
FFB00002H
T_MINUS19_LK
64K
0FFFFFH-0F0000H
FFAF0002H
T_MINUS20_LK
64K
0EFFFFH-0E0000H
FFAE0002H
T_MINUS21_LK
64K
0DFFFFH-0D0000H
FFAD0002H
T_MINUS22_LK
64K
0CFFFFH-0C0000H
FFAC0002H
T_MINUS23_LK
64K
0BFFFFH-0B0000H
FFAB0002H
T_MINUS24_LK
64K
0AFFFFH-0A0000H
FFAA0002H
T_MINUS25_LK
64K
09FFFFH-090000H
FFA90002H
T_MINUS26_LK
64K
08FFFFH-080000H
FFA80002H
T_MINUS27_LK
64K
07FFFFH-070000H
FFA70002H
T_MINUS28_LK
64K
06FFFFH-060000H
FFA60002H
T_MINUS29_LK
64K
05FFFFH-050000H
FFA50002H
T_MINUS30_LK
64K
04FFFFH-040000H
FFA40002H
T_MINUS31_LK
64K
03FFFFH-030000H
FFA30002H
T_MINUS32_LK
64K
02FFFFH-020000H
FFA20002H
T_MINUS33_LK
64K
01FFFFH-010000H
FFA10002H
T_MINUS34_LK
64K
00FFFFH-000000H
FFA00002H
T14.0 20005029
1. Address shown in this column is for boot device only. Address locations should appear elsewhere in the 4 GByte system memory map depending on ID strapping values on ID[3:0] pins when multiple LPC memory devices are used in a
system.
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16 Mbit LPC Serial Flash
SST49LF016C
EOL Data Sheet
Table 15: Block Locking Register Bits
Reserved Bit Read-Lock Bit Lock-Down Bit Write-Lock Bit
[7:3]
[2]
[1]
[0]
Lock Status
00000
0
0
0
Full Access
00000
0
0
1
Write Locked (Default State at Power-Up)
00000
0
1
0
Locked Open (Full Access Locked Down)
00000
0
1
1
Write Locked Down
00000
1
0
0
Block Read Locked (Registers alterable)
00000
1
0
1
Block Read & Write Lock (Registers alterable)
00000
1
1
0
Block Read Locked Down (Registers not
alterable)
00000
1
1
1
Block Read & Write lock Down (Registers
not alterable)
T15.0 20005029
Write-Lock Bit
The Write-Lock bit, bit 0, controls the lock state described in Table 15. The default Write status of all
blocks after power up is write locked. When bit 0 of the Block Locking register is set, Program and
Erase operations for the corresponding block are prevented. Clearing the Write-Lock bit will unprotect
the block. The Write-Lock bit must be cleared prior to starting a Program or Erase operation since it is
sampled at the beginning of the operation. The Write-Lock bit functions in conjunction with the hardware Write Lock pin TBL# for the top Boot Block. When TBL# is low, it overrides the software locking
scheme. The top Boot Block Locking register does not indicate the state of the TBL# pin. The WriteLock bit functions in conjunction with the hardware WP#/AAI pin for the remaining blocks (Blocks 0 to
33 for 49LF016C). When WP#/AAI is low, it overrides the software locking scheme. The Block Locking
register does not indicate the state of the WP#/AAI pin.
Lock-Down Bit
The Lock-Down bit, bit 1, controls the Block Locking register as described in Table 15. When in LPC
interface mode, the default Lock Down status of all blocks upon power-up is not locked down. Once the
Lock-Down bit is set, any future attempted changes to that Block Locking register will be ignored. The
Lock-Down bit is only cleared upon a device reset with RST# or INIT# or power down. Current Lock
Down status of a particular block can be determined by reading the corresponding Lock-Down bit.
Once a block’s Lock-Down bit is set, the Read-Lock and Write-Lock bits for that block can no longer be
modified: the block is locked down in its current state of read/write accessibility.
Read-Lock Bit
The default read status of all blocks upon power-up is read-unlocked. When a block’s read lock bit is
set, data cannot be read from that block. An attempted read from a read-locked block will result in the
data 00h. The read lock status can be unlocked by clearing the read lock bit: this can only be done provided that the block is not locked down. The current read lock status of a particular block can be determined by reading the corresponding read-lock bit.
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16 Mbit LPC Serial Flash
SST49LF016C
EOL Data Sheet
Security ID Registers
The SST49LF016C device offers a 256-bit Security ID register space. The Security ID space is divided
into two segments - one (64-bits) factory programmed segment and one (192 bits) user programmed
segment. The first segment is programmed and locked at SST with a unique 64-bit number. The user
segment (192 bits) is left blank (FFH) for the customer to be programmed as desired. Refer to Table 8,
“Software Command Sequence” for more details.
The Security ID Information and its Write Lock/Unlock status can be Read in the Register Access
Space for Execute-In-Place type of applications. (See Table 16.)
The Write Lock-out status of the Security ID space can be read from the SEC_ID_WRITE_LOCK register (see Table 16). The SEC_ID_WRITE_LOCK register is a read-only register that is accessible at
the address location specified in Table 16.
In case of multi-byte register reads with Firmware Memory cycle, for SEC_ID_WRITE_LOCK register,
the device will return register data for the addressed register until the command finishes, or is aborted.
In the case of multi-byte register reads with Firmware Memory cycle, for all the SEC_ID_BYTE registers, the device will return page-aligned sequential register data with wrap-around until the command
finishes, or is aborted.
Table 16: Security ID Registers
Register
Register
Address1
SEC_ID__WRITE_LOCK
FFBC0102H
SEC_ID_BYTE_0
SEC_ID_BYTE_1
Value
0000 0000b
0000 0001b
Access
Description
R
Write Unlocked
Write Locked
FFBC0180H
R
Factory Programmed
FFBC0181H
R
Factory Programmed
SEC_ID_BYTE_2
FFBC0182H
R
Factory Programmed
SEC_ID_BYTE_3
FFBC0183H
R
Factory Programmed
…
…
…
…
SEC_ID_BYTE_7
FFBC0187H
R
Factory Programmed
SEC_ID_BYTE_8
FFBC0188H
R
User Programmed
SEC_ID_BYTE_9
FFBC0189H
R
User Programmed
…
…
…
…
SEC_ID_BYTE_30
FFBC019EH
R
User Programmed
SEC_ID_BYTE_31
FFBC019FH
R
User Programmed
T16.0 20005029
1. Address shown in this column is for boot device only. Address locations should appear elsewhere in the 4 GByte system memory map depending on ID strapping values on ID[3:0] pins when multiple LPC memory devices are used in a
system.
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16 Mbit LPC Serial Flash
SST49LF016C
EOL Data Sheet
JEDEC ID Registers
The JEDEC ID registers for the boot device appear at FFBC0000H and FFBC0001H in the 4 GByte
system memory map, and will appear elsewhere if the device is not the boot device. This register is not
available to be read when the device is in Erase/Program operation. Unused register location will read
as 00H. See Table 17 for the JEDEC device ID code. In case of multi-byte register reads with Firmware
Memory cycle, the device will return register data for the addressed register until the command finishes, or is aborted.
Table 17: JEDEC ID Registers
Register
Register Address1
Default
Value
MANUF_REG
FFBC 0000H
BFH
DEV_REG
FFBC 0001H
5CH
Access
R
R
T17.0 20005029
1. Address shown in this column is for boot device only. Address locations should appear elsewhere in the 4 GByte system
memory map depending on ID strapping values on ID[3:0] pins when multiple LPC memory devices are used in a system.
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16 Mbit LPC Serial Flash
SST49LF016C
EOL Data Sheet
Auto-Address Increment (AAI) MODE
AAI Mode with Multi-byte Programming
AAI mode with multi-byte programming is provided for high-speed production programming. AutoAddress Increment mode requires only one address load for each 128-byte page of data.
Taking the WP#/AAI pin to the Supervoltage VH enables the AAI mode. The AAI command is started as
a normal Firmware Memory cycle. LD# should be low (VIL) as long as data is being loaded into the
device. In the MADDR field, the host may input any address within the 128-byte page to be programmed. The least significant seven bits of the address field will be ignored and the device will begin
programming at the beginning of the 128-byte page (i.e., the address will be page-aligned). The device
Ready/Busy status is output on the RY/BY# pin.
Data is accepted until the internal buffer is full. At that point RY/BY# goes low (busy) to indicate that the
internal buffer is full and cannot accept any more data. When the device is ready, RY/BY# pin goes
high and indicates to the host that more data (the next group of bytes) can be accepted by the internal
data buffer (see Table 18 and Figure 9).
After loading the final byte(s) of the 128-byte page, the RY/BY# signal remains low until the completion
of internal programming. After the completion of programming, the part will go into idle mode and the
RY/BY# will go high indicating that the AAI command has been completed (see Table 18). A subsequent AAI command may be initiated to begin programming the next 128-byte page.
Data will be accepted by the device as long as LD# is low and RY/BY# is high (until the last byte of the
128-byte page has been entered). For partial data-loads (i.e., less than 128 Bytes), LD# may be taken
high (VIH) to end the data loading. If LD# goes high before the full 128-byte page has been entered, the
device will program the data which has been entered to that point, and then terminate the AAI page
programming command. Any incompletely loaded data byte (nibble) will not be programmed. The
device will signify completion of the command by driving RYBY# high. Once RY/BY# goes high, LD#
can be taken low to begin a new AAI programming operation at a different address location.
The RY/BY# pin will stay low while internal programming completes. When the entire 128-byte page
has been programmed, the device will return to the idle mode and the RY/BY# pin will go high (VIH) to
indicate the AAI command has been completed.
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16 Mbit LPC Serial Flash
SST49LF016C
EOL Data Sheet
Table 18: LD# Input and RY/BY# Status in AAI Mode
LD#
state
RY/BY#
status
RY/BY#
Flag indication
L
H
Device is Ready, can accept more data until the last (128th) byte.
L
L
Device is Busy, cannot accept more data
L
H
Device is Ready for next operation if
previous data is the last (128th) byte.
H
H
Device is Ready for next operation
H
L
Device is Busy programming
T18.1 20005029
The user may terminate AAI programming by dropping the WP#/AAI pin to TTL levels (VIH/VIL) as long
as LD# is high and RY/BY# returns to high indicating the completion of the AAI cycle. Software blocklocking will be disabled in AAI mode (all blocks will be write-unlocked). If AAI drops below the Supervoltage VH before RY/BY# returns to high (and LD# high), the contents of the page may be indeterminate.
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SST49LF016C
EOL Data Sheet
AAI Data Load Protocol
Table 19: AAI Programming Cycle (initiated with WP#/AAI at VH ONLY)
Clock
Cycle
Field Name Field Contents LAD[3:0]
Comments
1
START
1110
IN
LFRAME# must be active (low) for the part to respond.
Only the last start field (before LFRAME# transitions
high) should be recognized. The START field contents
indicate a Firmware Memory Write cycle. (1110b)
2
IDSEL
0000b to 1111b IN
ID works identically to Firmware Memory cycle.
This field indicates which SST49LF016C device
should respond. If the IDSEL (ID select) field matches
the value of ID[3:0], then that particular device will
respond to the whole bus cycle.
3-9
MADDR
YYYY
IN
These seven clock cycles make up the 28-bit memory
address. YYYY is one nibble of the entire address.
Addresses are transferred most-significant nibble first.
Only bits [20:7] of the total address [27:0] are used for
AAI mode. The rest are “don’t care”.
10
MSIZE
KKKK
IN
MSIZE field is don’t care when in AAI mode
11-266
DATA
ZZZZ
IN
Data is transmitted to the device least significant nibble first, from byte 0 to byte 127 as long as the RY/BY#
is high and LD# low. The host will pause the clock and
data stream when RY/BY# goes low until it returns
high, signifying that the chip is ready for more data
T19.0 20005029
VH
WP#/AAI
LCLK
(Data Strobe Input)
1 2 3 4 5 6 7 8 9 10 11 12
264
266
LFRAME#
Start
MADDR
DATA
DATA
DATA
DATA
MSIZE
Byte 0
Byte N
Byte
N+1
Byte
2N
DATA DATA
Address
LAD[3:0]
IDSEL
Byte
126
Byte
127
LD#
RY/BY#
1237 F08.1
Figure 9: AAI Load Protocol Waveform
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16 Mbit LPC Serial Flash
SST49LF016C
EOL Data Sheet
Electrical Specifications
The AC and DC specifications for the LPC interface signals (LAD[3:0], LFRAME#, LCLCK and RST#) as
defined in Section 4.2.2.4 of the PCI local Bus specification, Rev. 2.1. Refer to Table 22 for the DC voltage and
current specifications. Refer to Table 26 through Table 28 for the AC timing specifications for Clock, Read, Write,
and Reset operations.
Absolute Maximum Stress Ratings (Applied conditions greater than those listed under “Absolute
Maximum Stress Ratings” may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these conditions or conditions greater than those defined in the
operational sections of this data sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.)
Temperature Under Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55°C to +125°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to +150°C
D.C. Voltage on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to VDD+0.5V
Transient Voltage ( VOUT > 0.1VDD
0.18VDD > VOUT > 0
38 VDD
mA
VOUT = 0.18VDD
-17.1(VDD-VOUT)
Equation
(Test Point)
IOL(AC)
Switching Current
Low
16 VDD
26.7 VOUT
(Test Point)
Conditions
mA
-12 VDD
C1
0.7VDD < VOUT < VDD
ICL
Low Clamp Current
-25+(VIN+1)/0.015
mA
-3 < VIN -1
ICH
High Clamp Current
25+(VIN-VDD-1)/
0.015
mA
VDD+4 > VIN VDD+1
slewr2
Output Rise Slew
Rate
1
4
V/ns
0.2VDD-0.6VDD load
slewf2
Output Fall Slew
Rate
1
4
V/ns
0.6VDD-0.2VDD load
T29.0 20005029
1. See PCI spec.
2. PCI specification output load is used.
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16 Mbit LPC Serial Flash
SST49LF016C
EOL Data Sheet
VTH
VTEST
LCLK
VTL
TVAL
LAD [3:0]
(Valid Output Data)
LAD [3:0]
(Float Output Data)
TON
TOFF
1237 F11.0
Figure 12:Output Timing parameters (LPC Mode)
VTH
LCLK
VTEST
VTL
TSU
TDH
LAD [3:0]
(Valid Input Data)
Inputs
Valid
VMAX
1237 F12.0
Figure 13:Input Timing Parameters (LPC Mode)
Table 30: Interface Measurement Condition Parameters (LPC Mode)
Symbol
Value
Units
1
0.6 VDD
V
VTL1
0.2 VDD
V
VTEST
0.4 VDD
V
VMAX1
0.4 VDD
V
1
V/ns
VTH
Input Signal Edge Rate
T30.0 20005029
1. The input test environment is done with 0.1 VDD of overdrive over VIH and VIL. Timing parameters must be met with no
more overdrive than this. VMAX specifies the maximum peak-to-peak waveform allowed for measuring input timing. Production testing may use different voltage values, but must correlate results back to these parameters.
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16 Mbit LPC Serial Flash
SST49LF016C
EOL Data Sheet
VH
WP#/AAI
TACYC
VTH
VTEST
LCLK
VTL
TASU
TADH
LAD [3:0]
(Valid Input Data)
VMAX
Inputs Valid
TLDSU
TLDDH
LD#
TRB
RY/BY#
1237 F13.3
Figure 14:Input Timing Parameters (AAI Mode)
Table 31: Input Cycle Timing Parameters, VDD=3.0-3.6V (AAI Mode)
Symbol
Parameter
Min
Max
Units
TACYC
Clock Cycle Time
135
ns
TASU
Data Set Up Time to Clock Rising
25
ns
TADH
Clock Rising to Data Hold Time
25
ns
TRB
RY/BY# LD# Falling
25
ns
TLDSU
LD# Set Up Time
25
ns
TLDDH
LD# Hold Time
25
ns
T31.3 20005029
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16 Mbit LPC Serial Flash
SST49LF016C
EOL Data Sheet
VIHT
INPUT
VIT
REFERENCE POINTS
VOT
OUTPUT
VILT
1237 F14.0
AC test inputs are driven at VIHT (0.9 VDD) for a logic “1” and VILT (0.1 VDD) for a logic “0”. Measurement reference points for inputs and outputs are VIT (0.5 VDD) and VOT (0.5 VDD). Input rise
and fall times (10% 90%) are