SY100EL14V
5V/3.3V 1:5 Clock Distribution
General Description
Features
The SY100EL14V is a low-skew, 1:5 clock distribution chip
designed explicitly for low-skew clock distribution
applications. The device can be driven by either a
differential or single-ended ECL or, if positive power
supplies are used, PECL input signal. The EL14V is
suitable for operation in systems operating with 3.3V to
5.0V supplies. If a single-ended input is to be used, the
VBB output should be connected to the /CLK input and
bypassed to ground via a 0.01µF capacitor. The VBB output
is designed to act as the switching reference for the input
of the EL14V under single-ended input conditions. As a
result, this pin can only source/sink up to 0.5mA of current.
•
•
•
•
•
•
•
•
The EL14V features a multiplexed clock input to allow for
the distribution of a lower speed scan or test clock along
with the high speed system clock. When LOW (or left open
and pulled LOW by the input pull-down resistor), the SEL
pin will select the differential clock input.
3.3V and 5V power supply options
70fsRMS typical additive phase jitter
Typical 30ps output-to-output skew
Max. 50ps output-to-output skew
Synchronous enable/disable
Multiplexed clock input
75kΩ internal input pull-down resistors
Available in 20-pin SOIC package
Applications
•
•
•
•
Processor clock distribution
SONET clock distribution
Fibre Channel clock distribution
Gigabit Ethernet clock distribution
The common enable (/EN) is synchronous, so that the
outputs will only be enabled/disable when they are already
in the LOW state. This avoids any chance of generating a
runt clock pulse when the device is enabled/disabled as
can happen with an asynchronous control. The internal
flip-flop is clocked on the falling edge of the input clock.
Therefore, all associated specification limits are referenced
to the negative edge of the clock input.
When both differential inputs are left open, CLK input will
pull down to VEE and /CLK input will bias around VCC/2.
Datasheets and support documentation are available on
Micrel’s web site at: www.micrel.com.
Block Diagram
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (408) 944-0800 • fax + 1 (408) 474-1000 • http://www.micrel.com
October 16, 2014
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SY100EL14V
Ordering Information(1)
Part Number
Package Type
Operating Range
Package Marking
Lead Finish
Z20-1
Industrial
SY100EL14VZG with
Pb-Free bar-line indicator
Pb-Free
NiPdAu
Z20-1
Industrial
SY100EL14VZG with
Pb-Free bar-line indicator
Pb-Free
NiPdAu
SY100EL14VZG
(2)
SY100EL14VZG TR
Note:
1. Contact factory for die availability. Dice are guaranteed at TA = 25°C, DC electricals only.
2. Tape and Reel.
Pin Configuration
20-Pin Narrow SOIC
(Top View)
Pin Description
Pin
Function
CLK
Truth Table
CLK
SCLK
SEL
/EN
Q
Differential clock inputs
L
X
L
L
L
SCLK
Scan clock input
H
X
L
L
H
/EN
Synchronous enable
X
L
H
L
L
SEL
Clock select input
X
H
H
L
H
VBB
Reference output
X
X
X
H
Q0 – Q4
Differential clock outputs
L
(3)
Note:
3. On next negative transition of CLK or SCLK
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SY100EL14V
Absolute Maximum Ratings(4)
Operating Ratings(5)
(6)
Input Voltage (VIN)
(VCC = 0V, VIN not more positive than VCC) .. –6V to +0V
(VEE = 0V, VIN not more positive than VCC)... +0V to +6V
(7)
Operating Range (VEE) .............................. –5.7V to –3.0V
Output Current (IOUT) Continuous ................................ 50mA
Surge....................................... 100mA
Lead Temperature (soldering, 20s) ............................ 260°C
Storage Temperature (Ts) ............................. –65 to +150°C
(8)
ESD Rating ............................................................. >1.5kV
Supply Voltage (VCC) PECL Operation ............ 3.0V to 5.5V
(VEE) ECL Operation ........... –3.0V to –5.5V
Ambient Temperature (TA) .......................... –40°C to +85°C
Junction Thermal Resistance
SOIC (θJA) .......................................................... 58°C/W
DC Electrical Characteristics(9)
VEE = VEE (min) to VEE (max); VCC = GND, TA = –40°C to +85°C, unless otherwise stated.
Outputs are terminated through a 50Ω resistor to VCC–2.0V.
Symbol
Parameter
VOH
Output High Voltage
VOL
Output Low Voltage
(10)
(10)
(10)
VOHA
Output High Voltage
VOLA
Output Low Voltage
VIH
Input High Voltage
VIL
Input Low Voltage
IIL
Input Low Current
IIH
Input High Current
IEE
Power Supply Current
VBB
Output Reference Voltage
(10)
(11)
Condition
Min.
Typ.
Max.
Units
TA = –40°C
VCC – 1.085
VCC – 1.005
VCC – 0.880
V
TA = 0°C to +85°C
VCC – 1.025
VCC – 0.955
VCC – 0.880
V
TA = –40°C
VCC – 1.830
VCC – 1.695
VCC – 1.555
V
TA = 0°C to +85°C
VCC – 1.810
VCC – 1.705
VCC – 1.620
TA = –40°C
VCC – 1.095
V
TA = 0°C to +85°C
VCC – 1.035
V
V
TA = –40°C
VCC – 1.555
V
TA = 0°C to +85°C
VCC – 1.610
V
VCC – 1.165
VCC – 0.880
V
VCC – 1.810
VCC – 1.475
V
Input LOW Current
/CLK
0.5
–300
µA
150
TA = –40°C to +25°C
32
40
TA = +85°C
34
42
VCC – 1.380
VCC – 1.260
µA
mA
V
Notes:
4. Exceeding the absolute maximum ratings may damage the device.
5. The device is not guaranteed to function outside its operating ratings.
6. In PECL mode operation, VIN(max) = VCC.
7. Parametric values specified at 100EL14V series: –3.0V to –5.5V.
8. Devices are ESD sensitive. Handling precautions are recommended. Human body model, 1.5kΩ in series with 100pF.
9. Specification for packaged product only
10. VIN = VIH(max) or VIL(min).
11. VIN = VIL(max).
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SY100EL14V
AC Electrical Characteristics
VEE = VEE (min) to VEE (max); VCC = GND, TA = –40°C to +85°C, unless otherwise stated.
Symbol
Parameter
Max.
Units
520
720
ps
TA = 0°C
550
750
ps
TA = +25°C
580
780
ps
TA = +85°C
630
830
ps
TA = –40°C
470
770
ps
TA = 0°C
500
800
ps
TA = +25°C
530
830
ps
TA = +85°C
580
880
ps
TA = –40°C
470
770
ps
TA = 0°C
500
800
ps
TA = +25°C
530
830
ps
TA = +85°C
580
880
ps
Part-to-Part Skew
200
ps
Within-Device Skew
50
ps
Propagation Delay
CLK to Q (Diff)
tPLH
tPHL
Propagation Delay
CLK to Q (SE)
Propagation Delay
SCLK to Q
Condition
Min.
TA = –40°C
Typ.
680
680
680
(12)
tskew
tS
Setup Time /EN
150
ps
tH
Hold Time /EN
200
ps
VPP
Minimum Input Swing, CLK
150
mV
VPP < 500mV
VCMR
(13)
Common Mode Range
VPP ≥ 500mV
tr/tf
tJITTER
Output Rise/Fall Time
Q (20% - 80%)
Additive Jitter
TA = –40°C
VCC – 2.000
VCC – 0.400
TA = 0°C to +85°C
VCC – 2.100
VCC – 0.400
TA = –40°C
VCC – 1.800
VCC – 0.400
TA = 0°C to +85°C
VCC – 1.900
VCC – 0.400
TA = –40°C to +85°C
Typical value at TA = +25°C
230
360
Carrier = 622MHz
Integration Range: 12kHz to 20MHz
70
Carrier = 156.25MHz
Integration Range: 12kHz to 20MHz
155
500
V
V
ps
fsRMS
Notes:
12. Skews are specified for identical LOW-to-HIGH or HIGH-to-LOW transitions.
13. The VCMR range is referenced to the most positive side of the differential input signal. Normal operation is obtained if the HIGH level falls within the
specified range and the peak-to-peak voltage lies between VPP(min) and 1V. The lower end of the VCMR range varies 1:1 with VEE. The numbers in
the specification table assume a nominal VEE of 3.3V. For PECL operation, the VCMR(min) will be fixed at 3.3V – |VCMR(min)|.
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SY100EL14V
Additive Phase Noise
VCC = +5V, TA = 25°.
October 16, 2014
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SY100EL14V
Package Information(14)
20-Pin Narrow SOIC (Z20-1)
Note:
14. Package information is correct as of the publication date. For updates and most current information, go to www.micrel.com.
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SY100EL14V
MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA
TEL +1 (408) 944-0800 FAX +1 (408) 474-1000 WEB http://www.micrel.com
Micrel, Inc. is a leading global manufacturer of IC solutions for the worldwide high performance linear and power, LAN, and timing & communications
markets. The Company’s products include advanced mixed-signal, analog & power semiconductors; high-performance communication, clock
management, MEMs-based clock oscillators & crystal-less clock generators, Ethernet switches, and physical layer transceiver ICs. Company
customers include leading manufacturers of enterprise, consumer, industrial, mobile, telecommunications, automotive, and computer products.
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information is not intended as a warranty and Micrel does not assume responsibility for its use. Micrel reserves the right to change circuitry,
specifications and descriptions at any time without notice. No license, whether express, implied, arising by estoppel or otherwise, to any intellectual
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