ECL Pro®
SY100EP196V
ECL Pro®
3.3V/5V 2.5GHz PROGRAMMABLE
DELAY CHIP WITH
FINE TUNE CONTROL
Micrel
SY100EP196V
FEATURES
■ Pin-for-pin, plug-in compatible to the ON
Semiconductor MC100EP196
■ Maximum frequency > 2.5GHz
■ Programmable range: 2.2ns to 12.2ns
■ 10ps increments
■ 30ps fine tuning range
■ PECL mode operating range: VCC = 3.0V to 5.5V
with VEE = 0V
■ NECL mode operating range: VCC = 0V
with VEE = –3.0V to –5.5V
■ Open input default state
■ Safety clamp on inputs
■ A logic high on the /EN pin will force Q to logic low
■ D[0:10] can accept either ECL, CMOS, or TTL inputs
■ VBB output reference voltage
■ Available in a 32-pin TQFP package
ECL Pro®
DESCRIPTION
The SY100EP196V is a programmable delay line, varying
the time a logic signal takes to traverse from IN to Q. This
delay can vary from about 2.2ns to about 12.2ns. The input
can be PECL, LVPECL, NECL, or LVNECL.
The delay varies in discrete steps based on a control
word presented to SY100EP196V. The 10-bit width of this
latched control register allows for delay increments of
approximately 10ps. In addition, delay may be varied
continuously in about a 30ps range by setting the voltage at
the FTUNE pin.
An eleventh control bit allows the cascading of multiple
SY100EP196V devices, for a wider delay range. Each
additional SY100EP196V effectively doubles the delay range
available.
For maximum flexibility, the control register interface
accepts CMOS or TTL level signals, as well as the input
level at the IN± pins.
All support documentation can be found on Micrel’s web
site at www.micrel.com.
CROSS REFERENCE TABLE
APPLICATIONS
■ Clock de-skewing
■ Timing adjustment
■ Aperture centering
Micrel Semiconductor
ON Semiconductor
SY100EP196VTI
MC100EP196FA
SY100EP196VTITR
MC100EP196FAR2
TYPICAL PERFORMANCE
TYPICAL APPLICATIONS CIRCUIT
Delay vs. Tap
12000
D
SY100EP196V
CLOCK+
IN
CLOCK–
/IN
Fine Tune Voltage
Q
Q+
Flip-Flop
CK
10000
Q–
DELAY (ps)
Data Signal
of Unknown Phase
FTUNE /Q
D[9:0]
8000
6000
4000
2000
CONTROL
LOGIC
0
0
200 400 600 800 1000 1200
TAP (DIGITAL WORD)
ECL Pro is a registered trademark of Micrel, Inc.
M0644-012704
Rev.: B
1
Amendment: /0
Issue Date: January 2004
ECL Pro®
SY100EP196V
Micrel
D7
D6
D5
D4
VEE
D3
D2
D1
PACKAGE/ORDERING INFORMATION
Ordering Information
Package
Type
Operating
Range
Package
Marking
SY100EP196VTI
T32-1
Industrial
SY100EP196V
SY100EP196VTITR(1)
T32-1
Industrial
SY100EP196V
32 31 30 29 28 27 26 25
D8
D9
D10
IN
/IN
VBB
VEF
VCF
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
Part Number
VEE
D0
VCC
Q
/Q
VCC
VCC
FTUNE
Note:
1. Tape and Reel.
VEE
LEN
SETMIN
SETMAX
VCC
/CASCADE
CASCADE
/EN
9 10 11 12 13 14 15 16
32-Pin TQFP (T32-1)
FUNCTIONAL BLOCK DIAGRAM
IN
0
0
0
0
/IN
1
1
1
1
/EN
0
1
512
256
128
64
32
GD
GD
GD
GD
GD
0
0
0
0
1
1
1
1
0
1
16
8
4
2
1
GD
GD
GD
GD
GD
FTUNE
D[9:0]
LEN
SETMIN
10-bit
Latch
SETMAX
0
Q
1
/Q
1
GD
D[10]
CASCADE
Latch
/CASCADE
VBB
VCF
VEF
M0644-012704
2
ECL Pro®
SY100EP196V
Micrel
PIN DESCRIPTION
Pin Number
Pin Name
23, 25, 26, 27, 29,
30, 31, 32, 1, 2
D[0:9]
Pin Function
CMOS, ECL, or TTL Select Inputs: These digital control signals adjust the amount of
delay from IN to Q. Please refer to the “AC Electrical Table” (page 3) and Table 7 (page
17) for delay values. Figure 9 shows how to interface these inputs to various logic family
standards. These inputs default to logic low when left unconnected. Bit 0 is the least
significant bit, and bit 9 is the most significant bit.
3
D[10]
CMOS, ECL, or TTL Select Input: This input latches just like D[0:9] does. It drives the
CASCADE, /CASCADE differential pair. Use only when cascading two or more
SY100EP196V to extend the range of delays required.
4, 5
IN, /IN
ECL Input: This is the signal to be delayed. If this input pair is left unconnected, this is
equivalent to a logic low input.
6
VBB
Voltage Output Reference: When using a single-ended logic source for IN and /IN,
connect the unused input of the differential pair to this pin. This pin can also re-bias ACcoupled inputs to IN and /IN. When used, de-couple this pin to VCC through an 0.01µF
capacitor. Limit current sinking or sourcing to 0.5mA or less.
7
VEF
Voltage Output: Connect this pin to VCF when the D inputs are ECL. Refer to the “Digital
Control Logic Standard” section of the “Functional Description” to interface the D inputs to
CMOS or TTL.
8
VCF
Voltage Input: The voltage at this pin sets the logic transition threshold for the D inputs.
9, 24, 28
VEE
Most Negative Supply. Supply ground for PECL systems.
10
LEN
ECL Control Input: When logic low, the D inputs flow through. Any changes to the D inputs
reflect in the delay between IN, /IN and Q, /Q. When logic high, the logic values at D are
latched, and these latched bits determine the delay.
11
SETMIN
ECL Control Input: When logic high, the contents of the D register are reset. This sets the
delay to the minimum possible, equivalent to D[0:9] being set to 0000000000. When logic
low, the value of the D register, or the logic value of SETMAX determines the delay from
IN, /IN to Q, /Q. This input defaults to logic low when left unconnected.
12
SETMAX
ECL Control Input: When logic high and SETMIN is logic low, the contents of the D
register are set high, and the delay is set to one step greater than the maximum possible
with D[0:9] set to 1111111111. When logic low, the value of the D register, or the logic
value of SETMIN determines the delay from IN, /IN to Q, /Q. This input defaults to logic
low when left unconnected.
13, 18, 19, 22
VCC
Most Positive Supply: Supply ground for NECL systems. Bypass to VEE with 0.1µF and
0.01µF low ESR capacitors.
14, 15
CASCADE,
100k ECL Outputs: These outputs are used when cascading two or more SY100EP196V
to /CASCADE extend the delay range required. Refer to Table 7 (page 17) for delay
values.
16
/EN
ECL Control Input: When set active low, Q, /Q are a delayed version of IN, /IN. When set
inactive high, IN, /IN are gated such that Q, /Q become a differential logic low. This input
defaults to logic low when left unconnected.
17
FTUNE
Voltage Control Input: By varying the voltage at this pin from VCC through VEE, the delay
may be fine tuned by approximately ±15ps.
20, 21
Q, /Q
M0644-012704
100k ECL Outputs: This signal pair is the delayed version of IN, /IN.
3
ECL Pro®
SY100EP196V
Micrel
Absolute Maximum Ratings(1)
Operating Ratings(2)
Supply Voltage (VCC)
PECL Mode (VEE=0V) ............................. –0.5V to +6.0V
Supply Voltage (VEE)
NECL Mode (VCC=0V) ............................ +0.5V to –6.0V
Any Input Voltage (VIN)
PECL Mode ....................................... –0.5V to VCC+0.5V
NECL Mode ....................................... +0.5V to VEE–0.5V
ECL Output Current (IOUT)
Continuous ............................................................. 50mA
Surge .................................................................... 100mA
IBB Sink/Source Current .......................................... ±0.5mA
Lead Temperature (soldering, 10 sec.) ................... +300°C
Storage Temperature (TS) ....................... –65°C to +150°C
ESD Rating(3) ........................................................... >1.5kV
Supply Voltage (VCC)
PECL Mode (VEE=0V) ............................. +3.0V to +5.5V
Supply Voltage (VEE)
NECL Mode (VCC=0V) ............................ –3.0V to –5.5V
Ambient Temperature (TA) ......................... –40°C to +85°C
Package Thermal Resistance
TQFP-32 (θJA)
Still-air ............................................................. 50°C/W
500lfpm ............................................................ 42°C/W
TQFP-32 (θJC) ..................................................... 20°C/W
DC ELECTRICAL CHARACTERISTICS
TA = –40°C to +85°C
Symbol
Parameter
VCC
Condition
Min
Typ
Max
Units
Power Supply Voltage (PECL)
3.0
4.5
3.3
5.0
3.6
5.5
V
V
VEE
Power Supply Voltage (NECL)
–3.6
–5.5
–3.3
–5.0
–3.0
–4.5
V
V
IEE
Power Supply Current(4)
150
175
mA
No Load, Over Supply Voltage
Notes:
1. Permanent device damage may occur if “Absolute Maximum Ratings” are exceeded. This is a stress rating only and functional operation is not
implied at conditions other than those detailed in the operational sections of this data sheet. Exposure to “Absolute Maximum Rating” conditions for
extended periods may affect device reliability.
2. The data sheet limits are not guaranteed if the device is operated beyond the operating ratings.
3. Devices are ESD sensitive. Handling precautions recommended.
4. Required 500lfpm air flow when using +5V or –5V power supply.
M0644-012704
4
ECL Pro®
SY100EP196V
Micrel
(100kEP) LVPECL DC ELECTRICAL CHARACTERISTICS
VCC = 3.3V, VEE = 0V; TA = –40°C to +85°C(5, 6)
Symbol
Parameter
Condition
Min
Typ
Max
Units
VOH
Output HIGH Voltage
Figures 2, 3, 6
2155
2280
2405
mV
VOL
Output LOW Voltage
Figures 2, 3, 6
1355
1480
1605
mV
VIH
Input HIGH Voltage
PECL
CMOS
TTL
Figures 1, 4
2075
1815
2000
2420
mV
mV
mV
Input LOW Voltage
PECL
CMOS
TTL
Figures 1, 4
1355
1675
1485
800
mV
mV
mV
VIL
VBB
Output Voltage Reference
1775
1875
1975
mV
VCF
Input Select Voltage
1610
1720
1825
mV
VEF
Mode Connection
1900
2000
2100
mV
VIHCMR
Input HIGH Voltage Common
Mode Range(7)
3.3
V
IIH
Input HIGH Current
150
µA
IIL
Input LOW Current
IN
/IN
Figure 5
2.0
0.5
–150
µA
µA
Notes:
5. Device is guaranteed to meet the DC specifications, shown in the table above, after thermal equilibrium has been established. The device is tested in
a socket such that transverse airflow of ≥ 500lfpm is maintained.
6. Input and output parameters vary 1:1 with VCC. VEE can vary +0.3V to –2.2V.
7. VIHCMR maximum varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal.
M0644-012704
5
ECL Pro®
SY100EP196V
Micrel
(100kEP) PECL DC ELECTRICAL CHARACTERISTICS
VCC = 5.0V, VEE = 0V; TA = –40°C to +85°C(8, 9)
Symbol
Parameter
Condition
Min
Typ
Max
Units
VOH
Output HIGH Voltage
Figures 2, 3, 6
3855
3980
4105
mV
VOL
Output LOW Voltage
Figures 2, 3, 6
3055
3180
3305
mV
VIH
Input HIGH Voltage
PECL
CMOS
TTL
Figures 1, 4
3775
2750
2000
4120
mV
mV
mV
Input LOW Voltage
PECL
CMOS
TTL
Figures 1, 4
3055
3375
2250
800
mV
mV
mV
3675
mV
5.0
V
150
µA
VIL
VBB
Output Voltage Reference
VIHCMR
Input HIGH Voltage Common
Mode Range(10)
IIH
Input HIGH Current
IIL
Input LOW Current
IN
/IN
3475
Figure 5
3575
2.0
µA
µA
0.5
–150
(100kEP) NECL DC ELECTRICAL CHARACTERISTICS
VCC = 0V, VEE = –5.5V to –3.0V; TA = –40°C to +85°C(8)
Symbol
Parameter
Condition
Min
Typ
Max
Units
VOH
Output HIGH Voltage
Figures 2, 3
–1145
–1020
–895
mV
VOL
Output LOW Voltage
Figures 2, 3
–1945
–1820
–1695
mV
VIH
Input HIGH Voltage NECL
Figures 1, 4
–1225
–880
mV
VIL
Input LOW Voltage NECL
Figures 1, 4
–1945
–1625
mV
VBB
Output Voltage Reference
–1325
mV
VIHCMR
Input HIGH Voltage Common
Mode Range(11)
0.0
V
IIH
Input HIGH Current
150
µA
IIL
Input LOW Current
IN
/IN
–1525
Figure 5
–1425
VEE+2.0
0.5
–150
µA
µA
Notes:
8. Device is guaranteed to meet the DC specifications, shown in the table above, after thermal equilibrium has been established. The device is tested in
a socket such that transverse airflow of ≥ 500lfpm is maintained.
9. Input and output parameters vary 1:1 with VCC. VEE can vary +2.0V to –0.5V.
10. VIHCMR maximum varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal.
11. VIHCMR minimum varies 1:1 with VEE. The VIHCMR range is referenced to the most positive side of the differential input signal.
M0644-012704
6
ECL Pro®
SY100EP196V
Micrel
AC ELECTRICAL CHARACTERISTICS
VCC = 3.0 to 5.5V, VEE = 0V or VCC = 0V, VEE = –3.0 to –5.5V; TA = –40°C to +85°C(12, 13)
TA = –40°C
Symbol
Parameter
Min
Frequency(14)
Typ
fMAX
Maximum
tPD
Propagation Delay
IN to Q; D[0-10]=0
IN to Q; D[0-10]=1023
/EN to Q: D[0-10]=0
D10 to CASCADE
1650
9500
1600
300
2000
11500
2150
420
tRANGE
Programmable Range
tPD(max)-tPD(min)
7850
9450
∆t
Step Delay(15)
Linearity(16)
tSKEW
Duty Cycle Skew(17)
Min
2.5
D0 High
D1 High
D2 High
D3 High
D4 High
D5 High
D6 High
D7 High
D8 High
D9 High
Lin
TA = +25°C
Max
Typ
TA = +85°C
Max
Min
2.5
2450
13500
2600
500
1800
9800
1800
325
2050
12200
2300
450
8200
10000
Typ
Max
2.5
2600
14000
2800
550
Unit
GHz
1950
10600
2000
325
2250
13300
2500
525
2750
15800
3000
625
ps
ps
ps
ps
8850
10950
ps
9
25
42
75
142
296
532
1080
2100
4250
10
26
42
80
143
300
540
1095
2150
4300
10
27
43
81
150
310
565
1140
2250
4500
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
±10
±10
±10
%LSB
tPHL-tPLH
25
ps
tS
Setup Time
D to LEN
D to IN(18)
/EN to IN(19)
200
300
300
0
140
150
200
300
300
0
160
170
200
300
300
0
180
180
ps
ps
ps
tH
Hold Time
LEN to D
IN to /EN(20)
200
400
60
250
200
400
100
280
200
400
80
300
ps
ps
tR
Release Time
/EN to IN(21)
SETMAX to LEN
SETMIN to LEN
400
350
200
275
400
350
500
250
200
400
350
300
335
ps
ps
ps
tJIT
Cycle-to-Cycle Jitter(22)
VPP
Input Voltage Swing (Differential)
tr
tf
Output Rise/Fall Time
20% to 80% (Q)
20% to 80% (CASCADE)
150
0.2
