SY58626L
DC-to-6.4Gbps Backplane Transmit Buffer with
Selectable Output Pre-emphasis, I/O DC-Offset
Control, and 200mV-3.0VPP Output Swing
General Description
The SY58626L high-speed, low jitter transmit buffer is
optimized for backplane and transmission line data-path
management applications in Automatic Test Equipment
(ATE) and Test & Measurement (T&M) systems. The
buffer includes a CML compatible, variable swing output
with selectable pre-emphasis.
The SY58626L is
capable of driving serial data from DC through 6.4Gbps
with a 3VPP (1.5VPK single ended) differential swing.
The SY58626L differential input includes Micrel’s
unique, 3-pin input termination architecture that directly
interfaces to any DC- or AC-coupled, differential signal
as small as 100mVPK without any termination resistor
networks in the signal path. The outputs are 50Ω
source-terminated CML with a programmable output
swing from 200mVPP to 3VPP (100mVPK to 1.5VPK).
The SY58626L includes an output stage that provides 4
levels of pre-emphasis. The output pre-emphasis level is
programmed with a three-bit interface. Unlike other
transmitter solutions, the output pre-emphasis duration
can be programmed from 60ps to 400ps.
The SY58626L operates at 3.3V ±10% supply and is
guaranteed over the commercial temperature range of
0°C to +70°C. The SY58626L transmitter is optimized to
work with the SY58627L receiver. The SY58626L is part
®
of Micrel’s high-speed, Precision Edge product line.
Data sheets and support documentation can be found
on Micrel’s website at: www.micrel.com.
®
Precision Edge
Features
• Transmit driver provides output pre-emphasis to
extend transmission range
• 4 selectable pre-emphasis levels
• Drives 6.4Gbps up to 12 FR4 PCB trace, or longer
combinations of FR4+cable+interconnect
• DC through 6.4Gbps data rate throughput
• Integrated loopback capability
• Unique pre-emphasis:
- Programmable pre-emphasis magnitude
- Programmable pre-emphasis duration
• Unique, flexible I/O:
- Internal termination to VTTIN pin interfaces to any
differential AC- or DC-coupled signals
- 50Ω source terminated CML outputs minimize
round-trip reflections
- Programmable output swing control: 200mV3.0VPP
- Output Disable and output shutdown
- DC-offset control with VTT I/O
• 3.3V ±10% supply voltage
• 0°C to +70°C temperature range
• Available in 32-pin (5mm x 5mm) QFN package
Applications
•
•
•
•
ATE, T&M backplane management
Combination FR4+cable+interconnect driver
Cable drivers
Electrical interface and interconnect applications that
require DC-offset control
United States Patent No. RE44,134
Precision Edge is a registered trademark of Micrel, Inc.
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (408) 944-0800 • fax + 1 (408) 474-1000 • http://www.micrel.com
June 2007
M9999-061207-C
hbwhelp@micrel.com or (408) 955-1690
Micrel, Inc.
SY58626L
Functional Block Diagram
June 2007
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SY58626L
Ordering Information(1)
Part Number
Package Type
Operating Range
Package Marking
Lead Finish
SY58626LMH
QFN-32
Commercial
SY58626L with
bar-line Pb-Free indicator
NiPdAu
Pb-Free
QFN-32
Commercial
SY58626L with
bar-line Pb-Free indicator
NiPdAu
Pb-Free
(2)
SY58626LMHTR
Notes:
1.
Contact factory for die availability. Dice are guaranteed at TA = 25°C, DC Electricals only.
2.
Tape and Reel.
Pin Configuration
32-Pin QFN
June 2007
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SY58626L
Pin Description
Pin Number
Pin Function
TXIN, /TXIN
Differential inputs: This input pair is the differential signal input to the device. They
accept AC- or DC-coupled signals as small as 100mV (200mVPP). Note that this
input will default to an undetermined state if left open. TXIN and /TXIN internally
terminate to the VTTIN pin through 50Ω. Please refer to the “Input Interface
Applications” section for more details.
VTTIN
Input termination center-tap: TXIN and /TXIN terminate to VTTIN. The VTTIN pin
provides a center-tap to the internal termination network for maximum interface
flexibility and DC-offset capability. Please refer to the “Input Interface Applications”
section for more details.
VREF-AC
Reference voltage: This output biases to VCC -1.3V. It is used for AC-coupling the
input pair (TXIN, /TXIN). Connect VREF-AC directly to the VTTIN pin. Bypass with a
0.01uF low ESR capacitor to VCC. Maximum sink/source current is ±1.5mA. Due to
the limited drive capability, the VREF-AC pin is only intended to drive the VTTIN pin.
Please refer to the “Input Interface Applications” section for more details.
TXVCTRL
Analog input that controls TXQ output swing amplitude. The operating range of the
control input is from VREF-CTRL (max swing) to VCC (min swing). Control of the
output swing can be obtained by using a variable resistor between VREF-CTRL and
VCC with the wiper driving TXVCTRL. Output swing ranges from 100mVPK to
1.5VPK. When the TXQ output is selected for maximum swing amplitude of 1.5VPK,
no pre-emphasis is possible since the maximum swing cannot extend beyond
1.5VPK. For applications that only require a fixed, full CML swing, connect
TXVCTRL to VREF-FIXED.
12
VREF-CTRL
Reference control voltage for TXVCTRL swing control. The operating range of the
control input is from VREF-CTRL (max swing) to VCC (min swing). Control of the
output swing can be obtained by using a variable resistor between VREF-CTRL and
VCC with the wiper driving TXVCTRL. Maximum sink/source current is ±1.5mA.
14
VREF-FIXED
Reference output voltage: Connect this reference output pin directly to the
TXVCTRL input pin, and the TXQ output swing is fixed to 400mVPK (800mVPP).
4, 5
7
8
13
24
29
1
30, 31
June 2007
Pin Name
/TXEN
TTL/CMOS (or VTH controlled) compatible control input for the TXQ Outputs pair.
When pulled HIGH, the TXQ Output pair is disabled. This input is internally
connected to a 25kΩ pull-down resistor and will default to a logic LOW state
(Enable) if left open. When disabled, the TXQ output goes LOW, and /TXQ goes
HIGH. Default threshold is Vcc/2 when VTH pin is floating.
/TXLBEN
TTL/CMOS (or VTH controlled) compatible control input for the TXLBQ output pair.
When pulled HIGH, the TXLBQ output pair is disabled. This input is internally
connected to a 25kΩ pull-down resistor and will default to a logic LOW state
(Enable) if left open. When disabled, the TXLBQ output goes LOW, and /TXLBQ
goes HIGH. Default threshold is Vcc/2 when VTH pin is floating.
LBSEL
Loopback MUX select control: The TTL/CMOS (or VTH controlled) compatible input
selects the input to the Loopback mode multiplexer. When LBSEL input is a logic
HIGH, the Loopback mode is selected, and the RXLBIN input pair is selected to
pass through the TXQ output. Note that the LBSEL pin is internally connected to a
25kΩ pull-down resistor and will default to a logic LOW state if left open (normal
operation). The loopback MUX includes internal input isolation to minimize
crosstalk.
RXLBIN,
/RXLBIN
Loopback differential input pair: AC-coupled, CML compatible input. This input pair
includes internal termination connected to an internal VBB for an AC-coupled bias
configuration. The RXLBIN input pair receives a signal from the RX buffer
(SY58627L RXLBQ) loopback output. This input pair does not include any
equalization. When Loopback mode is selected, the signal at the RXLBIN input is
directed to the TXQ output.
4
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SY58626L
Pin Description (Continued)
Pin Number
27, 28
23
2
21, 20
Pin Name
TXLBQ,
/TXLBQ
/TXQSHDN
VTH
TXQ,
/TXQ
19, 22
VTTOUT
17
MAG_CTRL0
18
MAG_CTRL1
32
MAG_CTRL2
10
DUR_CTRL0
11
DUR_CTRL1
9, 15, 26
VCC
3, 6, 16, 25
VEE,
Exposed Pad
June 2007
Pin Function
Transmit loopback differential output: CML compatible output pair with 400mV swing
into a 50Ω load (100Ω across the pair). The TXLBQ output pair is providing a copy of
the TXIN input signal, bypassing the pre-emphasis stage. The SY58626L loopback
function is optimized to operate with the SY58627L receiver, and the TXLBQ output
pair is AC-coupled directly to the TXLBIN input pair on the SY58627L.
TXQ shutdown control pin: The TTL/CMOS (or VTH controlled) compatible pin is an
active LOW function. This input is internally connected to a 25kΩ pull-up resistor and
will default to a logic HIGH state if left open. When pulled LOW, the TXQ and /TXQ
output currents are shut off, and the TXQ and /TXQ output voltage is set to the same
potential. The actual voltage level is set by the resistor divider ratio established by
the internal 50Ω source resistors (connected to VTTOUT) and the external load.
Default threshold is Vcc/2 when VTH pin is floating.
Input logic threshold control voltage for logic control threshold settings other than
LVTTL/CMOS. This input control pin can be externally biased to set the proper
threshold for all the logic control pins, /TXEN, LBSEL, /TXLBEN, 3-bit pre-emphasis
control, 2-bit pre-emphasis duration control, and /TXQSHDN. For standard
LVTTL/CMOS control, simply leave the VTH pin floating and the threshold voltage
defaults to VCC/2 (When VEE=0V). For LVPECL thresholds, set VTH to Vcc-1.3V.
Differential variable swing output pair: This CML output pair is the output of the
device. This output is designed to drive 100mVPK to 1.5VPK into 50Ω (100Ω across
the pair) with variable pre-emphasis. TXQ outputs include 50Ω source termination
resistors. When the loopback mode is selected, the TXQ output pair is driven by the
RXLBIN inputs.
Output termination center-tap: Each side of the differential output pair terminates to
the VTTOUT pin through 50Ω. The VTTOUT pin provides a center-tap to the output
termination network for maximum interface flexibility, and DC-offset capability.
Please refer to the “CML Output Interface Applications” section for more details.
Pre-emphasis magnitude level control input: TTL/CMOS (or VTH controlled)
compatible, 3-bit control interface. There are four levels of pre-emphasis magnitude,
as shown in the “Pre-Emphasis Magnitude Truth Table.” When MAG_CTRL2 (MSB)
is logic 1, pre-emphasis is disabled and the TXQ outputs will not include any preemphasis. Pre-emphasis magnitude ranges from 10% to 33% above the base swing.
Pre-emphasis duration control input. TTL/CMOS (or VTH controlled) compatible, 2-bit
control interface. This control establishes the pre-emphasis duration. Duration ranges
from 60ps to 400ps typical as shown in the “Pre-emphasis Duration Control Truth
Table.” Pre-emphasis duration is measured from the mid-point of the pre-emphasis
magnitude (50% point). Please refer to the “Pre-emphasis Output Description” for
details.
Positive power supply: Connect to +3.3V power supply. Bypass with 0.1µF//0.01µF
low ESR capacitors as close to VCC pins as possible.
Ground: Ground pins and exposed pad must be connected to the same ground
plane.
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SY58626L
Pre-emphasis Magnitude Truth Table
Disable Mag Select
(MSB=MAG_CTRL2)
Magnitude Select
(MAG_CTRL1)
Magnitude Select
(MAG_CTRL0)
Pre-emphasis
Magnitude
0
0
0
10%
0
0
1
15%
0
1
0
25%
0
1
1
33%
1
X
X
Disabled
DUR_CTRL0
Typical Data Rate
Time Duration
3.2Gbps-6.4Gbps
Pre-emphasis Duration Control Truth Table
Duration
DUR_CTRL1
Minimum (Shortest)
0
0
Medium-short
0
1
Medium-long
1
0
Longest
1
1
60ps
100ps
DC-3.2Gbps
200ps
400ps
Pre-emphasis Output Description
June 2007
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SY58626L
Absolute Maximum Ratings(1)
Operating Ratings(2)
Supply Voltage (VCC) ............................................... -0.5V to +4.0V
Input Voltage (VIN) ...................................................... -0.5V to VCC
Input Current (TXIN, /TXIN, ≤120mins) ................................ 67mA
CML Output Current (IOUT)
Continuous (≤120mins)..................................................... 67mA
Surge .............................................................................. 100mA
Termination Current
VT .................................................................................. ±100mA
VREF-AC Current
Source/sink current on VREF-AC.......................................... ±2mA
Source/sink current on VREF-CTRL....................................... ±2mA
Lead Temperature (soldering, 20 sec.) ..............................+260°C
Storage Temperature (TS) ..................................... -65°C to 150°C
Supply Voltage (VCC) .................................... +3.0V to +3.6V
Ambient Temperature (TA) ............................... 0°C to +70°C
(3)
Package Thermal Resistance
QFN (θJA)
Still-Air ............................................................... 34°C/W
QFN (ΨJB)
Junction-to-Board .............................................. 20°C/W
DC Electrical Characteristics(4)
TA= 0°C to +70°C; unless otherwise stated.
Symbol
Parameter
VCC
Power Supply
Condition
Min
Typ
Max
Units
3.0
3.3
3.6
V
IEE
Power Supply Current
290
370
mA
RIN
Input Resistance
(TXIN-to-VTTIN)
45
50
55
Ω
RDIFF_IN
Differential Input Resistance
(TXIN-to-/TXIN)
90
100
110
Ω
VIH
Input High Voltage
(TXIN, /TXIN)
VEE+1.5
VCC
V
VIL
Input LOW Voltage
(TXIN, /TXIN)
VEE+0.7
VIH-0.1
V
VIN
Input Voltage Swing
(TXIN, /TXIN)
See Figure 4a.
0.1
1.5
VPK
VDIFF_IN
Differential Input Voltage Swing
|TXIN-/TXIN|
See Figure 4b.
0.2
VTTIN
TXIN-to-VTTIN
(TXIN, /TXIN)
VTTIN
Range
VTTIN Voltage Range
Voltage applied to VTTIN pin
VTTOUT
Range
VTTOUT Voltage Range
Voltage applied to VTTOUT pin
Max VCC, includes 50Ω internal
source resistors, 1.5VPK output
swing, no external load current
VPP
1. 28
V
VEE+1.7
VCC+0.1
V
VCC-1.5
VCC+1.5
V
Notes:
1. Permanent device damage may occur if absolute maximum ratings are exceeded. This is a stress rating only and functional operation is
not implied at conditions other than those detailed in the operational sections of this data sheet. Exposure to absolute maximum ratings
conditions for extended periods may affect device reliability.
2. The data sheet limits are not guaranteed if the device is operated beyond the operating ratings.
3. Package thermal resistance assumes exposed pad is soldered (or equivalent) to the devices most negative potential on the PCB. θJA and
ΨJB values are determined for a 4-layer board in still air unless otherwise stated.
4. The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. 500lfpm
Airflow. TJ < 125°C.
June 2007
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SY58626L
TXQ Outputs DC Electrical Characteristics(5)
VCC = 3.3V ±10%; VEE = 0V; TA = 0°C to + 70°C; RL = 100Ω across output pair; unless otherwise stated.
Symbol
Parameter
VOUT
Range
Output Voltage Range
(TXQ, /TXQ)
Condition
Min
VCC-1.5
Maximum Swing (TXVCTRL =
VREF-CTRL)
No pre-emphasis
VOUT
TXQ Output Voltage Swing
(6)
(TXQ, /TXQ)
Maximum Swing (TXVCTRL =
VREF-CTRL)
No pre-emphasis
TXQ Differential Output Voltage
Swing
(7)
|TXQ-/TXQ|
Units
VCC
V
100
325
mVPK
400
3000
Minimum Swing
(TXVCTRL = VCC)
Fixed Output Swing
(TXVCTRL = VREF-Fixed)
Max
1500
Minimum Swing
(TXVCTRL = VCC)
Fixed Output Swing
(TXVCTRL = VREF-Fixed)
VDIFF_OUT
Typ
650
200
mVPP
800
ROUT
Output Resistance
45
50
55
Ω
VREF-AC
Output Voltage Reference
VCC-1.4
VCC-1.3
VCC-1.2
V
VREF-CTRL
VREF-CTRL Output Voltage
VCC-1.4
VCC-1.3
VCC-1.2
V
TXVCTRL
Output Swing Control Voltage
Range
VREF-AC
VCC
V
ITX QSHDN
TXQ Shutdown Leakage Current
-500
500
µA
TXLBQ CML Output DC Electrical Characteristics(5)
VCC = 3.3V ±10%; VEE = 0V; TA = 0°C to + 70°C; RL = 100Ω across output pair; unless otherwise stated.
Symbol
Parameter
Condition
VOH
TXLBQ Output High Voltage
RL = 50Ω to Vcc
Min
Typ
Max
Units
VCC-0.040
VCC-0.010
VCC
V
VOUT
TXLBQ Output Voltage Swing
(6)
(TXLBQ, /TXLBQ)
325
400
mVPK
VDIFF_OUT
TXLBQ Differential Output
Voltage Swing
(7)
|TXLBQ-/TXLBQ|
650
800
mVPP
ROUT
Output Impedance
45
50
55
Ω
Notes:
5. The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. 500lfpm
Airflow. TJ < 125°C.
6. Please refer to figure 4a.
7. Please refer to figure 4b.
June 2007
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SY58626L
Logic Control DC Electrical Characteristics(8)
VCC = 3.3V ±10%; VEE = 0V; TA = 0°C to + 70°C; unless otherwise stated.
Symbol
Parameter
Condition
Min
Typ
Max
Units
VIH
Input HIGH Voltage
All control input pins
VTH+0.2
VCC
V
VIL
Input LOW Voltage
All control input pins
VEE
VTH–0.2
V
VCTRL
Output Swing Control Voltage
Range at TXVCTRL
VREF-CTRL
VCC
V
IIH
Input HIGH Current
300
µA
IIL
Input LOW Current
VTH
Threshold Input Voltage
-300
Voltage applied to pin
(VEE = 0V)
1.4
µA
VCC/2
2.6
V
Notes:
8. The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. 500lfpm
Airflow. TJ < 125°C.
June 2007
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SY58626L
AC Electrical Characteristics(9)
VCC = 3.3V ±10%; VEE = 0V; TA = 0°C to + 70°C; RL = 100Ω across output pair; unless otherwise stated.
Symbol
Condition
Min
1.5VPK output swing,
No pre-emphasis
DC
6.4
400mV output swing,
33% pre-emphasis
DC
6.4
Data Rate Throughput (TXLBQ)
400mV output swing
DC
6.4
Gbps
tpd
Differential Propagation Delay
TXIN-to-TXQ (VIN >200mVPK)
150
450
ps
tpd Tempco
Differential Propagation Delay
Temperature Coefficient
Freq
Parameter
Data Rate Throughput (TXQ)
RXLBIN-to-TXQ
tEN
TXQ Enable/Disable Time
/TXEN
tLB_EN
TXLBQ Enable/Disable Time
/TXLBEN
tSHDN
tLBSEL
tPROG
MAG_CTRL
DUR_CTRL
TXQ Shutdown Time
Typ
250
Gbps
ps
120
fs/ C
o
600
200
ps
ps
/TXQ_SHDN HIGH-to-LOW
(TXQ Outputs SHUTDOWN)
3
/TXQ_SHDN LOW-to-HIGH
(TXQ Outputs ON)
3
4.5
350
600
4.5
ns
LBSEL
Programming Logic Control Time
3-bit pre-emphasis magnitude,
2-bit duration control
update-to-valid TXQ
1
(0,0,0)
10
(0,0,1)
15
(0,1,0)
25
(0,1,1)
33
(1,X,X)
0
Pre-emphasis Duration
DUR_CTRL (1,0)
Units
250
Loopback Select Time
Pre-emphasis Magnitude
(Percent beyond base swing)
MAG_CTRL (2,1,0)
Max
Minimum (shortest)
60
Medium-short
100
Medium-long
200
Longest
400
ps
ns
%
ps
tSKEW
Part-to-Part Skew
Note 10
tJITTER
Random Jitter (RJ)
Note 11, 13, 14, 15
1
ps
Deterministic Jitter (DJ)
Note 12, 13, 14, 15
15
ps
Output Rise/Fall Time (20% to 80%)
At full output swing
tr, tf
200
20
50
80
ps
ps
Notes:
9.
High-frequency AC-parameters are guaranteed by design and characterization.
10. Part-to-part skew is defined for two parts with identical power supply voltages at the same temperature and with no skew of the edges at
the respective inputs.
11. This jitter is the RMS difference between the RJ measured at the end of a 9in FR4 transmission line driven by the SY58626 and the
signal source.
12. This jitter is a difference between the DJ measured at the end of a 9in FR4 transmission path driven by an SY58626 and the signal
source.
13. PE Mag: 010 and PE Dur: 10.
14. The typical jitter is measured at 4.25Gbps and 6.4Gbps using PRBS 27 pattern and 4.25Gbps using K28.5 pattern.
15. The transmission line is differential 6mil FR4 stripline with 100Ω differential impedance.
June 2007
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SY58626L
•
Detailed Description
The SY58626L is a high speed, low jitter transmit
buffer with integrated loopback capability. Adjustable
pre-emphasis amplitudes and selectable pre-emphasis
durations are included with the transmitter. The
SY58626L also includes disable and shutdown control
for the transmitter output.
Control of the transmitter output swing buffer
can be obtained by using a variable resistor
connected between VREF-CTRL and VCC
with the wiper driving TXVCTRL. Please refer
to Figure 1 for more details.
Transmitter Disable and Shutdown
The SY58626L provides two methods to turn off the
output when desired. When /TXEN is pulled HIGH, the
transmitter output pair is disabled. TXQ goes to a LOW
state and /TXQ goes to a HIGH state. When
/TXQSHDN is pulled LOW, the transmitter output pair
is in shutdown mode. TXQ and /TXQ output currents
are shut off and the TXQ and /TXQ outputs are set to
the same potential. The threshold for the /TXEN and
/TXQSHDN pins is set with the VTH pin. Please refer
to the “Typical Operating Characteristics” for more
details.
Transmitter
The SY58626L transmitter includes the VTTIN and
VTTOUT pin for maximum interface flexibility and DCoffset capability for the input and output, respectively.
This feature allows for interfacing with different logic
families without the use of AC-coupling. The output
buffer has internal 50Ω source terminated CML
outputs for minimizing round-trip reflections.
Loopback
The SY58626L features a loopback test mode,
activated by setting LBSEL to logic HIGH. Using the
SY58626L with the SY58627L enables local loopback
and link side loopback, shown in Figures 2b and 2c.
This mode enables an external loopback path,
bypassing circuitry on both local and link side. Please
refer to Table 1 and Figure 3 for Loopback Control
information.
Figure 1. Variable Output Swing Circuit
Transmitter Variable-Swing Output Buffer
•
Connecting VREF-CTRL to TXVCTRL sets the
transmitter output buffer to max swing 1.5VPK
(3.0VPP).
•
Connecting VCC to TXVCTRL sets the
transmitter output buffer to minimum swing
100mVPK (200mVPP).
•
Connecting VREF-FIXED to TXVCTRL sets
the transmitter output buffer to 400mVPK
(800mVPP).
June 2007
Figure 2a. Normal Operation
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SY58626L
Link Side
Loopback
Mode
Normal
Mode
Micrel, Inc.
TXLB
TXLBENb
TXENb
TXQ
TXLBQ
0
0
0
TXIN
TXIN
0
0
1
0
TXIN
0
1
0
TXIN
0
0
1
1
0
0
1
0
0
RXLBIN
TXIN
1
0
1
0
TXIN
1
1
0
RXLBIN
0
1
1
1
0
0
Table 1. Transmit Loopback Control Signal
Figure 2b. Local Loopback Mode
Figure 3. Loopback Control Pin
Figure 2c. Link Side Loopback Mode
June 2007
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SY58626L
Typical Operating Characteristics
VCC = 3.3V ±10%; VIN > 400mV; TA = 25°C, RL = 100Ω across output pair; unless otherwise stated.
June 2007
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SY58626L
Typical Operating Characteristics (Continued)
VCC = 3.3V ±10%; VIN > 400mV; TA = 25°C, RL = 100Ω across output pair; unless otherwise stated.
Output Disable
Output Shutdown
TXQ
/TXQ
HIGH
/TXQ
TXQ
LOW
HIGH
/TXQSHDN
HIGH
LOW
/TXEN
LOW
Time (250ns/div.)
Time (250ns/div.)
June 2007
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SY58626L
Single-Ended and Differential Swings
Figure 4a. Single-Ended Voltage Swing
Figure 4b. Differential Voltage Swing
Input and Output Stages
Figure 5a. Simplified Differential Input Stage
June 2007
Figure 5b. Simplified Differential Output Stage
15
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Micrel, Inc.
SY58626L
Input Interface Applications
option: may connect VTTIN to VCC
Figure 6a. LVPECL Interface
(DC-Coupled)
Figure 6b. LVPECL Interface
(AC-Coupled)
Figure 6d. CML Interface
(AC-Coupled)
Figure 6e. LVDS Interface
(DC-Coupled)
June 2007
16
Figure 6c. CML Interface
(DC-Coupled)
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hbwhelp@micrel.com or (408) 955-1690
Micrel, Inc.
SY58626L
CML Output Interface Applications
Figure 7a. CML DC-Coupled
Termination
Figure 7b. CML DC-Coupled
Termination
Figure 7c. CML AC-Coupled
Termination
Related Product and Support Information
Part Number
Function
Datasheet Link
SY58627L
DC-to-6.4Gbps Backplane Receive Buffer with 4Stage Programmable Equalization and DC-Offset
Control
www.micrel.com/product-info/products/sy58627u.shtml
HBW Solutions
New Products and Applications
www.micrel.com/product-info/products/solutions.shtml
June 2007
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hbwhelp@micrel.com or (408) 955-1690
Micrel, Inc.
SY58626L
Package Information
32-Pin QFN
Package Notes:
1. Package meets Level 2 Moisture Sensitivity Classification.
2. All parts are dry-packed before shipment.
3. Exposed pad must be soldered to a ground for proper thermal management.
MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA
TEL +1 (408) 944-0800 FAX +1 (408) 474-1000 WEB http://www.micrel.com
The information furnished by Micrel in this data sheet is believed to be accurate and reliable. However, no responsibility is assumed by Micrel for
its use. Micrel reserves the right to change circuitry and specifications at any time without notification to the customer.
Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a
product can reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for
surgical implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant
injury to the user. A Purchaser’s use or sale of Micrel Products for use in life support appliances, devices or systems is a Purchaser’s own risk
and Purchaser agrees to fully indemnify Micrel for any damages resulting from such use or sale.
© 2005 Micrel, Incorporated.
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