SY87725L
2.5Gbps GPON/BPON ONU SERDES
General Description
Features
The SY87725L is a single chip transceiver for data rates
up to 2.5Gbps. On the receive side, it includes a
complete clock recovery and data retiming circuit with
an integrated 4-bit serial-to-parallel data converter. On
the transmit side, it includes a synthesizer with an
integrated 4-bit parallel-to-serial data converter.
The SY87725L receiver has a synthesizer that
generates an internal clock from an externally supplied
TTL or PECL REFCLK that can be either 155.52MHz or
77.76MHz. This internal clock can be used by the clock
recovery PLL if an absence of transitions on the input
serial data stream prevents normal clock recovery. This
enables it to provide a stable clock source in the
absence of transitions on the incoming serial data
stream.
The transmit synthesizer uses the CLKIN parallel data
clock to generate its own serial rate clock locked to
CLKIN. This enables the transmit and receive to operate
at different data rates.
The serial interface for both the transmit and receive
functions feature industry standard high-speed
differential CML I/O. The parallel interfaces feature highspeed LVDS I/O with an internal 100Ω termination on
the LVDS inputs.
The first bit for the serial-to-parallel conversion can be
moved using the RCV_SYNC input. The RCV_SYNC
input enables the parallel word boundary to move up in
time by one bit time for each pulse. This allows it to in
effect “swallow” one bit each time the RCV_SYNC pulse
is asserted.
Datasheets and support documentation can be found on
Micrel’s web site at: www.micrel.com.
•
•
•
•
•
•
•
•
•
•
Single 3.3V supply and 1W typ. power consumption
2.5G/1.25G/625Mbps down stream
1.25G/625M/156Mbps up stream
4-bit Serdes with LVDS interfaces
Serial Data input sensitivity of 30mV typical
Training mode for fast lock acquisition
Link Fault Indicator (LFIN: “HIGH” = Locked)
Separate training and MUX synthesizers
Loop back function for diagnostics
TTL–CML Translator for MAC-to-Laser diode driver
burst control
• Selectable double data rate option for low cost
FPGA/ASIC MAC implementation
• Available in Pb-Free (10mm x 10mm) 64-pin
EPAD-TQFP
Applications
• BPON/GPON/GEPON/EPON
Markets
• FTTH/FTTP
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (408) 944-0800 • fax + 1 (408) 474-1000 • http://www.micrel.com
July 2007
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SY87725L
Functional Block Diagram
July 2007
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SY87725L
Pin Configuration
64-Pin EPAD-TQFP (T64-1)
Ordering Information
Part Number
Package
Type
Operating
Range
Package Marking
Lead
Finish
SY87725LHY
H64-1
Industrial
SY87725LHY with
Pb-Free bar-line indicator
Pb-Free
Matte-Sn
H64-1
Industrial
SY87725LHY with
Pb-Free bar-line indicator
Pb-Free
Matte-Sn
SY87725LHYTR
(2)
Notes:
o
1. Contact factory for die availability. Dice are guaranteed at TA = 25 C, DC electricals only.
2. Tape and Reel.
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SY87725L
Pin Description
RECEIVE SECTION SIGNALS
Pin Number
Pin Name
55, 56
SINP, SINN
60, 61
REFCLKP,
REFCLKN,
Pin Description
Serial Data In (Differential LVPECL Input): This input receives the serial differential
data stream. An internal PLL recovers the embedded clock and data.
Reference Clock (TTL or Differential LVPECL Input): This input accepts either singleended TTL or differential LVPECL signals and is used as the reference for the internal
frequency synthesizer and the “training” frequency for the receiver PLL to keep it
centered in the absence of data at the SIN input. The REFCLKN input has an internal
reference circuit that applies the threshold voltage in case of a single-ended TTLsignal at REFCLKP. REFCLKN has an internal 75kΩ to GND and can be left open
in that case.
15
REFFREQSEL
Reference Clock Frequency Select (TTL Input): Selects REFCLK frequency of
77.76MHz when LOW or 155.52MHz when HIGH.
6, 7
RCV_PLLRP,
RCV_PLLRN
Clock Recovery PLL Loop Filter: External loop filter pins for the receive PLL.
1, 2
RCV_PLLSN,
RCV_PLLSP
Clock Synthesis PLL Loop Filter: External loop filter pins for the clock synthesis PLL.
59
RCV_SYNC
Receive Synchronizer (TTL Input): Single-ended asynchronous input to set the word
boundary on the 4-bit parallel data
3, 5
RCV_FSEL0,
RCV_FSEL1
Receive Frequency Control (TTL Inputs): Two single-ended frequency selects for
receive synthesizer.
39, 40,
41, 42,
43, 44,
45, 46
DOUTOP, DOUT0N,
DOUT1P, DOUT1N,
DOUT2P, DOUT2N,
DOUT3P, DOUT3N
Parallel Data Out (LVDS Outputs): These are the four pairs of receive parallel data
outputs.
33, 34
CLKOUT2P,
CLKOUT2N
Parallel Clock Out (LVDS Output): This output is the recovered clock at the transmit
byte clock rate and provides a clock that can be used as a reference clock to drive
CLKIN.
36, 37
CLKOUTP,
CLKOUTN
Parallel Clock Out (LVDS Output): This output is the recovered clock divided by 4 or 8
to provide the parallel data rate clock.
18
LFIN
63
RCV_DDRSEL
Double Data Rate Select (TTL Input): Selects either parallel data rate clock for normal
operation or one-half of parallel data rate clock for double data rate applications.
62
CD
Carrier Detect Input (LVPECL input): When HIGH, CD indicates the carrier is present
and when LOW it indicates the loss of carrier.
Link Fault Indicator (TTL Output): When HIGH, LFIN indicates CDR is “in-lock” and
when LOW it indicates CDR loss-of-lock.
TRANSMIT SECTION SIGNALS
25, 26, 27,
28, 29, 30,
31, 32
DIN0P, DIN0N,
DIN1P, DIN1N,
DIN2P, DIN2N,
DIN3P, DIN3N
22, 23
CLKINP, CLKINN
Parallel Clock In (LVDS Input): This input is the transmit parallel (byte-rate) clock.
10, 14
XMT_FSEL0,
XMT_FSEL1
Transmit Frequency Control (TTL Inputs): Two single-ended frequency selects for
transmit synthesizer.
11, 12
XMT_PLLSN,
XMT_PLLSP
Clock Synthesis PLL Loop Filter: External loop filter pins for the clock synthesis PLL.
49, 50
SOUTP, SOUTN
24
XMT_DDRSEL
July 2007
Parallel Data In (LVDS Inputs): These are the four pairs of transmit parallel data
inputs. Each Differential pair has a 100Ω internal termination across the pair.
Serial Data Out (Differential CML Output): This is the serial differential data stream
output.
Double Data Rate Select (TTL Input): Selects either parallel data rate clock for normal
operation or one-half of parallel data rate clock for double data rate applications.
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SY87725L
LOOPBACK CONTROLS
Pin Number
Pin Name
Pin Description
16, 17
XMT_CNTRL0,
XMT_CNTRL1
Transmit Loop back Multiplexer Control (TTL Inputs): Two single-ended control lines
to control the data flow for remote loop back or normal serial data output.
4, 64
RCV_CNTRL0,
RCV_CNTRL1
Receive Loop back Multiplexer Control (TTL Inputs): Two single-ended control lines
to control the data flow for local loop back or recovered serial data into the 1:4
DeMUX.
TRANSLATOR SIGNALS
48
IN
52, 53
OUTP, OUTN
Signal from MAC to be translated (TTL Input)
Signal to Laser Diode Driver (CML Differential Output)
POWER PINS AND TEST PIN
13
Testb
Test Mode Pin: When held LOW activates test mode. (For factory use only, leave
open for normal operation.)
20
Test
Test Mode Pin: When held HIGH activates test mode. (For factory use only, must be
tied to GND for normal operation.).
8
VCCA
9
GNDA
Analog Ground pin and exposed pad must be connected to the same ground plane.
19, 38, 47, 54,
57
VCC
Core Power: Connect to +3.3V power supply. Bypass with 0.1µF//0.1µF low
ESR capacitors as close to VCC pins as possible.
21, 35, 58
GND, Exposed Pad
Core Ground: Ground pins and exposed pad must be connected to the same ground
plane.
51
VCCO
July 2007
Analog Power: Connect to +3.3V power supply. Bypass with 0.1µF//0.1µF low
ESR capacitors as close to VCCA pin as possible.
CML Output Power: Connect to +3.3V power supply. Bypass with
0.1µF//0.1µF low ESR capacitors as close to VCCO pin as possible.
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SY87725L
Functional Description
Transmit Section
The SY87725L is a fully integrated transceiver with an
integrated serial-to-4-bit DeMUX and 4-bit-to-serial
Multiplexer.
Synthesizer Function
Receive Section
Clock and Data Recovery Function
The Clock Recovery function includes a synthesizer that
generates a stable frequency based on the REFCLK
input. The REFCLK input can be either a differential
PECL input or a single-ended TTL input. It can also be
either 77.76MHz or 155.52MHz as selected by
REFFREQSEL. The synthesized frequency derived from
the REFCLK is within 1000ppm of the incoming serial
data rate and is used by the Clock and Data Recovery
(CDR) circuit to “train” to the correct frequency range.
This training function minimizes the acquisition time for
the CDR to lock onto the incoming data stream by
keeping the CDR frequency within close range of the
recovered clock in the case of loss of data.
The RCV_FSEL0 and RCV_FSEL1 inputs select the
receive data rate. For example, these inputs can be
used to select an OC-48, OC-24 or OC-12 data rate for
the serial data in, SIN. The typical input sensitivity of
SIN is 30mV.
The Clock Recovery function also generates CLKOUT2
that is controlled by the XMT_DDRSEL input for regular
or double data rate applications. If a clean, low-jitter
byte-rate clock is not available for CLKIN to the Transmit
Synthesizer, CLKOUT2 can be used as the reference
clock.
DeMUX Function
The SY87725L Transmit Synthesizer uses the divide-by4 parallel clock input or a divide-by-8 clock input when
double data rate is selected as a reference clock. The
XMT_FSEL0 and XMT_FSEL1 inputs select the TX data
rate. For example, these inputs can be used to select an
OC-24, OC-12 or OC-3 rate for the serial data out,
SOUT.
MUX Function
The 4-bit parallel data input is converted to a serial data
stream with a 4:1 multiplexer. The parallel-to-serial
conversion sequence is LSB first, i.e. DIN0 will be
shifted out first, followed by DIN1, etc.
Auto-Alignment Function
Because the 4-bit parallel data input can have an
arbitrary phase relationship with the transmit byte-rate
clock input (CLKIN), an auto-alignment function is
included in the transmit parallel-to-serial circuit.
The phase of the 4-bit parallel data is sampled and
compared with the phase of the incoming CLKIN. If the
clock and data are not in the proper phase relationship,
the phase is internally adjusted to insure that the data
will be sampled at the optimal time. This can result in a
variation of the latency between the parallel data in and
the serial data out (TDOUT) of up to three CLKIN clock
cycles.
Loopback Function
Two 3:1 multiplexers are provided to allow Local or
Remote Loopback.
The recovered serial data from the CDR is converted to
a 4-bit parallel word by a 1:4 de-multiplexer. The serialto-parallel conversion sequence is LSB first, i.e. first
serial bit in is DOUT0, second serial bit in is DOUT1,
etc. A RCV_SYNC pulse input is used to set the word
boundary of the 4-bit parallel word. A single pulse,
applied asynchronously for a minimum of two input clock
cycles to the RCV_SYNC input, causes the start bit of
conversion to occur one bit earlier.
The CLKOUT output is the parallel data rate clock to be
used with the DOUT parallel data from the DeMUX. It is
selectable by the RCV_DDRSEL input to be either at the
parallel data rate or one-half the parallel data rate for
double data rate applications.
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SY87725L
Frequency Selections
XMT_FSEL0
XMT_FSEL1
TX DATA RATE
0
0
155.52Mbps
1
0
622.08Mbps
0
1
1244.16Mbps
1
1
N/A
Table 1. Transmit Frequency Selection
RCV_FSEL0
RCV_FSEL1
RX DATA RATE
0
0
N/A
1
0
622.08Mbps
0
1
1244.16Mbps
1
1
2488.32Mbps
Table 2. Receive Frequency Selection
XMT_FSEL0
XMT_FSEL1
XMT_DDRSEL
CLKOUT2
0
0
0
38.88MHz
1
0
0
155.52MHz
0
1
0
311.04MHz
1
1
0
N/A
0
0
1
19.44MHz
1
0
1
77.76MHz
0
1
1
155.52MHz
1
1
1
N/A
Table 3. CLKOUT2 Frequency Selection
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SY87725L
RCV_CNTRL0
RCV_CNTRL1
XMT_DDRSEL
RCV_DDRSEL
DOUT
CLKOUT
0
0
0
0
N/A
N/A
1
0
0
0
DIN
CLKIN
0
1
0
0
SIN (bypass)
REFCLK/4
1
1
0
0
SIN (Recovered Data)
Recovered Clock/4
0
0
1
0
N/A
N/A
1
0
1
0
DIN
2 * CLKIN
0
1
1
0
SIN (bypass)
REFCLK/4
1
1
1
0
SIN (Recovered Data)
Recovered Clock/4
0
0
0
1
N/A
N/A
1
0
0
1
DIN
CLKIN/2
0
1
0
1
SIN (bypass)
REFCLK/8
1
1
0
1
SIN (Recovered Data)
Recovered Clock/8
0
0
1
1
N/A
N/A
1
0
1
1
DIN
CLKIN
0
1
1
1
SIN (bypass)
REFCLK/8
1
1
1
1
SIN (Recovered Data)
Recovered Clock/8
Table 4. Local Loopback Controls
XMT_CNTRL0
XMT_CNTRL1
SOUT
0
0
SIN (Bypass CDR)
1
0
Recovered Clock (from SIN)
0
1
Recovered Data (from SIN)
1
1
DIN (Normal Data Flow)
Table 5. Remote Loopback Controls
Loop Filter Components
R
C
Rcv_PLLS
1.2kΩ
1µF
Rcv_PLLR
390Ω
1µF
XMT_PLLS
1.2kΩ
1µF
Table 6. Synthesizer & Clock Recovery Loop Filter Values
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SY87725L
Absolute Maximum Ratings(1)
Operating Ratings(2)
Supply Voltage (VCC) ................................. –0.5V to + 4.6V
Input Voltage (VIN)............................................ –0.5V to VCC
LVDS Output Current (IOUT)...................................... ±10mA
CML Outputs
Voltage......................................... VCC-1.0V to VCC+0.5V
Current ................................................................. ±25mA
Lead Temperature (soldering, 20 sec.) .................. +260°C
Storage Temperature (TS) ........................–65°C to +150°C
Supply Voltage (VCC) ............................+3.15V to +3.45V
Ambient Temperature (TA) ..................... –40°C to +85°C
(3)
Package Thermal Resistance
®
MLF θ JB
Still-Air ............................................................ 35°C/W
®
MLF ψJB
Junction-to-Board ............................................ 7°C/W
DC Electrical Characteristics(4)
TA = –40°C to +85°C, unless noted.
Symbol
Parameter
VCC
Power Supply
ICC
Power Supply Current
Condition
Min
Typ
Max
Units
3.15
3.3
3.45
V
300
380
mA
Max
Units
No load, max. VCC
LVPECL Electrical Characteristics(4)
VCC = VCCA = VCCO = 3.3V ±5%; GND = GNDA = 0V; TA = –40°C to +85°C, unless otherwise noted.
Symbol
Parameter
Condition
Min
Typ
VIH
Input HIGH Voltage
VCC–1.165
VCC–0.88
V
VIL
Input LOW Voltage
VCC–1.810
VCC–1.475
V
Units
CML Output Electrical Characteristics(4)
VCC = VCCA = VCCO = 3.3V ±5%; GND = GNDA = 0V; TA = –40°C to +85°C, unless otherwise noted.
Symbol
Parameter
VOH
VOUT
VDIFF_OUT
Condition
Min
Typ
Max
Output HIGH Voltage
VCC–0.020
VCC–0.010
VCC
Output LOW Voltage
325
400
mV
Differential Output Voltage
650
800
mV
V
Notes:
1. Permanent device damage may occur if absolute maximum ratings are exceeded. This is a stress rating only and functional operation is not
implied at conditions other than those detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions
for extended periods may affect device reliability
2. The data sheet limits are not guaranteed if the device is operated beyond the operating ratings.
3. Package Thermal Resistance assumes exposed pad is soldered (or equivalent) to the devices most negative potential on the PCB. θ JB
assumes a 4-layer PCB. ψ JA in still air unless otherwise stated.
4. The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established.
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SY87725L
LVTTL/CMOS DC Electrical Characteristics(5)
VCC = VCCA = VCCO = 3.3V ±5%; GND = GNDA = 0V; TA = –40°C to +85°C, unless otherwise noted.
Symbol
Parameter
Max
Units
VIH
Input HIGH Voltage
Condition
Min
2.0
Typ
VCC
V
VIL
Input LOW Voltage
0
0.8
V
IIH
Input HIGH Current
-125
30
µA
IIL
Input LOW Current
VOH
Output HIGH Voltage
IOH = 100µA
VOL
Output LOW Voltage
IOl = 4mA
IOS
Output Short-Circuit Current
VOUT = 0V (max. 1sec.)
-300
µA
2.0
V
-100
0.5
V
-15
mA
LVDS DC Electrical Characteristics(5)
VCC = VCCA = VCCO = 3.3V ±5%; GND = GNDA = 0V, RL = 100Ω across output pair; TA = –40°C to +85°C, unless
otherwise noted.
Symbol
Parameter
VIN-Range
VIN
VDIFF-IN
Input Voltage Range
Input Voltage Swing
Differential Input Voltage Swing
Input Differential
Resistance
Output Voltage Swing
Differential Output Voltage
Swing
Output Common Mode
Voltage
Change in Output Common
Mode Voltage
RIN
VOUT
VDIFF-OUT
VOCM
ΔVOCM
Condition
Min
Typ
0
100
200
85
100
Max
Units
2.4
500
1000
V
mV
mV
115
Ω
325
mV
650
mV
1.125
1.275
V
-50
+50
mV
Note:
5. The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established.
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SY87725L
AC Electrical Characteristics(6)
VCC = VCCA = VCCO = 3.3V ±5%; GND = GNDA = 0V; TA = –40°C to +85°C, unless otherwise noted
Symbol
Parameter
SINMAX
SIN Maximum Data Rate
Condition
2.5
Min
Typ
Max
Gbps
SOUTMAX
SOUT Maximum Data Rate
1.25
Gbps
tACQ
Acquisition Lock Time
15
Frequency Difference, LFIN
shows Out-of-Lock
1000
tCPWH
REFCLK Pulse Width HIGH Time
tCPWL
REFCLK Pulse Width LOW Time
tSKEW
Parallel CLKOUT to Parallel Data
Out Skew
See “Figure 1”
tPR, tPF
CML Output Rise/Fall Time
(20% to 80%)
At full output swing
40
tLR, tLF
LVDS Output Rise/Fall Time
(20% to 80%)
At full output swing
100
tDC
CLKOUT, CLKOUT2 Duty Cycle
µs
ppm
2.5
ns
2.5
ns
-150
45
Units
+150
ps
70
100
ps
250
400
ps
55
%
Note:
6.
The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established.
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SY87725L
Timing Diagrams
Receive Timing
INTERNAL CLK
SIN
D0
D1
D2
D3
D4
D5
D6
D7
DOUT0
D0
D4
DOUT1
D1
D5
DOUT2
D2
D6
D3
D7
DOUT3
tSKEW
CLKOUT(Normal Mode)
CLKOUT(Half Rate Mode)
Figure 1. 1:4 Serial-to-Parallel Conversion
INTERNAL CLK
SIN
D0
D1
D2
D3
D4
D5
D6
D7
D8
SYNC
DOUT0
D0
D5
DOUT1
D1
D6
DOUT2
D2
D7
DOUT3
D3
D8
CLKOUT(Normal Mode)
CLKOUT(Half Rate Mode)
Figure 2. 1:4 Serial-to-Parallel Conversion with SYNC Pulse
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SY87725L
Transmit Timing
CLKIN (Normal Mode)
CLKIN (Half Rate Mode)
DIN0
D0
D4
DIN1
D1
D5
DIN2
D2
D6
DIN3
D3
D7
INTERNAL SERIAL CLK
SOUT
D0
D1
D2
D3
Figure 3. 4:1 Parallel-to-Serial Conversion
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SY87725L
Applications Sections
This section illustrates the various operating modes of
the SY87725L with the appropriate control signals.
Transmit Section
On the transmit side, the upstream data appears at
DIN in a 4-bit wide parallel format at 312.5Mbps and
exits at SOUT at a 1.25Gbps serial rate. The CLKIN
input is synchronous with the parallel data at DIN.
The loopback control signals RCV_CNTRL0,
RCV_CNTRL1, XMT_CNTRL0, XMT_CNTRL1 shown
in the table below select the clock and data paths for
normal operation. The RCV_DDRSel input is selecting
the CLKOUT to be in normal rate (÷ 4) mode.
Normal Data Flow
Receive Section
The diagram below shows the data paths in a normal
operating mode. In this case, downstream data at a
serial rate of 2.5Gbps is arriving at SIN and the
recovered 4-bit parallel data is exiting at DOUT at
625Mbps. This is not the double data rate mode
(DDR) so the parallel rate is the serial rate ÷ 4.
Figure 4. Normal Data Flow
RCV_CNTRL0
RCV_CNTRL1
XMT_CNTRL0
XMT_CNTRL1
RCV_DDRSEL
1
1
1
1
0
Table 7. Loopback and DDR Select Control Signals
RCV_FSEL0
RCV_FSEL1
XMT_FSEL0
XMT_FSEL1
1
1
0
1
Table 8. Transmit and Receive Frequency Select
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SY87725L
previous section, but utilizes CLKOUT2 to be used as
the transmit parallel clock. In this mode, CLKOUT2
must be externally connected to CLKIN as shown in
the block diagram below.
Normal Data Flow (Secondary Clock)
Receive Section
This mode is identical to the Normal Mode in the
Figure 5. Normal Data Flow
RCV_CNTRL0
RCV_CNTRL1
XMT_CNTRL0
XMT_CNTRL1
RCV_DDRSEL
1
1
1
1
0
Table 9. Loopback and DDR Select Control Signals
RCV_FSEL0
RCV_FSEL1
XMT_FSEL0
XMT_FSEL1
1
1
0
1
Table 10. Transmit and Receive Frequency Select
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SY87725L
Remote Loopback Mode 00
This is the simplest of the loopback modes as its main
purpose is to verify if the link is OK.
It is possible to combine this with Local Loopback
modes; however, it is intended to be a stand-alone
test mode.
Figure 6. Remote Loopback Data Flow
XMT_CNTRL0
XMT_CNTRL1
0
0
Table 11. Loopback Control Signals
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SY87725L
looping back the recovered clock or data.
The REFCLK is necessary for normal operation of the
CDR.
Remote Loopback Modes 01 and 10
These modes verify the operation of the CDR by
Figure 7. Remote Loopback Recovered Clock Flow
XMT_CNTRL0
XMT_CNTRL1
1
0
Table 12. Loopback Control Signals
Figure 8. Remote Loopback Recovered Data Flow
XMT_CNTRL0
XMT_CNTRL1
0
1
Table 13. Loopback Control Signals
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SY87725L
CDR Bypass Mode
This mode bypasses the CDR and feeds SIN directly
into the DeMUX. Because the CDR is bypassed, there
is no recovered clock in this mode. The RefClk is fed
directly into the DeMUX and is the serial rate clock.
Therefore, in this mode only, the RefClk is not used by
the Synthesizer but will be at the same frequency as
the SIN data rate. In this mode the maximum SIN data
rate is 155.52Mbps and the matching RefClk
frequency will be 155.52MHz. The Data at SIN is
sampled at the falling edge of REFCLK.
Figure 9. CDR Bypass Mode
RCV_CNTRL0
RCV_CNTRL1
0
1
Table 14. Loopback Control Signals
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hbwhelp@micrel.com or (408) 955-1690
Micrel, Inc.
SY87725L
Local Loopback Mode
This mode loops the serial data out of the Mux back to
the serial input of the DeMux. This allows the
operation of the Mux and DeMux to be verified
through the parallel interface.
Figure 10. Local Loopback Data Flow
RCV_CNTRL0
RCV_CNTRL1
1
0
Table 15. Loopback Control Signals
July 2007
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SY87725L
Package Information
64-Pin EPAD-TQFP (T64-1)
MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA
TEL +1 (408) 944-0800 FAX +1 (408) 474-1000 WEB http:/www.micrel.com
The information furnished by Micrel in this data sheet is believed to be accurate and reliable. However, no responsibility is assumed by Micrel for
its use. Micrel reserves the right to change circuitry and specifications at any time without notification to the customer.
Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a
product can reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for
surgical implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant
injury to the user. A Purchaser’s use or sale of Micrel Products for use in life support appliances, devices or systems is a Purchaser’s own risk
and Purchaser agrees to fully indemnify Micrel for any damages resulting from such use or sale.
© 2006 Micrel, Incorporated.
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