SY88063CL
1.0625G to 12.5G Limiting Post Amplifier
with Digital Offset Correction
General Description
The SY88063CL limiting post amplifier is designed for use
in fiber-optic receivers for multi-rate applications from
1.0625Gbps to 12.5Gbps.
The SY88063CL contains a high-bandwidth, highsensitivity input stage with user-programmable, wide-range
SD assert/LOS de-assert threshold levels, which enables
optimized system reach. Typically, 4dB of electrical
hysteresis is provided to minimize LOS or SD chattering
caused by noisy input signals. A logic level control pin is
provided to enable user selection of an open-collector,
TTL-compatible LOS or SD status indication signal with an
external 5kΩ to 10kΩ pull-up resistor.
The SY88063CL provides fast SD assert and LOS deassert times over the entire differential input voltage range
of 5mVPP to 1800mVPP.
The SY88063CL input stage also provides a userselectable digital offset correction (DOC) function to
automatically compensate for internal device offsets in the
high-speed data path.
The SY88063CL provides integrated 50Ω input and output
impedances to optimize the high-speed signal paths and
reduce component count. A TTL-compatible JAM input is
provided to enable a SQUELCH function by feeding back
the LOS or SD signal. The JAM input disables only the
post amplifier output.
The SY88063CL operates from a single +3.3V power
supply, over temperatures ranging from –40°C to +85°C.
Datasheets and support documentation are available on
Micrel’s web site at: www.micrel.com.
Features
• Multi-rate operation from 1.0625Gbps to 12.5Gbps
• Selectable digital offset correction for internal offset
compensation in the high-speed data path
• Wide differential input range (5mVPP to 1800mVPP)
• Wide SD de-assert or LOS assert threshold range
− 3mVPP to 30mVPP
− 4dB typical electrical hysteresis
• Fast SD assert and LOS de-assert times
− 75ns typical; 120ns maximum
• Selectable LOS or SD status signal indicator
• TTL-compatible JAM input with internal pull-up
• Low-noise CML data inputs with integrated 50Ω
termination impedance to internal reference VREF
• Low-noise CML data outputs with integrated 50Ω
termination impedance
− 25ps typical rise/fall times
• Wide range power supply: 3.3V ±10%
• Industrial temperature range: −40°C to +85°C
• Available in a tiny 3mm × 3mm QFN package
Applications
•
•
•
•
•
•
Asymmetrical/Symmetrical 10GEPON
Asymmetrical/Symmetrical XGPON
10Gigabit Ethernet
8Gbps and 10Gbps Fibre Channel
SONET OC192/SDH STM64
WDM/DWDM systems
Markets
•
•
•
•
•
•
PON/FTTx
Datacom/Enterprise
Storage area networks
High-performance computing
Telecom
8G+ Optical transceivers
.
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (408) 944-0800 • fax + 1 (408) 474-1000 • http://www.micrel.com
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SY88063CL
Typical Application Circuit
Ordering Information
Part Number
SY88063CLMG
(1)
SY88063CLMG TR
Package Type
Operating Range
Package Marking
Lead Finish
3mm × 3mm QFN-16
Industrial
063C with Pb-Free bar-line indicator
NiPdAu Pb-Free
3mm × 3mm QFN-16
Industrial
063C with Pb-Free bar-line indicator
NiPdAu Pb-Free
Note:
1. Tape and reel.
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Pin Configuration
16-Pin 3mm × 3mm QFN
(Top View)
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SY88063CL
Pin Description
Pin #
Pin Name
Pin Type
1
GND
Negative Supply
Rail
2
RXIN+
High-Speed
Data Input
Differential Noninverting Data Input. LVPECL/CML compatible. AC-coupled
with 10nF (high-frequency, low-ESR capacitor is recommended).
Internally terminated with 50Ω to VCC – 0.9V. AC-coupled only.
3
RXIN−
High-Speed
Data Input
Differential Inverting Data Input. LVPECL/CML-compatible. AC-coupled with
10nF (high-frequency, low-ESR capacitor is recommended).
Internally terminated by 50Ω to VCC – 0.9V. AC-coupled only.
4
GND
Negative Supply
Rail
5
NC
No Connect
No Connect. Do not connect to logic circuits or power supply rails.
6
NC
No Connect
No Connect. Do not connect to logic circuits or power supply rails.
7
SD/LOS
Open Collector
Logic Output
Functional Description
Negative Supply Rail. Connect to the PCB negative power supply plane that is
also connected to the ePAD.
Negative Supply Rail. Connect to the PCB negative power supply plane that is
also connected to the ePAD.
Output Status Indicator. Loss-of-signal (LOS) or signal detect (SD) open
collector output externally terminated with 5kΩ to 10kΩ resistor to VCC. TTL
compatible.
LOS = High when RXIN± amplitude falls below the threshold set at the
SD/LOSLVL pin.
SD = Low when RXIN± amplitude falls below the threshold set at the
SD/LOSLVL pin.
Analog control input. Sets the trigger threshold for the LOS or SD status
indicator signals.
If SD/LOS_SEL = High (LOS selected), connect a resistor from the
SD/LOSLVL pin (loss of signal threshold level) to VCC to adjust the
LOS_Assert threshold for the RXIN± data inputs.
If SD/LOS_SEL = Low (SD selected), connect a resistor from the SD/LOSLVL
pin (signal detect threshold level) to VCC to adjust the SD_De-assert threshold
for the RXIN± data inputs.
8
SD/LOSLVL
Analog Input
9, 12
VCC
Positive Supply
Rail
10
RXOUT−
High-Speed
Data Output
Differential inverting data output. CML compatible and internally terminated by
50Ω to VCC. Can be AC- or DC-coupled to downstream devices.
11
RXOUT+
High-Speed
Data Output
Differential noninverting data output. CML compatible and internally
terminated by 50Ω to VCC. Can be AC- or DC-coupled to downstream devices.
13
TEST
Test Pin
Factory test pin. For factory use only. Do not connect to logic circuits or power
supply rails.
Logic Level
Input
Input control signal. TTL-compatible logic input signal to select LOS or SD as
the output signal. Internal ~18kΩ pull-up to VCC.
Default = High (NC): LOS selected – normal operation
LOS/SD_SEL = Low: SD selected and JAM operation is inverted
Logic Level
Input
Input control signal. TTL-compatible input signal that enables or disables the
RXOUT± output signals. Internal 27kΩ pull-up resistor to VCC. Can be
connected to SD/LOS to form a SQUELCH function.
When SD/LOS_SEL = High
Default = High and RXOUT± outputs are disabled.
Low = RXOUT± outputs are enabled
Operation is inverted when SD/LOS_SEL = Low and SD is selected.
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SD/LOS_SEL
15
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JAM
Positive power supply input. Bypass with a 0.1µF capacitor in parallel with a
0.01µF low-ESR capacitor to GND as close as possible to the VCC pin.
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Pin #
SY88063CL
Pin Name
Pin Type
16
DOC_EN
Logic Level
Input
ePAD
GND
Negative Supply
Rail
September 6, 2013
Functional Description
Input Control Signal. TTL-compatible logic input signal that enables or
disables the digital offset correction (DOC) circuit.
Default:
DOC_EN = High = Enable with internal 18kΩ pull-up to VCC if not connected to
an external logic low or high signal.
DOC_EN = Low disables the digital offset correction function.
Toggling the DOC_EN signal from high to low to high will cause a reset of the
DOC circuitry and initiate a new DOC routine to lock in new DOC values.
Note: Digital offset correction is not applied to large input signals.
Exposed Thermal Pad. Must be soldered to PCB plane connected to the
negative supply rail. The recommended via array is needed to remove heat
from the device.
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SY88063CL
Absolute Maximum Ratings(2)
Operating Ratings(3)
Supply Voltage (VCC) ......................................... 0V to +4.0V
Input Voltage (RXIN±) .............................. VCC – 1.5V to VCC
CML Output Voltage (VOUT)……....VCC − 1.0V to VCC + 0.5V
JAM Voltage ........................................................... 0 to VCC
SD/LOSLVL Voltage ................................ VCC – 1.3V to VCC
Lead Temperature (soldering, 20s) ............................ 260°C
Storage Temperature (Ts) ......................... –65°C to +150°C
Supply Voltage (VCC) .................................... +3.0V to +3.6V
Ambient Temperature (TA) .......................... –40°C to +85°C
Junction Temperature (TJ) ........................ –40°C to +120°C
(4)
Package Thermal Resistance ........ 3mm × 3mm QFN-16
(θJA) Still-air ........................................................ 60°C/W
(ψJB) ................................................................... 33°C/W
DC Electrical Characteristics
VCC = 3.0 to 3.6V; TA = –40°C to +85°C, typical values at VCC = 3.3V, TA = 25°C.
Symbol
Parameter
Condition
Min.
Typ.
Max.
Units
ICC
Power Supply Current
Note 5
60
75
mA
SD/LOSLVL
SD or LOS Threshold Voltage
VCC
V
VOH
RXOUT±
High Voltage
VCC − 0.020
VCC − 0.005
VCC
V
VOL
RXOUT±
Low Voltage
VCC − 0.400
VCC − 0.350
VCC − 0.300
V
VOS_DOC_ON
Differential Output Offset
Z0
Single-Ended Output
Impedance
45
50
55
Ω
ZI
Single-Ended Input
Impedance
45
50
55
Ω
VCC − 1.3
Digital Offset Correction = ON
±10
mV
Notes:
2. Permanent device damage may occur if absolute maximum ratings are exceeded. This is a stress rating only and functional operation is not implied
at conditions other than those detailed in the operational sections of this datasheet. Exposure to absolute maximum ratings conditions may affect
device reliability.
3. The datasheet limits are not guaranteed if the device is operated beyond the recommended operating conditions.
4. Package thermal resistance assumes that the exposed pad is soldered (or equivalent) to the devices most negative potential on the PCB. ψJB and
θJA assumes still air and a 4-layer PCB, unless otherwise stated. It also assumes that the recommended via pattern and via sizes on the PCB are
used.
5. DOC is enabled, outputs RXOUT± are loaded with external 50Ω loads, and the outputs are enabled.
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TTL DC Electrical Characteristics
VCC = 3.0 to 3.6V; TA = –40°C to +85°C, typical values at VCC = 3.3V, TA = 25°C.
Symbol
Parameter
VIH
JAM, DOC_EN, SD/LOS_SEL
Input High Voltage
VIL
JAM, DOC_EN, SD/LOS_SEL
Input Low Voltage
IIH
JAM, DOC_EN, SD/LOS_SEL
Input High Current
IIL
JAM, DOC_EN, SD/LOS_SEL
Input Low Current
VIN = 0.4V
−0.3
mA
VOH
SD or LOS Output High Level
Sourcing 100µA
2.4
V
VOL
SD or LOS Output Low Level
Sinking 2mA
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Condition
Min.
Typ.
Max.
2.0
V
0.8
VIN = 2.7V
20
VIN = VCC
100
0.4
7
Units
V
µA
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AC Electrical Characteristics
VCC = 3.3V ±10%, TA = –40°C to +85°C. Typical values at VCC = 3.3V, TA = 25°C; RLOAD = 50Ω to VCC.
Symbol
Parameter
Condition
tr , tf
Output Rise/Fall Time
(20% to 80%)
Typ.
Max.
Units
Note 6
25
40
ps
Deterministic
Note 7
10
Random
Note 8
1
VID_11.3G
Differential Input Voltage Swing
Note 9. See Figure 1.
5
1800
mVPP
VID_12.5G
Differential Input Voltage Swing
Note 9. See Figure 1.
10
1800
mVPP
VOD
Differential Output Voltage Swing
Note 6
600
700
800
mVPP
tLOS_D; tLOS_A
tSD_D; tSD_A
LOS De-assert, LOS Assert Time
SD De-assert, SD Assert Time
Note 10
75
120
ns
LOSAL_20k
Low LOS Assert Level
RLOSLVL = 20kΩ, Note 9
3
mVPP
LOSDL_20k
Low LOS De-assert Level
RLOSLVL = 20kΩ, Note 9
5
mVPP
HYSL_20k
Low LOS Hysteresis
RLOSLVL = 20kΩ, Note 11
LOSAM_10k
Medium LOS Assert Level
RLOSLVL = 10kΩ, Note 9
4.5
mVPP
LOSDM_10k
Medium LOS De-assert Level
RLOSLVL = 10kΩ, Note 9
7.3
mVPP
HYSM_10k
Medium LOS Hysteresis
RLOSLVL = 10kΩ, Note 11
LOSAH1_1k
High1 LOS Assert Level
RLOSLVL = 1kΩ, Note 9
18.6
mVPP
LOSDH1_1k
High1 LOS De-assert Level
RLOSLVL = 1kΩ, Note 9
28.3
mVPP
HYSH1_1k
High1 LOS Hysteresis
RLOSLVL = 1kΩ, Note 11
LOSAH2_100
High2 LOS Assert Level
RLOSLVL = 100Ω, Note 9
29.7
mVPP
LOSDH2_100
High2 LOS De-assert Level
RLOSLVL = 100Ω, Note 9
44.6
mVPP
HYSH2_100
High2 LOS Hysteresis
RLOSLVL = 100Ω, Note 11
AV(Diff)_063C
Differential Voltage Gain
S21_063C
Single-Ended Small-Signal Gain
tDOC_DELAY
tDOC_LOCK
tJITTER
Min.
2
2
2
2
4.4
4.1
3.6
3.5
ps
6
6
6
6
dB
dB
dB
dB
44
dB
38
dB
DOC Delay Time
15
µs
DOC Lock Time
150
µs
32
Note:
6. Amplifier is in limiting mode. Input is a 200MHz square wave.
7. Deterministic jitter is measured using 10Gbps K28.5 pattern, VID = 20mVPP.
8. Random jitter is measured using 10Gbps K28.7 pattern, VID = 20mVPP.
9. See “Typical Operating Characteristics” for a graph showing how to choose a particular RLOSLVL for a particular LOS assert and its associated deassert amplitude.
10. In real world applications, the LOS de-assert/assert time can be strongly influenced by the RC time constant of the AC-coupling capacitor and the
50Ω input termination. To keep this time low, use a decoupling capacitor with the lowest value that is allowed by the data rate and the number of
consecutive identical bits in the application (typical values are in the range of 0.001µF to 0.1µF).
11. This specification defines electrical hysteresis as 20log (LOS de-assert/LOS assert). The ratio between optical hysteresis and electrical hysteresis is
found to vary between 1.5 and 2, depending on the level of received optical power and ROSA characteristics.
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Typical Operating Characteristics
VCC = 3.3V, TA = 25°C, RLOAD = 50Ω to VCC, unless otherwise stated.
LOS Hysteresis
vs. LOSLVL Resistor
100
6
5
HYSTERESIS (dB)
INPUT SIGNAL AMPLITUDE (mVPP)
VID (LOS Assert) and
VID (LOS De-Assert) vs. RSD/LOSLVL
10
4
3
2
1
1
10
100
1000
10000
0
100000
SD/LOSLVL RESISTOR (Ω)
10
100
1000
10000
100000
SD/LOSLVL RESISTOR (Ω)
Linear Mode 10.3G Output with 5mVPP Differential Input Signal
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SY88063CL
Functional Block Diagram
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Functional Description
SD/LOSLVL and de-asserts low otherwise. LOS can be
fed back to the JAM input to perform the SQUELCH
function and to maintain output stability under a LOS
condition. JAM de-asserts the true output signal low
without removing the input signals. Typically, 4dB LOS
hysteresis is provided to prevent chattering.
The SY88063CL is a high-sensitivity, high-bandwidth
limiting post amplifier. It operates from a single +3.3V
power supply across the entire industrial temperature
range of –40°C to +85°C.
Signals with data rates from 1.0625Gbps to 12.5Gbps
and amplitudes as small as 5mVpp are supported.
Figure 1 shows the allowed input voltage swing.
When SD/LOS_SEL is used to select the SD output on
the SD/LOS pin, SD is asserted when the differential
input signal amplitude exceeds the level set by the
SD/LOSLVL resistor. The JAM operation is inverted when
SD is selected.
Signal Detect/Loss-of-Signal Level Setting
A programmable SD/LOS level set pin (SD/LOSLVL) sets
the threshold of the input amplitude detection.
Connecting an external resistor between VCC and
SD/LOSLVL sets the threshold voltage. This voltage
ranges from VCC to VCC − 1.3V. The external resistor
creates a voltage divider between VCC and VCC − 1.3V, as
shown in Figure 5.
Hysteresis
The SY88063CL provides typically 4dB LOS electrical
hysteresis, which is defined as 20log (VINLOS_De-Assert ÷
VINLOS_Assert). Because the relationship of the voltage
output of the ROSA to optical power at its input is linear,
the optical hysteresis is typically half of the electrical
hysteresis reported in the datasheet. In practice the ratio
between electrical and optical hysteresis is found to be
between 1.5 and 1.8. Thus, 4dB electrical hysteresis
corresponds to an optical hysteresis within the range of
2dB to 2.4dB.
Figure 1. VIS and VID Definition
The SY88063CL has a selectable SD or LOS status
output signal that can be fed back to the JAM input to
perform the SQUELCH function for output stability if there
is no signal at the input. SD/LOSLVL sets the sensitivity
of the input amplitude detection.
The SY88063CL has a user-selectable, integrated digital
offset correction function to cancel internally generated
output offsets.
Digital Offset Correction (DOC)
The digital offset correction (DOC) circuit compensates
for the inherent offsets found in high-gain amplifier
circuits and minimizes the offset seen at the outputs.
DOC is a user-selectable feature using the DOC_EN pin
as defined in the “Pin Description” table.
Input Amplifier/Buffer
Figure 2 shows a simplified schematic of the input stage.
The high sensitivity of the input amplifier allows signals
as small as 5mVpp to be detected and amplified. The
input amplifier allows input signals as large as 1800mVpp.
Input small signals are amplified with a typical 44dB
differential voltage gain.
Conventional analog offset compensation techniques
may be susceptible to drift from long continuous identical
digit (CID) patterns. They can also add additional cost
due to the extra DAC and manufacturing setup time
needed to optimize each individual module. The
SY88063CL avoids both of these issues and provides a
performance/cost optimized solution.
Output Buffer
The SY88063CL CML output buffer is designed to drive
50Ω impedance transmission lines and is internally
terminated with 50Ω to VCC. Figure 3 shows a simplified
schematic of the output stage.
The DOC circuitry automatically detects any internal
device offsets and locks the correction values but does
not apply offset correction to large input signals.
Signal Detect/Loss-of-Signal (SD/LOS)
The
SY88063CL
generates
a
user-selectable
(SD/LOS_SEL pin) signal detect (SD) or loss-of-signal
(LOS) open-collector TTL output, as shown in Figure 4.
LOS is used to determine whether the input amplitude is
too small to be considered as a valid input. LOS asserts
high if the input amplitude falls below the threshold set by
September 6, 2013
The DOC is enabled by default unless DOC_EN is pulled
low by an external logic level signal. It can be reset by
toggling the DOC_EN pin high-to-low-to-high. The DOC
reset routine typically completes in 200µs.
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Functional Circuit Structures
Figure 2. Input Structure
Figure 3. Output Structure
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Functional Circuit Structures (Continued)
Figure 4. SD/LOS Output Structure
Figure 5. SD/LOSLVL Setting Circuit
Related Product and Support Documentation
Document Number
Title
Application Note Link
AN-45
Notes on Sensitivity and Hysteresis
in Micrel Post Amplifiers
www.micrel.com/_PDF/HBW/App-Notes/an-45.pdf
SY88053CL_63CL_EB
SY88053CL/SY88063CL
Evaluation Board
http://www.micrel.com/_PDF/Eval-Board/SY88053CL_63CL_EB.pdf
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SY88063CL
Package Information(12)
16-Pin (3mm × 3mm) QFN-16
Note:
12. Package information is correct as of the publication date. For updates and most current information, go to www.micrel.com.
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MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA
TEL +1 (408) 944-0800 FAX +1 (408) 474-1000 WEB http://www.micrel.com
Micrel makes no representations or warranties with respect to the accuracy or completeness of the information furnished in this data sheet. This
information is not intended as a warranty and Micrel does not assume responsibility for its use. Micrel reserves the right to change circuitry,
specifications and descriptions at any time without notice. No license, whether express, implied, arising by estoppel or otherwise, to any intellectual
property rights is granted by this document. Except as provided in Micrel’s terms and conditions of sale for such products, Micrel assumes no liability
whatsoever, and Micrel disclaims any express or implied warranty relating to the sale and/or use of Micrel products including liability or warranties
relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right.
Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product
can reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical
implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. A
Purchaser’s use or sale of Micrel Products for use in life support appliances, devices or systems is a Purchaser’s own risk and Purchaser agrees to fully
indemnify Micrel for any damages resulting from such use or sale.
© 2013 Micrel, Incorporated.
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