SY89297U
2.5V/3.3V, 3.2 Gbps, Precision CML
Dual-Channel Programmable Delay
Features
General Description
• Dual-Channel, Programmable Delay Line
• Serial Programming Interface (SDATA, SCLK,
SLOAD)
• Guaranteed AC Performance over Temperature
and Voltage:
- >3.2 Gbps/1.6 GHz fMAX
• Programming Accuracy:
- Linearity: –15 ps to +15 ps INL
- Monotonic: –5 ps to +25 ps
- Resolution: 5 ps Programming Increments
• Low-Jitter Design: 1 psRMS Typical Random Jitter
• Programmable Delay Range: 5 ns Delay Range
• Cascade Capability for Increased Delay
• Flexible Voltage Operation:
- VCC = 2.5V ±5% or 3.3V ±10%
• Industrial Temperature Range: –40°C to +85°C
• Available in 24-Lead (4 mm x 4 mm) QFN
Package
The SY89297U is a DC-3.2 Gbps programmable,
two-channel delay line. Each channel has a delay
range from 2 ns to 7 ns (5 ns delta delay) in
programmable increments as small as 5 ps. The delay
step is extremely linear and monotonic over the entire
programming range, with 15 ps INL over temperature
and voltage.
Applications
Package Type
SCLK
SDATA
SOUT
GND
VCC
24
23
22
21
20
19
QA
/INA
17
/QA
VTA
3
16
VCC
VTB
4
15
VCC
INB
5
14
QB
/INB
6
13
/QB
8
9
10
11
12
VCC
7
GND
18
2
/ENA
1
/ENB
INA
GND
Automated Test Equipment
Digital Radio and Video Broadcasting
Closed Caption Encoders/Decoders
Test and Measurement
SLOAD
SY89297U
24-Lead 4x4 QFN (M)
Clock De-Skewing
Timing Adjustments
Aperture Centering
System Calibration
Markets
•
•
•
•
The SY89297U provides two independent 3.2 Gbps
delay lines in an ultra-small 4 mm x 4 mm, 24-pin QFN
package. For other delay line solutions, consider the
SY89295U and SY89296U single-channel delay lines.
Evaluation boards are available for all these parts.
VREF-AC
•
•
•
•
The delay varies in discrete steps based on a serial
control word provided by the 3-pin serial control
(SDATA, SCLK, and SLOAD). The control word for
each channel is 10-bits. Both channels are
programmed through a common serial interface. For
increased delay, multiple SY89297U delay lines can be
cascaded together.
United States Patent No. RE44,134
2018 Microchip Technology Inc.
DS20005835A-page 1
SY89297U
Functional Block Diagram
INA
CML
10 Bits
VTA
QA
5ps/Step = 5ns
/QA
/INA
/ENA
(TTL/CMOS)
Serial
Interface
{
SLOAD
SDATA
SCLK
LATCH B
D9B
...
LATCH A
D1B D0B D9A
...
20 Bits
D1A D0A
SOUT
TTL
Open-Collector
Resistor Pull-Up
CML
INB
QB
VTB
5ps/Step = 5ns
/QB
10 Bits
/INB
/ENB
VREF-AC
DS20005835A-page 2
2018 Microchip Technology Inc.
SY89297U
1.0
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings †
Supply Voltage (VCC) ................................................................................................................................ –0.5V to +4.0V
Input Voltage (VIN) ....................................................................................................................................... –0.5V to VCC
CML Output Voltage (VOUT) ..................................................................................................... VCC – 1.0V to VCC + 0.5V
Current (Source or Sink Current on VT) ................................................................................................................ ±70 mA
Input Current (Source or Sink Current on IN, /IN) ................................................................................................. ±35 mA
Current (VREF, Source or Sink Current on VREF-AC) (Note 1) ..............................................................................±0.5 mA
Operating Ratings ‡
Supply Voltage (VCC for TA = –40°C to +85°C)................................................................................. +2.375V to +2.625V
Supply Voltage (VCC for TA = –40°C to +75°C)......................................................................................... +3.0V to +3.6V
† Notice: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device.
This is a stress rating only and functional operation of the device at those or any other conditions above those indicated
in the operational sections of this specification is not intended. Exposure to maximum rating conditions for extended
periods may affect device reliability.
‡ Notice: The device is not guaranteed to function outside its operating ratings.
Note 1: Due to the limited drive capability, use for input of the same package only.
TABLE 1-1:
DC ELECTRICAL CHARACTERISTICS
Electrical Characteristics: TA = –40°C to +85°C, Channels A and B, unless noted. Note 1
Parameter
Power Supply Voltage Range
Symbol
VCC
Min.
Typ.
Max.
2.375
2.5
2.625
3.0
3.3
3.6
3.0
3.3
3.6
Units
Conditions
TA = –40°C to +85°C
V
TA = –40°C to +75°C
TA = –40°C to +85°C, Airflow =
500 lfpm
Maximum VCC, Both Channels
Combined, Output Load Included
Power Supply Current
ICC
—
195
250
mA
Input Resistance
(IN-to-VT, /IN-to-VT)
RIN
45
50
55
Ω
—
Differential Input Resistance
(IN-to-/IN)
RDIFF_IN
90
100
110
Ω
—
Input HIGH Voltage (IN, /IN)
VIH
1.2
—
VCC
V
—
V
—
Input LOW Voltage (IN, /IN)
VIL
0
—
VIH –
0.1
Input Voltage Swing (IN, /IN)
VIN
0.1
—
1.0
V
See Figure 5-1
Differential Input Voltage
Swing (|IN - /IN|)
VDIFF_IN
0.2
—
—
V
See Figure 5-2
Output Reference Voltage
VREF-AC
VCC –
1.3
VCC –
1.2
VCC –
1.1
V
—
VT_IN
—
—
1.28
V
—
Voltage from Input to VT
Note 1:
The circuit is designed to meet the DC specifications show in the table above after thermal equilibrium has
been established.
2018 Microchip Technology Inc.
DS20005835A-page 3
SY89297U
TABLE 1-2:
CML OUTPUTS DC ELECTRICAL CHARACTERISTICS
Electrical Characteristics: VCC = +2.5V +5% or +3.3V ±10%, RL = 100Ω across the outputs; TA = –40°C to +85°C,
unless otherwise stated. Note 1
Parameter
Symbol
Min.
Typ.
Max.
Units
Output HIGH Voltage
VOH
VCC –
0.02
VCC –
0.01
VCC
V
Output Voltage Swing
Conditions
RL = 50Ω to VCC
VOUT
325
400
—
mV
See Figure 5-1
Differential Output Voltage
Swing
VDIFF_OUT
650
800
—
mV
See Figure 5-2
Output Source Impedance
ROUT
45
50
55
Ω
Note 1:
—
The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium
has been established.
TABLE 1-3:
LVTTL/CMOS DC ELECTRICAL CHARACTERISTICS
Electrical Characteristics: VCC = 2.5V ±5% or 3.3V ±10%; TA = –40°C to +85°C; unless otherwise stated. Note 1
Parameter
Symbol
Min.
Typ.
Input High Voltage
VIH
2.0
Input Low Voltage
VIL
—
Input High Current
IIH
Input Low Current
IIL
Output LOW Voltage
Output High Leakage Current
Note 1:
VOL
Max.
Units
Conditions
—
—
V
—
0.8
V
—
—
—
150
µA
VIH = VCC
—
—
50
µA
VIL = 0.8V
—
—
0.55
V
SOUT Pin; IOL = 1 mA
—
—
100
µA
SOUT = VCC
—
The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium
has been established.
DS20005835A-page 4
2018 Microchip Technology Inc.
SY89297U
TABLE 1-4:
AC ELECTRICAL CHARACTERISTICS
Electrical Characteristics: TA = –40°C to +85°C, Channels A and B, unless otherwise stated. Note 1
Parameter
Maximum Operating
Frequency
Propagation Delay
Programmable Range
Step Delay
Integral Non-Linearity
Set-Up Time
Hold Time
2018 Microchip Technology Inc.
Symbol
fMAX
tpd
tRANGE
∆t
INL
tS
tH
Min.
Typ.
Max.
Units
Conditions
1.6
—
—
GHz
Clock: VOUT Swing >200 mVpk
3.2
—
—
Gbps
NRZ Data
1000
—
2000
5500
—
7500
1000
—
2500
IN to Q; D[0-9] = 0
IN to Q; D[0-9] = 1023
ps
/EN to Q: D[0-9] = 0; VTH = VCC/2
SDATA to SOUT (D0-D9 = Low),
No load
2000
—
4500
4150
5115
—
—
5
—
D0 High
—
10
—
D1 High
—
20
—
D2 High
—
40
—
D3 High
—
80
—
D4 High
—
160
—
D5 High
—
320
—
—
640
—
D7 High
—
1280
—
D8 High
—
2560
—
D9 High
—
5115
—
D0-D9 High
–5
—
25
Monotonic
–15
—
15
400
—
—
400
—
—
300
—
—
300
—
—
–100
—
—
200
—
—
ps
ps
ps
tpd(MAX) – tpd(MIN)
D6 High
Note 2
SDATA to SCLK
ps
SCLK to SLOAD, Note 3
/EN to IN, Note 4
SLOAD to SCLK, Note 5
ps
IN to /EN, Note 6
SCLK to SDATA
DS20005835A-page 5
SY89297U
TABLE 1-4:
AC ELECTRICAL CHARACTERISTICS (CONTINUED)
Electrical Characteristics: TA = –40°C to +85°C, Channels A and B, unless otherwise stated. Note 1
Parameter
Symbol
Min.
Pulse Width
tPW
1000
—
—
ps
SLOAD
tR
800
—
—
ps
/EN to IN, Note 7
—
—
2
psRMS
Note 8
tJITTER
—
—
20
psPP
Note 9
—
—
2
psRMS
Note 10
Output Rise/Fall Time
tr/tf
30
55
80
ps
20% to 80% (Q)
Duty Cycle
—
45
—
55
%
Input frequency = 1.6 GHz
Release Time
Cycle-to-Cycle Jitter
Total Jitter
Random Jitter
Typ.
Max.
Units
Conditions
High frequency AC electricals are guaranteed by design and characterization.
INL (Integral Non-Linearity) is defined from its corresponding point on the ideal delay versus D[9:0] curve
as the deviation from its ideal delay. The maximum difference is the INL. Theoretical Ideal Linearity (TIL) =
(measured maximum delay – measured minimum delay) ÷ 1023. INL = measured delay – (measured minimum delay + (step number x TIL)).
3: SCLK has to transition L-H a setup time before the SLOAD H-L transition to ensure the valid data is properly latched. See Figure 4-2.
4: This setup time is the minimum time that /EN must be asserted prior to the next transition of IN / /IN to prevent an output response greater than ±75 mV to that IN or /IN transition. See Figure 4-3.
5: SCLK has to transition L-H a hold time after the SLOAD H-L transition to ensure that the valid data is properly latched before starting to load new data. See Figure 4-2.
6: This hold time is the minimum time that /EN must remain asserted after a negative going transition of IN to
prevent an output response greater than ±75 mV to the IN transition. See Figure 4-3.
7: This release time is the minimum time that /EN must be de-asserted prior to the next IN / /IN transition to
affect the propagation delay of IN to Q less than 1 ps. See Figure 4-3.
8: Cycle-to-cycle jitter definition: The variation of periods between adjacent cycles over a random sample of
adjacent cycle pairs Tjitter_cc = Tn – Tn+1, where T is the time between rising edges of the output signal.
9: Total jitter definition: With an ideal clock input, no more than one output edge in 1012 output edges will
deviate by more than the specified peak-to-peak jitter value.
10: Random jitter definition: Jitter that is characterized by a Gaussian distribution, unbounded and is quantified by its standard deviation and mean. Random jitter is measured with a K28.7 comma detect pattern,
measured at 1.5 Gbps.
Note 1:
2:
DS20005835A-page 6
2018 Microchip Technology Inc.
SY89297U
TEMPERATURE SPECIFICATIONS (Note 1)
Parameters
Sym.
Min.
Typ.
Max.
Units
Junction Operating Temperature
TJ
—
—
+125
°C
Conditions
Temperature Ranges
—
Storage Temperature Range
TS
–65
—
+150
°C
—
Lead Temperature
—
—
—
+260
°C
Soldering, 20s
Ambient Temperature Range
TA
–40
—
+85
°C
—
JA
—
43
—
°C/W
Still-Air
ΨJB
—
30.5
—
°C/W
Junction-to-Board
Package Thermal Resistances, Note 2
Thermal Resistance QFN-24
Note 1:
2:
The maximum allowable power dissipation is a function of ambient temperature, the maximum allowable
junction temperature and the thermal resistance from junction to air (i.e., TA, TJ, JA). Exceeding the
maximum allowable power dissipation will cause the device operating junction temperature to exceed the
maximum +125°C rating. Sustained junction temperatures above +125°C can impact the device reliability.
Thermal performance on QFN packages assumes exposed pad is soldered (or equivalent) to the device
most negative potential (GND).
2018 Microchip Technology Inc.
DS20005835A-page 7
SY89297U
2.0
TYPICAL PERFORMANCE CURVES
Note:
The graphs and tables provided following this note are a statistical summary based on a limited number of
samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore outside the warranted range.
VCC = +2.5V, GND = 0V, VIN = 100 mV, RL = 100Ω across the outputs, TA = +25°C for Figure 2-1.
VCC = 2.5V or 3.3V, GND = 0V, VIN = 100 mV, RL = 100Ω across the outputs, TA = +25°C, Maximum Delay (D0-D9 =
High) for Figure 2-2 through Figure 2-5.
Output Swing
(100mV/div.)
Output Swing vs.
Output Swing
(100mV/div.)
FIGURE 2-1:
Frequency.
Time (150ps/div.)
Time (1ns/div.)
FIGURE 2-4:
Time (80ps/div.)
Time (400ps/div.)
FIGURE 2-3:
DS20005835A-page 8
1.6 Gbps Clock.
Output Swing
(100mV/div.)
155 Mbps Clock.
Output Swing
(100mV/div.)
FIGURE 2-2:
622 Mbps Clock.
FIGURE 2-5:
3.2 Gbps Clock.
2018 Microchip Technology Inc.
SY89297U
2.1
Phase Noise Chart
VCC = +2.5V, GND = 0V, VIN = 100 mV, RL = 100Ω across the outputs, TA = +25°C.
10
100
1K
10K
100K
1M
10M
100M
L(f) [dBc/Hz] vs. f[Hz]
FIGURE 2-6:
fC: 1 GHz. Delay Setting: 00001 00110 (2 ns).
2018 Microchip Technology Inc.
DS20005835A-page 9
SY89297U
3.0
PIN DESCRIPTIONS
The descriptions of the pins are listed in Table 3-1.
TABLE 3-1:
PIN FUNCTION TABLE
Pin Number
Pin Name
1, 2
INA, /INA
Channel A Differential Input: INA and /INA pins receive the Channel A data. QA
and /QA are the delayed product of INA and /INA. Each input is internally
terminated to VTA through a 50Ω resistor (100Ω across INA and /INA).
3
VTA
Input A Termination Center-Tap: Each side of the differential input pair
terminates to this pin. This pin provides a center-tap to a termination network for
maximum interface flexibility. See the Input Interface Applications section.
4
VTB
Input B Termination Center-Tap: Each side of the differential input pair
terminates to this pin. This pin provides a center-tap to a termination network for
maximum interface flexibility. See the Input Interface Applications section.
5, 6
INB, /INB
Channel B Differential Input: INB and /INB pins receive the Channel B data. QB
and /QB are the delayed product of INB and /INB. Each input is internally
terminated to VTB through a 50Ω resistor (100Ω across INB and /INB).
7
VREF-AC
Reference Voltage Output: For AC-coupled input signals, this pin can bias the
inputs IN and /IN. Connect VREF-AC directly to the VT input pin for each
channel. De-couple to VCC using a 0.01 µF capacitor. Maximum sink/source
current is ±0.5 mA. For DC-coupled input applications, leave VREF-AC pin
floating.
8, 11, 20
GND,
Exposed Pad
Negative Supply: Exposed pad must be connected to a ground plane that is the
same potential as the ground pins.
/ENA
CMOS/TTL-Compatible Enable Input: When the /ENA pin is pulled HIGH, QA is
held LOW and /QA goes HIGH after the programmed delay propagates through
the part. /ENA contains a 67 kΩ pull-down resistor and defaults LOW when left
floating. Logic threshold level is VCC/2
10
/ENB
CMOS/TTL-Compatible Enable Input: When the /ENB pin is pulled HIGH, QB is
held LOW and /QB goes HIGH after the programmed delay propagates through
the part. /ENB contains a 67 kΩ pull-down resistor and defaults LOW when left
floating. Logic threshold level is VCC/2
12, 15, 16, 19
VCC
Power Supply: Bypass each supply pin with 0.1 µF//0.01 µF low-ESR
capacitors. See Table 1-1 for more details. 2.5V ±5% or 3.3V ±10%.
13, 14
/QB, QB
CML Differential Output: QB and /QB are the delayed product of INB, /INB. CML
outputs are terminated at the destination with 100Ω across the pair. See the
CML Output Termination section.
17, 18
/QA, QA
CML Differential Output: QA and /QA are the delayed product of INA, /INA. CML
outputs are terminated at the destination with 100Ω across the pair. See the
CML Output Termination section.
SOUT
CMOS/TTL-compatible output: This pin is used to support cascading multiple
SY89297U delay lines. Serial data is clocked into the SDATA input and is
clocked out of SOUT into the next SY89297U delay line. SOUT pin includes an
internal 550Ω pull-up resistor.
SDATA, SCLK
CMOS/TTL-compatible 3-pin serial programming control inputs: The 3-pin serial
control sets each channel’s IN to Q delay. DA(0:9) control channel A delay.
DB(0:9) control channel B. To program the two channels, insert a 20-bit word
(DA0:DA9 and DB0:DB9) into SDATA and clock in the control bits with SCLK.
Maximum input frequency to SCLK is 40 MHz. Data is loaded into the serial
registers on the L-H transition of SCLK. After all 20-bits are clocked in, SLOAD
latches the new delay bits. These pins have internal pull-downs at the inputs.
See Table 1-4 for delay values. Logic threshold level is VCC/2. SCLK and SDATA
contain a 67 kΩ pull-down resistor and default LOW when left floating.
9
21
22, 23
DS20005835A-page 10
Description
2018 Microchip Technology Inc.
SY89297U
TABLE 3-1:
PIN FUNCTION TABLE (CONTINUED)
Pin Number
24
3.1
Pin Name
Description
SLOAD
CMOS/TTL-compatible 3-pin serial programming control input: SLOAD controls
the latches that transfer scanned data to the delay line. These latches are
transparent when SLOAD is high. Data transfers from the latch to the delay line
on a L-H transition of SLOAD. SLOAD has to transition H-L before new data is
loaded in the scan chain. When SLOAD is high, the latches are transparent and
SCLK cannot switch. Otherwise, new data will immediately transfer to the scan
chain. Logic threshold level is VCC/2. SLOAD contains a 67 kΩ pull-down
resistor and defaults LOW when left floating.
Truth Tables
TABLE 3-2:
INPUTS/OUTPUTS
Inputs
Outputs
INA, INB
/INA, /INB
QA, QB
/QA, /QB
0
1
0
1
1
0
1
0
TABLE 3-3:
INPUT ENABLE (LATCHES OUTPUTS)
/ENA, /ENB
Q, /Q (A, B)
1
Q = Low, /Q = HIGH
0
IN, /IN Delayed (normal operation)
2018 Microchip Technology Inc.
DS20005835A-page 11
SY89297U
4.0
TIMING DIAGRAMS
VCC/2
VCC/2
tS
tS
SDATA
VCC/2
VCC/2
SCLK
VCC/2
VCC/2
SDATA
tH
tH
VCC/2
VCC/2
SCLK
Setup and Hold Time: SDATA and SCLK.
FIGURE 4-1:
VCC/2
VCC/2
SCLK
tS
tH
SLOAD
VCC/2
FIGURE 4-2:
DS20005835A-page 12
Latched
Setup and Hold Time: SCLK and SLOAD.
2018 Microchip Technology Inc.
SY89297U
/EN
VCC/2
VCC/2
/EN
tS
tH
IN, /IN
IN, /IN
/EN
VCC/2
tR
IN, /IN
FIGURE 4-3:
Setup, Hold, and Release Time: IN and /EN.
VCC/2
VCC/2
SLOAD
tPW (min)
FIGURE 4-4:
SLOAD Pulse Width (tPW).
2018 Microchip Technology Inc.
DS20005835A-page 13
SY89297U
5.0
VOLTAGE SWINGS
6.0
INPUT AND OUTPUT STAGES
VCC
VIN, VOUT
400mV (typ.)
FIGURE 5-1:
Swing.
Single-Ended Voltage
IN
ȍ
VDIFF_IN, VDIFF_OUT
800mV (typ.)
VT
ȍ
GND
/IN
FIGURE 5-2:
Differential Voltage Swing.
FIGURE 6-1:
Input Stage.
VCC
ȍ
ȍ
/Q
Q
GND
FIGURE 6-2:
DS20005835A-page 14
CML Output Stage.
2018 Microchip Technology Inc.
SY89297U
7.0
INPUT INTERFACE
APPLICATIONS
VCC
IN
VCC
LVPECL
/IN
VCC
IN
CML
GND
/IN
SY89297U
SY89297U
0.1μF
VT
NC
VREF-AC
RP
GND
NC
VT
NC
VREF-AC
For VCC of 2.5V, RP ȍ
For VCC of 3.3V, RP ȍ
Optional: May connect VT to VCC.
CML Interface
FIGURE 7-1:
(DC-Coupled).
FIGURE 7-4:
(DC-Coupled).
LVPECL Interface
VCC
VCC
IN
LVDS
IN
/IN
CML
SY89297U
/IN
VCC
GND
SY89297U
GND
0.1μF
VT
NC
VT
NC
VREF-AC
VREF-AC
CML Interface
FIGURE 7-2:
(AC-Coupled).
FIGURE 7-5:
(DC-Coupled).
LVDS Interface
VCC
IN
LVPECL
/IN
RP
RP
GND
VCC
SY89297U
0.1μF
VT
GND
VREF-AC
For VCC of 2.5V, RP ȍ
For VCC of 3.3V, RP ȍ
FIGURE 7-3:
(AC-Coupled).
LVPECL Interface
2018 Microchip Technology Inc.
DS20005835A-page 15
SY89297U
8.0
CML OUTPUT TERMINATION
VCC
VCC
50ȍ
50ȍ
50ȍ
Z0 = 50ȍ
50ȍ
Z0 = 50ȍ
/Q
50ȍ
/Q
VBIAS
Z0 = 50ȍ
ȍ
50ȍ
Q
Z0 = 50ȍ
Q
GND
FIGURE 8-3:
CML AC-Coupled
Termination – 50Ω to VBIAS.
GND
FIGURE 8-1:
CML AC-Coupled
Termination – 100Ω Differential.
VCC
50ȍ
50ȍ
Z0 = 50ȍ
/Q
50ȍ
VCC
Z0 = 50ȍ
50ȍ
Q
GND
FIGURE 8-2:
CML AC-Coupled
Termination – 50Ω to VCC.
DS20005835A-page 16
2018 Microchip Technology Inc.
SY89297U
9.0
PACKAGING INFORMATION
9.1
Package Marking Information
24-Lead QFN*
–
XXXX
WWNNN
COO
Legend: XX...X
Y
YY
WW
NNN
COO
e3
*
Example
–
297U
21943
USA
Product code or customer-specific information
Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
Country of Origin
Pb-free JEDEC® designator for Matte Tin (Sn)
This package is Pb-free. The Pb-free JEDEC designator ( e3 )
can be found on the outer packaging for this package.
●, ▲, ▼ Pin one index is identified by a dot, delta up, or delta down (triangle
mark).
Note:
In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information. Package may or may not include
the corporate logo.
Underbar (_) and/or Overbar (⎯) symbol may not be to scale.
2018 Microchip Technology Inc.
DS20005835A-page 17
SY89297U
24-Lead 4 mm x 4 mm QFN Package Outline and Recommended Land Pattern
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging.
DS20005835A-page 18
2018 Microchip Technology Inc.
SY89297U
APPENDIX A:
REVISION HISTORY
Revision A (January 2018)
• Converted Micrel document SY89297U to Microchip data sheet DS20005835A.
• Minor text changes throughout.
2018 Microchip Technology Inc.
DS20005835A-page 19
SY89297U
NOTES:
DS20005835A-page 20
2018 Microchip Technology Inc.
SY89297U
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, contact your local Microchip representative or sales office.
PART NO.
X
Device
Voltage
Option
Device:
X
X
-XX
Examples:
a) SY89297UMG:
2.5V/3.3V, 3.2 Gbps Precision
CML Dual-Channel
Programmable Delay, 2.5V/3.3V,
24-Lead 4 mm x 4 mm QFN,
–40°C to +85°C (Pb-Free
NiPdAu), 75/Tube
b) SY89297UMG-TR:
2.5V/3.3V, 3.2 Gbps Precision
CML Dual-Channel
Programmable Delay, 2.5V/3.3V,
24-Lead 4 mm x 4 mm QFN,
–40°C to +85°C (Pb-Free
NiPdAu), 1,000/Reel
c) SY89297UMH:
2.5V/3.3V, 3.2 Gbps Precision
CML Dual-Channel
Programmable Delay, 2.5V/3.3V,
24-Lead 4 mm x 4 mm QFN,
–40°C to +75°C (Pb-Free
NiPdAu), 75/Tube
b) SY89297UMH-TR:
2.5V/3.3V, 3.2 Gbps Precision
CML Dual-Channel
Programmable Delay, 2.5V/3.3V,
24-Lead 4 mm x 4 mm QFN,
–40°C to +75°C (Pb-Free
NiPdAu), 1,000/Reel
Package Temperature
Special
Processing
Range
SY89297:
2.5V/3.3V, 3.2 Gbps Precision CML DualChannel Programmable Delay
Voltage Option:
U
=
2.5V/3.3V
Package:
M
=
24-Lead 4 mm x 4 mm QFN
Temperature
Range:
G
H
=
=
–40°C to +85°C (Pb-Free NiPdAu)
–40°C to +75°C (Pb-Free NiPdAu)
Special
Processing:
=
TR
=
75/Tube
1,000/Reel
Note 1:
2018 Microchip Technology Inc.
Tape and Reel identifier only appears in the
catalog part number description. This identifier is
used for ordering purposes and is not printed on
the device package. Check with your Microchip
Sales Office for package availability with the
Tape and Reel option.
DS20005835A-page 21
SY89297U
NOTES:
DS20005835A-page 22
2018 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
•
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights unless otherwise stated.
Microchip received ISO/TS-16949:2009 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
QUALITY MANAGEMENT SYSTEM
CERTIFIED BY DNV
Trademarks
The Microchip name and logo, the Microchip logo, AnyRate, AVR,
AVR logo, AVR Freaks, BeaconThings, BitCloud, CryptoMemory,
CryptoRF, dsPIC, FlashFlex, flexPWR, Heldo, JukeBlox, KEELOQ,
KEELOQ logo, Kleer, LANCheck, LINK MD, maXStylus,
maXTouch, MediaLB, megaAVR, MOST, MOST logo, MPLAB,
OptoLyzer, PIC, picoPower, PICSTART, PIC32 logo, Prochip
Designer, QTouch, RightTouch, SAM-BA, SpyNIC, SST, SST
Logo, SuperFlash, tinyAVR, UNI/O, and XMEGA are registered
trademarks of Microchip Technology Incorporated in the U.S.A.
and other countries.
ClockWorks, The Embedded Control Solutions Company,
EtherSynch, Hyper Speed Control, HyperLight Load, IntelliMOS,
mTouch, Precision Edge, and Quiet-Wire are registered
trademarks of Microchip Technology Incorporated in the U.S.A.
Adjacent Key Suppression, AKS, Analog-for-the-Digital Age, Any
Capacitor, AnyIn, AnyOut, BodyCom, chipKIT, chipKIT logo,
CodeGuard, CryptoAuthentication, CryptoCompanion,
CryptoController, dsPICDEM, dsPICDEM.net, Dynamic Average
Matching, DAM, ECAN, EtherGREEN, In-Circuit Serial
Programming, ICSP, Inter-Chip Connectivity, JitterBlocker,
KleerNet, KleerNet logo, Mindi, MiWi, motorBench, MPASM, MPF,
MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach,
Omniscient Code Generation, PICDEM, PICDEM.net, PICkit,
PICtail, PureSilicon, QMatrix, RightTouch logo, REAL ICE, Ripple
Blocker, SAM-ICE, Serial Quad I/O, SMART-I.S., SQI,
SuperSwitcher, SuperSwitcher II, Total Endurance, TSHARC,
USBCheck, VariSense, ViewSpan, WiperLock, Wireless DNA, and
ZENA are trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated in
the U.S.A.
Silicon Storage Technology is a registered trademark of Microchip
Technology Inc. in other countries.
GestIC is a registered trademark of Microchip Technology
Germany II GmbH & Co. KG, a subsidiary of Microchip Technology
Inc., in other countries.
All other trademarks mentioned herein are property of their
respective companies.
© 2018, Microchip Technology Incorporated, All Rights Reserved.
ISBN: 978-1-5224-2520-5
== ISO/TS 16949 ==
2018 Microchip Technology Inc.
DS20005835A-page 23
Worldwide Sales and Service
AMERICAS
ASIA/PACIFIC
ASIA/PACIFIC
EUROPE
Corporate Office
2355 West Chandler Blvd.
Chandler, AZ 85224-6199
Tel: 480-792-7200
Fax: 480-792-7277
Technical Support:
http://www.microchip.com/
support
Web Address:
www.microchip.com
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Tel: 61-2-9868-6733
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Tel: 91-80-3090-4444
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Fax: 43-7242-2244-393
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Tel: 45-4450-2828
Fax: 45-4485-2829
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Tel: 631-435-6000
San Jose, CA
Tel: 408-735-9110
Tel: 408-436-4270
Canada - Toronto
Tel: 905-695-1980
Fax: 905-695-2078
DS20005835A-page 24
China - Xiamen
Tel: 86-592-2388138
China - Zhuhai
Tel: 86-756-3210040
Germany - Garching
Tel: 49-8931-9700
Germany - Haan
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Fax: 49-89-627-144-44
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Fax: 31-416-690340
Norway - Trondheim
Tel: 47-7289-7561
Poland - Warsaw
Tel: 48-22-3325737
Romania - Bucharest
Tel: 40-21-407-87-50
Spain - Madrid
Tel: 34-91-708-08-90
Fax: 34-91-708-08-91
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Tel: 46-31-704-60-40
Sweden - Stockholm
Tel: 46-8-5090-4654
UK - Wokingham
Tel: 44-118-921-5800
Fax: 44-118-921-5820
2018 Microchip Technology Inc.
10/25/17
