SY89808LTI

NOT RECOMMENDED FOR NEW DESIGNS Precision Edge® ® SY89808L Precision Edge 3.3V, 500MHz, 1:9 DIFFERENTIAL HSTL (1.5V) FANOUT BUFFER/ TRANSLATOR Micrel, Inc. SY89808L FEATURES ■ 9 differential HSTL (1.5V compatible) output pairs Precision Edge® ■ 500MHz maximum clock frequency ■ Triple-buffered enable function DESCRIPTION ■ 3.3V core supply, 1.8V output supply for reduced ■ ■ ■ ■ ■ power LVPECL and HSTL inputs HSTL outputs drive 50Ω to ground with no offset voltage Low pin-to-pin skew (25ps max.) Guaranteed over industrial –40°C to +85°C temperature range Available in 32-pin TQFP package The SY89808L is a High-Performance Bus Clock Driver with 9 differential HSTL (High-Speed Transceiver Logic) 1.5V compatible output pairs. The part is designed for use in lowvoltage (3.3V/1.8V) applications which require a large number of outputs to drive precisely aligned, ultra-low skew signals to their destination. The input is multiplexed from either HSTL or LVPECL (Low-Voltage Positive-Emitter-Coupled Logic) by the CLK_SEL pin. The Output Enable (OE) is synchronous and triple-buffered so that the outputs will only be enabled/disabled when they are already in the LOW state. This avoids any potential of generating a runt clock pulse when the device is enabled/disabled, as can occur with an asynchronous control. The triple-buffering feature provides a three-clock delay from the time the OE input is asserted/de-asserted to when the clock appears at the outputs. The SY89808L features an ultra-low pin-to-pin skew of less than 25ps. The SY89808L is available in a 32-TQFP space saving package, enabling a lower overall cost solution. APPLICATIONS ■ Workstations ■ Parallel processor-based systems ■ High-performance computing ■ Communications TRUTH TABLE LOGIC SYMBOL CLK_SEL HSTL_CLK /HSTL_CLK 0 9 9 OE(1) CLK_SEL Q0 – Q8 /Q0 – /Q8 0 0 LOW HIGH 0 1 LOW HIGH 1 0 HSTL_CLK /HSTL_CLK 1 1 LVPECL_CLK /LVPECL_CLK Notes: Q0 — Q8 1. The OE (output enable) signal is synchronized with the low level of the HSTL_CLK and LVPECL_CLK signal. /Q0 — /Q8 LVPECL_CLK 1 /LVPECL_CLK TYPICAL PERFORMANCE EN ENABLE LOGIC OE 900 Output Amplitude vs. Frequency AMPLITUDE (mV) 800 700 600 500 400 1600 1400 1200 800 1000 600 FREQUENCY (MHz) Precision Edge is a registered trademark of Micrel, Inc. M9999-091405 hbwhelp@micrel.com or (408) 955-1690 400 0 200 200 300 Rev.: E 1 Amendment: /0 Issue Date: September 2005 Precision Edge® SY89808L Micrel, Inc. /Q2 Ordering Information(1) VCCO /Q1 Q2 /Q0 Q1 Q0 VCCO PACKAGE/ORDERING INFORMATION 32 31 30 29 28 27 26 25 24 1 Part Number Package Operating Type Range Package Marking Lead Finish SY89808LTI Sn-Pb SY89808LTI Sn-Pb VCCO SY89808LTI T32-1 HSTL_CLK 2 23 Q3 /HSTL_CLK 3 22 /Q3 SY89808LTITR(2) T32-1 Industrial SY89808LTG(3) T32-1 Industrial SY89808LTG with NiPdAu Pb-Free bar line indicator Pb-Free SY89808LTGTR(2, 3) T32-1 Industrial SY89808LTG with NiPdAu Pb-Free bar line indicator Pb-Free VCCI CLK_SEL 4 21 Q4 LVPECL_CLK 5 20 /Q4 /LVPECL_CLK 6 19 Q5 GND 7 18 /Q5 OE 8 17 9 10 11 12 13 14 15 16 Q6 VCCO VCCO Q7 /Q6 Q8 /Q7 /Q8 VCCO Top View Industrial Notes: 1. Contact factory for die availability. Dice are guaranteed at TA = 25°C, DC Electricals only. 2. Tape and Reel. 3. Pb-Free package is recommended for new designs. 32-Pin TQFP (T32-1) PIN DESCRIPTION Pin Number Pin Name Type Pin Function 2, 3 HSTL_CLK, /HSTL_CLK HSTL Input Differential clock input selected by CLK_SEL. Can be left floating if not selected. Floating input, if selected produces an indeterminate output. HSTL input signal requires external termination 50Ω to GND. 5, 6 LVPECL_CLK, /LVPECL_CLK LVPECL Input 4 CLK_SEL LVTTL Input Selects HSTL_CLK input when LOW and LVPECL_CLK output when HIGH. 11kΩ pull-up. 8 OE LVTTL Input Enable input synchronized internally to prevent glitching of the Q0-Q8 and /Q0-/Q8 outputs. Must be a minimum of three clock periods wide if synchronous with the CLK inputs and must meet the tS and tH requirements (refer to AC Electrical Characteristics). If asynchronous, must be a minimum of four clock periods wide. 11kΩ pull-up. 31, 29, 27, 23, 21, 19, 15, 13, 11 Q0–Q8 HSTL Output Differential clock outputs from HSTL_CLK when CLK_SEL = LOW and LVPECL outputs when CLK_SEL = HIGH. HSTL outputs must be terminated with 50Ω to GND. Q0–Q8 outputs are static LOW when OE = LOW. Unused output pairs may be left floating. 30, 28, 26, 22, 20, 18, 14, 12, 10 /Q0–/Q8 HSTL Output Differential clock outputs from HSTL_CLK when CLK_SEL = LOW and LVPECL outputs when CLK_SEL = HIGH. HSTL outputs must be terminated with 50Ω to GND. /Q0–/Q8 outputs are static HIGH when OE = LOW. Unused output pairs may be left floating. 1 VCCI VCC Core Power 9, 16, 17, 24, 25, 32 VCCO VCC Output Power 7 GND Ground M9999-091405 hbwhelp@micrel.com or (408) 955-1690 Differential clock input selected by CLK_SEL. Can be left floating. Floating input, if selected produces a LOW at the output (internal 75Ω pull-downs). Requires external termination. 75kΩ pull-up. Core VCC connected to 3.3V supply. Bypass with 0.1µF in parallel with 0.01µF low ESR capacitors as close to VCCI pin as possible. Output Buffer VCC connected to 1.8V supply. Bypass with 0.1µF in parallel with 0.01µF low ESR capacitors as close to VCCO pins as possible. All VCCO pins should be connected together on the PCB. Ground. 2 Precision Edge® SY89808L Micrel, Inc. Absolute Maximum Ratings(1) Operating Ratings(2) Supply Voltage (VIN) ..................................... –0.5V to VCCI VCC Pin Potential to Ground Pin (VCCI, VCCO) ............................................ –0.5V to +4.0V DC Output Current, Output HIGH (IOUT) .................. –50mA Lead Temperature (soldering, 20 sec.) ..................... 260°C Storage Temperature (TS) ....................... –65°C to +150°C Supply Voltage (VCCI) ............................................... +3.15V to +3.45V (VCCO) ................................................. +1.6V to +2.0V Ambient Temperature (TA) ......................... –40°C to +85°C Package Thermal Resistance TQFP (θJA) –Still-Air ........................................................... 50°C/W –500lfpm .......................................................... 42°C/W TQFP (θJC) .......................................................... 20°C/W DC ELECTRICAL CHARACTERISTICS Power Supply TA = –40°C to +85°C, unless otherwise stated. Symbol Parameter VCCI Condition Min Typ Max Units VCC Core 3.15 3.3 3.45 V VCCO VCC Output 1.6 1.8 2.0 V ICCI ICC Core — 80 110 mA Min Typ Max Units Max VCC, No Load HSTL VCCI = 3.3V ± 5%; VCCO = 1.8V ± 10%; RL = 50Ω to GND; TA = –40°C to +85°C, unless otherwise stated. Symbol Parameter Condition VOH Output HIGH Voltage 1.0 — 1.2 V VOL Output LOW Voltage 0.2 — 0.4 V VIH Input HIGH Voltage VX +0.1 — 1.6 V VIL Input LOW Voltage –0.3 — VX –0.1 V VX Input Crossover Voltage 0.68 — 0.9 V IIH Input HIGH Current +20 — –350 µA IIL Input LOW Current — — –500 µA LVPECL VCCI = 3.3V ± 5%; VCCO = 1.8V ± 10%; TA = –40°C to +85°C, unless otherwise stated. Symbol Parameter Condition Min Max Units VIH Input HIGH Voltage VCCI – 1.165 VCCI – 0.880 V VIL Input LOW Voltage VCCI – 1.810 VCCI – 1.475 V IIH Input HIGH Current — +150 µA IIL Input LOW Current 0.5 — µA LVCMOS/LVTTL VCCI = 3.3V ± 5%; VCCO = 1.8V ± 10%; TA = –40°C to +85°C, unless otherwise stated. Symbol Parameter VIH Condition Min Typ Max Units Input HIGH Voltage 2.0 — — V VIL Input LOW Voltage — — 0.8 V IIH Input HIGH Current +20 — –250 µA IIL Input LOW Current — — –600 µA Notes: 1. Permanent device damage may occur if “Absolute Maximum Ratings” are exceeded. This is a stress rating only and functional operation is not implied at conditions other than those detailed in the operational sections of this data sheet. Exposure to absolute maximum ratlng conditions for extended periods may affect device reliability. 2. The data sheet limits are not guaranteed if the device is operated beyond the operating ratings. M9999-091405 hbwhelp@micrel.com or (408) 955-1690 3 Precision Edge® SY89808L Micrel, Inc. AC ELECTRICAL CHARACTERISTICS VCCI = 3.3V ± 5%; VCCO = 1.8V ± 10%; All outputs are loaded with 50Ω to GND; TA = –40°C to +85°C, unless otherwise stated. Symbol Parameter Condition Min Typ Max Units fMAX Maximum Operating Frequency VOUT ≥ 450mV 500 — — MHz tpd Propagation Delay CLK-to-Q Note 3 0.800 1.000 1.200 ns SEL-to-Q Note 3 0.800 1.200 1.700 ns tSKEW Within-Device Skew Note 4 — — 25 ps tSKPP Part-to-Part Skew Note 5 — — 400 ps Vpp Minimum Input Swing LVPECL_CLK Note 6 150 — — mV VCMR Common Mode Range LVPECL_CLK Note 7 –1.5 — –0.4 V tS OE Set-Up Time Note 8 1.0 — — ns tH OE Hold Time 0.5 — — ns t r , tf Output Rise/Fall Time (20% – 80%) 250 450 650 ps tJITTER Cycle-to-Cycle Jitter Note 9 1 psRMS Total Jitter Note 10 10 psPP 3. Differential propagation delay is defined as the delay from the crossing point of the differential input signals to the crossing point of the differential output signals. 4. The within-device skew is defined as the worst case difference between any two similar delay paths within a single device operating at the same voltage and temperature. 5. The part-to-part skew is defined as the absolute worst case difference between any two delay paths on any two devices operating at the same voltage and temperature. 6. The VPP (min.) is defined as the minimum input differential voltage which will cause no increase in the propagation delay. 7. VCMR is defined as the range within which the VIH level may vary, with the device still meeting the propagation delay specification. The numbers in the table are referenced to VCCI. The VIL level must be such that the peak-to-peak voltage is less than 1.0V and greater than or equal to VPP (min.). The lower end of the CMR range varies 1:1 with VCCI. The VCMR (min) will be fixed at 3.3V – |VCMR (min)|. 8. OE set-up time is defined with respect to the rising edge of the clock. OE HIGH to LOW transition ensures outputs remain disabled during the next clock cycle. OE LOW to HIGH transition enables normal operation of the next input clock. 9. Cycle-to-cycle jitter definition: the variation of periods between adjacent cycles, Tn–Tn–1 where T is the time between rising edges of the output signal. 10. Total jitter definition: with an ideal clock source of ≤ fmax, no more than one output edge in 1012 output edges will deviate by more than the specified amount. M9999-091405 hbwhelp@micrel.com or (408) 955-1690 4 Precision Edge® SY89808L Micrel, Inc. TIMING DIAGRAMS Assert Latency De-assert Latency CLK tS tH OE Q0 - Q8 Notes: 1. The OE input signal must be a minimum of 3 clock periods with width. 2. The internal enable is asserted and de-asserted on the falling edge of clock. 3. The internal enable occurs 2.5 clock cycles (plus the set-up time of OE with the rising edge of clock) after the rising edge of the external OE. 4. If OE does not meet the tS of tH specifications as in asynchronous applications, OE must be a minimum of 4 clock periods in width. HSTL_CLK, LVPECL_CLK /HSTL_CLK, /LVPECL_CLK tPD Q0 - Q8 /Q0 - /Q8 CLK_SEL tPD tPD Q0 - Q8 /Q0 - /Q8 M9999-091405 hbwhelp@micrel.com or (408) 955-1690 5 Precision Edge® SY89808L Micrel, Inc. TYPICAL OPERATING CHARACTERISTICS VCCI = 3.0V, VCCO = 1.8V, TA = 25°C, unless otherwise stated. 400MHz Output 200MHz Output /Q Output Swing (100mV/div.) Output Swing (100mV/div.) /Q Q Q TIME (300ps/div) TIME (700ps/div) 500MHz Output Output Swing (100mV/div.) Q /Q TIME (300ps/div) M9999-091405 hbwhelp@micrel.com or (408) 955-1690 6 Precision Edge® SY89808L Micrel, Inc. LVPECL/HSTL INPUTS VCC VCC HSTL_CLK LVPECL_CLK 75kΩ 75kΩ /HSTL_CLK Clamp /LVPECL_CLK GND GND Figure 2. Simplified HSTL Input Stage Figure 1. Simplified LVPECL Input Stage HSTL OUTPUTS QOUT 1.6V QOUT — /QOUT QOUT 800mV /QOUT /QOUT Figure 4. Output Driver Signal Levels (Differential) Figure 3. Output Driver Signal Levels (Single-Ended) RELATED PRODUCT AND SUPPORT DOCUMENTATION Part Number Function Data Sheet Link SY89809L 3.3V 1:9 High-Performance, Low-Voltage Bus Clock Driver www.micrel.com/product-info/products/sy89809l.shtml SY89823L 3.3V, 500MHz 1:22 Differential HSTL (1.5V) Fanout Buffer/Translator www.micrel.com/product-info/products/sy89823l.html Exposed Pad Application Note www.amkor.com/products/notes_papers/epad.pdf HBW Solutions New Products and Applications www.micrel.com/product-info/products/solutions.shtml MIC3775 750mA µCap Low-Voltage Low-Dropout Regulator www.micrel.com/product-info/products/mic3775.shtml M9999-091405 hbwhelp@micrel.com or (408) 955-1690 7 Precision Edge® SY89808L Micrel, Inc. 32 LEAD TQFP (T32-1) Package Notes: Package meets Level 2 qualification. MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 TEL + 1 (408) 944-0800 FAX + 1 (408) 474-1000 WEB USA http://www.micrel.com The information furnished by Micrel in this datasheet is believed to be accurate and reliable. However, no responsibility is assumed by Micrel for its use. Micrel reserves the right to change circuitry and specifications at any time without notification to the customer. Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product can reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. A Purchaser’s use or sale of Micrel Products for use in life support appliances, devices or systems is at Purchaser’s own risk and Purchaser agrees to fully indemnify Micrel for any damages resulting from such use or sale. © 2005 Micrel, Incorporated. M9999-091405 hbwhelp@micrel.com or (408) 955-1690 8