SY89831U
Ultra-Precision 1:4 LVPECL Fanout
Buffer/Translator with Internal Termination
Precision Edge®
General Description
The SY89831U is a high-speed, 2GHz differential LVPECL
1:4 fanout buffer optimized for ultra-low skew applications.
Within-device skew is guaranteed to be less than 20ps
(5ps typ.) over supply voltage and temperature. The
differential input buffer has a unique internal termination
design that allows access to the termination network
through a VT pin. This feature allows the device to easily
interface to different logic standards. A VREF-AC
reference output is included for AC-coupled applications.
The SY89831U is a part of Micrel's high-speed clock
synchronization family. For applications that require a
different I/O combination, consult Micrel’s website at:
www.micrel.com, and choose from a comprehensive
product line of high-speed, low-skew fanout buffers,
translators, and clock generators.
Datasheets and support documentation are available on
Micrel’s web site at: www.micrel.com.
Precision Edge®
Features
• Guaranteed AC performance over temperature and
voltage
− DC-to 2.5GHz throughput (typical)
− 350ps propagation delay (IN-to-Q) (typical)
− 5ps within-device skew (typical)
− 150ps rise/fall time (typical)
• Ultra-low jitter design
− 62fs RMS phase jitter (typical)
• Unique patent-pending input termination and VT pin
accepts DC- and AC-coupled differential inputs
• 800mV, 100K LVPECL typical output swing
• Power supply 2.5V ±5% or 3.3V ±10%
• Industrial temperature range: –40°C to +85°C
• Available in 16-pin (3mm x 3mm) MLF® package
Applications
•
•
•
•
Processor clock distribution
SONET clock distribution
Fibre Channel clock distribution
Gigabit Ethernet clock distribution
United States Patent No. RE44,134
Precision Edge is a registered trademark of Micrel, Inc.
MicroLeadFrame and MLF are registered trademarks of Amkor Technology, Inc.
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (408) 944-0800 • fax + 1 (408) 474-1000 • http://www.micrel.com
January 17, 2014
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SY89831U
Ordering Information(1)
Part Number
(2)
SY89831UMG
(2, 3)
SY89831UMGTR
Package Type
Operating Range
Package Marking
Lead Finish
MLF-16
Industrial
831U with Pb-Free bar-line indicator
NiPdAu Pb-Free
MLF-16
Industrial
831U with Pb-Free bar-line indicator
NiPdAu Pb-Free
Notes:
1. Contact factory for die availability. Dice are guaranteed at TA = 25°C, DC electricals only.
2. Pb-Free package is recommended for new designs.
3. Tape and Reel.
Pin Configuration
16-MLF (MLF-16)
Pin Description
Pin #
Pin Name
15, 16
1, 2
3, 4
5, 6
Q0, /Q0
Q1, /Q1
Q2, /Q2
Q3, /Q3
Differential 100K LVPECL Outputs: These LVPECL outputs are the precision, low-skew copies of the
inputs. Please refer to the “Truth Table” section for details. Unused output pairs may be left open.
Terminate with 50Ω to VCC – 2V. See the “Output Termination Recommendations” section for more
details.
8
EN
This single-ended TTL/CMOS-compatible input functions as a synchronous output enable. The
synchronous enable ensures that enable/disable only occurs when the outputs are in a logic low state.
Note that this input is internally connected to a 25kΩ pull-up resistor and will default to logic high state
(enabled) if left open.
9, 12
/IN, IN
Differential Inputs: These input pairs are the differential signal inputs to the device. Inputs accept ACor DC-coupled differential signs as small as 100mV. Each pin of a pair internally terminates to a VT pin
through 50Ω. Note that these inputs default to an intermediate state if left open. Please refer to the
“Input Interface Applications” section for more details.
10
VREF-AC
Reference Voltage: These outputs bias to VCC – 1.4V. They are used when AC coupling the inputs
(IN, /IN). For AC-coupled applications, connect VREF-AC to the VT pin and bypass with a 0.01µF lowESR capacitor to VCC. See the “Input Interface Applications” section for more details. Maximum
sink/source current is ±1.5mA. Due to the limited drive capability, each VREF-AC pin should only drive
its respective VT pin. If VREF-AC is used with a 2.5V supply, make sure the input swing is large
enough to comply with the VIH min. spec.
January 17, 2014
Functional Description
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SY89831U
Pin #
Pin Name
Functional Description
11
VT
Input Termination Center-Tap: Each side of the differential input pair terminates to a VT pin. The VT
pins provide a center-tap to a termination network for maximum interface flexibility. See the “Input
Interface Applications” section for more details.
13
GND
Ground. GND pins and exposed pad must be connected to the most negative potential of the device
ground.
7, 14
VCC
Positive Power Supply: Bypass with 0.1µF/0.01µF low-ESR capacitors placed as close as possible to
each VCC pin.
Truth Table
IN
/IN
EN
Q
/Q
0
1
1
0
1
1
0
1
1
0
0
(4)
X
X
0
1
(4)
Note:
4. On the next negative transition of the input signal (IN).
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SY89831U
Absolute Maximum Ratings(5)
Operating Ratings(6)
Supply Voltage (VCC) .....................................−0.5V to +4.0V
Input Voltage (VIN) ................................. −0.5V to VCC + 0.5V
LVPECL Output Current (IOUT)
Continuous ............................................................ 50mA
Surge .................................................................. 100mA
Input Current
Source or Sink Current on (IN, /IN) .................... ±50mA
VREF-AC Current
Source or Sink Current on (IVT) ............................. ±2mA
Lead Temperature (soldering, 20s) ............................ 260°C
Storage Temperature (Ts)......................... –65°C to +150°C
Supply Voltage Range ......................... +2.375V to +2.625V
............................................................... +3.0V to +3.6V
Ambient Temperature (TA) .......................... –40°C to +85°C
(7)
Package Thermal Resistance
(θJA) Still Air........................................................ 60°C/W
(θJA) Junction to Board ....................................... 32°C/W
DC Electrical Characteristics(8)
TA = –40°C to +85°C, unless otherwise noted.
Symbol
Parameter
VCC
Power Supply
ICC
Power Supply Current
RIN
Input Resistance (IN-to-VT)
RDIFF-IN
Condition
Min.
Typ.
Max.
Units
2.625
3.6
V
47
70
mA
45
50
55
Ω
Differential Input Resistance
(IN-to-/IN)
90
100
110
Ω
VIH
Input HIGH Voltage (IN, /IN)
1.2
VCC
V
VIL
Input LOW Voltage (IN, /IN)
0
VIH – 0.1
V
VIN
Input Voltage Swing (IN, /IN)
See Figure 1.
0.1
1.7
V
VDIFF_IN
Differential Input Voltage Swing
|IN – /IN|
See Figure 2.
0.2
VREF–AC
Output Reference Voltage
2.375
3.0
No load, max. VCC
V
VCC – 1.525
VCC – 1.425
VCC – 1.325
V
Max.
Units
LVTTL/LVCMOS Input DC Electrical Characteristics
VCC = 2.375V to 3.60V; VEE = 0V; TA = –40°C to +85°C
Symbol
Parameter
Condition
Min.
Typ.
VIH
Input HIGH Voltage
2.0
VCC
V
VIL
Input LOW Voltage
0
0.8
V
IIH
Input HIGH Current
–125
20
µA
IIL
Input LOW Current
–300
µA
Notes:
5. Permanent device damage may occur if absolute maximum ratings are exceeded. This is a stress rating only and functional operation is not implied
at conditions other than those detailed in the operational sections of this datasheet. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.
6. The datasheet limits are not guaranteed if the device is operated beyond the operating ratings.
7. Package thermal resistance assumes the exposed pad is soldered (or equivalent) to the device’s most negative potential on the PCB. ΨJB and θJA
values are determined for a 4-layer board at the still-air package thermal resistance, unless otherwise stated.
8. The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established.
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SY89831U
LVPECL Output DC Electrical Characteristics(8)
VCC = 2.5V ±5% or 3.3V ±10%; RL = 50Ω to VCC − 2V; TA = –40°C to + 85°C, unless otherwise noted.
Symbol
Parameter
Condition
Min.
Typ.
Max.
Units
VOH
Output HIGH Voltage (Q, /Q)
VCC – 1.145
VCC – 0.895
V
VOL
Output LOW Voltage (Q, /Q)
VCC – 1.945
VCC – 1.695
V
VOUT
Output Voltage Swing (Q, /Q)
See Figure 1.
550
800
mV
VDIFF_OUT
Differential Output Voltage
Swing (Q, /Q)
See Figure 2.
1100
1600
mV
LVTTL/LVCMOS DC Electrical Characteristics(8)
VCC = 2.5V ±5% or 3.3V ±10%; TA = –40°C to + 85°C, unless otherwise noted.
Symbol
Parameter
Condition
VIH
Input HIGH Voltage
VIL
Min.
Typ.
Max.
Units
2.0
VCC
V
Input LOW Voltage
0
0.8
V
IIH
Input HIGH Current
–125
30
µA
IIL
Input LOW Current
–300
µA
AC Electrical Characteristics(9)
VCC = 2.5V ±5% or 3.3V ±10%; RL = 50Ω to VCC − 2V; TA = –40°C to + 85°C, unless otherwise noted.
Symbol
Parameter
Condition
fMAX
Maximum Frequency
VOUT ≥ 450mV
tpd
Propagation
Delay
tSKEW
IN-to-Q
VIN ≥ 100mV
IN-to-Q
VIN ≥ 800mV
Min.
Typ.
2.0
2.5
GHz
390
ps
250
Max.
Units
350
450
ps
5
20
ps
150
ps
Within-Device Skew
Note 10
Part-to-Part Skew
Note 11
tS
Set-Up Time
EN to IN, /IN
Note 12
300
ps
tH
Hold Time
EN to IN, /IN
Note 12
300
ps
tJITTER
RMS Phase Jitter
Output = 622MHz
Integration Range 12kHz–20MHz
tr , tf
Output Rise/Fall Times
(20% to 80%)
At full output swing
70
150
225
ps
Duty Cycle
Freq. < 630MHz
48
50
52
%
62
fs
Notes:
9. High-frequency AC parameters are guaranteed by design and characterization.
10. Within-device skew is measured between two different outputs under identical input transitions.
11. Part-to-part skew is defined for two parts with identical power supply voltages at the same temperature and no skew at the edges at the respective
inputs.
12. Set-up and hold times apply to synchronous applications that will enable/disable before the next clock cycle. For asynchronous applications, set-up
and hold times do not apply.
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SY89831U
Typical Phase Noise
SY89831U Phase Noise vs Frequency
3.3V, 622MHz, 12kHz-20MHz
Additive
-100.00
-110.00
Phase Noise (dBc/Hz)
-120.00
-130.00
-140.00
-150.00
-160.00
-170.00
-180.00
0.01
1
0.1
100
10
Offset Frequency (MHZ)
Millions
SY89831U Phase Noise vs Frequency
3.3V, 156.25MHz, 12kHz-20MHz
Additive
-100.00
-110.00
Phase Noise (dBc/Hz)
-120.00
-130.00
-140.00
-150.00
-160.00
-170.00
-180.00
0.001
0.01
0.1
1
Offset Frequency (MHZ)
January 17, 2014
6
10
100
Millions
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SY89831U
Typical Characteristics
VCC = 3.3V; GND = 0V; RL = 50Ω to VCC – 2V; TA = 25°C, unless otherwise noted.
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SY89831U
Typical Output Waveforms
VCC = 3.3V; GND = 0V; VIN = 800mV; RL = 50Ω to VCC − 2V; TA = 25°C, unless otherwise noted.
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SY89831U
Functional Block Diagram
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SY89831U
Single-Ended and Differential Swings
Figure 1. Single-Ended Swing
Figure 2. Differential Swing
Input and Output Stages
Figure 3. Simplified Differential
January 17, 2014
Figure 4. Simplified LVPECL Output Stage
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SY89831U
Input Interface Applications
Figure 5. DC-Coupled LVPECL
Input Interface
Figure 6. AC-Coupled LVPECL
Input Interface
Figure 7. DC-Coupled CML
Input Interface
Figure 8. AC-Coupled CML
Input Interface
Figure 9. DC-Coupled LVDS
Input Interface
Figure 10. AC-Coupled LVDS
Input Interface
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SY89831U
Output Termination Recommendations
Figure 11. Parallel Termination – Thevenin Equivalent
Note:
13. For +2.5V Systems: R1 = 250Ω, R2 = 62.5Ω.
Figure 12. Three-Resistor “Y-Termination”
Notes:
14. Power-saving alternative to Thevenin termination.
15. Place termination resistors as close to destination inputs as possible.
16. The Rb resistor sets the DC bias voltage equal to Vt. For +2.5V systems, Rb = 19Ω.
17. C1 is an optional bypass capacitor that compensates for any tr/tf mismatches.
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SY89831U
Related Product and Support Documentation
Part Number
Function
Data Sheet Link
SY89830U
1:4 LVPECL Fanout Buffer w/2:1 MUX Input
http://www.micrel.com/index.php/en/products/clocktiming/clock-data-distribution/fanout-buffers/article/51sy89830u.html
SY89832U
2.5V Ultra-Precision 1:4 LVDS Fanout
Buffer/ Translator with Internal Termination
http://www.micrel.com/index.php/en/products/clocktiming/clock-data-distribution/fanout-buffers/article/38sy89832u.html
SY89833AL
3.3V Ultra-Precision 1:4 LVDS Fanout
Buffer/Translator with Internal Termination
http://www.micrel.com/index.php/en/products/clocktiming/clock-data-distribution/fanout-buffers/article/39sy89833al.html
SY89834U
2.5/3.3V Two Input, 1GHz LVTTL/CMOS-toLVPECL 1:4 Fanout Buffer/Translator
http://www.micrel.com/index.php/en/products/clocktiming/clock-data-distribution/fanout-buffers/article/50sy89834u.html
16-MLF® Manufacturing Guidelines Exposed
Pad Application Note
www.amkor.com/products/notes_papers/MLF_AppNote_0
301.pdf
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SY89831U
Package Information(18)
PCB Thermal Consideration for 16-Pin MLF Package
(Always solder, or equivalent, the exposed pad to the PCB)
®
16-Pin EPAD MicroLeadFrame (MLF-16)
Notes:
18. Package information is correct as of the publication date. For updates and most current information, go to www.micrel.com.
19. Package meets Level 2 moisture sensitivity classification, and is shipped in dry-pack.
20. Exposed pads must be soldered to a ground for proper thermal management.
MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA
TEL +1 (408) 944-0800 FAX +1 (408) 474-1000 WEB http://www.micrel.com
Micrel makes no representations or warranties with respect to the accuracy or completeness of the information furnished in this data sheet. This
information is not intended as a warranty and Micrel does not assume responsibility for its use. Micrel reserves the right to change circuitry,
specifications and descriptions at any time without notice. No license, whether express, implied, arising by estoppel or otherwise, to any intellectual
property rights is granted by this document. Except as provided in Micrel’s terms and conditions of sale for such products, Micrel assumes no liability
whatsoever, and Micrel disclaims any express or implied warranty relating to the sale and/or use of Micrel products including liability or warranties
relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right.
Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product
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implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. A
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© 2014 Micrel, Incorporated.
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