SY89871UMG

SY89871U 2.5GHz Any Diff. In-To-LVPECL Programmable Clock Divider/Fanout Buffer w/ Internal Termination General Description The SY89871U is a 2.5V/3.3V LVPECL output precision clock divider capable of accepting a high-speed differential clock input (AC or DC-coupled) CML, LVPECL, HSTL or LVDS clock input signal and dividing down the frequency using a programmable divider ratio to create a frequencylocked lower speed version of the input clock (Bank B). Available divider ratios are 2, 4, 8, and 16. In a typical 622MHz clock system this would provide availability of 311MHz, 115MHz, 77MHz, or 38MHz auxiliary clock components. The differential input buffer has a unique internal termination design that allows access to the termination network through a VT pin. This feature allows the device to easily interface to different logic standards. A VREF-AC reference is included for AC-coupled applications. The SY89871U includes two phase-matched output banks. Bank A (QA) is a frequency-matched copy of the input. Bank B (QB0, QB1) is a divided down output of the input frequency. Bank A and Bank B maintain a matched delay independent of the divider setting. Data sheets and support documentation can be found on Micrel’s web site at: www.micrel.com. Typical Performance Precision Edge Features  Two matched-delay outputs: - Bank A: undivided pass-through (QA) - Bank B: programmable divide by 2, 4, 8, 16 (QB0, QB1)  Matched delay: all outputs have matched delay, independent of divider setting  Guaranteed AC performance: - >2.5GHz fMAX -