SY89873LMI

Precision Edge® 3.3V, 2.0GHz ANY DIFF. IN-TO-LVDS SY89873L ® Precision Edge PROGRAMMABLE CLOCK DIVIDER SY89873L FANOUT BUFFER W/ INTERNAL TERMINATION Micrel, Inc. FEATURES Guaranteed AC performance • > 2.0GHz fMAX output toggle • > 3.0GHz fMAX input • < 800ps tPD (matched-delay between banks) • < 15ps within-device skew • < 190ps rise/fall time Low jitter design • < 1psRMS cycle-to-cycle jitter Precision Edge® DESCRIPTION This 3.3V low-skew, low-jitter, precision LVDS output clock divider accepts any high-speed differential clock input (AC- or DC-coupled) CML, LVPECL, HSTL or LVDS and divides down the frequency using a programmable divider ratio to create a frequency-locked, lower speed version of the input clock. The SY89873L includes two output banks. Bank A is an exact copy of the input clock (pass through) with matched propagation delay to Bank B, the divided output bank. Available divider ratios are 2, 4, 8 and 16. In a typical 622MHz clock system this would provide availability of 311MHz, 155MHz, 77MHz or 38MHz auxiliary clock components. The differential input buffer has a unique internal termination design that allows access to the termination network through a VT pin. This feature allows the device to easily interface to all AC- or DC-coupled differential logic standards. A VREF-AC reference is included for AC-coupled applications. The SY89873L is part of Micrel’s high-speed Precision Edge® timing and distribution family. For 2.5V applications, consider the SY89872U. For applications that require an LVPECL output, consider the SY89871U. The /RESET input asynchronously resets the divider outputs (Bank B). In the pass-through function (Bank A) the /RESET synchronously enables or disables the outputs on the next falling edge of IN (rising edge of /N). Refer to the Timing Diagram. All support documentation can be found on Micrel’s web site at: www.micrel.com. Unique input termination and VT pin for DC-coupled and AC-coupled inputs: any differential inputs (LVPECL, LVDS, CML, HSTL) Precision differential LVDS outputs Matched delay: all outputs have matched delay, independent of divider setting TTL/CMOS inputs for select and reset/disable Two LVDS output banks (matched delay) • Bank A: Buffered copy of input clock (undivided) • Bank B: Divided output (÷2, ÷4, ÷8, ÷16), two copies 3.3V power supply Wide operating temperature range: –40°C to +85°C Available in 16-pin (3mm × 3mm) QFN package APPLICATIONS SONET/SDH line cards Transponders High-end, multiprocessor servers FUNCTIONAL BLOCK DIAGRAM TYPICAL APPLICATION 622MHz/155.5MHz SONET Clock Generator Enable FF /RESET Enable MUX VREF-AC QA /QA 622MHz LVPECL IN Clock In /IN IN VT QB0 50Ω Divided by 2, 4, 8 or 16 50Ω /IN /QB0 QB1 OC-12 or OC-3 Clock Gen QA /QA 622MHz LVDS Clock Out QB 155.5MHz LVDS Clock Out /QB Bank B: 155.5MHz: For OC-3 line card Set to divide-by-4 /QB1 Bank A: 622MHz: For OC-12 line card Set to pass-through S0 Decoder S1 United States Patent No. RE44,134 Precision Edge is a registered trademark of Micrel, Inc. M9999-082407 hbwhelp@micrel.com or (408) 955-1690 1 Rev.: F Amendment: /0 Issue Date: February 2007 Precision Edge® SY89873L Micrel, Inc. S0 S1 VCC GND PACKAGE/ORDERING INFORMATION 16 15 14 13 Ordering Information(1) 12 IN 2 11 VT QB1 3 10 VREF-AC /QB1 4 9 VCC 7 /IN 8 Package Marking Lead Finish SY89873LMG QFN-16 Industrial 873L with Pb-Free bar line indicator NiPdAu Pb-Free SY89873LMGTR(2) QFN-16 Industrial 873L with Pb-Free bar line indicator NiPdAu Pb-Free Notes: 1. Contact factory for die availability. Dice are guaranteed at TA = 25°C, DC Electricals only. 2. Tape and Reel. /RESET /DISABLE 6 /QA 1 QA QB0 /QB0 5 Package Operating Type Range Part Number 16-Pin QFN PIN DESCRIPTION Pin Number Pin Name Pin Function 1, 2, 3, 4 QB0, /QB0 QB1, /QB1 Differential Buffered Output Clocks: Divide by 2, 4, 8, 16. LVDS compatible. 5, 6 QA, /QA 7, 14 VCC 8 /RESET, /DISABLE 12, 9 IN, /IN 10 VREF-AC 11 VT 13 GND 16, 15 S0, S1 Differential Buffered Undivided Output Clock: LVDS compatible. Positive Power Supply: Bypass with 0.1µF//0.01µF low ESR capacitors. TTL/CMOS Compatible Output Reset and Disable: Internal 25kΩ pull-up. Input threshold is VCC/2. Logic LOW will reset the divider select, and align Bank A and Bank B edges. In addition, when LOW, Banks A and B will be disabled. Differential Input: Internal 50Ω termination resistors to VT input. See “Input Interface Applications” section. Reference Voltage: Equal to VCC–1.4V (approx.), and used for AC-coupled applications. Maximum sink/source current is 0.5mA. See “Input Interface Applications” section. Termination Center-Tap: For CML and LVDS inputs, leave this pin floating. Otherwise, see “Input Interface Applications” section. Ground: Exposed pad is internally connected to GND and must be connected to a ground plane for proper thermal operation. Select Pins: LVTTL/CMOS logic levels. Internal 25kΩ pull-up resistor. Logic HIGH if left unconnected (divided by 16 mode). S0 = LSB. Input threshold is VCC/2. TRUTH TABLE /RESET /DISABLE S1 S0 Bank A Output Bank B Outputs 1 0 0 Input Clock Input Clock ÷ 2 1 0 1 Input Clock Input Clock ÷ 4 1 1 0 Input Clock Input Clock ÷ 8 1 1 1 Input Clock Input Clock ÷ 16 0 X X QA = LOW, /QA = Notes: 1. On the next negative transition of the input signal. 2. Asynchronous Reset/Disable function. See "Timing Diagram." M9999-082407 hbwhelp@micrel.com or (408) 955-1690 2 HIGH(1) QB0 = LOW, /QB0 = HIGH(2) QB1 = LOW, /QB1 = HIGH(2) Precision Edge® SY89873L Micrel, Inc. Absolute Maximum Ratings(1) Operating Ratings(2) Supply Voltage (VCC) .................................. –0.5V to +4.0V Input Voltage (VIN) .................................. –0.5V to VCC+0.3 LVDS Output Current (IOUT) .................................... ±10mA Input Current IN, /IN (IIN) .......................................... ±50mA VREF-AC Input Sink/Source Current (IVREF-AC)(3) ............ ±2mA Lead Temperature (soldering, 20 sec.) ..................... 260°C Storage Temperature (TS) ....................... –65°C to +150°C Supply Voltage (VCC) ...................................... +3.3V ±10% Ambient Temperature (TA) ......................... –40°C to +85°C Package Thermal Resistance QFN (θJA) Still-Air ............................................................. 60°C/W 500 lfpm ........................................................... 54°C/W QFN (ΨJB)(4) Junction-to-Board ............................................ 38°C/W DC ELECTRICAL CHARACTERISTICS(5) TA= –40°C to +85°C; Unless otherwise stated. Symbol Parameter Condition Min Typ Max Units VCC Power Supply 3.0 3.3 3.6 V ICC Power Supply Current 85 115 mA RIN Differential Input Resistance (IN-to-/IN) 100 110 Ω VIH Input High Voltage IN, /IN Note 6 0.1 VCC+0.3 V VIL Input Low Voltage IN, /IN Note 6 –0.3 VCC V VIN Input Voltage Swing Notes 6, 7 0.1 3.6 V VDIFF_IN Differential Input Voltage Swing Notes 6, 7, 8 0.2 |IIN| Input Current IN, /IN Note 6 VREF-AC Reference Voltage Note 9 No load, Max VCC 90 V 45 VCC –1.525 VCC–1.425 VCC–1.325 mA V Notes: 1. Permanent device damage may occur if “Absolute Maximum Ratings” are exceeded. This is a stress rating only and functional operation is not implied at conditions other than those detailed in the operational sections of this data sheet. Exposure to “Absolute Maximum Ratings” conditions for extended periods may affect device reliability. 2. The data sheet limits are not guaranteed if the device is operated beyond the operating ratings. 3. Due to the limited drive capability use for input of the same package only. 4. Junction-to-board resistance assumes exposed pad is soldered (or equivalent) to the device’s most negative potential on the PCB. 5. The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. 6. Due to the internal termination (see “Input Buffer Structure” ) the input current depends on the applied voltages at IN, /IN and VT inputs. Do not apply a combination of voltages that causes the input current to exceed the maximum limit! 7. See “Timing Diagram” for VIN definition. VIN(max) is specified when VT is floating. 8. See Figures 1c and 1d for VDIFF definition. 9. Operating using VIN is limited to AC-coupled PECL or CML applications only. Connect directly to VT pin. M9999-082407 hbwhelp@micrel.com or (408) 955-1690 3 Precision Edge® SY89873L Micrel, Inc. LVDS OUTPUT DC ELECTRICAL CHARACTERISTICS(10) VCC = 3.3V ±10%; TA = –40°C to +85°C; Unless otherwise stated. Symbol Parameter Condition Min Typ Max Units VOUT Output Voltage Swing Notes 11, 12 250 350 450 mV VOH Output High Voltage Note 11 1.475 V VOL Output Low Voltage Note 11 0.925 VOCM Output Common Mode Voltage Note 11 1.125 1.275 V –50 50 mV Max Units VOCM Change in Common Mode Voltage V LVTTL/CMOS DC ELECTRICAL CHARACTERISTICS(10) VCC = 3.3V ±10%; TA = –40°C to +85°C; Unless otherwise stated. Symbol Parameter VIH Input HIGH Voltage VIL Input LOW Voltage IIH Input HIGH Current IIL Input LOW Current Condition Min Typ 2.0 –125 Notes: 10. The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. 11. Measured as per Figure 1a, 100 across Q and /Q outputs. 12. See Figure 1c. M9999-082407 hbwhelp@micrel.com or (408) 955-1690 4 V 0.8 V 20 μA –300 μA Precision Edge® SY89873L Micrel, Inc. AC ELECTRICAL CHARACTERISTICS(13) VCC = 3.3V ±10%; TA = –40°C to +85°C; Unless otherwise stated. Symbol Parameter Condition Min fMAX Maximum Output Toggle Frequency (Bank A and Bank B) Output Swing: ≥ 200mV 2.0 GHz Maximum Input Frequency Note 14 3.2 GHz Differential Propagation Delay (IN-to-Q) Input Swing < 400mV 550 660 800 ps Input Swing ≥ 400mV 500 610 750 ps Within-Device Skew (diff.) (QB0-to-QB1) Note 15 7 15 ps Within-Device Skew (diff.) (Bank A-to-Bank B) Note 15 12 30 ps Part-to-Part Skew (diff.) Note 15 250 ps trr Reset Recovery Time Note 16 Tjitter Cycle-to-Cycle Jitter Note 17 tr, tf Rise / Fall Time (20% to 80%) tPD tSKEW Typ Max 600 60 Units ps 110 1 psRMS 190 ps Notes: 13. Measured with 400mV input signal, 50% duty cycle. All outputs terminated with 100Ω between Q and /Q, unless otherwise stated. 14. Bank A (pass-through) maximum frequency is limited by the output stage. Bank B (input-to-output ÷2, ÷4, ÷8, ÷16) can accept an input frequency >3GHz, while Bank A will be slew-rate limited. 15. Skew is measured between outputs under identical transitions. 16. See “Timing Diagram.” 17. Cycle-to-cycle jitter definition: the variation in period between adjacent cycles over a random sample of adjacent cycle pairs. Tjitter_cc=Tn–Tn+1, where T is the time between rising edges of the output signal. M9999-082407 hbwhelp@micrel.com or (408) 955-1690 5 Precision Edge® SY89873L Micrel, Inc. LVDS OUTPUT 501 ±1% VOUT VOH, VOL 1001 ±1% 501 ±1% VOH, VOL GND VOCM, 6VOCM GND Figure 1a. LVDS Differential Measurement Figure 1b. LVDS Common Mode Measurement DEFINITION OF SINGLE-ENDED AND DIFFERENTIAL SWING VDIFF_IN, VDIFF_OUT 700mV (Typical) VIN, VOUT 350mV (Typical) Figure 1d. Differential Swing Figure 1c. Single-Ended Swing TIMING DIAGRAM VCC/2 /RESET tRR IN /IN VIN (Swing) tPD QB VOUT (Swing) /QB QA /QA M9999-082407 hbwhelp@micrel.com or (408) 955-1690 6 Precision Edge® SY89873L Micrel, Inc. TYPICAL OPERATING CHARACTERISTICS VCC = 3.3V, VIN = 400mV, TA = 25°C, unless otherwise stated. Output Amplitude vs. Frequency 800 PROPAGATION DELAY (ps) QA AMPLITUDE (mV) 350 300 250 200 150 100 50 0 0 800 PROPAGATION DELAY (ps) 700 600 500 400 500 1000 1500 2000 2500 FREQUENCY (MHz) Nominal Propagation Delay vs. Temperature 700 600 500 400 -40 -20 0 20 40 60 80 100 120 TEMPERATURE (°C) M9999-082407 hbwhelp@micrel.com or (408) 955-1690 7 Nominal Propagation Delay vs. Input Swing 0 200 400 600 800 1000 1200 INPUT SWING (mV) Precision Edge® SY89873L Micrel, Inc. FUNCTIONAL CHARACTERISTICS Conditions: VCC = 3.3V, TA = 25°C, unless otherwise stated. QA Output @ 1.25GHz QA @ 622MHz and QB @ 155.5MHz (Divided-by-4) /QA Output Swing (50mV/div.) Output Swing (100mV/div.) QA 622MHz QB ÷4 /QB 155MHz TIME (100ps/div.) TIME (1ns/div.) QA Output @ 2.0GHz Output Swing (50mV/div.) Q /Q TIME (100ps/div.) M9999-082407 hbwhelp@micrel.com or (408) 955-1690 8 Precision Edge® SY89873L Micrel, Inc. INPUT BUFFER STRUCTURE VCC VCC 1.86k1 1.86k1 1.86k1 25k1 R S0 S1 /RESET 1.86k1 R IN 501 VT 501 GND GND /IN Figure 2a. Simplified Differential Input Stage M9999-082407 hbwhelp@micrel.com or (408) 955-1690 Figure 2b. Simplified TTL/CMOS Input 9 Precision Edge® SY89873L Micrel, Inc. INPUT INTERFACE APPLICATIONS VCC = 3.3V VCC = 3.3V VCC = 3.3V VCC = 3.3V VCC = 3.3V VCC = 3.3V IN LVPECL IN IN /IN /IN NC NC GND SY89873L SY89873L GND /IN CML CML GND VCC VT .01µF VT VCC = 3.3V Figure 3b. AC-Coupled CML Input Interface VCC = 3.3V VCC = 3.3V VREF-AC Figure 3c. DC-Coupled LVPECL Input Interface VCC = 3.3V IN IN LVPECL LVDS /IN 100Ω GND /IN SY89873L 100Ω VCC GND VT * Bypass with 0.01µF to VCC 0.01µF Figure 3a. DC-Coupled CML Input Interface 50Ω NC SY89873L VCC VREF-AC VREF-AC VCC–2V* VT VREF-AC SY89873L GND NC VT NC VREF-AC 0.01µF Figure 3d. AC-Coupled LVPECL Input Interface Figure 3e. LVDS Input Interface RELATED MICREL PRODUCTS AND SUPPORT DOCUMENTATION Part Number Function Data Sheet Link SY89871U 2.5GHz Any Diff. In-to-LVPECL Programmable Clock Divider/Fanout Buffer w/Internal Termination www.micrel.com/product-info/products/sy89871u.shtml SY89872U 2.5V 2GHz Any Diff. In-to-LVDS Programmable Clock Divider/Fanout Buffer w/Internal Termination www.micrel.com/product-info/products/sy89872u.shtml HBW Solutions New Products and Applications www.micrel.com/product-info/products/solutions.shtml M9999-082407 hbwhelp@micrel.com or (408) 955-1690 10 Precision Edge® SY89873L Micrel, Inc. 16-PIN QFN (QFN-16) Package EP- Exposed Pad Die CompSide Island Heat Dissipation Heat Dissipation Heavy Copper Plane Heavy Copper Plane VEE VEE PCB Thermal Consideration for 16-Pin QFN Package (Always solder, or equivalent, the exposed pad to the PCB) Package Notes: 1. Package meets Level 2 moisture sensitivity classification, and is shipped in dry-pack form. 2. Exposed pads must be soldered to a ground for proper thermal management. MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA TEL + 1 (408) 944-0800 FAX + 1 (408) 474-1000 WEB http://www.micrel.com The information furnished by Micrel in this data sheet is believed to be accurate and reliable. However, no responsibility is assumed by Micrel for its use. Micrel reserves the right to change circuitry and specifications at any time without notification to the customer. Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product can reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. A Purchaser’s use or sale of Micrel Products for use in life support appliances, devices or systems is at Purchaser’s own risk and Purchaser agrees to fully indemnify Micrel for any damages resulting from such use or sale. © 2006 Micrel, Incorporated. M9999-082407 hbwhelp@micrel.com or (408) 955-1690 11