T89C51CC01UA-RLTIM

Features • • • • • • • • • • • • • • • • • • • • 1. 80C51 Core Architecture 256 Bytes of On-chip RAM 1K Bytes of On-chip XRAM 32K Bytes of On-chip Flash Memory – Data Retention: 10 Years at 85°C Erase/Write Cycle: 100K Boot Code Section with Independent Lock Bits 2K Bytes of On-chip Flash for Bootloader In-System Programming by On-Chip Boot Program (CAN, UART) and IAP Capability 2K Bytes of On-chip EEPROM Erase/Write Cycle: 100K 14-sources 4-level Interrupts Three 16-bit Timers/Counters Full Duplex UART Compatible 80C51 Maximum Crystal Frequency 40 MHz, in X2 Mode, 20 MHz (CPU Core, 20 MHz) Five Ports: 32 + 2 Digital I/O Lines Five-channel 16-bit PCA with: – PWM (8-bit) – High-speed Output – Timer and Edge Capture Double Data Pointer 21-bit Watchdog Timer (7 Programmable Bits) A 10-bit Resolution Analog to Digital Converter (ADC) with 8 Multiplexed Inputs Full CAN Controller: – Fully Compliant with CAN Rev2.0A and 2.0B – Optimized Structure for Communication Management (Via SFR) – 15 Independent Message Objects: Each Message Object Programmable on Transmission or Reception Individual Tag and Mask Filters up to 29-bit Identifier/Channel 8-byte Cyclic Data Register (FIFO)/Message Object 16-bit Status and Control Register/Message Object 16-bit Time-Stamping Register/Message Object CAN Specification 2.0 Part A or 2.0 Part B Programmable for Each Message Object Access to Message Object Control and Data Registers Via SFR Programmable Reception Buffer Length Up To 15 Message Objects Priority Management of Reception of Hits on Several Message Objects at the Same Time (Basic CAN Feature) Priority Management for Transmission Message Object Overrun Interrupt – Supports: Time Triggered Communication Autobaud and Listening Mode Programmable Automatic Reply Mode – 1-Mbit/s Maximum Transfer Rate at 8 MHz (1) Crystal Frequency in X2 Mode – Readable Error Counters – Programmable Link to On-chip Timer for Time Stamping and Network Synchronization – Independent Baud Rate Prescaler – Data, Remote, Error and Overload Frame Handling On-chip Emulation Logic (Enhanced Hook System) Power Saving Modes: – Idle Mode – Power-down Mode At BRP = 1 sampling point will be fixed. Enhanced 8-bit Microcontroller with CAN Controller and Flash Memory T89C51CC01 AT89C51CC01 Rev. 4129N–CAN–03/08 1 • Power Supply: 3V to 5.5V • Temperature Range: Industrial (-40° to +85°C) • Packages: VQFP44, PLCC44 Description The T89C51CC01 is the first member of the CANaryTM family of 8-bit microcontrollers dedicated to CAN network applications. In X2 mode a maximum external clock rate of 20 MHz reaches a 300 ns cycle time. Besides the full CAN controller T89C51CC01 provides 32K Bytes of Flash memory including In-System-Programming (ISP), 2K Bytes Boot Flash Memory, 2K Bytes EEPROM and 1.2-Kbyte RAM. Special attention is paid to the reduction of the electro-magnetic emission of T89C51CC01. TxDC RxDC T2 T2EX PCA ECI Vss Vcc TxD RxD Block Diagram XTAL1 ALE PSEN RAM 256x8 UART XTAL2 C51 CORE XRAM Flash Boot EE 32kx loader PROM 8 2kx8 2kx8 1kx8 PCA Timer 2 CAN CONTROLLER IB-bus CPU EA Notes: 2 VAGND VAVCC 10 bit ADC VAREF P4(2) P3 P2 INT1 INT0 T1 T0 RESET WR Parallel I/O Ports and Ext. Bus Watch Dog Port 0 Port 1 Port 2 Port 3 Port 4 P1(1) INT Ctrl P0 Timer 0 Timer 1 RD 1. 8 analog Inputs/8 Digital I/O 2. 2-Bit I/O Port A/T89C51CC01 4129N–CAN–03/08 A/T89C51CC01 6 5 4 3 2 1 44 43 42 41 40 P1.3/AN3/CEX0 P1.2/AN2/ECI P1.1/AN1/T2EX P1.0/AN 0/T2 VAREF VAGND RESET VSS VCC XTAL1 XTAL2 Pin Configuration 7 8 9 10 11 12 13 14 15 16 17 39 38 37 36 35 34 33 32 31 30 29 PLCC44 ALE PSEN P0.7/AD7 P0.6/AD6 P0.5/AD5 P0.4/AD4 P0.3/AD3 P0.2/AD2 P0.1/AD1 P0.0/AD0 P2.0/A8 P1.3/AN3/CEX0 P1.2/AN2/ECI P1.1/AN1/T2EX P1.0/AN 0/T2 VAREF VAGND RESET VSS VCC XTAL1 XTAL2 P3.6/WR P3.7/RD P4.0/ TxDC P4.1/RxDC P2.7/A15 P2.6/A14 P2.5/A13 P2.4/A12 P2.3/A11 P2.2/A10 P2.1/A9 18 19 20 21 22 23 24 25 26 27 28 P1.4/AN4/CEX1 P1.5/AN5/CEX2 P1.6/AN6/CEX3 P1.7/AN7/CEX4 EA P3.0/RxD P3.1/TxD P3.2/INT0 P3.3/INT1 P3.4/T0 P3.5/T1 44 43 42 41 40 39 38 37 36 35 34 P1.4/AN4/CEX1 P1.5/AN5/CEX2 P1.6/AN6/CEX3 P1.7/AN7/CEX4 EA P3.0/RxD P3.1/TxD P3.2/INT0 P3.3/INT1 P3.4/T0 P3.5/T1 2 33 32 3 4 30 1 5 6 7 8 31 VQFP44 29 28 27 9 26 25 10 24 11 23 ALE PSEN P0.7/AD7 P0.6/AD6 P0.5/AD5 P0.4 /AD4 P0.3 /AD3 P0.2 /AD2 P0.1 /AD1 P0.0 /AD0 P2.0/A8 P3.6/WR P3.7/RD P4.0/TxDC P4.1/RxDC P2.7/A15 P2.6/A14 P2.5/A13 P2.4/A12 P2.3/A11 P2.2/A10 P2.1/A9 12 13 14 15 16 17 18 19 20 21 22 3 4129N–CAN–03/08 I/O Configurations Each Port SFR operates via type-D latches, as illustrated in Figure 1 for Ports 3 and 4. A CPU "write to latch" signal initiates transfer of internal bus data into the type-D latch. A CPU "read latch" signal transfers the latched Q output onto the internal bus. Similarly, a "read pin" signal transfers the logical level of the Port pin. Some Port data instructions activate the "read latch" signal while others activate the "read pin" signal. Latch instructions are referred to as Read-Modify-Write instructions. Each I/O line may be independently programmed as input or output. Port 1, Port 3 and Port 4 Figure 1 shows the structure of Ports 1 and 3, which have internal pull-ups. An external source can pull the pin low. Each Port pin can be configured either for general-purpose I/O or for its alternate input output function. To use a pin for general-purpose output, set or clear the corresponding bit in the Px register (x = 1,3 or 4). To use a pin for general-purpose input, set the bit in the Px register. This turns off the output FET drive. To configure a pin for its alternate function, set the bit in the Px register. When the latch is set, the "alternate output function" signal controls the output level (see Figure 1). The operation of Ports 1, 3 and 4 is discussed further in the "quasi-Bidirectional Port Operation" section. Figure 1. Port 1, Port 3 and Port 4 Structure VCC ALTERNATE OUTPUT FUNCTION READ LATCH INTERNAL BUS WRITE TO LATCH READ PIN Note: Port 0 and Port 2 INTERNAL PULL-UP (1) P1.x P3.x P4.x D P1.X Q P3.X P4.X LATCH CL ALTERNATE INPUT FUNCTION The internal pull-up can be disabled on P1 when analog function is selected. Ports 0 and 2 are used for general-purpose I/O or as the external address/data bus. Port 0, shown in Figure 3, differs from the other Ports in not having internal pull-ups. Figure 3 shows the structure of Port 2. An external source can pull a Port 2 pin low. To use a pin for general-purpose output, set or clear the corresponding bit in the Px register (x = 0 or 2). To use a pin for general-purpose input, set the bit in the Px register to turn off the output driver FET. 4 A/T89C51CC01 4129N–CAN–03/08 A/T89C51CC01 Figure 2. Port 0 Structure ADDRESS LOW/ CONTROL DATA VDD (2) READ LATCH P0.x (1) 1 INTERNAL BUS WRITE TO LATCH D P0.X LATCH Q 0 READ PIN Notes: 1. Port 0 is precluded from use as general-purpose I/O Ports when used as address/data bus drivers. 2. Port 0 internal strong pull-ups assist the logic-one output for memory bus cycles only. Except for these bus cycles, the pull-up FET is off, Port 0 outputs are open-drain. Figure 3. Port 2 Structure ADDRESS HIGH/ CONTROL VDD INTERNAL PULL-UP (2) READ LATCH P2.x (1) 1 INTERNAL BUS WRITE TO LATCH D P2.X LATCH Q 0 READ PIN Notes: 1. Port 2 is precluded from use as general-purpose I/O Ports when as address/data bus drivers. 2. Port 2 internal strong pull-ups FET (P1 in FiGURE) assist the logic-one output for memory bus cycle. When Port 0 and Port 2 are used for an external memory cycle, an internal control signal switches the output-driver input from the latch output to the internal address/data line. Read-Modify-Write Instructions Some instructions read the latch data rather than the pin data. The latch based instructions read the data, modify the data and then rewrite the latch. These are called "ReadModify-Write" instructions. Below is a complete list of these special instructions (see Table ). When the destination operand is a Port or a Port bit, these instructions read the latch rather than the pin: 5 4129N–CAN–03/08 Table 1. Read-Modify-Write Instructions Instruction Description Example ANL logical AND ANL P1, A ORL logical OR ORL P2, A XRL logical EX-OR XRL P3, A JBC jump if bit = 1 and clear bit JBC P1.1, LABEL CPL complement bit CPL P3.0 INC increment INC P2 DEC decrement DEC P2 DJNZ decrement and jump if not zero DJNZ P3, LABEL MOV Px.y, C move carry bit to bit y of Port x MOV P1.5, C CLR Px.y clear bit y of Port x CLR P2.4 SET Px.y set bit y of Port x SET P3.3 It is not obvious the last three instructions in this list are Read-Modify-Write instructions. These instructions read the port (all 8 bits), modify the specifically addressed bit and write the new byte back to the latch. These Read-Modify-Write instructions are directed to the latch rather than the pin in order to avoid possible misinterpretation of voltage (and therefore, logic) levels at the pin. For example, a Port bit used to drive the base of an external bipolar transistor can not rise above the transistor’s base-emitter junction voltage (a value lower than VIL). With a logic one written to the bit, attempts by the CPU to read the Port at the pin are misinterpreted as logic zero. A read of the latch rather than the pins returns the correct logic-one value. Quasi-Bidirectional Port Operation Port 1, Port 2, Port 3 and Port 4 have fixed internal pull-ups and are referred to as "quasi-bidirectional" Ports. When configured as an input, the pin impedance appears as logic one and sources current in response to an external logic zero condition. Port 0 is a "true bidirectional" pin. The pins float when configured as input. Resets write logic one to all Port latches. If logical zero is subsequently written to a Port latch, it can be returned to input conditions by a logical one written to the latch. Note: Port latch values change near the end of Read-Modify-Write instruction cycles. Output buffers (and therefore the pin state) update early in the instruction after Read-ModifyWrite instruction cycle. Logical zero-to-one transitions in Port 1, Port 2, Port 3 and Port 4 use an additional pullup (p1) to aid this logic transition (see Figure 4.). This increases switch speed. This extra pull-up sources 100 times normal internal circuit current during 2 oscillator clock periods. The internal pull-ups are field-effect transistors rather than linear resistors. Pullups consist of three p-channel FET (pFET) devices. A pFET is on when the gate senses logical zero and off when the gate senses logical one. pFET #1 is turned on for two oscillator periods immediately after a zero-to-one transition in the Port latch. A logical one at the Port pin turns on pFET #3 (a weak pull-up) through the inverter. This inverter and pFET pair form a latch to drive logical one. pFET #2 is a very weak pull-up switched on whenever the associated nFET is switched off. This is traditional CMOS switch convention. Current strengths are 1/10 that of pFET #3. 6 A/T89C51CC01 4129N–CAN–03/08 A/T89C51CC01 Figure 4. Internal Pull-Up Configurations 2 Osc. PERIODS VCC VCC VCC p1(1) p2 p3 P1.x P2.x P3.x P4.x OUTPUT DATA n INPUT DATA READ PIN Note: Port 2 p1 assists the logic-one output for memory bus cycles. 7 4129N–CAN–03/08 SFR Mapping The Special Function Registers (SFRs) of the T89C51CC01 fall into the following categories: Table 2. C51 Core SFRs Mnemonic Add Name 7 6 5 4 3 2 1 0 ACC E0h Accumulator – – – – – – – – B F0h B Register – – – – – – – – PSW D0h Program Status Word CY AC F0 RS1 RS0 OV F1 P SP 81h Stack Pointer – – – – – – – – DPL 82h Data Pointer Low byte – – – – – – – – – – – – – – – – LSB of DPTR DPH 83h Data Pointer High byte MSB of DPTR Table 3. I/O Port SFRs Mnemonic Add Name 7 6 5 4 3 2 1 0 P0 80h Port 0 – – – – – – – – P1 90h Port 1 – – – – – – – – P2 A0h Port 2 – – – – – – – – P3 B0h Port 3 – – – – – – – – P4 C0h Port 4 (x2) – – – – – – – – Table 4. Timers SFRs Mnemonic Add Name 7 6 5 4 3 2 1 0 TH0 8Ch Timer/Counter 0 High byte – – – – – – – – TL0 8Ah Timer/Counter 0 Low byte – – – – – – – – TH1 8Dh Timer/Counter 1 High byte – – – – – – – – TL1 8Bh Timer/Counter 1 Low byte – – – – – – – – TH2 CDh Timer/Counter 2 High byte – – – – – – – – TL2 CCh Timer/Counter 2 Low byte – – – – – – – – TCON 88h Timer/Counter 0 and 1 control TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0 TMOD 89h Timer/Counter 0 and 1 Modes GATE1 C/T1# M11 M01 GATE0 C/T0# M10 M00 8 A/T89C51CC01 4129N–CAN–03/08 A/T89C51CC01 Table 4. Timers SFRs (Continued) Mnemonic Add Name 7 6 5 4 3 2 1 0 T2CON C8h Timer/Counter 2 control TF2 EXF2 RCLK TCLK EXEN2 TR2 C/T2# CP/RL2# T2MOD C9h Timer/Counter 2 Mode – – – – – – T2OE DCEN RCAP2H Timer/Counter 2 CBh Reload/Capture High byte – – – – – – – – RCAP2L Timer/Counter 2 CAh Reload/Capture Low byte – – – – – – – – WDTRST A6h Watchdog Timer Reset – – – – – – – – WDTPRG A7h Watchdog Timer Program – – – – – S2 S1 S0 7 6 5 4 3 2 1 0 FE/SM0 SM1 SM2 REN TB8 RB8 TI RI – – – – – – – – Table 5. Serial I/O Port SFRs Mnemonic Add Name SCON 98h Serial Control SBUF 99h Serial Data Buffer SADEN B9h Slave Address Mask – – – – – – – – SADDR A9h Slave Address – – – – – – – – Table 6. PCA SFRs Mnemonic Add Name 7 6 5 4 3 2 1 0 CCON D8h PCA Timer/Counter Control CF CR – CCF4 CCF3 CCF2 CCF1 CCF0 CMOD D9h PCA Timer/Counter Mode CIDL WDTE – – – CPS1 CPS0 ECF CL E9h PCA Timer/Counter Low byte – – – – – – – – CH F9h PCA Timer/Counter High byte – – – – – – – – CCAPM0 DAh PCA Timer/Counter Mode 0 ECOM0 CAPP0 CAPN0 MAT0 TOG0 PWM0 ECCF0 CCAPM1 DBh PCA Timer/Counter Mode 1 ECOM1 CAPP1 CAPN1 MAT1 TOG1 PWM1 ECCF1 CCAPM2 DCh PCA Timer/Counter Mode 2 ECOM2 CAPP2 CAPN2 MAT2 TOG2 PWM2 ECCF2 CCAPM3 DDh PCA Timer/Counter Mode 3 ECOM3 CAPP3 CAPN3 MAT3 TOG3 PWM3 ECCF3 CCAPM4 DEh PCA Timer/Counter Mode 4 ECOM4 CAPP4 CAPN4 MAT4 TOG4 PWM4 ECCF4 – CCAP0H FAh PCA Compare Capture Module 0 H CCAP0H7 CCAP0H6 CCAP0H5 CCAP0H4 CCAP0H3 CCAP0H2 CCAP0H1 CCAP0H0 CCAP1H FBh PCA Compare Capture Module 1 H CCAP1H7 CCAP1H6 CCAP1H5 CCAP1H4 CCAP1H3 CCAP1H2 CCAP1H1 CCAP1H0 CCAP2H FCh PCA Compare Capture Module 2 H CCAP2H7 CCAP2H6 CCAP2H5 CCAP2H4 CCAP2H3 CCAP2H2 CCAP2H1 CCAP2H0 CCAP3H FDh PCA Compare Capture Module 3 H CCAP3H7 CCAP3H6 CCAP3H5 CCAP3H4 CCAP3H3 CCAP3H2 CCAP3H1 CCAP3H0 CCAP4H FEh PCA Compare Capture Module 4 H CCAP4H7 CCAP4H6 CCAP4H5 CCAP4H4 CCAP4H3 CCAP4H2 CCAP4H1 CCAP4H0 9 4129N–CAN–03/08 Table 6. PCA SFRs (Continued) Mnemonic Add Name 7 6 5 4 3 2 1 0 CCAP0L EAh PCA Compare Capture Module 0 L CCAP0L7 CCAP0L6 CCAP0L5 CCAP0L4 CCAP0L3 CCAP0L2 CCAP0L1 CCAP0L0 CCAP1L EBh PCA Compare Capture Module 1 L CCAP1L7 CCAP1L6 CCAP1L5 CCAP1L4 CCAP1L3 CCAP1L2 CCAP1L1 CCAP1L0 CCAP2L ECh PCA Compare Capture Module 2 L CCAP2L7 CCAP2L6 CCAP2L5 CCAP2L4 CCAP2L3 CCAP2L2 CCAP2L1 CCAP2L0 CCAP3L EDh PCA Compare Capture Module 3 L CCAP3L7 CCAP3L6 CCAP3L5 CCAP3L4 CCAP3L3 CCAP3L2 CCAP3L1 CCAP3L0 CCAP4L EEh PCA Compare Capture Module 4 L CCAP4L7 CCAP4L6 CCAP4L5 CCAP4L4 CCAP4L3 CCAP4L2 CCAP4L1 CCAP4L0 Table 7. Interrupt SFRs Mnemonic Add Name 7 6 5 4 3 2 1 0 IEN0 A8h Interrupt Enable Control 0 EA EC ET2 ES ET1 EX1 ET0 EX0 IEN1 E8h Interrupt Enable Control 1 – – – – – ETIM EADC ECAN IPL0 B8h Interrupt Priority Control Low 0 – PPC PT2 PS PT1 PX1 PT0 PX0 IPH0 B7h Interrupt Priority Control High 0 – PPCH PT2H PSH PT1H PX1H PT0H PX0H IPL1 F8h Interrupt Priority Control Low 1 – – – – – POVRL PADCL PCANL IPH1 F7h Interrupt Priority Control High1 – – – – – POVRH PADCH PCANH Table 8. ADC SFRs Mnemonic Add Name 7 6 5 4 3 2 1 0 ADCON F3h ADC Control – PSIDLE ADEN ADEOC ADSST SCH2 SCH1 SCH0 ADCF F6h ADC Configuration CH7 CH6 CH5 CH4 CH3 CH2 CH1 CH0 ADCLK F2h ADC Clock – – – PRS4 PRS3 PRS2 PRS1 PRS0 ADDH F5h ADC Data High byte ADAT9 ADAT8 ADAT7 ADAT6 ADAT5 ADAT4 ADAT3 ADAT2 ADDL F4h ADC Data Low byte – – – – – – ADAT1 ADAT0 Table 9. CAN SFRs Mnemonic Add Name 7 6 5 4 3 2 1 0 CANGCON ABh CAN General Control ABRQ OVRQ TTC SYNCTTC AUT– BAUD TEST ENA GRES CANGSTA AAh CAN General Status – OVFG – TBSY RBSY ENFG BOFF ERRP CANGIT 9Bh CAN General Interrupt CANIT – OVRTIM OVRBUF SERG CERG FERG AERG CANBT1 B4h CAN Bit Timing 1 – BRP5 BRP4 BRP3 BRP2 BRP1 BRP0 – CANBT2 B5h CAN Bit Timing 2 – SJW1 SJW0 – PRS2 PRS1 PRS0 – CANBT3 B6h CAN Bit Timing 3 – PHS22 PHS21 PHS20 PHS12 PHS11 PHS10 SMP 10 A/T89C51CC01 4129N–CAN–03/08 A/T89C51CC01 Table 9. CAN SFRs (Continued) Mnemonic Add Name 7 6 5 4 3 2 1 0 CANEN1 CEh CAN Enable Channel byte 1 – ENCH14 ENCH13 ENCH12 ENCH11 ENCH10 ENCH9 ENCH8 CANEN2 CFh CAN Enable Channel byte 2 ENCH7 ENCH6 ENCH5 ENCH4 ENCH3 ENCH2 ENCH1 ENCH0 CANGIE C1h CAN General Interrupt Enable – – ENRX ENTX ENERCH ENBUF ENERG – CANIE1 C2h CAN Interrupt Enable Channel byte 1 – IECH14 IECH13 IECH12 IECH11 IECH10 IECH9 IECH8 CANIE2 C3h CAN Interrupt Enable Channel byte 2 IECH7 IECH6 IECH5 IECH4 IECH3 IECH2 IECH1 IECH0 CANSIT1 BAh CAN Status Interrupt Channel byte1 – SIT14 SIT13 SIT12 SIT11 SIT10 SIT9 SIT8 CANSIT2 BBh CAN Status Interrupt Channel byte2 SIT7 SIT6 SIT5 SIT4 SIT3 SIT2 SIT1 SIT0 CANTCON A1h CAN Timer Control TPRESC 7 TPRESC 6 TPRESC 5 TPRESC 4 TPRESC 3 TPRESC 2 TPRESC 1 TPRESC 0 CANTIMH ADh CAN Timer high CANTIM 15 CANTIM 14 CANTIM 13 CANTIM 12 CANTIM 11 CANTIM 10 CANTIM 9 CANTIM 8 CANTIML ACh CAN Timer low CANTIM 7 CANTIM 6 CANTIM 5 CANTIM 4 CANTIM 3 CANTIM 2 CANTIM 1 CANTIM 0 CANSTMH AFh CAN Timer Stamp high TIMSTMP 15 TIMSTMP 14 TIMSTMP 13 TIMSTMP 12 TIMSTMP 11 TIMSTMP 10 TIMSTMP 9 TIMSTMP 8 CANSTML AEh CAN Timer Stamp low TIMSTMP 7 TIMSTMP 6 TIMSTMP 5 TIMSTMP 4 TIMSTMP 3 TIMSTMP 2 TIMSTMP 1 TIMSTMP 0 CANTTCH A5h CAN Timer TTC high TIMTTC 15 TIMTTC 14 TIMTTC 13 TIMTTC 12 TIMTTC 11 TIMTTC 10 TIMTTC 9 TIMTTC 8 CANTTCL A4h CAN Timer TTC low TIMTTC TIMTTC TIMTTC TIMTTC TIMTTC TIMTTC TIMTTC TIMTTC 7 6 5 4 3 2 1 0 CANTEC 9Ch CAN Transmit Error Counter TEC7 TEC6 TEC5 TEC4 TEC3 TEC2 TEC1 TEC0 CANREC 9Dh CAN Receive Error Counter REC7 REC6 REC5 REC4 REC3 REC2 REC1 REC0 CANPAGE B1h CAN Page CHNB3 CHNB2 CHNB1 CHNB0 AINC INDX2 INDX1 INDX0 CANSTCH B2h CAN Status Channel DLCW TXOK RXOK BERR SERR CERR FERR AERR CANCONH B3h CAN Control Channel CONCH1 CONCH0 RPLV IDE DLC3 DLC2 DLC1 DLC0 CANMSG CAN Message Data MSG7 MSG6 MSG5 MSG4 MSG3 MSG2 MSG1 MSG0 A3h 11 4129N–CAN–03/08 Table 9. CAN SFRs (Continued) Mnemonic CANIDT1 CANIDT2 CANIDT3 CANIDT4 CANIDM1 CANIDM2 CANIDM3 CANIDM4 Add Name 7 6 5 4 3 2 1 0 CAN Identifier Tag byte 1(Part A) IDT10 IDT9 IDT8 IDT7 IDT6 IDT5 IDT4 IDT3 CAN Identifier Tag byte 1(PartB) IDT28 IDT27 IDT26 IDT25 IDT24 IDT23 IDT22 IDT21 CAN Identifier Tag byte 2 (PartA) IDT2 IDT1 IDT0 – – – – – CAN Identifier Tag byte 2 (PartB) IDT20 IDT19 IDT18 IDT17 IDT16 IDT15 IDT14 IDT13 CAN Identifier Tag byte 3(PartA) – – – – – – – – CAN Identifier Tag byte 3(PartB) IDT12 IDT11 IDT10 IDT9 IDT8 IDT7 IDT6 IDT5 CAN Identifier Tag byte 4(PartA) – – – – – RTRTAG – RB0TAG CAN Identifier Tag byte 4(PartB) IDT4 IDT3 IDT2 IDT1 IDT0 – RB1TAG – IDMSK10 IDMSK9 IDMSK8 IDMSK7 IDMSK6 IDMSK5 IDMSK4 IDMSK3 IDMSK28 IDMSK27 IDMSK26 IDMSK25 IDMSK24 IDMSK23 IDMSK22 IDMSK21 IDMSK2 IDMSK1 IDMSK0 – – – – – IDMSK20 IDMSK19 IDMSK18 IDMSK17 IDMSK16 IDMSK15 IDMSK14 IDMSK13 – – – – – – – – IDMSK12 IDMSK11 IDMSK10 IDMSK9 IDMSK8 IDMSK7 IDMSK6 IDMSK5 – – – – – RTRMSK – IDEMSK IDMSK4 IDMSK3 IDMSK2 IDMSK1 IDMSK0 – BCh BDh BEh BFh C4h C5h C6h C7h CAN Identifier Mask byte 1(PartA) CAN Identifier Mask byte 1(PartB) CAN Identifier Mask byte 2(PartA) CAN Identifier Mask byte 2(PartB) CAN Identifier Mask byte 3(PartA) CAN Identifier Mask byte 3(PartB) CAN Identifier Mask byte 4(PartA) CAN Identifier Mask byte 4(PartB) – Table 10. Other SFRs Mnemonic Add Name PCON 87h Power Control AUXR 8Eh AUXR1 CKCON 12 7 6 5 4 3 2 1 0 SMOD1 SMOD0 – POF GF1 GF0 PD IDL Auxiliary Register 0 – – M0 – XRS1 XRS2 EXTRAM A0 A2h Auxiliary Register 1 – – ENBOOT – GF3 0 – DPS 8Fh Clock Control CANX2 WDX2 PCAX2 SIX2 T2X2 T1X2 T0X2 X2 A/T89C51CC01 4129N–CAN–03/08 A/T89C51CC01 Table 10. Other SFRs Mnemonic Add Name FCON D1h Flash Control EECON D2h EEPROM Contol 7 6 5 4 3 2 1 0 FPL3 FPL2 FPL1 FPL0 FPS FMOD1 FMOD0 FBUSY EEPL3 EEPL2 EEPL1 EEPL0 – – EEE EEBUSY Table 11. SFR Mapping 0/8(1) 1/9 2/A 3/B 4/C 5/D 6/E F8h IPL1 xxxx x000 CH 0000 0000 CCAP0H 0000 0000 CCAP1H 0000 0000 CCAP2H 0000 0000 CCAP3H 0000 0000 CCAP4H 0000 0000 F0h B 0000 0000 ADCLK xxx0 0000 ADCON x000 0000 ADDL 0000 0000 ADDH 0000 0000 ADCF 0000 0000 E8h IEN1 xxxx x000 CCAP0L 0000 0000 CCAP1L 0000 0000 CCAP2L 0000 0000 CCAP3L 0000 0000 CCAP4L 0000 0000 E0h ACC 0000 0000 D8h CCON 00x0 0000 CMOD 00xx x000 CCAPM0 x000 0000 D0h PSW 0000 0000 FCON 0000 0000 EECON xxxx xx00 C8h T2CON 0000 0000 T2MOD xxxx xx00 RCAP2L 0000 0000 RCAP2H 0000 0000 TL2 0000 0000 TH2 0000 0000 CANEN1 x000 0000 CANEN2 0000 0000 CFh C0h P4 xxxx xx11 CANGIE 1100 0000 CANIE1 x000 0000 CANIE2 0000 0000 CANIDM1 xxxx xxxx CANIDM2 xxxx xxxx CANIDM3 xxxx xxxx CANIDM4 xxxx xxxx C7h B8h IPL0 x000 0000 SADEN 0000 0000 CANSIT1 x000 0000 CANSIT2 0000 0000 CANIDT1 xxxx xxxx CANIDT2 xxxx xxxx CANIDT3 xxxx xxxx CANIDT4 xxxx xxxx BFh B0h P3 1111 1111 CANPAGE 0000 0000 CANSTCH xxxx xxxx CANCONCH xxxx xxxx CANBT1 xxxx xxxx CANBT2 xxxx xxxx CANBT3 xxxx xxxx IPH0 x000 0000 B7h A8h IEN0 0000 0000 SADDR 0000 0000 CANGSTA 1010 0000 CANGCON 0000 0000 CANTIML 0000 0000 CANTIMH 0000 0000 CANSTMPL xxxx xxxx CANSTMPH xxxx xxxx AFh A0h P2 1111 1111 CANTCON 0000 0000 AUXR1 xxxx 00x0 CANMSG xxxx xxxx CANTTCL 0000 0000 CANTTCH 0000 0000 WDTRST 1111 1111 WDTPRG xxxx x000 A7h 98h SCON 0000 0000 SBUF 0000 0000 CANGIT 0x00 0000 CANTEC 0000 0000 0000 0000 90h P1 1111 1111 88h TCON 0000 0000 TMOD 0000 0000 TL0 0000 0000 TL1 0000 0000 80h P0 1111 1111 SP 0000 0111 DPL 0000 0000 DPH 0000 0000 0/8(1) 1/9 2/A 3/B CL 0000 0000 7/F FFh IPH1 xxxx x000 F7h EFh E7h CCAPM1 x000 0000 CCAPM2 x000 0000 CCAPM3 x000 0000 CCAPM4 x000 0000 DFh D7h CANREC 9Fh 97h TH0 0000 0000 4/C TH1 0000 0000 5/D AUXR x00x 1100 6/E CKCON 0000 0000 8Fh PCON 00x1 0000 87h 7/F Reserved Note: 1. These registers are bit–addressable. Sixteen addresses in the SFR space are both byte–addressable and bit–addressable. The bit–addressable SFR’s are those whose address ends in 0 and 8. The bit addresses, in this area, are 0x80 through to 0xFF. 13 4129N–CAN–03/08 Clock The T89C51CC01 core needs only 6 clock periods per machine cycle. This feature, called ”X2”, provides the following advantages: • Divides frequency crystals by 2 (cheaper crystals) while keeping the same CPU power. • Saves power consumption while keeping the same CPU power (oscillator power saving). • Saves power consumption by dividing dynamic operating frequency by 2 in operating and idle modes. • Increases CPU power by 2 while keeping the same crystal frequency. In order to keep the original C51 compatibility, a divider-by-2 is inserted between the XTAL1 signal and the main clock input of the core (phase generator). This divider may be disabled by the software. An extra feature is available to start after Reset in the X2 mode. This feature can be enabled by a bit X2B in the Hardware Security Byte. This bit is described in the section "In-System-Programming". Description The X2 bit in the CKCON register (see Table 12) allows switching from 12 clock cycles per instruction to 6 clock cycles and vice versa. At reset, the standard speed is activated (STD mode). Setting this bit activates the X2 feature (X2 mode) for the CPU Clock only (see Figure 5.). The Timers 0, 1 and 2, Uart, PCA, Watchdog or CAN switch in X2 mode only if the corresponding bit is cleared in the CKCON register. The clock for the whole circuit and peripheral is first divided by two before being used by the CPU core and peripherals. This allows any cyclic ratio to be accepted on the XTAL1 input. In X2 mode, as this divider is bypassed, the signals on XTAL1 must have a cyclic ratio between 40 to 60%. Figure 5. shows the clock generation block diagram. The X2 bit is validated on the XTAL1÷2 rising edge to avoid glitches when switching from the X2 to the STD mode. Figure 6 shows the mode switching waveforms. 14 A/T89C51CC01 4129N–CAN–03/08 A/T89C51CC01 Figure 5. Clock CPU Generation Diagram X2B Hardware byte PCON.0 On RESET IDL X2 CKCON.0 XTAL1 ÷2 CPU Core Clock 0 1 XTAL2 CPU CLOCK PD CPU Core Clock Symbol and ADC PCON.1 ÷2 1 FT0 Clock 0 ÷2 1 FT1 Clock 0 ÷2 1 FT2 Clock 0 ÷2 1 FUart Clock 0 ÷2 1 FPca Clock 0 ÷2 1 FWd Clock 0 ÷2 1 FCan Clock 0 PERIPH CLOCK X2 CKCON.0 Peripheral Clock Symbol CANX2 WDX2 PCAX2 SIX2 T2X2 T1X2 T0X2 CKCON.7 CKCON.6 CKCON.5 CKCON.4 CKCON.3 CKCON.2 CKCON.1 15 4129N–CAN–03/08 Figure 6. Mode Switching Waveforms XTAL1 XTAL1/2 X2 bit CPU clock STD Mode Note: 16 X2 Mode STD Mode In order to prevent any incorrect operation while operating in the X2 mode, users must be aware that all peripherals using the clock frequency as a time reference (UART, timers...) will have their time reference divided by two. For example a free running timer generating an interrupt every 20 ms will then generate an interrupt every 10 ms. A UART with a 4800 baud rate will have a 9600 baud rate. A/T89C51CC01 4129N–CAN–03/08 A/T89C51CC01 Register Table 12. CKCON Register CKCON (S:8Fh) Clock Control Register 7 6 5 4 3 2 1 0 CANX2 WDX2 PCAX2 SIX2 T2X2 T1X2 T0X2 X2 Bit Number 7 CANX2 CAN clock (1) Clear to select 6 clock periods per peripheral clock cycle. Set to select 12 clock periods per peripheral clock cycle. 6 WDX2 Watchdog clock (1) Clear to select 6 clock periods per peripheral clock cycle. Set to select 12 clock periods per peripheral clock cycle. 5 PCAX2 Programmable Counter Array clock (1) Clear to select 6 clock periods per peripheral clock cycle. Set to select 12 clock periods per peripheral clock cycle. 4 SIX2 Enhanced UART clock (MODE 0 and 2) (1) Clear to select 6 clock periods per peripheral clock cycle. Set to select 12 clock periods per peripheral clock cycle. 3 T2X2 Timer 2 clock (1) Clear to select 6 clock periods per peripheral clock cycle. Set to select 12 clock periods per peripheral clock cycle. 2 T1X2 Timer 1 clock (1) Clear to select 6 clock periods per peripheral clock cycle. Set to select 12 clock periods per peripheral clock cycle. T0X2 Timer 0 clock (1) Clear to select 6 clock periods per peripheral clock cycle. Set to select 12 clock periods per peripheral clock cycle. 1 0 Note: Bit Mnemonic Description X2 CPU clock Clear to select 12 clock periods per machine cycle (STD mode) for CPU and all the peripherals. Set to select 6 clock periods per machine cycle (X2 mode) and to enable the individual peripherals "X2"bits. 1. This control bit is validated when the CPU clock bit X2 is set; when X2 is low, this bit has no effect. Reset Value = 0000 0000b 17 4129N–CAN–03/08 Power Management Two power reduction modes are implemented in the T89C51CC01: the Idle mode and the Power-down mode. These modes are detailed in the following sections. In addition to these power reduction modes, the clocks of the core and peripherals can be dynamically divided by 2 using the X2 Mode detailed in Section “Clock”. Reset Pin In order to start-up (cold reset) or to restart (warm reset) properly the microcontroller, a high level has to be applied on the RST pin. A bad level leads to a wrong initialisation of the internal registers like SFRs, PC, etc. and to unpredictable behavior of the microcontroller. A warm reset can be applied either directly on the RST pin or indirectly by an internal reset source such as a watchdog, PCA, timer, etc. At Power-up (Cold Reset) Two conditions are required before enabling a CPU start-up: • VDD must reach the specified VDD range, • The level on xtal1 input must be outside the specification (VIH, VIL). If one of these two conditions are not met, the microcontroller does not start correctly and can execute an instruction fetch from anywhere in the program space. An active level applied on the RST pin must be maintained until both of the above conditions are met. A reset is active when the level VIH1 is reached and when the pulse width covers the period of time where VDD and the oscillator are not stabilized. Two parameters have to be taken into account to determine the reset pulse width: • VDD rise time (vddrst), • Oscillator startup time (oscrst). To determine the capacitor the highest value of these two parameters has to be chosen. The reset circuitry is shown in Figure 7. Figure 7. Reset Circuitry VDD Crst RST pin Internal reset Rrst Reset input circuitry 0 Table 13 and Table 15 give some typical examples for three values of VDD rise times, two values of oscillator start-up time and two pull-down resistor values. Table 13. Minimum Reset Capacitor for a 15k Pull-down Resistor oscrst/vddrst 1ms 10ms 100ms 5ms 2.7µF 4.7µF 47µF 20ms 10µF 15µF 47µF Note: 18 These values assume VDD starts from 0v to the nominal value. If the time between two on/off sequences is too fast, the power-supply de coupling capacitors may not be fully discharged, leading to a bad reset sequence. A/T89C51CC01 4129N–CAN–03/08 A/T89C51CC01 Warm Reset To achieve a valid reset, the reset signal must be maintained for at least 2 machine cycles (24 oscillator clock periods) while the oscillator is running. The number of clock periods is mode independent (X2 or X1). Watchdog Reset As detailed in Section “PCA Watchdog Timer”, page 123, the WDT generates a 96-clock period pulse on the RST pin. In order to properly propagate this pulse to the rest of the application in case of external capacitor or power-supply supervisor circuit, a 1KΩ resistor must be added as shown Figure 8. Figure 8. Reset Circuitry for WDT reset out usage VDD + RST RST VSS Reset Recommendation to Prevent Flash Corruption To CPU core and peripherals 1K RRST VDD VSS To other on-board circuitry An example of bad initialization situation may occur in an instance where the bit ENBOOT in AUXR1 register is initialized from the hardware bit BLJB upon reset. Since this bit allows mapping of the bootloader in the code area, a reset failure can be critical. If one wants the ENBOOT cleared in order to unmap the boot from the code area (yet due to a bad reset) the bit ENBOOT in SFRs may be set. If the value of Program Counter is accidently in the range of the boot memory addresses then a flash access (write or erase) may corrupt the Flash on-chip memory. It is recommended to use an external reset circuitry featuring power supply monitoring to prevent system malfunction during periods of insufficient power supply voltage (power supply failure, power supply switched off). Idle Mode Idle mode is a power reduction mode that reduces the power consumption. In this mode, program execution halts. Idle mode freezes the clock to the CPU at known states while the peripherals continue to be clocked. The CPU status before entering Idle mode is preserved, i.e., the program counter and program status word register retain their data for the duration of Idle mode. The contents of the SFRs and RAM are also retained. The status of the Port pins during Idle mode is detailed in Table 14. Entering Idle Mode To enter Idle mode, you must set the IDL bit in PCON register (see Table 15). The T89C51CC01 enters Idle mode upon execution of the instruction that sets IDL bit. The instruction that sets IDL bit is the last instruction executed. Note: Exiting Idle Mode If IDL bit and PD bit are set simultaneously, the T89C51CC01 enters Power-down mode. Then it does not go in Idle mode when exiting Power-down mode. There are two ways to exit Idle mode: 1. Generate an enabled interrupt. – Hardware clears IDL bit in PCON register which restores the clock to the CPU. Execution resumes with the interrupt service routine. Upon completion 19 4129N–CAN–03/08 of the interrupt service routine, program execution resumes with the instruction immediately following the instruction that activated Idle mode. The general-purpose flags (GF1 and GF0 in PCON register) may be used to indicate whether an interrupt occurred during normal operation or during Idle mode. When Idle mode is exited by an interrupt, the interrupt service routine may examine GF1 and GF0. 2. Generate a reset. – Note: A logic high on the RST pin clears IDL bit in PCON register directly and asynchronously. This restores the clock to the CPU. Program execution momentarily resumes with the instruction immediately following the instruction that activated the Idle mode and may continue for a number of clock cycles before the internal reset algorithm takes control. Reset initializes the T89C51CC01 and vectors the CPU to address C:0000h. 1. During the time that execution resumes, the internal RAM cannot be accessed; however, it is possible for the Port pins to be accessed. To avoid unexpected outputs at the Port pins, the instruction immediately following the instruction that activated Idle mode should not write to a Port pin or to the external RAM. 2. If Idle mode is invoked by ADC Idle, the ADC conversion completion will exit Idle. Power-down Mode The Power-down mode places the T89C51CC01 in a very low power state. Power-down mode stops the oscillator and freezes all clocks at known states. The CPU status prior to entering Power-down mode is preserved, i.e., the program counter, program status word register retain their data for the duration of Power-down mode. In addition, the SFRs and RAM contents are preserved. The status of the Port pins during Power-down mode is detailed in Table 14. Entering Power-down Mode To enter Power-down mode, set PD bit in PCON register. The T89C51CC01 enters the Power-down mode upon execution of the instruction that sets PD bit. The instruction that sets PD bit is the last instruction executed. Exiting Power-down Mode If VDD was reduced during the Power-down mode, do not exit Power-down mode until VDD is restored to the normal operating level. There are two ways to exit the Power-down mode: 1. Generate an enabled external interrupt. – Note: The T89C51CC01 provides capability to exit from Power-down using INT0#, INT1#. Hardware clears PD bit in PCON register which starts the oscillator and restores the clocks to the CPU and peripherals. Using INTx# input, execution resumes when the input is released (see Figure 9) while using KINx input, execution resumes after counting 1024 clock ensuring the oscillator is restarted properly (see Figure 8). Execution resumes with the interrupt service routine. Upon completion of the interrupt service routine, program execution resumes with the instruction immediately following the instruction that activated Power-down mode. 1. The external interrupt used to exit Power-down mode must be configured as level sensitive (INT0# and INT1#) and must be assigned the highest priority. In addition, the duration of the interrupt must be long enough to allow the oscillator to stabilize. The execution will only resume when the interrupt is deasserted. 2. Exit from power-down by external interrupt does not affect the SFRs nor the internal RAM content. 20 A/T89C51CC01 4129N–CAN–03/08 A/T89C51CC01 Figure 9. Power-down Exit Waveform Using INT1:0# INT1:0# OSC Active phase Power-down phase Oscillator restart phase Active phase 2. Generate a reset. – Notes: A logic high on the RST pin clears PD bit in PCON register directly and asynchronously. This starts the oscillator and restores the clock to the CPU and peripherals. Program execution momentarily resumes with the instruction immediately following the instruction that activated Power-down mode and may continue for a number of clock cycles before the internal reset algorithm takes control. Reset initializes the T89C51CC01 and vectors the CPU to address 0000h. 1. During the time that execution resumes, the internal RAM cannot be accessed; however, it is possible for the Port pins to be accessed. To avoid unexpected outputs at the Port pins, the instruction immediately following the instruction that activated the Power-down mode should not write to a Port pin or to the external RAM. 2. Exit from power-down by reset redefines all the SFRs, but does not affect the internal RAM content. Table 14. Pin Conditions in Special Operating Modes Mode Port 0 Port 1 Port 2 Port 3 Port 4 ALE PSEN# Reset Floating High High High High High High Idle (internal code) Data Data Data Data Data High High Idle (external code) Floating Data Data Data Data High High PowerDown(inter nal code) Data Data Data Data Data Low Low PowerDown (external code) Floating Data Data Data Data Low Low 3. 21 4129N–CAN–03/08 Registers Table 15. PCON Register PCON (S:87h) – Power configuration Register 7 6 5 4 3 2 1 0 SMOD1 SMOD0 - POF GF1 GF0 PD IDL Bit Number Bit Mnemonic Description 7 SMOD1 Serial port Mode bit 1 Set to select double baud rate in mode 1, 2 or 3 6 SMOD0 Serial port Mode bit 0 Clear to select SM0 bit in SCON register. Set to select FE bit in SCON register. 5 - 4 POF Power-Off Flag Clear to recognize next reset type. Set by hardware when Vcc rises from 0 to its nominal voltage. Can also be set by software. 3 GF1 General-purpose flag 1 One use is to indicate whether an interrupt occurred during normal operation or during Idle mode. 2 GF0 General-purpose flag 0 One use is to indicate whether an interrupt occurred during normal operation or during Idle mode. 1 PD Power-down Mode bit Cleared by hardware when an interrupt or reset occurs. Set to activate the Power-down mode. If IDL and PD are both set, PD takes precedence. 0 IDL Idle Mode bit Cleared by hardware when an interrupt or reset occurs. Set to activate the Idle mode. If IDL and PD are both set, PD takes precedence. Reserved The value read from this bit is indeterminate. Do not set this bit. Reset Value = 00X1 0000b 22 A/T89C51CC01 4129N–CAN–03/08 A/T89C51CC01 Data Memory The T89C51CC01 provides data memory access in two different spaces: 1. The internal space mapped in three separate segments: • the lower 128 Bytes RAM segment. • the upper 128 Bytes RAM segment. • the expanded 1024 Bytes RAM segment (XRAM). 2. The external space. A fourth internal segment is available but dedicated to Special Function Registers, SFRs, (addresses 80h to FFh) accessible by direct addressing mode. Figure 11 shows the internal and external data memory spaces organization. Figure 10. Internal Memory - RAM FFh FFh Upper 128 Bytes Internal RAM indirect addressing 80h 7Fh 00h Special Function Registers direct addressing 80h Lower 128 Bytes Internal RAM direct or indirect addressing Figure 11. Internal and External Data Memory Organization XRAM-XRAM FFFFh 64K Bytes External XRAM FFh or 3FFh 256 up to 1024 Bytes Internal XRAM EXTRAM = 0 00h EXTRAM = 1 0000h Internal External 23 4129N–CAN–03/08 Internal Space Lower 128 Bytes RAM The lower 128 Bytes of RAM (see Figure 11) are accessible from address 00h to 7Fh using direct or indirect addressing modes. The lowest 32 Bytes are grouped into 4 banks of 8 registers (R0 to R7). Two bits RS0 and RS1 in PSW register (see Figure 18) select which bank is in use according to Table 16. This allows more efficient use of code space, since register instructions are shorter than instructions that use direct addressing, and can be used for context switching in interrupt service routines. Table 16. Register Bank Selection RS1 RS0 Description 0 0 Register bank 0 from 00h to 07h 0 1 Register bank 0 from 08h to 0Fh 1 0 Register bank 0 from 10h to 17h 1 1 Register bank 0 from 18h to 1Fh The next 16 Bytes above the register banks form a block of bit-addressable memory space. The C51 instruction set includes a wide selection of single-bit instructions, and the 128 bits in this area can be directly addressed by these instructions. The bit addresses in this area are 00h to 7Fh. Figure 12. Lower 128 Bytes Internal RAM Organization 7Fh 30h 2Fh 20h 18h 10h 08h 00h Bit-Addressable Space (Bit Addresses 0-7Fh) 1Fh 17h 0Fh 4 Banks of 8 Registers R0-R7 07h Upper 128 Bytes RAM The upper 128 Bytes of RAM are accessible from address 80h to FFh using only indirect addressing mode. Expanded RAM The on-chip 1024 Bytes of expanded RAM (XRAM) are accessible from address 0000h to 03FFh using indirect addressing mode through MOVX instructions. In this address range, the bit EXTRAM in AUXR register is used to select the XRAM (default) or the XRAM. As shown in Figure 11 when EXTRAM = 0, the XRAM is selected and when EXTRAM = 1, the XRAM is selected. The size of XRAM can be configured by XRS1-0 bit in AUXR register (default size is 1024 Bytes). Note: 24 Lower 128 Bytes RAM, Upper 128 Bytes RAM, and expanded RAM are made of volatile memory cells. This means that the RAM content is indeterminate after power-up and must then be initialized properly. A/T89C51CC01 4129N–CAN–03/08 A/T89C51CC01 External Space Memory Interface The external memory interface comprises the external bus (port 0 and port 2) as well as the bus control signals (RD, WR, and ALE). Figure 13 shows the structure of the external address bus. P0 carries address A7:0 while P2 carries address A15:8. Data D7:0 is multiplexed with A7:0 on P0. Table 17 describes the external memory interface signals. Figure 13. External Data Memory Interface Structure RAM PERIPHERAL T89C51CC01 A15:8 P2 A15:8 ALE P0 AD7:0 Latch A7:0 A7:0 D7:0 RD WR OE WR Table 17. External Data Memory Interface Signals External Bus Cycles Signal Name Type A15:8 O Address Lines Upper address lines for the external bus. P2.7:0 AD7:0 I/O Address/Data Lines Multiplexed lower address lines and data for the external memory. P0.7:0 ALE O Address Latch Enable ALE signals indicates that valid address information are available on lines AD7:0. RD O Read Read signal output to external data memory. P3.7 WR O Write Write signal output to external memory. P3.6 Description Alternative Function - This section describes the bus cycles the T89C51CC01 executes to read (see Figure 14), and write data (see Figure 15) in the external data memory. External memory cycle takes 6 CPU clock periods. This is equivalent to 12 oscillator clock period in standard mode or 6 oscillator clock periods in X2 mode. For further information on X2 mode. Slow peripherals can be accessed by stretching the read and write cycles. This is done using the M0 bit in AUXR register. Setting this bit changes the width of the RD and WR signals from 3 to 15 CPU clock periods. For simplicity, the accompanying figures depict the bus cycle waveforms in idealized form and do not provide precise timing information. For bus cycle timing parameters refer to the Section “AC Characteristics”. 25 4129N–CAN–03/08 Figure 14. External Data Read Waveforms CPU Clock ALE RD 1 P0 P2 Notes: DPL or Ri P2 D7:0 DPH or P22 1. RD signal may be stretched using M0 bit in AUXR register. 2. When executing MOVX @Ri instruction, P2 outputs SFR content. Figure 15. External Data Write Waveforms CPU Clock ALE WR1 P0 P2 Notes: 26 DPL or Ri P2 D7:0 DPH or P22 1. WR signal may be stretched using M0 bit in AUXR register. 2. When executing MOVX @Ri instruction, P2 outputs SFR content. A/T89C51CC01 4129N–CAN–03/08 A/T89C51CC01 Dual Data Pointer Description The T89C51CC01 implements a second data pointer for speeding up code execution and reducing code size in case of intensive usage of external memory accesses. DPTR 0 and DPTR 1 are seen by the CPU as DPTR and are accessed using the SFR addresses 83h and 84h that are the DPH and DPL addresses. The DPS bit in AUXR1 register (see Figure 20) is used to select whether DPTR is the data pointer 0 or the data pointer 1 (see Figure 16). Figure 16. Dual Data Pointer Implementation DPL0 0 DPL1 1 DPL DPTR0 DPS DPTR1 Application DPH0 0 DPH1 1 AUXR1.0 DPTR DPH Software can take advantage of the additional data pointers to both increase speed and reduce code size, for example, block operations (copy, compare…) are well served by using one data pointer as a “source” pointer and the other one as a “destination” pointer. Hereafter is an example of block move implementation using the two pointers and coded in assembler. The latest C compiler takes also advantage of this feature by providing enhanced algorithm libraries. The INC instruction is a short (2 Bytes) and fast (6 machine cycle) way to manipulate the DPS bit in the AUXR1 register. However, note that the INC instruction does not directly force the DPS bit to a particular state, but simply toggles it. In simple routines, such as the block move example, only the fact that DPS is toggled in the proper sequence matters, not its actual value. In other words, the block move routine works the same whether DPS is '0' or '1' on entry. ; ASCII block move using dual data pointers ; Modifies DPTR0, DPTR1, A and PSW ; Ends when encountering NULL character ; Note: DPS exits opposite to the entry state unless an extra INC AUXR1 is added AUXR1EQU0A2h move:movDPTR,#SOURCE ; address of SOURCE incAUXR1 ; switch data pointers movDPTR,#DEST ; address of DEST mv_loop:incAUXR1; switch data pointers movxA,@DPTR; get a byte from SOURCE incDPTR; increment SOURCE address incAUXR1; switch data pointers movx@DPTR,A; write the byte to DEST incDPTR; increment DEST address jnzmv_loop; check for NULL terminator end_move: 27 4129N–CAN–03/08 Registers Table 18. PSW Register PSW (S:D0h) Program Status Word Register 7 6 5 4 3 2 1 0 CY AC F0 RS1 RS0 OV F1 P Bit Number Bit Mnemonic Description 7 CY Carry Flag Carry out from bit 1 of ALU operands. 6 AC Auxiliary Carry Flag Carry out from bit 1 of addition operands. 5 F0 User Definable Flag 0. 4-3 RS1:0 Register Bank Select Bits Refer to Table 16 for bits description. 2 OV Overflow Flag Overflow set by arithmetic operations. 1 F1 User Definable Flag 1 0 P Parity Bit Set when ACC contains an odd number of 1’s. Cleared when ACC contains an even number of 1’s. Reset Value = 0000 0000b Table 19. AUXR Register AUXR (S:8Eh) Auxiliary Register 7 6 5 4 3 2 1 0 - - M0 - XRS1 XRS0 EXTRAM A0 Bit Number 7-6 - 5 M0 4 - 3-2 28 Bit Mnemonic Description XRS1-0 Reserved The value read from these bits are indeterminate. Do not set this bit. Stretch MOVX control: the RD/ and the WR/ pulse length is increased according to the value of M0. M0 Pulse length in clock period 0 6 1 30 Reserved The value read from this bit is indeterminate. Do not set this bit. XRAM size: Accessible size of the XRAM XRS 1:0 XRAM size 0 0 256 Bytes 0 1 512 Bytes 1 0 768 Bytes 1 1 1024 Bytes (default) A/T89C51CC01 4129N–CAN–03/08 A/T89C51CC01 Bit Number 1 Bit Mnemonic Description EXTRAM 0 A0 Internal/External RAM (00h - FFh) access using MOVX @ Ri/@ DPTR 0 - Internal XRAM access using MOVX @ Ri/@ DPTR. 1 - External data memory access. Disable/Enable ALE) 0 - ALE is emitted at a constant rate of 1/6 the oscillator frequency (or 1/3 if X2 mode is used) 1 - ALE is active only during a MOVX or MOVC instruction. Reset Value = X00X 1100b Not bit addressable Table 20. AUXR1 Register AUXR1 (S:A2h) Auxiliary Control Register 1 7 6 5 4 3 2 1 0 - - ENBOOT - GF3 0 - DPS Bit Number Bit Mnemonic Description 7-6 - 5 Reserved The value read from these bits is indeterminate. Do not set these bits. Enable Boot Flash ENBOOT(1) Set this bit for map the boot Flash between F800h -FFFFh Clear this bit for disable boot Flash. Reserved The value read from this bit is indeterminate. Do not set this bit. 4 - 3 GF3 2 0 Always Zero This bit is stuck to logic 0 to allow INC AUXR1 instruction without affecting GF3 flag. 1 - Reserved for Data Pointer Extension. 0 DPS General-purpose Flag 3 Data Pointer Select Bit Set to select second dual data pointer: DPTR1. Clear to select first dual data pointer: DPTR0. Reset Value = XXXX 00X0b Note: 1. ENBOOT is initialized with the invert BLJB at reset. See In-System Programming section. 29 4129N–CAN–03/08 EEPROM Data Memory The 2-Kbyte on-chip EEPROM memory block is located at addresses 0000h to 07FFh of the XRAM/XRAM memory space and is selected by setting control bits in the EECON register. A read in the EEPROM memory is done with a MOVX instruction. A physical write in the EEPROM memory is done in two steps: write data in the column latches and transfer of all data latches into an EEPROM memory row (programming). The number of data written on the page may vary from 1 up to 128 Bytes (the page size). When programming, only the data written in the column latch is programmed and a ninth bit is used to obtain this feature. This provides the capability to program the whole memory by Bytes, by page or by a number of Bytes in a page. Indeed, each ninth bit is set when the writing the corresponding byte in a row and all these ninth bits are reset after the writing of the complete EEPROM row. Write Data in the Column Latches Data is written by byte to the column latches as for an external RAM memory. Out of the 11 address bits of the data pointer, the 4 MSBs are used for page selection (row) and 7 are used for byte selection. Between two EEPROM programming sessions, all the addresses in the column latches must stay on the same page, meaning that the 4 MSB must no be changed. The following procedure is used to write to the column latches: • Save and disable interrupt. • Set bit EEE of EECON register • Load DPTR with the address to write • Store A register with the data to be written • Execute a MOVX @DPTR, A • If needed loop the three last instructions until the end of a 128 Bytes page • Restore interrupt. Note: Programming The EEPROM programming consists of the following actions: • writing one or more Bytes of one page in the column latches. Normally, all Bytes must belong to the same page; if not, the last page address will be latched and the others discarded. • launching programming by writing the control sequence (50h followed by A0h) to the EECON register. • EEBUSY flag in EECON is then set by hardware to indicate that programming is in progress and that the EEPROM segment is not available for reading. • The end of programming is indicated by a hardware clear of the EEBUSY flag. Note: Read Data 30 The last page address used when loading the column latch is the one used to select the page programming address. The sequence 5xh and Axh must be executed without instructions between then otherwise the programming is aborted. The following procedure is used to read the data stored in the EEPROM memory: • Save and disable interrupt • Set bit EEE of EECON register • Load DPTR with the address to read • Execute a MOVX A, @DPTR • Restore interrupt A/T89C51CC01 4129N–CAN–03/08 A/T89C51CC01 Examples ;*F************************************************************************* ;* NAME: api_rd_eeprom_byte ;* DPTR contain address to read. ;* Acc contain the reading value ;* NOTE: before execute this function, be sure the EEPROM is not BUSY ;*************************************************************************** api_rd_eeprom_byte: ; Save and clear EA MOV EECON, #02h; map EEPROM in XRAM space MOVX A, @DPTR MOV EECON, #00h; unmap EEPROM ; Restore EA ret ;*F************************************************************************* ;* NAME: api_ld_eeprom_cl ;* DPTR contain address to load ;* Acc contain value to load ;* NOTE: in this example we load only 1 byte, but it is possible upto ;* 128 Bytes. ;* before execute this function, be sure the EEPROM is not BUSY ;*************************************************************************** api_ld_eeprom_cl: ; Save and clear EA MOV EECON, #02h ; map EEPROM in XRAM space MOVX @DPTR, A MOVEECON, #00h; unmap EEPROM ; Restore EA ret ;*F************************************************************************* ;* NAME: api_wr_eeprom ;* NOTE: before execute this function, be sure the EEPROM is not BUSY ;*************************************************************************** api_wr_eeprom: ; Save and clear EA MOV EECON, #050h MOV EECON, #0A0h ; Restore EA ret 31 4129N–CAN–03/08 Registers Table 21. EECON Register EECON (S:0D2h) EEPROM Control Register 7 6 5 4 3 2 1 0 EEPL3 EEPL2 EEPL1 EEPL0 - - EEE EEBUSY Bit Number Bit Mnemonic 7-4 EEPL3-0 Programming Launch command bits Write 5Xh followed by AXh to EEPL to launch the programming. 3 - Reserved The value read from this bit is indeterminate. Do not set this bit. 2 - Reserved The value read from this bit is indeterminate. Do not set this bit. 1 0 EEE EEBUSY Description Enable EEPROM Space bit Set to map the EEPROM space during MOVX instructions (Write in the column latches) Clear to map the XRAM space during MOVX. Programming Busy flag Set by hardware when programming is in progress. Cleared by hardware when programming is done. Can not be set or cleared by software. Reset Value = XXXX XX00b Not bit addressable 32 A/T89C51CC01 4129N–CAN–03/08 A/T89C51CC01 Program/Code Memory The T89C51CC01 implement 32K Bytes of on-chip program/code memory. Figure 17 shows the partitioning of internal and external program/code memory spaces depending on the product. The Flash memory increases EPROM and ROM functionality by in-circuit electrical erasure and programming. Thanks to the internal charge pump, the high voltage needed for programming or erasing Flash cells is generated on-chip using the standard VDD voltage. Thus, the Flash Memory can be programmed using only one voltage and allows InSystem-Programming commonly known as ISP. Hardware programming mode is also available using specific programming tool. Figure 17. Program/Code Memory Organization FFFFh 32K Bytes external memory 8000h 7FFFh 7FFFh 32K Bytes external memory 32K Bytes internal Flash EA = 0 EA = 1 0000h Notes: 0000h 1. If the program executes exclusively from on-chip code memory (not from external memory), beware of executing code from the upper byte of on-chip memory (7FFFh) and thereby disrupt I/O Ports 0 and 2 due to external prefetch. Fetching code constant from this location does not affect Ports 0 and 2. 2. Default factory programmed parts come with maximum hardware protection. Execution from external memory is not possible unless the Hardware Security Byte is reprogrammed. See Table 27. 33 4129N–CAN–03/08 17.22 External Code Memory Access Memory Interface The external memory interface comprises the external bus (port 0 and port 2) as well as the bus control signals (PSEN#, and ALE). Figure 18 shows the structure of the external address bus. P0 carries address A7:0 while P2 carries address A15:8. Data D7:0 is multiplexed with A7:0 on P0. Table 18 describes the external memory interface signals. Figure 18. External Code Memory Interface Structure Flash EPROM T89C51CC01 A15:8 P2 A15:8 ALE P0 AD7:0 Latch A7:0 A7:0 D7:0 PSEN# OE Table 23. External Code Memory Interface Signals External Bus Cycles Signal Name Type Alternate Function A15:8 O Address Lines Upper address lines for the external bus. P2.7:0 AD7:0 I/O Address/Data Lines Multiplexed lower address lines and data for the external memory. P0.7:0 ALE O Address Latch Enable ALE signals indicates that valid address information are available on lines AD7:0. - PSEN# O Program Store Enable Output This signal is active low during external code fetch or external code read (MOVC instruction). - Description This section describes the bus cycles the T89C51CC01 executes to fetch code (see Figure 19) in the external program/code memory. External memory cycle takes 6 CPU clock periods. This is equivalent to 12 oscillator clock period in standard mode or 6 oscillator clock periods in X2 mode. For further information on X2 mode see section “Clock “. For simplicity, the accompanying figure depicts the bus cycle waveforms in idealized form and do not provide precise timing information. For bus cycling parameters refer to the ‘AC-DC parameters’ section. 34 A/T89C51CC01 4129N–CAN–03/08 A/T89C51CC01 Figure 19. External Code Fetch Waveforms CPU Clock ALE PSEN# P0 D7:0 PCL P2 PCH Flash Memory Architecture D7:0 PCH PCL D7:0 PCH T89C51CC01 features two on-chip Flash memories: • Flash memory FM0: containing 32K Bytes of program memory (user space) organized into 128 byte pages, • Flash memory FM1: 2K Bytes for boot loader and Application Programming Interfaces (API). The FM0 can be program by both parallel programming and Serial In-System-Programming (ISP) whereas FM1 supports only parallel programming by programmers. The ISP mode is detailed in the "In-System-Programming" section. All Read/Write access operations on Flash Memory by user application are managed by a set of API described in the "In-System-Programming" section. Figure 20. Flash Memory Architecture 2K Bytes Flash memory boot space Hardware Security (1 byte) Extra Row (128 Bytes) Column Latches (128 Bytes) FM1 7FFFh 32K Bytes FFFFh F800h FM1 mapped between F800h and FFFFh when bit ENBOOT is set in AUXR1 register Flash memory user space FM0 0000h 35 4129N–CAN–03/08 FM0 Memory Architecture The Flash memory is made up of 4 blocks (see Figure 20): • The memory array (user space) 32K Bytes • The Extra Row • The Hardware security bits • The column latch registers User Space This space is composed of a 32K Bytes Flash memory organized in 256 pages of 128 Bytes. It contains the user’s application code. Extra Row (XRow) This row is a part of FM0 and has a size of 128 Bytes. The extra row may contain information for boot loader usage. Hardware Security Byte The Hardware security Byte space is a part of FM0 and has a size of 1 byte. The 4 MSB can be read/written by software, the 4 LSB can only be read by software and written by hardware in parallel mode. Column Latches The column latches, also part of FM0, have a size of full page (128 Bytes). The column latches are the entrance buffers of the three previous memory locations (user array, XROW and Hardware security byte). Cross Flash Memory Access Description The FM0 memory can be program only from FM1. Programming FM0 from FM0 or from external memory is impossible. The FM1 memory can be program only by parallel programming. The Table 24 show all software Flash access allowed. Code executing from Table 24. Cross Flash Memory Access 36 FM0 (user Flash) FM1 (boot Flash) Action FM0 (user Flash) FM1 (boot Flash) Read ok - Load column latch ok - Write - - Read ok ok Load column latch ok - Write ok - Read - - External memory Load column latch - - EA = 0 Write - - A/T89C51CC01 4129N–CAN–03/08 A/T89C51CC01 Overview of FM0 Operations The CPU interfaces to the Flash memory through the FCON register and AUXR1 register. These registers are used to: • Map the memory spaces in the adressable space • Launch the programming of the memory spaces • Get the status of the Flash memory (busy/not busy) Mapping of the Memory Space By default, the user space is accessed by MOVC instruction for read only. The column latches space is made accessible by setting the FPS bit in FCON register. Writing is possible from 0000h to 7FFFh, address bits 6 to 0 are used to select an address within a page while bits 14 to 7 are used to select the programming address of the page. Setting FPS bit takes precedence on the EXTRAM bit in AUXR register. The other memory spaces (user, extra row, hardware security) are made accessible in the code segment by programming bits FMOD0 and FMOD1 in FCON register in accordance with Table 25. A MOVC instruction is then used for reading these spaces. Table 25. FM0 Blocks Select Bits Launching Programming FMOD1 FMOD0 FM0 Adressable space 0 0 User (0000h-7FFFh) 0 1 Extra Row(FF80h-FFFFh) 1 0 Hardware Security Byte (0000h) 1 1 Reserved FPL3:0 bits in FCON register are used to secure the launch of programming. A specific sequence must be written in these bits to unlock the write protection and to launch the programming. This sequence is 5xh followed by Axh. Table 26 summarizes the memory spaces to program according to FMOD1:0 bits. 37 4129N–CAN–03/08 Table 26. Programming Spaces Write to FCON User Extra Row Hardware Security Byte Reserved Notes: Status of the Flash Memory FPL3:0 FPS FMOD1 FMOD0 Operation 5 X 0 0 No action A X 0 0 Write the column latches in user space 5 X 0 1 No action A X 0 1 Write the column latches in extra row space 5 X 1 0 No action A X 1 0 Write the fuse bits space 5 X 1 1 No action A X 1 1 No action 1. The sequence 5xh and Axh must be executing without instructions between them otherwise the programming is aborted. 2. Interrupts that may occur during programming time must be disabled to avoid any spurious exit of the programming mode. The bit FBUSY in FCON register is used to indicate the status of programming. FBUSY is set when programming is in progress. Selecting FM1 The bit ENBOOT in AUXR1 register is used to map FM1 from F800h to FFFFh. Loading the Column Latches Any number of data from 1 Byte to 128 Bytes can be loaded in the column latches. This provides the capability to program the whole memory by byte, by page or by any number of Bytes in a page. When programming is launched, an automatic erase of the locations loaded in the column latches is first performed, then programming is effectively done. Thus no page or block erase is needed and only the loaded data are programmed in the corresponding page. The following procedure is used to load the column latches and is summarized in Figure 21: 38 • Save then disable interrupt and map the column latch space by setting FPS bit. • Load the DPTR with the address to load. • Load Accumulator register with the data to load. • Execute the MOVX @DPTR, A instruction. • If needed loop the three last instructions until the page is completely loaded. • Unmap the column latch and Restore Interrupt A/T89C51CC01 4129N–CAN–03/08 A/T89C51CC01 Figure 21. Column Latches Loading Procedure Column Latches Loading Save and Disable IT EA = 0 Column Latches Mapping FCON = 08h (FPS=1) Data Load DPTR = Address ACC = Data Exec: MOVX @DPTR, A Last Byte to load? Data memory Mapping FCON = 00h (FPS = 0) Restore IT Note: The last page address used when loading the column latch is the one used to select the page programming address. Programming the Flash Spaces User Extra Row The following procedure is used to program the User space and is summarized in Figure 22: • Load up to one page of data in the column latches from address 0000h to 7FFFh. • Save then disable the interrupts. • Launch the programming by writing the data sequence 50h followed by A0h in FCON register (only from FM1). The end of the programming indicated by the FBUSY flag cleared. • Restore the interrupts. The following procedure is used to program the Extra Row space and is summarized in Figure 22: • Load data in the column latches from address FF80h to FFFFh. • Save then disable the interrupts. • Launch the programming by writing the data sequence 52h followed by A2h in FCON register. This step of the procedure must be executed from FM1. The end of the programming indicated by the FBUSY flag cleared. The end of the programming indicated by the FBUSY flag cleared. • Restore the interrupts. 39 4129N–CAN–03/08 Figure 22. Flash and Extra Row Programming Procedure Flash Spaces Programming Column Latches Loading see Figure 21 Save and Disable IT EA = 0 Launch Programming FCON = 5xh FCON = Axh FBusy Cleared? Clear Mode FCON = 00h End Programming Restore IT Hardware Security Byte 40 The following procedure is used to program the Hardware Security Byte space and is summarized in Figure 23: • Set FPS and map Hardware byte (FCON = 0x0C) • Save and disable the interrupts. • Load DPTR at address 0000h. • Load Accumulator register with the data to load. • Execute the MOVX @DPTR, A instruction. • Launch the programming by writing the data sequence 54h followed by A4h in FCON register. This step of the procedure must be executed from FM1. The end of the programming indicated by the FBUSY flag cleared. The end of the programming indicated by the FBusy flag cleared. • Restore the interrupts. A/T89C51CC01 4129N–CAN–03/08 A/T89C51CC01 Figure 23. Hardware Programming Procedure Flash Spaces Programming Save and Disable IT EA = 0 Save and Disable IT EA = 0 FCON = 0Ch Launch Programming FCON = 54h FCON = A4h Data Load DPTR = 00h ACC = Data Exec: MOVX @DPTR, A FBusy Cleared? End Loading Restore IT Clear Mode FCON = 00h End Programming RestoreIT Reading the Flash Spaces User The following procedure is used to read the User space: • Read one byte in Accumulator by executing MOVC A,@A+DPTR where A+DPTR is the address of the code byte to read. Note: Extra Row Hardware Security Byte FCON is supposed to be reset when not needed. The following procedure is used to read the Extra Row space and is summarized in Figure 24: • Map the Extra Row space by writing 02h in FCON register. • Read one byte in Accumulator by executing MOVC A,@A+DPTR with A = 0 and DPTR = FF80h to FFFFh. • Clear FCON to unmap the Extra Row. The following procedure is used to read the Hardware Security space and is summarized in Figure 24: • Map the Hardware Security space by writing 04h in FCON register. • Read the byte in Accumulator by executing MOVC A,@A+DPTR with A = 0 and DPTR = 0000h. • Clear FCON to unmap the Hardware Security Byte. 41 4129N–CAN–03/08 Figure 24. Reading Procedure Flash Spaces Reading Flash Spaces Mapping FCON = 0000aa0b(1) Data Read DPTR = Address ACC = 0 Exec: MOVC A, @A+DPTR Clear Mode FCON = 00h Note: Flash Protection from Parallel Programming 1. aa = 10 for the Hardware Security Byte. The three lock bits in Hardware Security Byte (see "In-System-Programming" section) are programmed according to Table 27 provide different level of protection for the onchip code and data located in FM0 and FM1. The only way to write these bits are the parallel mode. They are set by default to level 4 Table 27. Program Lock bit Program Lock Bits Security Level LB0 LB1 LB2 1 U U U No program lock features enabled. MOVC instruction executed from external program memory returns non coded data. 2 P U U MOVC instructions executed from external program memory are barred to return code bytes from internal memory, EA is sampled and latched on reset, and further parallel programming of the Flash is disabled. 3 U P U Same as 2, also verify through parallel programming interface is disabled. 4 U U P Same as 3, also external execution is disabled if code roll over beyond 7FFFh Protection Description Program Lock bits U: unprogrammed P: programmed WARNING: Security level 2 and 3 should only be programmed after Flash and Core verification. Preventing Flash Corruption 42 See the “Power Management” section. A/T89C51CC01 4129N–CAN–03/08 A/T89C51CC01 Registers FCON RegisterFCON (S:D1h) Flash Control Register 7 6 5 4 3 2 1 0 FPL3 FPL2 FPL1 FPL0 FPS FMOD1 FMOD0 FBUSY Bit Number Bit Mnemonic Description 7-4 FPL3:0 3 FPS 2-1 FMOD1:0 0 FBUSY Programming Launch Command Bits Write 5Xh followed by AXh to launch the programming according to FMOD1:0 (see Table 26) Flash Map Program Space Set to map the column latch space in the data memory space. Clear to re-map the data memory space. Flash Mode See Table 25 or Table 26. Flash Busy Set by hardware when programming is in progress. Clear by hardware when programming is done. Can not be changed by software. Reset Value = 0000 0000b 43 4129N–CAN–03/08 Operation Cross Memory Access Space addressable in read and write are: • RAM • ERAM (Expanded RAM access by movx) • XRAM (eXternal RAM) • EEPROM DATA • FM0 (user flash) • Hardware byte • XROW • Boot Flash • Flash Column latch The table below provide the different kind of memory which can be accessed from different code location. Table 28. Cross Memory Access XRAM Action RAM ERAM Hardware Boot FLASH FM0 E² Data Byte XROW Read OK OK OK OK - Write - OK(1) OK(1) OK(1) OK(1) Read - OK OK OK - Write - OK (idle) OK(1) - OK Read - - OK - - Write - - OK(1) - - boot FLASH FM0 External memory EA = 0 or Code Roll Over Note: 44 1. RWW: Read While Write A/T89C51CC01 4129N–CAN–03/08 A/T89C51CC01 Sharing Instructions Table 29. Instructions shared XRAM Action RAM ERAM EEPROM DATA Boot FLASH FM0 Hardware Byte XROW Read MOV MOVX MOVX MOVC MOVC MOVC MOVC Write MOV MOVX MOVX - by cl by cl by cl Note: by cl: using Column Latch Table 30. Read MOVX A, @DPTR Flash EEE bit in FPS in XRAM EECON Register FCON Register ENBOOT EA ERAM 0 0 X X OK 0 1 X X OK 1 0 X X 1 1 X X EEPROM DATA Column Latch OK OK Table 31. Write MOVX @DPTR,A Flash EEE bit in FPS bit in XRAM EECON Register FCON Register ENBOOT EA ERAM 0 0 X X OK 0 1 X EEPROM Data 1 0 1 0 X 1 1 X Latch OK OK X OK 1 0 Column OK OK 45 4129N–CAN–03/08 Table 32. Read MOVC A, @DPTR FCON Register Code Execution FMOD1 0 FMOD0 0 FPS ENBOOT DPTR 0 0000h to 7FFFh OK 0000h to 7FFFh OK X FM1 FM0 XROW Hardware External Byte Code 1 F800h to FFFFh Do not use this configuration 0000 to 007Fh 0 1 X X 1 0 X X X 0 000h to 7FFFh OK 0000h to 7FFFh OK From FM0 1 1 X OK See (1) OK 1 F800h to FFFFh Do not use this configuration 0000h to 7FFF OK 1 0 0 0 F800h to FFFFh 0 X 1 X 0 X 1 0000h to 007h OK NA OK 1 From FM1 (ENBOOT =1 0 1 X 0 See NA OK (2) NA 1 1 0 X OK X 0 NA 1 1 1 X OK 000h to 7FFFh 0 NA External code: EA=0 or Code Roll Over X 0 X X X OK 1. For DPTR higher than 007Fh only lowest 7 bits are decoded, thus the behavior is the same as for addresses from 0000h to 007Fh 2. For DPTR higher than 007Fh only lowest 7 bits are decoded, thus the behavior is the same as for addresses from 0000h to 007Fh 46 A/T89C51CC01 4129N–CAN–03/08 A/T89C51CC01 In-System Programming (ISP) With the implementation of the User Space (FM0) and the Boot Space (FM1) in Flash technology the T89C51CC01 allows the system engineer the development of applications with a very high level of flexibility. This flexibility is based on the possibility to alter the customer program at any stages of a product’s life: • Before mounting the chip on the PCB, FM0 Flash can be programmed with the application code. FM1 is always pre programmed by Atmel with a bootloader (chip can be ordered with CAN bootloader or UART bootloader).(1) • Once the chip is mounted on the PCB, it can be programmed by serial mode via the CAN bus or UART. Note: 1. The user can also program his own bootloader in FM1. This In-System-Programming (ISP) allows code modification over the total lifetime of the product. Besides the default Boot loader Atmel provide to the customer also all the needed Application-Programming-Interfaces (API) which are needed for the ISP. The API are located also in the Boot memory. This allow the customer to have a full use of the 32-Kbyte user memory. Flash Programming and Erasure There are three methods of programming the Flash memory: • The Atmel bootloader located in FM1 is activated by the application. Low level API routines (located in FM1)will be used to program FM0. The interface used for serial downloading to FM0 is the UART or the CAN. API can be called also by the user’s bootloader located in FM0 at [SBV]00h. • A further method exists in activating the Atmel boot loader by hardware activation. See Section “Hardware Security Byte”. • The FM0 can be programmed also by the parallel mode using a programmer. Figure 25. Flash Memory Mapping FFFFh F800h 2K Bytes IAP bootloader FM1 7FFFh Custom Boot Loader FM1 mapped between F800h and FFFFh when API called [SBV]00h 32K Bytes Flash memory FM0 0000h 47 4129N–CAN–03/08 Boot Process Software Boot Process Example Many algorithms can be used for the software boot process. Below are descriptions of the different flags and Bytes. Boot Loader Jump Bit (BLJB): - This bit indicates if on RESET the user wants to jump to this application at address @0000h on FM0 or execute the boot loader at address @F800h on FM1. - BLJB = 0 (i.e. bootloader FM1 executed after a reset) is the default Atmel factory programming. - To read or modify this bit, the APIs are used. Boot Vector Address (SBV): - This byte contains the MSB of the user boot loader address in FM0. - The default value of SBV is FCh (no user boot loader in FM0). - To read or modify this byte, the APIs are used. Extra Byte (EB) and Boot Status Byte (BSB): - These Bytes are reserved for customer use. - To read or modify these Bytes, the APIs are used. Hardware Boot Process At the falling edge of RESET, the bit ENBOOT in AUXR1 register is initialized with the value of Boot Loader Jump Bit (BLJB). Further at the falling edge of RESET if the following conditions (called Hardware condition) are detected. The FCON register is initialized with the value 00h and the PC is initialized with F800h (FM1 lower byte = Bootloader entry point). Hardware Conditions: • PSEN low(1) • EA high, • ALE high (or not connected). The Hardware condition forces the bootloader to be executed, whatever BLJB value is. Then BLBJ will be checked. If no hardware condition is detected, the FCON register is initialized with the value F0h. Then BLJB value will be checked. Conditions are: • If bit BLJB = 1: User application in FM0 will be started at @0000h (standard reset). • If bit BLJB = 0: Boot loader will be started at @F800h in FM1. Note: 1. As PSEN is an output port in normal operating mode (running user applications or bootloader applications) after reset it is recommended to release PSEN after the falling edge of Reset is signaled. The hardware conditions are sampled at reset signal Falling Edge, thus they can be released at any time when reset input is low. 2. To ensure correct microcontroller startup, the PSEN pin should not be tied to ground during power-on. 48 A/T89C51CC01 4129N–CAN–03/08 A/T89C51CC01 Figure 26. Hardware Boot Process Algorithm bit ENBOOT in AUXR1 register is initialized with BLJB inverted. RESET (Example, if BLJB=0, ENBOOT is set (=1) during reset, thus the bootloader is executed after the reset) Hardware Hardware condition? ENBOOT = 0 PC = 0000h No No Yes ENBOOT = 1 PC = F800h FCON = 00h FCON = F0h BLJB = = 0 ? Yes Software ENBOOT = 1 PC = F800h Application in FM0 Application Programming Interface Boot Loader in FM1 Several Application Program Interface (API) calls are available for use by an application program to permit selective erasing and programming of Flash pages. All calls are made by functions. All of these APIs are described in detail in the following documents on the Atmel web site. XROW Bytes • Datasheet Bootloader CAN T89C51CC01 • Datasheet Bootloader UART T89C51CC01 Table 33. XROW Mapping Description Default Value Address Copy of the Manufacturer Code 58h 30h Copy of the Device ID#1: Family code D7h 31h Copy of the Device ID#2: Memories size and type F7h 60h Copy of the Device ID#3: Name and Revision FFh 61h 49 4129N–CAN–03/08 Hardware Security Byte Table 34. Hardware Security Byte 7 6 5 4 3 2 1 0 X2B BLJB - - - LB2 LB1 LB0 Bit Number Bit Mnemonic Description 7 X2B X2 Bit Set this bit to start in standard mode. Clear this bit to start in X2 mode. 6 BLJB Boot Loader JumpBit - 1: To start the user’s application on next RESET (@0000h) located in FM0, - 0: To start the boot loader(@F800h) located in FM1. 5-3 - 2-0 LB2:0 Reserved The value read from these bits are indeterminate. Lock Bits After erasing the chip in parallel mode, the default value is : FFh The erasing in ISP mode (from bootloader) does not modify this byte. Notes: 50 1. Only the 4 MSB bits can be accessed by software. 2. The 4 LSB bits can only be accessed by parallel mode. A/T89C51CC01 4129N–CAN–03/08 A/T89C51CC01 Serial I/O Port The T89C51CC01 I/O serial port is compatible with the I/O serial port in the 80C52. It provides both synchronous and asynchronous communication modes. It operates as a Universal Asynchronous Receiver and Transmitter (UART) in three full-duplex modes (Modes 1, 2 and 3). Asynchronous transmission and reception can occur simultaneously and at different baud rates Serial I/O port includes the following enhancements: • Framing error detection • Automatic address recognition Figure 27. Serial I/O Port Block Diagram IB Bus Write SBUF Read SBUF SBUF Receiver SBUF Transmitter TXD Load SBUF Mode 0 Transmit Receive Shift register RXD Serial Port Interrupt Request RI TI SCON reg Framing Error Detection Framing bit error detection is provided for the three asynchronous modes. To enable the framing bit error detection feature, set SMOD0 bit in PCON register. Figure 28. Framing Error Block Diagram SM0/FE SM1 SM2 REN TB8 RB8 TI RI Set FE bit if stop bit is 0 (framing error) SM0 to UART mode control SMOD1SMOD0 - POF GF1 GF0 PD IDL To UART framing error control When this feature is enabled, the receiver checks each incoming data frame for a valid stop bit. An invalid stop bit may result from noise on the serial lines or from simultaneous transmission by two CPUs. If a valid stop bit is not found, the Framing Error bit (FE) in SCON register bit is set. The software may examine the FE bit after each reception to check for data errors. Once set, only software or a reset clears the FE bit. Subsequently received frames with valid stop bits cannot clear the FE bit. When the FE feature is enabled, RI rises on the stop bit instead of the last data bit (See Figure 29. and Figure 30.). 51 4129N–CAN–03/08 Figure 29. UART Timing in Mode 1 RXD D0 D1 D2 D3 D4 D5 D6 D7 Data byte Start bit Stop bit RI SMOD0=X FE SMOD0=1 Figure 30. UART Timing in Modes 2 and 3 RXD D0 Start bit D1 D2 D3 D4 Data byte D5 D6 D7 D8 Ninth Stop bit bit RI SMOD0=0 RI SMOD0=1 FE SMOD0=1 Automatic Address Recognition The automatic address recognition feature is enabled when the multiprocessor communication feature is enabled (SM2 bit in SCON register is set). Implemented in the hardware, automatic address recognition enhances the multiprocessor communication feature by allowing the serial port to examine the address of each incoming command frame. Only when the serial port recognizes its own address will the receiver set the RI bit in the SCON register to generate an interrupt. This ensures that the CPU is not interrupted by command frames addressed to other devices. If necessary, you can enable the automatic address recognition feature in mode 1. In this configuration, the stop bit takes the place of the ninth data bit. Bit RI is set only when the received command frame address matches the device’s address and is terminated by a valid stop bit. To support automatic address recognition, a device is identified by a given address and a broadcast address. Note: 52 The multiprocessor communication and automatic address recognition features cannot be enabled in mode 0 (i.e. setting SM2 bit in SCON register in mode 0 has no effect). A/T89C51CC01 4129N–CAN–03/08 A/T89C51CC01 Given Address Each device has an individual address that is specified in the SADDR register; the SADEN register is a mask byte that contains don’t-care bits (defined by zeros) to form the device’s given address. The don’t-care bits provide the flexibility to address one or more slaves at a time. The following example illustrates how a given address is formed. To address a device by its individual address, the SADEN mask byte must be 1111 1111b. For example: SADDR0101 0110b SADEN1111 1100b Given0101 01XXb Here is an example of how to use given addresses to address different slaves: Slave A:SADDR1111 0001b SADEN1111 1010b Given1111 0X0Xb Slave B:SADDR1111 0011b SADEN1111 1001b Given1111 0XX1b Slave C:SADDR1111 0011b SADEN1111 1101b Given1111 00X1b The SADEN byte is selected so that each slave may be addressed separately. For slave A, bit 0 (the LSB) is a don’t-care bit; for slaves B and C, bit 0 is a 1. To communicate with slave A only, the master must send an address where bit 0 is clear (e.g. 1111 0000b). For slave A, bit 1 is a 0; for slaves B and C, bit 1 is a don’t care bit. To communicate with slaves A and B, but not slave C, the master must send an address with bits 0 and 1 both set (e.g. 1111 0011b). To communicate with slaves A, B and C, the master must send an address with bit 0 set, bit 1 clear, and bit 2 clear (e.g. 1111 0001b). Broadcast Address A broadcast address is formed from the logical OR of the SADDR and SADEN registers with zeros defined as don’t-care bits, e.g.: SADDR 0101 0110b SADEN 1111 1100b SADDR OR SADEN1111 111Xb The use of don’t-care bits provides flexibility in defining the broadcast address, however in most applications, a broadcast address is FFh. The following is an example of using broadcast addresses: Slave A:SADDR1111 0001b SADEN1111 1010b Given1111 1X11b, Slave B:SADDR1111 0011b SADEN1111 1001b Given1111 1X11B, Slave C:SADDR=1111 0010b SADEN1111 1101b Given1111 1111b 53 4129N–CAN–03/08 For slaves A and B, bit 2 is a don’t care bit; for slave C, bit 2 is set. To communicate with all of the slaves, the master must send an address FFh. To communicate with slaves A and B, but not slave C, the master can send and address FBh. Registers Table 35. SCON Register SCON (S:98h) Serial Control Register 7 6 5 4 3 2 1 0 FE/SM0 SM1 SM2 REN TB8 RB8 TI RI Bit Number Bit Mnemonic Description FE 7 Framing Error bit (SMOD0=1) Clear to reset the error state, not cleared by a valid stop bit. Set by hardware when an invalid stop bit is detected. SM0 Serial port Mode bit 0 (SMOD0=0) Refer to SM1 for serial port mode selection. 6 SM1 Serial port Mode bit 1 SM0 SM1 Mode 0 0 Shift Register 0 1 8-bit UART 1 0 9-bit UART 1 1 9-bit UART 5 SM2 Serial port Mode 2 bit/Multiprocessor Communication Enable bit Clear to disable multiprocessor communication feature. Set to enable multiprocessor communication feature in mode 2 and 3. 4 REN Reception Enable bit Clear to disable serial reception. Set to enable serial reception. 3 TB8 Transmitter Bit 8/Ninth bit to transmit in modes 2 and 3 Clear to transmit a logic 0 in the 9th bit. Set to transmit a logic 1 in the 9th bit. 2 RB8 Receiver Bit 8/Ninth bit received in modes 2 and 3 Cleared by hardware if 9th bit received is a logic 0. Set by hardware if 9th bit received is a logic 1. 1 0 Baud Rate FXTAL/12 (or FXTAL /6 in mode X2) Variable FXTAL/64 or FXTAL/32 Variable TI Transmit Interrupt flag Clear to acknowledge interrupt. Set by hardware at the end of the 8th bit time in mode 0 or at the beginning of the stop bit in the other modes. RI Receive Interrupt flag Clear to acknowledge interrupt. Set by hardware at the end of the 8th bit time in mode 0, see Figure 29. and Figure 30. in the other modes. Reset Value = 0000 0000b Bit addressable 54 A/T89C51CC01 4129N–CAN–03/08 A/T89C51CC01 Table 36. SADEN Register SADEN (S:B9h) Slave Address Mask Register 7 6 5 4 3 2 1 0 – – – – – – – – Bit Number Bit Mnemonic Description Mask Data for Slave Individual Address 7-0 Reset Value = 0000 0000b Not bit addressable Table 37. SADDR Register SADDR (S:A9h) Slave Address Register 7 6 5 4 3 2 1 0 – – – – – – – – Bit Number Bit Mnemonic Description Slave Individual Address 7-0 Reset Value = 0000 0000b Not bit addressable Table 38. SBUF Register SBUF (S:99h) Serial Data Buffer 7 6 5 4 3 2 1 0 – – – – – – – – Bit Number 7-0 Bit Mnemonic Description Data sent/received by Serial I/O Port Reset Value = 0000 0000b Not bit addressable 55 4129N–CAN–03/08 Table 39. PCON Register PCON (S:87h) Power Control Register 7 6 5 4 3 2 1 0 SMOD1 SMOD0 – POF GF1 GF0 PD IDL Bit Number Bit Mnemonic Description 7 SMOD1 Serial port Mode bit 1 Set to select double baud rate in mode 1, 2 or 3. 6 SMOD0 Serial port Mode bit 0 Clear to select SM0 bit in SCON register. Set to select FE bit in SCON register. 5 - 4 POF Power-Off Flag Clear to recognize next reset type. Set by hardware when VCC rises from 0 to its nominal voltage. Can also be set by software. 3 GF1 General-purpose Flag Cleared by user for general-purpose usage. Set by user for general-purpose usage. 2 GF0 General-purpose Flag Cleared by user for general-purpose usage. Set by user for general-purpose usage. 1 PD Power-Down mode bit Cleared by hardware when reset occurs. Set to enter power-down mode. 0 IDL Idle mode bit Clear by hardware when interrupt or reset occurs. Set to enter idle mode. Reserved The value read from this bit is indeterminate. Do not set this bit. Reset Value = 00X1 0000b Not bit addressable 56 A/T89C51CC01 4129N–CAN–03/08 A/T89C51CC01 Timers/Counters The T89C51CC01 implements two general-purpose, 16-bit Timers/Counters. Such are identified as Timer 0 and Timer 1, and can be independently configured to operate in a variety of modes as a Timer or an event Counter. When operating as a Timer, the Timer/Counter runs for a programmed length of time, then issues an interrupt request. When operating as a Counter, the Timer/Counter counts negative transitions on an external pin. After a preset number of counts, the Counter issues an interrupt request. The various operating modes of each Timer/Counter are described in the following sections. Timer/Counter Operations A basic operation is Timer registers THx and TLx (x = 0, 1) connected in cascade to form a 16-bit Timer. Setting the run control bit (TRx) in TCON register (see Figure 40) turns the Timer on by allowing the selected input to increment TLx. When TLx overflows it increments THx; when THx overflows it sets the Timer overflow flag (TFx) in TCON register. Setting the TRx does not clear the THx and TLx Timer registers. Timer registers can be accessed to obtain the current count or to enter preset values. They can be read at any time but TRx bit must be cleared to preset their values, otherwise the behavior of the Timer/Counter is unpredictable. The C/Tx# control bit selects Timer operation or Counter operation by selecting the divided-down peripheral clock or external pin Tx as the source for the counted signal. TRx bit must be cleared when changing the mode of operation, otherwise the behavior of the Timer/Counter is unpredictable. For Timer operation (C/Tx# = 0), the Timer register counts the divided-down peripheral clock. The Timer register is incremented once every peripheral cycle (6 peripheral clock periods). The Timer clock rate is FPER/6, i.e. FOSC/12 in standard mode or FOSC/6 in X2 mode. For Counter operation (C/Tx# = 1), the Timer register counts the negative transitions on the Tx external input pin. The external input is sampled every peripheral cycles. When the sample is high in one cycle and low in the next one, the Counter is incremented. Since it takes 2 cycles (12 peripheral clock periods) to recognize a negative transition, the maximum count rate is FPER/12, i.e. FOSC/24 in standard mode or FOSC/12 in X2 mode. There are no restrictions on the duty cycle of the external input signal, but to ensure that a given level is sampled at least once before it changes, it should be held for at least one full peripheral cycle. Timer 0 Timer 0 functions as either a Timer or event Counter in four modes of operation. Figure 31 to Figure 34 show the logical configuration of each mode. Timer 0 is controlled by the four lower bits of TMOD register (see Figure 41) and bits 0, 1, 4 and 5 of TCON register (see Figure 40). TMOD register selects the method of Timer gating (GATE0), Timer or Counter operation (T/C0#) and mode of operation (M10 and M00). TCON register provides Timer 0 control functions: overflow flag (TF0), run control bit (TR0), interrupt flag (IE0) and interrupt type control bit (IT0). For normal Timer operation (GATE0 = 0), setting TR0 allows TL0 to be incremented by the selected input. Setting GATE0 and TR0 allows external pin INT0# to control Timer operation. Timer 0 overflow (count rolls over from all 1s to all 0s) sets TF0 flag generating an interrupt request. It is important to stop Timer/Counter before changing mode. 57 4129N–CAN–03/08 Mode 0 (13-bit Timer) Mode 0 configures Timer 0 as an 13-bit Timer which is set up as an 8-bit Timer (TH0 register) with a modulo 32 prescaler implemented with the lower five bits of TL0 register (see Figure 31). The upper three bits of TL0 register are indeterminate and should be ignored. Prescaler overflow increments TH0 register. Figure 31. Timer/Counter x (x = 0 or 1) in Mode 0 See the “Clock” section FTx CLOCK ÷6 0 THx (8 bits) 1 TLx (5 bits) Overflow TFx TCON reg Tx Timer x Interrupt Request C/Tx# TMOD reg INTx# GATEx TRx TMOD reg Mode 1 (16-bit Timer) TCON reg Mode 1 configures Timer 0 as a 16-bit Timer with TH0 and TL0 registers connected in cascade (see Figure 32). The selected input increments TL0 register. Figure 32. Timer/Counter x (x = 0 or 1) in Mode 1 See the “Clock” section FTx CLOCK ÷6 0 THx (8 bits) 1 Tx TLx (8 bits) Overflow TFx TCON reg Timer x Interrupt Request C/Tx# TMOD reg INTx# GATEx TMOD reg 58 TRx TCON reg A/T89C51CC01 4129N–CAN–03/08 A/T89C51CC01 Mode 2 (8-bit Timer with AutoReload) Mode 2 configures Timer 0 as an 8-bit Timer (TL0 register) that automatically reloads from TH0 register (see Figure 33). TL0 overflow sets TF0 flag in TCON register and reloads TL0 with the contents of TH0, which is preset by software. When the interrupt request is serviced, hardware clears TF0. The reload leaves TH0 unchanged. The next reload value may be changed at any time by writing it to TH0 register. Figure 33. Timer/Counter x (x = 0 or 1) in Mode 2 See the “Clock” section FTx CLOCK ÷6 0 TLx (8 bits) 1 Overflow TFx TCON reg Tx Timer x Interrupt Request C/Tx# TMOD reg INTx# GATEx THx (8 bits) TRx TMOD reg TCON reg Mode 3 (Two 8-bit Timers) Mode 3 configures Timer 0 such that registers TL0 and TH0 operate as separate 8-bit Timers (see Figure 34). This mode is provided for applications requiring an additional 8bit Timer or Counter. TL0 uses the Timer 0 control bits C/T0# and GATE0 in TMOD register, and TR0 and TF0 in TCON register in the normal manner. TH0 is locked into a Timer function (counting FPER /6) and takes over use of the Timer 1 interrupt (TF1) and run control (TR1) bits. Thus, operation of Timer 1 is restricted when Timer 0 is in mode 3. Figure 34. Timer/Counter 0 in Mode 3: Two 8-bit Counters FTx CLOCK ÷6 0 1 TL0 (8 bits) Overflow TH0 (8 bits) Overflow TF0 TCON.5 T0 Timer 0 Interrupt Request C/T0# TMOD.2 INT0# GATE0 TMOD.3 FTx CLOCK TR0 TCON.4 ÷6 See the “Clock” section TF1 TCON.7 Timer 1 Interrupt Request TR1 TCON.6 59 4129N–CAN–03/08 Timer 1 Timer 1 is identical to Timer 0 excepted for Mode 3 which is a hold-count mode. The following comments help to understand the differences: • Timer 1 functions as either a Timer or event Counter in three modes of operation. Figure 31 to Figure 33 show the logical configuration for modes 0, 1, and 2. Timer 1’s mode 3 is a hold-count mode. • Timer 1 is controlled by the four high-order bits of TMOD register (see Figure 41) and bits 2, 3, 6 and 7 of TCON register (see Figure 40). TMOD register selects the method of Timer gating (GATE1), Timer or Counter operation (C/T1#) and mode of operation (M11 and M01). TCON register provides Timer 1 control functions: overflow flag (TF1), run control bit (TR1), interrupt flag (IE1) and interrupt type control bit (IT1). • Timer 1 can serve as the Baud Rate Generator for the Serial Port. Mode 2 is best suited for this purpose. • For normal Timer operation (GATE1 = 0), setting TR1 allows TL1 to be incremented by the selected input. Setting GATE1 and TR1 allows external pin INT1# to control Timer operation. • Timer 1 overflow (count rolls over from all 1s to all 0s) sets the TF1 flag generating an interrupt request. • When Timer 0 is in mode 3, it uses Timer 1’s overflow flag (TF1) and run control bit (TR1). For this situation, use Timer 1 only for applications that do not require an interrupt (such as a Baud Rate Generator for the Serial Port) and switch Timer 1 in and out of mode 3 to turn it off and on. • It is important to stop Timer/Counter before changing mode. Mode 0 (13-bit Timer) Mode 0 configures Timer 1 as a 13-bit Timer, which is set up as an 8-bit Timer (TH1 register) with a modulo-32 prescaler implemented with the lower 5 bits of the TL1 register (see Figure 31). The upper 3 bits of TL1 register are ignored. Prescaler overflow increments TH1 register. Mode 1 (16-bit Timer) Mode 1 configures Timer 1 as a 16-bit Timer with TH1 and TL1 registers connected in cascade (see Figure 32). The selected input increments TL1 register. Mode 2 (8-bit Timer with AutoReload) Mode 2 configures Timer 1 as an 8-bit Timer (TL1 register) with automatic reload from TH1 register on overflow (see Figure 33). TL1 overflow sets TF1 flag in TCON register and reloads TL1 with the contents of TH1, which is preset by software. The reload leaves TH1 unchanged. Mode 3 (Halt) Placing Timer 1 in mode 3 causes it to halt and hold its count. This can be used to halt Timer 1 when TR1 run control bit is not available i.e. when Timer 0 is in mode 3. Interrupt Each Timer handles one interrupt source that is the timer overflow flag TF0 or TF1. This flag is set every time an overflow occurs. Flags are cleared when vectoring to the Timer interrupt routine. Interrupts are enabled by setting ETx bit in IEN0 register. This assumes interrupts are globally enabled by setting EA bit in IEN0 register. 60 A/T89C51CC01 4129N–CAN–03/08 A/T89C51CC01 Figure 35. Timer Interrupt System Timer 0 Interrupt Request TF0 TCON.5 ET0 IEN0.1 Timer 1 Interrupt Request TF1 TCON.7 ET1 IEN0.3 61 4129N–CAN–03/08 Registers Table 40. TCON Register TCON (S:88h) Timer/Counter Control Register 7 6 5 4 3 2 1 0 TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0 Bit Number Bit Mnemonic Description 7 TF1 Timer 1 Overflow Flag Cleared by hardware when processor vectors to interrupt routine. Set by hardware on Timer/Counter overflow, when Timer 1 register overflows. 6 TR1 Timer 1 Run Control Bit Clear to turn off Timer/Counter 1. Set to turn on Timer/Counter 1. 5 TF0 Timer 0 Overflow Flag Cleared by hardware when processor vectors to interrupt routine. Set by hardware on Timer/Counter overflow, when Timer 0 register overflows. 4 TR0 Timer 0 Run Control Bit Clear to turn off Timer/Counter 0. Set to turn on Timer/Counter 0. 3 IE1 Interrupt 1 Edge Flag Cleared by hardware when interrupt is processed if edge-triggered (see IT1). Set by hardware when external interrupt is detected on INT1# pin. 2 IT1 Interrupt 1 Type Control Bit Clear to select low level active (level triggered) for external interrupt 1 (INT1#). Set to select falling edge active (edge triggered) for external interrupt 1. 1 IE0 Interrupt 0 Edge Flag Cleared by hardware when interrupt is processed if edge-triggered (see IT0). Set by hardware when external interrupt is detected on INT0# pin. 0 IT0 Interrupt 0 Type Control Bit Clear to select low level active (level triggered) for external interrupt 0 (INT0#). Set to select falling edge active (edge triggered) for external interrupt 0. Reset Value = 0000 0000b 62 A/T89C51CC01 4129N–CAN–03/08 A/T89C51CC01 Table 41. TMOD Register TMOD (S:89h) Timer/Counter Mode Control Register 7 6 5 4 3 2 1 0 GATE1 C/T1# M11 M01 GATE0 C/T0# M10 M00 Bit Number Bit Mnemonic Description 7 GATE1 Timer 1 Gating Control Bit Clear to enable Timer 1 whenever TR1 bit is set. Set to enable Timer 1 only while INT1# pin is high and TR1 bit is set. 6 C/T1# Timer 1 Counter/Timer Select Bit Clear for Timer operation: Timer 1 counts the divided-down system clock. Set for Counter operation: Timer 1 counts negative transitions on external pin T1. 5 M11 4 M01 3 GATE0 Timer 0 Gating Control Bit Clear to enable Timer 0 whenever TR0 bit is set. Set to enable Timer/Counter 0 only while INT0# pin is high and TR0 bit is set. 2 C/T0# Timer 0 Counter/Timer Select Bit Clear for Timer operation: Timer 0 counts the divided-down system clock. Set for Counter operation: Timer 0 counts negative transitions on external pin T0. 1 M10 0 M00 Timer 1 Mode Select Bits M11 M01 Operating mode 0 0 Mode 0: 8-bit Timer/Counter (TH1) with 5-bit prescaler (TL1). 0 1 Mode 1: 16-bit Timer/Counter. 1 0 Mode 2: 8-bit auto-reload Timer/Counter (TL1)(1) 1 1 Mode 3: Timer 1 halted. Retains count Timer 0 Mode Select Bit M10 M00 Operating mode 0 0 Mode 0: 8-bit Timer/Counter (TH0) with 5-bit prescaler (TL0). 0 1 Mode 1: 16-bit Timer/Counter. 1 0 Mode 2: 8-bit auto-reload Timer/Counter (TL0)(2) 1 1 Mode 3: TL0 is an 8-bit Timer/Counter TH0 is an 8-bit Timer using Timer 1’s TR0 and TF0 bits. Notes: 1. Reloaded from TH1 at overflow. 2. Reloaded from TH0 at overflow. Reset Value = 0000 0000b 63 4129N–CAN–03/08 Table 42. TH0 Register TH0 (S:8Ch) Timer 0 High Byte Register 7 6 5 4 3 2 1 0 – – – – – – – – Bit Number Bit Mnemonic Description High Byte of Timer 0. 7:0 Reset Value = 0000 0000b Table 43. TL0 Register TL0 (S:8Ah) Timer 0 Low Byte Register 7 6 5 4 3 2 1 0 – – – – – – – – Bit Number Bit Mnemonic Description Low Byte of Timer 0. 7:0 Reset Value = 0000 0000b Table 44. TH1 Register TH1 (S:8Dh) Timer 1 High Byte Register 7 6 5 4 3 2 1 0 – – – – – – – – Bit Number 7:0 Bit Mnemonic Description High Byte of Timer 1. Reset Value = 0000 0000b 64 A/T89C51CC01 4129N–CAN–03/08 A/T89C51CC01 Table 45. TL1 Register TL1 (S:8Bh) Timer 1 Low Byte Register 7 6 5 4 3 2 1 0 – – – – – – – – Bit Number 7:0 Bit Mnemonic Description Low Byte of Timer 1. Reset Value = 0000 0000b 65 4129N–CAN–03/08 Timer 2 The T89C51CC01 timer 2 is compatible with timer 2 in the 80C52. It is a 16-bit timer/counter: the count is maintained by two eight-bit timer registers, TH2 and TL2 that are cascade- connected. It is controlled by T2CON register (See Table ) and T2MOD register (See Table 48). Timer 2 operation is similar to Timer 0 and Timer 1. C/T2 selects FT2 clock/6 (timer operation) or external pin T2 (counter operation) as timer clock. Setting TR2 allows TL2 to be incremented by the selected input. Timer 2 includes the following enhancements: Auto-Reload Mode • Auto-reload mode (up or down counter) • Programmable clock-output The auto-reload mode configures timer 2 as a 16-bit timer or event counter with automatic reload. This feature is controlled by the DCEN bit in T2MOD register (See Table 48). Setting the DCEN bit enables timer 2 to count up or down as shown in Figure 36. In this mode the T2EX pin controls the counting direction. When T2EX is high, timer 2 counts up. Timer overflow occurs at FFFFh which sets the TF2 flag and generates an interrupt request. The overflow also causes the 16-bit value in RCAP2H and RCAP2L registers to be loaded into the timer registers TH2 and TL2. When T2EX is low, timer 2 counts down. Timer underflow occurs when the count in the timer registers TH2 and TL2 equals the value stored in RCAP2H and RCAP2L registers. The underflow sets TF2 flag and reloads FFFFh into the timer registers. The EXF2 bit toggles when timer 2 overflow or underflow, depending on the direction of the count. EXF2 does not generate an interrupt. This bit can be used to provide 17-bit resolution. Figure 36. Auto-Reload Mode Up/Down Counter see section “Clock” FT2 CLOCK :6 0 1 TR2 T2CON.2 CT/2 T2CON.1 T2 (DOWN COUNTING RELOAD VALUE) FFh (8-bit) FFh (8-bit) T2EX: 1=UP 2=DOWN TOGGLE T2CONreg EXF2 TL2 (8-bit) TH2 (8-bit) TF2 T2CONreg RCAP2L (8-bit) TIMER 2 INTERRUPT RCAP2H (8-bit) (UP COUNTING RELOAD VALUE) 66 A/T89C51CC01 4129N–CAN–03/08 A/T89C51CC01 Programmable ClockOutput In clock-out mode, timer 2 operates as a 50%-duty-cycle, programmable clock generator (See Figure 37). The input clock increments TL2 at frequency FOSC/2. The timer repeatedly counts to overflow from a loaded value. At overflow, the contents of RCAP2H and RCAP2L registers are loaded into TH2 and TL2. In this mode, timer 2 overflows do not generate interrupts. The formula gives the clock-out frequency depending on the system oscillator frequency and the value in the RCAP2H and RCAP2L registers: FT2clock Clock – OutFrequency = ----------------------------------------------------------------------------------------4 × ( 65536 – RCAP2H ⁄ RCAP2L ) For a 16 MHz system clock in x1 mode, timer 2 has a programmable frequency range of 61 Hz (FOSC/216) to 4 MHz (FOSC/4). The generated clock signal is brought out to T2 pin (P1.0). Timer 2 is programmed for the clock-out mode as follows: • Set T2OE bit in T2MOD register. • Clear C/T2 bit in T2CON register. • Determine the 16-bit reload value from the formula and enter it in RCAP2H/RCAP2L registers. • Enter a 16-bit initial value in timer registers TH2/TL2. It can be the same as the reload value or different depending on the application. • To start the timer, set TR2 run control bit in T2CON register. It is possible to use timer 2 as a baud rate generator and a clock generator simultaneously. For this configuration, the baud rates and clock frequencies are not independent since both functions use the values in the RCAP2H and RCAP2L registers. Figure 37. Clock-Out Mode TL2 (8-bit) FT2 CLOCK TH2 (8-bit) OVERFLOW TR2 T2CON.2 RCAP2L RCAP2H (8-bit) (8-bit) Toggle T2 Q Q D T2OE T2MOD reg T2EX EXF2 EXEN2 T2CON reg TIMER 2 INTERRUPT T2CON reg 67 4129N–CAN–03/08 Registers Table 46. T2CON Register T2CON (S:C8h) Timer 2 Control Register 7 6 5 4 3 2 1 0 TF2 EXF2 RCLK TCLK EXEN2 TR2 C/T2# CP/RL2# Bit Number 7 Bit Mnemonic Description TF2 Timer 2 Overflow Flag TF2 is not set if RCLK=1 or TCLK = 1. Must be cleared by software. Set by hardware on timer 2 overflow. 6 EXF2 Timer 2 External Flag Set when a capture or a reload is caused by a negative transition on T2EX pin if EXEN2=1. Set to cause the CPU to vector to timer 2 interrupt routine when timer 2 interrupt is enabled. Must be cleared by software. 5 RCLK Receive Clock bit Clear to use timer 1 overflow as receive clock for serial port in mode 1 or 3. Set to use timer 2 overflow as receive clock for serial port in mode 1 or 3. 4 TCLK Transmit Clock bit Clear to use timer 1 overflow as transmit clock for serial port in mode 1 or 3. Set to use timer 2 overflow as transmit clock for serial port in mode 1 or 3. 3 EXEN2 2 TR2 1 C/T2# 0 CP/RL2# Timer 2 External Enable bit Clear to ignore events on T2EX pin for timer 2 operation. Set to cause a capture or reload when a negative transition on T2EX pin is detected, if timer 2 is not used to clock the serial port. Timer 2 Run Control bit Clear to turn off timer 2. Set to turn on timer 2. Timer/Counter 2 Select bit Clear for timer operation (input from internal clock system: FOSC). Set for counter operation (input from T2 input pin). Timer 2 Capture/Reload bit If RCLK=1 or TCLK=1, CP/RL2# is ignored and timer is forced to auto-reload on timer 2 overflow. Clear to auto-reload on timer 2 overflows or negative transitions on T2EX pin if EXEN2=1. Set to capture on negative transitions on T2EX pin if EXEN2=1. Reset Value = 0000 0000b Bit addressable 68 A/T89C51CC01 4129N–CAN–03/08 A/T89C51CC01 Table 47. T2MOD Register T2MOD (S:C9h) Timer 2 Mode Control Register 7 6 5 4 3 2 1 0 - - - - - - T2OE DCEN Bit Number Bit Mnemonic Description 7 - Reserved The value read from this bit is indeterminate. Do not set this bit. 6 - Reserved The value read from this bit is indeterminate. Do not set this bit. 5 - Reserved The value read from this bit is indeterminate. Do not set this bit. 4 - Reserved The value read from this bit is indeterminate. Do not set this bit. 3 - Reserved The value read from this bit is indeterminate. Do not set this bit. 2 - Reserved The value read from this bit is indeterminate. Do not set this bit. 1 T2OE Timer 2 Output Enable bit Clear to program P1.0/T2 as clock input or I/O port. Set to program P1.0/T2 as clock output. 0 DCEN Down Counter Enable bit Clear to disable timer 2 as up/down counter. Set to enable timer 2 as up/down counter. Reset Value = XXXX XX00b Not bit addressable Table 48. TH2 Register TH2 (S:CDh) Timer 2 High Byte Register 7 6 5 4 3 2 1 0 - - - - - - - - Bit Number 7-0 Bit Mnemonic Description High Byte of Timer 2. Reset Value = 0000 0000b Not bit addressable 69 4129N–CAN–03/08 Table 49. TL2 Register TL2 (S:CCh) Timer 2 Low Byte Register 7 6 5 4 3 2 1 0 - - - - - - - - Bit Number Bit Mnemonic Description 7-0 Low Byte of Timer 2. Reset Value = 0000 0000b Not bit addressable Table 50. RCAP2H Register RCAP2H (S:CBh) Timer 2 Reload/Capture High Byte Register 7 6 5 4 3 2 1 0 - - - - - - - - Bit Number Bit Mnemonic Description 7-0 High Byte of Timer 2 Reload/Capture. Reset Value = 0000 0000b Not bit addressable Table 51. RCAP2L Register RCAP2L (S:CAH) TIMER 2 REload/Capture Low Byte Register 7 6 5 4 3 2 1 0 - - - - - - - - Bit Number 7-0 Bit Mnemonic Description Low Byte of Timer 2 Reload/Capture. Reset Value = 0000 0000b Not bit addressable 70 A/T89C51CC01 4129N–CAN–03/08 A/T89C51CC01 Watchdog Timer T89C51CC01 contains a powerful programmable hardware Watchdog Timer (WDT) that automatically resets the chip if it software fails to reset the WDT before the selected time interval has elapsed. It permits large Time-Out ranking from 16ms to 2s @Fosc = 12MHz in X1 mode. This WDT consists of a 14-bit counter plus a 7-bit programmable counter, a Watchdog Timer reset register (WDTRST) and a Watchdog Timer programming (WDTPRG) register. When exiting reset, the WDT is -by default- disable. To enable the WDT, the user has to write the sequence 1EH and E1H into WDTRST register no instruction in between. When the Watchdog Timer is enabled, it will increment every machine cycle while the oscillator is running and there is no way to disable the WDT except through reset (either hardware reset or WDT overflow reset). When WDT overflows, it will generate an output RESET pulse at the RST pin. The RESET pulse duration is 96xTOSC, where TOSC=1/FOSC. To make the best use of the WDT, it should be serviced in those sections of code that will periodically be executed within the time required to prevent a WDT reset Note: When the Watchdog is enable it is impossible to change its period. Figure 38. Watchdog Timer Decoder RESET WR Control WDTRST Enable 14-bit COUNTER 7-bit COUNTER Fwd Clock WDTPRG Outputs - - - - - 2 1 0 RESET 71 4129N–CAN–03/08 Watchdog Programming The three lower bits (S0, S1, S2) located into WDTPRG register permit to program the WDT duration. Table 52. Machine Cycle Count S2 S1 S0 Machine Cycle Count 0 0 0 214 - 1 0 0 1 215 - 1 0 1 0 216 - 1 0 1 1 217 - 1 1 0 0 218 - 1 1 0 1 219 - 1 1 1 0 220 - 1 1 1 1 221 - 1 To compute WD Time-Out, the following formula is applied: F osc FTime – Out = ----------------------------------------------------------------------------WDX2 ∧ X2 14 Svalue 6×2 (2 × 2 ) Note: Svalue represents the decimal value of (S2 S1 S0) The following table outlines the time-out value for FoscXTAL = 12 MHz in X1 mode Table 53. Time-Out Computation 72 S2 S1 S0 Fosc = 12 MHz Fosc = 16 MHz Fosc = 20 MHz 0 0 0 16.38 ms 12.28 ms 9.82 ms 0 0 1 32.77 ms 24.57 ms 19.66 ms 0 1 0 65.54 ms 49.14 ms 39.32 ms 0 1 1 131.07 ms 98.28 ms 78.64 ms 1 0 0 262.14 ms 196.56 ms 157.28 ms 1 0 1 524.29 ms 393.12 ms 314.56 ms 1 1 0 1.05 s 786.24 ms 629.12 ms 1 1 1 2.10 s 1.57 s 1.25 s A/T89C51CC01 4129N–CAN–03/08 A/T89C51CC01 Watchdog Timer During Power-down Mode and Idle In Power-down mode the oscillator stops, which means the WDT also stops. While in Power-down mode, the user does not need to service the WDT. There are 2 methods of exiting Power-down mode: by a hardware reset or via a level activated external interrupt which is enabled prior to entering Power-down mode. When Power-down is exited with hardware reset, the Watchdog is disabled. Exiting Power-down with an interrupt is significantly different. The interrupt shall be held low long enough for the oscillator to stabilize. When the interrupt is brought high, the interrupt is serviced. To prevent the WDT from resetting the device while the interrupt pin is held low, the WDT is not started until the interrupt is pulled high. It is suggested that the WDT be reset during the interrupt service for the interrupt used to exit Power-down. To ensure that the WDT does not overflow within a few states of exiting powerdown, it is best to reset the WDT just before entering powerdown. In the Idle mode, the oscillator continues to run. To prevent the WDT from resetting T89C51CC01 while in Idle mode, the user should always set up a timer that will periodically exit Idle, service the WDT, and re-enter Idle mode. Register Table 54. WDTPRG Register WDTPRG (S:A7h) Watchdog Timer Duration Programming Register 7 6 5 4 3 2 1 0 – – – – – S2 S1 S0 Bit Number Bit Mnemonic Description 7 - Reserved The value read from this bit is indeterminate. Do not set this bit. 6 - Reserved The value read from this bit is indeterminate. Do not set this bit. 5 - Reserved The value read from this bit is indeterminate. Do not set this bit. 4 - Reserved The value read from this bit is indeterminate. Do not set this bit. 3 - Reserved The value read from this bit is indeterminate. Do not set this bit. 2 S2 Watchdog Timer Duration selection bit 2 Work in conjunction with bit 1 and bit 0. 1 S1 Watchdog Timer Duration selection bit 1 Work in conjunction with bit 2 and bit 0. 0 S0 Watchdog Timer Duration selection bit 0 Work in conjunction with bit 1 and bit 2. Reset Value = XXXX X000b 73 4129N–CAN–03/08 Table 55. WDTRST Register WDTRST (S:A6h Write only) Watchdog Timer Enable Register 7 6 5 4 3 2 1 0 – – – – – – – – Bit Number 7 Bit Mnemonic Description - Watchdog Control Value Reset Value = 1111 1111b Note: 74 The WDRST register is used to reset/enable the WDT by writing 1EH then E1H in sequence without instruction between these two sequences. A/T89C51CC01 4129N–CAN–03/08 A/T89C51CC01 CAN Controller The CAN Controller provides all the features required to implement the serial communication protocol CAN as defined by BOSCH GmbH. The CAN specification as referred to by ISO/11898 (2.0A and 2.0B) for high speed and ISO/11519-2 for low speed. The CAN Controller is able to handle all types of frames (Data, Remote, Error and Overload) and achieves a bitrate of 1-Mbit/sec. at 8 MHz1 Crystal frequency in X2 mode. Note: 1. At BRP = 1 sampling point will be fixed. CAN Protocol The CAN protocol is an international standard defined in the ISO 11898 for high speed and ISO 11519-2 for low speed. Principles CAN is based on a broadcast communication mechanism. This broadcast communication is achieved by using a message oriented transmission protocol. These messages are identified by using a message identifier. Such a message identifier has to be unique within the whole network and it defines not only the content but also the priority of the message. The priority at which a message is transmitted compared to another less urgent message is specified by the identifier of each message. The priorities are laid down during system design in the form of corresponding binary values and cannot be changed dynamically. The identifier with the lowest binary number has the highest priority. Bus access conflicts are resolved by bit-wise arbitration on the identifiers involved by each node observing the bus level bit for bit. This happens in accordance with the "wired and" mechanism, by which the dominant state overwrites the recessive state. The competition for bus allocation is lost by all nodes with recessive transmission and dominant observation. All the "losers" automatically become receivers of the message with the highest priority and do not re-attempt transmission until the bus is available again. Message Formats The CAN protocol supports two message frame formats, the only essential difference being in the length of the identifier. The CAN standard frame, also known as CAN 2.0 A, supports a length of 11 bits for the identifier, and the CAN extended frame, also known as CAN 2.0 B, supports a length of 29 bits for the identifier. Can Standard Frame Figure 39. CAN Standard Frames Data Frame Bus Idle SOF 11-bit identifier ID10..0 RTR IDE Arbitration Field Interframe Space r0 4-bit DLC DLC4..0 15-bit CRC 0 - 8 bytes Control Field Data Field CRC ACK del. ACK del. CRC Field ACK Field 7 bits End of Frame Intermission 3 bits Bus Idle (Indefinite) Interframe Space Remote Frame Bus Idle SOF Interframe Space 11-bit identifier ID10..0 Arbitration Field RTR IDE r0 4-bit DLC DLC4..0 Control Field 15-bit CRC CRC Field CRC ACK del. ACK del. ACK Field 7 bits End of Frame Intermission 3 bits Bus Idle (Indefinite) Interframe Space A message in the CAN standard frame format begins with the "Start Of Frame (SOF)", this is followed by the "Arbitration field" which consist of the identifier and the "Remote Transmission Request (RTR)" bit used to distinguish between the data frame and the data request frame called remote frame. The following "Control field" contains the "IDentifier Extension (IDE)" bit and the "Data Length Code (DLC)" used to indicate the 75 4129N–CAN–03/08 number of following data bytes in the "Data field". In a remote frame, the DLC contains the number of requested data bytes. The "Data field" that follows can hold up to 8 data bytes. The frame integrity is guaranteed by the following "Cyclic Redundant Check (CRC)" sum. The "ACKnowledge (ACK) field" compromises the ACK slot and the ACK delimiter. The bit in the ACK slot is sent as a recessive bit and is overwritten as a dominant bit by the receivers which have at this time received the data correctly. Correct messages are acknowledged by the receivers regardless of the result of the acceptance test. The end of the message is indicated by "End Of Frame (EOF)". The "Intermission Frame Space (IFS)" is the minimum number of bits separating consecutive messages. If there is no following bus access by any node, the bus remains idle. CAN Extended Frame Figure 40. CAN Extended Frames Data Frame Bus Idle SOF 11-bit base identifier IDT28..18 18-bit identifier extension ID17..0 SRR IDE RTR r1 Arbitration Field Interframe Space r0 4-bit DLC DLC4..0 15-bit CRC 0 - 8 bytes Control Field Data Field CRC ACK del. ACK del. CRC Field 7 bits ACK Field End of Frame Intermission Bus Idle 3 bits (Indefinite) Interframe Space Remote Frame Bus Idle SOF 11-bit base identifier IDT28..18 Interframe Space 18-bit identifier extension ID17..0 SRR IDE Arbitration Field RTR r1 r0 Control Field 4-bit DLC DLC4..0 15-bit CRC CRC Field CRC ACK del. ACK del. ACK Field 7 bits Intermission 3 bits End of Frame Bus Idle (Indefinite) Interframe Space A message in the CAN extended frame format is likely the same as a message in CAN standard frame format. The difference is the length of the identifier used. The identifier is made up of the existing 11-bit identifier (base identifier) and an 18-bit extension (identifier extension). The distinction between CAN standard frame format and CAN extended frame format is made by using the IDE bit which is transmitted as dominant in case of a frame in CAN standard frame format, and transmitted as recessive in the other case. Format Co-existence As the two formats have to co-exist on one bus, it is laid down which message has higher priority on the bus in the case of bus access collision with different formats and the same identifier / base identifier: The message in CAN standard frame format always has priority over the message in extended format. There are three different types of CAN modules available: – – – 2.0A - Considers 29 bit ID as an error 2.0B Passive - Ignores 29 bit ID messages 2.0B Active - Handles both 11 and 29 bit ID Messages Bit Timing To ensure correct sampling up to the last bit, a CAN node needs to re-synchronize throughout the entire frame. This is done at the beginning of each message with the falling edge SOF and on each recessive to dominant edge. Bit Construction One CAN bit time is specified as four non-overlapping time segments. Each segment is constructed from an integer multiple of the Time Quantum. The Time Quantum or TQ is the smallest discrete timing resolution used by a CAN node. 76 A/T89C51CC01 4129N–CAN–03/08 A/T89C51CC01 Figure 41. CAN Bit Construction CAN Frame (producer) Transmission Point (producer) Nominal CAN Bit Time Time Quantum (producer) Segments (producer) SYNC_SEG PROP_SEG PHASE_SEG_1 PHASE_SEG_2 propagation delay Segments (consumer) SYNC_SEG PROP_SEG PHASE_SEG_1 PHASE_SEG_2 Sample Point Synchronization Segment The first segment is used to synchronize the various bus nodes. On transmission, at the start of this segment, the current bit level is output. If there is a bit state change between the previous bit and the current bit, then the bus state change is expected to occur within this segment by the receiving nodes. Propagation Time Segment This segment is used to compensate for signal delays across the network. This is necessary to compensate for signal propagation delays on the bus line and through the transceivers of the bus nodes. Phase Segment 1 Phase Segment 1 is used to compensate for edge phase errors. This segment may be lengthened during resynchronization. Sample Point The sample point is the point of time at which the bus level is read and interpreted as the value of the respective bit. Its location is at the end of Phase Segment 1 (between the two Phase Segments). Phase Segment 2 This segment is also used to compensate for edge phase errors. This segment may be shortened during resynchronization, but the length has to be at least as long as the information processing time and may not be more than the length of Phase Segment 1. Information Processing Time It is the time required for the logic to determine the bit level of a sampled bit. The Information processing Time begins at the sample point, is measured in TQ and is fixed at 2 TQ for the Atmel CAN. Since Phase Segment 2 also begins at the sample point and is the last segment in the bit time, Phase Segment 2 minimum shall not be less than the Information processing Time. Bit Lengthening As a result of resynchronization, Phase Segment 1 may be lengthened or Phase Segment 2 may be shortened to compensate for oscillator tolerances. If, for example, the transmitter oscillator is slower than the receiver oscillator, the next falling edge used for resynchronization may be delayed. So Phase Segment 1 is lengthened in order to adjust the sample point and the end of the bit time. 77 4129N–CAN–03/08 Bit Shortening If, on the other hand, the transmitter oscillator is faster than the receiver one, the next falling edge used for resynchronization may be too early. So Phase Segment 2 in bit N is shortened in order to adjust the sample point for bit N+1 and the end of the bit time Synchronization Jump Width The limit to the amount of lengthening or shortening of the Phase Segments is set by the Resynchronization Jump Width. This segment may not be longer than Phase Segment 2. Programming the Sample Point Programming of the sample point allows "tuning" of the characteristics to suit the bus. Early sampling allows more Time Quanta in the Phase Segment 2 so the Synchronization Jump Width can be programmed to its maximum. This maximum capacity to shorten or lengthen the bit time decreases the sensitivity to node oscillator tolerances, so that lower cost oscillators such as ceramic resonators may be used. Late sampling allows more Time Quanta in the Propagation Time Segment which allows a poorer bus topology and maximum bus length. Arbitration Figure 42. Bus Arbitration Arbitration lost node A TXCAN Node A loses the bus Node B wins the bus node B TXCAN CAN bus SOF ID10 ID9 ID8 ID7 ID6 ID5 ID4 ID3 ID2 ID1 ID0 RTR IDE --------- The CAN protocol handles bus accesses according to the concept called “Carrier Sense Multiple Access with Arbitration on Message Priority”. During transmission, arbitration on the CAN bus can be lost to a competing device with a higher priority CAN Identifier. This arbitration concept avoids collisions of messages whose transmission was started by more than one node simultaneously and makes sure the most important message is sent first without time loss. The bus access conflict is resolved during the arbitration field mostly over the identifier value. If a data frame and a remote frame with the same identifier are initiated at the same time, the data frame prevails over the remote frame (c.f. RTR bit). Errors The CAN protocol signals any errors immediately as they occur. Three error detection mechanisms are implemented at the message level and two at the bit level: Error at Message Level • Cyclic Redundancy Check (CRC) The CRC safeguards the information in the frame by adding redundant check bits at the transmission end. At the receiver these bits are re-computed and tested against the received bits. If they do not agree there has been a CRC error. • Frame Check This mechanism verifies the structure of the transmitted frame by checking the bit fields against the fixed format and the frame size. Errors detected by frame checks are designated "format errors". 78 A/T89C51CC01 4129N–CAN–03/08 A/T89C51CC01 Error at Bit Level • ACK Errors As already mentioned frames received are acknowledged by all receivers through positive acknowledgement. If no acknowledgement is received by the transmitter of the message an ACK error is indicated. • Monitoring The ability of the transmitter to detect errors is based on the monitoring of bus signals. Each node which transmits also observes the bus level and thus detects differences between the bit sent and the bit received. This permits reliable detection of global errors and errors local to the transmitter. • Bit Stuffing The coding of the individual bits is tested at bit level. The bit representation used by CAN is "Non Return to Zero (NRZ)" coding, which guarantees maximum efficiency in bit coding. The synchronization edges are generated by means of bit stuffing. Error Signalling If one or more errors are discovered by at least one node using the above mechanisms, the current transmission is aborted by sending an "error flag". This prevents other nodes accepting the message and thus ensures the consistency of data throughout the network. After transmission of an erroneous message that has been aborted, the sender automatically re-attempts transmission. CAN Controller Description The CAN Controller accesses are made through SFR. Several operations are possible by SFR: • arithmetic and logic operations, transfers and program control (SFR is accessible by direct addressing). • 15 independent message objects are implemented, a pagination system manages their accesses. Any message object can be programmed in a reception buffer block (even non-consecutive buffers). For the reception of defined messages one or several receiver message objects can be masked without participating in the buffer feature. An IT is generated when the buffer is full. The frames following the buffer-full interrupt will not be taken into account until at least one of the buffer message objects is re-enabled in reception. Higher priority of a message object for reception or transmission is given to the lower message object number. The programmable 16-bit Timer (CANTIMER) is used to stamp each received and sent message in the CANSTMP register. This timer starts counting as soon as the CAN controller is enabled by the ENA bit in the CANGCON register. The Time Trigger Communication (TTC) protocol is supported by the T89C51CC01. 79 4129N–CAN–03/08 Figure 43. CAN Controller Block Diagram Bit Stuffing /Destuffing TxDC RxDC Bit Timing Logic Error Counter Rec/Tec Cyclic Redundancy Check Receive Page Register DPR(Mailbox + Registers) Transmit Priority Encoder µC-Core Interface Interface Bus CAN Controller Mailbox and Registers Organization 80 Core Control The pagination allows management of the 321 registers including 300(15x20) Bytes of mailbox via 34 SFR’s. All actions on the message object window SFRs apply to the corresponding message object registers pointed by the message object number find in the Page message object register (CANPAGE) as illustrate in Figure 44. A/T89C51CC01 4129N–CAN–03/08 A/T89C51CC01 Figure 44. CAN Controller Memory Organization SFR’s On-chip CAN Controller registers General Control General Status General Interrupt Bit Timing - 1 Bit Timing - 2 Bit Timing - 3 Enable message object - 1 Enable message object - 2 Enable Interrupt Enable Interrupt message object - 1 Enable Interrupt message object - 2 Status Interrupt message object - 1 Status Interrupt message object - 2 Timer Control CANTimer High CANTimer Low TimTTC High TimTTC Low TEC counter REC counter Page message object (message object number) (Data offset) 15 message objects message object 14 - Status message object 14 - Control and DLC Ch.14 - Message Data - byte 0 message object 0 - Status message object 0 - Control and DLC message object Status message object Control and DLC Ch.0 - Message Data - byte 0 Ch.14 - ID Tag - 1 Ch.14 - ID Tag - 2 Ch.14 - ID Tag - 3 Ch.14 - ID Tag - 4 ID Tag - 1 ID Tag - 2 ID Tag - 3 ID Tag - 4 Ch.0 - ID Tag - 1 Ch.0 - ID Tag - 2 Ch.0 - ID Tag - 3 Ch.0 - ID Tag - 4 Ch.14 - ID Mask - 1 Ch.14 - ID Mask - 2 Ch.14 - ID Mask - 3 Ch.14 - ID Mask - 4 ID Mask - 1 ID Mask - 2 ID Mask - 3 ID Mask - 4 Ch.0 - ID Mask- 1 Ch.0 - ID Mask- 2 Ch.0 - ID Mask- 3 Ch.0 - ID Mask - 4 Ch.14 TimStmp High Ch.14 TimStmp Low TimStmp High TimStmp Low Ch.0 TimStmp High Ch.0 TimStmp Low Message Data 8 Bytes message object Window SFRs 81 4129N–CAN–03/08 Working on Message Objects The Page message object register (CANPAGE) is used to select one of the 15 message objects. Then, message object Control (CANCONCH) and message object Status (CANSTCH) are available for this selected message object number in the corresponding SFRs. A single register (CANMSG) is used for the message. The mailbox pointer is managed by the Page message object register with an auto-incrementation at the end of each access. The range of this counter is 8. Note that the maibox is a pure RAM, dedicated to one message object, without overlap. In most cases, it is not necessary to transfer the received message into the standard memory. The message to be transmitted can be built directly in the maibox. Most calculations or tests can be executed in the mailbox area which provide quicker access. CAN Controller Management In order to enable the CAN Controller correctly the following registers have to be initialized: • General Control (CANGCON), • Bit Timing (CANBT 1, 2 and 3), • And for each page of 15 message objects – message object Control (CANCONCH), – message object Status (CANSTCH). During operation, the CAN Enable message object registers 1 and 2 (CANEN 1 and 2) gives a fast overview of the message objects availability. The CAN messages can be handled by interrupt or polling modes. A message object can be configured as follows: • Transmit message object, • Receive message object, • Receive buffer message object. • Disable This configuration is made in the CONCH field of the CANCONCH register (see Table 56). When a message object is configured, the corresponding ENCH bit of CANEN 1 and 2 register is set. Table 56. Configuration for CONCH1:2 CONCH 1 CONCH 2 Type of Message Object 0 0 disable 0 1 Transmitter 1 0 Receiver 1 1 Receiver buffer When a Transmitter or Receiver action of a message object is completed, the corresponding ENCH bit of the CANEN 1 and 2 register is cleared. In order to re-enable the message object, it is necessary to re-write the configuration in CANCONCH register. Non-consecutive message objects can be used for all three types of message objects (Transmitter, Receiver and Receiver buffer), 82 A/T89C51CC01 4129N–CAN–03/08 A/T89C51CC01 Buffer Mode Any message object can be used to define one buffer, including non-consecutive message objects, and with no limitation in number of message objects used up to 15. Each message object of the buffer must be initialized CONCH2 = 1 and CONCH1 = 1; Figure 45. Buffer mode message object 14 message object 13 message object 12 message object 11 message object 10 message object 9 message object 8 message object 7 message object 6 message object 5 message object 4 message object 3 message object 2 message object 1 message object 0 Block buffer buffer 7 buffer 6 buffer 5 buffer 4 buffer 3 buffer 2 buffer 1 buffer 0 The same acceptance filter must be defined for each message objects of the buffer. When there is no mask on the identifier or the IDE, all messages are accepted. A received frame will always be stored in the lowest free message object. When the flag Rxok is set on one of the buffer message objects, this message object can then be read by the application. This flag must then be cleared by the software and the message object re-enabled in buffer reception in order to free the message object. The OVRBUF flag in the CANGIT register is set when the buffer is full. This flag can generate an interrupt. The frames following the buffer-full interrupt will not stored and no status will be overwritten in the CANSTCH registers involved in the buffer until at least one of the buffer message objects is re-enabled in reception. This flag must be cleared by the software in order to acknowledge the interrupt. 83 4129N–CAN–03/08 IT CAN Management The different interrupts are: • Transmission interrupt, • Reception interrupt, • Interrupt on error (bit error, stuff error, crc error, form error, acknowledge error), • Interrupt when Buffer receive is full, • Interrupt on overrun of CAN Timer. Figure 46. CAN Controller Interrupt Structure CANGIE.5 ENRX CANGIE.4 CANGIE.3 ENTX ENERCH RXOK i CANSIT1/2 CANSTCH.5 SIT i TXOK i CANSTCH.6 CANIE1/2 BERR i EICH i CANSTCH.4 i=0 SERR i CANGIT.7 CANIT CANSTCH.3 SIT i CERR i i=14 CANSTCH.2 FERR i CANGIE.2 CANSTCH.1 ENBUF AERR i IEN1.0 ECAN CANSTCH.0 CANIT OVRBUF CANGIT.4 CANGIE.1 ENERG SERG CANGIT.3 CERG CANGIT.2 FERG CANGIT.1 IEN1.2 AERG ETIM CANGIT.0 OVRIT OVRTIM CANGIT.5 To enable a transmission interrupt: • Enable General CAN IT in the interrupt system register, • Enable interrupt by message object, EICHi, • Enable transmission interrupt, ENTX. To enable a reception interrupt: 84 • Enable General CAN IT in the interrupt system register, • Enable interrupt by message object, EICHi, A/T89C51CC01 4129N–CAN–03/08 A/T89C51CC01 • Enable reception interrupt, ENRX. To enable an interrupt on message object error: • Enable General CAN IT in the interrupt system register, • Enable interrupt by message object, EICHi, • Enable interrupt on error, ENERCH. To enable an interrupt on general error: • Enable General CAN IT in the interrupt system register, • Enable interrupt on error, ENERG. To enable an interrupt on Buffer-full condition: • Enable General CAN IT in the interrupt system register, • Enable interrupt on Buffer full, ENBUF. To enable an interrupt when Timer overruns: • Enable Overrun IT in the interrupt system register. When an interrupt occurs, the corresponding message object bit is set in the SIT register. To acknowledge an interrupt, the corresponding CANSTCH bits (RXOK, TXOK,...) or CANGIT bits (OVRTIM, OVRBUF,...), must be cleared by the software application. When the CAN node is in transmission and detects a Form Error in its frame, a bit Error will also be raised. Consequently, two consecutive interrupts can occur, both due to the same error. When a message object error occurs and is set in CANSTCH register, no general error are set in CANGIE register. 85 4129N–CAN–03/08 Bit Timing and Baud Rate FSM’s (Finite State Machine) of the CAN channel need to be synchronous to the time quantum. So, the input clock for bit timing is the clock used into CAN channel FSM’s. Field and segment abbreviations: • BRP: Baud Rate Prescaler. • TQ: Time Quantum (output of Baud Rate Prescaler). • SYNS: SYNchronization Segment is 1 TQ long. • PRS: PRopagation time Segment is programmable to be 1, 2, ..., 8 TQ long. • PHS1: PHase Segment 1 is programmable to be 1, 2, ..., 8 TQ long. • PHS2: PHase Segment 2 is programmable to be superior or equal to the INFORMATION PROCESSING TIME and inferior or equal to TPHS1. • INFORMATION PROCESSING TIME is 2 TQ. • SJW: (Re) Synchronization Jump Width is programmable to be minimum of PHS1 and 4. The total number of TQ in a bit time has to be programmed at least from 8 to 25. Figure 47. Sample And Transmission Point Bit Timing FCAN CLOCK Prescaler BRP System clock Tscl Time Quantum PRS 3-bit length PHS1 3-bit length Sample point PHS2 3-bit length SJW 2-bit length Transmission point The baud rate selection is made by Tbit calculation: Tbit = Tsyns + Tprs + Tphs1 + Tphs2 1. Tsyns = Tscl = (BRP[5..0]+ 1)/Fcan = 1TQ. 2. Tprs = (1 to 8) * Tscl = (PRS[2..0]+ 1) * Tscl 3. Tphs1 = (1 to 8) * Tscl = (PHS1[2..0]+ 1) * Tscl 4. Tphs2 = (1 to 8) * Tscl = (PHS2[2..0]+ 1) * Tscl Tphs2 = Max of (Tphs1 and 2TQ) 5. Tsjw = (1 to 4) * Tscl = (SJW[1..0]+ 1) * Tscl The total number of Tscl (Time Quanta) in a bit time must be comprised between 8 to 25. 86 A/T89C51CC01 4129N–CAN–03/08 A/T89C51CC01 Figure 48. General Structure of a Bit Period 1/ Fcan oscillator Bit Rate Prescaler Tscl system clock one nominal bit data Tsyns (*) Tprs (1) Phase error ≤ 0 (2) Phase error ≥ 0 (3) Phase error > 0 (4) Phase error < 0 Tphs1 (1) Tphs2 (2) Tphs1 + Tsjw (3) Tphs2 - Tsjw (4) Tbit (*) Synchronization Segment: SYNS Tsyns = 1xTscl (fixed) Sample Point Transmission Point Tbit calculation: Tbit = Tsyns + Tprs + Tphs1 + Tphs2 example of bit timing determination for CAN baudrate of 500kbit/s: Fosc = 12 MHz in X1 mode => FCAN = 6 MHz Verify that the CAN baud rate you want is an integer division of FCAN clock. FCAN/CAN baudrate = 6 MHz/500 kHz = 12 The time quanta TQ must be comprised between 8 and 25: TQ = 12 and BRP = 0 Define the various timing parameters: Tbit = Tsyns + Tprs + Tphs1 + Tphs2 = 12TQ Tsyns = 1TQ and Tsjw =1TQ => SJW = 0 If we chose a sample point at 66.6% => Tphs2 = 4TQ => PHS2 = 3 Tbit = 12 = 4 + 1 + Tphs1 + Tprs, let us choose Tprs = 3 Tphs1 = 4 PHS1 = 3 and PRS = 2 BRP = 0 so CANBT1 = 00h SJW = 0 and PRS = 2 so CANBT2 = 04h PHS2 = 3 and PHS1 = 3 so CANBT3 = 36h 87 4129N–CAN–03/08 Fault Confinement With respect to fault confinement, a unit may be in one of the three following status: • error active • error passive • bus off An error active unit takes part in bus communication and can send an active error frame when the CAN macro detects an error. An error passive unit cannot send an active error frame. It takes part in bus communication, but when an error is detected, a passive error frame is sent. Also, after a transmission, an error passive unit will wait before initiating further transmission. A bus off unit is not allowed to have any influence on the bus. For fault confinement, two error counters (TEC and REC) are implemented. See CAN Specification for details on Fault confinement. Figure 49. Line Error Mode ERRP = 0 BOFF = 0 TEC>127 or REC>127 Init. Error Active TEC IDT0-29 RTR => RTRTAG RB => RB0-1TAG IDE => IDE in CANCONCH register Figure 50. Acceptance filter block diagram RxDC Rx Shift Register (internal) ID and RB RTR IDE 13/32 13/32 = 13/32 Write Enable 13/32 ID TAG Registers (Ch i) and CanConch ID and RB RTR IDE Hit (Ch i) 1 13/32 ID MSK Registers (Ch i) ID and RB RTR IDE example: To accept only ID = 318h in part A. ID MSK = 111 1111 1111 b ID TAG = 011 0001 1000 b 89 4129N–CAN–03/08 Description of the different steps for: Data Frame Node B RT R EN CH RP L TX V RXOK O K RT R EN CH RP L TX V O RX K O K Node A message object in transmission 0 1 u u x 0 0 u u u message object disabled 0 0 u c x 1 0 u c u RA M E message object in transmission 1 1 u u x 0 0 u u u message object in by CAN controller reception 0 1 c u x 1 0 u c u message object disabled 0 0 u c x 0 1 u u c FR AM E ME FRA ) TA diate A D me (im 1 1 u u x 0 0 u u u message object disabled 0 1 c u x 1 0 u c u 0 0 c c x 0 1 u u c RE M OT EF RA ME ME RA A F red) T DA efer (d i u : modified by user 90 message object in reception 0 0 u c x 0 1 u u c message object disabled RT R EN CH RP L TX V O RX K O K RE MO TE RP L TX V O RX K O K message object in transmission message object in reception by user x 0 0 u u u 1 1 u u 1 0 0 u u u message object in reception 0 1 c u 0 0 0 c u u message object in transmission by CAN controller 0 0 u c 0 1 0 c c u message object disabled Remote Frame RT R EN CH • 0 1 u u Remote Frame, With Automatic Reply, RT R EN CH RP L TX V RXOK O K • DA TA F RP L TX V RXOK O K • RT R EN CH Data and Remote Frame 1 1 u u 0 0 0 u u u message object in reception 1 0 u c 0 0 1 u u c message object disabled 0 1 u u x 0 0 u u u message object in transmission by user 0 0 u c x 1 0 u c u message object disabled i c : modified by CAN A/T89C51CC01 4129N–CAN–03/08 A/T89C51CC01 Time Trigger Communication (TTC) and Message Stamping The T89C51CC01 has a programmable 16-bit Timer (CANTIMH and CANTIML) for message stamp and TTC. This CAN Timer starts after the CAN controller is enabled by the ENA bit in the CANGCON register. Two modes in the timer are implemented: • Time Trigger Communication: – Note: • Capture of this timer value in the CANTTCH and CANTTCL registers on Start Of Frame (SOF) or End Of Frame (EOF), depending on the SYNCTTC bit in the CANGCON register, when the network is configured in TTC by the TTC bit in the CANGCON register. In this mode, CAN only sends the frame once, even if an error occurs. Message Stamping – Capture of this timer value in the CANSTMPH and CANSTMPL registers of the message object which received or sent the frame. – All messages can be stamps. – The stamping of a received frame occurs when the RxOk flag is set. – The stamping of a sent frame occurs when the TxOk flag is set. The CAN Timer works in a roll-over from FFFFh to 0000h which serves as a time base. When the timer roll-over from FFFFh to 0000h, an interrupt is generated if the ETIM bit in the interrupt enable register IEN1 is set. Figure 51. Block Diagram of CAN Timer When 0xFFFF to 0x0000 OVRTIM CANGIT.5 Fcan CLOCK ÷6 CANTCON CANGCON.1 ENA CANGCON.5 CANGCON.4 TTC SYNCTTC CANTIMH and CANTIML TXOK i SOF on CAN frame CANSTCH.4 EOF on CAN frame RXOK i CANSTCH.5 CANSTMPH and CANSTMPL CANTTCH and CANTTCL 91 4129N–CAN–03/08 CAN Autobaud and Listening Mode To activate the Autobaud feature, the AUTOBAUD bit in the CANGCON register must be set. In this mode, the CAN controller is only listening to the line without acknowledging the received messages. It cannot send any message. The error flags are updated. The bit timing can be adjusted until no error occurs (good configuration find). In this mode, the error counters are frozen. To go back to the standard mode, the AUTOBAUD bit must be cleared. Figure 52. Autobaud Mode TxDC’ TxDC AUTOBAUD CANGCON.3 RxDC’ Routines Examples RxDC 1 0 1. Init of CAN macro // Reset the CAN macro CANGCON = 01h; // Disable CAN interrupts ECAN = 0; ETIM = 0; // Init the Mailbox for num_page =0; num_page IT’s on message objects 11 and 8. see Figure 46. Reset Value = x000 0000b 101 4129N–CAN–03/08 Table 67. CANSIT2 Register CANSIT2 (S:BBh Read Only) CAN Status Interrupt Message Object Registers 2 7 6 5 4 3 2 1 0 SIT7 SIT6 SIT5 SIT4 SIT3 SIT2 SIT1 SIT0 Bit Number 7-0 Bit Mnemonic Description SIT7:0 Status of Interrupt by Message Object 0 - no interrupt. 1 - IT turned on. Reset when interrupt condition is cleared by user. SIT7:0 = 0b 0000 1001 -> IT’s on message objects 3 and 0 see Figure 46. Reset Value = 0000 0000b Table 68. CANIE1 Register CANIE1 (S:C2h) CAN Enable Interrupt Message Object Registers 1 7 6 5 4 3 2 1 0 - IECH14 IECH13 IECH12 IECH11 IECH10 IECH9 IECH8 Bit Number 7 6-0 Bit Mnemonic Description - IECH14:8 Reserved The values read from this bit is indeterminate. Do not set this bit. Enable interrupt by Message Object 0 - disable IT. 1 - enable IT. IECH14:8 = 0b 0000 1100 -> Enable IT’s of message objects 11 and 10. see Figure 46. Reset Value = x000 0000b 102 A/T89C51CC01 4129N–CAN–03/08 A/T89C51CC01 Table 69. CANIE2 Register CANIE2 (S:C3h) CAN Enable Interrupt Message Object Registers 2 7 6 5 4 3 2 1 0 IECH 7 IECH 6 IECH 5 IECH 4 IECH 3 IECH 2 IECH 1 IECH 0 Bit Number 7-0 Bit Mnemonic Description IECH7:0 Enable interrupt by Message Object 0 - disable IT. 1 - enable IT. IECH7:0 = 0b 0000 1100 -> Enable IT’s of message objects 3 and 2. Reset Value = 0000 0000b Table 70. CANBT1 Register CANBT1 (S:B4h) CAN Bit Timing Registers 1 7 6 5 4 3 2 1 0 - BRP 5 BRP 4 BRP 3 BRP 2 BRP 1 BRP 0 - Bit Number 7 Bit Mnemonic Description - Reserved The value read from this bit is indeterminate. Do not set this bit. Baud rate prescaler The period of the CAN controller system clock Tscl is programmable and determines the individual bit timing. 6-1 BRP5:0 BRP[5..0] + 1 Tscl = 0 Note: - Fcan Reserved The value read from this bit is indeterminate. Do not set this bit. The CAN controller bit timing registers must be accessed only if the CAN controller is disabled with the ENA bit of the CANGCON register set to 0. See Figure 48. No default value after reset. 103 4129N–CAN–03/08 Table 71. CANBT2 Register CANBT2 (S:B5h) CAN Bit Timing Registers 2 7 6 5 4 3 2 1 0 - SJW 1 SJW 0 - PRS 2 PRS 1 PRS 0 - Bit Number 7 6-5 Bit Mnemonic Description - SJW1:0 Reserved The value read from this bit is indeterminate. Do not set this bit. Re-synchronization Jump Width To compensate for phase shifts between clock oscillators of different bus controllers, the controller must re-synchronize on any relevant signal edge of the current transmission. The synchronization jump width defines the maximum number of clock cycles. A bit period may be shortened or lengthened by a re-synchronization. Tsjw = Tscl x (SJW [1..0] +1) 4 3-1 - PRS2:0 Reserved The value read from this bit is indeterminate. Do not set this bit. Programming Time Segment This part of the bit time is used to compensate for the physical delay times within the network. It is twice the sum of the signal propagation time on the bus line, the input comparator delay and the output driver delay. Tprs = Tscl x (PRS[2..0] + 1) 0 Note: - Reserved The value read from this bit is indeterminate. Do not set this bit. The CAN controller bit timing registers must be accessed only if the CAN controller is disabled with the ENA bit of the CANGCON register set to 0. See Figure 48. No default value after reset. 104 A/T89C51CC01 4129N–CAN–03/08 A/T89C51CC01 Table 72. CANBT3 Register CANBT3 (S:B6h) CAN Bit Timing Registers 3 7 6 5 4 3 2 1 0 - PHS2 2 PHS2 1 PHS2 0 PHS1 2 PHS1 1 PHS1 0 SMP Bit Number 7 Bit Mnemonic Description - Reserved The value read from this bit is indeterminate. Do not set this bit. Phase Segment 2 This phase is used to compensate for phase edge errors. This segment can be shortened by the re-synchronization jump width. 6-4 PHS2 2:0 Tphs2 = Tscl x (PHS2[2..0] + 1) Phase segment 2 is the maximum of Phase segment1 and the Information Processing Time (= 2TQ). 3-1 PHS1 2:0 Phase Segment 1 This phase is used to compensate for phase edge errors. This segment can be lengthened by the re-synchronization jump width. Tphs1 = Tscl x (PHS1[2..0] + 1) 0 Note: SMP Sample Type 0 - once, at the sample point. 1 - three times, the threefold sampling of the bus is the sample point and twice over a distance of a 1/2 period of the Tscl. The result corresponds to the majority decision of the three values. The CAN controller bit timing registers must be accessed only if the CAN controller is disabled with the ENA bit of the CANGCON register set to 0. See Figure 48. No default value after reset. 105 4129N–CAN–03/08 Table 73. CANPAGE Register CANPAGE (S:B1h) CAN Message Object Page Register 7 6 5 4 3 2 1 0 CHNB 3 CHNB 2 CHNB 1 CHNB 0 AINC INDX2 INDX1 INDX0 Bit Number Bit Mnemonic Description 7-4 CHNB3:0 3 AINC 2-0 INDX2:0 Selection of Message Object Number The available numbers are: 0 to 14 (see Figure 44). Auto Increment of the Index (active low) 0 - auto-increment of the index (default value). 1 - non-auto-increment of the index. Index Byte location of the data field for the defined message object (see Figure 44). Reset Value = 0000 0000b Table 74. CANCONCH Register CANCONCH (S:B3h) CAN Message Object Control and DLC Register 7 6 5 4 3 2 1 0 CONCH 1 CONCH 0 RPLV IDE DLC 3 DLC 2 DLC 1 DLC 0 Bit Number 7-6 Bit Mnemonic Description CONCH1:0 Configuration of Message Object CONCH1 CONCH0 0 0: disable 0 1: Launch transmission 1 0: Enable Reception 1 1: Enable Reception Buffer Note: The user must re-write the configuration to enable the corresponding bit in the CANEN1:2 registers. 5 RPLV 4 IDE 3-0 DLC3:0 Reply Valid Used in the automatic reply mode after receiving a remote frame 0 - reply not ready. 1 - reply ready and valid. Identifier Extension 0 - CAN standard rev 2.0 A (ident = 11 bits). 1 - CAN standard rev 2.0 B (ident = 29 bits). Data Length Code Number of Bytes in the data field of the message. The range of DLC is from 0 up to 8. This value is updated when a frame is received (data or remote frame). If the expected DLC differs from the incoming DLC, a warning appears in the CANSTCH register. No default value after reset 106 A/T89C51CC01 4129N–CAN–03/08 A/T89C51CC01 Table 75. CANSTCH Register CANSTCH (S:B2h) CAN Message Object Status Register 7 6 5 4 3 2 1 0 DLCW TXOK RXOK BERR SERR CERR FERR AERR Bit Number Bit Mnemonic Description DLCW Data Length Code Warning The incoming message does not have the DLC expected. Whatever the frame type, the DLC field of the CANCONCH register is updated by the received DLC. TXOK Transmit OK The communication enabled by transmission is completed. When the controller is ready to send a frame, if two or more message objects are enabled as producers, the lower index message object (0 to 13) is supplied first. This flag can generate an interrupt and it must be cleared by software. RXOK Receive OK The communication enabled by reception is completed. In the case of two or more message object reception hits, the lower index message object (0 to 13) is updated first. This flag can generate an interrupt and it must be cleared by software. 4 BERR Bit Error (Only in Transmission) The bit value monitored is different from the bit value sent. Exceptions: the monitored recessive bit sent as a dominant bit during the arbitration field and the acknowledge slot detecting a dominant bit during the sending of an error frame. This flag can generate an interrupt and it must be cleared by software. 3 SERR Stuff Error Detection of more than five consecutive bits with the same polarity. This flag can generate an interrupt and it must be cleared by software. 7 6 5 2 CERR CRC Error The receiver performs a CRC check on each destuffed received message from the start of frame up to the data field. If this checking does not match with the destuffed CRC field, a CRC error is set. This flag can generate an interrupt and it must be cleared by software. 1 FERR 0 AERR Form Error The form error results from one or more violations of the fixed form in the following bit fields: CRC delimiter acknowledgment delimiter end_of_frame This flag can generate an interrupt. Acknowledgment Error No detection of the dominant bit in the acknowledge slot. This flag can generate an interrupt and it must be cleared by software. Note: See Figure 46. No default value after reset. 107 4129N–CAN–03/08 Table 76. CANIDT1 Register for V2.0 part A CANIDT1 for V2.0 part A (S:BCh) CAN Identifier Tag Registers 1 7 6 5 4 3 2 1 0 IDT 10 IDT 9 IDT 8 IDT 7 IDT 6 IDT 5 IDT 4 IDT 3 Bit Number 7-0 Bit Mnemonic Description IDT10:3 IDentifier tag value See Figure 50. No default value after reset. Table 77. CANIDT2 Register for V2.0 part A CANIDT2 for V2.0 part A (S:BDh) CAN Identifier Tag Registers 2 7 6 5 4 3 2 1 0 IDT 2 IDT 1 IDT 0 - - - - - Bit Number Bit Mnemonic Description 7-5 IDT2:0 4-0 - IDentifier tag value See Figure 50. Reserved The values read from these bits are indeterminate. Do not set these bits. No default value after reset. Table 78. CANIDT3 Register for V2.0 part A CANIDT3 for V2.0 part A (S:BEh) CAN Identifier Tag Registers 3 7 6 5 4 3 2 1 0 - - - - - - - - Bit Number 7-0 Bit Mnemonic Description - Reserved The values read from these bits are indeterminate. Do not set these bits. No default value after reset. 108 A/T89C51CC01 4129N–CAN–03/08 A/T89C51CC01 Table 79. CANIDT4 Register for V2.0 part A CANIDT4 for V2.0 part A (S:BFh) CAN Identifier Tag Registers 4 7 6 5 4 3 2 1 0 - - - - - RTRTAG - RB0TAG Bit Number Bit Mnemonic Description 7-3 - 2 RTRTAG 1 - 0 RB0TAG Reserved The values read from these bits are indeterminate. Do not set these bits. Remote Transmission Request Tag Value. Reserved The values read from this bit are indeterminate. Do not set these bit. Reserved Bit 0 Tag Value. No default value after reset. Table 80. CANIDT1 Register for V2.0 part B CANIDT1 for V2.0 part B (S:BCh) CAN Identifier Tag Registers 1 7 6 5 4 3 2 1 0 IDT 28 IDT 27 IDT 26 IDT 25 IDT 24 IDT 23 IDT 22 IDT 21 Bit Number 7-0 Bit Mnemonic Description IDT28:21 IDentifier Tag Value See Figure 50. No default value after reset. Table 81. CANIDT2 Register for V2.0 part B CANIDT2 for V2.0 part B (S:BDh) CAN Identifier Tag Registers 2 7 6 5 4 3 2 1 0 IDT 20 IDT 19 IDT 18 IDT 17 IDT 16 IDT 15 IDT 14 IDT 13 Bit Number 7-0 Bit Mnemonic Description IDT20:13 IDentifier Tag Value See Figure 50. No default value after reset. 109 4129N–CAN–03/08 Table 82. CANIDT3 Register for V2.0 part B CANIDT3 for V2.0 part B (S:BEh) CAN Identifier Tag Registers 3 7 6 5 4 3 2 1 0 IDT 12 IDT 11 IDT 10 IDT 9 IDT 8 IDT 7 IDT 6 IDT 5 Bit Number 7-0 Bit Mnemonic Description IDT12:5 IDentifier Tag Value See Figure 50. No default value after reset. Table 83. CANIDT4 Register for V2.0 part B CANIDT4 for V2.0 part B (S:BFh) CAN Identifier Tag Registers 4 7 6 5 4 3 2 1 0 IDT 4 IDT 3 IDT 2 IDT 1 IDT 0 RTRTAG RB1TAG RB0TAG Bit Number Bit Mnemonic Description IDentifier Tag Value See Figure 50. 7-3 IDT4:0 2 RTRTAG Remote Transmission Request Tag Value 1 RB1TAG Reserved bit 1 Tag Value 0 RB0TAG Reserved bit 0 Tag Value No default value after reset. Table 84. CANIDM1 Register for V2.0 part A CANIDM1 for V2.0 part A (S:C4h) CAN Identifier Mask Registers 1 7 6 5 4 3 2 1 0 IDMSK 10 IDMSK 9 IDMSK 8 IDMSK 7 IDMSK 6 IDMSK 5 IDMSK 4 IDMSK 3 Bit Number 7-0 Bit Mnemonic Description IDTMSK10:3 IDentifier mask value 0 - comparison true forced. 1 - bit comparison enabled. See Figure 50. No default value after reset. 110 A/T89C51CC01 4129N–CAN–03/08 A/T89C51CC01 Table 85. CANIDM2 Register for V2.0 part A CANIDM2 for V2.0 part A (S:C5h) CAN Identifier Mask Registers 2 7 6 5 4 3 2 1 0 IDMSK 2 IDMSK 1 IDMSK 0 - - - - - Bit Number Bit Mnemonic Description 7-5 IDTMSK2:0 4-0 - IDentifier Mask Value 0 - comparison true forced. 1 - bit comparison enabled. See Figure 50. Reserved The values read from these bits are indeterminate. Do not set these bits. No default value after reset. Table 86. CANIDM3 Register for V2.0 part A CANIDM3 for V2.0 part A (S:C6h) CAN Identifier Mask Registers 3 7 6 5 4 3 2 1 0 - - - - - - - - Bit Number 7-0 Bit Mnemonic Description - Reserved The values read from these bits are indeterminate. No default value after reset. 111 4129N–CAN–03/08 Table 87. CANIDM4 Register for V2.0 part A CANIDM4 for V2.0 part A (S:C7h) CAN Identifier Mask Registers 4 7 6 5 4 3 2 1 0 - - - - - RTRMSK - IDEMSK Bit Number Bit Mnemonic Description 7-3 - 2 RTRMSK 1 - 0 IDEMSK Note: Reserved The values read from these bits are indeterminate. Do not set these bits. Remote Transmission Request Mask Value 0 - comparison true forced. 1 - bit comparison enabled. Reserved The value read from this bit is indeterminate. Do not set this bit. IDentifier Extension Mask Value 0 - comparison true forced. 1 - bit comparison enabled. The ID Mask is only used for reception. No default value after reset. Table 88. CANIDM1 Register for V2.0 part B CANIDM1 for V2.0 part B (S:C4h) CAN Identifier Mask Registers 1 7 6 5 4 3 2 1 0 IDMSK 28 IDMSK 27 IDMSK 26 IDMSK 25 IDMSK 24 IDMSK 23 IDMSK 22 IDMSK 21 Bit Number 7-0 Note: Bit Mnemonic Description IDMSK28:21 IDentifier Mask Value 0 - comparison true forced. 1 - bit comparison enabled. See Figure 50. The ID Mask is only used for reception. No default value after reset. 112 A/T89C51CC01 4129N–CAN–03/08 A/T89C51CC01 Table 89. CANIDM2 Register for V2.0 part B CANIDM2 for V2.0 part B (S:C5h) CAN Identifier Mask Registers 2 7 6 5 4 3 2 1 0 IDMSK 20 IDMSK 19 IDMSK 18 IDMSK 17 IDMSK 16 IDMSK 15 IDMSK 14 IDMSK 13 Bit Number 7-0 Note: Bit Mnemonic Description IDMSK20:13 IDentifier Mask Value 0 - comparison true forced. 1 - bit comparison enabled. See Figure 50. The ID Mask is only used for reception. No default value after reset. Table 90. CANIDM3 Register for V2.0 part B CANIDM3 for V2.0 part B (S:C6h) CAN Identifier Mask Registers 3 7 6 5 4 3 2 1 0 IDMSK 12 IDMSK 11 IDMSK 10 IDMSK 9 IDMSK 8 IDMSK 7 IDMSK 6 IDMSK 5 Bit Number 7-0 Note: Bit Mnemonic Description IDMSK12:5 IDentifier Mask Value 0 - comparison true forced. 1 - bit comparison enabled. See Figure 50. The ID Mask is only used for reception. No default value after reset. 113 4129N–CAN–03/08 Table 91. CANIDM4 Register for V2.0 part B CANIDM4 for V2.0 part B (S:C7h) CAN Identifier Mask Registers 4 7 6 5 4 3 2 1 0 IDMSK 4 IDMSK 3 IDMSK 2 IDMSK 1 IDMSK 0 RTRMSK - IDEMSK Bit Number Bit Mnemonic Description 7-3 IDMSK4:0 IDentifier Mask Value 0 - comparison true forced. 1 - bit comparison enabled. See Figure 50. 2 RTRMSK Remote Transmission Request Mask Value 0 - comparison true forced. 1 - bit comparison enabled. 1 - 0 IDEMSK Note: Reserved The value read from this bit is indeterminate. Do not set this bit. IDentifier Extension Mask Value 0 - comparison true forced. 1 - bit comparison enabled. The ID Mask is only used for reception. No default value after reset. Table 92. CANMSG Register CANMSG (S:A3h) CAN Message Data Register 7 6 5 4 3 2 1 0 MSG 7 MSG 6 MSG 5 MSG 4 MSG 3 MSG 2 MSG 1 MSG 0 Bit Number 7-0 Bit Mnemonic Description MSG7:0 Message Data This register contains the mailbox data byte pointed at the page message object register. After writing in the page message object register, this byte is equal to the specified message location (in the mailbox) of the pre-defined identifier + index. If auto-incrementation is used, at the end of the data register writing or reading cycle, the mailbox pointer is auto-incremented. The range of the counting is 8 with no end loop (0, 1,..., 7, 0,...) No default value after reset. 114 A/T89C51CC01 4129N–CAN–03/08 A/T89C51CC01 Table 93. CANTCON Register CANTCON (S:A1h) CAN Timer ClockControl 7 6 5 4 3 2 1 0 TPRESC 7 TPRESC 6 TPRESC 5 TPRESC 4 TPRESC 3 TPRESC 2 TPRESC 1 TPRESC 0 Bit Number 7-0 Bit Mnemonic Description Timer Prescaler of CAN Timer This register is a prescaler for the main timer upper counter range = 0 to 255. See Figure 51. TPRESC7:0 Reset Value = 00h Table 94. CANTIMH Register CANTIMH (S:ADh) CAN Timer High 7 6 5 4 3 2 CANGTIM 15 CANGTIM 14 CANGTIM 13 CANGTIM 12 CANGTIM 11 CANGTIM 10 Bit Number Bit Mnemonic Description 7-0 CANGTIM15:8 High byte of Message Timer See Figure 51. 1 0 CANGTIM 9 CANGTIM 8 Reset Value = 0000 0000b Table 95. CANTIML Register CANTIML (S:ACh) CAN Timer Low 7 6 5 4 3 2 1 0 CANGTIM 7 CANGTIM 6 CANGTIM 5 CANGTIM 4 CANGTIM 3 CANGTIM 2 CANGTIM 1 CANGTIM 0 Bit Number 7-0 Bit Mnemonic Description CANGTIM7:0 Low byte of Message Timer See Figure 51. Reset Value = 0000 0000b 115 4129N–CAN–03/08 Table 96. CANSTMPH Register CANSTMPH (S:AFh Read Only) CAN Stamp Timer High 7 6 5 4 3 2 TIMSTMP 15 TIMSTMP 14 TIMSTMP 13 TIMSTMP 12 TIMSTMP 11 TIMSTMP 10 Bit Number Bit Mnemonic Description 7-0 TIMSTMP15:8 High byte of Time Stamp See Figure 51. 1 0 TIMSTMP 9 TIMSTMP 8 No default value after reset Table 97. CANSTMPL Register CANSTMPL (S:AEh Read Only) CAN Stamp Timer Low 7 6 5 4 3 2 1 0 TIMSTMP 7 TIMSTMP 6 TIMSTMP 5 TIMSTMP 4 TIMSTMP 3 TIMSTMP 2 TIMSTMP 1 TIMSTMP 0 Bit Number 7-0 Bit Mnemonic Description TIMSTMP7:0 Low byte of Time Stamp See Figure 51. No default value after reset Table 98. CANTTCH Register CANTTCH (S:A5h Read Only) CAN TTC Timer High 7 6 5 4 3 2 1 0 TIMTTC 15 TIMTTC 14 TIMTTC 13 TIMTTC 12 TIMTTC 11 TIMTTC 10 TIMTTC 9 TIMTTC 8 Bit Number 7-0 Bit Mnemonic Description TIMTTC15:8 High byte of TTC Timer See Figure 51. Reset Value = 0000 0000b 116 A/T89C51CC01 4129N–CAN–03/08 A/T89C51CC01 Table 99. CANTTCL Register CANTTCL (S:A4h Read Only) CAN TTC Timer Low 7 6 5 4 3 2 1 0 TIMTTC 7 TIMTTC 6 TIMTTC 5 TIMTTC 4 TIMTTC 3 TIMTTC 2 TIMTTC 1 TIMTTC 0 Bit Number 7-0 Bit Mnemonic Description TIMTTC7:0 Low byte of TTC Timer See Figure 51. Reset Value = 0000 0000b 117 4129N–CAN–03/08 Programmable Counter Array (PCA) The PCA provides more timing capabilities with less CPU intervention than the standard timer/counters. Its advantages include reduced software overhead and improved accuracy. The PCA consists of a dedicated timer/counter which serves as the time base for an array of five compare/capture modules. Its clock input can be programmed to count any of the following signals: • PCA clock frequency/6 (see “clock” section) • PCA clock frequency/2 • Timer 0 overflow • External input on ECI (P1.2) Each compare/capture modules can be programmed in any one of the following modes: • rising and/or falling edge capture, • software timer, • high-speed output, • pulse width modulator. Module 4 can also be programmed as a Watchdog timer. see the "PCA Watchdog Timer" section. When the compare/capture modules are programmed in capture mode, software timer, or high speed output mode, an interrupt can be generated when the module executes its function. All five modules plus the PCA timer overflow share one interrupt vector. The PCA timer/counter and compare/capture modules share Port 1 for external I/Os. These pins are listed below. If the pin is not used for the PCA, it can still be used for standard I/O. PCA Timer 118 PCA Component External I/O Pin 16-bit Counter P1.2/ECI 16-bit Module 0 P1.3/CEX0 16-bit Module 1 P1.4/CEX1 16-bit Module 2 P1.5/CEX2 16-bit Module 3 P1.6/CEX3 16-bit Module 4 P1.7/CEX4 The PCA timer is a common time base for all five modules (see Figure 53). The timer count source is determined from the CPS1 and CPS0 bits in the CMOD SFR (see Table 8) and can be programmed to run at: • 1/6 the PCA clock frequency. • 1/2 the PCA clock frequency. • the Timer 0 overflow. • the input on the ECI pin (P1.2). A/T89C51CC01 4129N–CAN–03/08 A/T89C51CC01 Figure 53. PCA Timer/Counter To PCA modules FPca/6 overflow FPca/2 CH T0 OVF It CL 16 bit up counter P1.2 CIDL WDTE CF CR CPS1 CPS0 ECF CMOD 0xD9 Idle CCF4 CCF3 CCF2 CCF1 CCF0 CCON 0xD8 The CMOD register includes three additional bits associated with the PCA. • The CIDL bit which allows the PCA to stop during idle mode. • The WDTE bit which enables or disables the Watchdog function on module 4. • The ECF bit which when set causes an interrupt and the PCA overflow flag CF in CCON register to be set when the PCA timer overflows. The CCON register contains the run control bit for the PCA and the flags for the PCA timer and each module. PCA Modules • The CR bit must be set to run the PCA. The PCA is shut off by clearing this bit. • The CF bit is set when the PCA counter overflows and an interrupt will be generated if the ECF bit in CMOD register is set. The CF bit can only be cleared by software. • The CCF0:4 bits are the flags for the modules (CCF0 for module0...) and are set by hardware when either a match or a capture occurs. These flags also can be cleared by software. Each one of the five compare/capture modules has six possible functions. It can perform: • 16-bit Capture, positive-edge triggered • 16-bit Capture, negative-edge triggered • 16-bit Capture, both positive and negative-edge triggered • 16-bit Software Timer • 16-bit High Speed Output • 8-bit Pulse Width Modulator. In addition module 4 can be used as a Watchdog Timer. 119 4129N–CAN–03/08 Each module in the PCA has a special function register associated with it (CCAPM0 for module 0 ...). The CCAPM0:4 registers contain the bits that control the mode that each module will operate in. • The ECCF bit enables the CCF flag in the CCON register to generate an interrupt when a match or compare occurs in the associated module. • The PWM bit enables the pulse width modulation mode. • The TOG bit when set causes the CEX output associated with the module to toggle when there is a match between the PCA counter and the module’s capture/compare register. • The match bit MAT when set will cause the CCFn bit in the CCON register to be set when there is a match between the PCA counter and the module’s capture/compare register. • The two bits CAPN and CAPP in CCAPMn register determine the edge that a capture input will be active on. The CAPN bit enables the negative edge, and the CAPP bit enables the positive edge. If both bits are set both edges will be enabled. • The bit ECOM in CCAPM register when set enables the comparator function. PCA Interrupt Figure 54. PCA Interrupt System CF CR CCF4 CCF3 CCF2 CCF1 CCF0 CCON PCA Timer/Counter Module 0 Module 1 To Interrupt Module 2 Module 3 Module 4 ECF CMOD.0 PCA Capture Mode 120 ECCFn EC EA CCAPMn.0 IEN0.6 IEN0.7 To use one of the PCA modules in capture mode either one or both of the CCAPM bits CAPN and CAPP for that module must be set. The external CEX input for the module (on port 1) is sampled for a transition. When a valid transition occurs the PCA hardware loads the value of the PCA counter registers (CH and CL) into the module’s capture registers (CCAPnL and CCAPnH). If the CCFn bit for the module in the CCON SFR and the ECCFn bit in the CCAPMn SFR are set then an interrupt will be generated. A/T89C51CC01 4129N–CAN–03/08 A/T89C51CC01 Figure 55. PCA Capture Mode PCA Counter CH CL (8bits) (8bits) CEXn n = 0, 4 CCAPnH CCAPnL PCA Interrupt Request CCFn CCON - 0CAPPn CAPNn 000 ECCFn 0 7 CCAPMn Register (n = 0, 4) 16-bit Software Timer Mode The PCA modules can be used as software timers by setting both the ECOM and MAT bits in the modules CCAPMn register. The PCA timer will be compared to the module’s capture registers and when a match occurs an interrupt will occur if the CCFn (CCON SFR) and the ECCFn (CCAPMn SFR) bits for the module are both set. Figure 56. PCA 16-bit Software Timer and High Speed Output Mode PCA Counter CH CL (8 bits) (8 bits) Compare/Capture Module CCAPnL CCAPnH (8 bits) (8 bits) Match Toggle 16-Bit Comparator CEXn Enable CCFn CCON reg 7 “0” Reset Write to CCAPnL “1” PCA Interrupt Request ECOMn0 0 MATn TOGn0 ECCFn 0 CCAPMn Register (n = 0, 4) For software Timer mode, set ECOMn and MATn. For high speed output mode, set ECOMn, MATn and TOGn. Write to CCAPnH 121 4129N–CAN–03/08 High Speed Output Mode In this mode the CEX output (on port 1) associated with the PCA module will toggle each time a match occurs between the PCA counter and the module’s capture registers. To activate this mode the TOG, MAT, and ECOM bits in the module’s CCAPMn SFR must be set. Figure 57. PCA High Speed Output Mode CCON CF Write to CCAPnH CR CCF4 CCF3 CCF2 CCF1 CCF0 0xD8 Reset PCA IT Write to CCAPnL “0” CCAPnH “1” CCAPnL Enable 16-bit comparator CH Match CL CEXn PCA counter/timer ECOMn CAPPn CAPNn MATn TOGn PWMn ECCFn Pulse Width Modulator Mode 122 CCAPMn, n = 0 to 4 0xDA to 0xDE All the PCA modules can be used as PWM outputs. The output frequency depends on the source for the PCA timer. All the modules will have the same output frequency because they all share the PCA timer. The duty cycle of each module is independently variable using the module’s capture register CCAPLn. When the value of the PCA CL SFR is less than the value in the module’s CCAPLn SFR the output will be low, when it is equal to or greater than it, the output will be high. When CL overflows from FF to 00, CCAPLn is reloaded with the value in CCAPHn. the allows the PWM to be updated without glitches. The PWM and ECOM bits in the module’s CCAPMn register must be set to enable the PWM mode. A/T89C51CC01 4129N–CAN–03/08 A/T89C51CC01 Figure 58. PCA PWM Mode CCAPnH CL rolls over from FFh TO 00h loads CCAPnH contents into CCAPnL CCAPnL “0” CL < CCAPnL 8-Bit Comparator CL (8 bits) CEX CL > = CCAPnL “1” PCA Watchdog Timer ECOMn PWMn CCAPMn.6 CCAPMn.1 An on-board Watchdog timer is available with the PCA to improve system reliability without increasing chip count. Watchdog timers are useful for systems that are sensitive to noise, power glitches, or electrostatic discharge. Module 4 is the only PCA module that can be programmed as a Watchdog. However, this module can still be used for other modes if the Watchdog is not needed. The user pre-loads a 16-bit value in the compare registers. Just like the other compare modes, this 16-bit value is compared to the PCA timer value. If a match is allowed to occur, an internal reset will be generated. This will not cause the RST pin to be driven high. To hold off the reset, the user has three options: • periodically change the compare value so it will never match the PCA timer, • periodically change the PCA timer value so it will never match the compare values, or • disable the Watchdog by clearing the WDTE bit before a match occurs and then reenable it. The first two options are more reliable because the Watchdog timer is never disabled as in the third option. If the program counter ever goes astray, a match will eventually occur and cause an internal reset. If other PCA modules are being used the second option not recommended either. Remember, the PCA timer is the time base for all modules; changing the time base for other modules would not be a good idea. Thus, in most applications the first solution is the best option. 123 4129N–CAN–03/08 PCA Registers Table 100. CMOD Register CMOD (S:D9h) PCA Counter Mode Register 7 6 5 4 3 2 1 0 CIDL WDTE - - - CPS1 CPS0 ECF Bit Number Bit Mnemonic Description PCA Counter Idle Control bit Clear to let the PCA run during Idle mode. Set to stop the PCA when Idle mode is invoked. 7 CIDL 6 WDTE 5 - Reserved The value read from this bit is indeterminate. Do not set this bit. 4 - Reserved The value read from this bit is indeterminate. Do not set this bit. 3 - Reserved The value read from this bit is indeterminate. Do not set this bit. 2-1 CPS1:0 0 ECF Watchdog Timer Enable Clear to disable Watchdog Timer function on PCA Module 4, Set to enable it. EWC Count Pulse Select bits CPS1 CPS0 Clock source 0 0 Internal Clock, FPca/6 0 1 Internal Clock, FPca/2 1 0 Timer 0 overflow 1 1 External clock at ECI/P1.2 pin (Max. Rate = FPca/4) Enable PCA Counter Overflow Interrupt bit Clear to disable CF bit in CCON register to generate an interrupt. Set to enable CF bit in CCON register to generate an interrupt. Reset Value = 00XX X000b 124 A/T89C51CC01 4129N–CAN–03/08 A/T89C51CC01 Table 101. CCON Register CCON (S:D8h) PCA Counter Control Register 7 6 5 4 3 2 1 0 CF CR - CCF4 CCF3 CCF2 CCF1 CCF0 Bit Number Bit Mnemonic Description 7 CF PCA Timer/Counter Overflow flag Set by hardware when the PCA Timer/Counter rolls over. This generates a PCA interrupt request if the ECF bit in CMOD register is set. Must be cleared by software. 6 CR PCA Timer/Counter Run Control bit Clear to turn the PCA Timer/Counter off. Set to turn the PCA Timer/Counter on. 5 - 4 3 2 1 0 Reserved The value read from this bit is indeterminate. Do not set this bit. CCF4 PCA Module 4 Compare/Capture flag Set by hardware when a match or capture occurs. This generates a PCA interrupt request if the ECCF 4 bit in CCAPM 4 register is set. Must be cleared by software. CCF3 PCA Module 3 Compare/Capture flag Set by hardware when a match or capture occurs. This generates a PCA interrupt request if the ECCF 3 bit in CCAPM 3 register is set. Must be cleared by software. CCF2 PCA Module 2 Compare/Capture flag Set by hardware when a match or capture occurs. This generates a PCA interrupt request if the ECCF 2 bit in CCAPM 2 register is set. Must be cleared by software. CCF1 PCA Module 1 Compare/Capture flag Set by hardware when a match or capture occurs. This generates a PCA interrupt request if the ECCF 1 bit in CCAPM 1 register is set. Must be cleared by software. CCF0 PCA Module 0 Compare/Capture flag Set by hardware when a match or capture occurs. This generates a PCA interrupt request if the ECCF 0 bit in CCAPM 0 register is set. Must be cleared by software. Reset Value = 00X0 0000b 125 4129N–CAN–03/08 Table 102. CCAPnH Registers CCAP0H (S:FAh) CCAP1H (S:FBh) CCAP2H (S:FCh) CCAP3H (S:FDh) CCAP4H (S:FEh) PCA High Byte Compare/Capture Module n Register (n=0..4) 7 6 5 4 3 2 1 0 CCAPnH 7 CCAPnH 6 CCAPnH 5 CCAPnH 4 CCAPnH 3 CCAPnH 2 CCAPnH 1 CCAPnH 0 Bit Number 7:0 Bit Mnemonic Description CCAPnH 7:0 High byte of EWC-PCA comparison or capture values Reset Value = 0000 0000b Table 103. CCAPnL Registers CCAP0L (S:EAh) CCAP1L (S:EBh) CCAP2L (S:ECh) CCAP3L (S:EDh) CCAP4L (S:EEh) PCA Low Byte Compare/Capture Module n Register (n=0..4) 7 6 5 4 3 2 1 0 CCAPnL 7 CCAPnL 6 CCAPnL 5 CCAPnL 4 CCAPnL 3 CCAPnL 2 CCAPnL 1 CCAPnL 0 Bit Number 7:0 Bit Mnemonic Description CCAPnL 7:0 Low byte of EWC-PCA comparison or capture values Reset Value = 0000 0000b 126 A/T89C51CC01 4129N–CAN–03/08 A/T89C51CC01 Table 104. CCAPMn Registers CCAPM0 (S:DAh) CCAPM1 (S:DBh) CCAPM2 (S:DCh) CCAPM3 (S:DDh) CCAPM4 (S:DEh) PCA Compare/Capture Module n Mode registers (n=0..4) 7 6 5 4 3 2 1 0 - ECOMn CAPPn CAPNn MATn TOGn PWMn ECCFn Bit Number 7 Bit Mnemonic Description - Reserved The Value read from this bit is indeterminate. Do not set this bit. 6 ECOMn Enable Compare Mode Module x bit Clear to disable the Compare function. Set to enable the Compare function. The Compare function is used to implement the software Timer, the high-speed output, the Pulse Width Modulator (PWM) and the Watchdog Timer (WDT). 5 CAPPn Capture Mode (Positive) Module x bit Clear to disable the Capture function triggered by a positive edge on CEXx pin. Set to enable the Capture function triggered by a positive edge on CEXx pin 4 CAPNn Capture Mode (Negative) Module x bit Clear to disable the Capture function triggered by a negative edge on CEXx pin. Set to enable the Capture function triggered by a negative edge on CEXx pin. 3 MATn Match Module x bit Set when a match of the PCA Counter with the Compare/Capture register sets CCFx bit in CCON register, flagging an interrupt. 2 TOGn Toggle Module x bit The toggle mode is configured by setting ECOMx, MATx and TOGx bits. Set when a match of the PCA Counter with the Compare/Capture register toggles the CEXx pin. 1 PWMn Pulse Width Modulation Module x Mode bit Set to configure the module x as an 8-bit Pulse Width Modulator with output waveform on CEXx pin. 0 ECCFn Enable CCFx Interrupt bit Clear to disable CCFx bit in CCON register to generate an interrupt request. Set to enable CCFx bit in CCON register to generate an interrupt request. Reset Value = X000 0000b 127 4129N–CAN–03/08 Table 105. CH Register CH (S:F9h) PCA Counter Register High Value 7 6 5 4 3 2 1 0 CH 7 CH 6 CH 5 CH 4 CH 3 CH 2 CH 1 CH 0 Bit Number 7:0 Bit Mnemonic Description CH 7:0 High byte of Timer/Counter Reset Value = 0000 00000b Table 106. CL Register CL (S:E9h) PCA counter Register Low Value 7 6 5 4 3 2 1 0 CL 7 CL 6 CL 5 CL 4 CL 3 CL 2 CL 1 CL 0 Bit Number 7:0 Bit Mnemonic Description CL0 7:0 Low byte of Timer/Counter Reset Value = 0000 00000b 128 A/T89C51CC01 4129N–CAN–03/08 A/T89C51CC01 Analog-to-Digital Converter (ADC) This section describes the on-chip 10 bit analog-to-digital converter of the T89C51CC01. Eight ADC channels are available for sampling of the external sources AN0 to AN7. An analog multiplexer allows the single ADC converter to select one from the 8 ADC channels as ADC input voltage (ADCIN). ADCIN is converted by the 10-bit cascaded potentiometric ADC. Two modes of conversion are available: - Standard conversion (8 bits). - Precision conversion (10 bits). For the precision conversion, set bit PSIDLE in ADCON register and start conversion. The device is in a pseudo-idle mode, the CPU does not run but the peripherals are always running. This mode allows digital noise to be as low as possible, to ensure high precision conversion. For this mode it is necessary to work with end of conversion interrupt, which is the only way to wake the device up. If another interrupt occurs during the precision conversion, it will be served only after this conversion is completed. Features • 8 channels with multiplexed inputs • 10-bit cascaded potentiometric ADC • Conversion time 16 micro-seconds (typ.) • Zero Error (offset) ± 2 LSB max • Positive External Reference Voltage Range (VAREF) 2.4 to 3.0 Volt (typ.) • ADCIN Range 0 to 3Volt • Integral non-linearity typical 1 LSB, max. 2 LSB • Differential non-linearity typical 0.5 LSB, max. 1 LSB • Conversion Complete Flag or Conversion Complete Interrupt • Selectable ADC Clock ADC Port 1 I/O Functions Port 1 pins are general I/O that are shared with the ADC channels. The channel select bit in ADCF register define which ADC channel/port1 pin will be used as ADCIN. The remaining ADC channels/port1 pins can be used as general-purpose I/O or as the alternate function that is available. A conversion launched on a channel which are not selected on ADCF register will not have any effect. VAREF VAREF should be connected to a low impedance point and must remain in the range specified in Table 122. If the ADC is not used, it is recommended to connect VAREF to VAGND. 129 4129N–CAN–03/08 Figure 59. ADC Description ADCON.5 ADCON.3 ADEN ADSST ADC Interrupt Request ADCON.4 ADEOC ADC CLOCK CONTROL EADC AN0/P1.0 000 AN1/P1.1 001 AN2/P1.2 010 AN3/P1.3 011 AN4/P1.4 100 AN5/P1.5 101 AN6/P1.6 110 AN7/P1.7 IEN1.1 ADCIN Rai SAR Cai AVSS ADDH 2 ADDL - Sample and Hold 111 8 + 10 R/2R DAC SCH2 SCH1 SCH0 ADCON.2 ADCON.1 ADCON.0 VAREF VAGND Figure 60 shows the timing diagram of a complete conversion. For simplicity, the figure depicts the waveforms in idealized form and do not provide precise timing information. For ADC characteristics and timing parameters refer to the Section “AC Characteristics” of the T89C51CC01 datasheet. Figure 60. Timing Diagram CLK ADEN TSETUP (1) ADSST TCONV (2) ADEOC Notes: 130 1. Tsetup min, see the AC Parameter for A/D conversion. 2. Tconv = 11 clock ADC = 1sample and hold + 10 bit conversion The user must ensure that Tsetup time between setting ADEN and the start of the first conversion. A/T89C51CC01 4129N–CAN–03/08 A/T89C51CC01 ADC Converter Operation A start of single A/D conversion is triggered by setting bit ADSST (ADCON.3). After completion of the A/D conversion, the ADSST bit is cleared by hardware. The end-of-conversion flag ADEOC (ADCON.4) is set when the value of conversion is available in ADDH and ADDL, it must be cleared by software. If the bit EADC (IEN1.1) is set, an interrupt occur when flag ADEOC is set (see Figure 62). Clear this flag for rearming the interrupt. The bits SCH0 to SCH2 in ADCON register are used for the analog input channel selection.(1) Note: 1. Always leave Tsetup time before starting a conversion unless ADEN is permanently high. In this case one should wait Tsetup only before the first conversion. Table 107. Selected Analog input Voltage Conversion SCH1 SCH0 Selected Analog input 0 0 0 AN0 0 0 1 AN1 0 1 0 AN2 0 1 1 AN3 1 0 0 AN4 1 0 1 AN5 1 1 0 AN6 1 1 1 AN7 When the ADCIN is equals to VAREF the ADC converts the signal to 3FFh (full scale). If the input voltage equals VAGND, the ADC converts it to 000h. Input voltage between VAREF and VAGND are a straight-line linear conversion. All other voltages will result in 3FFh if greater than VAREF and 000h if less than VAGND. Note: Clock Selection SCH2 ADCIN should not exceed VAREF absolute maximum range (see “Absolute Maximum Ratings” on page 144) The ADC clock is the same as CPU. The maximum clock frequency is defined in the DC parmeters for A/D converter. A prescaler is featured (ADCCLK) to generate the ADC clock from the oscillator frequency. if PRS > 0 then fADC = Fperiph / 2 x PRS if PRS = 0 then fADC = Fperiph / 64 131 4129N–CAN–03/08 Figure 61. A/D Converter clock CPU CLOCK ADC Clock Prescaler ADCLK ÷2 A/D CPU Core Clock Symbol Converter ADC Standby Mode When the ADC is not used, it is possible to set it in standby mode by clearing bit ADEN in ADCON register. In this mode its power dissipation is reduced. IT ADC Management An interrupt end-of-conversion will occurs when the bit ADEOC is activated and the bit EADC is set. For re-arming the interrupt the bit ADEOC must be cleared by software. Figure 62. ADC Interrupt Structure ADCI ADEOC ADCON.2 EADC IEN1.1 Routines examples 1. Configure P1.2 and P1.3 in ADC channels // configure channel P1.2 and P1.3 for ADC ADCF = 0Ch // Enable the ADC ADCON = 20h 2. Start a standard conversion // The variable "channel" contains the channel to convert // The variable "value_converted" is an unsigned int // Clear the field SCH[2:0] ADCON and = F8h // Select channel ADCON | = channel // Start conversion in standard mode ADCON | = 08h // Wait flag End of conversion while((ADCON and 01h)! = 01h) // Clear the End of conversion flag ADCON and = EFh // read the value value_converted = (ADDH