TC6320TG-G

TC6320 N-Channel and P-Channel Enhancement-Mode MOSFET Pair Features General Description • • • • • • • • • The TC6320 consists of high-voltage, low-threshold N-channel and P-channel MOSFETs in 8-lead SOIC and DFN packages. Both MOSFETs have integrated gate-to-source resistors and gate-to-source Zener diode clamps which are desired for high-voltage pulser applications. It is a complimentary, high-speed, high-voltage, gate-clamped N-channel and P-channel MOSFET pair, which utilizes an advanced vertical DMOS structure and a well-proven silicon gate manufacturing process. This combination produces a device with the power handling capabilities of bipolar transistors and with the high input impedance and positive temperature coefficient inherent in MOS devices. Characteristic of all MOS structures, this device is free from thermal runaway and thermally induced secondary breakdown. Integrated Gate-to-source Resistor Integrated Gate-to-source Zener Diode Low Threshold Low On-resistance Low Input Capacitance Fast Switching Speeds Free from Secondary Breakdown Low Input and Output Leakage Independent Electrically Isolated N-channel and P-channel Applications • • • • • • High-voltage Pulsers Amplifiers Buffers Piezoelectric Transducer Drivers General Purpose Line Drivers Logic-level Interfaces Microchip’s vertical DMOS FETs are ideally suited to a wide range of switching and amplifying applications where very low threshold voltage, high breakdown voltage, high input impedance, low input capacitance and fast switching speeds are desired. Package Types 8-lead SOIC (Top view) 5-lead DFN (Top view) SN 1 8 DN GN 2 7 DN GN SP 3 6 DP GP GP 4 5 DP SN 1 8 DN 2 7 DN 3 6 DP 5 DP DN DP SP 4 See Table 2-1 and Table 2-2 for pin information.  2017 Microchip Technology Inc. DS20005697A-page 1 TC6320 Functional Block Diagram SN GN DN N-Channel DN P-Channel DS20005697A-page 2 GP DP SP DP  2017 Microchip Technology Inc. TC6320 Typical Application Circuit VDD +100V VH OE 10nF INA INB 10nF VSS MD12xx, MD17xx, or MD18xx  2017 Microchip Technology Inc. -100V VL TC6320 DS20005697A-page 3 TC6320 1.0 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings† Drain-to-source Voltage ........................................................................................................................................ BVDSS Drain-to-gate Voltage ........................................................................................................................................... BVDGS Operating Ambient Temperature, TA ................................................................................................... –55°C to +150°C Storage Temperature, TS ..................................................................................................................... –55°C to +150°C † Notice: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at those or any other conditions above those indicated in the operational sections of this specification is not intended. Exposure to maximum rating conditions for extended periods may affect device reliability. N-CHANNEL ELECTRICAL CHARACTERISTICS Electrical Specifications: TA = TJ = 25°C unless otherwise specified. Parameter Sym. Min. Typ. Max. Unit Conditions — — V VGS = 0V, ID = 2 mA V VGS = VDS, ID = 1 mA DC PARAMETER (Note 1 unless otherwise specified) Drain-to-source Breakdown Voltage Gate Threshold Voltage Change in VGS(th) with Temperature BVDSS 200 VGS(th) 1 — 2 ∆VGS(th) — — –4.5 mV/°C VGS = VDS, ID = 1 mA (Note 2) Gate-to-source Shunt Resistor RGS 10 — 50 kΩ IGS = 100 µA Gate-to-Source Zener Voltage VZGS 13.2 — 25 V IGS = 2 mA — — 10 µA VDS = Maximum rating,  VGS = 0V — — 1 mA VDS = 0.8 Maximum rating, VGS = 0V, TA = 125°C (Note 2) 1 — — Zero-gate Voltage Drain Current On-state Drain Current Static Drain-to-source On-state  Resistance Change in RDS(ON) with Temperature IDSS ID(ON) A VGS = 4.5V, VDS = 25V 2 — — — — 8 — — 7 ∆RDS(ON) — — 1 %/°C GFS 400 — — mmho VDS = 25V, ID = 500 mA RDS(ON) Ω VGS = 10V, VDS = 25V VGS = 4.5V, ID = 150 mA VGS = 10V, ID = 1A VGS = 4.5V, ID = 150 mA (Note 2) AC PARAMETER (Note 2) Forward Transconductance Input Capacitance CISS — — 110 Common Source Output Capacitance COSS — — 60 pF pF Reverse Transfer Capacitance CRSS — — 23 pF Turn-on Delay Time td(ON) — — 10 tr — — 15 ns ns td(OFF) — — 20 ns tf — — 15 ns VSD — — 1.8 V Rise Time Turn-off Delay Time Fall Time VGS = 0V, VDS = 25V, f = 1 MHz VDD = 25V, ID = 1A, RGEN = 25Ω DIODE PARAMETER Diode Forward Voltage Drop VGS = 0V, ISD = 500 mA (Note 1) Reverse Recovery Time trr — 300 — ns VGS = 0V, ISD = 500 mA (Note 2) Note 1: All DC parameters are 100% tested at 25°C unless otherwise stated. Pulse test: 300 µs pulse, 2% duty cycle. 2: Specification is obtained by characterization and is not 100% tested. DS20005697A-page 4  2017 Microchip Technology Inc. TC6320 P-CHANNEL ELECTRICAL CHARACTERISTICS Electrical Specifications: TA = TJ = 25°C unless otherwise specified. Parameter Sym. Min. Typ. Max. Unit Conditions V VGS = 0V, ID = –2 mA V VGS = VDS, ID = –1 mA DC PARAMETER (Note 1 unless otherwise specified) Drain-to-source Breakdown Voltage Gate Threshold Voltage BVDSS –200 — — VGS(th) –1 — –2.4 ∆VGS(th) — — 4.5 Gate-to-source Shunt Resistor RGS 10 — 50 kΩ IGS = 100 µA Gate-to-Source Zener Voltage VZGS 13.2 — 25 V IGS = –2 mA — — –10 µA VDS = Maximum rating,  VGS = 0V — — –1 mA VDS = 0.8 Maximum rating, VGS = 0V, TA = 125°C (Note 2) –1 — — –2 — — — — 10 — — 8 — — 1 %/°C mmho VDS = –25V, ID = –500 mA pF VGS = 0V, pF VDS = –25V, f = 1 MHz pF Change in VGS(th) with Temperature Zero-gate Voltage Drain Current On-state Drain Current Static Drain-to-source On-state  Resistance mV/°C VGS = VDS, ID = –1 mA (Note 2) IDSS ID(ON) RDS(ON) Change in RDS(ON) with Temperature ∆RDS(ON) A Ω VGS = –4.5V, VDS = –25V VGS = –10V, VDS = –25V VGS = –4.5V, ID = –150 mA VGS = –10V, ID = –1A VGS = –10V, ID = –200 mA (Note 2) AC PARAMETER (Note 2) Forward Transconductance GFS 400 — — Input Capacitance CISS — — 200 Common Source Output Capacitance COSS — — 55 Reverse Transfer Capacitance CRSS — — 30 Turn-on Delay Time td(ON) — — 10 tr — — 15 ns ns td(OFF) — — 20 ns tf — — 15 ns VSD — — –1.8 V Rise Time Turn-off Delay Time Fall Time VDD = –25V, ID = –1A, RGEN = 25Ω DIODE PARAMETER Diode Forward Voltage Drop VGS = 0V, ISD = –500 mA (Note 1) Reverse Recovery Time trr — 300 — ns VGS = 0V, ISD = –500 mA (Note 2) Note 1: All DC parameters are 100% tested at 25°C unless otherwise stated. Pulse test: 300 µs pulse, 2% duty cycle. 2: Specification is obtained by characterization and is not 100% tested. TEMPERATURE SPECIFICATIONS Electrical Characteristics: Unless otherwise specified, for all specifications TA =TJ = +25°C. Parameter Sym. Min. Typ. Max. Unit Conditions Operating Ambient Temperature TA –55°C — +150 °C Storage Temperature TS –55°C — +150 °C JA — 44 — °C/W Note 1 JA — 101 — °C/W Note 1 TEMPERATURE RANGE PACKAGE THERMAL RESISTANCE 8-lead DFN 8-lead SOIC Note 1: 1 oz., four-layer, 3” x 4” PCB  2017 Microchip Technology Inc. DS20005697A-page 5 TC6320 2.0 PIN DESCRIPTION Table 2-1 and Table 2-2 show the description of pins in TC6320 8-lead DFN and 8-lead SOIC, respectively. Refer to Package Types for the location of pins. TABLE 2-1: 8-LEAD DFN PIN FUNCTION TABLE Pin Number Pin Name 1 SN Source N-channel 2 GN Gate N-channel 3 GP Gate P-channel 4 SP Source P-channel 5 DP Drain P-channel 6 DP Drain P-channel 7 DN Drain N-channel 8 DN Drain N-channel TABLE 2-2: Pin Number Description 8-LEAD SOIC FUNCTION TABLE Pin Name Description 1 SN Source N-channel 2 GN Gate N-channel 3 SP Source P-channel 4 GP Gate P-channel 5 DP Drain P-channel 6 DP Drain P-channel 7 DN Drain N-channel 8 DN Drain N-channel DS20005697A-page 6  2017 Microchip Technology Inc. TC6320 3.0 FUNCTIONAL DESCRIPTION Figure 3-1 and Figure 3-2 illustrate the switching waveforms and test circuits for TC6320. 10V 90% VDD Input 0V t(OFF) t(ON) td(ON) td(OFF) tr RL Pulse Generator 10% OUTPUT RGEN tf D.U.T VDD 10% 10% Input Output 90% 0V FIGURE 3-1: 0V 90% N-Channel Switching Waveforms and Test Circuit. Pulse Generator 10% Input -10V 90% RGEN t(ON) td(ON) D.U.T t(OFF) tr tf td(OFF) Input OUTPUT 0V 90% 90% RL Output 10% VDD FIGURE 3-2: VDD 10% P-Channel Switching Waveforms and Test Circuit. PRODUCT SUMMARY RDS(ON) (Maximum) (Ω) BVDSS/BVDGS (V) N-Channel P-Channel N-Channel P-Channel 200 –200 7 8  2017 Microchip Technology Inc. DS20005697A-page 7 TC6320 4.0 PACKAGING INFORMATION 4.1 Package Marking Information 8-lead DFN XXXXXXX XXXXXXX e3 YYWW NNN Legend: XX...X Y YY WW NNN e3 * Note: DS20005697A-page 8 Example TC6320 K6 e3 1715 222 8-lead SOIC Example XXXXXXX e3 YYWW NNN TC6320TG e3 1727 555 Product Code or Customer-specific information Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week ‘01’) Alphanumeric traceability code Pb-free JEDEC® designator for Matte Tin (Sn) This package is Pb-free. The Pb-free JEDEC designator ( e3 ) can be found on the outer packaging for this package. In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for product code or customer-specific information. Package may or not include the corporate logo.  2017 Microchip Technology Inc. TC6320 Note: For the most current package drawings, see the Microchip Packaging Specification at www.microchip.com/packaging.  2017 Microchip Technology Inc. DS20005697A-page 9 TC6320 Note: For the most current package drawings, see the Microchip Packaging Specification at www.microchip.com/packaging. DS20005697A-page 10  2017 Microchip Technology Inc. TC6320 APPENDIX A: REVISION HISTORY Revision A (October 2017) • Converted Supertex Doc# DSFP-TC6320 to Microchip DS20005697A • Changed the package marking format • Changed the quantity of the 8-lead DFN K6 package from 3000/Reel to 3300/Reel • Changed the quantity of the 8-lead SOIC TG package from 2000/Reel to 3300/Reel • Made minor text changes throughout the document  2017 Microchip Technology Inc. DS20005697A-page 11 TC6320 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, contact your local Microchip representative or sales office. XX PART NO. - Package Options Device X - Environmental X Media Type Examples:  a) TC6320K6-G: N-Channel and P-Channel Enhancement-Mode MOSFET Pair,         8‐lead (4x4) VDFN, 3300/Reel  Device: TC6320 = N-Channel and P-Channel EnhancementMode MOSFET Pair Packages: K6 = 8-lead (4x4) VDFN TG = 8-lead SOIC Environmental: G = Lead (Pb)-free/RoHS-compliant Package Media Type: (blank) DS20005697A-page 12 = 3300/Reel for a K6 Package = 3300/Reel for a TG Package b) TC6320TG-G: N-Channel and P-Channel Enhancement-Mode MOSFET Pair, 8-lead SOIC, 3300/Reel  2017 Microchip Technology Inc. Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. • Microchip is willing to work with the customer who is concerned about the integrity of their code. • Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer’s risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights unless otherwise stated. Microchip received ISO/TS-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified. QUALITY MANAGEMENT SYSTEM CERTIFIED BY DNV Trademarks The Microchip name and logo, the Microchip logo, AnyRate, AVR, AVR logo, AVR Freaks, BeaconThings, BitCloud, CryptoMemory, CryptoRF, dsPIC, FlashFlex, flexPWR, Heldo, JukeBlox, KEELOQ, KEELOQ logo, Kleer, LANCheck, LINK MD, maXStylus, maXTouch, MediaLB, megaAVR, MOST, MOST logo, MPLAB, OptoLyzer, PIC, picoPower, PICSTART, PIC32 logo, Prochip Designer, QTouch, RightTouch, SAM-BA, SpyNIC, SST, SST Logo, SuperFlash, tinyAVR, UNI/O, and XMEGA are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. ClockWorks, The Embedded Control Solutions Company, EtherSynch, Hyper Speed Control, HyperLight Load, IntelliMOS, mTouch, Precision Edge, and Quiet-Wire are registered trademarks of Microchip Technology Incorporated in the U.S.A. Adjacent Key Suppression, AKS, Analog-for-the-Digital Age, Any Capacitor, AnyIn, AnyOut, BodyCom, chipKIT, chipKIT logo, CodeGuard, CryptoAuthentication, CryptoCompanion, CryptoController, dsPICDEM, dsPICDEM.net, Dynamic Average Matching, DAM, ECAN, EtherGREEN, In-Circuit Serial Programming, ICSP, Inter-Chip Connectivity, JitterBlocker, KleerNet, KleerNet logo, Mindi, MiWi, motorBench, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient Code Generation, PICDEM, PICDEM.net, PICkit, PICtail, PureSilicon, QMatrix, RightTouch logo, REAL ICE, Ripple Blocker, SAM-ICE, Serial Quad I/O, SMART-I.S., SQI, SuperSwitcher, SuperSwitcher II, Total Endurance, TSHARC, USBCheck, VariSense, ViewSpan, WiperLock, Wireless DNA, and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. Silicon Storage Technology is a registered trademark of Microchip Technology Inc. in other countries. GestIC is a registered trademark of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in other countries. All other trademarks mentioned herein are property of their respective companies. © 2017, Microchip Technology Incorporated, All Rights Reserved. ISBN: 978-1-5224-2207-5 == ISO/TS 16949 ==  2017 Microchip Technology Inc. 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