TN2124
N-Channel Enhancement-Mode Vertical DMOS FET
Features
General Description
•
•
•
•
•
•
•
The TN2124 low-threshold Enhancement-mode
(normally-off) transistor uses a vertical Diffusion
Metal-Oxide Semiconductor (DMOS) structure and a
well-proven silicon gate manufacturing process. This
combination produces a device with the power
handling capabilities of bipolar transistors and the high
input impedance and positive temperature coefficient
inherent in Metal-Oxide Semiconductor (MOS)
devices. Characteristic of all MOS structures, this
device is free from thermal runaway and thermally
induced secondary breakdown.
Free from Secondary Breakdown
Low Power Drive Requirement
Ease of Paralleling
Low CISS and Fast Switching Speeds
Excellent Thermal Stability
Integral Source-Drain Diode
High Input Impedance and High Gain
Applications
•
•
•
•
•
•
•
Logic-Level Interfaces (Ideal for TTL and CMOS)
Solid-State Relays
Battery-Operated Systems
Photovoltaic Drives
Analog Switches
General Purpose Line Drivers
Telecommunication Switches
Microchip’s vertical DMOS Field-Effect Transistors
(FETs) are ideally suited to a wide range of switching
and amplifying applications where very low threshold
voltage, high breakdown voltage, high input
impedance, low input capacitance and fast switching
speeds are desired.
Package Type
3-lead SOT-23
(Top view)
DRAIN
SOURCE
GATE
See Table 3-1 for pin information.
2018 Microchip Technology Inc.
DS20005698A-page 1
TN2124
1.0
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings†
Drain-to-Source Voltage ...................................................................................................................................... BVDSS
Drain-to-Gate Voltage .......................................................................................................................................... BVDGS
Gate-to-Source Voltage ......................................................................................................................................... ±20V
Operating Ambient Temperature, TA ................................................................................................... –55°C to +150°C
Storage Temperature, TS ..................................................................................................................... –55°C to +150°C
† Notice: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only, and functional operation of the device at those or any other conditions above those
indicated in the operational sections of this specification is not intended. Exposure to maximum rating conditions for
extended periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
Electrical Specifications: TA = 25°C unless otherwise specified. All DC parameters are 100% tested at 25°C unless
otherwise stated. Pulse test: 300 µs pulse, 2% duty cycle
Parameter
Sym.
Min. Typ. Max.
Drain-to-Source Breakdown Voltage
BVDSS
240
—
—
V
VGS = 0V, ID = 1 mA
Gate Threshold Voltage
VGS(th)
0.8
—
2
V
VGS = VDS, ID = 1 mA
∆VGS(th)
—
—
–5.5 mV/°C
VGS = VDS, ID = 1 mA
(Note 1)
IGSS
—
0.1
100
nA
VGS = ±20V, VDS = 0V
—
—
1
µA
VGS = 0V,
VDS = Maximum rating
—
—
100
µA
VDS = 0.8 Maximum rating,
VGS = 0V, TA = 125°C
(Note 1)
140
—
—
mA
VGS = 4.5V, VDS = 25V
—
—
30
Ω
VGS = 3V, ID = 25 mA
—
—
15
Ω
VGS = 4.5V, ID = 120 mA
—
0.7
1
%/°C
VGS = 4.5V, ID = 120 mA
(Note 1)
Change in VGS(th) with Temperature
Gate Body Leakage Current
Zero-Gate Voltage Drain Current
On-State Drain Current
Static Drain-to-Source On-State Resistance
Change in RDS(ON) with Temperature
Note 1:
Unit
IDSS
ID(ON)
RDS(ON)
∆RDS(ON)
Conditions
Specification is obtained by characterization and is not 100% tested.
DS20005698A-page 2
2018 Microchip Technology Inc.
TN2124
AC ELECTRICAL CHARACTERISTICS
Electrical Specifications: TA = 25°C unless otherwise specified. Specification is obtained by characterization and is
not 100% tested.
Parameter
Sym.
Min.
Typ.
Max.
Forward Transconductance
GFS
100
170
—
Input Capacitance
CISS
—
38
50
pF
Common Source Output Capacitance
COSS
—
9
15
pF
Reverse Transfer Capacitance
CRSS
—
3
5
pF
Turn-On Delay Time
td(ON)
—
4
7
ns
tr
—
2
5
ns
td(OFF)
—
7
10
ns
tf
—
9
12
ns
VSD
—
—
1.8
V
VGS = 0V, ISD = 120 mA (Note 1)
trr
—
400
—
ns
VGS = 0V, ISD = 120 mA
Rise Time
Turn-Off Delay Time
Fall Time
Unit
Conditions
mmho VDS = 25V, ID = 120 mA
VGS = 0V, VDS = 25V,
f = 1 MHz
VDD = 25V, ID = 140 mA,
RGEN = 25Ω
DIODE PARAMETER
Diode Forward Voltage Drop
Reverse Recovery Time
Note 1:
Unless otherwise stated, all DC parameters are 100% tested at +25°C. Pulse test: 300 µs pulse, 2% duty
cycle
TEMPERATURE SPECIFICATIONS
Electrical Characteristics: Unless otherwise specified, for all specifications TA = TJ = +25°C.
Parameter
Sym. Min.
Typ.
Max.
Unit
Conditions
TEMPERATURE RANGE
Operating Ambient Temperature
TA
–55
—
+150
°C
Storage Temperature
TS
–55
—
+150
°C
JA
—
203
—
°C/W
PACKAGE THERMAL RESISTANCE
3-lead SOT-23
THERMAL CHARACTERISTICS
Package
ID (Note 1)
(Continuous)
(mA)
ID
(Pulsed)
(mA)
Power Dissipation
at TA = 25°C
(W)
IDR (Note 1)
(mA)
IDRM
(mA)
134
250
0.36
134
250
3-lead SOT-23
Note 1:
ID (continuous) is limited by maximum TJ.
2018 Microchip Technology Inc.
DS20005698A-page 3
TN2124
2.0
TYPICAL PERFORMANCE CURVES
The graphs and tables provided following this note are a statistical summary based on a limited number of
samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g. outside specified power supply range) and therefore outside the warranted range.
2.0
1.0
1.6
0.8
1.2
VGS = 10V
8V
6V
4V
0.8
ID (amperes)
ID (amperes)
Note:
VGS = 10V
8V
6V
4V
0.6
3V
0.4
3V
0.4
0.2
2V
2V
0
0
10
20
30
40
0
50
0
2.0
4.0
FIGURE 2-1:
Output Characteristics.
FIGURE 2-4:
1.0
0.8
1.6
0.6
1.2
PD (watts)
GFS (siemens)
8.0
10
Saturation Characteristics.
2.0
VDS = 25V
-55OC
0.4
0.8
0.4
0.2
25OC
TA = 125OC
0
6.0
VDS (volts)
VDS (volts)
0
0.2
0.4
0.6
SOT-23
0.8
0
1.0
0
25
50
ID (amperes)
Transconductance vs. Drain
FIGURE 2-2:
Current.
75
100
125
150
TA (OC)
FIGURE 2-5:
Temperature.
10
Power Dissipation vs.
1.0
Thermal Resistance (normalized)
TA = 25OC
ID (amperes)
1.0
SOT-23 (pulsed)
0.1
SOT-23 (DC)
0.01
0
10
100
1000
VDS (volts)
FIGURE 2-3:
Operating Area.
DS20005698A-page 4
Maximum Rated Safe
0.8
0.6
SOT-23
TA = 25OC
PD = 0.36W
0.4
0.2
0
0.001
0.01
0.1
1.0
10
tP (seconds)
FIGURE 2-6:
Characteristics.
Thermal Response
2018 Microchip Technology Inc.
TN2124
50
1.1
VGS = 3.0V
RDS(ON) (ohms)
BVDSS (normalized)
40
1.0
30
20
VGS = 4.5V
10
0.9
-50
0
50
100
0
150
0
0.2
Tj ( C)
FIGURE 2-7:
Temperature.
0.4
0.6
0.8
1.0
ID (amperes)
O
FIGURE 2-10:
Current.
BVDSS Variation with
On-resistance vs. Drain
2.0
1.0
1.4
RDS(ON) @ 4.5V, 120mA
125OC
1.6
0.8
VGS(th) (normalized)
TA = -55 C
O
ID (amperes)
25 C
0.6
0.4
1.2
1.2
1.0
0.8
0.8
RDS(ON) (normalized)
O
VGS(th) @ 1.0mA
0.4
0.2
0.6
VDS = 25V
0
0
2.0
4.0
6.0
8.0
10
-50
0
VGS (volts)
FIGURE 2-8:
50
0
150
100
Tj (OC)
Transfer Characteristics.
FIGURE 2-11:
Temperature.
V(th) and RDS Variation with
10
100
f = 1.0MHz
8.0
VGS (volts)
C (picofarads)
75
50
6.0
VDS = 10V
4.0
100pF
CISS
VDS = 40V
25
2.0
CRSS
COSS
32 pF
0
0
10
20
30
40
0
0
FIGURE 2-9:
Capacitance vs.
Drain-to-Source Voltage.
2018 Microchip Technology Inc.
0.2
0.4
0.6
0.8
1.0
QG (nanocoulombs)
VDS (volts)
FIGURE 2-12:
Characteristics.
Gate Drive Dynamic
DS20005698A-page 5
TN2124
3.0
PIN DESCRIPTION
The details on the pins of TN2124 are listed on
Table 3-1. Refer to Package Type for the location of
pins.
TABLE 3-1:
PIN FUNCTION TABLE
Pin Number
Pin Name
1
Gate
2
Source
3
Drain
DS20005698A-page 6
Description
Gate
Source
Drain
2018 Microchip Technology Inc.
TN2124
4.0
FUNCTIONAL DESCRIPTION
Figure 4-1 illustrates the switching waveforms and test
circuit for TN2124.
10V
VDD
90%
Pulse
Generator
INPUT
10%
0V
t(ON)
t(OFF)
tr
td(ON)
VDD
td(OFF)
0V
RGEN
10%
90%
FIGURE 4-1:
TABLE 4-1:
OUTPUT
tf
10%
OUTPUT
RL
INPUT
D.U.T.
90%
Switching Waveforms and Test Circuit.
PRODUCT SUMMARY
BVDSS/BVDGS
(V)
RDS(ON)
(Maximum)
(Ω)
VGS(th)
(Maximum)
(V)
240
15
2
2018 Microchip Technology Inc.
DS20005698A-page 7
TN2124
5.0
PACKAGING INFORMATION
5.1
Package Marking Information
3-lead SOT-23
XXXNNN
Legend: XX...X
Y
YY
WW
NNN
e3
*
Note:
DS20005698A-page 8
Example
N1C256
Product Code or Customer-specific information
Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
Pb-free JEDEC® designator for Matte Tin (Sn)
This package is Pb-free. The Pb-free JEDEC designator ( e3 )
can be found on the outer packaging for this package.
In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for product code or customer-specific information. Package may or
not include the corporate logo.
2018 Microchip Technology Inc.
TN2124
3-Lead TO-236AB (SOT-23) Package Outline (K1/T)
2.90x1.30mm body, 1.12mm height (max), 1.90mm pitch
D
3
E1 E
Gauge
Plane
0.25
1
Seating
Plane
L
2
e
L1
b
e1
View B
Top View
View B
A
A
A2
Seating
Plane
A1
Side View
View A - A
A
Note: For the most current package drawings, see the Microchip Packaging Specification at www.microchip.com/packaging.
Symbol
Dimension
(mm)
A
A1
A2
b
D
E
E1
MIN
0.89
0.01
0.88
0.30
2.80
2.10
1.20
NOM
-
-
0.95
-
2.90
-
1.30
MAX
1.12
0.10
1.02
0.50
3.04
2.64
1.40
e
0.95
BSC
e1
1.90
BSC
L
0.20†
0.50
0.60
L1
0.54
REF
ș
0O
8O
JEDEC Registration TO-236, Variation AB, Issue H, Jan. 1999.
† This dimension differs from the JEDEC drawing.
Drawings not to scale.
2018 Microchip Technology Inc.
DS20005698A-page 9
TN2124
NOTES:
DS20005698A-page 10
2018 Microchip Technology Inc.
TN2124
APPENDIX A:
REVISION HISTORY
Revision A (April 2018)
• Converted Supertex Doc# DSFP-TN2124 to
Microchip DS20005698A
• Added some sections to comply with the standard
Microchip format
• Changed the package marking format
• Made minor text changes throughout
the document
2018 Microchip Technology Inc.
DS20005698A-page 11
TN2124
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, contact your local Microchip representative or sales office.
XX
PART NO.
-
Package
Options
Device
X
-
Environmental
X
Media Type
Device:
TN2124
=
N-Channel Enhancement-Mode Vertical
DMOS FET
Package:
K1
=
3-lead SOT-23
Environmental:
G
=
Lead (Pb)-free/RoHS-compliant Package
Media Type:
(blank)
=
3000/Reel for a K1 Package
DS20005698A-page 12
Example:
a) TN2124K1-G:
N-Channel Enhancement-Mode
Vertical DMOS FET, 3-lead SOT-23,
3000/Reel
2018 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
•
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
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© 2018, Microchip Technology Incorporated, All Rights Reserved.
ISBN: 978-1-5224-2937-1
== ISO/TS 16949 ==
2018 Microchip Technology Inc.
DS20005698A-page 13
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DS20005698A-page 14
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2018 Microchip Technology Inc.
10/25/17
