TN2501
N-Channel Enhancement-Mode Vertical DMOS FET
Features
General Description
•
•
•
•
•
•
•
The TN2501 low-threshold Enhancement-mode
(normally-off) transistor uses a vertical Diffusion Metal
Oxide Semiconductor (DMOS) structure and a
well-proven silicon-gate manufacturing process. This
combination produces a device with the power
handling capabilities of bipolar transistors and the high
input impedance and positive temperature coefficient
inherent in Metal-Oxide Semiconductor (MOS)
devices. Characteristic of all MOS structures, this
device is free from thermal runaway and thermally
induced secondary breakdown.
Low Threshold
High Input Impedance
110 pF Maximum Low-Input Capacitance
Fast Switching Speeds
Low On-Resistance
Free from Secondary Breakdown
Low Input and Output Leakage
Applications
•
•
•
•
•
•
•
Logic-Level Interfaces (Ideal for TTL and CMOS)
Solid-State Relays
Battery-Operated Systems
Photovoltaic Drives
Analog Switches
General Purpose Line Drivers
Telecommunication Switches
Microchip’s vertical DMOS Field-Effect Transistors
(FETs) are ideally suited to a wide range of switching
and amplifying applications where very low threshold
voltage, high breakdown voltage, high input
impedance, low input capacitance and fast switching
speeds are desired.
Package Type
3-lead SOT-89
(Top view)
DRAIN
SOURCE
DRAIN
GATE
See Table 3-1 for pin information.
2018 Microchip Technology Inc.
DS20005948A-page 1
TN2501
1.0
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings†
Drain-to-Source Voltage ...................................................................................................................................... BVDSS
Drain-to-Gate Voltage ......................................................................................................................................... BVDGS
Gate-to-Source Voltage ......................................................................................................................................... ±20V
Operating Ambient Temperature, TA ................................................................................................... –55°C to +150°C
Storage Temperature, TS ..................................................................................................................... –55°C to +150°C
† Notice: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only, and functional operation of the device at those or any other conditions above those
indicated in the operational sections of this specification is not intended. Exposure to maximum rating conditions for
extended periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
Electrical Specifications: TA = 25°C unless otherwise specified. All DC parameters are 100% tested at 25°C unless
otherwise stated. (Pulse test: 300 µs pulse, 2% duty cycle)
Parameter
Sym.
Min. Typ. Max.
Unit
Conditions
Drain-to-Source Breakdown Voltage
BVDSS
18
—
—
V
VGS = 0V, ID = 1 mA
Gate Threshold Voltage
VGS(th)
0.3
—
1
V
VGS = VDS, ID = 1 mA
∆VGS(th)
—
—
–4
mV/°C
VGS = VDS, ID = 1 mA
(Note 1)
IGSS
—
—
100
nA
VGS = ±15V, VDS = 0V
—
—
10
µA
VGS = 0V,
VDS = Maximum rating
—
—
1
mA
VDS = 0.8 Maximum rating,
VGS = 0V, TA = 125°C
(Note 1)
ID(ON)
250
600
—
mA
VGS = VDS = 3V
—
—
25
Ω
VGS = 1.2V, ID = 3 mA
RDS(ON)
—
—
3.5
Ω
VGS = 2V, ID = 50 mA
—
—
2.5
Ω
VGS = 3V, ID = 200 mA
—
—
0.75
%/°C
VGS = 3V, ID = 200 mA
(Note 1)
Change in VGS(th) with Temperature
Gate Body Leakage Current
Zero-Gate Voltage Drain Current
On-State Drain Current
Static Drain-to-Source On-State Resistance
Change in RDS(ON) with Temperature
Note 1:
IDSS
∆RDS(ON)
Specification is obtained by characterization and is not 100% tested.
DS20005948A-page 2
2018 Microchip Technology Inc.
TN2501
AC ELECTRICAL CHARACTERISTICS
Electrical Specifications: TA = 25°C unless otherwise specified. All AC parameters are sample tested.
Parameter
Sym.
Min.
Typ.
Max.
Forward Transconductance
GFS
150
300
—
Input Capacitance
CISS
—
—
110
pF
Common Source Output Capacitance
COSS
—
—
60
pF
Reverse Transfer Capacitance
CRSS
—
—
35
pF
Turn-On Delay Time
td(ON)
—
—
5
ns
tr
—
—
15
ns
td(OFF)
—
—
15
ns
tf
—
—
8
ns
VSD
—
1.1
1.8
V
VGS = 0V, ISD = 200 mA (Note 1)
trr
—
100
—
ns
VGS = 0V, ISD = 200 mA
Rise Time
Turn-Off Delay Time
Fall Time
Unit
Conditions
mmho VDS = 3V, ID = 200 mA
VGS = 0V,
VDS = 15V,
f = 1 MHz
VDD = 15V,
ID = 250 mA,
RGEN = 25Ω
DIODE PARAMETER
Diode Forward Voltage Drop
Reverse Recovery Time
Note 1:
All DC parameters are 100% tested at 25°C unless otherwise stated.
(Pulse test: 300 µs pulse, 2% duty cycle)
TEMPERATURE SPECIFICATIONS
Parameter
Sym.
Min.
Typ.
Max.
Unit
Operating Ambient Temperature
TA
–55
—
+150
°C
Storage Temperature
TS
–55
—
+150
°C
JA
—
133
—
°C/W
Conditions
TEMPERATURE RANGE
PACKAGE THERMAL RESISTANCE
3-lead SOT-89
THERMAL CHARACTERISTICS
Package
3-lead SOT-89
Note 1:
2:
ID (Note 1)
(Continuous)
(mA)
ID
(Pulsed)
(mA)
400
560
Power Dissipation
IDR (Note 1)
at TA = 25°C
(Note 2)
(mA)
(W)
1.6
400
IDRM
(mA)
560
ID (continuous) is limited by maximum rated TJ.
TA = 25°C. Mounted on an FR4 Board, 25 mm x 25 mm x 1.57 mm.
2018 Microchip Technology Inc.
DS20005948A-page 3
TN2501
2.0
TYPICAL PERFORMANCE CURVES
Note:
The graphs and tables provided following this note are a statistical summary based on a limited number of
samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g. outside specified power supply range) and therefore outside the warranted range.
1.0
5.0
VGS = 10V
4.0
0.8
ID (amperes)
ID (amperes)
8V
3.0
6V
2.0
1.0
VGS = 4.0V
0.6
0.4
3.0V
0.2
4V
2.0V
3V
1.0V
0
0.0
0
10
0
20
2
4
VDS (volts)
FIGURE 2-1:
6
8
10
VDS (volts)
Output Characteristics.
FIGURE 2-4:
1.0
Saturation Characteristics.
2.0
V DS =15V
SOT-89
0.6
T A = -55 O C
PD (watts)
GFS (siemens)
0.8
T A =25 O C
0.4
1.0
T A =125 O C
0.2
0.0
0.0
0.2
0.4
0.6
0.8
0
0
1.0
25
50
ID (amperes)
Transconductance vs. Drain
FIGURE 2-2:
Current.
125
150
1.0
Thermal Resistance (normalized)
T A = 25 O C
1.0
SOT-89 (pulsed)
ID (amperes)
100
FIGURE 2-5:
Power Dissipation vs.
Ambient Temperature.
10
0.1
75
TA (OC)
SOT-89 (DC)
0.01
0.001
0.1
SOT-89
PD = 1.6W
TC = 25OC
0.8
0.6
0.4
0.2
0
1.0
10
100
0.001
VDS (volts)
FIGURE 2-3:
Operating Area.
DS20005948A-page 4
Maximum Rated Safe
0.01
0.1
1.0
10
tp (Seconds)
FIGURE 2-6:
Characteristics.
Thermal Response
2018 Microchip Technology Inc.
TN2501
10
1.1
VGS = 2V
RDS(ON) (ohms)
BVDSS (normalized)
8
1.0
6
VGS = 3V
4
2
0
50
100
0
150
0
0.2
O
FIGURE 2-7:
Temperature.
0.4
0.6
0.8
FIGURE 2-10:
Current.
BVDSS Variation with
On-Resistance vs. Drain
1.0
1.6
VDS = 15V
25 OC
1.4
RDS(ON) @ 3V, 0.2A
1.4
TA = -55OC
VGS(th) (normalized)
ID (amperes)
0.8
0.6
1.0
ID (amperes)
TJ ( C)
125OC
0.4
1.2
V(th) @ 1mA
1.2
1.0
1.0
0.8
RDS(ON) (normalized)
0.9
-50
0.8
0.2
0.6
0
0
2
4
6
8
-50
10
0
0.6
150
100
TJ (OC)
VGS (volts)
FIGURE 2-8:
50
Transfer Characteristics.
FIGURE 2-11:
Temperature.
100
V(th) and RDS Variation with
10
f = 1MHz
8
VDS = 10V
130 pF
VGS (volts)
C (picofarads)
75
CISS
50
COSS
25
6
VDS = 15V
4
2
CRSS
60pF
0
0
5
10
15
20
0
0
VDS (volts)
FIGURE 2-9:
Capacitance vs.
Drain-to-Source Voltage.
2018 Microchip Technology Inc.
0.4
0.8
1.2
1.6
2.0
QG (nanocoloumbs)
FIGURE 2-12:
Characteristics.
Gate Drive Dynamic
DS20005948A-page 5
TN2501
3.0
PIN DESCRIPTION
The details on the pins of TN2501 are listed on
Table 3-1. Refer to Package Type for the location of
pins.
TABLE 3-1:
PIN FUNCTION TABLE
Pin Number
Pin Name
Description
1
Gate
Gate
2
Drain
Drain
3
Source
Source
DS20005948A-page 6
2018 Microchip Technology Inc.
TN2501
4.0
FUNCTIONAL DESCRIPTION
Figure 4-1 illustrates the switching waveforms and test
circuit for TN2501.
10V
VDD
90%
Pulse
Generator
INPUT
0V
10%
t(ON)
td(ON)
VDD
td(OFF)
tr
0V
tf
FIGURE 4-1:
INPUT
10%
90%
OUTPUT
RGEN
10%
OUTPUT
TABLE 4-1:
t(OFF)
RL
D.U.T.
90%
Switching Waveforms and Test Circuit.
PRODUCT SUMMARY
BVDSS/BVDGS
(V)
RDS(ON)
(Maximum)
(Ω)
ID(ON)
(Minimum)
(mA)
VGS(TH)
(Maximum)
(V)
18
2.5
250
1
2018 Microchip Technology Inc.
DS20005948A-page 7
TN2501
5.0
PACKAGING INFORMATION
5.1
Package Marking Information
3-lead SOT-89
XXXXYWW
NNN
Legend: XX...X
Y
YY
WW
NNN
e3
*
Note:
DS20005948A-page 8
Example
TN5U855
398
Product Code or Customer-specific information
Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
Pb-free JEDEC® designator for Matte Tin (Sn)
This package is Pb-free. The Pb-free JEDEC designator ( e3 )
can be found on the outer packaging for this package.
In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for product code or customer-specific information. Package may or
not include the corporate logo.
2018 Microchip Technology Inc.
TN2501
3-Lead TO-243AA (SOT-89) Package Outline (N8)
D
D1
C
E H
L
1
2
E1
3
b
b1
e
A
e1
Side View
Top View
Note: For the most current package drawings, see the Microchip Packaging Specification at www.microchip.com/packaging.
Symbol
Dimensions
(mm)
A
b
b1
C
D
D1
E
E1
MIN
1.40
0.44
0.36
0.35
4.40
1.62
2.29
2.00†
NOM
-
-
-
-
-
-
-
-
MAX
1.60
0.56
0.48
0.44
4.60
1.83
2.60
2.29
e
1.50
BSC
e1
3.00
BSC
H
L
3.94
0.73†
-
-
4.25
1.20
JEDEC Registration TO-243, Variation AA, Issue C, July 1986.
† This dimension differs from the JEDEC drawing
Drawings not to scale.
2018 Microchip Technology Inc.
DS20005948A-page 9
TN2501
NOTES:
DS20005948A-page 10
2018 Microchip Technology Inc.
TN2501
APPENDIX A:
REVISION HISTORY
Revision A (May 2018)
• Converted Supertex Doc# DSFP-TN2501 to
Microchip DS20005948A
• Changed the package marking format
• Added some sections to comply with Microchip
formatting standards
• Made minor text changes throughout the
document
2018 Microchip Technology Inc.
DS20005948A-page 11
TN2501
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, contact your local Microchip representative or sales office.
XX
PART NO.
-
Package
Options
Device
X
-
Environmental
X
Media Type
Device:
TN2501
=
N-Channel Enhancement-Mode Vertical
DMOS FET
Package:
N8
=
3-lead SOT-89
Environmental:
G
=
Lead (Pb)-free/RoHS-compliant Package
Media Type:
(blank)
=
2000/Reel for an N8 Package
DS20005948A-page 12
Example:
a) TN2501N8-G:
N-Channel EnhancementMode, Vertical DMOS FET,
3-lead SOT-89, 2000/Reel
2018 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
•
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
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OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
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headquarters, design and wafer fabrication facilities in Chandler and
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are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
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CERTIFIED BY DNV
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© 2018, Microchip Technology Incorporated, All Rights Reserved.
ISBN: 978-1-5224-3154-1
== ISO/TS 16949 ==
2018 Microchip Technology Inc.
DS20005948A-page 13
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10/25/17
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