TP0610T
P-Channel Enhancement-Mode Vertical DMOS FET
Features
General Description
•
•
•
•
•
•
•
The TP0610T is a low-threshold, Enhancement-mode
(normally-off) transistor that utilizes a vertical DMOS
structure and a well-proven silicon gate manufacturing
process. This combination produces a device with the
power handling capabilities of bipolar transistors and
the high input impedance and positive temperature
coefficient inherent in MOS devices. Characteristic of
all MOS structures, this device is free from thermal
runaway and thermally induced secondary breakdown.
High Input Impedance and High Gain
Low Power Drive Requirement
Ease of Paralleling
Low CISS and Fast Switching Speeds
Excellent Thermal Stability
Integral Source-Drain Diode
Free from Secondary Breakdown
Applications
•
•
•
•
•
•
•
Microchip’s vertical DMOS FETs are ideally suited to a
wide range of switching and amplifying applications
where very low threshold voltage, high breakdown
voltage, high input impedance, low input capacitance,
and fast switching speeds are desired.
Logic-Level Interfaces (Ideal for TTL and CMOS)
Solid-State Relays
Battery-Operated Systems
Photo-Voltaic Drives
Analog Switches
Power Management
Telecommunication Switches
Package Type
3-lead SOT-23 (TO-236AB)
(Top view)
DRAIN
SOURCE
GATE
See Table 3-1 for pin information.
2019-2020 Microchip Technology Inc.
DS20005701B-page 1
TP0610T
1.0
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings†
Drain-to-Source Voltage ....................................................................................................................................... BVDSS
Drain-to-Gate Voltage .......................................................................................................................................... BVDGS
Gate-to-Source Voltage.......................................................................................................................................... ±20V
Operating Ambient Temperature, TA .................................................................................................... –55°C to +150°C
Storage Temperature, TS...................................................................................................................... –55°C to +150°C
† Notice: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only, and functional operation of the device at those or any other conditions above those
indicated in the operational sections of this specification is not intended. Exposure to maximum rating conditions for
extended periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
Electrical Specifications: TA = 25°C unless otherwise specified. All DC parameters are 100% tested at 25°C unless
otherwise stated. Pulse test: 300 µs pulse, 2% duty cycle
Parameter
Drain-to-Source Breakdown
Voltage
Gate Threshold Voltage
Change in VGS(th) with Temperature
Gate Body Leakage
Zero-Gate Voltage Drain Current
On-State Drain Current
Static Drain-to-Source On-State
Resistance
Change in RDS(ON) with
Temperature
Note 1:
Sym.
Min.
Typ.
Max.
Unit
Conditions
BVDSS
–60
—
—
V
VGS = 0V, ID = –10 μA
V
VGS = VDS, ID = –1 mA
VGS(th)
–1
—
–2.4
ΔVGS(th)
—
—
6.5
IGSS
—
—
±10
nA
VGS = ± 20V, VDS = 0V
—
–1
μA
VGS = 0V,
VDS = Maximum rating
—
–200
μA
VDS = 0.8 Maximum rating,
VGS = 0V, TA = 125°C (Note 1)
—
—
mA
VGS = –4.5V, VDS = –10V
—
25
Ω
VGS = –4.5V, ID = –25 mA
—
10
Ω
VGS = –10V, ID = –200 mA
%/°C
VGS = –10V, ID = –200 mA
(Note 1)
IDSS
—
ID(ON)
–50
RDS(ON)
ΔRDS(ON)
—
—
—
1
mV/°C VGS = VDS, ID = –1 mA (Note 1)
Specification is obtained by characterization and is not 100% tested.
DS20005701B-page 2
2019-2020 Microchip Technology Inc.
TP0610T
AC ELECTRICAL CHARACTERISTICS
Electrical Specifications: TA = 25°C unless otherwise specified. Specification is obtained by characterization and is
not 100% tested.
Parameter
Sym.
Min.
Typ.
Max.
Unit
Conditions
Forward Transconductance
GFS
60
—
—
Input Capacitance
CISS
—
—
60
pF
Common Source Output
Capacitance
COSS
—
—
30
pF
Reverse Transfer Capacitance
CRSS
—
—
10
pF
Turn-On Delay Time
td(ON)
—
—
10
ns
tr
—
—
15
ns
td(OFF)
—
—
15
ns
tf
—
—
20
ns
VSD
—
—
–2
V
VGS = 0V, ISD = –120 mA
(Note 1)
trr
—
400
—
ns
VGS = 0V, ISD = –400 mA
Rise Time
Turn-Off Delay Time
Fall Time
DIODE PARAMETER
Diode Forward Voltage Drop
Reverse Recovery Time
Note 1:
mmho VDS = –10V, ID = –100 mA
VGS = 0V, VDS = –25V,
f = 1 MHz
VDD = –25V, ID = –180 mA,
RGEN = 25Ω
Unless otherwise stated, all DC parameters are 100% tested at 25°C.
Pulse test: 300 µs pulse, 2% duty cycle
TEMPERATURE SPECIFICATIONS
Parameter
Sym.
Min.
Typ.
Max.
Unit
Operating Ambient Temperature
TA
–55
—
+150
°C
Storage Temperature
TS
–55
—
+150
°C
JA
—
203
—
°C/W
Conditions
TEMPERATURE RANGE
PACKAGE THERMAL RESISTANCE
3-lead SOT-23
THERMAL CHARACTERISTICS
Package
3-lead SOT-23
Note 1:
ID (Note 1)
(Continuous)
(mA)
ID
(Pulsed)
(mA)
Power Dissipation at
TA = 25°C
(W)
IDR (Note 1)
(mA)
IDRM
(mA)
–120
–400
0.36
–120
–400
ID (continuous) is limited by maximum TJ.
2019-2020 Microchip Technology Inc.
DS20005701B-page 3
TP0610T
2.0
Note:
TYPICAL PERFORMANCE CURVES
The graphs and tables provided following this note are a statistical summary based on a limited number of
samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g. outside specified power supply range) and therefore outside the warranted range.
FIGURE 2-1:
Output Characteristics.
FIGURE 2-4:
Saturation Characteristics.
FIGURE 2-2:
Current.
Transconductance vs. Drain
FIGURE 2-5:
Temperature.
Power Dissipation vs.
FIGURE 2-3:
Operating Area.
Maximum Rated Safe
FIGURE 2-6:
Characteristics.
Thermal Response
DS20005701B-page 4
2019-2020 Microchip Technology Inc.
TP0610T
FIGURE 2-7:
Temperature.
BVDSS Variation with
FIGURE 2-10:
Current.
On-Resistance vs. Drain
FIGURE 2-8:
Transfer Characteristics.
FIGURE 2-11:
Temperature.
V(th) and RDS Variation with
FIGURE 2-12:
Characteristics.
Gate Drive Dynamic
FIGURE 2-9:
Capacitance vs.
Drain-to-source Voltage.
2019-2020 Microchip Technology Inc.
DS20005701B-page 5
TP0610T
3.0
PIN DESCRIPTION
Table 3-1 shows the description of pins in TP0610T
SOT-23 (TO–236AB). Refer to Package Type for the
location of pins.
TABLE 3-1:
PIN FUNCTION TABLE
Pin Number
Pin Name
1
Gate
2
Source
3
Drain
DS20005701B-page 6
Description
Gate
Source
Drain
2019-2020 Microchip Technology Inc.
TP0610T
4.0
FUNCTIONAL DESCRIPTION
Figure 4-1 illustrates the switching waveforms and test
circuit for TP0610T.
0V
Pulse
Generator
10%
INPUT
RGEN
90%
t(OFF)
-10V
t(ON)
D.U.T.
td(ON)
tr
td(OFF)
tf
INPUT
OUTPUT
0V
90%
OUTPUT
10%
RL
90%
10%
VDD
FIGURE 4-1:
TABLE 4-1:
VDD
Switching Waveforms and Test Circuit.
PRODUCT SUMMARY
BVDSS/BVDGS
(V)
RDS(ON)
(Maximum)
(Ω)
VGS(th)
(Maximum)
(mA)
–60
10
–50
2019-2020 Microchip Technology Inc.
DS20005701B-page 7
TP0610T
5.0
PACKAGING INFORMATION
5.1
Package Marking Information
3-lead SOT-23
XXXNNN
Legend: XX...X
Y
YY
WW
NNN
e3
*
Note:
DS20005701B-page 8
Example
T50636
Product Code or Customer-specific information
Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
Pb-free JEDEC® designator for Matte Tin (Sn)
This package is Pb-free. The Pb-free JEDEC designator ( e3 )
can be found on the outer packaging for this package.
In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for product code or customer-specific information. Package may or
not include the corporate logo.
2019-2020 Microchip Technology Inc.
TP0610T
3-Lead TO-236AB (SOT-23) Package Outline (K1/T)
2.90x1.30mm body, 1.12mm height (max), 1.90mm pitch
D
3
E1 E
Gauge
Plane
0.25
1
Seating
Plane
L
2
e
L1
b
e1
View B
Top View
View B
A
A
A2
Seating
Plane
A1
Side View
View A - A
A
Note: For the most current package drawings, see the Microchip Packaging Specification at www.microchip.com/packaging.
Symbol
Dimension
(mm)
A
A1
A2
b
D
E
E1
MIN
0.89
0.01
0.88
0.30
2.80
2.10
1.20
NOM
-
-
0.95
-
2.90
-
1.30
MAX
1.12
0.10
1.02
0.50
3.04
2.64
1.40
e
0.95
BSC
e1
1.90
BSC
L
0.20†
0.50
0.60
L1
0.54
REF
ș
0O
8O
JEDEC Registration TO-236, Variation AB, Issue H, Jan. 1999.
† This dimension differs from the JEDEC drawing.
Drawings not to scale.
2019-2020 Microchip Technology Inc.
DS20005701B-page 9
TP0610T
NOTES:
DS20005701B-page 10
2019-2020 Microchip Technology Inc.
TP0610T
APPENDIX A:
REVISION HISTORY
Revision A (July 2019)
• Converted Supertex Doc# DSFP-TP0610T to
Microchip DS20005701B
• Corrected the order of the diagrams in the Typical
Performance Curves section
• Made minor text changes throughout the document
Revision B (February 2020)
• Changed all Typical Performance Curves in Revision A to the curves shown in this version
2019-2020 Microchip Technology Inc.
DS20005701B-page 11
TP0610T
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, contact your local Microchip representative or sales office.
XX
PART NO.
-
Package
Options
Device
X
-
Environmental
X
Media Type
Device:
TP0610T
=
P-Channel Enhancement-Mode Vertical
DMOS FET
Package:
(blank)
=
3-lead SOT-23
Environmental:
G
=
Lead (Pb)-free/RoHS-compliant Package
Media Type:
(blank)
=
3000/Reel for an SOT-23 Package
DS20005701B-page 12
Example:
a) TP0610T-G:
P-Channel Enhancement-Mode
Vertical DMOS FET, 3-lead SOT-23,
3000/Reel
2019-2020 Microchip Technology Inc.
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intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
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Microchip is willing to work with the customer who is concerned about the integrity of their code.
•
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mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
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ISBN:978-1-5224-5608-7
DS20005701B-page 13
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05/14/19