TP2502
P-Channel Enhancement-Mode Vertical DMOS FET
Features
General Description
•
•
•
•
•
•
•
The TP2502 low-threshold Enhancement-mode
(normally-off) transistor uses a vertical DMOS structure
and a well-proven silicon-gate manufacturing process.
This combination produces a device with the power
handling capabilities of bipolar transistors and the high
input impedance and positive temperature coefficient
inherent in MOS devices. Characteristic of all MOS
structures, this device is free from thermal runaway and
thermally induced secondary breakdown.
–2.4V Maximum Low Threshold
High Input Impedance
125 pF Maximum Low Input Capacitance
Fast Switching Speeds
Low On-Resistance
Free from Secondary Breakdown
Low Input and Output Leakage
Applications
•
•
•
•
•
•
•
Logic-Level Interfaces (Ideal for TTL and CMOS)
Solid-State Relays
Battery-Operated Systems
Photovoltaic Drives
Analog Switches
General Purpose Line Drivers
Telecommunication Switches
Microchip’s vertical DMOS FETs are ideally suited to a
wide range of switching and amplifying applications
where very low threshold voltage, high breakdown
voltage, high input impedance, low input capacitance
and fast switching speeds are desired.
Package Type
3-lead SOT-89
(Top view)
DRAIN
SOURCE
DRAIN
GATE
See Table 3-1 for pin information.
2019 Microchip Technology Inc.
DS20005962A-page 1
TP2502
1.0
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings†
Drain-to-Source Voltage ...................................................................................................................................... BVDSS
Drain-to-Gate Voltage ......................................................................................................................................... BVDGS
Gate-to-Source Voltage ......................................................................................................................................... ±20V
Operating Junction Temperature, TJ ................................................................................................... –55°C to +150°C
Storage Temperature, TS ..................................................................................................................... –55°C to +150°C
† Notice: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only, and functional operation of the device at those or any other conditions above those
indicated in the operational sections of this specification is not intended. Exposure to maximum rating conditions for
extended periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
Electrical Specifications: TA = 25°C unless otherwise specified. All DC parameters are 100% tested at 25°C unless
otherwise stated. Pulse test: 300 µs pulse, 2% duty cycle
Parameter
Sym.
Min.
Drain-to-Source Breakdown Voltage
BVDSS
–20
—
—
V
VGS = 0V, ID = –2 mA
Gate Threshold Voltage
VGS(th)
–1
—
–2.4
V
VGS = VDS, ID = –1 mA
∆VGS(th)
—
3
4.5
mV/°C
VGS = VDS, ID = –1 mA
(Note 1)
IGSS
—
—
–100
nA
VGS = ± 20V, VDS = 0V
—
—
–100
μA
VGS = 0V,
VDS = Maximum rating
—
—
–10
mA
VDS = 0.8 Maximum rating,
VGS = 0V, TA = 125°C
(Note 1)
–0.4
–0.7
—
A
VGS = –5V, VDS = –15V
–2
–3.3
—
A
VGS = –10V, VDS = –15V
—
2
3.5
Ω
VGS = –5V, ID = –250 mA
—
1.5
2
Ω
VGS = –10V, ID = –1A
—
0.75
1.2
%/°C
VGS = –10V, ID = –1A
(Note 1)
Change in VGS(th) with Temperature
Gate Body Leakage Current
Zero-Gate Voltage Drain Current
On-State Drain Current
Static Drain-to-Source On-State Resistance
Change in RDS(ON) with Temperature
Note 1:
Typ. Max.
Unit
IDSS
ID(ON)
RDS(ON)
∆RDS(ON)
Conditions
Specification is obtained by characterization and is not 100% tested.
DS20005962A-page 2
2019 Microchip Technology Inc.
TP2502
AC ELECTRICAL CHARACTERISTICS
Electrical Specifications: TA = 25°C unless otherwise specified. Specification is obtained by characterization and
is not 100% tested.
Parameter
Sym.
Min.
Typ.
Max.
Forward Transconductance
GFS
300
650
—
Input Capacitance
CISS
—
—
125
pF
Common Source Output Capacitance
COSS
—
—
70
pF
Reverse Transfer Capacitance
CRSS
—
—
25
pF
Turn-On Delay Time
td(ON)
—
—
10
ns
tr
—
—
11
ns
td(OFF)
—
—
15
ns
tf
—
—
12
ns
VSD
—
–1.3
–2
V
VGS = 0V, ISD = –1.5A (Note 1)
trr
—
300
—
ns
VGS = 0V, ISD = –1.5A
Rise Time
Turn-Off Delay Time
Fall Time
Unit
Conditions
mmho VDS = –15V, ID = –1A
VGS = 0V,
VDS = –20V,
f = 1 MHz
VDD = –20V,
ID = –1A,
RGEN = 25Ω
DIODE PARAMETER
Diode Forward Voltage Drop
Reverse Recovery Time
Note 1:
Unless otherwise stated, all DC parameters are 100% tested at 25°C. Pulse test: 300 µs pulse, 2% duty
cycle
TEMPERATURE SPECIFICATIONS
Parameter
Sym.
Min.
Typ. Max.
Unit
Operating Junction Temperature
TJ
–55
—
+150
°C
Storage Temperature
TS
–55
—
+150
°C
JA
—
133
—
°C/W
Conditions
TEMPERATURE RANGE
PACKAGE THERMAL RESISTANCE
3-lead SOT-89
THERMAL CHARACTERISTICS
Package
3-lead SOT-89
Note 1:
2:
ID (Note 1)
(Continuous)
(mA)
ID
(Pulsed)
(A)
–630
–3.3
Power Dissipation
IDR (Note 1)
at TA = 25°C
(Note 2)
(mA)
(W)
1.6
–630
IDRM
(A)
–3.3
ID (continuous) is limited by maximum rated TJ.
Mounted on an FR4 board, 25 mm x 25 mm x 1.57 mm
2019 Microchip Technology Inc.
DS20005962A-page 3
TP2502
2.0
TYPICAL PERFORMANCE CURVES
Note:
The graphs and tables provided following this note are a statistical summary based on a limited number of
samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g. outside specified power supply range) and therefore outside the warranted range.
-5
-5
-4
-4
ID (amperes)
ID (amperes)
VGS = -10V
-3
-9V
-8V
-2
-7V
VGS = -10V
-3
-9V
-8V
-2
-7V
-6V
-1
0
-6V
-1
-5V
-5V
-4V
-3V
0
-10
-20
-30
0
-40
-4V
-3V
0
-1
-2
-3
-4
VDS (volts)
FIGURE 2-1:
1.0
Output Characteristics.
FIGURE 2-4:
-6
-7
-8
-9
-10
Saturation Characteristics.
2.0
VDS = -15V
SOT-89
0.8
1.6
TA = -55OC
0.6
PD (watts)
GFS (siemens)
-5
VDS (volts)
TA = 25OC
0.4
1.2
0.8
TA = 150OC
0.2
0
0.4
0
-0.4
-0.8
-1.2
-1.6
0
-2.0
0
25
50
ID (amperes)
FIGURE 2-2:
Current.
75
100
125
150
TA (OC)
Transconductance vs. Drain
FIGURE 2-5:
Power Dissipation vs.
Ambient Temperature.
-10
Thermal Resistance (normalized)
1.0
SOT-89 (pulsed)
-1.0
ID (amperes)
SOT-89 (DC)
-0.1
TA = 25OC
0.6
0.4
-1.0
-10
-100
SOT-89
TA = 25OC
PD = 1.6W
0.2
0
-0.01
-0.1
0.8
0.001
FIGURE 2-3:
Operating Area.
DS20005962A-page 4
Maximum Rated Safe
0.01
0.1
1
10
tp (seconds)
VDS (volts)
FIGURE 2-6:
Characteristics.
Thermal Response
2019 Microchip Technology Inc.
TP2502
5
1.1
VGS = -5.0V
RDS(ON) (ohms)
BVDSS (normalized)
4
1.0
VGS = -10V
3
2
1
-50
0
50
100
0
150
0
-1
-2
Tj (OC)
FIGURE 2-7:
Temperature.
-3
-4
-5
ID (amperes)
FIGURE 2-10:
Current.
BVDSS Variation with
On-Resistance vs. Drain
-5
2.0
1.4
VDS = -15V
RDS(ON) @ -10V, -1.0A
1.6
VGS(th) normalized)
ID (amperes)
-4
TA = -55OC
-3
-2
25OC
150OC
V(th) @ -1mA
1.2
1.2
0.8
0.8
RDS(ON) (normalized)
0.9
0.4
-1
0.6
0
0
-2
-4
-6
-8
-50
-10
0
0
150
100
O
Tj ( C)
VGS (volts)
FIGURE 2-8:
50
Transfer Characteristics.
FIGURE 2-11:
Temperature.
200
V(th) and RDS Variation with
-10
f = 1.0MHz
200 pF
-8
VGS (volts)
C (picofarads)
150
100
CISS
VDS = -10V
-6
-4
VDS = -40V
50
-2
COSS
80 pF
CRSS
0
0
-10
-20
-30
-40
0
0
VDS (volts)
FIGURE 2-9:
Capacitance vs.
Drain-to-Source Voltage.
2019 Microchip Technology Inc.
0.5
1.0
1.5
2.0
2.5
QG (nanocoulombs)
FIGURE 2-12:
Characteristics.
Gate Drive Dynamic
DS20005962A-page 5
TP2502
3.0
PIN DESCRIPTION
The details on the pins of TP2502 are listed in
Table 3-1. Refer to Package Type for the location of
pins.
TABLE 3-1:
PIN FUNCTION TABLE
Pin Number
Pin Name
Description
1
Gate
Gate
2, 4
Drain
Drain
3
Source
DS20005962A-page 6
Source
2019 Microchip Technology Inc.
TP2502
4.0
FUNCTIONAL DESCRIPTION
Figure 4-1 illustrates the switching waveforms and test
circuit for TP2502.
0V
Pulse
Generator
10%
INPUT
RGEN
90%
t(OFF)
-10V
t(ON)
D.U.T.
td(ON)
tr
td(OFF)
tf
INPUT
OUTPUT
0V
90%
OUTPUT
RL
90%
10%
10%
VDD
VDD
FIGURE 4-1:
TABLE 4-1:
Switching Waveforms and Test Circuit.
PRODUCT SUMMARY
BVDSS/BVDGS
(V)
RDS(ON)
(Maximum)
(Ω)
VGS(TH)
(Maximum)
(V)
ID(ON)
(Minimum)
(A)
–20
2
–2.4
–2
2019 Microchip Technology Inc.
DS20005962A-page 7
TP2502
5.0
PACKAGING INFORMATION
5.1
Package Marking Information
3-lead SOT-89
XXXXYWW
NNN
Legend: XX...X
Y
YY
WW
NNN
e3
*
Note:
DS20005962A-page 8
Example
TP5L926
493
Product Code or Customer-specific information
Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
Pb-free JEDEC® designator for Matte Tin (Sn)
This package is Pb-free. The Pb-free JEDEC designator ( e3 )
can be found on the outer packaging for this package.
In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for product code or customer-specific information. Package may or
not include the corporate logo.
2019 Microchip Technology Inc.
TP2502
3-Lead TO-243AA (SOT-89) Package Outline (N8)
D
D1
C
E H
L
1
2
E1
3
b
b1
e
A
e1
Side View
Top View
Note: For the most current package drawings, see the Microchip Packaging Specification at www.microchip.com/packaging.
Symbol
Dimensions
(mm)
A
b
b1
C
D
D1
E
E1
MIN
1.40
0.44
0.36
0.35
4.40
1.62
2.29
2.00†
NOM
-
-
-
-
-
-
-
-
MAX
1.60
0.56
0.48
0.44
4.60
1.83
2.60
2.29
e
1.50
BSC
e1
3.00
BSC
H
L
3.94
0.73†
-
-
4.25
1.20
JEDEC Registration TO-243, Variation AA, Issue C, July 1986.
† This dimension differs from the JEDEC drawing
Drawings not to scale.
2019 Microchip Technology Inc.
DS20005962A-page 9
TP2502
NOTES:
DS20005962A-page 10
2019 Microchip Technology Inc.
TP2502
APPENDIX A:
REVISION HISTORY
Revision A (January 2019)
• Converted Supertex Doc# DSFP-TP2502 to
Microchip DS20005962A
• Added a pin function table
• Changed the package marking format
• Made formatting changes to comply with Microchip documentation standards
• Made minor text changes throughout the
document
2019 Microchip Technology Inc.
DS20005962A-page 11
TP2502
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, contact your local Microchip representative or sales office.
XX
PART NO.
-
Package
Options
Device
X
-
Environmental
X
Media Type
Device:
TP2502
=
P-Channel Enhancement-Mode Vertical
DMOS FET
Package:
N8
=
3-lead SOT-89
Environmental:
G
=
Lead (Pb)-free/RoHS-compliant Package
Media Type:
(blank)
=
2000/Reel for an N8 Package
DS20005962A-page 12
Example:
a) TP2502N8-G:
P-Channel EnhancementMode, Vertical DMOS FET,
3-lead SOT-89, 2000/Reel
2019 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
•
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
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OTHERWISE, RELATED TO THE INFORMATION,
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© 2019, Microchip Technology Incorporated, All Rights Reserved.
ISBN: 978-1-5224-4030-7
== ISO/TS 16949 ==
2019 Microchip Technology Inc.
DS20005962A-page 13
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DS20005962A-page 14
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08/15/18
