UCS1003-3-BP

UCS1003-1/2/3 USB Port Power Controller with Charger Emulation Features Description • Port Power Switch with Two Current Limit Behaviors: - 2.9V to 5.5V source voltage range - Up to 3.0A current (2.85A typical) with 55 m on resistance - Overcurrent trip or Constant-Current Limiting - Soft turn-on circuitry - Selectable current limit - UCS1003-1 has programmable current limit via the SMBus 2.0/I2C protocol - Dynamic thermal management - Undervoltage Lockout (UVLO) and Overvoltage Lockout (OVLO) - Backdrive, back-voltage protection - Latch or auto-recovery (low test current) Fault handling - Selectable active-high or active-low power switch enable - BC1.2 VBUS discharge port renegotiation function • Selectable/Automatic Cycling of Universal Serial Bus (USB) Data Line Charger Emulation Profiles: - USB-IF BC1.2 Charging Downstream Port (CDP) and Dedicated Charging Port (DCP) modes, Chinese Telecommunications Industry Standard YD/T 1591-2009 and most Apple® Inc., Samsung and RIM® protocols standard - UCS1003-1 supports other charger emulation profiles as defined via the SMBus 2.0/I2C protocol - Supports 12W charging emulation - USB 2.0 compliant high-speed data switch (in Data Pass-Through, SDP and CDP modes) - Nine preloaded charger emulation profiles for maximum compatibility coverage of the peripheral devices - UCS1003-1 has one custom programmable charger emulation profile for portable device support for fully host-controlled charger emulation • Supports Active Cables • UCS1003-1 Supports Self-Contained Current Monitoring and Rationing for Power Allocation Applications • UCS1003-1 and UCS1003-3 have Low-Power Attach Detection and Open-Drain (A_DET#) Pin • UCS1003-2 has Charging Active (CHRG#) Open-Drain Pin • Ultra Low-Power Sleep State • Optional Split Supply Support for VS and VDD for Low Power in System Standby States • Wake on Attach USB (UCS1003-1 and UCS1003-3) • UCS1003-1 Supports SMBus 2.0/I2C Communications: - Supports block write and read - Multiple SMBus addresses • Wide Operating Temperature Range: -40°C to +85°C • IEC61000-4-2 8/15 kV Electrostatic Discharge (ESD) Immunity • UL Recognized and EN/IEC 60950-1 (CB) Certified The UCS1003-1/2/3 family of devices provides a USB port power switch for precise control of up to 3.0A continuous current (2.85A typical) with Overcurrent Limit (OCL), dynamic thermal management, latch or auto-recovery (low test current) Fault handling, selectable active-high or active-low enable, Undervoltage and Overvoltage Lockout, backdrive protection and back-voltage protection. Split supply support for VS and VDD is an option for low power in system standby states. This gives batteryoperated applications (such as on-board computers) the ability to detect attachments from a Sleep or OFF state. After the Attach Detection is flagged, the system can decide to wake-up and/or provide charging. In addition to Power Switching and Current-Limiting modes, the UCS1003-1/2/3 will automatically charge a wide variety of portable devices, including USB-IF BC1.2, YD/T-1591 (2009), most Apple Inc., Samsung, RIM and many others. Nine preloaded charger emulation profiles maximize the compatibility coverage of the peripheral devices. Additionally, a customizable charger emulation profile is available in UCS1003-1 to accommodate unique existing and future portable device handshaking/signature requirements. The UCS1003-1 also provides current monitoring to allow intelligent management of system power and charge rationing for controlled delivery of current, regardless of the host power state. This is especially important for battery-operated applications that want to provide power and do not want to drain the battery excessively. The UCS1003-1/2/3 family is available in a 4 mm x 4 mm 20-pin QFN package.  2014-2015 Microchip Technology Inc. Applications • • • • • Notebook and Netbook Computers Tablets and E-Book Readers Desktops and Monitors Docking Stations and Printers AC-DC Wall Adapters DS20005346B-page 1 UCS1003-1/2/3 Package Type EM_EN A_DET# DPOUT DMOUT GND EM_EN CHRG# DPOUT DMOUT UCS1003-2 4x4 QFN* GND UCS1003-1 4x4 QFN* 20 19 18 17 16 20 19 18 17 16 13 ALERT# VBUS1 3 12 SMCLK/S0 VBUS2 4 11 SMDATA/LATCH 6 7 8 9 10 SEL VS1 VS2 VDD PWR_EN COMM_SEL/ILIM 5 14 DPIN EP 21 13 ALERT# 12 S0 11 LATCH ILIM 5 6 7 8 9 10 PWR_EN VBUS2 4 M2 2 VDD VBUS1 3 14 DPIN 15 DMIN VS2 EP 21 M1 1 VS1 M2 2 15 DMIN SEL M1 1 GND EM_EN A_DET# DPOUT DMOUT UCS1003-3 4x4 QFN* 20 19 18 17 16 15 DMIN M1 1 M2 2 14 DPIN EP 21 VBUS1 3 13 ALERT# 12 S0 VBUS2 4 11 LATCH 6 7 8 9 10 SEL VS1 VS2 VDD PWR_EN ILIM 5 * Includes Exposed Thermal Pad (EP); see Table 3-1. DS20005346B-page 2  2014-2015 Microchip Technology Inc. UCS1003-1/2/3 Block Diagram DPIN DMIN VDD USB 2.0 HS Data Switch & Charger Emulator VDD DMOUT Attach Detector VS GND DPOUT VBUS UVLO, OVLO Power Switch COMM_SEL(1)/ILIM ALERT# A_DET#(1,3) VDD Charger Control, Measurement, OCL CHRG#(2) Temp Interface, Logic PWR_EN SEL EM_EN M1 M2 SMCLK(1)/S0 SMDATA(1)/LATCH Note 1: 2: 3: Available for UCS1003-1 only. Available for UCS1003-2 only. Available for UCS1003-3 only.  2014-2015 Microchip Technology Inc. DS20005346B-page 3 UCS1003-1/2/3 NOTES: DS20005346B-page 4  2014-2015 Microchip Technology Inc. UCS1003-1/2/3 1.0 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings† Voltage on VDD, VS and VBUS Pins ....................................................................................................................-0.3 to 6V Pull-up Voltage (VPULLUP) .................................................................................................................... -0.3 to VDD + 0.3V Data Switch Current (IHSW_ON), Switch On........................................................................................................... ±50 mA Port Power Switch Current .................................................................................................................... Internally Limited Data Switch Pin Voltage To Ground (DPOUT, DPIN, DMOUT, DMIN); (VDD powered or unpowered)....... -0.3 to VDD + 0.3V Differential Voltage Across Open Data Switch (DPOUT – DPIN, DMOUT – DMIN, DPIN – DPOUT, DMIN – DMOUT) .........VDD Voltage on any Other Pin to Ground ................................................................................................... -0.3 to VDD + 0.3V Current on any Other Pin ...................................................................................................................................... ±10 mA Package Power Dissipation ............................................................................................................................... Table 1-1 Operating Ambient Temperature Range ..................................................................................................... -40 to +125°C Storage Temperature Range....................................................................................................................... -55 to +150°C † Notice: Stresses above those listed under “Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. TABLE 1-1: POWER DISSIPATION SUMMARY Package JC JA Derating Factor Above +25°C TA < +25°C Power Rating TA < +70°C Power Rating TA < +85°C Power Rating High K (see Note 1) 20-pin QFN 4 x 4 mm 6°C/W 41°C/W 24.4 mW°/C 2193 mW 1095 mW 729 mW Low K (see Note 1) 20-pin QFN 4 x 4 mm 6°C/W 60°C/W 16.67 mW°/C 1498 mW 748 mW 498 mW Board Note 1: Junction to ambient (JA) is dependent on the design of the thermal vias. A High K board uses a thermal via design with a thermal landing soldered to the PCB ground plane, with 0.3 mm (12 mil) diameter vias in a 3x3 matrix (9 total) at 0.5 mm (20 mil) pitch. The board is multilayer with 1-ounce internal power and ground planes and 2-ounce copper traces on top and bottom. A Low K board is a two-layer board without thermal via design, with 2-ounce copper traces on the top and bottom.  2014-2015 Microchip Technology Inc. DS20005346B-page 5 UCS1003-1/2/3 TABLE 1-2: ELECTRICAL CHARACTERISTICS Electrical Characteristics: Unless otherwise specified, VDD = 4.5V to 5.5V, VS = 2.9V to 5.5V, VPULLUP = 3V to 5.5V, TA = -40°C to +85°C; all Typical values at VDD = VS = 5V, TA = +27°C. Characteristic Sym. Min. Typ. Max. Unit Conditions Supply Voltage VDD 4.5 5 5.5 V (Note 1) Source Voltage VS 2.9 5 5.5 V (Note 1) Supply Current in Active (IDD_ACTIVE + IVS_ACT) IACTIVE — 650 750 µA Average current, IBUS = 0 mA Supply Current in Sleep (IDD_SLEEP + IVS_SLEEP) ISLEEP — 5 15 µA Average current, VPULLUP  VDD IDETECT — 185 — µA Average current, no portable device attached VS Low Threshold VS_UVLO — 2.5 — V VS voltage increasing VS Low Hysteresis VS_UVLO_HYST — 100 — mV VS voltage decreasing VDD Low Threshold VDD_TH — 4 — V VDD voltage increasing VDD Low Hysteresis VDD_TH_HYST — 500 — mV VDD voltage decreasing Power Supply Supply Current in Detect (IDD_DETECT + IVS_DETECT) Power-on Reset I/O Pins – SMCLK (UCS1003-1), SMDATA (UCS1003-1), EM_EN, M1, M2, PWR_EN, S0, LATCH, ALERT#, A_DET# (UCS1003-1 and UCS1003-3), CHRG# (UCS1003-2) – DC Parameters Output Low Voltage VOL — — 0.4 V ISINK_IO = 8 mA, SMDATA, ALERT#, A_DET#, CHRG# Input High Voltage VIH 2.0 — — V PWR_EN, EM_EN, M1, M2, LATCH, S0, SMDATA, SMCLK Input Low Voltage VIL — — 0.8 V PWR_EN, EM_EN, M1, M2, LATCH, S0, SMDATA, SMCLK Leakage Current ILEAK — — ±5 µA Powered or unpowered, VPULLUP  VDD ALERT#, A_DET# Pins Blanking Time tBLANK — 25 — ms ALERT# Pin Interrupt Masking Time tMASK — 5 — ms Interrupt Pins – AC Parameters SMBus/I2C Timing (UCS1003-1 only) Input Capacitance CIN — 5 — pF Clock Frequency fSMB 10 — 400 kHz — 50 ns — — µs Spike Suppression tSP Bus Free Time Stop to Start tBUF Note 1: 2: 3: 4: 5: 1.3 (Note 2) For split supply systems using the Attach Detection feature, VS must not exceed VDD + 150 mV. This parameter is ensured by design and not 100% tested. This parameter is characterized, but not 100% production tested. The current measurement full-scale range maximum value is 3.0A. However, the UCS1003-1 cannot report values above ILIM (if IBUS_R2MIN  ILIM) or above IBUS_R2MIN (if IBUS_R2MIN > ILIM and ILIM 1.68A). The Min and Max values represent the boundaries of a programmable range for UCS1003-1 only. Each value in the range is typical. DS20005346B-page 6  2014-2015 Microchip Technology Inc. UCS1003-1/2/3 TABLE 1-2: ELECTRICAL CHARACTERISTICS (CONTINUED) Electrical Characteristics: Unless otherwise specified, VDD = 4.5V to 5.5V, VS = 2.9V to 5.5V, VPULLUP = 3V to 5.5V, TA = -40°C to +85°C; all Typical values at VDD = VS = 5V, TA = +27°C. Characteristic Sym. Min. Typ. Max. Unit Start Setup Time tSU:STA 0.6 — — µs Start Hold Time tHD:STA 0.6 — — µs Stop Setup Time tSU:STO 0.6 — — µs Data Hold Time tHD:DAT 0 — — µs When transmitting to the master Data Hold Time tHD:DAT 0.3 — — µs When receiving from the master Data Setup Time tSU:DAT 0.6 — — µs Clock Low Period tLOW 1.3 — — µs Clock High Period tHIGH 0.6 — — µs Clock/Data Fall Time tFALL — — 300 ns Min = 20 + 0.1 CLOAD ns (Note 3) Clock/Data Rise Time tRISE — — 300 ns Min = 20 + 0.1 CLOAD ns (Note 3) CLOAD — — 400 pF Per bus line (Note 2) Time-out tTIMEOUT 25 — 35 ms Disabled by default (Note 2) Idle Reset tIDLE_RESET 350 — — µs Disabled by default (Note 2) Capacitive Load Conditions High-Speed Data Switch High-Speed Data Switch – DC Parameters Switch Leakage Current IHSW_OFF — ±0.5 — µA Switch open – DPIN to DPOUT, DMIN to DMOUT or all four pins to ground; VDD  VS RCHG — 2 — M DPOUT or DMOUT to VBUS, or ground (see Figure 1-2), BC1.2 DCP charger emulation is active On Resistance RON_HSW — 2 —  Switch closed, VDD = 5V Test Current = 8 mA, Test Voltage = 0.4V (see Figure 1-2) On Resistance RON_HSW_1 — 5 —  Switch closed, VDD = 5V, Test Current = 8 mA, Test Voltage = 3.0V (see Figure 1-2) Delta-On Resistance RON_HSW — ±0.3 —  Switch closed, VDD = 5V, ITST = 8 mA, VTST = 0 to 1.5V (see Figure 1-2) Charger Resistance High-Speed Data Switch – AC Parameters DP, DM Capacitance to Ground CHSW_ON — 4 — pF Switch closed, VDD = 5V DP, DM Capacitance to Ground CHSW_OFF — 2 — pF Switch open, VDD = 5V Note 1: 2: 3: 4: 5: For split supply systems using the Attach Detection feature, VS must not exceed VDD + 150 mV. This parameter is ensured by design and not 100% tested. This parameter is characterized, but not 100% production tested. The current measurement full-scale range maximum value is 3.0A. However, the UCS1003-1 cannot report values above ILIM (if IBUS_R2MIN  ILIM) or above IBUS_R2MIN (if IBUS_R2MIN > ILIM and ILIM 1.68A). The Min and Max values represent the boundaries of a programmable range for UCS1003-1 only. Each value in the range is typical.  2014-2015 Microchip Technology Inc. DS20005346B-page 7 UCS1003-1/2/3 TABLE 1-2: ELECTRICAL CHARACTERISTICS (CONTINUED) Electrical Characteristics: Unless otherwise specified, VDD = 4.5V to 5.5V, VS = 2.9V to 5.5V, VPULLUP = 3V to 5.5V, TA = -40°C to +85°C; all Typical values at VDD = VS = 5V, TA = +27°C. Characteristic Sym. Min. Typ. Max. Unit Conditions Turn-Off Time tHSW_OFF — 400 — µs Time from state control (EM_EN, M1, M2) switch on to switch off, RTERM = 50, CLOAD = 5 pF Turn-On Time tHSW_ON — 400 — µs Time from state control (EM_EN, M1, M2) switch off to switch on, RTERM = 50, CLOAD = 5 pF tPD — 0.25 — ns RTERM = 50, CLOAD = 5 pF Propagation Delay Skew tPD — 25 — ps RTERM = 50, CLOAD = 5 pF Rise/Fall Time tF/R — 10 — ns RTERM = 50, CLOAD = 5 pF DP – DM Crosstalk XTALK — -40 — dB RTERM = 50, CLOAD = 5 pF Off Isolation OIRR — -30 — dB RTERM = 50, CLOAD = 5 pF, f = 240 MHz -3 dB Bandwidth BW — 1100 — MHz RTERM = 50, CLOAD = 5 pF, VDPOUT = VDMOUT = 350 mV DC tJ — 200 — ps RTERM = 50, CLOAD = 5 pF, Rise Time = Fall Time = 500 ps at 480 Mbps (PRBS = 215 – 1) tSK(P) — 20 — ps RTERM = 50, CLOAD = 5 pF Propagation Delay Total Jitter Skew of Opposite Transitions of the Same Output Port Power Switch Port Power Switch – DC Parameter Overvoltage Lockout VS_OV — 6 — V On Resistance RON_PSW — 55 — m VS Leakage Current ILEAK_VS — 2.2 — µA Sleep state into VS pin Back-Voltage Protection Threshold VBV_TH — 150 — mV VBUS > VS, VS > VS_UVLO IBD_1 — 0 3 µA VDD < VDD_TH, Any powered power pin to any unpowered power pin; current out of unpowered pin (Note 3) IBD_2 — 0 2 µA VDD < VDD_TH, Any powered power pin to any unpowered power pin, except for VDD to VBUS in Detect power state and VS to VBUS in Active power state; current out of unpowered pin (Note 3) Backdrive Current Note 1: 2: 3: 4: 5: 4.75V < VS < 5.25V For split supply systems using the Attach Detection feature, VS must not exceed VDD + 150 mV. This parameter is ensured by design and not 100% tested. This parameter is characterized, but not 100% production tested. The current measurement full-scale range maximum value is 3.0A. However, the UCS1003-1 cannot report values above ILIM (if IBUS_R2MIN  ILIM) or above IBUS_R2MIN (if IBUS_R2MIN > ILIM and ILIM 1.68A). The Min and Max values represent the boundaries of a programmable range for UCS1003-1 only. Each value in the range is typical. DS20005346B-page 8  2014-2015 Microchip Technology Inc. UCS1003-1/2/3 TABLE 1-2: ELECTRICAL CHARACTERISTICS (CONTINUED) Electrical Characteristics: Unless otherwise specified, VDD = 4.5V to 5.5V, VS = 2.9V to 5.5V, VPULLUP = 3V to 5.5V, TA = -40°C to +85°C; all Typical values at VDD = VS = 5V, TA = +27°C. Characteristic Selectable Current Limits Sym. Min. Typ. Max. Unit ILIM1 — 570 — mA Conditions ILIM Resistor = 0 or 47 k (UCS1003-1 only) ILIM Resistor = 47 k (UCS1003-2/3) (minimum mA setting) ILIM2 — 1000 — ILIM Resistor = 10 k or 56 k (UCS1003-1 only) ILIM Resistor = 56 k (UCS1003-2/3) ILIM3 — 1130 — ILIM Resistor = 12 k or 68 k (UCS1003-1 only) ILIM Resistor = 68 k (UCS1003-2/3) ILIM4 — 1350 — ILIM Resistor = 15 k or 82 k (UCS1003-1 only) ILIM Resistor = 82 k (UCS1003-2/3) ILIM5 — 1680 — ILIM Resistor = 18 k or 100 k (UCS1003-1 only) ILIM Resistor = 100 k (UCS1003-2/3) ILIM6 — 2050 — ILIM Resistor = 22 k or 120 k (UCS1003-1 only) ILIM Resistor = 120 k (UCS1003-2/3) ILIM7 — 2280 — ILIM Resistor = 27 k or 150 k (UCS1003-1 only) ILIM Resistor = 150 k (UCS1003-2/3) ILIM8 2700 2850 3000 ILIM Resistor = 33 k or VDD (UCS1003-1 only) ILIM Resistor = VDD (UCS1003-2/3) Pin Wake Time tPIN_WAKE — 3 — ms SMBus Wake Time tSMB_WAKE — 4 — ms (UCS1003-1 only) Idle Sleep Time tIDLE_SLEEP — 200 — ms (UCS1003-1 only) Note 1: 2: 3: 4: 5: For split supply systems using the Attach Detection feature, VS must not exceed VDD + 150 mV. This parameter is ensured by design and not 100% tested. This parameter is characterized, but not 100% production tested. The current measurement full-scale range maximum value is 3.0A. However, the UCS1003-1 cannot report values above ILIM (if IBUS_R2MIN  ILIM) or above IBUS_R2MIN (if IBUS_R2MIN > ILIM and ILIM 1.68A). The Min and Max values represent the boundaries of a programmable range for UCS1003-1 only. Each value in the range is typical.  2014-2015 Microchip Technology Inc. DS20005346B-page 9 UCS1003-1/2/3 TABLE 1-2: ELECTRICAL CHARACTERISTICS (CONTINUED) Electrical Characteristics: Unless otherwise specified, VDD = 4.5V to 5.5V, VS = 2.9V to 5.5V, VPULLUP = 3V to 5.5V, TA = -40°C to +85°C; all Typical values at VDD = VS = 5V, TA = +27°C. Characteristic Sym. Min. Typ. Max. Unit TREG — 110 — °C Die temperature at which current limit will be reduced Thermal Regulation Hysteresis TREG_HYST — 10 — °C Hysteresis for tREG functionality; temperature must drop by this value before ILIM value is restored to normal operation Thermal Shutdown Threshold TTSD — 135 — °C Die temperature at which port power switch will turn off Thermal Shutdown Hysteresis TTSD_HYST — 35 — °C After shutdown, due to TTSD being reached, die temperature drop required before port power switch can be turned on again Auto-Recovery Test Current ITEST — 190 — mA Portable device attached, VBUS = 0V, Die Temp < TTSD Auto-Recovery Test Voltage VTEST — 750 — mV Portable device attached, VBUS = 0V before application, Die Temp < TTSD programmable (UCS1003-1 only), 250-1000 mV, default listed RDISCHARGE — 100 —  Thermal Regulation Limit Discharge Impedance Conditions Port Power Switch – AC Parameters Turn-On Delay tON_PSW — 0.75 — ms PWR_EN active toggle to switch on time, VBUS discharge is not active Turn-Off Time tOFF_PSW_INA — 0.75 — ms PWR_EN inactive toggle to switch off time, CBUS = 120 μF Turn-Off Time tOFF_PSW_ERR — 1 — ms Overcurrent error, VBUS min error or discharge error to switch off, CBUS = 120 μF Turn-Off Time tOFF_PSW_ERR — 100 — ns TSD or backdrive error to switch off, CBUS = 120 μF tR_BUS — 1.1 — ms Measured from 10% to 90% of VBUS, CLOAD = 220 μF, ILIM = 1.0A Soft Turn-on Rate IBUS/t — 100 — mA/µs Temperature Update Time tDC_TEMP — 200 — ms VBUS Output Rise Time Note 1: 2: 3: 4: 5: Programmable (UCS1003-1 only) 200-1600 ms, default listed For split supply systems using the Attach Detection feature, VS must not exceed VDD + 150 mV. This parameter is ensured by design and not 100% tested. This parameter is characterized, but not 100% production tested. The current measurement full-scale range maximum value is 3.0A. However, the UCS1003-1 cannot report values above ILIM (if IBUS_R2MIN  ILIM) or above IBUS_R2MIN (if IBUS_R2MIN > ILIM and ILIM 1.68A). The Min and Max values represent the boundaries of a programmable range for UCS1003-1 only. Each value in the range is typical. DS20005346B-page 10  2014-2015 Microchip Technology Inc. UCS1003-1/2/3 TABLE 1-2: ELECTRICAL CHARACTERISTICS (CONTINUED) Electrical Characteristics: Unless otherwise specified, VDD = 4.5V to 5.5V, VS = 2.9V to 5.5V, VPULLUP = 3V to 5.5V, TA = -40°C to +85°C; all Typical values at VDD = VS = 5V, TA = +27°C. Characteristic Sym. Min. Typ. Max. Unit Short-Circuit Response Time tSHORT_LIM — 1.5 — µs Time from detection of short to current limit applied; no CBUS applied Short-Circuit Detection Time tSHORT — 6 — ms Time from detection of short to port power switch disconnect and ALERT# pin assertion tUL — 7 — ms From PWR_EN edge transition from inactive to active to begin error recovery Auto-Recovery Mode Cycle Time tCYCLE — 25 — ms Time delay before error condition check, programmable (UCS1003-1 only) 10-25 ms, default listed Auto-Recovery Delay tRST — 20 — ms Portable device attached, VBUS must be  VTEST after this time, programmable (UCS1003-1 only) 10-25 ms, default listed tDISCHARGE — 200 — ms Amount of time discharge resistor applied, programmable (UCS1003-1 only) 100-400 ms, default listed Latched Mode Cycle Time Discharge Time Conditions Port Power Switch Operation with Trip Mode Current Limiting Region 2 Current Keep-out IBUS_R2MIN — 0.12 — A Minimum VBUS Allowed at Output VBUS_MIN 1.5 2.0 2.25 V Port Power Switch Operation with Constant-Current Limiting (Variable Slope) Region 2 Current Keep-out IBUS_R2MIN — 1.68 — A Minimum VBUS Allowed at Output VBUS_MIN 1.5 2.0 2.25 V Current Measurement (UCS1003-1 only) – DC Current Measurement Range Reported Current Measurement Resolution IBUS_M 0 — 2988.6 mA Range 0-255 LSB (Note 4) DIBUS_M — 11.72 — mA 1 LSB — ±2 — % — ±2 — LSB Current Measurement Accuracy 180 mA < IBUS < ILIM IBUS < 180 mA Current Measurement (UCS1003-1 only) – AC Sampling Rate Note 1: 2: 3: 4: 5: — 500 — µs For split supply systems using the Attach Detection feature, VS must not exceed VDD + 150 mV. This parameter is ensured by design and not 100% tested. This parameter is characterized, but not 100% production tested. The current measurement full-scale range maximum value is 3.0A. However, the UCS1003-1 cannot report values above ILIM (if IBUS_R2MIN  ILIM) or above IBUS_R2MIN (if IBUS_R2MIN > ILIM and ILIM 1.68A). The Min and Max values represent the boundaries of a programmable range for UCS1003-1 only. Each value in the range is typical.  2014-2015 Microchip Technology Inc. DS20005346B-page 11 UCS1003-1/2/3 TABLE 1-2: ELECTRICAL CHARACTERISTICS (CONTINUED) Electrical Characteristics: Unless otherwise specified, VDD = 4.5V to 5.5V, VS = 2.9V to 5.5V, VPULLUP = 3V to 5.5V, TA = -40°C to +85°C; all Typical values at VDD = VS = 5V, TA = +27°C. Characteristic Sym. Min. Typ. Max. Unit Conditions Charge Rationing (UCS1003-1 only) - DC Accumulated Current Measurement Accuracy — ±4.5 — % Charge Rationing (UCS1003-1 only) – AC Current Measurement Update Time — tPCYCLE 1 — s Attach/Removal Detection VBUS Bypass – DC On Resistance RON_BYP — 50 —  Leakage Current ILEAK_BYP — — 3 µA Switch off (Note 2) Current Limit IDET_CHG / IBUS_BYP — 2 — mA VDD = 5V and VBUS > 4.75V Attach/Removal Detection – DC Attach Detection Threshold IDET_QUAL — 800 — µA Programmable (UCS1003-1 only) 200-1000 µA, default listed Primary Removal Detection Threshold IREM_QUAL_ACT — 700 — µA Programmable (UCS1003-1 only) 100-900 µA, default listed, Active power state IREM_QUAL_DET — 800 — µA Programmable (UCS1003-1 only) 200-1000 µA, default listed, Detect power state (see Section 8.4 “Removal Detection”) Time from attach to A_DET# assert (UCS1003-1 and UCS1003-3 only) Attach/Removal Detection – AC Attach Detection Time tDET_QUAL — 100 — ms Removal Detection Time tREM_QUAL — 1000 — ms tDET_CHARGE — 800 — ms CBUS = 500 µF maximum, programmable 200-2000 ms, default listed Allowed Charge Time Charger Emulation Profile General Emulation – DC Charging Current Threshold Note 1: 2: 3: 4: 5: IBUS_CHG — 46.9 — mA Default value for UCS1003-1 — 175.8 — mA UCS1003-2 and UCS1003-3 For split supply systems using the Attach Detection feature, VS must not exceed VDD + 150 mV. This parameter is ensured by design and not 100% tested. This parameter is characterized, but not 100% production tested. The current measurement full-scale range maximum value is 3.0A. However, the UCS1003-1 cannot report values above ILIM (if IBUS_R2MIN  ILIM) or above IBUS_R2MIN (if IBUS_R2MIN > ILIM and ILIM 1.68A). The Min and Max values represent the boundaries of a programmable range for UCS1003-1 only. Each value in the range is typical. DS20005346B-page 12  2014-2015 Microchip Technology Inc. UCS1003-1/2/3 TABLE 1-2: ELECTRICAL CHARACTERISTICS (CONTINUED) Electrical Characteristics: Unless otherwise specified, VDD = 4.5V to 5.5V, VS = 2.9V to 5.5V, VPULLUP = 3V to 5.5V, TA = -40°C to +85°C; all Typical values at VDD = VS = 5V, TA = +27°C. Characteristic Sym. Min. Typ. Max. Unit IBUS_CHG_RNG 11.72 — 175.8 mA RDCP_RES — — 200  Connected between DPOUT and DMOUT, 0V < DPOUT = DMOUT < 3V Response Magnitude (voltage divider option resistance range) SX_RXMAG_ DVDR 93 — 200 k (Note 5) Resistor Ratio Range (voltage divider option) SX_RATIO 0.25 — 0.66 V/V (Note 5) Resistor Ratio Accuracy (voltage divider option) SX_RATIO_ ACC — ±0.5 — % Average over range Response Magnitude (resistor option range) SX_RXMAG_ RES 1.8 — 150 k (Note 5) Internal Resistor Tolerance (resistor option) SX_RXMAG_ RES_ACC — ±10 — % Average over range Response Magnitude (voltage option range) SX_RXMAG_ VOLT 0.4 — 2.2 V (Note 5) Voltage Option Accuracy SX_RXMAG_ VOLT_ACC — ±1 — % No load, average over range Voltage Option Accuracy SX_RXMAG_ VOLT_ACC_ 150 — -6 — % 150 µA load, average over range Voltage Option Accuracy SX_RXMAG_ VOLT_ACC_ 250 — -10 — % 250 µA load, average over range Voltage Option Output SX_RXMAG_ VOLT_BC 0.5 — — V DMOUT = 0.6V, 250 µA load (Note 3) Response Magnitude (zero volt option range) SX_PUPD 10 — 150 µA SX_RXMAG_VOLT = 0 (Note 5) Pull-Down Current Accuracy SX_PUPD _ ACC_3p6 — ±5 — % DPOUT or DMOUT = 3.6V, compliance voltage Pull-Down Current SX_PUPD _ ACC_BC 50 — — µA Setting = 100 µA, DPOUT or DMOUT = 0.15V compliance voltage (Note 3) Stimulus Voltage Threshold Range SX_TH 0.3 — 2.2 V (Note 5) Stimulus Voltage Accuracy SX_TH_ ACC — ±2 — % Average over range Stimulus Voltage Accuracy SX_TH_ACC_ BC 0.25 — — V At SX_TH = 0.3V (Note 3) Charging Current Threshold Range DP-DM Shunt Resistor Value Note 1: 2: 3: 4: 5: Conditions (Note 5) For split supply systems using the Attach Detection feature, VS must not exceed VDD + 150 mV. This parameter is ensured by design and not 100% tested. This parameter is characterized, but not 100% production tested. The current measurement full-scale range maximum value is 3.0A. However, the UCS1003-1 cannot report values above ILIM (if IBUS_R2MIN  ILIM) or above IBUS_R2MIN (if IBUS_R2MIN > ILIM and ILIM 1.68A). The Min and Max values represent the boundaries of a programmable range for UCS1003-1 only. Each value in the range is typical.  2014-2015 Microchip Technology Inc. DS20005346B-page 13 UCS1003-1/2/3 TABLE 1-2: ELECTRICAL CHARACTERISTICS (CONTINUED) Electrical Characteristics: Unless otherwise specified, VDD = 4.5V to 5.5V, VS = 2.9V to 5.5V, VPULLUP = 3V to 5.5V, TA = -40°C to +85°C; all Typical values at VDD = VS = 5V, TA = +27°C. Characteristic Sym. Min. Typ. Max. Unit Conditions General Emulation – AC — 50 — ms Default Emulation Reset Time Range tEM_RESET_ RNG 50 — 175 ms (Note 5) Emulation Time-out Range tEM_ TIMEOUT 0.8 — 12.8 s (Note 5) Stimulus Delay, SX_TD Range tSTIM_DEL 0 — 100 ms (Note 5) Emulation Delay tRES_EM — — 0.5 s Emulation Reset Time Note 1: 2: 3: 4: 5: tEM_RESET Time from set impedance to impedance appearing on DP/DM (Note 3) For split supply systems using the Attach Detection feature, VS must not exceed VDD + 150 mV. This parameter is ensured by design and not 100% tested. This parameter is characterized, but not 100% production tested. The current measurement full-scale range maximum value is 3.0A. However, the UCS1003-1 cannot report values above ILIM (if IBUS_R2MIN  ILIM) or above IBUS_R2MIN (if IBUS_R2MIN > ILIM and ILIM 1.68A). The Min and Max values represent the boundaries of a programmable range for UCS1003-1 only. Each value in the range is typical. Fall Time Rise Time 90% 90% VCRS 10% 10% Differential Data Lines tR tF Data Signal Rise and Fall Time FIGURE 1-1: DS20005346B-page 14 USB Rise Time/Fall Time Measurement.  2014-2015 Microchip Technology Inc. UCS1003-1/2/3 VBUS RCHG DPOUT DPIN RCHG VTST ITST VBUS RCHG DMOUT DMIN RCHG VTST FIGURE 1-2: TABLE 1-3: ITST Description of DC Terms. TEMPERATURE SPECIFICATIONS Parameters Sym Min Typ Max Units Operating Temperature Range TA -40 — +85 °C Storage Temperature Range TA -55 — +150 °C Conditions Temperature Ranges Thermal Package Resistances (see Table 1-1)  2014-2015 Microchip Technology Inc. DS20005346B-page 15 UCS1003-1/2/3 NOTES: DS20005346B-page 16  2014-2015 Microchip Technology Inc. UCS1003-1/2/3 2.0 TYPICAL PERFORMANCE CURVES Note: The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range. Note: Unless otherwise indicated, VDD = VS = 5V, TA = +27°C. Voltage (V) Voltage (V) 6 5 4 3 2 1 0 Current (A) VS = VDD = 5V, short applied at 16 ms 6 5 4 3 2 1 0 5 VDD ALERT# Pin IBUS Current 0 0 10 20 30 40 50 Time (ms) FIGURE 2-4: Power-up Into a Short. 6 14 VBUS VS = VDD = 5V, ILIM = 2.05A (typical), short applied at 17.2 µs Voltage (V) 5 10 3 8 2 6 1 4 0 2 IBUS 0 -1 -2 -2 0 FIGURE 2-2: USB-IF High-Speed Eye Diagram (With Data Switch). 4 3 IBUS 2 2 1 1 VBUS 0 0 -1 -1 0 FIGURE 2-3: Power-up. 2 4 6 Time (ms) 8 Short Applied After  2014-2015 Microchip Technology Inc. 40 Time (µs) Internal Power Switch Short 10 VBUS Voltage (V) Voltage (V) 5 5 4 4 3 FIGURE 2-5: Response. 6 Current (A) ALERT # 5 20 6 VS = VDD = 5V ILIM = 3A max. (2.85A typical), short applied at 2 ms 6 12 4 Current (A) FIGURE 2-1: USB-IF High-Speed Eye Diagram (Without Data Switch). VS = VDD = 5V M2 = 0, M1 = PWR_EN = 1 3 2 1 EM_EN 0 -1 0 FIGURE 2-6: 100 200 300 Time (ms) 400 500 VBUS Discharge Behavior. DS20005346B-page 17 UCS1003-1/2/3 Note: Unless otherwise indicated, VDD = VS = 5V, TA = +27°C. 90 70 60 On Resistance (m:) Off Isolation (dB) 80 70 60 50 40 30 20 DPOUT = DMOUT = 0.35V 30 20 0 0.1 FIGURE 2-7: Frequency. 1 10 Frequency (MHz) 100 -40 1000 Data Switch Off Isolation vs. 0 200 -2 180 -4 160 -6 -8 -10 -12 -14 10 35 Temperature (°C) 85 DPOUT = DMOUT = 3V 140 120 DPOUT = DMOUT = 0.15V 100 80 60 20 -18 0 -20 0.01 1 100 Frequency (MHz) FIGURE 2-8: Frequency. -40 10000 Data Switch Bandwidth vs. -15 FIGURE 2-11: Temperature. 2.5 10 35 Temperature (°C) 60 85 RDCP_RES Resistance vs. 1 VS = VDD = 5V 0.95 2.0 0.9 0.85 Time (ms) On Resistance (:) 60 40 DPOUT = DMOUT = 0.35V -16 -15 FIGURE 2-10: Power Switch On Resistance vs. Temperature. Resistance (:) Gain (dB) 40 10 10 0 0.01 50 1.5 1.0 0.8 Turn off time 0.75 0.7 Turn on time 0.65 0.6 0.5 0.55 DPOUT = DMOUT = 0.4V 0.5 0.0 -40 -15 FIGURE 2-9: vs. Temperature. DS20005346B-page 18 10 35 Temperature (°C) 60 85 Data Switch On Resistance -40 -15 FIGURE 2-12: vs. Temperature. 10 35 Temperature (°C) 60 85 Power Switch On/Off Time  2014-2015 Microchip Technology Inc. UCS1003-1/2/3 Note: Unless otherwise indicated, VDD = VS = 5V, TA = +27°C. 0 VDD = 5V Current Limit Accuracy (%) Threshold Voltage (V) 6 5.99 5.98 5.97 5.96 5.95 5.94 5.93 5.92 5.91 5.9 -40 -15 FIGURE 2-13: vs. Temperature. 10 35 Temperature (°C) 60 85 VS Overvoltage Threshold Note: Specification is 0% maximum and -10% minimum -3 -4 -5 -6 -7 -8 -9 -40 -15 FIGURE 2-16: vs. Temperature. 10 35 Temperature (°C) 60 85 Trip Current Limit Operation 5 2.9 4 VDD = 5V 2.8 VS = VDD = 5V 3 2.7 Accuracy (%) VS Threshold Voltage (V) -2 -10 3 2.6 Threshold 2.5 2.4 Hysteresis 2.3 2 1 0 -1 -2 2.2 -3 2.1 -4 2 -5 -40 -15 FIGURE 2-14: vs. Temperature. 10 35 Temperature (°C) 60 85 VS Undervoltage Threshold 0 0.5 1 FIGURE 2-17: Accuracy. 1.5 Current (A) 2 2.5 3 IBUS Measurement 800 5.5 5 4.5 4 3.5 3 2.5 2 1.5 1 0.5 0 700 VS = VDD = 5V S0 = '1' PWR_EN disabled 0 500 1000 1500 2000 2500 3000 3500 4000 Current (µA) FIGURE 2-15: Detect State VBUS vs. IBUS.  2014-2015 Microchip Technology Inc. Supply Current (µA) Voltage (V) VS = VDD = 5V ILIM = 3.0 A max. (2.85A typical) -1 IDD + IS 600 500 IS 400 300 IDD 200 100 VS = VDD = 5V 0 -40 FIGURE 2-18: Temperature. -15 10 35 Temperature (°C) 60 85 Active State Current vs. DS20005346B-page 19 UCS1003-1/2/3 Note: Unless otherwise indicated, VDD = VS = 5V, TA = +27°C. 250 40% 35% 200 IDD + IS 150 IDD 30% Samples (%) 100 25% 20% 15% 10% 5% 50 IS FIGURE 2-19: Temperature. 10 1.072 1.060 1.048 1.036 1.024 1.012 1.000 VBUS Current (A) Detect State Current vs. FIGURE 2-22: Distribution. ILIM2 Trip Current 30% 25% Samples (%) 8 IDD + IS 7 6 5 IDD 4 3 20% 15% 10% 5% 2 IS 1.170 1.180 1.190 1.425 1.440 1.160 1.150 1.140 1.130 85 1.410 FIGURE 2-20: Temperature. 60 1.120 10 35 Temperature (°C) 1.110 -15 1.100 -40 1.090 1.070 0 1.080 0% 1 VBUS Current (A) Sleep State Current vs. FIGURE 2-23: Distribution. 30% 35% 25% 30% 20% Samples (%) 15% 10% 5% ILIM3 Trip Current 25% 20% 15% 10% 5% VBUS Current (A) FIGURE 2-21: Distribution. DS20005346B-page 20 ILIM1 Trip Current 1.395 1.380 1.365 1.350 1.335 1.320 1.305 0% 1.290 0.606 0.600 0.594 0.588 0.582 0.576 0.570 0.564 0.558 0.552 0.546 0.540 0.534 0% 1.260 Samples (%) 0.988 85 VS = VDD = 5V 9 Sleep Current (µA) 60 0.976 10 35 Temperature (°C) 0.964 -15 0.952 -40 0.940 0.928 0% 0 1.275 Detect Current (µA) VS = VDD = 5V VBUS Current (A) FIGURE 2-24: Distribution. ILIM4 Trip Current  2014-2015 Microchip Technology Inc. UCS1003-1/2/3 Note: Unless otherwise indicated, VDD = VS = 5V, TA = +27°C. 30% 40% 35% 25% Samples (%) Samples (%) 30% 25% 20% 15% 20% 15% 10% 10% 5% 5% ILIM6 Trip Current 2.380 2.975 2.400 2.360 2.340 2.300 2.320 3.000 2.925 2.900 2.875 2.850 2.825 2.700 2.158 2.140 2.122 2.104 2.086 2.068 2.050 2.032 2.014 0% 1.996 0% 1.978 5% 1.960 5% 2.800 10% 2.775 10% 15% 2.750 15% 20% 2.725 20%  2014-2015 Microchip Technology Inc. 2.950 25% Samples (%) 25% VBUS Current (A) ILIM7 Trip Current FIGURE 2-27: Distribution. 30% 1.942 Samples (%) ILIM5 Trip Current 30% FIGURE 2-26: Distribution. 2.280 VBUS Current (A) VBUS Current (A) FIGURE 2-25: Distribution. 2.260 2.240 2.220 2.200 2.160 1.800 1.780 1.760 1.740 1.720 1.700 1.680 1.660 1.640 1.620 1.600 1.580 1.560 2.180 0% 0% VBUS Current (A) FIGURE 2-28: Distribution. ILIM8 Trip Current DS20005346B-page 21 UCS1003-1/2/3 NOTES: DS20005346B-page 22  2014-2015 Microchip Technology Inc.  2014-2015 Microchip Technology Inc. 3.0 PIN DESCRIPTION Descriptions of the pins are listed in Table 3-1. TABLE 3-1: PIN FUNCTION TABLE UCS1003-1/2/3 4x4 QFN Symbol 1 M1 Active Mode Selector Input #1. 2 M2 Active Mode Selector Input #2. 3 VBUS1 4 VBUS2 5 COMM_SEL/ILIM Function Voltage output from power switch. These pins are internally connected and must be tied together. COMM_SEL (UCS1003-1 only) – Selects SMBus or Stand-Alone mode of operation (see Table 11-1). Pin Type Connection Type if Pin Not Used DI Connect to ground or VDD (Note 3) DI Connect to ground or VDD (Note 3) Hi-Power (Note 1) Leave open AIO n/a AIO n/a ILIM – Selects the hardware current limit at power-up. 6 SEL Selects polarity of PWR_EN control, and in the UCS1003-1, the SMBus address (see Table 11-2). 7 VS1 Voltage input to power switch. These pins are internally connected and must be tied together. Hi-Power 8 VS2 9 VDD 10 PWR_EN Port power switch enable input. Polarity determined by SEL pin. DI 11 SMDATA/LATCH SMDATA (UCS1003-1 only) – SMBus data input/output (requires pull-up resistor). DIOD SMCLK/S0 Power LATCH – In Stand-Alone mode, latch/auto-recovery Fault handling mechanism selection input (see Section 7.5 “Fault Handling Mechanism”). DI SMCLK (UCS1003-1 only) – SMBus clock input (requires pull-up resistor). DI n/a Connect to ground or VDD (Note 3) n/a n/a S0 – In Stand-Alone mode, enables Attach/Removal Detection feature (see Section 5.3.6 “S0 Input”). DS20005346B-page 23 Note 1: 2: 3: Total leakage current from Pins 3 and 4 (VBUS) to ground must be less than 100 µA for proper Attach/Removal Detection operation. It is recommended to use 2 M pull-down resistors on the DPOUT and/or DMOUT pin if a portable device stimulus is expected when using the customer charger emulation profile with the high-speed data switch open. The 2 M value is based on BC1.1 impedance characteristics for Dedicated Charging Ports. To ensure operation, the PWR_EN pin must be enabled, as determined by the SEL pin decode, when it is not driven by an external device. Furthermore, one of the M1, M2 or EM_EN pins must be connected to VDD if all three are not driven from an external device. If the PWR_EN pin is disabled, or all of the M1, M2 and EM_EN pins are connected to ground, the UCS1003-1 will remain in the Sleep or Detect state unless activated via the SMBus (UCS1003-2 and UCS1003-3 will remain in Sleep or Detect state indefinitely). UCS1003-1/2/3 12 Main power supply input for chip functionality. Connect to ground PIN FUNCTION TABLE (CONTINUED) UCS1003-1/2/3 4x4 QFN Symbol Function 13 ALERT# Active-low error event output flag (requires pull-up resistor). OD Connect to ground 14 DPIN USB data input (plus). AIO Connect to ground or ground through a resistor 15 DMIN USB data input (minus). AIO Connect to ground or ground through a resistor 16 DMOUT USB data output (minus). AIO (Note 2) Connect to ground 17 DPOUT USB data output (plus). AIO (Note 2) Connect to ground OD Connect to ground Active-low “Charging Active” output flag (requires pull-up resistor). OD Connect to ground Active mode selector input. DI Connect to ground or VDD (Note 3) 18 A_DET# Active-low device Attach Detection output flag (UCS1003-1 and UCS1003-3) (requires pull-up resistor). CHRG# (UCS1003-2) 19 EM_EN 20 GND 21 EP Note 1: 2: 3: Ground. Exposed thermal pad. Must be connected to electrical ground. Pin Type Connection Type if Pin Not Used Power n/a EP n/a  2014-2015 Microchip Technology Inc. Total leakage current from Pins 3 and 4 (VBUS) to ground must be less than 100 µA for proper Attach/Removal Detection operation. It is recommended to use 2 M pull-down resistors on the DPOUT and/or DMOUT pin if a portable device stimulus is expected when using the customer charger emulation profile with the high-speed data switch open. The 2 M value is based on BC1.1 impedance characteristics for Dedicated Charging Ports. To ensure operation, the PWR_EN pin must be enabled, as determined by the SEL pin decode, when it is not driven by an external device. Furthermore, one of the M1, M2 or EM_EN pins must be connected to VDD if all three are not driven from an external device. If the PWR_EN pin is disabled, or all of the M1, M2 and EM_EN pins are connected to ground, the UCS1003-1 will remain in the Sleep or Detect state unless activated via the SMBus (UCS1003-2 and UCS1003-3 will remain in Sleep or Detect state indefinitely). UCS1003-1/2/3 DS20005346B-page 24 TABLE 3-1: UCS1003-1/2/3 TABLE 3-2: Pin Type Power Hi-Power PIN TYPES DESCRIPTION Description This pin is used to supply power or ground to the device. This pin is a high-current pin. AIO Analog Input/Output – This pin is used as an I/O for analog signals. DI Digital Input – This pin is used as a digital input. This pin will be glitch-free. DIOD Open-Drain Digital Input/Output – This pin is bidirectional. It is open-drain and requires a pull-up resistor. This pin will be glitch-free. OD Open-Drain Digital Output – Used as a digital output. It is open-drain and requires a pull-up resistor. This pin will be glitch-free. EP Exposed Thermal Pad.  2014-2015 Microchip Technology Inc. DS20005346B-page 25 UCS1003-1/2/3 NOTES: DS20005346B-page 26  2014-2015 Microchip Technology Inc. UCS1003-1/2/3 4.0 TERMS AND ABBREVIATIONS Note: In the case of UCS1003-1, the M1, M2, PWR_EN and EM_EN pins each have Configuration bits (_SET in Section 10.4.3 “Switch Configuration Register”) that may be used to perform the same function as the external pin state. These bits are accessed via the SMBus/I2C and are OR’d with the respective pin. This OR’d combination of pin state and register bit is referenced as the control. TABLE 4-1: TERMS AND ABBREVIATIONS Term/Abbreviation Description Active Mode Active Power State Operation mode: Data Pass-Through, BC1.2 SDP, BC1.2 CDP, BC1.2 DCP or Dedicated Charger Emulation Cycle mode. Attach Detection An Attach Detection event occurs when the current drawn by a portable device is greater than IDET_QUAL for longer than tDET_QUAL. Attachment The physical insertion of a portable device into a USB port that UCS1003-1/2/3 is controlling. CC Constant Current. CDM Charged Device Model. JEDEC model for characterizing susceptibility of a device to damage from ESD. CDP or USB-IF BC1.2 CDP Charging Downstream Port. The combination of the UCS1003-1/2/3 CDP handshake and an active standard USB host comprises a CDP. This enables a BC1.2 compliant portable device to simultaneously draw current up to 1.5A while data communication is active. The USB high-speed data switch is closed in this mode. Charge Enable When a charger emulation profile has been accepted by a portable device and charging commences. Charger Emulation Profile Representation of a charger comprised of DPOUT, DMOUT and VBUS signaling, which make up a defined set of signatures or handshaking protocols. Connection USB-IF term which refers to establishing active USB communications between a USB host and a USB device. Current-Limiting Mode Determines the action that is performed when the IBUS current reaches the ILIM threshold. Trip opens the port power switch. Constant Current (variable slope) allows VBUS to be dropped by the portable device. DCE Dedicated Charger Emulation. Charger emulation in which the UCS1003-1/2/3 can deliver power only (by default). No active USB data communication is possible when charging in this mode (by default). DCP or USB-IF BC1.2 DCP Dedicated Charging Port. This functions as a dedicated charger for a BC1.2 portable device. This allows the portable device to draw currents up to 1.5A with Constant-Current Limiting (and beyond 1.5A with trip current limiting). No USB communications are possible (by default). DC Dedicated Charger. A charger which inherently does not have USB communications, such as an A/C wall adapter. Disconnection USB-IF term which refers to the loss of active USB communications between a USB host and a USB device. Dynamic Thermal Management The UCS1003-1/2/3 automatically adjusts port power switch limits and modes to lower internal power dissipation when the thermal regulation temperature value is approached. Enumeration A USB-specific term indicating that a host is detecting and identifying USB devices. Handshake Application of a charger emulation profile that requires a response. Two-way communication between the UCS1003-1/2/3 and the portable device. HBM Human Body Model. HSW High-Speed Switch. IBUS_R2MIN Current Limiter mode boundary.  2014-2015 Microchip Technology Inc. DS20005346B-page 27 UCS1003-1/2/3 TABLE 4-1: TERMS AND ABBREVIATIONS (CONTINUED) Term/Abbreviation Description ILIM The IBUS current threshold used in current limiting. In Trip mode, when ILIM is reached, the port power switch is opened. In Constant-Current mode, when the current exceeds ILIM, operation continues at a reduced voltage and increased current; if VBUS voltage drops below VBUS_MIN, the port power switch is opened. Legacy USB devices that require non-BC1.2 signatures to be applied on the DPOUT and DMOUT pins to enable charging. OCL Overcurrent Limit. POR Power-on Reset. Portable Device USB device attached to the USB port. Power Thief A USB device that does not follow the handshaking conventions of a BC1.2 device or legacy devices and draws current immediately upon receiving power (i.e., a USB book light, portable fan, etc). Removal Detection A Removal Detection event occurs when the current load on the VBUS pin drops to less than IREM_QUAL for longer than tREM_QUAL. Removal The physical removal of a portable device from a USB port that the UCS1003-1/2/3 is controlling. Response An action, usually in response to a stimulus, in charger emulation performed by the UCS1003-1/2/3 device via the USB data lines. SDP or USB-IF SDP Standard Downstream Port. The combination of the UCS1003-1/2/3 High-Speed Switch being closed with an upstream USB host present comprises a BC1.2 SDP. This enables a BC1.2 compliant portable device to simultaneously draw current up to 0.5A while data communication is active. Signature Application of a charger emulation profile without waiting for a response. One-way communication from the UCS1003-1/2/3 to the portable device. Stand-Alone Mode Indicates that the communication protocol is not active and all communications between the UCS1003-1/2/3 and a controller are done via the external pins only (M1, M2, EM_EN, PWR_EN, S0 and LATCH as inputs, and ALERT# and A_DET# as outputs). Stimulus An event in charger emulation detected by the UCS1003-1/2/3 device via the USB data lines. DS20005346B-page 28  2014-2015 Microchip Technology Inc. UCS1003-1/2/3 5.0 The UCS1003-1 also provides current monitoring to allow intelligent management of system power and charge rationing for controlled delivery of current, regardless of the host power state. This is especially important for battery-operated applications that need to provide power without excessively draining the battery or that require power allocation depending on application activities. GENERAL DESCRIPTION The UCS1003-1/2/3 family of devices provides a single USB port power switch for precise control of up to 3.0A continuous current with Overcurrent Limit (OCL), dynamic thermal management, latch or auto-recovery Fault handling, selectable active-high or active-low enable, Undervoltage and Overvoltage Lockout, and back-voltage protection. Figure 5-1 shows a UCS1003-1 full-featured system configuration in which the UCS1003-1 provides a port power switch and low-power Attach Detection with wake-up signaling (wake on USB). The current limit is established at power-up. It can be lowered, if required, after power-up via the SMBus/I2C. This configuration also provides configurable USB data line charger emulation, programmable current limiting (as determined by the accepted charger emulation profile), active current monitoring and port charge rationing. Split supply support for VBUS and VDD is an option for low power in system standby states. In addition to power switching and current limiting, the UCS1003-1/2/3 provides charger emulation profiles to charge a wide variety of portable devices, including USB-IF BC1.2 (CDP or DCP modes), YD/T-1591 (2009), 12W charging, most Apple, Samsung and RIM portable devices, and many others (refer to Section 9.0 “Active State” for more information on preloaded charger emulation profiles). The UCS1003-1 has a custom programmable charger emulation profile for portable device support for fully host controlled charger emulation. USB Host 5V Host CIN DPIN DPOUT DMIN DMOUT VS1 VBUS1 VS2 VBUS2 5V UCS1003-1 Device CBUS VDD 3V-5.5V EM_EN 3V-5.5V M1 M2 PWR_EN VDD SMDATA A_DET# SMCLK ALERT# SEL VDD COMM_SEL/ILIM GND FIGURE 5-1: USB Host). UCS1003-1 System Configuration (with Charger Emulation, SMBus Control and  2014-2015 Microchip Technology Inc. DS20005346B-page 29 UCS1003-1/2/3 Figure 5-2 shows a system configuration in which the UCS1003-1/2/3 devices provide a USB data switch, port power switch, low-power Attach Detection and portable device Attach/Removal Detection signaling. This configuration does not include configurable data line charger emulation, programmable current limiting or current monitoring and rationing. 5V VDD DPIN USB Host 5V Host CIN DPOUT DMIN DMOUT VS1 VBUS1 VS2 VBUS2 UCS1003-X Device CBUS EM_EN 3V-5.5V Enable Detect State Latch Upon Fault M1 3V-5.5V M2 PWR_EN LATCH S0 A_DET#/CHRG# ALERT# VDD Disable Detect State Auto-Recovery Upon Fault SEL COMM_SEL/ILIM GND FIGURE 5-2: USB Host). DS20005346B-page 30 UCS1003-1/2/3 System Configuration (Charger Emulation, No SMBus and with  2014-2015 Microchip Technology Inc. UCS1003-1/2/3 Figure 5-3 shows a system configuration in which the UCS1003-1/2/3 devices provide a port power switch, low-power Attach Detection and portable device Attachment Detection signaling. This configuration is useful for applications that already provide USB BC1.2 and/or legacy data line handshaking on the USB data lines, but still require port power switching and current limiting. 5V Host CIN DPOUT DMIN DMOUT VS1 VBUS1 VS2 VBUS2 USB Host (DP, DM) Device CBUS EM_EN UCS1003-X M1 3V-5.5V Latch Upon Fault Enable Detect State DPIN M2 PWR_EN SEL 3V-5.5V LATCH S0 VDD COMM_SEL/ILIM Disable Detect State Auto-Recovery Upon Fault 5V VDD GND FIGURE 5-3: A_DET#/CHRG# ALERT# UCS1003-1/2/3 System Configuration (No SMBus, No Charger Emulation).  2014-2015 Microchip Technology Inc. DS20005346B-page 31 UCS1003-1/2/3 Figure 5-4 shows a system configuration in which the UCS1003-1/2/3 devices provide a port power switch, low-power Attach Detection, charger emulation (with no USB host) and portable device Attachment Detection signaling. This configuration is useful for wall adapter-type applications. 15 k DPIN DPOUT DMIN DMOUT 5V VS1 VBUS1 CIN VS2 VBUS2 15 k Device CBUS EM_EN M1 UCS1003-X 3V-5.5V Enable Detect State M2 Latch Upon Fault PWR_EN SEL 3V-5.5V LATCH S0 VDD COMM_SEL/ILIM Disable Detect State Auto-Recovery Upon Fault 5V VDD GND A_DET#/CHRG# ALERT# FIGURE 5-4: UCS1003-1/2/3 System Configuration (No SMBus, No USB Host and with Charger Emulation). DS20005346B-page 32  2014-2015 Microchip Technology Inc. UCS1003-1/2/3 5.1 UCS1003-1/2/3 Power States The UCS1003-1/2/3 has the following power states listed in Table 5-1. TABLE 5-1: POWER STATES DESCRIPTION State Description Off This power state is entered when the voltage at the VDD pin voltage is < VDD_TH. In this state, the device is considered “off”. The UCS1003-1/2/3 devices will not retain their digital states. UCS1003-1 will not retain register contents, nor respond to SMBus/I2C communications. The port power switch, bypass switch and the high-speed data switches will be off. See Section 5.1.1 “OFF State Operation”. Sleep This is the lowest power state available. While in this state, the UCS1003-1/2/3 devices will retain digital functionality and respond to changes in emulation controls. UCS1003-1 will wake to respond to SMBus/I2C communications. The high-speed switch and all other functionality will be disabled. See Section 5.1.2 “Sleep State Operation”. Detect This is a low-current power state. In this state, the device is actively looking for a portable device to be attached. The high-speed switch is disabled by default. While in this state, the UCS1003-1 will retain the configuration and charge rationing data, but it will not monitor the bus current. SMBus/I2C communications will be fully functional. See Section 5.1.3 “Detect State Operation”. Error This power state is entered when a Fault condition exists. See Section 5.1.5 “Error State Operation”. Active This power state provides full functionality. While in this state, operations include activation of the port power switch, USB data line handshaking/charger emulation, current limiting and charge rationing. See Section 5.1.4 “Active State Operation”.  2014-2015 Microchip Technology Inc. DS20005346B-page 33 UCS1003-1/2/3 Table 5-2 shows the settings for the various power states, except for the OFF and Error states. If VDD < VDD_TH, the UCS1003-1/2/3 devices are in the OFF state. To determine the mode of operation in the Active state, see Table 9-1. Using configurations not listed in Table 5-2 are not recommended and may produce undesirable results. Note: TABLE 5-2: POWER STATE CONTROL SETTINGS M1, M2, EM_EN Portable Device Attached Power State VS PWR_EN S0 Sleep N/A Disabled 0 Not set to Data Pass-Through mode (Note 1) N/A N/A Enabled 0 All = 0b N/A Detect N/A (see Section 8.0 < V S_UVLO “Detect State”) Disabled 1 N/A N/A Enabled 1 All  0b N/A > VS_UVLO Enabled 1 All  0b No • High-speed switch disabled (by default) • Automatic transition to Active state when conditions met (see Section 5.1.3.1 “Automatic Transition from Detect to Active”) Active > VS_UVLO (see Section 9.0 “Active State”) Enabled 0 All  0b N/A • High-speed switch enabled/ disabled based on mode • Port power switch is on at all times • Attach and Removal Detection disabled (Note 2) > VS_UVLO Enabled 1 All  0b Yes • Port power switch is on • Removal Detection enabled Note 1: 2: Behavior • All switches disabled • VBUS will be near ground potential • The UCS1003-1 wakes to respond to SMBus communications • High-speed switch disabled (by default) • Port power switch disabled • Host-controlled transition to Active state (see Section 5.1.3.2 “Host-Controlled Transition from Detect to Active”) In order to transition from Active State Data Pass-Through mode into Sleep with these settings, change the M1, M2 and EM_EN pins before changing the PWR_EN pin. See Section 9.4 “Data Pass-Through (No Charger Emulation)”. If S0 = 0 and a portable device is not attached in DCE Cycle mode, the UCS1003-1/2/3 devices will be cycling through charger emulation profiles (by default). There is no assurance which charger emulation profile will be applied first when a portable device attaches. DS20005346B-page 34  2014-2015 Microchip Technology Inc. UCS1003-1/2/3 5.1.1 OFF STATE OPERATION The first data byte read from the UCS1003-1, when in the Sleep state, will wake the device; however, the data to be read will return all ‘0’s and should be considered invalid. This is a “dummy” read byte meant to wake the UCS1003-1. Subsequent read or write bytes will be accepted normally. After the dummy read, the UCS1003-1 will be in a higher power state (see Figure 5-6). The device will return to Sleep after the last communication or if no further communication has occurred. The device is in the OFF state if VDD is less than VDD_TH. When the UCS1003-1/2/3 devices are in the OFF state, it does nothing and all circuitry is disabled. In the case of UCS1003-1, the digital register values are not stored and the device will not respond to SMBus commands. 5.1.2 SLEEP STATE OPERATION When the UCS1003-1/2/3 devices are in the Sleep state, the device is in its lowest power state. The highspeed switch, bypass switch and the port power switch are disabled. The Attach and Removal Detection feature is disabled. VBUS will be near ground potential. The ALERT# pin is not asserted. If asserted prior to entering the Sleep state, the ALERT# pin will be released. The A_DET# pin is released. In the case of UCS1003-1, SMBus activity is limited to single byte read or write. Figure 5-5 shows the timing diagrams for waking the UCS1003-1/2/3 family via external pins. Figure 5-6 shows the timing for waking the UCS1003-1 device via SMBus. Wake with M1 or M2 to Active State Data Pass-Through Mode (PWR_EN enabled, S0 = 0, EM_EN = 0, VS > VS_UVLO) M1 or M2 tPIN_WAKE Port Power Switch Closed (Active state) Wake with S0 (VS > VS_UVLO, M1 & M2 & EM_EN not all ‘0’s and not set to data pass-through) S0 tPIN_WAKE Bypass Switch Closed (Detect state) FIGURE 5-5: Wake Timing via External Pins. SMBus Read Dummy Read Returns Invalid Data and Places Device in Temporary Active State S 0101_1110 A 0001_0000 A S 0101_1111 A invalid data Read Returns Valid Data NP S 0101_1110 A 0001_0000 A S 0101_1111 A valid data N P tSMB_WAKE Power State FIGURE 5-6: Temporary Active State (not all functionality available) Sleep tIDLE_SLEEP Sleep Wake via SMBus Read with S0 = 0.  2014-2015 Microchip Technology Inc. DS20005346B-page 35 UCS1003-1/2/3 5.1.3 DETECT STATE OPERATION When the UCS1003-1/2/3 is in the Detect state, the port power switch will be disabled. The high-speed switch is also disabled by default. The VBUS output will be connected to the VDD voltage by a secondary bypass switch (see Section 8.0 “Detect State”). 5.1.3.3 When conditions cause the UCS1003-1/2/3 to transition from the Detect state to the Active state, the following occurs: 1. The Attach Detection feature will be disabled; the Removal Detection feature remains enabled unless S0 is changed to ‘0’. The bypass switch will be turned off. The discharge switch will be turned on briefly for tDISCHARGE. The port power switch will be turned on. There is one non-recommended configuration which places the UCS1003-1/2/3 in the Detect state, but VBUS will not be discharged and a portable device attachment will not be detected. For the recommended configurations, see Table 5-2. 2. 3. There are two methods for transitioning from the Detect state to the Active state: automatic and host-controlled. 5.1.4 5.1.3.1 Automatic Transition from Detect to Active For the Detect state, set S0 to ‘1’, enable PWR_EN, set the EM_EN, M1 and M2 controls to the desired Active mode (Table 9-1), and supply VS > VS_UVLO. When a portable device is attached and an Attach Detection event occurs, the UCS1003-1/2/3 will automatically transition to the Active state and operate according to the selected Active mode. 5.1.3.2 Host-Controlled Transition from Detect to Active For the Detect state, set S0 to ‘1’, set the EM_EN, M1 and M2 controls to the desired Active mode (Table 9-1), and configure one of the following: • Disable PWR_EN and supply VS OR • Enable PWR_EN and don’t supply VS; when a portable device is attached and an Attach Detection event occurs, the host must respond to transition to the Active state. Depending on the control settings in the Detect state, this could entail: • Enabling PWR_EN OR • Supplying VS above the threshold. Note: If S0 is ‘1’, PWR_EN is enabled and VS is not present, the A_DET# pin will cycle if the current draw exceeds the current capacity of the bypass switch. State Change from Detect to Active 4. ACTIVE STATE OPERATION Every time that the UCS1003-1/2/3 enters the Active state and the port power switch is closed, it will enter the mode as instructed by the host controller (see Section 9.0 “Active State”). The UCS1003-1/2/3 cannot be in the Active state (and therefore, the port power switch cannot be turned on) if any of the following conditions exist: • • • • VS < VS_UVLO PWR_EN is disabled M1, M2 and EM_EN are all set to ‘0’ S0 is set to ‘1’ and an Attach Detection event has not occurred 5.1.5 ERROR STATE OPERATION The UCS1003-1/2/3 will enter the Error state from the Active state when any of the following events are detected: • The maximum allowable internal die temperature (TTSD) has been exceeded (see Section 7.2.1.2 “Thermal Shutdown”). • An overcurrent condition has been detected (see Section 7.1.1 “Current Limit Setting”). • An undervoltage condition on VBUS has been detected (see Section 5.2.5 “Undervoltage Lockout on VS”). • A backdrive condition has been detected (see Section 5.2.3 “Back-Voltage Detection”). • A discharge error has been detected (see Section 7.3 “VBUS Discharge”). • An overvoltage condition on the VS pins. The UCS1003-1/2/3 will enter the Error state from the Detect state when a backdrive condition has been detected or when the maximum allowable internal die temperature has been exceeded. The UCS1003-1/2/3 will enter the Error state from the Sleep state when a backdrive condition has been detected. DS20005346B-page 36  2014-2015 Microchip Technology Inc. UCS1003-1/2/3 When the UCS1003-1/2/3 enters the Error state, the port power switch, VBUS bypass switch and the highspeed switch are turned off, and the ALERT# pin is asserted (by default). They will remain off while in this power state. The UCS1003-1/2/3 will leave this state as determined by the Fault handling selection (see Section 7.5 “Fault Handling Mechanism”). When using the latch Fault handler and the user has reactivated the device by clearing the ERR bit (for UCS1003-1 only, see Section 10.3 “Status Registers”) or toggling the PWR_EN control, the UCS1003-1/2/3 will check that all of the error conditions have been removed. If using the auto-recovery Fault handler, after the tCYCLE time period, the UCS1003-1/2/3 will check that all of the error conditions have been removed. If all of the error conditions have been removed, the UCS1003-1/2/3 will return to the Active state or Detect state, as applicable. Returning to the Active state will cause the UCS1003-1/2/3 to restart the selected mode (see Section 9.2 “Active Mode Selection”). If the device is in the Error state and a Removal Detection event occurs, it will check the error conditions and then return to the power state defined by the PWR_EN, M1, M2, EM_EN and S0 controls. 5.2 5.2.1 Supply Voltages VDD SUPPLY VOLTAGE The UCS1003-1/2/3 family requires 4.5V to 5.5V to be present on the VDD pin for core device functionality. Core device functionality consists of maintaining register states, wake-up upon SMBus/I2C query and Attach Detection. 5.2.2 VS SOURCE VOLTAGE VS can be a separate supply and can be greater than VDD to accommodate high-current applications in which current path resistances result in unacceptable voltage drops that may prevent optimal charging of some portable devices.  2014-2015 Microchip Technology Inc. 5.2.3 BACK-VOLTAGE DETECTION Whenever the following conditions are true, the port power switch will be disabled, the VBUS bypass switch will be disabled, the high-speed data switch will be disabled and a back-voltage event will be flagged. This will cause the UCS1003-1/2/3 to enter the Error power state (see Section 5.1.5 “Error State Operation”). • The VBUS voltage exceeds the VS voltage by VBV_TH and the port power switch is closed. The port power switch will be opened immediately. If the condition lasts for longer than tMASK, then the UCS1003-1/2/3 will enter the Error state. Otherwise, the port power switch will be turned on as soon as the condition is removed. • The VBUS voltage exceeds the VDD voltage by VBV_TH and the VBUS bypass switch is closed. The bypass switch will be opened immediately. If the condition lasts for longer than tMASK, then the UCS1003-1/2/3 will enter the Error state. Otherwise, the bypass switch will be turned on as soon as the condition is removed. 5.2.4 BACKDRIVE CURRENT PROTECTION If a self-powered portable device is attached, it may drive the VBUS port to its power supply voltage level; however, the UCS1003-1/2/3 family is designed such that leakage current from the VBUS pins to the VDD or VS pins shall not exceed IBD_1 (if the VDD voltage is zero), or IBD_2 (if the VDD voltage exceeds VDD_TH). 5.2.5 UNDERVOLTAGE LOCKOUT ON VS The UCS1003-1/2/3 family requires a minimum voltage (VS_UVLO) be present on the VS pin for the Active power state. 5.2.6 OVERVOLTAGE DETECTION AND LOCKOUT ON VS The UCS1003-1/2/3 port power switch will be disabled if the voltage on the VS pin exceeds a voltage (VS_OV) for longer than the specified time (tMASK). This will cause the device to enter the Error state. DS20005346B-page 37 UCS1003-1/2/3 5.3 Note: 5.3.1 Discrete Input Pins If it is necessary to connect any of the control pins, except the COMM_SEL/ILIM or SEL pins, via a resistor to VDD or GND, the resistor value should not exceed 100 k in order to meet the VIH and VIL specifications. COMM_SEL/ILIM INPUT The COMM_SEL/ILIM input determines the initial ILIM settings and the Communications mode, as shown in Table 11-1. 5.3.2 SEL INPUT The SEL pin selects the polarity of the PWR_EN control. If the SEL pin is high, the PWR_EN control is active-high enable. If the SEL pin is low, the PWR_EN control is active-low enable. In addition, if the UCS1003-1 is not configured to operate in Stand-Alone mode, the SEL pin determines the SMBus address. See Table 11-2. The SEL pin state is latched upon device power-up and further changes will have no effect. 5.3.3 M1, M2 AND EM_EN INPUTS The M1, M2 and EM_EN input controls determine the Active mode and affect the power state (see Table 5-2 and Table 9-1). When these controls are all set to ‘0’ and PWR_EN is enabled, the UCS1003-1/2/3 Attach and Removal Detection feature is disabled. In case of the UCS1003-1 configured in SMBus mode, the M1, M2 and EM_EN pin states will be ignored by the UCS1003-1 if the PIN_IGN Configuration bit is set (see Section 10.4.3 “Switch Configuration Register”); otherwise, the M1_SET, M2_SET and EM_EN_SET Configuration bits (see Section 10.4.3 “Switch Configuration Register”) are checked along with the pins. DS20005346B-page 38 5.3.4 PWR_EN INPUT The PWR_EN control enables the port power switch to be turned on if conditions are met and affects the power state (see Table 5-2). The port power switch cannot be closed if PWR_EN is disabled. However, if PWR_EN is enabled, the port power switch is not necessarily closed (see Section 5.1.4 “Active State Operation”). Polarity is controlled by the SEL pin. In the case of the UCS1003-1 configured in SMBus mode, the PWR_EN pin state will be ignored by the UCS1003-1 if the PIN_IGN Configuration bit is set (see Section 10.4.3 “Switch Configuration Register”); otherwise, the PWR_ENS Configuration bit (see Section 10.4.3 “Switch Configuration Register”) is checked along with the pin. 5.3.5 LATCH INPUT The latch input control determines the behavior of the Fault handling mechanism (see Section 7.5 “Fault Handling Mechanism”). When the UCS1003-1 is configured to operate in Stand-Alone mode (see Section 11.3 “Stand-Alone Operating Mode”), the latch control is available exclusively via the LATCH pin (see Table 11-10). When the UCS1003-1 is configured to operate in SMBus mode, the latch control is available exclusively via the LATCHS Configuration bit (see Section 10.4.3 “Switch Configuration Register”). 5.3.6 S0 INPUT The S0 control enables the Attach and Removal Detection feature, and affects the power state (see Table 5-2). When S0 is set to ‘1’, an Attach Detection event must occur before the port power switch can be turned on. When S0 is set to ‘0’, the Attach and Removal Detection feature is not enabled. When the UCS1003-1 is configured to operate in SMBus mode (see Section 11.3 “Stand-Alone Operating Mode”), the S0 control is available exclusively via the S0_SET Configuration bit (see Section 10.4.3 “Switch Configuration Register”). Otherwise, the S0 control is available exclusively via the S0 pin since the SMBus protocol will be disabled.  2014-2015 Microchip Technology Inc. UCS1003-1/2/3 5.4 5.4.1 Discrete Output Pins ALERT# AND A_DET# OUTPUT PINS The ALERT# pin is an active-low, open-drain interrupt to the host controller. The ALERT# pin is asserted (by default – see ALERT_MASK in Section 10.4.1 “General Configuration Register”) when an error occurs (see Register 10-3). In the case of UCS1003-1, the ALERT# pin can also be asserted when the LOW_CUR (portable device is pulling less current and may be finished charging) or TREG (thermal regulation temperature exceeded) bits are set and linked. Also, when charge rationing is enabled in UCS1003-1, the ALERT# pin is asserted by default when the current rationing threshold is reached (as determined by RATION_BEH – see Table 7-2). The ALERT# pin is released when all error conditions that may assert the ALERT# pin (such as an error condition, charge rationing, and TREG and LOW_CHG if linked) have been removed or reset as necessary. The CHRG# pin (UCS1003-2) provides an active-low, open-drain output indication that charging of an attached device is active. It will remain asserted until this condition no longer exists and then will be automatically released. 5.4.2 INTERRUPT BLANKING The ALERT#, A_DET# (UCS1003-1 and UCS1003-3) and CHRG# (UCS1003-2) pins will not be asserted for a specified time (up to tBLANK) after power-up. Additionally, an error condition (except for the thermal shutdown) must be present for longer than a specified time (tMASK) before the ALERT# pin is asserted. The A_DET# pin (UCS1003-1, UCS1003-3) provides an active-low, open-drain output indication that a valid Attach Detection event has occurred. It will remain asserted until the UCS1003-1 or UCS1003-3 is placed into the Sleep state, or a Removal Detection event occurs. For wake on USB, the A_DET# pin assertion can be utilized by the system. If the S0 control is ‘0’ and the UCS1003-1 or UCS1003-3 is in the Active state, the A_DET# pin will be asserted regardless if a portable device is attached or not. If S0 is ‘1’, PWR_EN is enabled and VS is not present; the A_DET# pin will cycle if the current draw exceeds the current capacity of the bypass switch.  2014-2015 Microchip Technology Inc. DS20005346B-page 39 UCS1003-1/2/3 NOTES: DS20005346B-page 40  2014-2015 Microchip Technology Inc. UCS1003-1/2/3 6.0 USB HIGH-SPEED DATA SWITCH The UCS1003-1/2/3 family contains a series USB 2.0 compliant, high-speed switch between the DPIN and DMIN pins, and between the DPOUT and DMOUT pins. This switch is designed for high-speed, low-latency functionality to allow USB 2.0 full-speed and high-speed communications with minimal interference. Note: 6.1 If the VDD voltage is less than VDD_TH, the high-speed data switch will be disabled and opened. USB-IF High-Speed Compliance The USB data switch will not significantly degrade the signal integrity through the device DP/DM pins with USB high-speed communications. Nominally, the switch is closed in the Active state, allowing uninterrupted USB communications between the upstream host and the portable device. The switch is opened when: • The UCS1003-1/2/3 family is actively emulating, using any of the charger emulation profiles except CDP (by default – see Section 10.4.5 “High-Speed Switch Configuration Register”) • The UCS1003-1/2/3 family is operating as a dedicated charger unless the HSW_DCE Configuration bit is set (see Section 10.4.5 “High-Speed Switch Configuration Register”) • The UCS1003-1/2/3 family is in the Detect state (by default) or in the Sleep state  2014-2015 Microchip Technology Inc. DS20005346B-page 41 UCS1003-1/2/3 NOTES: DS20005346B-page 42  2014-2015 Microchip Technology Inc. UCS1003-1/2/3 7.0 USB PORT POWER SWITCH 7.1.2 SHORT-CIRCUIT OUTPUT CURRENT LIMITING To ensure compliance to various charging specifications, the UCS1003-1/2/3 family contains a USB port power switch that supports two Current-Limiting modes: Trip and Constant-Current (variable slope) modes. The Current-Limit mode (ILIM) is pin-selectable (and may be updated via the register set). The switch also includes soft-start circuitry and a separate short-circuit current limit. Short-circuit current limiting occurs when the output current is above the selectable current limit (ILIMx). This event will be detected and the current will immediately be limited (within tSHORT_LIM time). If the condition remains, the port power switch will flag an error condition and enter the Error state (see Section 5.1.5 “Error State Operation”). The port power switch is on in the Active state (except when VBUS is discharging). 7.1.3 7.1 Current Limiting 7.1.1 CURRENT LIMIT SETTING The UCS1003-1/2/3 hardware set current limit (ILIM) can be one of eight values (see Table 11-1, which applies to UCS1003-1, and Table 7-1, which applies to UCS1003-2 and UCS1003-3). This resistor value is read once upon the UCS1003-1/2/3 devices’ power-up. TABLE 7-1: UCS1003-2 AND UCS1003-3 ILIM SELECTION(1,2) SOFT START When the PWR_EN control changes states to enable the port power switch, or an Attach Detection event occurs in the Detect power state and the PWR_EN control is already enabled, the UCS1003-1/2/3 family invokes a soft-start routine for the duration of the VBUS rise time (tR_BUS). This soft-start routine will limit current flow from VS into VBUS while it is active. This circuitry will prevent current spikes due to a step in the portable device current draw. In the case when a portable device is attached while the PWR_EN pin is already enabled, if the bus current exceeds ILIM, the UCS1003-1/2/3 current limiter will respond within a specified time (tSHORT_LIM) and will operate normally at this point. The CBUS capacitor will deliver the extra current, if any, as required by the load change. ILIM Resistor ±5% ILIM Setting 47 k Pull-Down 570 mA 56 k Pull-Down 1000 mA 7.1.4 68 k Pull-Down 1130 mA The UCS1003-1/2/3 current limiting has two modes: Trip and Constant-Current (variable slope) modes. Either mode functions at all times when the port power switch is closed. The Current-Limiting mode used depends on the Active state mode (see Section 9.9 “Current Limit Mode Associations”). When operating in the Detect power state (see Section 5.1.3 “Detect State Operation”), the current capacity at VBUS is limited to IBUS_BYP, as described in Section 8.2 “VBUS Bypass Switch”. 82 k Pull-Down 1350 mA 100 k Pull-Down 1680 mA 120 k Pull-Down 2050 mA 150 k Pull-Down 2280 mA VDD (if a pull-up resistor is used, its value must not exceed 100 k) 2850 mA (3000 mA maximum) Note 1: 2: Unless otherwise indicated, the values specified above are the typical ILIM in Table 1-2. ILIM pull-down resistors with values less than 33 k, connected to UCS1003-2 or UCS1003-3, will cause unexpected behavior. In the case of UCS1003-1, the current limit can be changed via the SMBus/I2C after power-up; however, the programmed current limit cannot exceed the hardware set current limit. At power-up, the hardware current limit (ILIM) and Communication mode, in the case of UCS1003-1 (StandAlone or SMBus/I2C), are determined via the pull-down resistor (or pull-up resistor if connected to VDD) on the COMM_SEL/ILIM pin, as shown in Table 11-1.  2014-2015 Microchip Technology Inc. 7.1.4.1 CURRENT-LIMITING MODES Trip Mode When using Trip Current-Limiting mode, the UCS1003-1/2/3 USB port power switch functions as a low-resistance switch and rapidly turns off if the current limit is exceeded. While operating using Trip CurrentLimiting mode, the VBUS output voltage will be held relatively constant (equal to the VS voltage minus the RON x IBUS current) for all current values up to the ILIM. If the current drawn by a portable device exceeds ILIM, the following occurs: 1. 2. 3. The port power switch will be turned off (Trip mode action). The UCS1003-1/2/3 will enter the Error state and assert the ALERT# pin. The Fault handling circuitry will then determine subsequent actions. DS20005346B-page 43 UCS1003-1/2/3 Trip Current-Limiting mode is used by default when the UCS1003-1/2/3 family is in Data Pass-Through and Dedicated Charger Emulation Cycle mode (except when the BC1.2 DCP charger emulation profile is accepted), and when there’s no handshake. This method is also used when charger emulation is active. Note: 7.1.4.2 To avoid cycling in Trip mode, set ILIM higher than the highest expected portable device current draw. In CC mode, the port power switch allows the attached portable device to reduce VBUS output voltage to less than the input VS voltage, while maintaining current delivery. The V/I slope depends on the user set ILIM value. This slope is held constant for a given ILIM value. 7.2.1 Thermal Management and Voltage Protection THERMAL MANAGEMENT The UCS1003-1/2/3 family utilizes two-stage internal thermal management. The first is named Dynamic Thermal Management and the second is a Fixed Thermal Shutdown. 7.2.1.1 2: The UCS1003-1/2/3 will not actively discharge VBUS as a result of the temperature exceeding TREG; however, any load current provided by a portable device or other load will cause VBUS to be discharged when the port power switch is opened, possibly resulting in an attached portable device resetting. Constant-Current Limiting (Variable Slope) Constant-Current Limiting is used when a portable device handshakes using the BC1.2 DCP charger emulation profile and the current drawn is greater than ILIM (and ILIM < 1.68A). It is also used in BC1.2 CDP mode and during the DCE Cycle when a charger emulation profile is being applied, and the emulation time-out is active. 7.2 Note 1: If the temperature exceeds the TREG threshold while operating in the DCE Cycle mode, after a charger emulation profile has been accepted, the profile will be removed. The UCS1003-1/2/3 will not restart the DCE Cycle mode until one of the control inputs changes states to restart emulation. If the UCS1003-1/2/3 is operating using ConstantCurrent Limiting (variable slope) and the ILIM setting has been reduced to its minimum set point, and the temperature is still above TREG, the UCS1003-1/2/3 will switch to operating using Trip Current-Limiting mode. This will be done by reducing the IBUS_R2MIN setting to 120 mA and restoring the ILIM setting to the value immediately below the programmed setting (e.g., if the programmed ILIM is 2.05A, the value will be set to 1.68A). If the temperature continues to remain above TREG, the UCS1003-1/2/3 will continue this cycle (open the port power switch and reduce the ILIM setting by one step). If the UCS1003-1/2/3 internal temperature drops below TREG – TREG_HYST, the UCS1003-1/2/3 will take action based on the following: 1. Dynamic Thermal Management For the first stage (active in both Current-Limiting modes), referred to as Dynamic Thermal Management, the UCS1003-1/2/3 devices automatically adjust port power switch limits and modes to lower power dissipation when the thermal regulation temperature value is approached, as described below. If the internal temperature exceeds the TREG value, the port power switch is opened, the current limit (ILIM) is lowered by one step and a timer is started (tDC_TEMP). When this timer expires, the port power switch is closed and the internal temperature is checked again. If it remains above the TREG threshold, the UCS1003-1/2/3 devices repeat this cycle (open port power switch and reduce the ILIM setting by one step) until ILIM reaches its minimum value. 2. If the Current Limit mode changed from CC mode to Trip mode, then a timer is started. When this timer expires, the UCS1003-1/2/3 will reset the port power switch operation to its original configuration, allowing it to operate using Constant-Current Limiting (variable slope). If the Current Limit mode did not change from CC mode to Trip mode, or was already operating in Trip mode, the UCS1003-1/2/3 will reset the port power switch operation to its original configuration. If the UCS1003-1/2/3 family is operating using Trip Current-Limiting mode and the ILIM setting has been reduced to its minimum set point, and the temperature is above TREG, the port power switch will be closed and the current limit will be held at its minimum setting until the temperature drops below TREG – TREG_HYST. 7.2.1.2 Thermal Shutdown The second stage consists of a hardware implemented thermal shutdown corresponding to the maximum allowable internal die temperature (TTSD). If the internal temperature exceeds this value, the port power switch will immediately be turned off until the temperature is below TTSD – TTSD_HYST. DS20005346B-page 44  2014-2015 Microchip Technology Inc. UCS1003-1/2/3 7.3 VBUS Discharge 7.4 The UCS1003-1/2/3 will discharge VBUS through an internal 100 resistor when at least one of the following conditions occurs: • The PWR_EN control is disabled (triggered on the inactive edge of the PWR_EN control). • A portable device Removal Detection event is flagged. • The VS voltage drops below a specified threshold (VS_UVLO) that causes the port power switch to be disabled. • When commanded into the Sleep power state via the EM_EN, M1 and M2 controls. • Before each charger emulation profile is applied. • Upon recovery from the Error state. • When commanded via the SMBus (for UCS1003-1 only, see Section 10.4 “Configuration Registers”) in the Active state. • Any time that the port power switch is activated after the VBUS bypass switch has been on (i.e., whenever VBUS voltage transitions from being driven from VDD to being driven from VS, such as going from Detect to Active power state). • Any time that the VBUS bypass switch is activated after the port power switch has been on (i.e., going from Active to Detect power state). Battery Full (UCS1003-1 Only) Delivery of bus current to a portable device can be rationed by the UCS1003-1. When this functionality is enabled, the host system must provide the UCS1003-1 with an accumulated charge maximum limit (in mAh). The charge rationing functionality works only in the Active power state. It continuously monitors the current delivered, as well as the time elapsed since the mode was activated (or since the data was updated). This information is compiled to generate a charge rationing number that is checked against the host limit. Once the programmed current rationing limit has been reached, the UCS1003-1 will take action as determined by the RATION_BEH bits, as described in Table 7-2. Note that this does not cause the device to enter the Error state. Once the charge rationing circuitry has reached the programmed threshold, the UCS1003-1 will maintain the desired behavior until charge rationing is reset. Once charge rationing has been reset or disabled, the UCS1003-1 will recover, as shown in Table 7-3. When the VBUS discharge circuitry is activated, at the end of the tDISCHARGE time, the UCS1003-1/2/3 will confirm that VBUS was discharged. If the VBUS voltage is not below the VTEST level, a discharge error will be flagged (by setting the DISCH_ERR status bit in the case of UCS1003-1) and the UCS1003-1/2/3 will enter the Error state. TABLE 7-2: CHARGE RATIONING BEHAVIOR RATION_BEH Behavior 1 0 0 0 Report 0 1 Report and Disconnect (default) Actions taken ALERT# pin asserted. 1. 2. 3. 1 0 Disconnect and Go to Sleep 1. 2. 3. 1 1 Ignore  2014-2015 Microchip Technology Inc. Notes ALERT# pin asserted. Charger emulation profile removed. Port power switch disconnected. The HSW will not be affected. All bus monitoring is still active. Changing the M1, M2, EM_EN, S0 and PWR_EN controls will cause the device to change power states as defined by the pin combinations; however, the port power switch will remain off until the rationing circuitry is reset. Furthermore, the bypass switch will not be turned on if enabled via the S0 control. Port power switch disconnected. Charger emulation profile removed. Device will enter the Sleep state. The HSW will be disabled. All VBUS and VS monitoring will be stopped. Changing the M1, M2, EM_EN, S0 and PWR_EN controls will have no effect on the power state until the rationing circuitry is reset. Take no further action. DS20005346B-page 45 UCS1003-1/2/3 TABLE 7-3: CHARGE RATIONING RESET BEHAVIOR Behavior Report Reset Actions 1. 2. 3. Reset the Total Accumulated Charge registers. Clear the RATION status bit. Release the ALERT# pin. Report 1. and Disconnect 2. 3. 4. Reset the Total Accumulated Charge registers. Clear the RATION status bit. Release the ALERT# pin. Check the M1, M2, EM_EN, S0 and PWR_EN controls and enter the indicated power state if the controls changed (see Note 1). Disconnect 1. and Go to Sleep 2. 3. Reset the Total Accumulated Charge registers. Clear the RATION status bit. Check the M1, M2, EM_EN, S0 and PWR_EN controls and enter the indicated power state if the controls changed (see Note 1). Ignore Note 1: 7.4.1 1. 2. Reset the Total Accumulated Charge registers. Clear the RATION status bit. Any time the charge rationing circuitry checks the pin conditions when changing rationing behavior or resetting charge rationing, if the external pin conditions have changed, then charger emulation will be restarted (provided emulation is enabled via the pin states). If the pin conditions have not changed, the UCS1003-1 returns to the previous power state as if the rationing threshold had not been reached (e.g., it will not discharge VBUS or restart emulation). CHARGE RATIONING INTERACTIONS When charge rationing is active, regardless of the specified behavior, the UCS1003-1 will function normally until the charge rationing threshold is reached. Note that charge rationing is only active when the UCS1003-1 is in the Active state and it does not automatically reset when a Removal or Attach Detection event occurs. Charger emulation will start over if a Removal Detection event and Attach Detection event occur while charge rationing is active, and the charge rationing threshold has not been reached. This allows charging of sequential portable devices while charge is being rationed, which means that the accumulated power given to several portable devices will still be held to the stated rationing limit. DS20005346B-page 46 Changing the charge rationing behavior will have no effect on the Charge Rationing Data registers. If the behavior is changed prior to reaching the charge rationing threshold, this change will occur and be transparent to the user. When the charge rationing threshold is reached, the UCS1003-1 will take action, as shown in Table 7-2. If the behavior is changed after the charge rationing threshold has been reached, the UCS1003-1 will immediately adopt the newly programmed behavior, clearing the ALERT# pin and restoring switch operation respectively (see Table 7-4).  2014-2015 Microchip Technology Inc. UCS1003-1/2/3 TABLE 7-4: EFFECTS OF CHANGING RATIONING BEHAVIOR AFTER THRESHOLD REACHED Previous Behavior New Behavior Ignore Report Report Report and Disconnect Note 1: Assert ALERT# pin. Report and Disconnect 1. 2. 3. Assert ALERT# pin. Remove charger emulation profile. Open port power switch. See the Report and Disconnect (default) in Table 7-2. Disconnect and Go to Sleep 1. 2. 3. Remove charger emulation profile. Open port power switch. Enter the Sleep state. See the Disconnect and Go to Sleep entry in Table 7-2. Ignore Release ALERT# pin. Report and Disconnect Open port power switch. See the Report and Disconnect (default) entry in Table 7-2. Disconnect and Go to Sleep 1. 2. 3. 4. Release the ALERT# pin. Remove charger emulation profile. Open the port power switch. Enter the Sleep state. See the Disconnect and Go to Sleep entry in Table 7-2. Ignore 1. 2. Release the ALERT# pin. Check the M1, M2, EM_EN, S0 and PWR_EN controls, and enter the indicated power state if the controls changed (see Note 1). Report Check the M1, M2, EM_EN, S0 and PWR_EN controls, and enter the indicated power state if the controls changed (see Note 1). Disconnect and Go to Sleep Disconnect and Go to Sleep Actions taken 1. 2. Release the ALERT# pin. Enter the Sleep state. See the Disconnect and Go to Sleep entry in Table 7-2. Ignore Check the M1, M2, EM_EN, S0 and PWR_EN controls, and enter the indicated power state if the controls changed (see Note 1). Report 1. 2. Assert the ALERT# pin. Check the M1, M2, EM_EN, S0 and PWR_EN controls, and enter the indicated power state if the controls changed (see Note 1). Report and Disconnect 1. 2. Assert the ALERT# pin. Check the M1, M2, EM_EN, S0 and PWR_EN controls to determine the power state, then enter that state, except that the port power switch and bypass switch will not be closed (see Note 1). Any time the charge rationing circuitry checks the pin conditions when changing rationing behavior or resetting charge rationing, if the external pin conditions have changed, then charger emulation will be restarted (provided emulation is enabled via the pin states). If the pin conditions have not changed, the UCS1003-1 returns to the previous power state as if the rationing threshold had not been reached (e.g., it will not discharge VBUS or restart emulation).  2014-2015 Microchip Technology Inc. DS20005346B-page 47 UCS1003-1/2/3 If the RTN_EN control bit is set to ‘0’ prior to reaching the charge rationing threshold, rationing will be disabled and the Total Accumulated Charge registers will be cleared. If the RTN_EN bit is set to ‘0’ after the charge rationing threshold has been reached, the following will be done: 1. 2. 3. RATION status bit will be cleared. The ALERT# pin will be released if asserted by the rationing circuitry and no other conditions are present. The M1, M2, EM_EN, S0 and PWR_EN controls are checked to determine the power state. See Note 1 in Table 7-4. Note: If the rationing behavior was set to “Report and Disconnect” when the charge rationing threshold was reached, and then the RTN_EN bit is cleared, the portable device may start charging sub-optimally because the charger emulation profile has been removed. Toggle the PWR_EN control to restart charger emulation. Setting the RTN_RST control bit to ‘1’ will automatically reset the Total Accumulated Charge registers to 00_00h. If this is done prior to reaching the charge rationing threshold, the data will continue to be accumulated, restarting from 00_00h. If this is done after the charge rationing threshold is reached, the UCS1003-1 will take action, as shown in Table 7-3. DS20005346B-page 48 7.5 Fault Handling Mechanism The UCS1003-1/2/3 has two modes for handling Faults: • Latch (latch-upon-Fault) • Auto-Recovery (automatically attempt to restore the Active power state after a Fault occurs). If the SMBus is actively utilized, auto-recovery Fault handling is the default error handler, as determined by the LATCHS bit (see Section 10.4.3 “Switch Configuration Register”). Otherwise, the Fault handling mechanism used depends on the state of the LATCH pin. Faults include overcurrent, overvoltage (on VS), undervoltage (on VBUS), back-voltage (VBUS to VS or VBUS to VDD), discharge error and maximum allowable internal die temperature (TTSD) exceeded (see Section 5.1.5 “Error State Operation”). 7.5.1 AUTO-RECOVERY FAULT HANDLING When the LATCH control is low, auto-recovery Fault handling is used. When an error condition is detected, the UCS1003-1/2/3 will immediately enter the Error state and assert the ALERT# pin (see Section 5.1.5 “Error State Operation”). Independently from the host controller, the UCS1003-1/2/3 will wait a preset time (tCYCLE), check error conditions (tTST) and restore Active operation if the error condition(s) no longer exist. If all other conditions that may cause the ALERT# pin to be asserted have been removed, the ALERT# pin will be released.  2014-2015 Microchip Technology Inc. UCS1003-1/2/3 7.5.2 LATCHED FAULT HANDLING enabled to disabled or by clearing the ERR bit via SMBus), the UCS1003-1/2/3 will check error conditions once and restore Active operation if error conditions no longer exist. If an error condition still exists, the host controller is required to issue the command again to check error conditions. When the LATCH control is high, latch Fault handling is used. When an error condition is detected, the UCS1003-1/2/3 will enter the Error power state and assert the ALERT# pin. Upon command from the host controller (by toggling the PWR_EN control from tCYCLE VBUS tRST tCYCLE tRST VTEST tDISCHARGE Short Applied IBUS ITST Short Detected, VBUS Discharged, Enter Error State FIGURE 7-1: Wait tCYCLE Check Short Condition, Short Still Present, Return to Error State ITST Wait tCYCLE Check Short Condition, Short Removed, Return to Normal Operation Error Recovery Timing (Short-Circuit Example).  2014-2015 Microchip Technology Inc. DS20005346B-page 49 UCS1003-1/2/3 NOTES: DS20005346B-page 50  2014-2015 Microchip Technology Inc. UCS1003-1/2/3 The UCS1003-1/2/3 can detect the attachment and removal of a portable device on the USB port. Attach and Removal Detection does not perform any charger emulation or qualification of the device. The high-speed switch is “off” (by default) during the Detect power state. Until the port power switch is enabled, the current available to a portable device will be limited to that used to detect device attachment (IDET_QUAL). Once an Attach Detection event occurs, the UCS1003-1/2/3 will wait for the PWR_EN control to be enabled (if not already). When PWR_EN is enabled and VS is above the threshold, the UCS1003-1/2/3 will activate the USB port power switch and operate in the selected Active mode (see Section 9.0 “Active State”). 8.2 8.4 8.0 DETECT STATE 8.1 Device Attach/Removal Detection VBUS Bypass Switch The UCS1003-1/2/3 family contains circuitry to provide VBUS current, as shown in Figure 8-1. In the Detect state, VDD is the voltage source; in the Active state, VS is the voltage source. The bypass switch and the port power switch are never both on at the same time. While the VBUS bypass switch is active, the current available to a portable device will be limited to IBUS_BYP and the Attach Detection feature is active. VDD 1. 3. VS VBUS Port Power Switch VS FIGURE 8-1: 8.3 The Removal Detection feature will be active in the Active and Detect power states if S0 = 1. This feature monitors the current load on the VBUS pin. If this load drops to less than IREM_QUAL_DET for longer than tREM_QUAL, a Removal Detection event is flagged. When this event occurs, the following will be performed: 2. Bypass Switch VBUS Removal Detection 4. Disable the port power switch and the bypass switch. Deassert the A_DET# pin (UCS1003-1 and UCS1003-3 only) and set the REM status register bit (UCS1003-1 only). Enable an internal discharging device that will discharge the VBUS line within tDISCHARGE. Once the VBUS pin has been discharged, the device will return to the Detect state regardless of the PWR_EN control state. Detect State VBUS Biasing. Attach Detection The primary Attach Detection feature is only active in the Detect power state. When active, this feature constantly monitors the current load on the VBUS pin. If the current drawn by a portable device is greater than IDET_QUAL, for longer than tDET_QUAL, an Attach Detection event occurs. This will cause the UCS1003-1 or UCS1003-3 to assert the A_DET# pin low and the ADET_PIN and ATT status bits to be set in the UCS1003-1 registers. The UCS1003-2 internally flags the event.  2014-2015 Microchip Technology Inc. DS20005346B-page 51 UCS1003-1/2/3 NOTES: DS20005346B-page 52  2014-2015 Microchip Technology Inc. UCS1003-1/2/3 9.0 ACTIVE STATE 9.1 Active State Overview The UCS1003-1/2/3 family has the following modes of operation in the Active state: Data Pass-Through, BC1.2 DCP, BC1.2 SDP, BC1.2 CDP and Dedicated Charger Emulation Cycle. The Current-Limiting mode depends on the Active mode behavior (see Table 9-2). 9.2 Note 1: If it is desired that the Data Pass-Through mode operates as a traditional/standard port power switch, the S0 control should be set to ‘0’ to allow the port power switch to be closed without requiring an Attach Detection event. When entering this mode, there is no automatic VBUS discharge. 2: When the M1, M2 and EM_EN controls are set to ‘0’, ‘1’, ‘0’ or to ‘1’, ‘1’, ‘0’, respectively, Data Pass-Through mode will persist if the PWR_EN control is disabled; however, the UCS1003-1/2/3 will draw more current. To leave the Data Pass-Through mode, the PWR_EN control must be enabled before the M1, M2 and EM_EN controls are changed to the desired mode. Active Mode Selection The Active mode selection is controlled by three controls: EM_EN, M1 and M2, as shown in Table 9-1. TABLE 9-1: ACTIVE MODE SELECTION M1 M2 EM_EN Active mode 0 0 1 Dedicated Charger Emulation Cycle 0 1 0 Data Pass-Through 0 1 1 BC1.2 DCP 1 0 0 BC1.2 SDP (Note 1) 1 0 1 Dedicated Charger Emulation Cycle 1 1 0 Data Pass-Through 1 1 1 BC1.2 CDP Note 1: 9.3 BC1.2 SDP behaves the same as the Data Pass-Through mode with the exception that it is preceded by a VBUS discharge when the mode is entered per the BC1.2 specification. Data Pass-Through (No Charger Emulation) When commanded to Data Pass-Through mode, the UCS1003-1/2/3 devices will close their USB highspeed data switch to allow USB communications between a portable device and host controller, and will operate using Trip Current-Limiting mode. No charger emulation profiles are applied in this mode. Data PassThrough mode will persist until commanded otherwise by the M1, M2 and EM_EN controls.  2014-2015 Microchip Technology Inc. BC1.2 SDP (No Charger Emulation) When commanded to BC1.2 SDP mode, UCS1003-1/2/3 devices will discharge VBUS, close their USB high-speed data switch to allow USB communications between a portable device and host controller, and will operate using Trip Current-Limiting mode. No charger emulation profiles are applied in this mode. BC1.2 SDP mode will persist until commanded otherwise by the M1, M2, EM_EN and PWR_EN controls. Note: BC1.2 Detection Renegotiation The BC1.2 specification allows a charger to act as an SDP, CDP or DCP and to change between these roles. To force an attached portable device to repeat the Charging Detection procedure, VBUS must be cycled. In compliance with this specification, the UCS1003-1/2/3 family automatically cycles VBUS when switching between the BC1.2 SDP, BC1.2 DCP and BC1.2 CDP modes. 9.4 9.5 9.6 If it is desired that the BC1.2 SDP mode operates as a traditional/standard port power switch, the S0 control should be set to ‘0’ to allow the port power switch to be closed without requiring an Attach Detection event. BC1.2 CDP When BC1.2 CDP is selected as the Active mode, UCS1003-1/2/3 devices will discharge VBUS, close their USB high-speed data switch (by default) and apply the BC1.2 CDP charger emulation profile, which performs handshaking per the specification. The combination of the UCS1003-1/2/3 CDP handshake, along with a standard USB host, comprises a charging downstream port. In BC1.2 CDP mode, there is no emulation time-out. If the handshake is successful, the UCS1003-1/2/3 will operate using Constant-Current Limiting (variable slope). If the handshake is not successful, the UCS1003-1/2/3 will leave the applied CDP profile in place, leave the high-speed switch closed, enable Constant-Current Limiting and persist in this condition until commanded otherwise by the M1, M2, EM_EN and PWR_EN controls. DS20005346B-page 53 UCS1003-1/2/3 The UCS1003-1/2/3 will respond per the BC1.2 specification to the portable device initiated charger renegotiation requests. Note 1: BC1.2 compliance testing may require the S0 control to be set to ‘0’ (Attach and Removal Detection feature disabled) while testing is in progress. 2: When the UCS1003-1/2/3 devices are in BC1.2 CDP mode and the Attach and Removal Detection feature is enabled, if a power thief (such as a USB light or fan) attaches but does not assert the DP pin, a removal event will not occur when the portable device is removed. However, if a standard USB device is subsequently attached, Removal Detection will again be fully functional. As well, if PWR_EN is cycled or M1, M2 and/or EM_EN change state, a removal event will occur and Attach Detection will be reactivated. 9.6.1 1. 2. 3. 4. 9.7 Note: 9.7.1 1. 2. 3. All CDP handshaking is performed with the high-speed switch closed. VBUS voltage is applied. Primary Detection – When the portable device drives a voltage between 0.4V and 0.8V onto the DPOUT pin, the UCS1003-1/2/3 will drive 0.6V onto the DMOUT pin within 20 ms. When the portable device drives the DPOUT pin back to ‘0’, the UCS1003-1/2/3 will then drive the DMOUT pin back to ‘0’ within 20 ms. Optional Secondary Detection – If the portable device then drives a voltage of 0.6V (nominal) onto the DMOUT pin, the UCS1003-1/2/3 will take no other action. This will cause the portable device to observe a ‘0’ on the DPOUT pin and know that it is connected to a CDP. BC1.2 DCP When BC1.2 DCP is selected as the Active mode, UCS1003-1/2/3 will discharge VBUS and apply the BC1.2 DCP charger emulation profile per the specification. In BC1.2 DCP mode, the emulation timeout and requirement for portable device current draw are automatically disabled. In the case of UCS1003-1, when the BC1.2 DCP charger emulation profile is applied within the Dedicated Charger Emulation Cycle mode (see Section 9.11.1 “BC1.2 DCP Charger Emulation Profile within DCE Cycle”), the time-out and current draw requirement are enabled. DS20005346B-page 54 BC1.2 compliance testing may require the S0 control to be set to ‘0’ (Attach and Removal Detection feature disabled) while testing is in progress. BC1.2 DCP CHARGER EMULATION PROFILE The BC1.2 DCP charger emulation profile is described as follows: BC1.2 CDP CHARGER EMULATION PROFILE The BC1.2 CDP charger emulation profile acts in a reactionary manner based on stimulus from the portable device, as described below and shown in Figure 2-1. Note: If the portable device is charging after the DCP charger emulation profile is applied, the UCS1003-1/2/3 will leave in place the resistive short, leave the high-speed switch open and enable Constant-Current Limiting (variable slope). 9.8 VBUS voltage is applied. A resistor (RDCP_RES) is connected between the DPOUT and DMOUT pins. Primary Detection – If the portable device drives 0.6V (nominal) onto the DPOUT pin, the UCS1003-1/2/3 will take no other action than to leave the resistor connected between DPOUT and DMOUT. This will cause the portable device to see 0.6V (nominal) on the DMOUT pin and know that it is connected to a DCP. Optional Secondary Detection – If the portable device drives 0.6V (nominal) onto the DMOUT pin, the UCS1003-1/2/3 will take no other action than to leave the resistor connected between DPOUT and DMOUT. This will cause the portable device to see 0.6V (nominal) on the DPOUT pin and know that it is connected to a DCP. Dedicated Charger Emulation Cycle When commanded to Dedicated Charger Emulation Cycle mode, the UCS1003-1/2/3 family enables an attached portable device to enter its Charging mode by applying specific charger emulation profiles in a predefined sequence. Using these profiles, the UCS1003-1/2/3 family is capable of generating and recognizing several signal levels on the DPOUT and DMOUT pins. The preloaded charger emulation profiles include those compatible with YD/T-1591 (2009), 12W charging, Samsung and many RIM portable devices. In the case of UCS1003-1, other levels, sequences and protocols are configurable via the SMBus/I2C. When a charger emulation profile is applied, a programmable timer for the emulation profile is started. When emulation time-out occurs, the UCS1003-1/2/3 family checks the IBUS current against a programmable threshold. If the current is above the threshold, the charger emulation profile is accepted and the associated Current-Limiting mode is applied. No active USB data communication is possible when charging in this mode (by default – see Section 10.4.5 “High-Speed Switch Configuration Register”).  2014-2015 Microchip Technology Inc. UCS1003-1/2/3 9.8.1 EMULATION RESET Prior to applying any of the charger emulation profiles, the UCS1003-1/2/3 will perform an emulation Reset. This means that the UCS1003-1/2/3 family resets the VBUS line by disconnecting the port power switch and connecting VBUS to ground via an internal 100 resistor for tDISCHARGE time. The port power switch will be held open for a time equal to tEM_RESET, at which point, the port power switch will be closed and the VBUS voltage applied. The DPOUT and DMOUT pins will be pulled low using internal 15 k pull-down resistors. Note: 9.8.2 To help prevent possible damage to a portable device, the DPOUT and DMOUT pins have current limiting in place when the emulation profiles are applied. In the case of UCS1003-1, emulation time-outs can be programmed for each charger emulation profile (see Section 10.11 “Preloaded Emulation Time-out Configuration Registers” and Register 10-35). 9.8.3 DCE CYCLE RETRY If none of the charger emulation profiles cause a charge current to be drawn, the UCS1003-1/2/3 will perform emulation Reset and cycle through the profiles again (if the EM_RETRY bit is set in the UCS1003-1 default – see Section 10.4.2 “Emulation Configuration Register”). The UCS1003-1/2/3 will continue to cycle through the profiles as long as charging current is not drawn and the PWR_EN control is enabled. If the emulation retry is not enabled, the UCS1003-1 will flag, “No Handshake”, and end the DCE Cycle mode using Trip Current-Limiting mode. EMULATION CYCLING In Dedicated Charger Emulation Cycle mode, the charger emulation profiles (if enabled) will be applied in the following order: 1. 2. 3. 4. 5. 6. 7. 8. Legacy 1 Legacy 2 Legacy 3 Legacy 4 Legacy 5 Legacy 6 Legacy 7 Custom (UCS1003-1 only; disabled by default). If the CS_FRST Configuration bit is set, then the custom charger emulation profile will be tested first and the order will proceed as given. If S0 = 0 and a portable device is not attached in DCE Cycle mode, the UCS1003-1/2/3 will be cycling through charger emulation profiles (by default). There is no assurance which charger emulation profile will be applied first when a portable device attaches. The UCS1003-1/2/3 will apply a charger emulation profile until one of the following exit conditions occurs: • Current greater than IBUS_CHG is detected flowing out of VBUS at the respective emulation time-out time. In this case, the profile is assumed to be accepted and no other profiles will be applied. • The respective emulation time-out (tEM_TIMEOUT) time is reached without current that exceeds the IBUS_CHG limit flowing out of VBUS (the emulation time-out is enabled by default, see Section 10.4.2 “Emulation Configuration Register” and Register 10-35). The profile is assumed to be rejected, and the UCS1003-1/2/3 will perform emulation Reset and apply the next profile if there is one.  2014-2015 Microchip Technology Inc. DS20005346B-page 55 UCS1003-1/2/3 9.9 Current Limit Mode Associations The UCS1003-1/2/3 will close the port power switch and use the Current-Limiting mode, as shown in Table 9-2. TABLE 9-2: CURRENT LIMIT MODE OPTIONS Current Limit Mode (See Section 10.14 “Current-Limiting Behavior Configuration Registers”) Active Mode Data Pass-Through Trip mode BC1.2 SDP Trip mode BC1.2 CDP CC mode if ILIM < 1.68A; otherwise, Trip mode BC1.2 DCP CC mode if ILIM < 1.68A; otherwise, Trip mode DCE Cycle Mode UCS1003-1 During DCE Cycle, when a charger emulation profile is CC mode if ILIM < 1.68A; otherwise, Trip mode being applied and the emulation time-out is active BC1.2 DCP charger emulation profile accepted or the emulation time-out is disabled CC mode if ILIM < 1.68A; otherwise, Trip mode Legacy 2 charger emulation profile accepted or the emulation time-out is disabled CC mode if ILIM < 1.68A; otherwise, Trip mode Legacy 1 or Legacy 3 – Legacy 7 charger emulation profile accepted or the emulation time-out is disabled Trip mode if IBUS_R2MIN < ILIM or ILIM > 1.68A (normal operation); otherwise, CC mode (see Register 10-49)(Note 1) Custom charger emulation profile accepted or the emulation time-out is disabled Trip mode if IBUS_R2MIN < ILIM or ILIM > 1.68A (normal operation); otherwise, CC mode (see Register 10-49)(Note 1) No handshake (DCE Cycle with emulation retry not enabled) Trip mode if IBUS_R2MIN < ILIM or ILIM > 1.68A (normal operation); otherwise, CC mode (see Register 10-49)(Note 1) UCS1003-2/3 During DCE Cycle, when a charger emulation profile is CC mode if ILIM < 1.68A; otherwise, Trip mode being applied and the emulation time-out is active Legacy 3 charger emulation profile accepted CC mode if ILIM < 1.68A; otherwise, Trip mode Legacy 1, Legacy 2 or Legacy 4 – Legacy 7 charger emulation profile accepted Trip mode Note 1: In the case of UCS1003-1, under these specific conditions with ILIM < 1.68A, it is the relationship of ILIM and IBUS_R2MIN that determines the Current-Limiting mode. In these cases, the value of IBUS_R2MIN is determined by the CS_R2_IMIN bits, Custom Current-Limiting Behavior Configuration (Register 10-49). DS20005346B-page 56  2014-2015 Microchip Technology Inc. UCS1003-1/2/3 9.10 No Handshake (UCS1003-1 only) In DCE Cycle mode with emulation retry disabled, a “no handshake” condition is flagged. The NO_HS status bit stays set when the end of the DCE Cycle is reached without a handshake and without drawing current (see Register 10-5). All signatures/handshaking placed on the DPOUT and DMOUT pins are removed. The UCS1003-1 will operate with the high-speed switch opened or closed, as determined by the high-speed switch configuration, and will use Trip or Constant-Current Limiting as determined by the IBUS_R2MIN setting (CS_R2_IMIN bits, Custom Current-Limiting Behavior Configuration). The portable devices that can cause this are generally the ones that pull up DPOUT to some voltage and leave it there or apply the wrong voltage. 9.11 Preloaded Charger Emulation Profiles in UCS1003-1 The following charger emulation profiles are resident to the UCS1003-1: • BC1.2 DCP Charger Emulation Profile within DCE Cycle • Legacy 2 Charger Emulation Profile • Legacy 1, 3, 4 and 6 Charger Emulation Profiles • Legacy 5 Charger Emulation Profile • Legacy 7 Charger Emulation Profile • BC1.2 CDP Charger Emulation Profile • BC1.2 DCP Charger Emulation Profile 9.11.1 BC1.2 DCP CHARGER EMULATION PROFILE WITHIN DCE CYCLE When the BC1.2 DCP charger emulation profile (see Section 9.7.1 “BC1.2 DCP Charger Emulation Profile”) is applied within the DCE Cycle (dedicated charger emulation cycle is selected as the Active mode), the behavior after the profile is applied differentiates from the Active mode BC1.2 DCP (BC1.2 DCP in Table 9-1) because the tEM_TIMEOUT timer is enabled (by default) during the DCE Cycle. During the DCE Cycle, after the DCP charger emulation profile is applied, the UCS1003-1 will perform one of the following: 1. 2. If the portable device is drawing more than IBUS_CHG current when the tEM_TIMEOUT timer expires, the UCS1003-1 will flag that a BC1.2 DCP was detected. The UCS1003-1 will leave in place the resistive short, leave the high-speed switch open and then enable Constant-Current Limiting (variable slope). If the portable device does not draw more than IBUS_CHG current when the tEM_TIMEOUT timer expires, the UCS1003-1 will stop applying the DCP charger emulation profile and proceed to the next charger emulation profile in the DCE Cycle.  2014-2015 Microchip Technology Inc. 9.11.2 LEGACY 2 CHARGER EMULATION PROFILE The Legacy 2 charger emulation profile does the following: 1. The UCS1003-1 will connect a resistor (RDCP_RES) between DPOUT and DMOUT. 2. VBUS is applied. 3. If the portable device draws more than IBUS_CHG current when the tEM_TIMEOUT timer expires (enabled by default), the UCS1003-1 will accept that this is the correct charger emulation profile for the attached portable device and charging commences. The resistive short between the DPOUT and DMOUT pins will be left in place. 4. If the portable device does not draw more than IBUS_CHG current when the tEM_TIMEOUT timer expires, the UCS1003-1 will stop the Legacy 2 charger emulation. This will cause the resistive short between the DPOUT and DMOUT pins to be removed. Emulation Reset occurs and UCS1003-1 will initiate the next charger emulation profile. 9.11.3 LEGACY 1, 3, 4 AND 6 CHARGER EMULATION PROFILES Legacy 1, 3, 4 and 6 charger emulation profiles follow the same pattern of operation, although the voltage that is applied on the DPOUT and DMOUT pins will vary. They do the following: 1. The UCS1003-1 will apply a voltage on the DPOUT pin using either a current-limited voltage source or a voltage divider between VBUS and ground, with the center tap on the DPOUT pin. 2. The UCS1003-1 will apply a possibly different voltage on the DMOUT pin, using either a currentlimited voltage source or a voltage divider between VBUS and ground, with the center tap on the DMOUT pin. 3. VBUS voltage is applied. 4. If the portable device draws more than IBUS_CHG current when the tEM_TIMEOUT timer expires, the UCS1003-1 will accept that the currently applied profile is the correct charger emulation profile for the attached portable device; charging commences. The voltages applied to the DPOUT and DMOUT pins will remain in place (unless EM_RESP is set to ‘0b’). The UCS1003-1 will begin operating in Trip mode or CC mode, as determined by the IBUS_R2MIN setting (see Section 10.14 “Current-Limiting Behavior Configuration Registers”). 5. If the portable device does not draw more than IBUS_CHG current when the tEM_TIMEOUT timer expires, the UCS1003-1 will stop the currently applied charger emulation profile. This will cause all voltages put onto the DPOUT and DMOUT pins to be removed. Emulation Reset occurs, and the UCS1003-1 will initiate the next charger emulation profile. DS20005346B-page 57 UCS1003-1/2/3 9.11.4 LEGACY 5 CHARGER EMULATION PROFILE 9.12 Legacy 5 charger emulation profile does the following: 1. 2. 3. 4. The UCS1003-1 will apply 900 mV to both the DPOUT and the DMOUT pins. VBUS voltage is applied. If the portable device draws more than IBUS_CHG current when the tEM_TIMEOUT timer expires, the UCS1003-1 will accept that the currently applied profile is the correct charger emulation profile for the attached portable device; charging commences. The voltages applied to the DPOUT and DMOUT pins will remain in place (unless EM_RESP is set to ‘0b’). The UCS1003-1 will begin operating in Trip mode or CC mode, as determined by the IBUS_R2MIN setting (see Section 10.14 “Current-Limiting Behavior Configuration Registers”). If the portable device does not draw more than IBUS_CHG current when the tEM_TIMEOUT timer expires, the UCS1003-1 will stop the currently applied charger emulation profile. This will cause all voltages put onto the DPOUT and DMOUT pins to be removed. Emulation Reset occurs and the UCS1003-1 will initiate the next charger emulation profile. 9.11.5 LEGACY 7 CHARGER EMULATION PROFILE The Legacy 7 charger emulation profile does the following: 1. 2. 3. 4. The UCS1003-1 will apply a voltage on the DPOUT pin using a voltage divider between VBUS and ground with the center tap on the DPOUT pin. VBUS voltage is applied. If the portable device draws more than IBUS_CHG current when the tEM_TIMEOUT timer expires, the UCS1003-1 will accept that Legacy 7 is the correct charger emulation profile for the attached portable device. Charging commences. The voltage applied to the DPOUT pin will remain in place (unless EM_RESP is set to 0b). The UCS1003-1 will begin operating in Trip mode or CC mode, as determined by the setting (see Section 10.14 IBUS_R2MIN “Current-Limiting Behavior Configuration Registers”). If the portable device does not draw more than IBUS_CHG current when tEM_TIMEOUT timer expires, the UCS1003-1 will stop the Legacy 7 charger emulation profile. This will cause the voltage put onto the DPOUT pin to be removed. Emulation reset occurs, and the UCS1003-1 will initiate the next charger emulation profile. DS20005346B-page 58 Preloaded Charger Emulation Profiles in UCS1003-2 and UCS1003-3 The following charger emulation profiles are resident to the UCS1003-2/3: • • • • • • Legacy 1 Charger Emulation Profile Legacy 2, 4, 5 and 7 Charger Emulation Profiles Legacy 3 Charger Emulation Profile Legacy 6 Charger Emulation Profile BC1.2 CDP Charger Emulation Profile BC1.2 DCP Charger Emulation Profile 9.12.1 LEGACY 1 CHARGER EMULATION PROFILE Legacy 1 charger emulation profile does the following: 1. 2. 3. 4. The UCS1003-2/3 will apply 900 mV to both the DPOUT and the DMOUT pins. VBUS voltage is applied. If the portable device is charging, the UCS1003-2/3 will accept that the currently applied profile is the correct charger emulation profile for the attached portable device; charging commences. The voltages applied to the DPOUT and DMOUT pins will remain in place. The UCS1003-2/3 will begin operating in Trip mode. If the portable device is not charging, the UCS1003-2/3 will stop the currently applied charger emulation profile. This will cause all voltages put onto the DPOUT and DMOUT pins to be removed. Emulation Reset occurs and the UCS1003-2/3 will initiate the next charger emulation profile.  2014-2015 Microchip Technology Inc. UCS1003-1/2/3 9.12.2 LEGACY 2, 4, 5 AND 7 CHARGER EMULATION PROFILES Legacy 2, 4, 5 and 7 charger emulation profiles follow the same pattern of operation, although the voltage that is applied on the DPOUT and DMOUT pins will vary. They do the following: 1. 2. 3. 4. 5. The UCS1003-2/3 will apply a voltage on the DPOUT pin using either a current-limited voltage source or a voltage divider between VBUS and ground, with the center tap on the DPOUT pin. The UCS1003-2/3 will apply a possibly different voltage on the DMOUT pin, using either a current-limited voltage source or a voltage divider between VBUS and ground. with the center tap on the DMOUT pin. VBUS voltage is applied. If the portable device is charging, the UCS1003-2/3 will accept that the currently applied profile is the correct charger emulation profile for the attached portable device; charging commences. The voltages applied to the DPOUT and DMOUT pins will remain in place. The UCS1003-2/3 will begin operating in Trip mode (see Section 10.14 “Current-Limiting Behavior Configuration Registers”). If the portable device is not charging, the UCS1003-2/3 will stop the currently applied charger emulation profile. This will cause all voltages put onto the DPOUT and DMOUT pins to be removed. Emulation Reset occurs and the UCS1003-2/3 will initiate the next charger emulation profile. 9.12.3 LEGACY 3 CHARGER EMULATION PROFILE The Legacy 3 charger emulation profile does the following: 1. 2. 3. 4. The UCS1003-2/3 will connect a resistor (RDCP_RES) between DPOUT and DMOUT. VBUS is applied. If the portable device is charging, the UCS1003-2/3 will accept that this is the correct charger emulation profile for the attached portable device; charging commences. The resistive short between the DPOUT and DMOUT pins will be left in place. If the portable device is not charging, the UCS1003-2/3 will stop the Legacy 3 charger emulation. This will cause a resistive short between the DPOUT and DMOUT pins to be removed. Emulation Reset occurs and the UCS1003-2/3 will initiate the next charger emulation profile.  2014-2015 Microchip Technology Inc. 9.12.4 LEGACY 6 CHARGER EMULATION PROFILE The Legacy 6 charger emulation profile does the following: 1. 2. 3. 4. The UCS1003-2/3 will apply a voltage on the DPOUT pin using a voltage divider between VBUS and ground, with the center tap on the DPOUT pin. VBUS voltage is applied. If the portable device is charging, the UCS1003-2/3 will accept that Legacy 6 is the correct charger emulation profile for the attached portable device; charging commences. The voltage applied to the DPOUT pin will remain in place. The UCS1003-2/3 will begin operating in Trip mode. If the portable device is not charging, the UCS1003-2/3 will stop the Legacy 6 charger emulation profile. This will cause the voltage put onto the DPOUT pin to be removed. Emulation Reset occurs and the UCS1003-2/3 will initiate the next charger emulation profile. 9.13 Custom Charger Emulation Profile (UCS1003-1 only) The UCS1003-1 allows the user to create a custom charger emulation profile to handshake as any type of charger. This profile can be included in the DCE Cycle. In addition, it can be placed first or last in the profile sequence in the DCE Cycle (see Register 10-35). The custom charger emulation profile uses a number of registers to define stimuli and behaviors. The custom charger emulation profile uses three separate stimulus/response pairs that will be detected and applied in sequence, allowing flexibility to “build” any of the preloaded emulation profiles, or tailor the profile to match a specific charger application. For details, see Application Note 24.14 – “UCS1002 Fundamentals of Custom Charger Emulation”. DS20005346B-page 59 UCS1003-1/2/3 NOTES: DS20005346B-page 60  2014-2015 Microchip Technology Inc. UCS1003-1/2/3 10.0 UCS1003-1 REGISTER DESCRIPTION The registers shown in Table 10-1 are accessible through the SMBus or I2C protocol. While in the Sleep state, the UCS1003-1 will retain configuration and charge rationing data as indicated in the text. If a register does not indicate that data will be retained in the Sleep power state, this information will be lost when the UCS1003-1 enters the Sleep power state. TABLE 10-1: Register Address REGISTER SET IN HEXADECIMAL ORDER Register Name R/W Function Default Value Page No. 00h Current Measurement R Stores the current measurement 00h 62 01h Total Accumulated Charge High Byte R Stores the total accumulated charge delivered high byte 00h 63 02h Total Accumulated Charge Middle High Byte R Stores the total accumulated charge delivered middle high byte 00h 63 03h Total Accumulated Charge Middle Low Byte R Stores the total accumulated charge delivered middle low byte 00h 63 04h Total Accumulated Charge Low Byte R Stores the total accumulated charge delivered low byte 00h 63 0Fh Other Status R Indicates emulation status as well as the ALERT# and A_DET# pin status 00h 64 10h Interrupt Status 00h 65 Indicates general status 00h 67 Indicates which charger emulation profile was accepted 00h 68 See Indicates why ALERT# pin is asserted Register 10-3 11h General Status R/R-C 12h Profile Status 1 R 13h Profile Status 2 R 14h Pin Status R 15h General Configuration R/W 00h 70 Indicates the pin states of the internal control pins 00h 72 Controls basic functionality 01h 67 16h Emulation Configuration R/W Controls emulation functionality 8Ch 74 17h Switch Configuration R/W Controls advanced switch functions 04h 76 18h Attach Detect Configuration R/W Controls Attach Detect functionality 46h 77 19h Current Limit R/W Controls the maximum current limit 00h 79 1Ah Charge Rationing Threshold High Byte R/W Controls the current threshold, ITHRESH, used by the charge rationing circuitry FFh 80 1Bh Charge Rationing Threshold Low Byte R/W Controls the current threshold, ITHRESH, used by the charge rationing circuitry FFh 80 1Ch Auto-Recovery Configuration R/W Controls the auto-recovery functionality 2Ah 81 1Eh IBUS_CHG Configuration R/W Stores the limit for IBUS_CHG used to determine if emulation is successful 04h 82 1Fh tDET_CHARGE Configuration R/W Stores bits that define the tDET_CHARGE time 03h 83 20h BCS Emulation Enable R/W Enables BCS charger emulation profiles 06h 84 21h Legacy Emulation Enable R/W Enables Legacy charger emulation profiles 00h 85 22h BCS Emulation Time-out Configuration R/W Controls time-out for each BCS charger emulation profile 10h 86  2014-2015 Microchip Technology Inc. DS20005346B-page 61 UCS1003-1/2/3 TABLE 10-1: Register Address REGISTER SET IN HEXADECIMAL ORDER (CONTINUED) Register Name R/W Function Default Value Page No. 23h Legacy Emulation Time-out Configuration 1 R/W Controls time-out for Legacy Charger Emulation Profiles 1–4 B0h 87 24h Legacy Emulation Time-out Configuration 2 R/W Controls time-out for Legacy Charger Emulation Profiles 5–7 04h 88 25h High-Speed Switch Configuration R/W Controls when the high-speed switch is enabled 14h 78 30h Applied Charger Emulation R Indicates which charger emulation profile is being applied 00h 90 31h Preloaded Emulation Stimulus 1 – Configuration 1 R Indicates the stimulus and timing for Stimulus 1 00h 91 32h Preloaded Emulation Stimulus 1 – Configuration 2 R Indicates the response and magnitude for Stimulus 1 00h 92 33h Preloaded Emulation Stimulus 1 – Configuration 3 R Indicates the threshold and pull-up/pull-down settings for Stimulus 1 00h 94 34h Preloaded Emulation Stimulus 1 – Configuration 4 R Indicates the resistor ratio for Stimulus 1 00h 95 35h Preloaded Emulation Stimulus 2 – Configuration 1 R Indicates the stimulus and timing for Stimulus 2 00h 96 36h Preloaded Emulation Stimulus 2 – Configuration 2 R Indicates the response and magnitude for Stimulus 2 00h 97 37h Preloaded Emulation Stimulus 2 – Configuration 3 R Indicates the threshold and pull-up/pull-down settings for Stimulus 2 00h 99 38h Preloaded Emulation Stimulus 2 – Configuration 4 R Indicates the resistor ratio for Stimulus 2 00h 100 39h Preloaded Emulation Stimulus 3 – Configuration 1 R Indicates the stimulus and timing for Stimulus 3 (CDP only) 00h 101 3Ah Preloaded Emulation Stimulus 3 – Configuration 2 R Indicates the response and magnitude for Stimulus 3 (CDP only) 00h 102 3Bh Preloaded Emulation Stimulus 3 – Configuration 3 R Indicates the threshold and pull-up/pull-down settings for Stimulus 3 (CDP only) 00h 104 40h Custom Emulation Configuration R/W Controls general configuration of the custom charger emulation profile 01h 106 41h Custom Stimulus/Response Pair 1 – Configuration 1 R/W Sets the stimulus and timing for Stimulus 1 00h 107 42h Custom Stimulus/Response Pair 1 – Configuration 2 R/W Sets the response and magnitude for Stimulus 1 00h 108 43h Custom Stimulus/Response Pair 1 – Configuration 3 R/W Sets the threshold and pull-up/pull-down settings for Stimulus 1 00h 110 44h Custom Stimulus/Response Pair 1 – Configuration 4 R/W Sets the resistor ratio for Stimulus 1 00h 111 45h Custom Stimulus/Response Pair 2 – Configuration 1 R/W Sets the stimulus and timing for Stimulus 2 00h 112 46h Custom Stimulus/Response Pair 2 – Configuration 2 R/W Sets the response and magnitude for Stimulus 2 00h 113 47h Custom Stimulus/Response Pair 2 – Configuration 3 R/W Sets the threshold and pull-up/pull-down settings for Stimulus 2 00h 115 48h Custom Stimulus/Response Pair 2 – Configuration 4 R/W Sets the resistor ratio for Stimulus 2 00h 116 DS20005346B-page 62  2014-2015 Microchip Technology Inc. UCS1003-1/2/3 TABLE 10-1: Register Address REGISTER SET IN HEXADECIMAL ORDER (CONTINUED) Default Value Page No. Sets the stimulus and timing for Stimulus 3 00h 117 R/W Sets the response and magnitude for Stimulus 3 00h 118 Custom Stimulus/Response Pair 3 – Configuration 3 R/W Sets the threshold and pull-up/pull-down settings for Stimulus 3 00h 120 4Ch Custom Stimulus/Response Pair 3 – Configuration 4 R/W Sets the resistor ratio for Stimulus 3 00h 121 50h Applied Current-Limiting Behavior R Indicates the applied current-limiting behavior 82h 122 51h Custom Current-Limiting Behavior Configuration R/W Controls the custom current-limiting behavior 82h 123 FDh Product ID R Stores a fixed value that identifies each product 4Eh 123 FEh Manufacturer ID R Stores a fixed value that identifies Microchip 5Dh 123 FFh Revision R Stores a fixed value that represents the revision number 82h 123 Register Name R/W 49h Custom Emulation Stimulus 3 – Configuration 1 R/W 4Ah Custom Stimulus/Response Pair 3 – Configuration 2 4Bh During Power-on Reset (POR), the default values are stored in the registers. A POR is initiated when power is first applied to the part and the voltage on the VDD supply surpasses the VDD_TH level, as specified in the electrical characteristics. Any reads to undefined registers will return 00h. Writes to undefined registers will not have an effect. When a bit is “set”, this means that the user writes a logic ‘1’ to it. When a bit is “cleared”, this means that the user writes a logic ‘0’ to it. Function 10.1 Current Measurement Register (Address 00h) Name Current Measurement Bits Address Cof Default 8 00h R 00h The Current Measurement register stores the measured current value delivered to the portable device (IBUS). This value is updated continuously while the device is in the Active power state. The bit weights are in mA and the range is from 0 mA to 2988.6 (the maximum value corresponds to 255 LSBs, where1 LSB = 11.72 mA). This data will be cleared when the device enters the Sleep or Detect states. This data will also be cleared whenever the port power switch is turned off (including during emulation or any time that VBUS is discharged).  2014-2015 Microchip Technology Inc. DS20005346B-page 63 UCS1003-1/2/3 10.2 The Total Accumulated Charge registers store the total accumulated charge delivered from the VS source to a portable device. The bit weighting of the registers is given in mAh. The register value is reset to 00_00h only when the RTN_RST bit is set or if the RTN_EN bit is cleared. This value will be retained when the device transitions out of the Active state, and resumes accumulation if the device returns to the Active state and charge rationing is still enabled. Total Accumulated Charge Registers Name Bits Address Cof Default Total Accumulated Charge High Byte 8 01h R 00h Total Accumulated Charge Middle High Byte 8 02h R 00h Total Accumulated Charge Middle Low Byte 8 03h R 00h Total Accumulated Charge Low Byte 8 04h R 00h REGISTER 10-1: R-0 R-0 These registers are updated every second while the UCS1003-1 is in the Active power state. Every time the value is updated, it is compared against the target value in the Charge Rationing Threshold registers (see Section 10.6 “Charge Rationing Threshold Registers”). TOTAL ACCUMULATED CHARGE REGISTERS (ADDRESSES 01h-04h) R-0 R-0 R-0 R-0 R-0 R-0 ACC bit 31 bit 24 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 ACC bit 23 bit 26 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 ACC bit 15 bit 8 R-0 R-0 ACC U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 31-6 ACC: Total Accumulated Charge bits 1 LSB = 0.00325 mAh bit 5-0 Unimplemented: Read as ‘0’ DS20005346B-page 64 x = Bit is unknown  2014-2015 Microchip Technology Inc. UCS1003-1/2/3 10.3 Status Registers Name Bits Address Other Status Interrupt Status General Status Profile Status 1 Profile Status 2 Pin Status 8 8 8 8 8 8 REGISTER 10-2: U-0 U-0 — — 0Fh 10h 11h 12h 13h 14h Cof Default R R/W R/R-C R R R 00h 00h 00h 00h 00h 00h The Status registers store bits that indicate error conditions, as well as Attach Detection and Removal Detection. Unless otherwise noted, these bits will operate as described when the UCS1003-1 is operating in Stand-Alone mode. OTHER STATUS REGISTER (ADDRESS 0Fh) R-0 R-0 R-0 ALERT_PIN ADET_PIN(1) CHG_ACT(2) R-0 EM_ACT(3) R-0 R-0 EM_STEP bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-6 Unimplemented: Read as ‘0’ bit 5 ALERT_PIN: ALERT# Pin Status bit This bit is set and cleared as the ALERT# pin changes states. 1 = ALERT# pin is asserted low 0 = ALERT# pin is released bit 4 ADET_PIN: A_DET# Pin Status bit(1) When set, indicates that the A_DET# pin is asserted low. This bit is set and cleared as the A_DET# pin changes states. 1 = A_DET# pin is asserted low 0 = A_DET# pin is released bit 3 CHG_ACT: IBUS Set/Clear Status bit(2) This bit is automatically set when IBUS > IBUS_CHG and cleared when IBUS < IBUS_CHG. 1 = IBUS > IBUS_CHG 0 = IBUS < IBUS_CHG bit 2 EM_ACT: UCS1003-1 Active State and Emulating Status bit(3) The actual profile that is being applied is identified by PRE_EM_SEL (see Section 10.12.1 “Applied Charger Emulation Register”). This bit is set and cleared automatically. 1 = Device is in the Active state and emulating 0 = Device is not emulating bit 1-0 EM_STEP: Charger Emulation Stimulus/Response Pair Application bits Indicates which stimulus/response pair is currently being applied by the charger emulation profile as shown below. These bits are set and cleared automatically. Note that the Legacy charger emulation profiles and the BC1.2 DCP charger emulation profile do not use Stimulus/Response Pair #3. 00 = None applied, waiting for current. 01 = Stimulus/Response #1 10 = Stimulus/Response #2 00 = Stimulus/Response #3 if applicable Note 1: 2: 3: If S0 is ‘1’, PWR_EN is enabled and VS is not present; the ADET_PIN bit will cycle if the current draw exceeds the current capacity of the bypass switch. The CHG_ACT bit does not indicate that a portable device has accepted one of the charger emulation profiles. This bit will cycle during the Dedicated Charger Emulation Cycle mode. The EM_ACT bit does not indicate that a portable device has accepted one of the emulation profiles. This bit will cycle during the Dedicated Charger Emulation Cycle mode  2014-2015 Microchip Technology Inc. DS20005346B-page 65 UCS1003-1/2/3 REGISTER 10-3: R/W-0 (1,2) ERR INTERRUPT STATUS REGISTER (ADDRESS 10h) R-0 R-0 R-0 R-0 R-0 R-0 R-0 DISCH_ERR RESET KEEP_OUT TSD OV_VOLT BACK_V OV_LIM bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 ERR: Error Detection Status bit(1,2) Indicates that an error was detected and the device has entered the Error state. Writing this bit to a ‘0’ will clear the Error state and allows the device to be returned to the Active state. When written to ‘0’, all error conditions are checked. If all error conditions have been removed, the UCS1003-1 returns to the Active state. This bit is set automatically by the UCS1003-1 when the Error state is entered. Regardless of the Fault handling mechanism used, if any other bit is set in the Interrupt Status register (10h), the device will not leave the Error state. This bit is cleared automatically by the UCS1003-1 if the auto-recovery Fault handling functionality is active and no error conditions are detected. Likewise, this bit is cleared when the PWR_EN control is disabled. 1 = One or more errors have been detected and the UCS1003-1 has entered the Error state 0 = There are no errors detected. bit 6 DISCH_ERR: Discharge VBUS Error Status bit Indicates that the UCS1003-1 was unable to discharge the VBUS node. This bit will be cleared when read if the error condition has been removed or if the ERR bit is cleared. This bit will cause the ALERT# pin to be asserted and the device to enter the Error state. 1 = UCS1003-1 was unable to discharge the VBUS node 0 = No VBUS discharge error. bit 5 RESET: Reset Status bit Indicates that UCS1003-1 has just been reset and should be reprogrammed. This bit will be set at power-up. This bit is cleared when read or when the PWR_EN control is toggled. The ALERT# pin is not asserted when this bit is set. This data is retained in the Sleep state. 1 = UCS1003-1 has just been reset 0 = Reset did not occur. bit 4 KEEP_OUT: V-I Output on VBUS Pins Status bit Indicates that the V-I output on the VBUS pins has dropped below VBUS_MIN. This bit will be cleared when read if the error condition has been removed or if the ERR bit is cleared. This bit will cause the ALERT# pin to be asserted and the device to enter the Error state. 1 = VBUS < VBUS_MIN 0 = VBUS > VBUS_MIN bit 3 TSD: TTSD Threshold Internal Temperature Status bit Indicates that the internal temperature has exceeded the TTSD threshold and the device has entered the Error state. This bit will be cleared when read if the error condition has been removed or if the ERR bit is cleared. This bit will cause the ALERT# pin to be asserted and the device to enter the Error state. 1 = Internal temperature > TTSD 0 = Internal temperature < TTSD Note 1: 2: If the auto-recovery Fault handling is not used, the ERR bit must be written to a logic ‘0’ to be cleared. It will also be cleared when the PWR_EN control is disabled. Note that the ERR bit does not necessarily reflect the ALERT# pin status. The ALERT# pin may be cleared or asserted without the ERR bit changing states. DS20005346B-page 66  2014-2015 Microchip Technology Inc. UCS1003-1/2/3 REGISTER 10-3: INTERRUPT STATUS REGISTER (ADDRESS 10h) (CONTINUED) bit 2 OV_VOLT: VS_OV Threshold Voltage Status bit Indicates that the VS voltage has exceeded the VS_OV threshold and the device has entered the Error state. This bit will be cleared when read if the error condition has been removed or if the ERR bit is cleared. This bit will cause the ALERT# pin to be asserted and the device to enter the Error state. 1 = VS > VS_OV 0 = VS < VS_OV bit 1 BACK_V: VBUS Voltage Status bit Indicates that the VBUS voltage has exceeded the VS or VDD voltages by more than 150 mV. This bit will be cleared when read if the error condition has been removed or if the ERR bit is cleared. This bit will cause the ALERT# pin to be asserted and the device to enter the Error state. 1 = VBUS > VS, or VBUS > VDD by more than 150 mV 0 = VBUS voltage has not exceeded the VS and VDD voltages by more than 150 mV bit 0 OV_LIM: IBUS Current Threshold Status bit Indicates that the IBUS current has exceeded both the ILIM threshold and the IBUS_R2MIN threshold settings. This bit will be cleared when read if the error condition has been removed or if the ERR bit is cleared. This bit will cause the ALERT# pin to be asserted and the device to enter the Error state. 1 = IBUS > ILIM and IBUS_R2MIN 0 = IBUS has not exceeded both ILIM threshold and the IBUS_R2MIN threshold settings Note 1: 2: If the auto-recovery Fault handling is not used, the ERR bit must be written to a logic ‘0’ to be cleared. It will also be cleared when the PWR_EN control is disabled. Note that the ERR bit does not necessarily reflect the ALERT# pin status. The ALERT# pin may be cleared or asserted without the ERR bit changing states.  2014-2015 Microchip Technology Inc. DS20005346B-page 67 UCS1003-1/2/3 REGISTER 10-4: GENERAL STATUS REGISTER (ADDRESS 11h) R-0 U-0 U-0 R-0 R-0 R/C-0 R/C-0 R/C-0 RATION — — CC_MODE TREG LOW_CUR REM ATT bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit C = Clear on Read bit -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 RATION: Programmed Power Amount Delivery Status bit Indicates that the UCS1003-1 has delivered the programmed amount of power to a portable device. If the RATION_BEH bits are set to interrupt the host, this bit will cause the ALERT# pin to be asserted. This bit is cleared when read. This bit is also cleared automatically when the RTN_RST bit is set or the RTN_EN bit is cleared (see Section 10.4.1 “General Configuration Register”). 1 = UCS1003-1 has delivered the programmed amount of power to a portable device 0 = UCS1003-1 has not delivered the programmed amount of power to a portable device bit 6-5 Unimplemented: Read as ‘0’ bit 4 CC_MODE: IBUS Current Indication Status bit Indicates that the IBUS current has exceeded ILIM. Current is in Region 2 (IBUS_R2MIN). 1 = IBUS > ILIM 0 = IBUS < ILIM bit 3 TREG: TREG Internal Temperature Indication Status bit Indicates that the internal temperature has exceeded TREG and that the current limit has been reduced. This bit is cleared when read and will not cause the ALERT# pin to be asserted unless the ALERT_LINK bit is set. 1 = Internal temperature > TREG 0 = Internal temperature < TREG bit 2 LOW_CUR: Portable Device Charge Current Indication Status bit Indicates that a portable device has reduced its charge current to below ~6.4 mA and may be finished charging. This bit is cleared when read and will not cause the ALERT# pin to be asserted unless the ALERT_LINK bit is set. 1 = IBUS < 6.4 mA 0 = IBUS > 6.4 mA bit 1 REM: Removal Detection Event Status bit Indicates that a Removal Detection event has occurred and there is no longer a portable device present. This bit is cleared when read and will not cause the ALERT# pin to be asserted. It will cause the A_DET# pin to be released. 1 = Removal detected 0 = No removal detected bit 0 ATT: Attach Detection Event Status bit Indicates that an Attach Detection event has occurred and there is a new portable device present. This bit is cleared when read and will not cause the ALERT# pin to be asserted. It will cause the A_DET# pin to be asserted. 1 = Attach detected 0 = No attach detected DS20005346B-page 68  2014-2015 Microchip Technology Inc. UCS1003-1/2/3 10.3.1 PROFILE STATUS 1 REGISTER These bits are indicators only and will not cause the ALERT# pin or A_DET# pin to change states. The CUST, DCP, CDP and PT bits are cleared under the following circumstances: REGISTER 10-5: • The PWR_EN control is disabled • A new Active mode is selected • A Removal Detection event occurs PROFILE STATUS 1 REGISTER (ADDRESS 12h) R-0 U-0 U-0 R-0 R-0 R-0 R-0 R-0 NO_HS(1) — — VS_LOW CUST DCP CDP PT(2) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown NO_HS: No Handshake Status bit(1) The NO_HS bit is only set during the Dedicated Charger Emulation Cycle mode (see Section 9.10 “No Handshake (UCS1003-1 only)”). This bit is automatically cleared whenever a new charger emulation profile is applied. 1 = No handshake at the end of the DCE Cycle 0 = A new charger emulation profile has been applied bit 7 bit 6-5 Unimplemented: Read as ‘0’ bit 4 VS_LOW: VS_UVLO Voltage Threshold Status bit Indicates that the VS voltage is below the VS_UVLO threshold and the port power switch is held off. This bit is cleared automatically when the VS voltage is above the VS_UVLO threshold. 1 = VS < VS_UVLO 0 = VS > VS_UVLO bit 3 CUST: Custom Charger Emulation Profile Status bit Indicates that the portable device successfully performed a handshake with the user-defined custom charger emulation profile during the DCE Cycle and is charging. Based on the custom charger emulation profile configuration, the high-speed switch will either be open or closed (see Section 10.13 “Custom Emulation Configuration Registers”). The port power switch Current-Limiting mode is determined by the Custom Current Limiting Behavior Configuration register settings (see Section 10.14.2 “Custom Current-Limiting Behavior Configuration Register”). 1 = Custom profile handshake completed 0 = No custom profile handshake bit 2 DCP: DCP Charger Emulation Profile Status bit Indicates that the portable device accepted the BC1.2 DCP charger emulation profile and is charging. The high-speed switch will be controlled via the HSW_DCE bit (see Section 10.4.5 “High-Speed Switch Configuration Register”) and the port power switch will use Constant-Current Limiting. 1 = DCP handshake completed 0 = No DCP handshake Note 1: 2: The NO_HS bit does not indicate that a portable device is drawing current and it may be cleared to ‘0’ (indicating a handshake), and a portable device not charge. This bit is set at the end of each charger emulation profile if a portable device does not handshake with it. This bit will not be set at the same time that any other Profile Status register bits are set. When the UCS1003-1 is configured as a data pass-through and a removal event and then an Attach event occurs without changing the Active mode, the PT bit will not be set again, even though the UCS1003-1 is still operating as a data pass-through as configured. Toggling the M1 control will re-enable the PT status bit.  2014-2015 Microchip Technology Inc. DS20005346B-page 69 UCS1003-1/2/3 REGISTER 10-5: PROFILE STATUS 1 REGISTER (ADDRESS 12h) (CONTINUED) bit 1 CDP: CDP Charger Emulation Profile Status bit Indicates that the portable device successfully performed a handshake with the BC1.2 CDP charger emulation profile and is charging. The high-speed switch will be closed and the port power switch will use Trip Current Limiting. 1 = CDP handshake completed 0 = No CDP handshake bit 0 PT: Data Pass-Through/SDP Active Mode Status bit(2) Indicates that the UCS1003-1 is in the Data Pass-Through or BC1.2 SDP Active mode. The high-speed switch will be closed and the port power switch will use Trip Current Limiting. 1 = UCS1003-1 is in the Data Pass-Through or BC1.2 SDP Active mode. 0 = UCS1003-1 is not in the Data Pass-Through or BC1.2 SDP Active mode. Note 1: 2: The NO_HS bit does not indicate that a portable device is drawing current and it may be cleared to ‘0’ (indicating a handshake), and a portable device not charge. This bit is set at the end of each charger emulation profile if a portable device does not handshake with it. This bit will not be set at the same time that any other Profile Status register bits are set. When the UCS1003-1 is configured as a data pass-through and a removal event and then an Attach event occurs without changing the Active mode, the PT bit will not be set again, even though the UCS1003-1 is still operating as a data pass-through as configured. Toggling the M1 control will re-enable the PT status bit. DS20005346B-page 70  2014-2015 Microchip Technology Inc. UCS1003-1/2/3 10.3.2 PROFILE STATUS 2 REGISTER These bits indicate which profile was accepted. These bits are indicators only and will not cause the ALERT# pin or A_DET# pin to change states. These bits are cleared under the following circumstances: REGISTER 10-6: • The PWR_EN control is disabled • A new Active mode is selected • A Removal Detection event occurs PROFILE STATUS 2 REGISTER (ADDRESS 13h) U-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 — LG7 LG6 LG5 LG4 LG3 LG2 LG1 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 Unimplemented: Read as ‘0’ bit 6 LG7: Legacy 7 Charger Emulation Profile Status bit Indicates that the portable device successfully performed a handshake with the Legacy 7 charger emulation profile and is charging. The high-speed switch will be controlled via the HSW_DCE bit (see Section 10.4.5 “High-Speed Switch Configuration Register”). The port power switch Current-Limiting mode is determined by the Custom Current-Limiting Behavior register settings (see Section 10.14.2 “Custom Current-Limiting Behavior Configuration Register”). 1 = Handshake successful with the Legacy 7 charger emulation profile and charging 0 = Not charging with Legacy 7 charger emulation profile bit 5 LG6: Legacy 6 Charger Emulation Profile Status bit Indicates that the portable device successfully performed a handshake with the Legacy 6 charger emulation profile and is charging. The high-speed switch will be controlled via the HSW_DCE bit (see Section 10.4.5 “High-Speed Switch Configuration Register”). The port power switch Current-Limiting mode is determined by the Custom Current-Limiting Behavior register settings (see Section 10.14.2 “Custom Current-Limiting Behavior Configuration Register”). 1 = Handshake successful with the Legacy 6 charger emulation profile and charging 0 = Not charging with Legacy 6 charger emulation profile bit 4 LG5: Legacy 5 Charger Emulation Profile Status bit Indicates that the portable device successfully performed a handshake with the Legacy 5 charger emulation profile and is charging. The high-speed switch will be controlled via the HSW_DCE bit (see Section 10.4.5 “High-Speed Switch Configuration Register”). The port power switch Current-Limiting mode is determined by the Custom Current-Limiting Behavior register settings (see Section 10.14.2 “Custom Current-Limiting Behavior Configuration Register”). 1 = Handshake successful with the Legacy 5 charger emulation profile and charging 0 = Not charging with Legacy 5 charger emulation profile bit 3 LG4: Legacy 4 Charger Emulation Profile Status bit Indicates that the portable device successfully performed a handshake with the Legacy 4 charger emulation profile and is charging. The high-speed switch will be controlled via the HSW_DCE bit (see Section 10.4.5 “High-Speed Switch Configuration Register”). The port power switch Current-Limiting mode is determined by the Custom Current-Limiting Behavior register settings (see Section 10.14.2 “Custom Current-Limiting Behavior Configuration Register”). 1 = Handshake successful with the Legacy 4 charger emulation profile and charging 0 = Not charging with Legacy 4 charger emulation profile  2014-2015 Microchip Technology Inc. DS20005346B-page 71 UCS1003-1/2/3 REGISTER 10-6: PROFILE STATUS 2 REGISTER (ADDRESS 13h) (CONTINUED) bit 2 LG3: Legacy 3 Charger Emulation Profile Status bit Indicates that the portable device successfully performed a handshake with the Legacy 3 charger emulation profile and is charging. The high-speed switch will be controlled via the HSW_DCE bit (see Section 10.4.5 “High-Speed Switch Configuration Register”). The port power switch Current-Limiting mode is determined by the Custom Current-Limiting Behavior register settings (see Section 10.14.2 “Custom Current-Limiting Behavior Configuration Register”). 1 = Handshake successful with the Legacy 3 charger emulation profile and charging 0 = Not charging with Legacy 3 charger emulation profile bit 1 LG2: Legacy 2 Charger Emulation Profile Status bit Indicates that the portable device successfully performed a handshake with the Legacy 2 charger emulation profile and is charging. The high-speed switch will be controlled via the HSW_DCE bit (see Section 10.4.5 “High-Speed Switch Configuration Register”). The port power switch Current-Limiting mode is determined by the Custom Current-Limiting Behavior register settings (see Section 10.14.2 “Custom Current-Limiting Behavior Configuration Register”). 1 = Handshake successful with the Legacy 2 charger emulation profile and charging 0 = Not charging with Legacy 2 charger emulation profile bit 0 LG1: Legacy 1 Charger Emulation Profile Status bit Indicates that the portable device successfully performed a handshake with the Legacy 1 charger emulation profile and is charging. The high-speed switch will be controlled via the HSW_DCE bit (see Section 10.4.5 “High-Speed Switch Configuration Register”). The port power switch Current-Limiting mode is determined by the Custom Current-Limiting Behavior register settings (see Section 10.14.2 “Custom Current-Limiting Behavior Configuration Register”). 1 = Handshake successful with the Legacy 1 charger emulation profile and charging 0 = Not charging with Legacy 1 charger emulation profile DS20005346B-page 72  2014-2015 Microchip Technology Inc. UCS1003-1/2/3 10.3.3 PIN STATUS REGISTER The Pin Status register reflects the current pin state of the external control pins, as well as identifying the power state. These bits are linked to the X_SET bits (see Section 10.4.3 “Switch Configuration Register”). REGISTER 10-7: PIN STATUS REGISTER (ADDRESS 14h) U-0 R-0 R-0 R-0 R-0 R-0 — PWR_EN_PIN M2_PIN M1_PIN EM_EN_PIN SEL_PIN R-0 R-0 PWR_STATE(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 Unimplemented: Read as ‘0’ bit 6 PWR_EN_PIN: PWR_EN Pin Control Status bit Reflects the PWR_EN control state. This bit is set and cleared automatically as the PWR_EN pin/PWR_ENS bit state changes. 1 = PWR_EN is logic ‘1’ 0 = PWR_EN is logic ‘0’ bit 5 M2_PIN: M2 Pin Control Status bit Reflects the M2 pin state. This bit is set and cleared automatically as the M2 pin/M2_SET state changes. 1 = M2 is logic ‘1’ 0 = M2 is logic ‘0’ bit 4 M1_PIN: M1 Pin Control Status bit Reflects the M1 pin state. This bit is set and cleared automatically as the M1 pin/M1_SET state changes. 1 = M1 is logic ‘1’ 0 = M1 is logic ‘0’ bit 3 EM_EN_PIN: EM_EN Pin Control Status bit Reflects the EM_EN pin state. This bit is set and cleared automatically as the EM_EN pin/EM_EN_SET state changes. 1 = EM_EN is logic ‘1’ 0 = EM_EN logic ‘0’ bit 2 SEL_PIN: SEL Pin Control Status bit Reflects the polarity settings determined by the SEL pin decode. This bit is set or cleared automatically upon device power-up as the SEL pin is decoded. 1 = The PWR_EN control is active-high 0 = The PWR_EN control is active-low bit 1-0 PWR_STATE: Power State Control Status bits(1) Indicates the current power state. These bits are set and cleared automatically as the power state changes. 00 = Sleep 01 = Detect 10 = Active 11 = Error Note 1: Accessing the SMBus/I2C causes the UCS1003-1 to leave the Sleep state. As a result, the PWR_STATE bits will never read as ‘00b’.  2014-2015 Microchip Technology Inc. DS20005346B-page 73 UCS1003-1/2/3 10.4 Configuration Registers Name General Configuration Emulation Configuration Switch Configuration Attach Detect Configuration High-Speed Switch Configuration Bits Address Cof Default 8 8 8 8 8 15h 16h 17h 18h 25h R/W R/W R/W R/W R/W 01h 8Ch 04h 46h 14h The Configuration registers control basic device functionality. 10.4.1 GENERAL CONFIGURATION REGISTER The contents of this register are retained in Sleep. REGISTER 10-8: GENERAL CONFIGURATION REGISTER (ADDRESS 15h) R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 ALERT_MASK — ALERT_LINK DSCHG RTN_EN RTN_RST R/W-0 R/W-1 RATION_BEH bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 ALERT_MASK: ALERT# Pin Assertion bit 1 = The ALERT# pin will not be asserted in the event of an error condition 0 = The ALERT# pin will be asserted if an error condition or indicator event is detected bit 6 Unimplemented: Read as ‘0’ bit 5 ALERT_LINK: ALERT# Pin LOW_CUR/TREG Link Assertion bit 1 = The ALERT# pin will be asserted if the LOW_CUR or TREG indicator bit is set 0 = The ALERT# pin will not be asserted if the LOW_CUR or TREG indicator bit is set bit 4 DSCHG: VBUS Discharge bit Forces the VBUS to be reset and discharged when the UCS1003-1 is in the Active state. Writing this bit to a logic ‘1’ will cause the port power switch to be opened and the discharge circuitry to activate to discharge VBUS. The port power switch will remain open while this bit is ‘1’. This bit is not self-clearing. bit 3 RTN_EN: Charge Rationing Enable bit 1 = Charge rationing is enabled (see Section 7.4 “Battery Full (UCS1003-1 Only)”) 0 = Charge rationing is disabled. The Total Accumulated Charge registers will be cleared to 00_00h and current data will no longer be accumulated. If the Total Accumulated Charge registers have already reached the Charge Rationing Threshold (see Section 10.6 “Charge Rationing Threshold Registers”), the applied response will be removed as if the charge rationing had been reset. This will also clear the RATION status bit (if set). bit 2 RTN_RST: Charge Rationing Reset bit When this bit is set to ‘1’, the Total Accumulated Charge registers are reset to 00_00h. In addition, when this bit is set, the RATION status bit will be cleared, and if there are no other errors or active indicators, the ALERT# pin will be released. 1 = EM_EN is logic ‘1’ 0 = EM_EN is logic ‘0’ bit 1-0 RATION_BEH: Power Rationing Threshold Control bit (see Table 7-2) 00 = Report 01 = Report and disconnect 10 = Disconnect and go to Sleep 11 = Ignore DS20005346B-page 74  2014-2015 Microchip Technology Inc. UCS1003-1/2/3 10.4.2 EMULATION CONFIGURATION REGISTER The contents of this register are retained in Sleep. REGISTER 10-9: EMULATION CONFIGURATION REGISTER (ADDRESS 16h) R/W-1 U-0 U-0 DIS_TO — — R/W-0 R/W-1 EM_TO_DIS(1) EM_RETRY R/W-1 EM_RESP(2) R/W-0 R/W-0 EM_RESET_TIME bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 DIS_TO: Disable Time-out and Idle Reset bit (see Section 11.2.1.6 “SMBus Time-out and Idle Reset”) 1 = The Time-out and Idle Reset functionality is disabled; this is used for I2C compliance 0 = The Time-out and Idle Reset functionality is enabled bit 6-5 Unimplemented: Read as ‘0’ bit 4 EM_TO_DIS: Emulation Time-out Disable bit(1) Disables the emulation circuitry time-out for all charger emulation profiles in the DCE Cycle. There is a separate bit to enable/disable the emulation time-out for the custom charger emulation profile (Register 10-35); however, if the EM_TO_DIS bit is set, the emulation time-out will also be disabled for the custom charger emulation profile. 1 = Emulation time-out is disabled during the DCE Cycle. The applied charger emulation profile will not exit as a result of an emulation time-out event. The IBUS current will be checked continuously, and if it exceeds the IBUS_CHG threshold for any reason, the charger emulation profile will be accepted. 0 = Emulation time-out is enabled during the DCE Cycle. An individual charger emulation profile will be applied and maintained for the duration of the tEM_TIMEOUT value. When this timer expires, the UCS1003-1 will determine whether the charger emulation profile was successful and take appropriate action. bit 3 EM_RETRY: Dedication Charger Emulation bit Configures whether the DCE Cycle will reset and restart if it reaches the final profile without the portable device drawing charging current, and accepting one of the profiles. This bit is only used if the UCS1003-1 is configured to emulate a dedicated charger. 1 = Once the DCE Cycle is completed, it will perform emulation Reset and restart from the first enabled charger emulation profile in the DCE Cycle. 0 = Once the DCE Cycle is completed, it will not restart. The DPOUT and DMOUT will be left as High Z pins and the port power switch will be closed. The Current-Limiting mode is determined by the Custom Current Limiting Behavior settings (see Section 10.14.2 “Custom Current-Limiting Behavior Configuration Register”). Note 1: 2: If the EM_TO_DIS bit is set and the Legacy 1, Legacy 3 or custom charger emulation profiles were accepted during the DCE cycle, a removal is not detected. To avoid this issue, re-enable the emulation time-out after applying any test profiles and charging with the ‘final’ profile. If the HSW_DCE bit is set, the high-speed switch will be closed regardless of the status of the EM_RESP bit. Leaving the emulation response applied will not allow normal USB traffic. Therefore, prior to setting the HSW_DCE bit, this bit should be cleared.  2014-2015 Microchip Technology Inc. DS20005346B-page 75 UCS1003-1/2/3 REGISTER 10-9: EMULATION CONFIGURATION REGISTER (ADDRESS 16h) (CONTINUED) bit 2 EM_RESP: Leave Emulation Response bit(2) Enables the Dedicated Charger Emulation Cycle mode to hold the DPOUT and DMOUT stimulus response after the UCS1003-1 has finished emulation using the Legacy, BC1.2 DCP or custom charger emulation profiles. 1 = If a portable device begins drawing charging current while the UCS1003-1 is applying the BC1.2 DCP, Custom or any of the Legacy charger emulation profiles during the DCE Cycle, the last response applied will be kept in place until a Removal Detection event occurs, the internal temperature exceeds the TREG value or emulation is restarted. In the case of the BC1.2 DCP or Legacy 2 charger emulation profiles, this will be the short (RDCP_RES). In the case of the Legacy 1 or Legacy 3-7 profiles, this will be the DPOUT and DMOUT pin voltages. If a portable device does not draw charging current, the DCE Cycle will behave normally. 0 = The dedicated emulation circuitry will behave normally. It will remove the short condition when the tEM_TIMEOUT timer has expired, regardless if the portable device has drawn charging current or not. bit 1-0 EM_RESET_TIME: tEM_RESET Length Time bit Determines the length of the tEM_RESET time (see Section 9.8.1 “Emulation Reset”) as shown below. The value selected does not include discharge time; however, this value plus discharge result in the actual Reset time. 00 = 50 ms 01 = 75 ms 10 = 125 ms 11 = 175 ms Note 1: 2: If the EM_TO_DIS bit is set and the Legacy 1, Legacy 3 or custom charger emulation profiles were accepted during the DCE cycle, a removal is not detected. To avoid this issue, re-enable the emulation time-out after applying any test profiles and charging with the ‘final’ profile. If the HSW_DCE bit is set, the high-speed switch will be closed regardless of the status of the EM_RESP bit. Leaving the emulation response applied will not allow normal USB traffic. Therefore, prior to setting the HSW_DCE bit, this bit should be cleared. DS20005346B-page 76  2014-2015 Microchip Technology Inc. UCS1003-1/2/3 10.4.3 SWITCH CONFIGURATION REGISTER The contents of this register are retained in Sleep. REGISTER 10-10: SWITCH CONFIGURATION REGISTER (ADDRESS 17h) R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-1 R/W-0 R/W-0 PIN_IGN — EM_EN_SET M2_SET M1_SET S0_SET PWR_ENS LATCHS bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 x = Bit is unknown PIN_IGN: Pin Ignore Selection Mode Determination bit Ignores the M1, M2, PWR_EN and EM_EN pin states when determining the Active mode selection and power state. 1 = The Active mode selection and power state will be set by the individual control bits and not by the M1, M2, PWR_EN and EM_EN pin states; these pin states are ignored. 0 = The Active mode selection and power state will be set by the OR’d combination of the M1, M2, PWR_EN and EM_EN pin states and the corresponding bit states. bit 6 Unimplemented: Read as ‘0’ bit 5 EM_EN_SET: EM_EN Pin Selection Mode Determination bit In conjunction with other controls, determines the Active mode that is selected (see Section 9.2 “Active Mode Selection”) and power state (see Table 5-2). This bit is OR’d with the EM_EN pin. bit 4 M2_SET: M2 Pin Selection Mode Determination bit In conjunction with other controls, determines the Active mode that is selected (see Section 9.2 “Active Mode Selection”) and power state (see Table 5-2). This bit is OR’d with the M2 pin. bit 3 M1_SET: M1 Pin Selection Mode Determination bit In conjunction with other controls, determines the Active mode that is selected (see Section 9.2 “Active Mode Selection”) and power state (see Table 5-2). This bit is OR’d with the M1 pin. bit 2 S0_SET: SMBus Mode Attach/Removal Detection bit In SMBus mode, enables the Attach and Removal Detection feature and affects the power state (see Section 9.2 “Active Mode Selection”). 1 = Detection is enabled; also see Table 5-2 0 = Detection is not enabled; also see Table 5-2 bit 1 PWR_ENS: Port Power Switch State bit Controls whether the port power switch may be turned on or not and affects the power state (see Section 5.3.4 “PWR_EN Input”). This bit is OR’d with the PWR_EN pin and the polarity of both are controlled by SEL pin decode. Thus, if the polarity is set to active-high, either the PWR_EN pin or this bit must be ‘1’ to enable the port power switch. bit 0 LATCHS: SMBus Mode Fault Handling Routine Control bit In SMBus mode, controls the Fault handling routine that is used in the case that an error is detected (see Section 5.3.5 “Latch Input”). 1 = The UCS1003-1 will latch its error conditions; in order for the device to return to normal Active state, the ERR bit must be cleared by the user 0 = The UCS1003-1 will automatically retry when an error condition is detected  2014-2015 Microchip Technology Inc. DS20005346B-page 77 UCS1003-1/2/3 10.4.4 ATTACH DETECTION CONFIGURATION RESISTER The contents of this register are retained in Sleep. REGISTER 10-11: ATTACH DETECTION CONFIGURATION REGISTER (ADDRESS 18h) R/W-0 R/W-1 R/W-0 RESERVED R/W-0 R/W-0 R/W-1 DISCHG_TIME_SEL R/W-1 R/W-0 ATT_TH(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-4 Reserved: Do not change bit 3-2 DISCHG_TIME_SEL: tDISCHARGE Time Setting bits 00 = 100 ms 01 = 200 ms 10 = 300 ms 11 = 400 ms bit 1-0 ATT_TH: Attach/Removal Detection Threshold bits(1) Determines the Attach Detection threshold (IDET_QUAL) and Removal Detection thresholds (IREM_QUAL_DET and IREM_QUAL_ACT) as shown below. 00 = 200 µA Attach, 100 µA Removal Threshold 01 = 400 µA Attach, 300 µA Removal Threshold 10 = 800 µA Attach, 700 µA Removal Threshold 11 = 1000 µA Attach, 900 µA Removal Threshold Note 1: The Removal Threshold is different when operating in the Active power state versus when operating in the Detect power state. DS20005346B-page 78  2014-2015 Microchip Technology Inc. UCS1003-1/2/3 10.4.5 HIGH-SPEED SWITCH CONFIGURATION REGISTER The contents of this register are retained in Sleep. REGISTER 10-12: HIGH-SPEED SWITCH CONFIGURATION REGISTER (ADDRESS 25h) U-0 U-0 U-0 R/W-1 R/W-0 R/W-1 R/W-0 R/W-0 — — — RESERVED HSW_CUST HSW_CDP HSW_DET HSW_DCE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-5 Unimplemented: Read as ‘0’ bit 4 Reserved: Do not change bit 3 HSW_CUST: Custom Handshake USB High-Speed Data Switch Enable bit Enables the USB high-speed data switch to be active during the custom handshake. This control is checked at the beginning of charger emulation. Therefore, changing this control during emulation will have no immediate effect. Upon restarting charger emulation (as a result of the EM_RETRY bit being set, a Removal Detection event or change of emulation controls), the high-speed switch will close. 1 = The USB high-speed data switch is enabled while the custom charger emulation profile is applied; also, if the custom charger emulation profile is accepted during the Dedicated Charger Emulation Cycle mode, the high-speed switch will stay closed 0 = The USB high-speed data switch is disabled while the custom charger emulation profile is applied bit 2 HSW_CDP: CDP Handshake USB High-Speed Data Switch Enable bit Enables the USB high-speed data switch to be active during the CDP handshake. This control is checked at the beginning of charger emulation. Therefore, changing this control during emulation will have no immediate effect. Upon restarting charger emulation (as a result of a Removal Detection event or change of emulation controls), the high-speed switch will close. 1 = The USB high-speed data switch is enabled during the CDP handshake 0 = The USB high-speed data switch is disabled during the CDP handshake bit 1 HSW_DET: Detect Power State USB High-Speed Data Switch Enable bit Enables the USB high-speed data switch to be active during the Detect power state. If the S0 control is set to ‘0’, this bit is ignored. 1 = The USB high-speed data switch will be closed during the Detect power state 0 = The USB high-speed data switch is open during the Detect power state bit 0 HSW_DCE: DCP Charger Emulation Profile USB High-Speed Data Switch Enable bit Enables the USB high-speed data switch after the DCP charger emulation profile or one of the Legacy charger emulation profiles was accepted during the DCE Cycle and the portable device is charging. This bit is ignored if the UCS1003-1 is not in the Active state. This bit will not cause the high-speed switch to be closed during emulation when the DCP and Legacy profiles are applied, only after the DCP or a Legacy charger emulation profile has been accepted. 1 = The USB high-speed data switch will be closed 0 = The USB high-speed data switch will be open  2014-2015 Microchip Technology Inc. DS20005346B-page 79 UCS1003-1/2/3 10.5 Current Limit Register Name Bits Address Current Limit 8 19h Cof Default R/W 00h The Current Limit register controls the ILIM used by the port power switch. The default setting is based on the resistor on the COMM_SEL/ILIM pin and this value cannot be changed to be higher than the hardware set value. The contents of this register are retained in Sleep. REGISTER 10-13: CURRENT LIMIT REGISTER (ADDRESS 19h) U-0 U-0 U-0 U-0 U-0 — — — — — R/W-0 R/W-0 R/W-0 ILIM_SW(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-3 Unimplemented: Read as ‘0’ bit 2-0 ILIM_SW: ILIM Value Setting bits(1) 000 = 0.57A 001 = 1.00A 010 = 1.13A 011 = 1.35A 100 = 1.68A 101 = 2.05A 110 = 2.28A 111 = 2.85A (3.0A maximum) Note 1: x = Bit is unknown Unless otherwise indicated, the values specified are the typical ILIM in Table 1-2. DS20005346B-page 80  2014-2015 Microchip Technology Inc. UCS1003-1/2/3 10.6 Charge Rationing Threshold Registers Name Bits Address Cof Default Charge Rationing Threshold High Byte 8 1Ah R/W FFh Charge Rationing Threshold Low Byte 8 1Bh R/W FFh The Charge Rationing Threshold registers set the maximum allowed charge that will be delivered to a portable device. Every time the Total Accumulated Charge registers are updated, the value is checked against this limit. If the value meets or exceeds this limit, the RATION bit is set (see Section 10.4.1 “General Configuration Register”) and action taken according to the RATION_BEH bits (see Section 10.4.1 “General Configuration Register”). The units are in mAh, with a range from 0 to ~218429. The contents of this register are retained in Sleep. REGISTER 10-14: CHARGE RATIONING THRESHOLD (ADDRESS 1Ah-1Bh) R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 CHTHR bit 15 bit 8 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 CHTHR bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-0 x = Bit is unknown CHTHR: Charge Rationing Threshold bits LSB = 3.333 mAh  2014-2015 Microchip Technology Inc. DS20005346B-page 81 UCS1003-1/2/3 10.7 Auto-Recovery Configuration Register Name Bits Address Cof Default Auto-Recovery Configuration 8 1Ch R/W 2Ah The contents of this register are retained in Sleep. Once the auto-recovery Fault handling algorithm has checked the overtemperature and backdrive conditions, it will set the ILIM value to ITEST, and then turn on the port power switch and start the tRST timer. If, after the timer has expired, the VBUS voltage is less than VTEST, then it is assumed that a short-circuit condition is present and the Error state is reset. The Auto-Recovery Configuration register sets the parameters used when the auto-recovery Fault handling algorithm is invoked (see Section 7.5.1 “Auto-Recovery Fault Handling”). REGISTER 10-15: AUTO-RECOVERY CONFIGURATION REGISTER (ADDRESS 1Ch) U-0 R/W-0 — R/W-1 R/W-0 TCYCLE R/W-1 R/W-0 TRST_SW R/W-1 R/W-0 VTST_SW bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 Unimplemented: Read as ‘0’ bit 6-4 TCYCLE: Delay Cycle Time bits Defines the delay (tCYCLE) after the Error state is entered before the auto-recovery Fault handling algorithm is started, as shown below. 000 = 15 ms 001 = 20 ms 010 = 25 ms 011 = 30 ms 101 = 40 ms 110 = 45 ms 111 = 50 ms bit 3-2 TRST_SW: tRST Setting Time bits 00 = 10 ms 01 = 15 ms 10 = 20 ms 11 = 25 ms bit 1-0 VTST_SW: VTEST Value Setting bits 00 = 250 mV 01 = 500 mV 10 = 750 mV 11 = 1000 mV DS20005346B-page 82  2014-2015 Microchip Technology Inc. UCS1003-1/2/3 10.8 IBUS_CHG Configuration Register Name Bits Address IBUS_CHG Configuration 8 1Eh Cof Default R/W 04h The IBUS_CHG Configuration register sets the IBUS_CHG current value. If current greater than IBUS_CHG is detected flowing out of VBUS, emulation is successful. The bit weights are in mA, and the range is from 11.72 mA to 175.8 mA. The contents of this register are not retained in Sleep. REGISTER 10-16: IBUS_CHG CONFIGURATION REGISTER (ADDRESS 1Eh) U-0 U-0 U-0 U-0 — — — — R/W-0 R/W-1 R/W-0 R/W-0 ICHG bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-4 Unimplemented: Read as ‘0’ bit 3-0 ICHGP: IBUS_CHG Current Value bits 1 LSB = 11.72 mA  2014-2015 Microchip Technology Inc. x = Bit is unknown DS20005346B-page 83 UCS1003-1/2/3 10.9 TDET_CHARGE Configuration Register Name Bits Address TDET_CHARGE Configuration 8 1Fh Cof Default R/W 03h The TDET_CHARGE Configuration register controls the tDC_TEMP and tDET_CHARGE timing. The tDC_TEMP timer is started whenever the temperature exceeds TREG. This timer is meant to give the system time to cool at the lower ILIM setting before changing ILIM again. The tDET_CHARGE timer is started whenever the VBUS voltage is discharged and the bypass switch is reactivated. This timer is meant to be a delay to allow the VBUS capacitor to charge before detecting an Attach Detection event. If tDET_CHARGE time is increased greater than 800 ms, larger bus capacitors can be accommodated; however, with a portable device present and PWR_EN disabled, a Removal Detection event, and then another Attach Detection event will occur. The contents of this register are retained in Sleep. REGISTER 10-17: TDET_CHARGE CONFIGURATION REGISTER (ADDRESS 1Fh) U-0 U-0 U-0 — — — R/W-0 R/W-0 R/W-0 DC_TEMP_SET R/W-1 R/W-1 DET_CHARGE_SET bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-5 Unimplemented: Read as ‘0’ bit 4-3 DC_TEMP_SET: tDC_TEMP Time Determination bits 00 = 200 ms 01 = 400 ms 10 = 800 ms 11 = 1600 ms bit 2-0 DET_CHARGE_SET: tDET_CHARGE Time Determination bits 000 = 200 ms 001 = 400 ms 010 = 600 ms 011 = 800 ms 100 = 1000 ms 101 = 1200 ms 110 = 1400 ms 111 = 2000 ms DS20005346B-page 84 x = Bit is unknown  2014-2015 Microchip Technology Inc. UCS1003-1/2/3 The Preloaded Emulation Enable registers enable the charger emulation profiles used by the emulation circuitry. 10.10 Preloaded Emulation Enable Registers Name Bits Address Cof Default BCS Emulation Enable 8 20h R/W 06h Legacy Emulation Enable 8 21h R/W 00h The contents of these registers are retained in Sleep. REGISTER 10-18: BCS EMULATION ENABLE REGISTER (ADDRESS 20h) U-0 U-0 U-0 R/W-0 U-0 — — — DCP_EM_DIS — R/W-1 R/W-1 R/W-0 RESERVED bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-5 Unimplemented: Read as ‘0’ bit 4 DCP_EM_DIS: DCP Charger Emulation Profile in the DCE Cycle Disable bit This bit is ignored if the M1, M2 and EM_EN control settings have selected DCP mode (see Table 9-1). 1 = The BC1.2 DCP charger emulation profile is not enabled during the DCE Cycle 0 = The BC1.2 DCP charger emulation profile is enabled during the Dedicated Charger Emulation Cycle mode bit 3 Unimplemented: Read as ‘0’ bit 2-0 Reserved: Do not change  2014-2015 Microchip Technology Inc. DS20005346B-page 85 UCS1003-1/2/3 REGISTER 10-19: LEGACY EMULATION ENABLE REGISTER (ADDRESS 21h) U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — L7EM_DIS L6EM_DIS L5EM_DIS L4EM_DIS L3EM_DIS L2EM_DIS L1EM_DIS bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 Unimplemented: Read as ‘0’ bit 6 L7EM_DIS: Legacy 7 charger emulation profile Disable bit 1 = The Legacy 7 charger emulation profile is not enabled 0 = The Legacy 7 charger emulation profile is enabled bit 5 L6EM_DIS: Legacy 6 charger emulation profile Disable bit 1 = The Legacy 6 charger emulation profile is not enabled 0 = The Legacy 6 charger emulation profile is enabled bit 4 L7EM_DIS: Legacy 5 charger emulation profile Disable bit 1 = The Legacy 5 charger emulation profile is not enabled 0 = The Legacy 5 charger emulation profile is enabled bit 3 L7EM_DIS: Legacy 4 charger emulation profile Disable bit 1 = The Legacy 4 charger emulation profile is not enabled 0 = The Legacy 4 charger emulation profile is enabled bit 2 L7EM_DIS: Legacy 3 charger emulation profile Disable bit 1 = The Legacy 3 charger emulation profile is not enabled 0 = The Legacy 3 charger emulation profile is enabled bit 1 L7EM_DIS: Legacy 2 charger emulation profile Disable bit 1 = The Legacy 2 charger emulation profile is not enabled 0 = The Legacy 2 charger emulation profile is enabled bit 0 L7EM_DIS: Legacy 1 charger emulation profile Disable bit 1 = The Legacy 1 charger emulation profile is not enabled 0 = The Legacy 1 charger emulation profile is enabled DS20005346B-page 86 x = Bit is unknown  2014-2015 Microchip Technology Inc. UCS1003-1/2/3 10.11 Preloaded Emulation Time-out Configuration Registers Name Name Bits Address Cof Default BCS Emulation Time-out Configuration 8 22h R/W 10h Legacy Emulation Time-out Configuration 1 8 23h R/W B0h Bits Address Cof Default Legacy Emulation Time-out Configuration 2 8 24h R/W 04h The Preloaded Emulation Time-out Configuration registers control the tEM_TIMEOUT setting that is applied whenever the indicated preloaded charger emulation profile is applied during the DCE Cycle. These settings are not used if the EM_TO_DIS bit is set. The contents of this registers are retained in Sleep. REGISTER 10-20: BCS EMULATION TIME-OUT CONFIGURATION REGISTER (ADDRESS 22h) U-0 U-0 — — R/W-0 R/W-1 R/W-0 DCP_EM_TO R/W-0 R/W-0 R/W-0 RESERVED bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-6 Unimplemented: Read as ‘0’ bit 5-4 DCP_EM_TO: BC1.2 DCP tEM_TIMEOUT Setting Definition bits These bits are applied when the BC1.2 DCP charger emulation profile is used during the DCE Cycle. 00 = 0.8s 01 = 1.6s 10 = 6.4s 00 = 12.8s bit 3-0 Reserved: Do not change  2014-2015 Microchip Technology Inc. DS20005346B-page 87 UCS1003-1/2/3 REGISTER 10-21: LEGACY EMULATION TIME-OUT CONFIGURATION 1 REGISTER (ADDRESS 23h) R/W-1 R/W-0 L1EM_TO R/W-1 R/W-1 L2EM_TO R/W-0 R/W-0 L3EM_TO R/W-0 R/W-0 L4EM_TO bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-6 L1EM_TO: Legacy 1 tEM_TIMEOUT Setting Definition bits These bits are applied when the Legacy 1 charger emulation profile is used during the DCE Cycle. 00 = 0.8s 01 = 1.6s 10 = 6.4s 11 = 12.8s bit 5-4 L2EM_TO: Legacy 2 tEM_TIMEOUT Setting Definition bits These bits are applied when the Legacy 2 charger emulation profile is used during the DCE Cycle. 00 = 0.8s 01 = 1.6s 10 = 6.4s 11 = 12.8s bit 3-2 L3EM_TO: Legacy 3 tEM_TIMEOUT Setting Definition bits These bits are applied when the Legacy 3 charger emulation profile is used during the DCE Cycle. 00 = 0.8s 01 = 1.6s 10 = 6.4s 11 = 12.8s bit 1-0 L4EM_TO: LEGACY 4 tEM_TIMEOUT Setting Definition bits These bits are applied when the Legacy 4 charger emulation profile is used during the DCE Cycle. 00 = 0.8s 01 = 1.6s 10 = 6.4s 11 = 12.8s DS20005346B-page 88  2014-2015 Microchip Technology Inc. UCS1003-1/2/3 REGISTER 10-22: LEGACY EMULATION TIME-OUT CONFIGURATION 2 REGISTER (ADDRESS 24h) U-0 U-0 — — R/W-0 R/W-0 L5EM_TO R/W-0 R/W-1 L6EM_TO R/W-0 R/W-0 L7EM_TO bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-6 Unimplemented: Read as ‘0’ bit 5-4 L5EM_TO: Legacy 5 tEM_TIMEOUT Setting Definition bits These bits are applied when the Legacy 5 charger emulation profile is used during the DCE Cycle. 00 = 0.8s 01 = 1.6s 10 = 6.4s 11 = 12.8s bit 3-2 L6EM_TO: Legacy 6 tEM_TIMEOUT Setting Definition bits These bits are applied when the Legacy 6 charger emulation profile is used during the DCE Cycle. 00 = 0.8s 01 = 1.6s 10 = 6.4s 11 = 12.8s bit 1-0 L5EM_TO: Legacy 7 tEM_TIMEOUT Setting Definition bits These bits are applied when the Legacy 7 charger emulation profile is used during the DCE Cycle. 00 = 0.8s 01 = 1.6s 10 = 6.4s 11 = 12.8s  2014-2015 Microchip Technology Inc. DS20005346B-page 89 UCS1003-1/2/3 10.12 Preloaded Emulation Configuration Registers Name Bits Address Cof Default The Preloaded Emulation Configuration registers store the settings loaded from internal memory as required for the preloaded charger emulation profile that is actively being applied. These registers are read-only. Applied Charger Emulation 8 30h R 00h Preloaded Emulation Stimulus 1 – Configuration 1 8 31h R 00h Preloaded Emulation Stimulus 1 – Configuration 2 8 32h R 00h Preloaded Emulation Stimulus 1 – Configuration 3 8 33h R 00h Preloaded Emulation Stimulus 1 – Configuration 4 8 34h R 00h Preloaded Emulation Stimulus 2 – Configuration 1 8 35h R 00h Preloaded Emulation Stimulus 2 – Configuration 2 8 36h R 00h The contents of registers 31h, 35h and 39h are not retained in Sleep. They are updated as needed. Preloaded Emulation Stimulus 2 – Configuration 3 8 37h R 00h The contents of registers 32h, 33h, 34h, 36h, 37h, 38h, 3Ah, 3Bh and 40h are retained in Sleep. Preloaded Emulation Stimulus 2 – Configuration 4 8 38h R 00h Preloaded Emulation Stimulus 3 – Configuration 1 8 39h R 00h Preloaded Emulation Stimulus 3 – Configuration 2 8 3Ah R 00h Preloaded Emulation Stimulus 3 – Configuration 3 8 3Bh R 00h DS20005346B-page 90 The Legacy charger emulation profiles, the BC1.2 SDP, and the BC1.2 DCP charger emulation profiles do not use the Stimulus 3 Configuration registers (39h-3Bh). Whenever these charger emulation profiles are applied, registers 39h-3Bh will not be updated and their contents should be ignored. Whenever a Legacy charger emulation profile is applied within the DCE Cycle, these controls will not be updated and should be ignored. These settings are only used by the BC1.2 CDP and BC1.2 DCP charger emulation profiles.  2014-2015 Microchip Technology Inc. UCS1003-1/2/3 10.12.1 APPLIED CHARGER EMULATION REGISTER The contents of this register are not retained in Sleep. The contents are updated as the charger emulation profile being applied changes. REGISTER 10-23: APPLIED CHARGER EMULATION REGISTER (ADDRESS 30h) U-0 U-0 U-0 U-0 — — — — R-0 R-0 R-0 R-0 PRE_EM_SEL bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-4 Unimplemented: Read as ‘0’ bit 3-0 PRE_EM_SEL: Active Charger Emulation Profile Selection bits Indicates which of the charger emulation profiles is being actively applied, as shown below. 0000 = Data Pass-Through or BC1.2 SDP mode 0001 = BC1.2 CDP 0010 = BC1.2 DCP 0011 = Legacy 1 0100 = Legacy 2 0101 = Legacy 3 0110 = Legacy 4 0111 = Legacy 5 1000 = Legacy 6 1001 = Legacy 7 1010 = Custom profile All others = Not used  2014-2015 Microchip Technology Inc. DS20005346B-page 91 UCS1003-1/2/3 REGISTER 10-24: PRELOADED EMULATION STIMULUS 1 CONFIGURATION 1 REGISTER (ADDRESS 31h) U-0 R-0 — S1_TD_TYPE R-0 R-0 R-0 R-0 S1_TD R-0 R-0 STIM1 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 Unimplemented: Read as ‘0’ bit 6 S1_TD_TYPE: Stimulus 1 Timer Behavior Determination bit 1 = The stimulus timer controls how long the response is applied after the stimulus is detected; the response is applied immediately and held for the duration of the timer then removed (if the stimulus has been removed) 0 = The stimulus timer is a delay from when the stimulus is detected until the response is performed bit 5-3 S1_TD: Stimulus 1 tSTIM_DEL Value Determination bits 000 = 0 ms 001 = 1 ms 010 = 5 ms 011 = 10 ms 100 = 20 ms 101 = 40 ms 110 = 80 ms 111 = 100 ms bit 2-0 STIM1: Stimulus 1 Determination Usage bits Determines the Stimulus 1 that is used as shown below. Note that the lower threshold for the window comparator option is fixed at 400 mV and only applies to the DPOUT pin. This setting cannot be used for the DMOUT port. 000 = (default) VBUS voltage is ready to be applied before port power switch is closed; next stimulus will not wait for this to be removed 001 = DPOUT voltage is higher than the threshold (S1_TH) 010 = Window comparator; DPOUT voltage is lower than the threshold (S1_TH) and DPOUT voltage higher than the fixed threshold 011 = DMOUT voltage is higher than the threshold (S1_TH) 100 = Do not use 101 = Do not use 110 = DPOUT voltage is higher than the threshold (S1_TH) 111 = VBUS voltage is present after port power switch is closed; next stimulus will not wait for this to be removed. DS20005346B-page 92  2014-2015 Microchip Technology Inc. UCS1003-1/2/3 REGISTER 10-25: PRELOADED EMULATION STIMULUS 1 CONFIGURATION 2 REGISTER (ADDRESS 32h) R-0 R-0 R-0 R-0 R-0 S1_R1MAG R-0 R-0 R-0 S1_R1 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-4 x = Bit is unknown S1_R1MAG: Stimulus 1 Response Magnitude bits Determines the magnitude of the response to the stimulus. The bit decode changes meaning based on which response was selected. Data written to any field that is identified as ‘Do not use’ will not be accepted. The data will not be updated and the settings will remain set at the previous value. For S1_R1 Settings 0000-0011: The response is a voltage applied on the DPOUT/DMOUT pins. The S1_R1MAG>3:0> bits specify the voltage relative to ground:. 0000 = Pull-down 0110 = 600 mV 1100 = 1800 mV 0001 = 400 mV 0111 = 700 mV 1101 = 2000 mV 0010 = 400 mV 1000 = 800 mV 1110 = 2200 mV 0011 = 400 mV 1001 = 900 mV 1111 = Do not use 0100 = 400 mV 1010 = 1400 mV 0101 = 500 mV 1011 = 1600 mV For S1_R1 Settings 0100, 0111, 1101-1111: The response is a resistor connected on DPOUT/DMOUT to GND or VBUS. The S1_R1MAG bits specify the resistor value. 0000 = 1.8 k 0110 = 40 k 1100 = 100 k 0001 = 10 k 0111 = 43 k 1101 = 120 k 0010 = 15 k 1000 = 50 k 1110 = 150 k 1111 = Do not use 0011 = 20 k 1001 = 60 k 0100 = 25 k 1010 = 75 k 0101 = 30 k 1011 = 80 k For S1_R1 Settings 0110, 1001, 1100: The response is a voltage divider applied from VBUS to GND with the “center” at DPOUT/DMOUT. The S1_R1MAG bits specify the minimum resistance of the voltage divider (sum of R1 + R2). Note 1: 2: 0000 = 93 k 0110 = 200 k 1100 = 200 k 0001 = 100 k 0111 = 200 k 1101 = 200 k 0010 = 125 k 1000 = 93 k 1110 = 200 k 1111 = Do not use 0011 = 150 k 1001 = 100 k 0100 = 200 k 1010 = 125 k 0101 = 200 k 1011 = 150 k If STIM1 = 000b and no other response was applied to the DPOUT pin, the 15 k pull-down resistor applied to the DPOUT pin during emulation Reset is not removed. Otherwise, the previous response is left on the DPOUT pin (if applicable) or the 15 k pull-down resistor is removed. If STIM1 = 000b and no other response was applied to the DMOUT pin, the 15 k pull-down resistor applied to the DMOUT pin during emulation Reset is not removed. Otherwise, the previous response is left on the DMOUT pin (if applicable) or the 15 k pull-down resistor is removed.  2014-2015 Microchip Technology Inc. DS20005346B-page 93 UCS1003-1/2/3 REGISTER 10-25: PRELOADED EMULATION STIMULUS 1 CONFIGURATION 2 REGISTER (ADDRESS 32h) (CONTINUED) bit 3-0 S1_R1: Stimulus 1 Response Definition bits 0000 = Removes previous response on DPOUT and DMOUT 0001 = Applies voltage on DPOUT(1) 0010 = Applies voltage on DMOUT(2) 0011 = Applies voltage on DPOUT and DMOUT 0100 = Connects resistor from DPOUT to GND(1) 0101 = Do not use 0110 = Connects voltage divider from VBUS to GND with ‘center’ at DPOUT(1) 0111 = Connects resistor from DMOUT to GND(2) 1000 = Do not use 1001 = Connects voltage divider from VBUS to GND with ‘center’ at DMOUT(2) 1010 = Connects  200resistor from DPOUT to DMOUT 1011 = Do not use 1100 = Connects voltage divider from VBUS to GND with ‘center’ at DPOUT and DMOUT 1101 = Connects resistor from DPOUT to GND and DMOUT to GND 1110 = If STIM1 = 000, the 15 kpull-down resistors applied to DPOUT and DMOUT during emulation Reset are not removed. If STIM1 = 111, the 15 kpull-down resistors applied to DPOUT and DMOUT during emulation Reset are removed. For all other STIM1 settings, whatever was applied is not changed. 1111 = Same as ‘1110’ definition above Note 1: 2: If STIM1 = 000b and no other response was applied to the DPOUT pin, the 15 k pull-down resistor applied to the DPOUT pin during emulation Reset is not removed. Otherwise, the previous response is left on the DPOUT pin (if applicable) or the 15 k pull-down resistor is removed. If STIM1 = 000b and no other response was applied to the DMOUT pin, the 15 k pull-down resistor applied to the DMOUT pin during emulation Reset is not removed. Otherwise, the previous response is left on the DMOUT pin (if applicable) or the 15 k pull-down resistor is removed. DS20005346B-page 94  2014-2015 Microchip Technology Inc. UCS1003-1/2/3 REGISTER 10-26: PRELOADED EMULATION STIMULUS 1 CONFIGURATION 3 REGISTER (ADDRESS 33h)(1) U-0 U-0 — — R-0 R-0 R-0 S1_PUPD R-0 R-0 R-0 S1_TH bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-6 Unimplemented: Read as ‘0’ bit 5-4 S1_PUPD: Stimulus 1 Pull-Down Current Magnitude bits Determines the magnitude of the pull-down current applied on the DPOUT and DMOUT pins when the stimulus response is to apply a voltage and the voltage magnitude is set at pull-down (‘0000b’). The bit decode is given below. 00 = 10 µA 01 = 50 µA 10 = 100 µA 11 = 150 µA bit 3-0 S1_TH: Stimulus 1 Threshold Value Definition bits Defines the threshold value, as shown below, for the specified stimulus. If the stimulus VBUS voltage is ready to be applied or applied (i.e., STIM1 = 000b or 111b), the threshold value is ignored. 0000 = 400 mV 0001 = 400 mV 0010 = 400 mV 0011 = 300 mV 0100 = 400 mV 0101 = 500 mV 0110 = 600 mV 0111 = 700 mV 1000 = 800 mV 1001 = 900 mV 1010 = 1400 mV 1011 = 1600 mV 1100 = 1800 mV 1101 = 2000 mV 1110 = 2200 mV 1111 = Do not use Note 1: The Legacy charger emulation profiles do not use these settings. Whenever a Legacy charger emulation profile is applied within the DCE Cycle, these controls will not be updated and should be ignored. These settings are only used by the BC1.2 CDP and DCP charger emulation profiles.  2014-2015 Microchip Technology Inc. DS20005346B-page 95 UCS1003-1/2/3 REGISTER 10-27: PRELOADED EMULATION STIMULUS 1 CONFIGURATION 4 REGISTER (ADDRESS 34h)(1) U-0 U-0 U-0 U-0 U-0 — — — — — R-0 R-0 R-0 S1_RATIO bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-3 Unimplemented: Read as ‘0’ bit 2-0 S1_RATIO: Stimulus 1 Voltage Divider Ratio bits Determines the voltage divider ratio, as shown below, when the stimulus response is set to connect a voltage divider (i.e., S1_R1 = 0110b, 1001b or 1100b). 000 = 0.25 001 = 0.33 010 = 0.4 011 = 0.5 100 = 0.54 101 = 0.6 110 = 0.66 111 = Do not use Note 1: The BC1.2 DCP and CDP charger emulation profiles do not use this control. Whenever the BC1.2 CDP or DCP charger emulation profile is applied, these controls will not be updated and should be ignored. These settings are only used by the Legacy charger emulation profiles. DS20005346B-page 96  2014-2015 Microchip Technology Inc. UCS1003-1/2/3 REGISTER 10-28: PRELOADED EMULATION STIMULUS 2 CONFIGURATION 1 REGISTER (ADDRESS 35h) U-0 R-U — S2_TD_TYPE R-0 R-0 R-0 R-0 S2_TD R-0 R-0 STIM2 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 Unimplemented: Read as ‘0’ bit 6 S2_TD_TYPE: Stimulus 2 Timer Behavior Determination bit 1 = The stimulus timer controls how long the response is applied after the stimulus is detected; the response is applied immediately and held for the duration of the timer, then removed (if the stimulus has been removed) 0 = The stimulus timer is a delay from when the stimulus is detected until the response is performed bit 5-3 S2_TD: Stimulus 2 tSTIM_DEL Determination Value bits 000 = 0 ms 001 = 1 ms 010 = 5 ms 011 = 10 ms 100 = 20 ms 101 = 40 ms 110 = 80 ms 111 = 100 ms bit 2-0 STIM2: Stimulus 2 Determination Usage bits Determines the Stimulus 2 that is used, as shown below. Note that the lower threshold for the window comparator option is fixed at 400 mV and only applies to the DPOUT pin. This setting cannot be used for the DMOUT port. 000 = VBUS voltage is ready to be applied before port power switch is closed; next stimulus will not wait for this to be removed 001 = DPOUT voltage is greater than the threshold (S2_TH) 010 = Window comparator; DPOUT voltage is lower than the threshold (S2_TH) and DPOUT voltage is greater than the fixed threshold 011 = DMOUT voltage is greater than the threshold (S2_TH) 100 = Do not use 101 = Do not use 110 = DPOUT voltage is greater than the threshold (S2_TH) 111 = Voltage is present after the port power switch is closed; next stimulus will not wait for this to be removed  2014-2015 Microchip Technology Inc. DS20005346B-page 97 UCS1003-1/2/3 REGISTER 10-29: PRELOADED EMULATION STIMULUS 2 CONFIGURATION 2 REGISTER (ADDRESS 36h) R-0 R-0 R-0 R-0 R-0 S2_R2MAG R-0 R-0 R-0 S2_R2 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-4 x = Bit is unknown S2_R2MAG: Stimulus 2 Response Magnitude bits Determines the magnitude of the response to the stimulus. The bit decode changes meaning based on which response was selected. Data written to any field that is identified as “Do not use” will not be accepted. The data will not be updated and the settings will remain set at the previous value. For S2_R2 Settings 0000-0011: The response is a voltage applied on the DPOUT/DMOUT pins. The S2_R2MAG bits specify the voltage relative to ground. 0000 = Pull-down 0110 = 600 mV 1100 = 1800 mV 0001 = 400 mV 0111 = 700 mV 1101 = 2000 mV 0010 = 400 mV 1000 = 800 mV 1110 = 2200 mV 0011 = 400 mV 1001 = 900 mV 1111 = Do not use 0100 = 400 mV 1010 = 1400 mV 0101 = 500 mV 1011 = 1600 mV For S2_R2 settings 0100, 0111, 1101-1111: The response is a resistor connected on DPOUT/DMOUT to GND or VBUS. The S2_R2MAG bits specify the resistor value. 0000 = 1.8 k 0110 = 40 k 1100 = 100 k 0001 = 10 k 0111 = 43 k 1101 = 120 k 0010 = 15 k 1000 = 50 k 1110 = 150 k 0011 = 20 k 1001 = 60 k 1111 = Do not use 0100 = 25 k 1010 = 75 k 0101 = 30 k 1011 = 80 k For S2_R2 Settings 0110, 1001, 1100: The response is a voltage divider applied from VBUS to GND with the ‘center’ at DPOUT/DMOUT. The S2_R2MAG bits specify the minimum resistance of the voltage divider (sum of R1 + R2). Note 1: 2: 0000 = 93 k 0110 = 200 k 1100 = 200 k 0001 = 100 k 0111 = 200 k 1101 = 200 k 0010 = 125 k 1000 = 93 k 1110 = 200 k 0011 = 150 k 1001 = 100 k 1111 = Do not use 0100 = 200 k 1010 = 125 k 0101 = 200 k 1011 = 150 k If STIM2 = 000b and no other response was applied to the DPOUT pin, the 15 k pull-down resistor applied to the DPOUT pin during emulation Reset is not removed. Otherwise, the previous response is left on the DPOUT pin (if applicable) or the 15 k pull-down resistor is removed. If STIM2 = 000b and no other response was applied to the DMOUT pin, the 15 k pull-down resistor applied to the DMOUT pin during emulation Reset is not removed. Otherwise, the previous response is left on the DMOUT pin (if applicable) or the 15 k pull-down resistor is removed. DS20005346B-page 98  2014-2015 Microchip Technology Inc. UCS1003-1/2/3 REGISTER 10-29: PRELOADED EMULATION STIMULUS 2 CONFIGURATION 2 REGISTER (ADDRESS 36h) (CONTINUED) bit 3-0 S2_R2: Stimulus 2 Response Definition bits 0000 = Removes previous response on DPOUT and DMOUT 0001 = Applies voltage on DPOUT(1) 0010 = Applies voltage on DMOUT(2) 0011 = Applies voltage on DPOUT and DMOUT 0100 = Connects resistor from DPOUT to GND(1) 0101 = Do not use 0110 = Connects voltage divider from VBUS to GND with ‘center’ at DPOUT(1) 0111 = Connects resistor from DMOUT to GND(2) 1000 = Do not use 1001 = Connects voltage divider from VBUS to GND with ‘center’ at DMOUT(2) 1010 = Connects  200resistor from DPOUT to DMOUT 1011 = Do not use 1100 = Connects voltage divider from VBUS to GND with ‘center’ at DPOUT and DMOUT 1101 = Connects resistor from DPOUT to GND and DMOUT to GND 1110 = If STIM2 = 000, the 15 kpull-down resistors applied to DPOUT and DMOUT during emulation Reset are not removed. If STIM2 = 111, the 15 kpull-down resistors applied to DPOUT and DMOUT during emulation Reset are removed. For all other STIM2 settings, whatever was applied is not changed. 1111 = Same as ‘1110’ definition above Note 1: 2: If STIM2 = 000b and no other response was applied to the DPOUT pin, the 15 k pull-down resistor applied to the DPOUT pin during emulation Reset is not removed. Otherwise, the previous response is left on the DPOUT pin (if applicable) or the 15 k pull-down resistor is removed. If STIM2 = 000b and no other response was applied to the DMOUT pin, the 15 k pull-down resistor applied to the DMOUT pin during emulation Reset is not removed. Otherwise, the previous response is left on the DMOUT pin (if applicable) or the 15 k pull-down resistor is removed.  2014-2015 Microchip Technology Inc. DS20005346B-page 99 UCS1003-1/2/3 REGISTER 10-30: PRELOADED EMULATION STIMULUS 2 CONFIGURATION 3 REGISTER (ADDRESS 37h)(1) U-0 U-0 — — R-0 R-0 R-0 S2_PUPD R-0 R-0 R-0 S2_TH bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-6 Unimplemented: Read as ‘0’ bit 5-4 S2_PUPD: Stimulus 2 Pull-Down Current Magnitude bits Determines the magnitude of the pull-down current applied on the DPOUT and DMOUT pins when the stimulus response is to apply a voltage and the voltage magnitude is set at pull-down (‘0000b’). The bit decode is as follows: 00 = 10 µA 01 = 50 µA 10 = 100 µA 11 = 150 µA bit 3-0 S2_TH: Stimulus 2 Threshold Value Definition bits Defines the threshold value, as shown below, for the specified stimulus. If the stimulus VBUS voltage is ready to be applied or applied (i.e., STIM2 = 000b or 111b), the threshold value is ignored. 0000 = 400 mV 0001 = 400 mV 0010 = 400 mV 0011 = 300 mV 0100 = 400 mV 0101 = 500 mV 0110 = 600 mV 0111 = 700 mV 1000 = 800 mV 1001 = 900 mV 1010 = 1400 mV 1011 = 1600 mV 1100 = 1800 mV 1101 = 2000 mV 1110 = 2200 mV 1111 = Do not use Note 1: The Legacy charger emulation profiles do not use these settings. Whenever a Legacy charger emulation profile is applied within the DCE Cycle, these controls will not be updated and should be ignored. These settings are only used by the BC1.2 CDP and DCP charger emulation profiles. DS20005346B-page 100  2014-2015 Microchip Technology Inc. UCS1003-1/2/3 REGISTER 10-31: PRELOADED EMULATION STIMULUS 2 CONFIGURATION 4 REGISTER (ADDRESS 38h)(1) U-0 U-0 U-0 U-0 U-0 — — — — — R-0 R-0 R-0 S2_RATIO bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-3 Unimplemented: Read as ‘0’ bit 2-0 S2_RATIO: Stimulus 2 Voltage Divider Ratio bits Determines the voltage divider ratio, as shown below, when the stimulus response is set to connect a voltage divider (i.e., S2_R2 = 0110b, 1001b or 1100b). 000 = 0.25 001 = 0.33 010 = 0.4 011 = 0.5 100 = 0.54 101 = 0.6 110 = 0.66 111 = Do not use Note 1: The BC1.2 DCP and CDP charger emulation profiles do not use this control. Whenever the BC1.2 CDP or DCP charger emulation profile is applied, these controls will not be updated and should be ignored. These settings are only used by the Legacy charger emulation profiles.  2014-2015 Microchip Technology Inc. DS20005346B-page 101 UCS1003-1/2/3 REGISTER 10-32: PRELOADED EMULATION STIMULUS 3 CONFIGURATION 1 REGISTER (ADDRESS 39h) U-0 R-0 — S3_TD_TYPE R-0 R-0 R-0 R-0 S3_TD R-0 R-0 STIM3 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 Unimplemented: Read as ‘0’ bit 6 S3_TD_TYPE: Stimulus 3 Timer Behavior Determination bit 1 = The stimulus timer controls how long the response is applied after the stimulus is detected; the response is applied immediately and held for the duration of the timer, then removed (if the stimulus has been removed) 0 = The stimulus timer is a delay from when the stimulus is detected until the response is performed bit 5-3 S3_TD: Stimulus 3 tSTIM_DEL Determination Value bits 000 = 0 ms 001 = 1 ms 010 = 5 ms 011 = 10 ms 100 = 20 ms 101 = 40 ms 110 = 80 ms 111 = 100 ms bit 2-0 STIM3: Stimulus 3 Determination Usage bits Determines the Stimulus 3 that is used as shown below. Note that the lower threshold for the window comparator option is fixed at 400 mV and only applies to the DPOUT pin. This setting cannot be used for the DMOUT port. 000 = VBUS voltage is ready to be applied before port power switch is closed; next stimulus will not wait for this to be removed 001 = DPOUT voltage is greater than the threshold (S3_TH) 010 = Window comparator; DPOUT voltage is less than the threshold (S3_TH) and DPOUT voltage is greater than the fixed threshold 011 = DMOUT voltage is greater than the threshold (S3_TH) 100 = Do not use 101 = Do not use 110 = DPOUT voltage is greater than the threshold (S3_TH) 111 = Voltage is present after the port power switch is closed; next stimulus will not wait for this to be removed DS20005346B-page 102  2014-2015 Microchip Technology Inc. UCS1003-1/2/3 REGISTER 10-33: PRELOADED EMULATION STIMULUS 3 CONFIGURATION 2 REGISTER (ADDRESS 3Ah) R-0 R-0 R-0 R-0 R-0 S3_R3MAG R-0 R-0 R-0 S3_R3 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-4 x = Bit is unknown S3_R3MAG: Stimulus 3 Response Magnitude bits Determines the magnitude of the response to the stimulus. The bit decode changes meaning based on which response was selected. Data written to any field that is identified as “Do not use” will not be accepted. The data will not be updated and the settings will remain set at the previous value. For S3_R3 Settings 0000-0011: The response is a voltage applied on the DPOUT/DMOUT pins. The S3_R3MAG bits specify the voltage relative to ground. 0000 = Pull Down 0110 = 600 mV 1100 = 1800 mV 0001 = 400 mV 0111 = 700 mV 1101 = 2000 mV 0010 = 400 mV 1000 = 800 mV 1110 = 2200 mV 0011 = 400 mV 1001 = 900 mV 1111 = Do not use 0100 = 400 mV 1010 = 1400 mV 0101 = 500 mV 1011 = 1600 mV For S3_R3 Settings 0100, 0111, 1101-1111: The response is a resistor connected on DPOUT/DMOUT to GND or VBUS. The S3_R3MAG bits specify the resistor value. 0000 = 1.8 k 0110 = 40 k 1100 = 100 k 0001 = 10 k 0111 = 43 k 1101 = 120 k 0010 = 15 k 1000 = 50 k 1110 = 150 k 0011 = 20 k 1001 = 60 k 1111 = Do not use 0100 = 25 k 1010 = 75 k 0101 = 30 k 1011 = 80 k For S3_R3 settings 0110, 1001, 1100: The response is a voltage divider applied from VBUS to GND with the ‘center’ at DPOUT/DMOUT. The S3_R3MAG bits specify the minimum resistance of the voltage divider (sum of R1 + R2). Note 1: 2: 0000 = 93 k 0110 = 200 k 1100 = 200 k 0001 = 100 k 0111 = 200 k 1101 = 200 k 0010 = 125 k 1000 = 93 k 1110 = 200 k 0011 = 150 k 1001 = 100 k 1111 = Do not use 0100 = 200 k 1010 = 125 k 0101 = 200 k 1011 = 150 k If STIM3 = 000b and no other response was applied to the DPOUT pin, the 15 k pull-down resistor applied to the DPOUT pin during emulation Reset is not removed. Otherwise, the previous response is left on the DPOUT pin (if applicable) or the 15 k pull-down resistor is removed. If STIM3 = 000b and no other response was applied to the DMOUT pin, the 15 k pull-down resistor applied to the DMOUT pin during emulation Reset is not removed. Otherwise, the previous response is left on the DMOUT pin (if applicable) or the 15 k pull-down resistor is removed.  2014-2015 Microchip Technology Inc. DS20005346B-page 103 UCS1003-1/2/3 REGISTER 10-33: PRELOADED EMULATION STIMULUS 3 CONFIGURATION 2 REGISTER (ADDRESS 3Ah) (CONTINUED) bit 3-0 S3_R3: Stimulus 3 Response Definition bits 0000 = Removes previous response on DPOUT and DMOUT 0001 = Applies voltage on DPOUT(1) 0010 = Applies voltage on DMOUT(2) 0011 = Applies voltage on DPOUT and DMOUT 0100 = Connects resistor from DPOUT to GND(1) 0101 = Do not use 0110 = Connects voltage divider from VBUS to GND with ‘center’ at DPOUT(1) 0111 = Connects resistor from DMOUT to GND(2) 1000 = Do not use 1001 = Connects voltage divider from VBUS to GND with “center” at DMOUT(2) 1010 = Connects  200resistor from DPOUT to DMOUT 1011 = Do not use 1100 = Connects voltage divider from VBUS to GND with ‘center’ at DPOUT and DMOUT 1101 = Connects resistor from DPOUT to GND and DMOUT to GND 1110 = If STIM3 = 000, the 15 kpull-down resistors applied to DPOUT and DMOUT during emulation reset are not removed. If STIM3 = 111, the 15 kpull-down resistors applied to DPOUT and DMOUT during emulation reset are removed. For all other STIM3 settings, whatever was applied is not changed. 1111 = Same as ‘1110’ definition above Note 1: 2: If STIM3 = 000b and no other response was applied to the DPOUT pin, the 15 k pull-down resistor applied to the DPOUT pin during emulation Reset is not removed. Otherwise, the previous response is left on the DPOUT pin (if applicable) or the 15 k pull-down resistor is removed. If STIM3 = 000b and no other response was applied to the DMOUT pin, the 15 k pull-down resistor applied to the DMOUT pin during emulation Reset is not removed. Otherwise, the previous response is left on the DMOUT pin (if applicable) or the 15 k pull-down resistor is removed. DS20005346B-page 104  2014-2015 Microchip Technology Inc. UCS1003-1/2/3 REGISTER 10-34: PRELOADED EMULATION STIMULUS 3 CONFIGURATION 3 REGISTER (ADDRESS 3Bh)(1) U-0 U-0 — — R-0 R-0 R-0 S3_PUPD R-0 R-0 R-0 S3_TH bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-6 Unimplemented: Read as ‘0’ bit 5-4 S3_PUPD: Stimulus 3 Pull-Down Current Magnitude bits Determines the magnitude of the pull-down current applied on the DPOUT and DMOUT pins when the stimulus response is to apply a voltage and the voltage magnitude is set at pull-down (‘0000b’). The bit decode is as follows: 00 = 10 µA 01 = 50 µA 10 = 100 µA 11 = 150 µA bit 3-0 S3_TH: Stimulus 3 Threshold Value Definition bits Defines the threshold value, as shown below, for the specified stimulus. If the stimulus VBUS voltage is ready to be applied or applied (i.e., STIM3 = 000b or 111b), the threshold value is ignored. 0000 = 400 mV 0001 = 400 mV 0010 = 400 mV 0011 = 300 mV 0100 = 400 mV 0101 = 500 mV 0110 = 600 mV 0111 = 700 mV 1000 = 800 mV 1001 = 900 mV 1010 = 1400 mV 1011 = 1600 mV 1100 = 1800 mV 1101 = 2000 mV 1110 = 2200 mV 1111 = Do not use Note 1: The Legacy charger emulation profiles do not use these settings. Whenever a Legacy charger emulation profile is applied within the DCE Cycle, these controls will not be updated and should be ignored. These settings are only used by the BC1.2 CDP and DCP charger emulation profiles.  2014-2015 Microchip Technology Inc. DS20005346B-page 105 UCS1003-1/2/3 10.13 Custom Emulation Configuration Registers Name Bits Address Cof Default Custom Emulation Configuration 8 40h R/W 01h Custom Emulation Stimulus 1 – Configuration 1 8 41h R/W 00h Custom Emulation Stimulus 1 – Configuration 2 8 42h R/W 00h Custom Emulation Stimulus 1 – Configuration 3 8 43h R/W 00h Custom Emulation Stimulus 1 – Configuration 4 8 44h R/W 00h Custom Emulation Stimulus 2 – Configuration 1 8 45h R/W 00h Custom Emulation Stimulus 2 – Configuration 2 8 46h R/W 00h Custom Emulation Stimulus 2 – Configuration 3 8 47h R/W 00h Custom Emulation Stimulus 2 – Configuration 4 8 48h R/W 00h Custom Emulation Stimulus 3 – Configuration 1 8 49h R/W 00h Custom Emulation Stimulus 3 – Configuration 2 8 4Ah R/W 00h Custom Emulation Stimulus 3 – Configuration 3 8 4Bh R/W 00h Custom Emulation Stimulus 3 – Configuration 3 8 4Ch R/W 00h The Custom Emulation Configuration registers store the values used by the custom charger emulation circuitry. The custom charger emulation profile is set up as three stimuli and the respective responses. DS20005346B-page 106 The contents of registers 40h to 4Ch are retained in Sleep.  2014-2015 Microchip Technology Inc. UCS1003-1/2/3 REGISTER 10-35: CUSTOM EMULATION CONFIGURATION REGISTER (ADDRESS 40h) U-0 U-0 R/W-0 — — CS_TO_DIS R/W-0 R/W-0 CS_EM_TO R/W-0 R-0 R/W-1 CS_FRST RESERVED CSEM_DIS bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-6 Unimplemented: Read as ‘0’ bit 5 CS_TO_DIS: Emulation Time-out Timer Disable bit Disables the emulation time-out timer when the custom charger emulation profile is applied during the DCE Cycle. If the EM_TO_DIS is set, this bit will have no effect.(1) 1 = The emulation time-out timer is disabled when the custom charger emulation profile is applied during the DCE Cycle. When the custom charger emulation profile is being applied, the UCS1003-1 will be constantly monitoring the IBUS current. When the IBUS current is greater than IBUS_CHG, regardless of the reason, then the custom charger emulation profile will be accepted. If the portable device does not draw more than IBUS_CHG current, then the UCS1003-1 will continue waiting until this bit is cleared. 0 = The emulation time-out timer is enabled when the custom charger emulation profile is applied during the DCE Cycle and the EM_TO_DIS bit is not set bit 4-3 CS_EM_TO: tEM_TIMEOUT Value During Custom Charger Emulation Value bits These bits are used when the custom charger emulation profile is used during the DCE Cycle. 00 = 0.8s 01 = 1.6s 10 = 6.4s 11 = 12.8s bit 2 CS_FRST: Custom Charger Emulation Profile Disable bit 1 = The custom charger emulation profile is the first of the profiles applied during the DCE Cycle 0 = The custom charger emulation profile is the last of the profiles applied during the DCE Cycle bit 1 Reserved: Do not change. This bit will read ‘0’ and should not be written to a logic ‘1’. bit 0 CSEM_DIS: Custom Charger Emulation Profile Placement in DCE Cycle bit 1 = The custom charger emulation profile is not enabled 0 = The custom charger emulation profile is enabled Note 1: If the CS_TO_DIS bit is set and the custom charger emulation profile was accepted during the DCE Cycle, a removal is not detected. To avoid this issue, re-enable the emulation time-out after applying any test profiles and charging with the ‘final’ profile.  2014-2015 Microchip Technology Inc. DS20005346B-page 107 UCS1003-1/2/3 REGISTER 10-36: CUSTOM EMULATION STIMULUS 1 CONFIGURATION 1 REGISTER (ADDRESS 41h) U-0 R/W-0 — CS_S1TYPE R/W-0 R/W-0 R/W-0 R/W-0 CS_S1_TD R/W-0 R/W-0 CS_STIM1 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 Unimplemented: Read as ‘0’ bit 6 CS_S1TYPE: Stimulus 1 Timer Behavior Determination bit 1 = The stimulus timer controls how long the response is applied after the stimulus is detected; the response is applied immediately and held for the duration of the timer, then removed (if the stimulus has been removed) 0 = The stimulus timer is a delay from when the stimulus is detected until the response is performed bit 5-3 CS_S1_TD: Stimulus 1 tSTIM_DEL Value Determination bits 000 = 0 ms 001 = 1 ms 010 = 5 ms 011 = 10 ms 100 = 20 ms 101 = 40 ms 110 = 80 ms 111 = 100 ms bit 2-0 CS_STIM1: Stimulus 1 Usage Determination bits Determines the Stimulus 1 that is used as shown below. Note that the lower threshold for the window comparator option is fixed at 400 mV and only applies to the DPOUT pin. This setting cannot be used for the DMOUT port. 000 = VBUS voltage is ready to be applied before port power switch is closed; next stimulus will not wait for this to be removed 001 = DPOUT voltage is greater than the threshold (CS_S1_TH) 010 = Window comparator; DPOUT voltage is lower than the threshold (CS_S1_TH) and DPOUT voltage is greater than the fixed threshold 011 = DMOUT voltage is greater than the threshold (CS_S1_TH) 100 = Do not use 101 = Do not use 110 = DPOUT voltage is greater than the threshold (CS_S1_TH) 111 = VBUS voltage is present after port power switch is closed; next stimulus will not wait for this to be removed DS20005346B-page 108  2014-2015 Microchip Technology Inc. UCS1003-1/2/3 REGISTER 10-37: CUSTOM EMULATION STIMULUS 1 CONFIGURATION 2 REGISTER (ADDRESS 42h) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CS_S1_R1MAG R/W-0 R/W-0 R/W-0 CS_S1_R1 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-4 x = Bit is unknown CS_S1_R1MAG: Stimulus 1 Response Magnitude bits Determines the magnitude of the response to the stimulus. The bit decode changes meaning based on which response was selected. Data written to any field that is identified as ‘Do not use’ will not be accepted. The data will not be updated and the settings will remain set at the previous value. For CS_S1_R1 Settings 0000-0011: The response is a voltage applied on the DPOUT/DMOUT pins. The CS_S1_R1MAG bits specify the voltage relative to ground. 0000 = Pull-down 0110 = 600 mV 1100 = 1800 mV 0001 = 400 mV 0111 = 700 mV 1101 = 2000 mV 0010 = 400 mV 1000 = 800 mV 1110 = 2200 mV 0011 = 400 mV 1001 = 900 mV 1111 = Do not use 0100 = 400 mV 1010 = 1400 mV 0101 = 500 mV 1011 = 1600 mV For CS_S1_R1 Settings 0100, 0111, 1101-1111: The response is a resistor connected on DPOUT/DMOUT to GND or VBUS. The CS_S1_R1MAG bits specify the resistor value. 0000 = 1.8 k 0110 = 40 k 1100 = 100 k 0001 = 10 k 0111 = 43 k 1101 = 120 k 0010 = 15 k 1000 = 50 k 1110 = 150 k 0011 = 20 k 1001 = 60 k 1111 = Do not use 0100 = 25 k 1010 = 75 k 0101 = 30 k 1011 = 80 k For CS_S1_R1 Settings 0110, 1001, 1100: The response is a voltage divider applied from VBUS to GND with the ‘center’ at DPOUT/DMOUT. The CS_S1_R1MAG bits specify the minimum resistance of the voltage divider (sum of R1 + R2). Note 1: 2: 0000 = 93 k 0110 = 200 k 1100 = 200 k 0001 = 100 k 0111 = 200 k 1101 = 200 k 0010 = 125 k 1000 = 93 k 1110 = 200 k 0011 = 150 k 1001 = 100 k 1111 = Do not use 0100 = 200 k 1010 = 125 k 0101 = 200 k 1011 = 150 k If STIM1 = 000b and no other response was applied to the DPOUT pin, the 15 k pull-down resistor applied to the DPOUT pin during emulation Reset is not removed. Otherwise, the previous response is left on the DPOUT pin (if applicable) or the 15 k pull-down resistor is removed. If STIM1 = 000b and no other response was applied to the DMOUT pin, the 15 k pull-down resistor applied to the DMOUT pin during emulation Reset is not removed. Otherwise, the previous response is left on the DMOUT pin (if applicable) or the 15 k pull-down resistor is removed.  2014-2015 Microchip Technology Inc. DS20005346B-page 109 UCS1003-1/2/3 REGISTER 10-37: CUSTOM EMULATION STIMULUS 1 CONFIGURATION 2 REGISTER (ADDRESS 42h) (CONTINUED) bit 3-0 CS_S1_R1: Stimulus 1 Response Definition bits 0000 = Removes previous response on DPOUT and DMOUT 0001 = Applies voltage on DPOUT(1) 0010 = Applies voltage on DMOUT(2) 0011 = Applies voltage on DPOUT and DMOUT 0100 = Connects resistor from DPOUT to GND(1) 0101 = Do not use 0110 = Connects voltage divider from VBUS to GND with ‘center’ at DPOUT(1) 0111 = Connects resistor from DMOUT to GND(2) 1000 = Do not use 1001 = Connects voltage divider from VBUS to GND with ‘center’ at DMOUT(2) 1010 = Connects  200resistor from DPOUT to DMOUT 1011 = Do not use 1100 = Connects voltage divider from VBUS to GND with ‘center’ at DPOUT and DMOUT 1101 = Connects resistor from DPOUT to GND and DMOUT to GND 1110 = If CS_STIM1 = 000, the 15 kpull-down resistors applied to DPOUT and DMOUT during emulation Reset are not removed. If CS_STIM1 = 111, the 15 kpull-down resistors applied to DPOUT and DMOUT during emulation Reset are removed. For all other CS_STIM1 settings, whatever was applied is not changed. 1111 = Same as ‘1110’ definition above Note 1: 2: If STIM1 = 000b and no other response was applied to the DPOUT pin, the 15 k pull-down resistor applied to the DPOUT pin during emulation Reset is not removed. Otherwise, the previous response is left on the DPOUT pin (if applicable) or the 15 k pull-down resistor is removed. If STIM1 = 000b and no other response was applied to the DMOUT pin, the 15 k pull-down resistor applied to the DMOUT pin during emulation Reset is not removed. Otherwise, the previous response is left on the DMOUT pin (if applicable) or the 15 k pull-down resistor is removed. DS20005346B-page 110  2014-2015 Microchip Technology Inc. UCS1003-1/2/3 REGISTER 10-38: CUSTOM EMULATION STIMULUS 1 CONFIGURATION 3 REGISTER (ADDRESS 43h)(1) U-0 U-0 — — R/W-0 R/W-0 R/W-0 CS_S1_PUPD R/W-0 R/W-0 R/W-0 CS_S1_TH bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-6 Unimplemented: Read as ‘0’ bit 5-4 CS_S1_PUPD: Stimulus 1 Pull-Down Current Magnitude bits Determines the magnitude of the pull-down current applied on the DPOUT and DMOUT pins when the stimulus response is to apply a voltage and the voltage magnitude is set at pull-down (‘0000b’). The bit decode is given below. 00 = 10 µA 01 = 50 µA 10 = 100 µA 11 = 150 µA bit 3-0 CS_S1_TH: Stimulus 3 Threshold Value Definition bits Defines the threshold value, as shown below, for the specified stimulus. If the stimulus VBUS voltage is ready to be applied or applied (i.e., CS_STIM1 = 000b or 111b), the threshold value is ignored. 0000 = 400 mV 0001 = 400 mV 0010 = 400 mV 0011 = 300 mV 0100 = 400 mV 0101 = 500 mV 0110 = 600 mV 0111 = 700 mV 1000 = 800 mV 1001 = 900 mV 1010 = 1400 mV 1011 = 1600 mV 1100 = 1800 mV 1101 = 2000 mV 1110 = 2200 mV 1111 = Do not use Note 1: The Legacy charger emulation profiles do not use these settings. Whenever a Legacy charger emulation profile is applied within the DCE Cycle, these controls will not be updated and should be ignored. These settings are only used by the BC1.2 CDP and DCP charger emulation profiles.  2014-2015 Microchip Technology Inc. DS20005346B-page 111 UCS1003-1/2/3 REGISTER 10-39: CUSTOM EMULATION STIMULUS 1 CONFIGURATION 4 REGISTER (ADDRESS 44h)(1) U-0 U-0 U-0 U-0 U-0 — — — — — R/W-0 R/W-0 R/W-0 CS_S1_RATIO bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-3 Unimplemented: Read as ‘0’ bit 2-0 CS_S1_RATIO: Stimulus 1 Voltage Divider Ratio bits Determines the voltage divider ratio, as shown below, when the stimulus response is set to connect a voltage divider (i.e., CS_S1_R1 = 0110b, 1001b or 1100b). 000 = 0.25 001 = 0.33 010 = 0.4 011 = 0.5 100 = 0.54 101 = 0.6 110 = 0.66 111 = Do not use Note 1: The BC1.2 DCP and CDP charger emulation profiles do not use this control. Whenever the BC1.2 CDP or DCP charger emulation profile is applied, these controls will not be updated and should be ignored. These settings are only used by the Legacy charger emulation profiles. DS20005346B-page 112  2014-2015 Microchip Technology Inc. UCS1003-1/2/3 REGISTER 10-40: CUSTOM EMULATION STIMULUS 2 CONFIGURATION 1 REGISTER (ADDRESS 45h) U-0 R/W-0 — CS_S2TYPE R/W-0 R/W-0 R/W-0 R/W-0 CS_S2_TD R/W-0 R/W-0 CS_STIM2 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 Unimplemented: Read as ‘0’ bit 6 CS_S2TYPE: Stimulus 2 Timer Behavior Determination bit 1 = The stimulus timer controls how long the response is applied after the stimulus is detected; the response is applied immediately and held for the duration of the timer, then removed (if the stimulus has been removed) 0 = The stimulus timer is a delay from when the stimulus is detected until the response is performed bit 5-3 CS_S2_TD: Stimulus 2 tSTIM_DEL Value Determination bits 000 = 0 ms 001 = 1 ms 010 = 5 ms 011 = 10 ms 100 = 20 ms 101 = 40 ms 110 = 80 ms 111 = 100 ms bit 2-0 CS_STIM2: Stimulus 2 Usage Determination bits Determines the Stimulus 2 that is used as shown below. Note that the lower threshold for the window comparator option is fixed at 400 mV and only applies to the DPOUT pin. This setting cannot be used for the DMOUT port. 000 = VBUS voltage is ready to be applied before port power switch is closed; next stimulus will not wait for this to be removed (default) 001 = DPOUT voltage is greater than the threshold (CS_S2_TH) 010 = Window comparator; DPOUT voltage is less than the threshold (S1_TH) and DPOUT voltage greater than the fixed threshold 011 = DMOUT voltage is greater than the threshold (CS_S2_TH) 100 = Do not use 101 = Do not use 110 = DPOUT voltage is greater than the threshold (CS_S2_TH) 111 = Voltage is present after the port power switch is closed; next stimulus will not wait for this to be removed.  2014-2015 Microchip Technology Inc. DS20005346B-page 113 UCS1003-1/2/3 REGISTER 10-41: CUSTOM EMULATION STIMULUS 2 CONFIGURATION 2 REGISTER (ADDRESS 46h) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CS_S2_R2MAG R/W-0 R/W-0 R/W-0 CS_S2_R2 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-4 x = Bit is unknown CS_S2_R2MAG: Stimulus 2 Response Magnitude bits Determines the magnitude of the response to the stimulus. The bit decode changes meaning based on which response was selected. Data written to any field that is identified as “Do not use” will not be accepted. The data will not be updated and the settings will remain set at the previous value. For CS_S2_R2 Settings 0000-0011: The response is a voltage applied on the DPOUT/DMOUT pins. The CS_S2_R2MAG bits specify the voltage relative to ground. 0000 = Pull Down 0110 = 600 mV 1100 = 1800 mV 0001 = 400 mV 0111 = 700 mV 1101 = 2000 mV 0010 = 400 mV 1000 = 800 mV 1110 = 2200 mV 0011 = 400 mV 1001 = 900 mV 1111 = Do not use 0100 = 400 mV 1010 = 1400 mV 0101 = 500 mV 1011 = 1600 mV For CS_S2_R2 Settings 0100, 0111, 1101-1111: The response is a resistor connected on DPOUT/DMOUT to GND or VBUS. The CS_S2_R2MAG bits specify the resistor value. 0000 = 1.8 k 0110 = 40 k 1100 = 100 k 0001 = 10 k 0111 = 43 k 1101 = 120 k 0010 = 15 k 1000 = 50 k 1110 = 150 k 0011 = 20 k 1001 = 60 k 1111 = Do not use 0100 = 25 k 1010 = 75 k 0101 = 30 k 1011 = 80 k For CS_S2_R2 Settings 0110, 1001, 1100: The response is a voltage divider applied from VBUS to GND with “center” at DPOUT/DMOUT. The CS_S2_R2MAG bits specify the minimum resistance of the voltage divider (Sum of R1 + R2): Note 1: 2: 0000 = 93 k 0110 = 200 k 1100 = 200 k 0001 = 100 k 0111 = 200 k 1101 = 200 k 0010 = 125 k 1000 = 93 k 1110 = 200 k 0011 = 150 k 1001 = 100 k 1111 = Do not use 0100 = 200 k 1010 = 125 k 0101 = 200 k 1011 = 150 k If STIM1 = 000b and no other response was applied to the DPOUT pin, the 15 k pull-down resistor applied to the DPOUT pin during emulation Reset is not removed. Otherwise, the previous response is left on the DPOUT pin (if applicable) or the 15 k pull-down resistor is removed. If STIM1 = 000b and no other response was applied to the DMOUT pin, the 15 k pull-down resistor applied to the DMOUT pin during emulation Reset is not removed. Otherwise, the previous response is left on the DMOUT pin (if applicable) or the 15 k pull-down resistor is removed. DS20005346B-page 114  2014-2015 Microchip Technology Inc. UCS1003-1/2/3 REGISTER 10-41: CUSTOM EMULATION STIMULUS 2 CONFIGURATION 2 REGISTER (ADDRESS 46h) (CONTINUED) bit 3-0 CS_S2_R2: Stimulus 2 Response Definition bits 0000 = Removes previous response on DPOUT and DMOUT 0001 = Applies voltage on DPOUT(1) 0010 = Applies voltage on DMOUT(2) 0011 = Applies voltage on DPOUT and DMOUT. 0100 = Connects resistor from DPOUT to GND(1) 0101 = Do not use 0110 = Connects voltage divider from VBUS to GND with ‘center’ at DPOUT(1) 0111 = Connects resistor from DMOUT to GND(2) 1000 = Do not use 1001 = Connects voltage divider from VBUS to GND with ‘center’ at DMOUT(2) 1010 = Connects  200resistor from DPOUT to DMOUT 1011 = Do not use 1100 = Connects voltage divider from VBUS to GND with ‘center’ at DPOUT and DMOUT 1101 = Connects resistor from DPOUT to GND and DMOUT to GND 1110 = If CS_STIM2 = 000, the 15 kpull-down resistors applied to DPOUT and DMOUT during emulation Reset are not removed. If CS_STIM2 = 111, the 15 kpull-down resistors applied to DPOUT and DMOUT during emulation Reset are removed. For all other CS_STIM2 settings, whatever was applied is not changed. 1111 = Same as ‘1110’ definition above Note 1: 2: If STIM1 = 000b and no other response was applied to the DPOUT pin, the 15 k pull-down resistor applied to the DPOUT pin during emulation Reset is not removed. Otherwise, the previous response is left on the DPOUT pin (if applicable) or the 15 k pull-down resistor is removed. If STIM1 = 000b and no other response was applied to the DMOUT pin, the 15 k pull-down resistor applied to the DMOUT pin during emulation Reset is not removed. Otherwise, the previous response is left on the DMOUT pin (if applicable) or the 15 k pull-down resistor is removed.  2014-2015 Microchip Technology Inc. DS20005346B-page 115 UCS1003-1/2/3 REGISTER 10-42: CUSTOM EMULATION STIMULUS 2 CONFIGURATION 3 REGISTER (ADDRESS 47h)(1) U-0 U-0 — — R/W-0 R/W-0 R/W-0 CS_S2_PUPD R/W-0 R/W-0 R/W-0 CS_S2_TH bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-6 Unimplemented: Read as ‘0’ bit 5-4 CS_S2_PUPD: Stimulus 2 Pull-Down Current Magnitude bits Determines the magnitude of the pull-down current applied on the DPOUT and DMOUT pins when the stimulus response is to apply a voltage and the voltage magnitude is set at pull-down (‘0000b’). The bit decode is as follows: 00 = 10 µA 01 = 50 µA 10 = 100 µA 11 = 150 µA bit 3-0 CS_S2_TH: Stimulus 2 Threshold Value Definition bits Defines the threshold value, as shown below, for the specified stimulus. If the stimulus VBUS voltage is ready to be applied or applied (i.e., CS_STIM2 = 000b or 111b), the threshold value is ignored. 0000 = 400 mV 0001 = 400 mV 0010 = 400 mV 0011 = 300 mV 0100 = 400 mV 0101 = 500 mV 0110 = 600 mV 0111 = 700 mV 1000 = 800 mV 1001 = 900 mV 1010 = 1400 mV 1011 = 1600 mV 1100 = 1800 mV 1101 = 2000 mV 1110 = 2200 mV 1111 = Do not use Note 1: The Legacy charger emulation profiles do not use these settings. Whenever a Legacy charger emulation profile is applied within the DCE Cycle, these controls will not be updated and should be ignored. These settings are only used by the BC1.2 CDP and DCP charger emulation profiles. DS20005346B-page 116  2014-2015 Microchip Technology Inc. UCS1003-1/2/3 REGISTER 10-43: CUSTOM EMULATION STIMULUS 2 CONFIGURATION 4 REGISTER (ADDRESS 48h)(1) U-0 U-0 U-0 U-0 U-0 — — — — — R/W-0 R/W-0 R/W-0 CS_S2_RATIO bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-3 Unimplemented: Read as ‘0’ bit 2-0 CS_S2_RATIO: Stimulus 2 Voltage Divider Ratio bits Determines the voltage divider ratio, as shown below, when the stimulus response is set to connect a voltage divider (i.e., CS_S2_R2 = 0110b, 1001b or 1100b). 000 = 0.25 001 = 0.33 010 = 0.4 011 = 0.5 100 = 0.54 101 = 0.6 110 = 0.66 111 = Do not use Note 1: The BC1.2 DCP and CDP charger emulation profiles do not use this control. Whenever the BC1.2 CDP or DCP charger emulation profile is applied, these controls will not be updated and should be ignored. These settings are only used by the Legacy charger emulation profiles.  2014-2015 Microchip Technology Inc. DS20005346B-page 117 UCS1003-1/2/3 REGISTER 10-44: CUSTOM EMULATION STIMULUS 3 CONFIGURATION 1 REGISTER (ADDRESS 49h) U-0 R/W-0 — CS_S3TYPE R/W-0 R/W-0 R/W-0 R/W-0 CS_S3_TD R/W-0 R/W-0 CS_STIM3 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 Unimplemented: Read as ‘0’ bit 6 CS_S3TYPE: Stimulus 3 Timer Behavior Determination bit 1 = The stimulus timer controls how long the response is applied after the stimulus is detected; the response is applied immediately and held for the duration of the timer, then removed (if the stimulus has been removed) 0 = The stimulus timer is a delay from when the stimulus is detected until the response is performed bit 5-3 CS_S3_TD: Stimulus 3 tSTIM_DEL Value Determination bits 000 = 0 ms 001 = 1 ms 010 = 5 ms 011 = 10 ms 100 = 20 ms 101 = 40 ms 110 = 80 ms 111 = 100 ms bit 2-0 CS_STIM3: Stimulus 3 Usage Determination bits Determines the Stimulus 3 that is used as shown below. Note that the lower threshold for the window comparator option is fixed at 400 mV and only applies to the DPOUT pin. This setting cannot be used for the DMOUT port. 000 = VBUS voltage is ready to be applied before port power switch is closed; next stimulus will not wait for this to be removed (default) 001 = DPOUT voltage is greater than the threshold (CS_S3_TH) 010 = Window comparator; DPOUT voltage is lower than the threshold (CS_S3_TH) and DPOUT voltage greater than the fixed threshold 011 = DMOUT voltage is greater than the threshold (CS_S3_TH) 100 = Do not use 101 = Do not use 110 = DPOUT voltage is greater than the threshold (CS_S3_TH) 111 = Voltage is present after the port power switch is closed; next stimulus will not wait for this to be removed. DS20005346B-page 118  2014-2015 Microchip Technology Inc. UCS1003-1/2/3 REGISTER 10-45: CUSTOM EMULATION STIMULUS 3 CONFIGURATION 2 REGISTER (ADDRESS 4Ah) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CS_S3_R3MAG R/W-0 R/W-0 R/W-0 CS_S3_R3 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-4 x = Bit is unknown CS_S3_R3MAG: Stimulus 3 Response Magnitude bits Determines the magnitude of the response to the stimulus. The bit decode changes meaning based on which response was selected. Data written to any field that is identified as “Do not use” will not be accepted. The data will not be updated and the settings will remain set at the previous value. For CS_S3_R3 Settings 0000-0011: The response is a voltage applied on the DPOUT/DMOUT pins. The CS_S3_R3MAG bits specify the voltage relative to ground. 0000 = Pull-down 0110 = 600 mV 1100 = 1800 mV 0001 = 400 mV 0111 = 700 mV 1101 = 2000 mV 0010 = 400 mV 1000 = 800 mV 1110 = 2200 mV 0011 = 400 mV 1001 = 900 mV 1111 = Do not use 0100 = 400 mV 1010 = 1400 mV 0101 = 500 mV 1011 = 1600 mV For CS_S3_R3 Settings 0100, 0111, 1101-1111: The response is a resistor connected on DPOUT/DMOUT to GND or VBUS. The CS_S3_R3MAG bits specify the resistor value. 0000 = 1.8 k 0110 = 40 k 1100 = 100 k 0001 = 10 k 0111 = 43 k 1101 = 120 k 0010 = 15 k 1000 = 50 k 1110 = 150 k 0011 = 20 k 1001 = 60 k 1111 = Do not use 0100 = 25 k 1010 = 75 k 0101 = 30 k 1011 = 80 k For CS_S3_R3 Settings 0110, 1001, 1100: The response is a voltage divider applied from VBUS to GND with the ‘center’ at DPOUT/DMOUT. The CS_S3_R3MAG bits specify the minimum resistance of the voltage divider (sum of R1 + R2). Note 1: 2: 0000 = 93 k 0110 = 200 k 1100 = 200 k 0001 = 100 k 0111 = 200 k 1101 = 200 k 0010 = 125 k 1000 = 93 k 1110 = 200 k 0011 = 150 k 1001 = 100 k 1111 = Do not use 0100 = 200 k 1010 = 125 k 0101 = 200 k 1011 = 150 k If STIM1 = 000b and no other response was applied to the DPOUT pin, the 15 k pull-down resistor applied to the DPOUT pin during emulation Reset is not removed. Otherwise, the previous response is left on the DPOUT pin (if applicable) or the 15 k pull-down resistor is removed. If STIM1 = 000b and no other response was applied to the DMOUT pin, the 15 k pull-down resistor applied to the DMOUT pin during emulation Reset is not removed. Otherwise, the previous response is left on the DMOUT pin (if applicable) or the 15 k pull-down resistor is removed.  2014-2015 Microchip Technology Inc. DS20005346B-page 119 UCS1003-1/2/3 REGISTER 10-45: CUSTOM EMULATION STIMULUS 3 CONFIGURATION 2 REGISTER (ADDRESS 4Ah) (CONTINUED) bit 3-0 CS_S3_R3: Stimulus 3 Response Definition bits 0000 = Removes previous response on DPOUT and DMOUT 0001 = Applies voltage on DPOUT(1) 0010 = Applies voltage on DMOUT(2) 0011 = Applies voltage on DPOUT and DMOUT 0100 = Connects resistor from DPOUT to GND(1) 0101 = Do not use 0110 = Connects voltage divider from VBUS to GND with ‘center’ at DPOUT(1) 0111 = Connects resistor from DMOUT to GND(2) 1000 = Do not use 1001 = Connects voltage divider from VBUS to GND with ‘center’ at DMOUT(2) 1010 = Connects  200resistor from DPOUT to DMOUT 1011 = Do not use 1100 = Connects voltage divider from VBUS to GND with ‘center’ at DPOUT and DMOUT 1101 = Connects resistor from DPOUT to GND and DMOUT to GND 1110 = If CS_STIM3 = 000, the 15 kpull-down resistors applied to DPOUT and DMOUT during emulation Reset are not removed. If CS_STIM3 = 111, the 15 kpull-down resistors applied to DPOUT and DMOUT during emulation Reset are removed. For all other CS_STIM3 settings, whatever was applied is not changed. 1111 = Same as ‘1110’ definition above Note 1: 2: If STIM1 = 000b and no other response was applied to the DPOUT pin, the 15 k pull-down resistor applied to the DPOUT pin during emulation Reset is not removed. Otherwise, the previous response is left on the DPOUT pin (if applicable) or the 15 k pull-down resistor is removed. If STIM1 = 000b and no other response was applied to the DMOUT pin, the 15 k pull-down resistor applied to the DMOUT pin during emulation Reset is not removed. Otherwise, the previous response is left on the DMOUT pin (if applicable) or the 15 k pull-down resistor is removed. DS20005346B-page 120  2014-2015 Microchip Technology Inc. UCS1003-1/2/3 REGISTER 10-46: CUSTOM EMULATION STIMULUS 3 CONFIGURATION 3 REGISTER (ADDRESS 4Bh)(1) U-0 U-0 — — R/W-0 R/W-0 R/W-0 CS_S3_PUPD R/W-0 R/W-0 R/W-0 CS_S3_TH bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-6 Unimplemented: Read as ‘0’ bit 5-4 CS_S3_PUPD: Stimulus 3 Pull-Down Current Magnitude bits Determines the magnitude of the pull-down current applied on the DPOUT and DMOUT pins when the stimulus response is to apply a voltage and the voltage magnitude is set at pull-down (‘0000b’). The bit decode is as follows: 00 = 10 µA 01 = 50 µA 10 = 100 µA 11 = 150 µA bit 3-0 CS_S3_TH: Stimulus 3 Threshold Value Definition bits Defines the threshold value, as shown below, for the specified stimulus. If the stimulus VBUS voltage is ready to be applied or applied (i.e., CS_STIM3 = 000b or 111b), the threshold value is ignored. 0000 = 400 mV 0001 = 400 mV 0010 = 400 mV 0011 = 300 mV 0100 = 400 mV 0101 = 500 mV 0110 = 600 mV 0111 = 700 mV 1000 = 800 mV 1001 = 900 mV 1010 = 1400 mV 1011 = 1600 mV 1100 = 1800 mV 1101 = 2000 mV 1110 = 2200 mV 1111 = Do not use Note 1: The Legacy charger emulation profiles do not use these settings. Whenever a Legacy charger emulation profile is applied within the DCE Cycle, these controls will not be updated and should be ignored. These settings are only used by the BC1.2 CDP and DCP charger emulation profiles.  2014-2015 Microchip Technology Inc. DS20005346B-page 121 UCS1003-1/2/3 REGISTER 10-47: CUSTOM EMULATION STIMULUS 3 CONFIGURATION 4 REGISTER (ADDRESS 4Ch)(1) U-0 U-0 U-0 U-0 U-0 — — — — — R/W-0 R/W-0 R/W-0 CS_S3_RATIO bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-3 Unimplemented: Read as ‘0’ bit 2-0 CS_S3_RATIO: Stimulus 3 Voltage Divider Ratio bits Determines the voltage divider ratio, as shown below, when the stimulus response is set to connect a voltage divider (i.e., CS_S3_R3 = 0110b, 1001b or 1100b). 000 = 0.25 001 = 0.33 010 = 0.4 011 = 0.5 100 = 0.54 101 = 0.6 110 = 0.66 111 = Do not use Note 1: The BC1.2 DCP and CDP charger emulation profiles do not use this control. Whenever the BC1.2 CDP or DCP charger emulation profile is applied, these controls will not be updated and should be ignored. These settings are only used by the Legacy charger emulation profiles. DS20005346B-page 122  2014-2015 Microchip Technology Inc. UCS1003-1/2/3 10.14.1 10.14 Current-Limiting Behavior Configuration Registers Name Bits Address Cof Default Applied Current-Limiting Behavior 8 50h R 82h Custom Current-Limiting Behavior Configuration 8 51h R/W 82h APPLIED CURRENT-LIMITING BEHAVIOR REGISTER The Applied Current-Limiting Behavior register stores the values used by the applied Current-Limiting mode (Trip or CC) when the custom settings are not used. The contents of this register are updated automatically when charger emulation is completed. REGISTER 10-48: APPLIED CURRENT-LIMITING BEHAVIOR REGISTER (ADDRESS 50h)(1) R-1 R-0 U-0 (1) SEL_VBUS_MIN — R-0 R-0 SEL_R2_IMIN R-0 (1) R-1 R-0 RESERVED bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 SEL_VBUS_MIN: VBUS_MIN Voltage Definition bits 00 = 1.5V 01 = 1.75V 10 = 2.0V 11 = 2.25V bit 5 Unimplemented: Read as ‘0’ bit 4-2 SEL_R2_IMIN: IBUS_R2MIN Current Definition bits 000 = 120 mA 001 = 570 mA 010 = 1000 mA 011 = 1350 mA 100 = 1680 mA 101 = 2050 mA bit 1-0 Reserved: Do not change Note 1: x = Bit is unknown The values specified in this register are typical.  2014-2015 Microchip Technology Inc. DS20005346B-page 123 UCS1003-1/2/3 10.14.2 CUSTOM CURRENT-LIMITING BEHAVIOR CONFIGURATION REGISTER (except Legacy 2), the custom charger emulation profile or does not handshake as a dedicated charger (i.e., a power thief). The contents of this register are retained in Sleep. The Custom Current Limiting Behavior Configuration Register allows programming of current limit parameters. These controls are used when a portable device handshakes using the Legacy charger emulation profiles REGISTER 10-49: CUSTOM CURRENT-LIMITING BEHAVIOR CONFIGURATION REGISTER (ADDRESS 51h)(1) R/W-1 R/W-0 U-0 R/W-0 — CS_VBUS_MIN bit 7 R/W-0 R/W-0 R/W-0 RESERVED bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 R/W-1 CS_R2_IMIN x = Bit is unknown CS_VBUS_MIN: Custom VBUS_MIN Voltage Definition bits Note that VBUS_MIN is checked even when operating with Trip Current Limiting. 00 = 1.5V 01 = 1.75V 10 = 2.0V 11 = 2.25V Unimplemented: Read as ‘0’ bit 5 bit 4-2 CS_R2_IMIN: Custom IBUS_R2MIN Threshold Definition bits The default is 120 mA. This value is used under the following conditions: when a portable device handshakes using the Legacy charger emulation profiles (except Legacy 2), the custom charger emulation profile or when it does not handshake in DCE Cycle (i.e., a power thief). Under these conditions, the Current-Limiting mode is determined by the relative value of IBUS_R2MIN and ILIM. When IBUS_R2MIN < ILIM or ILIM > 1.68A, Trip Current-Limiting mode is used; otherwise, CC mode is used. Define the IBUS_R2MIN current as follows: 000 = 120 mA 001 = 570 mA 010 = 1000 mA 011 = 1350 mA 100 = 1680 mA 101 = 2050 mA bit 1-0 Reserved: Do not change Note 1: The values specified in this register are typical. 10.15 Product ID Register Name Bits Address Product ID 8 FDh 10.17 Revision Register Cof Default R 4Eh The Product ID register stores a unique 8-bit value that identifies the UCSXXXX Device Family. Name Revision Bits Address Cof 8 FFh R Default 82h The Revision register stores an 8-bit value that represents the part revision. 10.16 Manufacturer ID Register Name Bits Address Manufacturer ID 8 FEh Cof Default R 5Dh The Manufacturer ID register stores a unique 8-bit value that identifies Microchip Technology Inc. DS20005346B-page 124  2014-2015 Microchip Technology Inc. UCS1003-1/2/3 11.0 UCS1003-1 COMMUNICATIONS 11.1 Operating Mode Note: The UCS1003-1 can operate in SMBus mode (see Section 11.2 “SMBus Operating Mode”) or Stand-Alone mode (see Section 11.3 “Stand-Alone Operating Mode”). The resistor on the COMM_SEL/ILIM pin determines the operating mode and the hardware ILIM setting, as shown in Table 11-1. Unless connected to GND or VDD, the resistors in Table 11-1 are pull-down resistors. TABLE 11-1: If it is necessary to connect the COMM_SEL/ILIM pin to VDD via a pull-up resistor, it is recommended that this resistor value not exceed 100 k. UCS1003-1 COMMUNICATION MODE AND ILIM SELECTION Selection Resistor ±5% ILIM Setting(1) Communications Mode GND 570 mA SMBus – see Section 11.2.1.2 10 k pull-down 1000 mA SMBus – see Section 11.2.1.2 12 k pull-down 1130 mA SMBus – see Section 11.2.1.2 15 k pull-down 1350 mA SMBus – see Section 11.2.1.2 18 k pull-down 1680 mA SMBus – see Section 11.2.1.2 22 k pull-down 2050 mA SMBus – see Section 11.2.1.2 27 kpull-down 2280 mA SMBus – see Section 11.2.1.2 33 k pull-down 2850 mA (3000 mA maximum) SMBus – see Section 11.2.1.2 47 k pull-down 570 mA Stand-Alone mode 56 k pull-down 1000 mA Stand-Alone mode 68 k pull-down 1130 mA Stand-Alone mode 82 k pull-down 1350 mA Stand-Alone mode 100 k pull-down 1680 mA Stand-Alone mode 120 k pull-down 2050 mA Stand-Alone mode 150 k pull-down 2280 mA Stand-Alone mode VDD (If a pull-up resistor is used, its value must not exceed 100 k.) 2850 mA (3000 mA maximum) Stand-Alone mode Note 1: Unless otherwise indicated, the values specified in this column are the typical ILIM in the Table 1-2.  2014-2015 Microchip Technology Inc. DS20005346B-page 125 UCS1003-1/2/3 11.2 11.2.1 SMBus Operating Mode When the COMM_SEL/ILIM pin is connected directly to ground, or though a pull-down resistor with a value of 33 k or below as listed in Table 11-1, the UCS1003-1 communicates via the SMBus or I2C communication protocols. Note 1: Upon power-up, the UCS1003-1 will not respond to any SMBus communications for 5.5 ms. After this time, full functionality is available. SYSTEM MANAGEMENT BUS In SMBus mode, the UCS1003-1 communicates with a host controller. The SMBus is a two-wire serial communication protocol between a computer host and its peripheral devices. A detailed timing diagram is shown in Figure 11-1. Stretching of the SMCLK signal is supported; however, the UCS1003-1 will not stretch the clock signal. 2: When in the Sleep state, the first SMBus read command sent to the UCS1003-1 device address will wake it. Any data sent to the UCS1003-1 will be ignored and any data read from the UCS1003-1 should be considered invalid. The UCS1003-1 will be fully functional 3 ms after this first read command is sent. See Section 5.1.2 “Sleep State Operation”. THIGH TLOW THD:STA T SU:STO T FALL SMCLK T RISE THD:STA THD:DAT TSU:DAT T SU:STA SMDATA TBUF P S FIGURE 11-1: 11.2.1.1 P - Stop Condition P SMBus Timing Diagram. SMBus Start Bit The SMBus Start bit is defined as a transition of the SMBus data line from a logic ‘1’ state to a logic ‘0’ state while the SMBus clock line is in a logic ‘1’ state. 11.2.1.2 S S - Start Condition SMBus Address and RD/WR Bit The SMBus address is determined based on the resistor connected on the SEL pin, as shown in Table 11-2. Note: If it is necessary to connect the SEL pin to VDD via a resistor, the pull-up resistor may be any value up to 100 k. The SMBus address byte consists of the 7-bit client address followed by the RD/WR indicator bit. If this RD/WR bit is a logic ‘0’, the SMBus host is writing data to the client device. If this RD/WR bit is a logic ‘1’, the SMBus host is reading data from the client device. DS20005346B-page 126  2014-2015 Microchip Technology Inc. UCS1003-1/2/3 TABLE 11-2: 11.2.1.3 SEL PIN DECODE Resistor (±5%) PWR_EN Polarity GND 10 k pull-down 12 k pull-down 15 k pull-down 18 k pull-down 22 k pull-down 27 k pull-down 33 k pull-down 47 k pull-down 56 k pull-down 68 k pull-down 82 k pull-down 100 k pull-down 120 k pull-down 150 k pull-down VDD (If a pull-up resistor is used, its value must not exceed 100 k) Active-Low Active-Low Active-Low Active-Low Active-Low Active-Low Active-Low Active-Low Active-High Active-High Active-High Active-High Active-High Active-High Active-High Active-High SMBus Data Bytes All SMBus data bytes are sent Most Significant bit (MSb) first and composed of eight bits of information. 11.2.1.4 SMBus ACK and NACK Bits The SMBus client will Acknowledge all data bytes that it receives. This is done by the client device pulling the SMBus data line low after the eighth bit of each byte that is transmitted. This applies to both the write byte and block write protocols. By holding the SMBus data line high after the eighth data bit has been sent, the host will NACK (not Acknowledge) the last data byte to be received from the client. For the block read protocol, the host will ACK each data byte that it receives, except the last data byte. 11.2.1.5 SMBus Stop Bit The SMBus Stop bit is defined as a transition of the SMBus data line from a logic ‘0’ state to a logic ‘1’ state while the SMBus clock line is in a logic ‘1’ state. When the UCS1003-1 detects an SMBus Stop bit, and it has been communicating with the SMBus protocol, it will reset its client interface and prepare to receive further communications. 11.2.1.6 SMBus Time-out and Idle Reset The UCS1003-1 includes an SMBus time-out feature. If the clock is held at logic ‘0’ for tTIMEOUT, the device can time-out and reset the SMBus interface. The SMBus interface can also reset if both the clock and data lines are held at a logic ‘1’ for tIDLE_RESET. Communication is restored with a Start condition. This  2014-2015 Microchip Technology Inc. SMBus Address 1010_111 1010_110 1010_101 1010_100 0110_000 0110_001 0110_010 0110_011 0110_011 0110_010 0110_001 0110_000 1010_100 1010_101 1010_110 1010_111 (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) functionality defaults to disabled and can be enabled by clearing the DIS_TO bit in the Emulation Configuration register (Register 10-9). 11.2.2 SMBUS AND I2C COMPATIBILITY The major differences between SMBus and I2C devices are highlighted in this section. For more information, refer to the SMBus 2.0 and I2C specifications. • UCS1003-1 supports I2C Fast mode at 400 kHz. This covers the SMBus maximum time of 100 kHz. • Minimum frequency for SMBus communications is 10 kHz. • The SMBus client protocol will reset if the clock is held at a logic ‘0’ for longer than 30 ms. This timeout functionality is disabled by default in the UCS1003-1 and can be enabled by clearing the DIS_TO bit. I2C does not have a time-out. • Except when operating in Sleep mode, the SMBus client protocol will reset if both the clock and data lines are held at a logic ‘1’ for longer than 200 µs (Idle condition). This function is disabled by default in the UCS1003-1 device and can be enabled by clearing the DIS_TO bit. I2C does not have an Idle condition. • I2C devices do not support the Alert Response Address functionality (which is optional for SMBus). • I2C devices support block read and write differently. I2C protocol allows for an unlimited number of bytes to be sent in either direction. The SMBus protocol requires that an additional data byte, indicating the number of bytes to read/write, is transmitted. The UCS1003-1 supports I2C formatting only. DS20005346B-page 127 UCS1003-1/2/3 11.2.3 SMBUS PROTOCOLS The UCS1003-1 is SMBus 2.0 protocol-compatible and supports write byte, read byte, send byte and receive byte as valid protocols, as shown in the following sections. All protocols in these sections use the convention in Table 11-3. TABLE 11-3: PROTOCOL FORMAT Data Sent to Device Data Sent to the Host Data Sent Data Sent 11.2.3.1 SMBus Write Byte The write byte is used to write one byte of data to a specific register, as shown in Table 11-4. TABLE 11-4: WRITE BYTE PROTOCOL Start Client Address WR ACK Register Address ACK Register Data ACK Stop 10 YYYY_YYY 0 0 XXh 0 XXh 0 01 11.2.3.2 SMBus Read Byte The read byte protocol is used to read one byte of data from the registers, as shown in Table 11-5. TABLE 11-5: READ BYTE PROTOCOL Start Client Address WR ACK Register Address ACK Start Client Address RD ACK 10 YYYY_YYY 0 0 XXh 0 1 0 YYYY_YYY 1 0 11.2.3.3 Register NACK Data XXh 1 Stop 01 SMBus Send Byte The send byte protocol is used to set the internal address register pointer to the correct address location. No data is transferred during the send byte protocol, as shown in Table 11-6. TABLE 11-6: SEND BYTE PROTOCOL Start Client Address WR ACK Register Address ACK Stop 10 YYYY_YYY 0 0 XXh 0 01 11.2.3.4 SMBus Receive Byte The receive byte protocol is used to read data from a register when the Internal Register Address Pointer is known to be at the right location (e.g., set via send byte). This is used for consecutive reads of the same register, as shown in Table 11-7. TABLE 11-7: RECEIVE BYTE PROTOCOL Start Client Address RD ACK Register Data NACK Stop 10 YYYY_YYY 1 0 XXh 1 01 DS20005346B-page 128  2014-2015 Microchip Technology Inc. UCS1003-1/2/3 I2C PROTOCOLS 11.2.4 Note: The UCS1003-1 supports I2C block read and block write. The protocols listed below use the convention shown in Table 11-3. 11.2.4.1 When using the block write protocol, the Internal Address Pointer will be automatically incremented after every data byte is received; it will wrap from FFh to 00h. Block Write The block write is used to write multiple data bytes to a group of contiguous registers, as shown in Table 11-8. TABLE 11-8: BLOCK WRITE PROTOCOL Start Client Address WR ACK Register Address ACK Register Data ACK 10 YYYY_YYY 0 0 XXh 0 XXh 0 Register Data ACK Register Data ACK ... Register Data ACK Stop XXh 0 XXh 0 ... XXh 0 01 11.2.4.2 Block Read Note: The block read is used to read multiple data bytes from a group of contiguous registers, as shown in Table 11-9. TABLE 11-9: When using the block read protocol, the Internal Address Pointer will be automatically incremented after every data byte is received; it will wrap from FFh to 00h. BLOCK READ PROTOCOL Start Client Address WR ACK Register Address ACK Start Client Address RD ACK Register Data 10 YYYY_YYY 0 0 XXh 0 10 YYYY_YYY 1 0 XXh ACK Register Data ACK Register Data ACK Register Data ACK ... 0 XXh 0 XXh 0 XXh 0 ...  2014-2015 Microchip Technology Inc. Register NACK Data XXh 1 Stop 01 DS20005346B-page 129 UCS1003-1/2/3 11.3 Stand-Alone Operating Mode Stand-Alone mode allows the UCS1003-1 to operate without active SMBus/I2C communications. Stand-Alone mode can be enabled by connecting a pull-down resistor, greater or equal to 47 k on the COMM_SEL/ILIM pin, as shown in Table 11-1. When the device is configured to operate in StandAlone mode, the Fault handling and Attach Detection controls are determined via the LATCH and S0 pins, as shown in Table 11-10. Note: If it is necessary to connect the S0 or LATCH pins to VDD via a pull-up resistor, the pull-up resistor value should be 100 k in order to ensure the VIH specification. Similarly, if it is necessary to connect the S0 or LATCH pins to GND via a pull-down resistor, the pull-down resistor value should be 100 k in order to ensure the VIL specification. TABLE 11-10: STAND-ALONE FAULT AND ATTACH DETECTION SELECTION LATCH Pin S0 Pin Command Low Low No Attach Detection. Auto-recovery upon Error Detection. Low High Attach Detection in the Detect power state. Auto-recovery upon Error Detection. High Low No Attach Detection. Error states are latched and require host to change the PWR_EN control to recover from the Error state. High High Attach Detection in the Detect power state. Error states are latched and require host to change the PWR_EN control to recover from the Error state. Note: In the Stand-Alone operating mode, communications from and to the UCS1003-1 are limited to the PWR_EN, EM_EN, M2, M1, ALERT# and A_DET# pins. DS20005346B-page 130  2014-2015 Microchip Technology Inc. UCS1003-1/2/3 12.0 PACKAGING INFORMATION 12.1 Package Marking Information 20-Lead QFN (4x4 mm) U1003-X YWWNNNA R Example U1003-2 424KS9A CTW Legend: X Device version Y Year code (last digit of calendar year) WW Week code (week of January 1 is week “01”) NNN Alphanumeric traceability code R Revision Country of origin Pb-free JEDEC designator for Matte Tin (Sn) e3 * This package is Pb-free. The Pb-free JEDEC designator ( e3 ) can be found on the outer packaging for this package. Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information.  2014-2015 Microchip Technology Inc. DS20005346B-page 131 UCS1003-1/2/3 DS20005346B-page 132  2014-2015 Microchip Technology Inc. Note: For the most current package drawings, see the Microchip Packaging Specification at http://www.microchip.com/packaging UCS1003-1/2/3 APPENDIX A: REVISION HISTORY Revision B (December 2015) The following is the list of modifications: 1. Updated Features to indicate EN/IEC 60950-1 (CB) certification. Revision A (September 2014) • Original Release of this Document.  2014-2015 Microchip Technology Inc. DS20005346B-page 133 UCS1003-1/2/3 NOTES: DS20005346B-page 134  2014-2015 Microchip Technology Inc. UCS1003-1/2/3 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. Device Device: [X](1) -XX Package Tape and Reel UCS1003-1: UCS1003-2: UCS1003-3: Package: Examples: BP USB Port Power Controller with Charger Emulation USB Port Power Controller with Charger Emulation USB Port Power Controller with Charger Emulation = 20-pin, QFN Lead-Free ROHS Compliant Package a) UCS1003-1-BP: 20-pin 4x4 QFN Lead-Free ROHS Compliant Package. b) UCS1003-1-BP-TR: 20-pin 4x4 QFN Lead-Free ROHS Compliant Package, Tape and Reel. Note 1: Tape and Reel identifier only appears in the catalog part number description. This identifier is used for ordering purposes and is not printed on the device package. Check with your Microchip sales office for package availability for the Tape and Reel option. Tape and Reel Option: Blank = Standard packaging (tube or tray) TR = Tape and Reel(1)  2014-2015 Microchip Technology Inc. DS20005346B-page 135 UCS1003-1/2/3 NOTES: DS20005346B-page 136  2014-2015 Microchip Technology Inc. Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. • Microchip is willing to work with the customer who is concerned about the integrity of their code. • Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer’s risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights unless otherwise stated. Trademarks The Microchip name and logo, the Microchip logo, dsPIC, FlashFlex, flexPWR, JukeBlox, KEELOQ, KEELOQ logo, Kleer, LANCheck, MediaLB, MOST, MOST logo, MPLAB, OptoLyzer, PIC, PICSTART, PIC32 logo, RightTouch, SpyNIC, SST, SST Logo, SuperFlash and UNI/O are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. The Embedded Control Solutions Company and mTouch are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, BodyCom, chipKIT, chipKIT logo, CodeGuard, dsPICDEM, dsPICDEM.net, ECAN, In-Circuit Serial Programming, ICSP, Inter-Chip Connectivity, KleerNet, KleerNet logo, MiWi, motorBench, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient Code Generation, PICDEM, PICDEM.net, PICkit, PICtail, RightTouch logo, REAL ICE, SQI, Serial Quad I/O, Total Endurance, TSHARC, USBCheck, VariSense, ViewSpan, WiperLock, Wireless DNA, and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. Silicon Storage Technology is a registered trademark of Microchip Technology Inc. in other countries. GestIC is a registered trademark of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in other countries. All other trademarks mentioned herein are property of their respective companies. © 2014-2015, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. ISBN: 978-1-5224-0075-2 QUALITY MANAGEMENT SYSTEM CERTIFIED BY DNV == ISO/TS 16949 ==  2014-2015 Microchip Technology Inc. Microchip received ISO/TS-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified. 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