UCS81003AMR-C1A

UCS81003 Automotive USB Port Power Controller with Charger Emulation Features General Description • Port Power Switch with Two Current Limit Behaviors - 2.9V to 5.5V Source Voltage Range - Up to 3.0A Current (2.85A typical) with 55 m on Resistance - Overcurrent Trip or Constant Current Limiting - Soft Turn-On Circuitry - Programmable Current Limit - Dynamic Thermal Management - Undervoltage and Overvoltage Lockout - Back-Drive, Back-Voltage Protection - Latch or Auto-Recovery (Low Test Current) Fault Handling - Selectable Active-High or Active-Low Power Switch Enable - BC1.2 VBUS Discharge Port Renegotiation Function • Selectable/Automatic Cycling of Universal Serial Bus (USB) Data Line Charger Emulation Profiles - USB-IF BC1.2 Charging Downstream Port (CDP) and Dedicated Charging Port (DCP) modes, Chinese Telecommunications Industry Standard YD/T 1591-2009 and most Apple® Inc. and RIM® Protocols Standard; others as defined via the SMBus 2.0/I2C Protocol - Supports 12W Charging Emulation - USB 2.0 Compliant High-Speed Data Switch (in Data Pass-Through, SDP and CDP modes) - Nine Preloaded Charger Emulation Profiles for Maximum Compatibility Coverage of the Peripheral Devices - One Custom-Programmable Charger Emulation Profile for Portable Device Support for Fully Host-Controlled Charger Emulation • Supports Active Cables • Self-Contained Current Monitoring and Rationing for Power-Allocation Applications • Low-Power Attach Detection and Open-Drain (A_DET#) Pin • Ultra Low-Power Sleep State • Optional Split Supply Support for VS and VDD for Low-Power in System Standby States • Wake on Attach USB • SMBus 2.0/I2C Communications - Supports Block Write and Read - Multiple SMBus Addresses • Wide Operating Temperature Range: -40°C to +85°C • IEC61000-4-2 8/15 kV Electrostatic Discharge (ESD) Immunity The UCS81003 provides a USB port power switch for precise control of up to 3.0A continuous current (2.85A typical) with Overcurrent Limit (OCL), dynamic thermal management, latch or auto-recovery (low-test current) fault handling, selectable active-low or activehigh enable, undervoltage and overvoltage lockout, back-drive protection and back-voltage protection.  2014-2018 Microchip Technology Inc. Split supply support for VS and VDD is an option for low power in system standby states. This gives batteryoperated applications (such as on-board computers) the ability to detect attachments from a Sleep or OFF state. After the Attach Detection is flagged, the system can decide to wake-up or provide charging, or both. In addition to Power Switching and Current Limiting modes, the UCS81003 automatically charges a wide variety of portable devices, including USB-IF BC1.2, YD/T-1591 (2009), most Apple Inc. and RIM, and many others. Nine preloaded charger emulation profiles maximize the compatibility coverage of the peripheral devices. Additionally, a customizable charger emulation profile is available to accommodate unique existing and future portable device handshaking/signature requirements. The UCS81003 also provides current monitoring to enable intelligent management of system power and charge rationing for controlled delivery of current, regardless of the host power state. This is especially important for battery-operated applications to provide power and not to excessively drain the battery. The UCS81003 is available in a 5 mm x 5 mm 28-pin VQFN package. Applications • • • • • DC Power Socket Replacement Consumer USB Port Protection Consumer Device Charging Port Auxiliary Box Charging Feature Rear Seat Entertainment Consumer Access Point DS20005334B-page 1 UCS81003 Package Type 22 NC 23 DMOUT 24 DPOUT 25 A_DET# M1 26 EM_EN 1 27 GND NC 28 NC UCS81003 5 x 5 VQFN* 21 NC 2 20 DMIN M2 3 19 DPIN VBUS 4 18 ALERT# VBUS2 5 17 SMCLK/S0 VBUS3 6 16 SMDATA/LATCH COMM_SEL/ILIM 7 15 NC 8 9 10 11 12 13 14 SEL VS1 VS2 VS3 VDD PWR_EN NC EP-29 * Includes Exposed Thermal Pad (EP); see Table 3-1. DS20005334B-page 2  2014-2018 Microchip Technology Inc. UCS81003 Block Diagram DPIN DMIN VDD USB 2.0 HS Data Switch & Charger Emulator VDD DMOUT Attach Detector VS GND DPOUT VBUS UVLO, OVLO Power Switch COMM_SEL/ILIM ALERT# A_DET# VDD Charger Control, Measurement, OCL Temp PWR_EN Interface, Logic SEL EM_EN M1 M2 SMCLK/S0 SMDATA/LATCH  2014-2018 Microchip Technology Inc. DS20005334B-page 3 UCS81003 1.0 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings † Voltage on VDD, VS and VBUS pins ....................................................................................................................-0.3 to 6V Pull-Up Voltage (VPULLUP) ................................................................................................................... -0.3 to VDD + 0.3V Data Switch Current (IHSW_ON), Switch On .......................................................................................................... ±50 mA Port Power Switch Current ..................................................................................................................... Internally limited Data Switch Pin Voltage To Ground (DPOUT, DPIN, DMOUT, DMIN); (VDD powered or unpowered) ...... -0.3 to VDD + 0.3V Differential Voltage Across Open Data Switch (DPOUT -DPIN, DMOUT - DMIN, DPIN - DPOUT, DMIN - DMOUT) .............VDD Voltage on any Other Pin to Ground ................................................................................................... -0.3 to VDD + 0.3V Current on any Other Pin ...................................................................................................................................... ±10 mA Package Power Dissipation ............................................................................................................................... Table 1-1 Maximum Junction Temperature Under Bias ........................................................................................................ +125°C Storage Temperature Range................................................................................................................... -55°C to +150°C Note: † Notice: Stresses above those listed under “Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. TABLE 1-1: POWER DISSIPATION SUMMARY Package JC JA De-rating Factor Above +25°C TA < +25°C Power Rating TA < +70°C Power Rating TA < +85°C Power Rating High K (see Note 1) 28-pin VQFN 5 x 5 mm 4°C/W 32°C/W 31.3 mW°/C 2470 mW 1220 mW 800 mW Low K (see Note 1) 28-pin VQFN 5 x 5 mm 4°C/W 51°C/W 19.6 mW°/C 1620 mW 800 mW 530 mW Board Note 1: Junction to ambient (JA) is dependent on the design of the thermal vias. Without thermal vias and thermal landing, the JA is approximately 77°C/W, including localized PCB temperature increase. This JA value is an estimate for a JEDEC® compliant 2S2P PCB with thermal vias. TABLE 1-2: ELECTRICAL CHARACTERISTICS Electrical Characteristics: Unless otherwise specified, VDD = 4.5V to 5.5V, VS = 2.9V to 5.5V, VPULLUP = 3V to 5.5V, TJ = -40°C to +125°C; all Typical values at VDD = VS = 5V, TJ = +27°C. Parameter Sym. Min. Typ. Max. Unit Conditions Power Supply Supply Voltage VDD 4.5 5 5.5 V Note 1 Source Voltage VS 2.9 5 5.5 V Note 1 IACTIVE — 650 750 µA Average current IBUS = 0 mA, TJ < +85°C Supply Current in Active (IDD_ACTIVE + IVS_ACT) Note 1: 2: 3: 4: 5: For split supply systems using the Attach Detection feature, VS must not exceed VDD + 150 mV. This parameter is ensured by design and is not 100% tested. This parameter is characterized, but not 100% production tested. The current measurement full-scale range maximum value is 3.0A. However, the UCS81003 cannot report values above ILIM (if IBUS_R2MIN  ILIM) or above IBUS_R2MIN (if IBUS_R2MIN > ILIM and ILIM 1.68A). The minimum and maximum values represent the boundaries of a programmable range. Each value in the range is typical. DS20005334B-page 4  2014-2018 Microchip Technology Inc. UCS81003 TABLE 1-2: ELECTRICAL CHARACTERISTICS (CONTINUED) Electrical Characteristics: Unless otherwise specified, VDD = 4.5V to 5.5V, VS = 2.9V to 5.5V, VPULLUP = 3V to 5.5V, TJ = -40°C to +125°C; all Typical values at VDD = VS = 5V, TJ = +27°C. Parameter Supply Current in Sleep (IDD_SLEEP + IVS_SLEEP) Supply Current in Detect (IDD_DETECT + IVS_DETECT) Sym. Min. Typ. Max. Unit ISLEEP — 5 15 µA Average current VPULLUP  VDD, TJ < +85°C Conditions IDETECT — 175 — µA Average current, no portable device attached Power-On Reset VS Low Threshold VS_UVLO — 2.5 — V VS voltage increasing VS Low Hysteresis VS_UVLO_HYST — 100 — mV VS voltage decreasing VDD Low Threshold VDD_TH — 4 — V VDD voltage increasing VDD Low Hysteresis VDD_TH_HYST — 500 — mV VDD voltage decreasing Pins I/O Pins – SMCLK, SMDATA, EM_EN, M1, M2, PWR_EN, S0, LATCH, ALERT#, A_DET# – DC Parameters Output Low Voltage VOL — — 0.4 V ISINK_IO = 8 mA SMDATA, ALERT#, A_DET# Input High Voltage VIH 2.1 — — V PWR_EN, EM_EN, M1, M2, LATCH, S0, SMDATA, SMCLK Input Low Voltage VIL — — 0.8 V PWR_EN, EM_EN, M1, M2, LATCH, S0, SMDATA, SMCLK Leakage Current ILEAK — — ±5 µA Powered or unpowered, VPULLUP  VDD, TJ < +85°C ALERT#, A_DET# Pin Blanking Time tBLANK — 25 — ms ALERT# Pin Interrupt Masking Time tMASK — 5 — ms Interrupt Pins – AC Parameters SMBus/I2C Timing Input Capacitance CIN — 5 — pF Clock Frequency fSMB 10 — 400 kHz — 50 ns Spike Suppression tSP Bus Free Time Stop to Start Note 2 tBUF 1.3 — — µs Start Setup Time tSU:STA 0.6 — — µs Start Hold Time tHD:STA 0.6 — — µs Stop Setup Time tSU:STO 0.6 — — µs Data Hold Time tHD:DAT 0 — — µs When transmitting to the Master Data Hold Time tHD:DAT 0.3 — — µs When receiving from the Master Data Setup Time tSU:DAT 0.6 — — µs Clock Low Period tLOW 1.3 — — µs Note 1: 2: 3: 4: 5: For split supply systems using the Attach Detection feature, VS must not exceed VDD + 150 mV. This parameter is ensured by design and is not 100% tested. This parameter is characterized, but not 100% production tested. The current measurement full-scale range maximum value is 3.0A. However, the UCS81003 cannot report values above ILIM (if IBUS_R2MIN  ILIM) or above IBUS_R2MIN (if IBUS_R2MIN > ILIM and ILIM 1.68A). The minimum and maximum values represent the boundaries of a programmable range. Each value in the range is typical.  2014-2018 Microchip Technology Inc. DS20005334B-page 5 UCS81003 TABLE 1-2: ELECTRICAL CHARACTERISTICS (CONTINUED) Electrical Characteristics: Unless otherwise specified, VDD = 4.5V to 5.5V, VS = 2.9V to 5.5V, VPULLUP = 3V to 5.5V, TJ = -40°C to +125°C; all Typical values at VDD = VS = 5V, TJ = +27°C. Sym. Min. Typ. Max. Unit Clock High Period Parameter tHIGH 0.6 — — µs Clock/Data Fall Time tFALL — — 300 ns Min = 20 + 0.1 CLOAD ns, Note 3 Clock/Data Rise Time tRISE — — 300 ns Min = 20 + 0.1 CLOAD ns, Note 3 Capacitive Load Timeout Idle Reset Conditions CLOAD — — 400 pF Per bus line, Note 2 tTIMEOUT 25 — 35 ms Disabled by default, Note 2 tIDLE_RESET 350 — — µs Disabled by default, Note 2 High-Speed Data Switch High-Speed Data Switch – DC Parameters Switch Leakage Current IHSW_OFF — ±0.5 — µA Switch open – DPIN to DPOUT, DMIN to DMOUT, or all four pins to ground. VDD  VS RCHG — 2 — M DPOUT or DMOUT to VBUS or ground (see Figure 1-2), BC1.2 DCP charger emulation active On Resistance RON_HSW — 2 —  Switch closed, VDD = 5V test current = 8 mA, test voltage = 0.4V, see Figure 1-2 On Resistance RON_HSW_1 — 5 —  Switch closed, VDD = 5V, test current = 8 mA, test voltage = 3.0V, see Figure 1-2 Delta-On Resistance RON_HSW — ±0.3 —  Switch closed, VDD = 5V, ITST = 8 mA, VTST = 0 to 1.5V, see Figure 1-2 Charger Resistance High-Speed Data Switch – AC Parameters DP, DM Capacitance to Ground CHSW_ON — 4 — pF Switch closed, VDD = 5V DP, DM Capacitance to Ground CHSW_OFF — 2 — pF Switch open, VDD = 5V Turn-Off Time tHSW_OFF — 400 — µs Time from state control (EM_EN, M1, M2) switch ON to switch OFF, RTERM = 50, CLOAD = 5 pF Turn-On Time tHSW_ON — 400 — µs Time from state control (EM_EN, M1, M2) switch OFF to switch ON, RTERM = 50, CLOAD = 5 pF Note 1: 2: 3: 4: 5: For split supply systems using the Attach Detection feature, VS must not exceed VDD + 150 mV. This parameter is ensured by design and is not 100% tested. This parameter is characterized, but not 100% production tested. The current measurement full-scale range maximum value is 3.0A. However, the UCS81003 cannot report values above ILIM (if IBUS_R2MIN  ILIM) or above IBUS_R2MIN (if IBUS_R2MIN > ILIM and ILIM 1.68A). The minimum and maximum values represent the boundaries of a programmable range. Each value in the range is typical. DS20005334B-page 6  2014-2018 Microchip Technology Inc. UCS81003 TABLE 1-2: ELECTRICAL CHARACTERISTICS (CONTINUED) Electrical Characteristics: Unless otherwise specified, VDD = 4.5V to 5.5V, VS = 2.9V to 5.5V, VPULLUP = 3V to 5.5V, TJ = -40°C to +125°C; all Typical values at VDD = VS = 5V, TJ = +27°C. Parameter Sym. Min. Typ. Max. Unit tPD — 0.25 — ns RTERM = 50, CLOAD = 5 pF Propagation Delay Skew tPD — 25 — ps RTERM = 50, CLOAD = 5 pF Rise/Fall Time tF/R — 10 — ns RTERM = 50, CLOAD = 5 pF DP – DM Crosstalk XTALK — -40 — dB RTERM = 50, CLOAD = 5 pF Off Isolation OIRR — -30 — dB RTERM = 50, CLOAD = 5 pF, f = 240 MHz -3 dB Bandwidth BW — 1100 — MHz RTERM = 50, CLOAD = 5 pF, VDPOUT = VDMOUT = 350 mV DC tJ — 200 — ps RTERM = 50, CLOAD = 5 pF, Rise Time = Fall Time = 500 ps at 480 Mbps (PRBS = 215 – 1) tSK(P) — 20 — ps RTERM = 50, CLOAD = 5 pF Propagation Delay Total Jitter Skew of Opposite Transitions of the Same Output Conditions Port Power Switch Port Power Switch – DC Parameters Overvoltage Lockout VS_OV — 6 — V On Resistance RON_PSW — 55 — m VS Leakage Current ILEAK_VS — 2.22 — µA Sleep state into VS pin Back-Voltage Protection Threshold VBV_TH — 150 — mV VBUS > VS, VS > VS_UVLO IBD_1 — 0 3 µA VDD < VDD_TH, Any powered power pin to any unpowered power pin. Current out of unpowered pin (Note 3). IBD_2 — 0 2 µA VDD < VDD_TH, Any powered power pin to any unpowered power pin, except for VDD to VBUS in Detect power state and VS to VBUS in Active power state. Current out of unpowered pin (Note 3). Back-Drive Current Note 1: 2: 3: 4: 5: 4.75V < VS < 5.25V For split supply systems using the Attach Detection feature, VS must not exceed VDD + 150 mV. This parameter is ensured by design and is not 100% tested. This parameter is characterized, but not 100% production tested. The current measurement full-scale range maximum value is 3.0A. However, the UCS81003 cannot report values above ILIM (if IBUS_R2MIN  ILIM) or above IBUS_R2MIN (if IBUS_R2MIN > ILIM and ILIM 1.68A). The minimum and maximum values represent the boundaries of a programmable range. Each value in the range is typical.  2014-2018 Microchip Technology Inc. DS20005334B-page 7 UCS81003 TABLE 1-2: ELECTRICAL CHARACTERISTICS (CONTINUED) Electrical Characteristics: Unless otherwise specified, VDD = 4.5V to 5.5V, VS = 2.9V to 5.5V, VPULLUP = 3V to 5.5V, TJ = -40°C to +125°C; all Typical values at VDD = VS = 5V, TJ = +27°C. Parameter Sym. Min. Typ. Max. Unit ILIM1 — 570 — mA ILIM2 — 1000 — ILIM Resistor = 10 k or 56 k ILIM3 — 1130 — ILIM Resistor = 12 k or 68 k ILIM4 — 1350 — ILIM Resistor = 15 k or 82 k ILIM5 — 1680 — ILIM Resistor = 18 k or 100 k ILIM6 — 2050 — ILIM Resistor = 22 k or 120 k ILIM7 — 2280 — ILIM Resistor = 27 k or 150 k ILIM8 — 2850 3000 Pin Wake Time tPIN_WAKE — 3 — ms SMBus Wake Time tSMB_WAKE — 4 — ms Idle Sleep Time tIDLE_SLEEP — 200 — ms TREG — 110 — °C Die Temperature at which current limit is reduced. TREG_HYST — 10 — °C Hysteresis for tREG functionality. Temperature must drop by this value before ILIM value restored to normal operation. Thermal Shutdown Threshold TTSD — 135 — °C Die Temperature at which port power switch turns OFF. Thermal Shutdown Hysteresis TTSD_HYST — 35 — °C After shutdown due to TTSD being reached, a die temperature drop is required before port power switch can be turned ON again. Auto-Recovery Test Current ITEST — 190 — mA Portable device attached, VBUS = 0V, Die Temp < TTSD Auto-Recovery Test Voltage VTEST — 750 — mV Portable device attached, VBUS = 0V before application, Die Temp < TTSD Programmable, 250-1000 mV, default listed RDISCHARGE — 100 —  Selectable Current Limits Thermal Regulation Limit Thermal Regulation Hysteresis Discharge Impedance Note 1: 2: 3: 4: 5: Conditions ILIM Resistor = 0 or 47 k (minimum mA setting) ILIM Resistor = 33 k or VDD For split supply systems using the Attach Detection feature, VS must not exceed VDD + 150 mV. This parameter is ensured by design and is not 100% tested. This parameter is characterized, but not 100% production tested. The current measurement full-scale range maximum value is 3.0A. However, the UCS81003 cannot report values above ILIM (if IBUS_R2MIN  ILIM) or above IBUS_R2MIN (if IBUS_R2MIN > ILIM and ILIM 1.68A). The minimum and maximum values represent the boundaries of a programmable range. Each value in the range is typical. DS20005334B-page 8  2014-2018 Microchip Technology Inc. UCS81003 TABLE 1-2: ELECTRICAL CHARACTERISTICS (CONTINUED) Electrical Characteristics: Unless otherwise specified, VDD = 4.5V to 5.5V, VS = 2.9V to 5.5V, VPULLUP = 3V to 5.5V, TJ = -40°C to +125°C; all Typical values at VDD = VS = 5V, TJ = +27°C. Parameter Sym. Min. Typ. Max. Unit Conditions tON_PSW — 0.75 — ms PWR_EN active toggle to switch on time, VBUS discharge not active. tOFF_ — 0.75 — ms PWR_EN inactive toggle to switch off time CBUS = 120 µF — 1 — ms Overcurrent Error, VBUS Min Error, or Discharge Error to switch off, CBUS = 120 µF — 100 — ns TSD or back-drive error to switch off, CBUS = 120 µF tR_BUS — 1.1 — ms Measured from 10% to 90% of VBUS, CLOAD = 220 µF, ILIM = 1.0A Soft Turn-On Rate IBUS/t — 100 — mA/µs Temperature Update Time tDC_TEMP — 200 — ms Programmable 200-1600 ms, default listed Short-Circuit Response Time tSHORT_LIM — 1.5 — µs Time from detection of short to current limit applied. No CBUS applied. Short-Circuit Detection Time tSHORT — 6 — ms Time from detection of short to port power switch disconnect and ALERT# pin assertion. tUL — 7 — ms From PWR_EN edge transition from inactive to active to begin error recovery. Auto-Recovery Mode Cycle Time tCYCLE — 25 — ms Time delay before error condition check. Programmable 10-25 ms, default listed. Auto-Recovery Delay tRST — 20 — ms Portable device attached, VBUS must be  VTEST after this time. Programmable 10-25 ms, default listed. tDISCHARGE — 200 — ms Amount of time discharge resistor applied. Programmable 100-400 ms, default listed. Port Power Switch – AC Parameters Turn-On Delay Turn-Off Time PSW_INA Turn-Off Time tOFF_ PSW_ERR Turn-Off Time tOFF_ PSW_ERR VBUS Output Rise Time Latched Mode Cycle Time Discharge Time Note 1: 2: 3: 4: 5: For split supply systems using the Attach Detection feature, VS must not exceed VDD + 150 mV. This parameter is ensured by design and is not 100% tested. This parameter is characterized, but not 100% production tested. The current measurement full-scale range maximum value is 3.0A. However, the UCS81003 cannot report values above ILIM (if IBUS_R2MIN  ILIM) or above IBUS_R2MIN (if IBUS_R2MIN > ILIM and ILIM 1.68A). The minimum and maximum values represent the boundaries of a programmable range. Each value in the range is typical.  2014-2018 Microchip Technology Inc. DS20005334B-page 9 UCS81003 TABLE 1-2: ELECTRICAL CHARACTERISTICS (CONTINUED) Electrical Characteristics: Unless otherwise specified, VDD = 4.5V to 5.5V, VS = 2.9V to 5.5V, VPULLUP = 3V to 5.5V, TJ = -40°C to +125°C; all Typical values at VDD = VS = 5V, TJ = +27°C. Parameter Sym. Min. Typ. Max. Unit Conditions Port Power Switch Operation With Trip Mode Current Limiting Region 2 Current Keep-Out IBUS_R2MIN — 0.12 — A VBUS_MIN 1.5 2.0 2.25 V Minimum VBUS ed at Output Note 5 Port Power Switch Operation with Constant Current Limiting (Variable Slope) Region 2 Current Keep-Out IBUS_R2MIN — 1.68 — A Minimum VBUS Allowed at Output VBUS_MIN 1.5 2.0 2.25 V Note 5 Current Measurement Current Measurement – DC Parameters Current Measurement Range Reported Current Measurement Resolution IBUS_M 0 — 2988.6 mA Range 0-255 LSB (see Note 4) DIBUS_M — 11.72 — mA 1 LSB — — ±2 — % — ±2 — LSB — 500 — µs Current Measurement Accuracy 180 mA < IBUS < ILIM IBUS < 180 mA Current Measurement – AC Parameter Sampling Rate — Charge Rationing Charge Rationing – DC Parameters Accumulated Current Measurement Accuracy — — ±4.5 — % tPCYCLE — 1 — s Charge Rationing – AC Parameter Current Measurement Update Time Attach/Removal Detection VBUS Bypass – DC Parameters On Resistance RON_BYP — 50 —  Leakage Current ILEAK_BYP — — 3 µA Switch off, TA < +85°C, Note 2 Current Limit IDET_CHG/ IBUS_BYP — 2 — mA VDD = 5V and VBUS > 4.75V — 800 — µA Programmable 200-1000 µA, default listed. Attach/Removal Detection – DC Parameters Attach Detection Threshold Note 1: 2: 3: 4: 5: IDET_QUAL For split supply systems using the Attach Detection feature, VS must not exceed VDD + 150 mV. This parameter is ensured by design and is not 100% tested. This parameter is characterized, but not 100% production tested. The current measurement full-scale range maximum value is 3.0A. However, the UCS81003 cannot report values above ILIM (if IBUS_R2MIN  ILIM) or above IBUS_R2MIN (if IBUS_R2MIN > ILIM and ILIM 1.68A). The minimum and maximum values represent the boundaries of a programmable range. Each value in the range is typical. DS20005334B-page 10  2014-2018 Microchip Technology Inc. UCS81003 TABLE 1-2: ELECTRICAL CHARACTERISTICS (CONTINUED) Electrical Characteristics: Unless otherwise specified, VDD = 4.5V to 5.5V, VS = 2.9V to 5.5V, VPULLUP = 3V to 5.5V, TJ = -40°C to +125°C; all Typical values at VDD = VS = 5V, TJ = +27°C. Parameter Primary Removal Detection Threshold Sym. Min. Typ. Max. Unit Conditions IREM_QUAL_ — 700 — µA Programmable 100-900 µA, default listed, Active power state — 800 — µA Programmable 200-1000 µA, default listed, Detect power state (see Section 8.4 “Removal Detection”). Time from Attach to A_DET# assert ACT Attach/Removal Detection – AC Parameters Attach Detection Time tDET_QUAL — 100 — ms Removal Detection Time tREM_QUAL — 1000 — ms tDE- — 800 — ms CBUS = 500 µF maximum, Programmable 200-2000 ms, default listed. Allowed Charge Time T_CHARGE Charger Emulation Profile General Emulation – DC Parameters Charging Current Threshold Charging Current Threshold Range IBUS_CHG — 175.8 — mA Default IBUS_ 11.72 — 175.8 mA Note 5 — 200  Connected between DPOUT and DMOUT, 0V < DPOUT = DMOUT < 3V CHG_RNG DP-DM Shunt Resistor Value RDCP_RES Response Magnitude (voltage divider option resistance range) SX_RXMAG_ DVDR 93 — 200 k Note 5 Resistor Ratio Range (voltage divider option) SX_RATIO 0.25 — 0.66 V/V Note 5 Resistor Ratio Accuracy (voltage divider option) SX_RATIO_ ACC — ±0.5 — % Average over range Response Magnitude (resistor option range) SX_RXMAG_ RES 1.8 — 150 k Note 5 Internal Resistor Tolerance (resistor option) SX_RXMAG_ RES_ACC — ±10 — % Average over range Response Magnitude (voltage option range) SX_RXMAG_ VOLT 0.4 — 2.2 V Note 5 Voltage Option Accuracy SX_RXMAG_ VOLT_ACC — ±1 — % No load, average over range Voltage Option Accuracy SX_RXMAG_ VOLT_ACC_ 150 — -6 — % 150 µA load, average over range Voltage Option Accuracy SX_RXMAG_ VOLT_ACC_ 250 — -10 — % 250 µA load, average over range Note 1: 2: 3: 4: 5: For split supply systems using the Attach Detection feature, VS must not exceed VDD + 150 mV. This parameter is ensured by design and is not 100% tested. This parameter is characterized, but not 100% production tested. The current measurement full-scale range maximum value is 3.0A. However, the UCS81003 cannot report values above ILIM (if IBUS_R2MIN  ILIM) or above IBUS_R2MIN (if IBUS_R2MIN > ILIM and ILIM 1.68A). The minimum and maximum values represent the boundaries of a programmable range. Each value in the range is typical.  2014-2018 Microchip Technology Inc. DS20005334B-page 11 UCS81003 TABLE 1-2: ELECTRICAL CHARACTERISTICS (CONTINUED) Electrical Characteristics: Unless otherwise specified, VDD = 4.5V to 5.5V, VS = 2.9V to 5.5V, VPULLUP = 3V to 5.5V, TJ = -40°C to +125°C; all Typical values at VDD = VS = 5V, TJ = +27°C. Sym. Min. Typ. Max. Unit Voltage Option Output Parameter SX_RXMAG_ VOLT_BC 0.5 — — V DMOUT = 0.6V, 250 µA load, Note 3 Conditions Response Magnitude (Zero Volt Option Range) SX_PUPD 10 — 150 µA SX_RXMAG_VOLT = 0 Note 5 Pull-Down Current Accuracy SX_PUPD _ACC_3p6 — ±5 — % DPOUT or DMOUT = 3.6V Compliance voltage Pull-Down Current SX_PUPD _ACC_BC 50 — — µA Setting = 100 µA DPOUT or DMOUT = 0.15V Compliance voltage, Note 3 Stimulus Voltage Threshold Range SX_TH 0.3 — 2.2 V Note 5 Stimulus Voltage Accuracy SX_TH_ ACC — ±2 — % Average over range Stimulus Voltage Accuracy SX_TH_ ACC_BC 0.25 — — V At SX_TH = 0.3V, Note 3 General Emulation – AC Parameters Emulation Reset Time tEM_RESET — 50 — ms Default Emulation Reset Time Range tEM_RESET_ 50 — 175 ms Note 5 0.8 — 12.8 s Note 5 Note 5 RNG Emulation Timeout Range tEM_ TIMEOUT Stimulus Delay, SX_TD Range tSTIM_DEL 0 — 100 ms Emulation Delay tRES_EM — — 0.5 s Note 1: 2: 3: 4: 5: Time from set impedance to impedance appears on DP/DM, Note 3. For split supply systems using the Attach Detection feature, VS must not exceed VDD + 150 mV. This parameter is ensured by design and is not 100% tested. This parameter is characterized, but not 100% production tested. The current measurement full-scale range maximum value is 3.0A. However, the UCS81003 cannot report values above ILIM (if IBUS_R2MIN  ILIM) or above IBUS_R2MIN (if IBUS_R2MIN > ILIM and ILIM 1.68A). The minimum and maximum values represent the boundaries of a programmable range. Each value in the range is typical. FIGURE 1-1: DS20005334B-page 12 USB Rise Time/Fall Time Measurement.  2014-2018 Microchip Technology Inc. UCS81003 VBUS RCHG DPOUT DPIN RCHG VTST ITST VBUS RCHG DMOUT DMIN RCHG VTST FIGURE 1-2: TABLE 1-3: ITST Description of DC Terms. TEMPERATURE SPECIFICATIONS Parameter Sym. Min. Operating Temperature Range TA -40 Storage Temperature Range TA -55 Typ. Max. Unit — +85 °C — +150 °C Conditions Temperature Ranges Thermal Package Resistances – see Table 1-1  2014-2018 Microchip Technology Inc. DS20005334B-page 13 UCS81003 2.0 TYPICAL PERFORMANCE CURVES Note: The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (for example, outside specified power supply range) and therefore outside the warranted range. Note: Unless otherwise indicated, VDD = VS = 5V, TJ = +27°C. Voltage (V) Voltage (V) 6 5 4 3 2 1 0 Current (A) VS = VDD = 5V, short applied at 16 ms 6 5 4 3 2 1 0 5 VDD ALERT# Pin IBUS Current 0 0 10 20 30 40 50 Time (ms) FIGURE 2-4: Power-Up Into a Short. 6 14 VBUS VS = VDD = 5V, ILIM = 2.05A (typical), short applied at 17.2 µs Voltage (V) 5 4 10 3 8 2 6 1 4 0 2 IBUS 0 -1 -2 -2 0 FIGURE 2-2: USB-IF High-Speed Eye Diagram (With Data Switch). 4 3 IBUS 2 2 1 1 VBUS 0 0 -1 -1 0 2 FIGURE 2-3: Power-Up. DS20005334B-page 14 4 6 Time (ms) 8 Short Applied After Time (µs) 40 Internal Power Switch Short 10 VBUS Voltage (V) Voltage (V) 5 5 4 4 3 FIGURE 2-5: Response. 6 Current (A) ALERT # 5 20 6 VS = VDD = 5V ILIM = 3A max. (2.85A typical), short applied at 2 ms 6 12 Current (A) FIGURE 2-1: USB-IF High-Speed Eye Diagram (Without Data Switch). VS = VDD = 5V M2 = 0, M1 = PWR_EN = 1 3 2 1 EM_EN 0 -1 0 FIGURE 2-6: 100 200 300 Time (ms) 400 500 VBUS Discharge Behavior.  2014-2018 Microchip Technology Inc. UCS81003 Note: Unless otherwise indicated, VDD = VS = 5V, TJ = +27°C. 90 70 60 On Resistance (m:) Off Isolation (dB) 80 70 60 50 40 30 20 DPOUT = DMOUT = 0.35V 30 20 0 0.1 FIGURE 2-7: Frequency. 1 10 Frequency (MHz) 100 -40 1000 Data Switch Off Isolation vs. 0 200 -2 180 -4 160 -6 -8 -10 -12 -14 10 35 Temperature (°C) 85 DPOUT = DMOUT = 3V 140 120 DPOUT = DMOUT = 0.15V 100 80 60 20 -18 0 -20 0.01 1 100 Frequency (MHz) FIGURE 2-8: Frequency. -40 10000 Data Switch Bandwidth vs. -15 FIGURE 2-11: vs.Temperature. 2.5 10 35 Temperature (°C) 60 85 RDCP_RES Resistance 1 VS = VDD = 5V 0.95 2.0 0.9 0.85 Time (ms) On Resistance (:) 60 40 DPOUT = DMOUT = 0.35V -16 -15 FIGURE 2-10: Power Switch On Resistance vs. Temperature. Resistance (:) Gain (dB) 40 10 10 0 0.01 50 1.5 1.0 0.8 Turn off time 0.75 0.7 Turn on time 0.65 0.6 0.5 0.55 DPOUT = DMOUT = 0.4V 0.5 0.0 -40 -15 FIGURE 2-9: vs. Temperature. 10 35 Temperature (°C) 60 85 Data Switch On Resistance  2014-2018 Microchip Technology Inc. -40 -15 FIGURE 2-12: vs. Temperature. 10 35 Temperature (°C) 60 85 Power Switch On/Off Time DS20005334B-page 15 UCS81003 Note: Unless otherwise indicated, VDD = VS = 5V, TJ = +27°C. 0 Current Limit Accuracy Threshold Voltage (V) 6 VDD = 5V 5.99 5.98 5.97 5.96 5.95 5.94 5.93 5.92 5.91 -40 -15 FIGURE 2-13: vs. Temperature. Note: Specification is 0% maximum and -10% minimum -3 -4 -5 -6 -7 -8 10 35 Temperature (°C) 60 85 VS Overvoltage Threshold -10 -40 -15 10 35 Temperature (°C) FIGURE 2-16: vs. Temperature. 3 60 85 Trip Current Limit Operation 5 2.9 4 VDD = 5V 2.8 VS = VDD = 5V 3 2.7 Accuracy (%) VS Threshold Voltage (V) -2 -9 5.9 2.6 Threshold 2.5 2.4 Hysteresis 2.3 2 1 0 -1 -2 2.2 -3 2.1 -4 2 -5 -40 -15 FIGURE 2-14: vs. Temperature. 10 35 Temperature (°C) 60 85 VS Undervoltage Threshold 0 0.5 1 FIGURE 2-17: Accuracy. 1.5 Current (A) 2 2.5 3 IBUS Measurement 800 5.5 5 4.5 4 3.5 3 2.5 2 1.5 1 0.5 0 700 VS = VDD = 5V S0 = '1' PWR_EN disabled 0 500 1000 1500 2000 2500 3000 3500 4000 Current (µA) FIGURE 2-15: DS20005334B-page 16 Detect State VBUS vs. IBUS. $FWLYH Current (µA) Voltage (V) VS = VDD = 5V ILIM = 3.0 A max. (2.85A typical) -1 IDD + IS 600 500 IS 400 300 IDD 200 100 VS = VDD = 5V 0 -40 FIGURE 2-18: Temperature. -15 10 35 Temperature (°C) 60 85 Active State Current vs.  2014-2018 Microchip Technology Inc. UCS81003 Note: Unless otherwise indicated, VDD = VS = 5V, TJ = +27°C. 250 Detect Current (µA) VS = VDD = 5V 200 IDD + IS 150 IDD 100 50 IS 0 -40 -15 FIGURE 2-19: Temperature. 10 Sleep Current (µA) 9 10 35 Temperature (°C) 60 85 Detect State Current vs. VS = VDD = 5V 8 IDD + IS 7 6 5 IDD 4 3 2 IS 1 0 -40 -15 FIGURE 2-20: Temperature. 10 35 Temperature (°C) 60 85 Sleep State Current vs.  2014-2018 Microchip Technology Inc. DS20005334B-page 17  2014-2018 Microchip Technology Inc. 3.0 PIN DESCRIPTION The function of the pins are listed in Table 3-1. TABLE 3-1: PIN FUNCTION TABLE UCS81003 5x5 VQFN Symbol 1 NC Function Not internally connected Pin Type n/a Connection Type if Pin Not Used Leave open 2 M1 Active mode selector input #1 DI Connect to ground or VDD (see Note 3) 3 M2 Active mode selector input #2 DI Connect to ground or VDD (see Note 3) 4 VBUS1 5 VBUS2 6 VBUS3 7 COMM_SEL/ILIM Voltage output from Power Switch These pins are internally connected and must be tied together. COMM_SEL – selects SMBus or Stand-Alone mode of operation (see Table 11-1). Hi-Power Note 1 Leave open AIO n/a n/a ILIM – selects the hardware current limit at power-up. 8 SEL Selects polarity of PWR_EN control and SMBus address (see Table 11-2). AIO 9 VS1 10 Voltage input to Power Switch. These pins are internally connected and must be tied together. Hi-Power VS2 11 VS3 12 VDD 13 PWR_EN 14 15 DS20005334B-page 18 3: Power n/a Port power switch enable input. Polarity is determined by SEL pin. DI Connect to ground or VDD (see Note 3) NC Not internally connected n/a Leave open NC Not internally connected n/a Leave open Total leakage current from pins 4, 5 and 6 (VBUS) to ground must be less than 100 µA for proper attach/removal detection operation. It is recommended to use 2 M pull-down resistors on the DPOUT or DMOUT pin, or both if a portable device stimulus is expected when using the Customer Charger Emulation profile with the high-speed data switch open. The 2 M value is based on BC1.1 impedance characteristics for Dedicated Charging Ports. To ensure operation, the PWR_EN pin must be enabled, as determined by the SEL pin decode, when it is not driven by an external device. Furthermore, one of the M1, M2 or EM_EN pins must be connected to VDD if all three are not driven from an external device. If the PWR_EN pin is disabled or all of the M1, M2, and EM_EN pins are connected to ground, the UCS81003 remains in the Sleep or Detect state unless activated via the SMBus. UCS81003 Note 1: 2: Main power supply input for chip functionality Connect to ground PIN FUNCTION TABLE UCS81003 5x5 VQFN Symbol 16 SMDATA/LATCH 17 SMCLK/S0 Function SMDATA - SMBus data input/output (requires pull-up resistor) Pin Type DIOD Connection Type if Pin Not Used n/a LATCH - In Stand-Alone mode, Latch/Auto-Recovery Fault Handling mechanism selection input (see Section 7.5 “Fault Handling Mechanism”) DI SMCLK - SMBus Clock Input (requires pull-up resistor) DI n/a Active-low error event output flag (requires pull-up resistor) OD Connect to ground S0 - In Stand-Alone mode, enables Attach/Removal Detection feature (see Section 5.3.6 “S0 Input”) 18 ALERT# 19 DPIN USB data input (plus) AIO Connect to ground or ground through a resistor 20 DMIN USB data input (minus) AIO Connect to ground or ground through a resistor 21 NC Not internally connected n/a Leave open Leave open 22 NC Not internally connected n/a 23 DMOUT USB data output (minus) AIO (see Note 2) USB data output (plus) Connect to ground  2014-2018 Microchip Technology Inc. 24 DPOUT AIO (see Note 2) Connect to ground 25 A_DET# Active-low device Attach Detection output flag (requires pull-up resistor) OD Connect to ground 26 EM_EN Active mode selector input DI Connect to ground or VDD (see Note 3) 27 GND 28 NC Not internally connected n/a Leave open 29 EP Exposed Thermal Pad. Must be connected to the electrical ground. EP n/a Note 1: 2: 3: Ground Power n/a Total leakage current from pins 4, 5 and 6 (VBUS) to ground must be less than 100 µA for proper attach/removal detection operation. It is recommended to use 2 M pull-down resistors on the DPOUT or DMOUT pin, or both if a portable device stimulus is expected when using the Customer Charger Emulation profile with the high-speed data switch open. The 2 M value is based on BC1.1 impedance characteristics for Dedicated Charging Ports. To ensure operation, the PWR_EN pin must be enabled, as determined by the SEL pin decode, when it is not driven by an external device. Furthermore, one of the M1, M2 or EM_EN pins must be connected to VDD if all three are not driven from an external device. If the PWR_EN pin is disabled or all of the M1, M2, and EM_EN pins are connected to ground, the UCS81003 remains in the Sleep or Detect state unless activated via the SMBus. UCS81003 DS20005334B-page 19 TABLE 3-1: UCS81003 The description of the pin types are listed in Table 3-2. TABLE 3-2: PIN TYPES DESCRIPTION Pin Type Power Hi-Power AIO DI Description This pin is used to supply power or ground to the device This pin is a high-current pin Analog Input/Output – this pin is used as an I/O for analog signals. Digital Input – this pin is used as a digital input. This pin is glitch-free. DIOD Open-Drain Digital Input/Output – this pin is bidirectional. It is open-drain and requires a pull-up resistor. This pin is glitch-free. OD Open-Drain Digital Output – used as a digital output. It is open-drain and requires a pull-up resistor. This pin is glitch-free. EP Exposed Thermal Pad DS20005334B-page 20  2014-2018 Microchip Technology Inc. UCS81003 4.0 TERMS AND ABBREVIATIONS Note: The M1, M2, PWR_EN and EM_EN pins each have configuration bits (_SET in Section 10.4.3 “Switch Configuration Register”) that may be used to perform the same function as the external pin state. These bits are accessed via the SMBus/I2C and are OR’d with the respective pin. This OR’d combination of pin state and register bit is referenced as the control. TABLE 4-1: TERMS AND ABBREVIATIONS Term/Abbreviation Description Active mode Active power state operation mode: Data Pass-Through, BC1.2 SDP, BC1.2 CDP, BC1.2 DCP or Dedicated Charger Emulation Cycle. Attach Detection An Attach Detection event occurs when the current drawn by a portable device is greater than IDET_QUAL for longer than tDET_QUAL. Attachment The physical insertion of a portable device into a USB port that UCS81003 is controlling. CC Constant Current CDM Charged Device Model. JEDEC® model for characterizing susceptibility of a device to damage from ESD. CDP or USB-IF BC1.2 CDP Charging Downstream Port. The combination of the UCS81003 CDP handshake and an active standard USB host comprises a CDP. This enables a BC1.2 compliant portable device to simultaneously draw current up to 1.5A while data communication is active. The USB high-speed data switch is closed in this mode. Charge Enable When a charger emulation profile is accepted by a portable device and charging commences. Charger Emulation Profile Representation of a charger comprised of DPOUT, DMOUT and VBUS signaling which makes a defined set of signatures or handshaking protocols. Connection USB-IF term which refers to establishing active USB communications between a USB host and a USB device. Current Limiting Mode Determines the action that is performed when the IBUS current reaches the ILIM threshold. Trip opens the port power switch. Constant Current (variable slope) enables VBUS to be dropped by the portable device. DCE Dedicated Charger Emulation. Charger emulation in which the UCS81003 can deliver power only (by default). No active USB data communication is possible when charging in this mode (by default). DCP or USB-IF BC1.2 DCP Dedicated Charging Port. This functions as a dedicated charger for a BC1.2 portable device. This enables the portable device to draw currents up to 1.5A with Constant Current Limiting (and beyond 1.5A with Trip Current Limiting). By default, no USB communications are possible. DC Dedicated Charger. A charger which inherently does not have USB communications such as an A/C wall adapter. Disconnection USB-IF term which refers to the loss of active USB communications between a USB host and a USB device. Dynamic Thermal Management The UCS81003 automatically adjusts port power switch limits and modes to lower internal power dissipation when the thermal regulation temperature value is approached. Enumeration A USB-specific term indicating that a host is detecting and identifying USB devices. Handshake Application of a charger emulation profile that requires a response. Two-way communication between the UCS81003 and the portable device. HBM Human Body Model HSW High-Speed Switch IBUS_R2MIN Current limiter mode boundary ILIM The IBUS current threshold used in current limiting. In Trip mode, when ILIM is reached, the port power switch is opened. In Constant Current mode, when the current exceeds ILIM, operation continues at a reduced voltage and increased current; if VBUS voltage drops below VBUS_MIN, the port power switch is opened.  2014-2018 Microchip Technology Inc. DS20005334B-page 21 UCS81003 TABLE 4-1: TERMS AND ABBREVIATIONS (CONTINUED) Term/Abbreviation Description Legacy USB devices that require non-BC1.2 signatures must be applied on the DPOUT and DMOUT pins to enable charging. OCL Overcurrent Limit POR Power-On Reset Portable Device USB device attached to the USB port. Power Thief A USB device that does not follow the handshaking conventions of a BC1.2 device or Legacy devices and draws current immediately upon receiving power (that is, a USB book light, portable fan, and so on). Removal Detection A Removal Detection event occurs when the current load on the VBUS pin drops to less than IREM_QUAL for longer than tREM_QUAL. Removal The physical removal of a portable device from a USB port controlled by the UCS81003. Response An action, usually in response to a stimulus, in charger emulation performed by the UCS81003 device via the USB data lines. SDP or USB-IF SDP Standard Downstream Port. The combination of the UCS81003 high-speed switch being closed with an upstream USB host present comprises a BC1.2 SDP. This enables a BC1.2 compliant portable device to simultaneously draw current up to 0.5A while data communication is active. Signature Application of a charger emulation profile without waiting for a response. One-way communication from the UCS81003 to the portable device. Stand-Alone Mode Indicates that the communications protocol is not active and all communications between the UCS81003 and a controller are done via the external pins only (M1, M2, EM_EN, PWR_EN, S0 and LATCH as inputs; ALERT# and A_DET# as outputs). Stimulus An event in charger emulation detected by the UCS81003 device via the USB data lines. DS20005334B-page 22  2014-2018 Microchip Technology Inc. UCS81003 5.0 GENERAL DESCRIPTION The UCS81003 provides a single USB port power switch for precise control of up to 3.0A continuous current with Overcurrent Limit (OCL), dynamic thermal management, latch or auto-recovery fault handling, selectable active-low or active-high enable, undervoltage and overvoltage lockout, and backvoltage protection. Split supply support for VBUS and VDD is an option for low power in system standby states. In addition to power switching and current limiting, the UCS81003 provides automatic and configurable charger emulation profiles to charge a wide variety of portable devices, including USB-IF BC1.2 (CDP or DCP modes), YD/T-1591 (2009), 12W charging, most Apple and RIM portable devices and many others. CIN 5V Figure 5-1 shows a UCS81003 full-featured system configuration in which the UCS81003 provides a port power switch and low-power Attach Detection with wake-up signaling (wake on USB). The current limit is established at power-up. It can be lowered if required after power-up via the SMBus/I2C. This configuration also provides configurable USB data line-charger emulation, programmable current limiting (as determined by the accepted charger emulation profile), active current monitoring, and port charge rationing. DPIN DPOUT DMIN DMOUT VS1 VBUS1 VS2 VBUS2 VS3 VBUS3 UCS81003 USB Host 5V Host The UCS81003 also provides current monitoring to enable intelligent management of system power and charge rationing for controlled delivery of current regardless of the host power state. This is especially important for battery-operated applications that must provide power without excessively draining the battery, or require power allocation depending on application activities. Device CBUS VDD 3V–5.5V EM_EN 3V–5.5V M1 M2 PWR_EN EC VDD SMDATA A_DET# SMCLK ALERT# SEL VDD COMM_SEL /ILIM GND FIGURE 5-1: Host). UCS81003 System Configuration (with Charger Emulation, SMBus Control and USB  2014-2018 Microchip Technology Inc. DS20005334B-page 23 UCS81003 Figure 5-2 shows a system configuration in which the UCS81003 provides a USB data switch, port power switch, low-power Attach Detection and portable device Attach/Removal Detection signaling. This configuration does not include configurable data line charger emulation, programmable current limiting or current monitoring and rationing. USB Host 5V Host CIN DPIN DPOUT DMIN DMOUT VS1 VBUS1 VS2 VBUS2 Device CBUS VBUS3 UCS81003 EM_EN VS3 3V–5.5V M1 M2 Latch Upon Fault Enable Detect State PWR_EN SEL 3V–5.5V LATCH S0 COMM_SEL/ILIM Disable Detect State Auto-recovery Upon Fault FIGURE 5-2: DS20005334B-page 24 5V VDD A_DET# GND ALERT# UCS81003 System Configuration (Charger Emulation, No SMBus, with USB Host).  2014-2018 Microchip Technology Inc. UCS81003 Figure 5-3 shows a system configuration in which the UCS81003 provides a port power switch, low-power Attach Detection and portable device attachment detected signaling. This configuration is useful for applications that provide USB BC1.2 or legacy data line handshaking, or both on the USB data lines, but still require port power switching and current limiting. 5V Host CIN DPIN DPOUT DMIN DMOUT VS1 VBUS1 VS2 VBUS2 USB Host (DP, DM) Device CBUS VBUS3 UCS81003 EM_EN VS3 3V–5.5V Enable Detect State M1 M2 Latch Upon Fault PWR_EN SEL 3V–5.5V LATCH S0 COMM_SEL/ILIM Disable Detect State FIGURE 5-3: Auto-recovery Upon Fault 5V VDD A_DET# GND ALERT# UCS81003 System Configuration (No SMBus, No Charger Emulation).  2014-2018 Microchip Technology Inc. DS20005334B-page 25 UCS81003 Figure 5-4 shows a system configuration in which the UCS81003 provides a port power switch, low-power Attach Detection, charger emulation (with no USB host) and portable device attachment detected signaling. This configuration is useful for wall adapter-type applications and cigarette-plug adapters. Nȍ DPIN DPOUT DMIN DMOUT 5V VS1 VBUS1 CIN VS2 VBUS2 Nȍ Device CBUS VBUS3 UCS81003 EM_EN VS3 3V–5.5V Enable Detect State M1 M2 Latch Upon Fault PWR_EN SEL 3V–5.5V LATCH S0 COMM_SEL/ILIM Disable Detect State Auto-recovery Upon Fault FIGURE 5-4: Emulation). 5.1 5V VDD A_DET# GND ALERT# UCS81003 System Configuration (No SMBus, No USB Host, with Charger UCS81003 Power States The UCS81003 has the following power states: TABLE 5-1: POWER STATES DESCRIPTION State Description OFF This power state is entered when the voltage at the VDD pin voltage is < VDD_TH. In this state, the device is considered OFF. The UCS81003 does not retain its digital states and register contents, nor respond to SMBus/I2C communications. The port power switch, bypass switch, and the high-speed data switches are turned OFF. See Section 5.1.1 “Off State Operation”. Sleep This is the lowest power state available. While in this state, the UCS81003 retains digital functionality, respond to changes in emulation controls and wake to respond to SMBus/I2C communications. The highspeed switch and all other functionality are disabled. See Section 5.1.2 “Sleep State Operation”. Detect This is a low-current power state. In this state, the device is actively looking for a portable device to be attached. The high-speed switch is disabled by default. While in this state, the UCS81003 retains the configuration and charge rationing data, but does not monitor the bus current. The SMBus/I2C communications is fully functional. See Section 5.1.3 “Detect State Operation”. Error This power state is entered when a fault condition exists. See Section 5.1.5 “Error State Operation”. Active This power state provides full functionality. While in this state, operations include activation of the port power switch, USB data line handshaking/charger emulation, and current limiting and charge rationing. See Section 5.1.4 “Active State Operation”. DS20005334B-page 26  2014-2018 Microchip Technology Inc. UCS81003 Table 5-2 shows the settings for the various power states, except OFF and Error. If VDD < VDD_TH, the UCS81003 is in the OFF state. To determine the mode of operation in the Active state, see Table 9-1. Note: Using configurations that are unlisted in Table 5-2 is not recommended and may produce undesirable results. TABLE 5-2: POWER STATES CONTROL SETTINGS M1, M2, EM_EN Portable Device Attached Power State VS PWR_EN S0 Sleep n/a disabled 0 Not set to Data Pass-Through. (Note 1) n/a enabled 0 All = 0b n/a Detect (see Section 8.0 “Detect State” n/a disabled 1 n/a n/a < VS_UVLO enabled 1 All  0b n/a > VS_UVLO enabled 1 All  0b No • High-Speed switch disabled (by default). • Automatic transition to Active state when conditions met (see Section 5.1.3.1 “Automatic Transition from Detect to Active”). > VS_UVLO enabled 0 All  0b n/a • High-Speed switch enabled/disabled based on mode. • Port power switch is ON at all times. • Attach and Removal Detection disabled. See Note 2. > VS_UVLO enabled 1 All  0b Yes • Port power switch is ON. • Removal Detection enabled. Active (see Section 9.0 “Active State”) Note 1: 2: n/a Behavior • All switches disabled. • VBUS is near ground potential. • The UCS81003 wakes to respond to SMBus communications. • High-Speed switch disabled (by default). • Port power switch disabled. • Host-Controlled transition to Active state (see Section 5.1.3.2 “Host-Controlled Transition from Detect to Active”). In order to transition from Active State Data Pass-Through mode into Sleep with these settings, change the M1, M2 and EM_EN pins before changing the PWR_EN pin. See Section 9.4 “Data Pass-Through (No Charger Emulation)”. If S0 = ’0’ and a portable device is not attached in DCE Cycle mode, the UCS81003 is cycling through charger emulation profiles (by default). There is no guarantee which charger emulation profile is applied first when a portable device is attached.  2014-2018 Microchip Technology Inc. DS20005334B-page 27 UCS81003 5.1.1 OFF STATE OPERATION When in the Sleep state, the first data byte read from the UCS81003 wakes the device; however, the data to be read returns all ‘0’s and must be considered invalid. This is dummy read byte is meant to wake the UCS81003. Subsequent read or write bytes are normally accepted. After the dummy read, the UCS81003 is in a higher power state (see Figure 5-6). The device returns to Sleep after the last communication, or if no further communication has occurred. The device is in the OFF state if VDD is less than VDD_TH. When the UCS81003 is in the OFF state it does nothing and all circuitry is disabled. Digital register values are not stored and the device does not respond to SMBus commands. 5.1.2 SLEEP STATE OPERATION When the UCS81003 is in the Sleep state, the device is in its lowest power state. The high-speed switch, bypass switch, and the port power switch are disabled. The Attach and Removal Detection feature is disabled. VBUS is near ground potential. The ALERT# pin is not asserted. If asserted prior to entering the Sleep state, the ALERT# pin is released. The A_DET# pin is released. SMBus activity is limited to single byte read or write. Figure 5-5 shows timing diagrams for waking the UCS81003 via external pins. Figure 5-6 shows the timing for waking the UCS81003 via SMBus. Wake with M1 or M2 to Active State Data Pass-through Mode (PWR_EN enabled, S0 = ‘0’, EM_EN = ‘0’, VS > VS_UVLO) M1 or M2 tPIN_WAKE Port power switch closed (Active state) Wake with S0 (VS > VS_UVLO, M1 & M2 & EM_EN not all ‘0’ and not set to Data Pass-through) S0 tPIN_WAKE Bypass switch closed (Detect state) FIGURE 5-5: Wake Timing via External Pins. SMBus Read Dummy read returns invalid data and places device in temporary Active state S 0101_111 0 A 0001_0000 Power State Sleep FIGURE 5-6: DS20005334B-page 28 A S 0101_111 1 A Read returns valid data invalid data NP S 0101_111 0 A 0001_0000 tSMB_WAKE temporary Active state (not all functionality available) A S 0101_111 1 A valid data NP tIDLE_SLEEP Sleep Wake via SMBus Read with S0 = ‘0’.  2014-2018 Microchip Technology Inc. UCS81003 5.1.3 DETECT STATE OPERATION 5.1.3.3 State Change from Detect to Active When the UCS81003 is in the Detect state, the port power switch is disabled. The high-speed switch is also disabled by default. The VBUS output is connected to the VDD voltage by a secondary bypass switch (see Section 8.0 “Detect State”). When conditions cause the UCS81003 to transition from the Detect state to the Active state, the following occurs: There is one non-recommended configuration which places the UCS81003 in the Detect state, but VBUS is not discharged and a portable device attachment is not detected. For the recommended configurations, see Table 5-2. 2. 3. There are two methods for transitioning from the Detect state to the Active state: automatic and host-controlled. 5.1.3.1 Automatic Transition from Detect to Active For the Detect state, set S0 to ‘1’, enable PWR_EN, set the EM_EN, M1, and M2 controls to the desired Active mode (Table 9-1), and supply VS > VS_UVLO. When a portable device is attached and an Attach Detection event occurs, the UCS81003 automatically transitions to the Active state and operate according to the selected Active mode. 5.1.3.2 Host-Controlled Transition from Detect to Active For the Detect state, set S0 to ‘1’, set the EM_EN, M1, and M2 controls to the desired Active mode (Table 9-1), and configure one of the following: • disable PWR_EN and supply VS , or • enable PWR_EN and do not supply VS. When a portable device is attached and an Attach Detection event occurs, the host must respond to transition to the Active state. Depending on the control settings in the Detect state, this entails: • enabling PWR_EN, or • supplying VS above the threshold. Note: If S0 is '1', PWR_EN is enabled and VS is not present, the A_DET# pin cycles if the current draw exceeds the current capacity of the bypass switch. 1. 4. The Attach Detection feature is disabled and the Removal Detection feature remains enabled unless S0 is changed to ‘0’. The bypass switch is turned OFF. The discharge switch is turned ON briefly for tDISCHARGE. The port power switch is turned ON. 5.1.4 ACTIVE STATE OPERATION Whenever the UCS81003 enters the Active state and the port power switch is closed, it enters the mode as instructed by the host controller (see Section 9.0 “Active State”). The UCS81003 cannot be in the Active state (therefore, the port power switch cannot be turned ON) if any of the following conditions exist: • • • • VS < VS_UVLO PWR_EN is disabled. M1, M2, and EM_EN are all set to '0' . S0 is set to ‘1’ and an Attach Detection event did not occur. 5.1.5 ERROR STATE OPERATION The UCS81003 enters the Error state from the Active state when any of the following events are detected: • Maximum allowable internal die temperature is exceeded (TTSD) (see Section 7.2.1.2 “Thermal Shutdown”). • An overcurrent condition (see Section 7.1.1 “Current Limit Setting”). • An undervoltage condition on VBUS (see Section 5.2.5 “Undervoltage Lockout on VS”). • A back-drive condition (see Section 5.2.3 “Backvoltage Detection”). • A discharge error (see Section 7.3 “VBUS Discharge”). • An overvoltage condition on the VS pins. The UCS81003 enters the Error state from the Detect state when a back-drive condition is detected or when the maximum allowable internal die temperature is exceeded. The UCS81003 enters the Error state from the Sleep state when a back-drive condition is detected. When the UCS81003 enters the Error state, the port power switch, VBUS bypass switch, and the high-speed switch are turned OFF, and the ALERT# pin is asserted (by default). These switches remain OFF while in this power state. The UCS81003 leaves this state as determined by the fault handling selection (see Section 7.5 “Fault Handling Mechanism”).  2014-2018 Microchip Technology Inc. DS20005334B-page 29 UCS81003 When using the Latch fault handler and the user has reactivated the device by clearing the ERR bit (see Section 10.3 “Status Registers”), or toggling the PWR_EN control, the UCS81003 checks that all of the error conditions are removed. If using Auto-Recovery Fault Handler, after the tCYCLE time period, the UCS81003 checks that all of the error conditions are removed. If all of the error conditions are removed, the UCS81003 returns to the Active state or Detect state as applicable. Returning to the Active state causes the UCS81003 to restart the selected mode (see Section 9.2 “Active Mode Selection”). If the device is in the Error state and a Removal Detection event occurs, it checks the error conditions and then returns to the power state as defined by the PWR_EN, M1, M2, EM_EN, and S0 controls. 5.2 5.2.1 Supply Voltages VDD SUPPLY VOLTAGE The UCS81003 requires 4.5V to 5.5V to be present on the VDD pin for core device functionality. Core device functionality consists of maintaining register states, wake-up upon SMBus/I2C query and Attach Detection. 5.2.2 BACK-VOLTAGE DETECTION Whenever the following conditions are true, the port power switch, the VBUS bypass switch, and the highspeed data switch are disabled, and a back-voltage event is flagged. This causes the UCS81003 to enter the Error power state (see Section 5.1.5 “Error State Operation”). • The VBUS voltage exceeds the VS voltage by VBV_TH and the port power switch is closed. The port power switch is immediately opened. If the condition lasts for longer than tMASK, then the UCS81003 enters the Error state. Otherwise, the port power switch is turned ON as soon as the condition is removed. • The VBUS voltage exceeds the VDD voltage by VBV_TH and the VBUS bypass switch is closed. The bypass switch is immediately opened. If the condition lasts for longer than tMASK, then the UCS81003 enters the Error state. Otherwise, the bypass switch is turned ON as soon as the condition is removed. DS20005334B-page 30 BACK-DRIVE CURRENT PROTECTION If a self-powered portable device is attached, it may drive the VBUS port to its power supply voltage level; however, the UCS81003 is designed such that leakage current from the VBUS pins to the VDD or VS pins shall not exceed IBD_1 (if the VDD voltage is zero) or IBD_2 (if the VDD voltage exceeds VDD_TH). 5.2.5 UNDERVOLTAGE LOCKOUT ON VS The UCS81003 requires a minimum voltage (VS_UVLO) to be present on the VS pin for Active power state. 5.2.6 OVERVOLTAGE DETECTION AND LOCKOUT ON VS The UCS81003 port power switch is disabled if the voltage on the VS pin exceeds a voltage (VS_OV) for longer than the specified time (tMASK). This causes the device to enter the Error state. 5.3 Note: VS SOURCE VOLTAGE VS can be a separate supply and can be greater than VDD to accommodate high-current applications in which current path resistances result in unacceptable voltage drops that may prevent optimal charging of some portable devices. 5.2.3 5.2.4 5.3.1 Discrete Input Pins If it is necessary to connect any of the control pins except the COMM_SEL/ILIM or SEL pins via a resistor to VDD or GND, the resistor value must not exceed 100 k in order to meet the VIH and VIL specifications. COMM_SEL/ILIM INPUT The COMM_SEL/ILIM input determines the initial ILIM settings and the communications mode as shown in Table 11-1. 5.3.2 SEL INPUT The SEL pin selects the polarity of the PWR_EN control. In addition, if the UCS81003 is not configured to operate in Stand-Alone mode, the SEL pin determines the SMBus address. See Table 11-2. The SEL pin state is latched upon device power-up and further changes have no effect. 5.3.3 M1, M2, AND EM_EN INPUTS The M1, M2, and EM_EN input controls determine the Active mode and affect the power state (see Table 5-2 and Table 9-1). When these controls are all set to ‘0’ and PWR_EN is enabled, the UCS81003 Attach and Removal Detection feature is disabled. In SMBus mode, the M1, M2, and EM_EN pin states are ignored by the UCS81003 if the PIN_IGN configuration bit is set (see Section 10.4.3 “Switch Configuration Register”); otherwise, the M1_SET, M2_SET, and EM_EN_SET configuration bits (see Section 10.4.3 “Switch Configuration Register”) are checked along with the pins.  2014-2018 Microchip Technology Inc. UCS81003 5.3.4 PWR_EN INPUT The PWR_EN control enables the port power switch to be turned ON if conditions are met and affects the power state (see Table 5-2). The port power switch cannot be closed if PWR_EN is disabled. However, if PWR_EN is enabled, the port power switch is not necessarily closed (see Section 5.1.4 “Active State Operation”). Polarity is controlled by the SEL pin. In SMBus mode, the PWR_EN pin state is ignored by the UCS81003 if the PIN_IGN configuration bit is set (see Section 10.4.3 “Switch Configuration Register”); otherwise, the PWR_ENS configuration bit (see Section 10.4.3 “Switch Configuration Register”) is checked along with the pin. 5.3.5 LATCH INPUT The Latch input control determines the behavior of the fault handling mechanism (see Section 7.5 “Fault Handling Mechanism”). When the UCS81003 is configured to operate in StandAlone mode (see Section 11.3 “Stand-Alone Operating Mode”), the LATCH control is available exclusively via the LATCH pin (see Table 11-10). When the UCS81003 is configured to operate in SMBus mode, the LATCH control is available exclusively via the LATCHS configuration bit (see Section 10.4.3 “Switch Configuration Register”). 5.3.6 S0 INPUT The S0 control enables the Attach and Removal Detection feature and affects the power state (see Table 5-2). When S0 is set to ‘1’, an Attach Detection event must occur before the port power switch can be turned ON (this statement requires PWR_EN_BEH OTP bit is set to ‘1’). When S0 is set to ‘0’, the Attach and Removal Detection feature is not enabled. When the device is configured to operate in SMBus mode (see Section 11.3 “Stand-Alone Operating Mode”), the S0 control is available exclusively via the S0_SET configuration bit (see Section 10.4.3 “Switch Configuration Register”). Otherwise, the S0 control is exclusively available via the S0 pin since the SMBus protocol is disabled.  2014-2018 Microchip Technology Inc. 5.4 5.4.1 Discrete Output Pins ALERT# AND A_DET# OUTPUT PINS The ALERT# pin is an active-low open-drain interrupt to the host controller. The ALERT# pin is asserted (by default - see ALERT_MASK in Section 10.4.1 “General Configuration Register”) when an error occurs (see Register 10-3). The ALERT# pin can also be asserted when the LOW_CUR (portable device is pulling less current and may be finished charging) or TREG (thermal regulation temperature exceeded) bits are set and linked. As well, when charge rationing is enabled, the ALERT# pin is asserted by default when the current rationing threshold is reached as determined by RATION_BEH (see Table 7-1). The ALERT# pin is released when all error conditions that may assert the ALERT# pin (such as an error condition, charge rationing, and TREG and LOW_CHG if linked) are removed or reset as necessary. The A_DET# pin provides an active-low open-drain output indication that a valid Attach Detection event has occurred. It remains asserted until the UCS81003 is placed into the Sleep state or a Removal Detection event occurs. For wake on USB, the A_DET# pin assertion can be utilized by the system. If the S0 control is ‘0’ and the UCS81003 is in the Active state, the A_DET# pin is asserted regardless if a portable device is attached or not. If S0 is '1', PWR_EN is enabled and VS is not present, the A_DET# pin cycles if the current draw exceeds the current capacity of the bypass switch. 5.4.2 INTERRUPT BLANKING The ALERT# and A_DET# pins are not asserted for a specified time (up to tBLANK) after power-up. Additionally, an error condition (except for the thermal shutdown) must be present for longer than a specified time (tMASK) before the ALERT# pin is asserted. DS20005334B-page 31 UCS81003 6.0 USB HIGH-SPEED DATA SWITCH The UCS81003 contains a series USB 2.0-compliant high-speed switch between the DPIN and DMIN pins and between the DPOUT and DMOUT pins. This switch is designed for high-speed, low-latency functionality to enable USB 2.0 full-speed and high-speed communications with minimal interference. Nominally, the switch is closed in the Active state, enabling uninterrupted USB communications between the upstream host and the portable device. The switch is opened when: • The UCS81003 is actively emulating using any of the charger emulation profiles except CDP (by default - see Section 10.4.5 “High-Speed Switch Configuration Register”). • The UCS81003 is operating as a dedicated charger unless the HSW_DCE configuration bit is set (see Section 10.4.5 “High-Speed Switch Configuration Register”). • The UCS81003 is in the Detect state (by default) or in the Sleep state. Note: 6.1 If the VDD voltage is less than VDD_TH, the high-speed data switch is disabled and opened. USB-IF High-Speed Compliance The USB data switch does not significantly degrade the signal integrity through the device DP/DM pins with USB high-speed communications. DS20005334B-page 32  2014-2018 Microchip Technology Inc. UCS81003 7.0 USB PORT POWER SWITCH To assure compliance to various charging specifications, the UCS81003 contains a USB port power switch that supports two current-limiting modes: Trip and Constant Current (variable slope). The current limit (ILIM) is pin selectable (and may be updated via the register set). The switch also includes soft start circuitry and a separate short-circuit current limit. The port power switch is ON in the Active state (except when VBUS is discharging). 7.1 7.1.1 Current Limiting CURRENT LIMIT SETTING The UCS81003 hardware set current limit (ILIM), can be one of eight values (see Table 11-1). This resistor value is read once upon UCS81003 power-up. The current limit can be changed via the SMBus/I2C after powerup; however, the programmed current limit cannot exceed the hardware set current limit. At power-up, the communication mode (Stand-Alone or SMBus/I2C) and hardware current limit (ILIM) are determined via the pull-down resistor (or pull-up resistor, if connected to VDD) on the COMM_SEL/ILIM pin as shown in Table 11-1. 7.1.2 SHORT CIRCUIT OUTPUT CURRENT LIMITING Short circuit current limiting occurs when the output current is above the selectable current limit (ILIMx). This event is detected and the current immediately becomes limited (within tSHORT_LIM time). If the condition remains, the port power switch flags an Error condition and enters the Error state (see Section 5.1.5 “Error State Operation”). 7.1.3 SOFT START When the PWR_EN control changes its state to enable the port power switch, or an Attach Detection event occurs in the Detect power state and the PWR_EN control is enabled, the UCS81003 invokes a soft start routine for the duration of the VBUS rise time (tR_BUS). This soft start routine limits current flow from VS into VBUS while it is active. This circuitry prevents current spikes due to a step in the portable device current draw. In the case when a portable device is attached while the PWR_EN pin is enabled, if the bus current exceeds ILIM, the UCS81003 current limiter responds within a specified time (tSHORT_LIM) and operates normally at this point. The CBUS capacitor delivers the extra current, if any, as required by the load change. 7.1.4 closed. The current limiting mode used depends on the Active state mode (see Section 9.9 “Current Limit Mode Associations”). When operating in the Detect power state (see Section 5.1.3 “Detect State Operation”), the current capacity at VBUS is limited to IBUS_BYP as described in Section 8.2 “VBUS Bypass Switch”. 7.1.4.1 Trip Mode When using Trip Current Limiting, the UCS81003 USB port power switch functions as a low-resistance switch and rapidly turns OFF if the current limit is exceeded. While operating using Trip Current Limiting, the VBUS output voltage is held relatively constant (equal to the VS voltage minus the RON x IBUS current) for all current values up to the ILIM. If the current drawn by a portable device exceeds ILIM, the following occurs: 1. 2. 3. The port power switch is turned OFF (Trip action). The UCS81003 enters the Error state and assert the ALERT# pin. The fault handling circuitry determines subsequent actions. Trip Current Limiting is used by default when the UCS81003 is in Data Pass-Through and Dedicated Charger Emulation Cycle (except when the BC1.2 DCP charger emulation profile is accepted), and when there is no handshake. This method is also used when charger emulation is active. Note: 7.1.4.2 To avoid cycling in Trip mode, set ILIM higher than the highest expected portable device current draw. Constant Current Limiting (Variable Slope) Constant Current Limiting is used when a portable device handshakes using the BC1.2 DCP charger emulation profile and the current drawn is greater than ILIM (and ILIM < 1.68A). It is also used in BC1.2 CDP mode and during the DCE Cycle when a charger emulation profile is being applied and the emulation timeout is active. In CC mode, the port power switch enables the attached portable device to reduce VBUS output voltage to less than the input VS voltage while maintaining current delivery. The V/I slope depends on the user set ILIM value. This slope is held constant for a given ILIM value. CURRENT-LIMITING MODES The UCS81003 current limiting has two modes: Trip and Constant Current (variable slope). Either mode functions at all times when the port power switch is  2014-2018 Microchip Technology Inc. DS20005334B-page 33 UCS81003 7.2 7.2.1 Thermal Management and Voltage Protection THERMAL MANAGEMENT If the UCS81003 internal temperature drops below TREG – TREG_HYST, the UCS81003 takes action based on the following: 1. The UCS81003 utilizes two-stage internal thermal management: Dynamic Thermal Management and Fixed Thermal Shutdown. 7.2.1.1 Dynamic Thermal Management For the first stage (active in both current limiting modes), referred to as Dynamic Thermal Management, the UCS81003 automatically adjusts port power switch limits and modes to lower power dissipation when the thermal regulation temperature value is approached as described below. If the internal temperature exceeds the TREG value, the port power switch is opened, the current limit (ILIM) is lowered by one step and a timer is started (tDC_TEMP). When this timer expires, the port power switch is closed and the internal temperature is checked again. If it remains above the TREG threshold, the UCS81003 repeats this cycle (opens port power switch and reduces the ILIM setting by one step) until ILIM reaches its minimum value. Note 1: If the temperature exceeds the TREG threshold while operating in the DCE Cycle mode after a charger emulation profile is accepted, the profile is removed. The UCS81003 does not restart the DCE Cycle until one of the control inputs changes state to restart emulation. 2: The UCS81003 does not actively discharge VBUS as a result of the temperature exceeding TREG; however, any load current provided by a portable device or other load causes VBUS to be discharged when the port power switch is opened, possibly resulting in an attached portable device resetting. If the UCS81003 is operating using Constant Current Limiting (variable slope) and the ILIM setting is reduced to its minimum set point and the temperature is still above TREG, the UCS81003 switches to operating using Trip Current Limiting. This is done by reducing the IBUS_R2MIN setting to 120 mA and restoring the ILIM setting to the value immediately below the programmed setting (for example, if the programmed ILIM is 2.05A, the value is set to 1.68A). If the temperature continues to remain above TREG, the UCS81003 continues this cycle (open the port power switch and reduce the ILIM setting by one step). DS20005334B-page 34 2. If the Current Limit mode changed from CC mode to Trip mode, then a timer is started. When this timer expires, the UCS81003 resets the port power switch operation to its original configuration, enabling it to operate using Constant Current Limiting (variable slope). If the Current Limit mode did not change from CC mode to Trip mode, or has started operating in Trip mode, the UCS81003 resets the port power switch operation to its original configuration. If the UCS81003 is operating using Trip Current Limiting and the ILIM setting is reduced to its minimum set point and the temperature is above TREG, the port power switch is closed and the current limit is held at its minimum setting until the temperature drops below TREG – TREG_HYST. 7.2.1.2 Thermal Shutdown The second-stage thermal management consists of a hardware implemented thermal shutdown corresponding to the maximum allowable internal die temperature (TTSD). If the internal temperature exceeds this value, the port power switch immediately turns OFF until the temperature is below TTSD – TTSD_HYST. 7.3 VBUS Discharge The UCS81003 discharges VBUS through an internal 100 resistor when at least one of the following conditions occurs: • The PWR_EN control is disabled (triggered on the inactive edge of the PWR_EN control). • A portable device Removal Detection event is flagged. • The VS voltage drops below a specified threshold (VS_UVLO) that causes the port power switch to be disabled. • When commanded into the Sleep power state via the EM_EN, M1, and M2 controls. • Before each charger emulation profile is applied (UCS81003AM and UCS81003AB), unless it is a power-up condition (UCS81003AB only). • Upon recovery from the Error state. • When commanded via the SMBus (see Section 10.4 “Configuration Registers”) in the Active state. • Any time that the port power switch is activated after the VBUS bypass switch is ON (that is, whenever VBUS voltage transitions from being driven from VDD to being driven from VS, such as going from Detect to Active power state). • Any time that the VBUS bypass switch is activated after the port power switch is ON (that is, going from Active to Detect power state).  2014-2018 Microchip Technology Inc. UCS81003 When the VBUS discharge circuitry is activated, at the end of the tDISCHARGE time, the UCS81003 confirms that VBUS is discharged. If the VBUS voltage is not below the VTEST level, a discharge error is flagged (by setting the DISCH_ERR status bit) and the UCS81003 enters the Error state. 7.4 Battery Full Delivery of bus current to a portable device can be rationed by the UCS81003. When this functionality is enabled, the host system must provide the UCS81003 with an accumulated charge maximum limit (in mAh). The charge rationing functionality works only in the Active power state. It continuously monitors the current TABLE 7-1: delivered and the time elapsed since the mode is activated (or since the data is updated). This information is compiled to generate a charge-rationing number that is checked against the host limit. Once the programmed current-rationing limit is reached, the UCS81003 takes action as determined by the RATION_BEH bits as described in Table 7-1. Note that this does not cause the device to enter the Error state. Once the charge rationing circuitry has reached the programmed threshold, the UCS81003 maintains the desired behavior until charge rationing is reset. Once charge rationing is reset or disabled, the UCS81003 recovers as shown in Table 7-2. CHARGE RATIONING BEHAVIOR RATION_BEH Behavior Actions taken Notes 1 0 0 0 0 1 Report 1. and 2. Disconnect (default) 3. ALERT# pin asserted. Charger emulation profile removed. Port power switch disconnected. The HSW is not affected. All bus monitoring is still active. Changing the M1, M2, EM_EN, S0, and PWR_EN controls causes the device to change power states as defined by the pin combinations; however, the port power switch remains OFF until the rationing circuitry is reset. Furthermore, the bypass switch is not turned ON if enabled via the S0 control. 1 0 Disconnect 1. and Go to Sleep 2. Port power switch disconnected. Charger emulation profile removed. Device enters the Sleep state. The HSW is disabled. All VBUS and VS monitoring are stopped. Changing the M1, M2, EM_EN, S0, and PWR_EN controls has no effect on the power state until the rationing circuitry is reset. Report ALERT# pin asserted. 3. 1 Ignore 1 TABLE 7-2: CHARGE RATIONING RESET BEHAVIOR Behavior Report Reset Actions 1. 2. 3. Report 1. and Disconnect 2. 3. 4. Note 1: Take no further action. Reset the Total Accumulated Charge registers. Clear the RATION status bit. Release the ALERT# pin. Reset the Total Accumulated Charge registers. Clear the RATION status bit. Release the ALERT# pin. Check the M1, M2, EM_EN, S0 and PWR_EN controls and enter the indicated power state if the controls changed (Note 1). Any time the charge rationing circuitry checks the pin conditions when changing rationing behavior or resetting charge rationing, if the external pin conditions changed, then charger emulation is restarted (provided emulation is enabled via the pin states). If the pin conditions did not change, the UCS81003 returns to the previous power state as if the rationing threshold is not reached (for example, it does not discharge VBUS or restart emulation).  2014-2018 Microchip Technology Inc. DS20005334B-page 35 UCS81003 TABLE 7-2: CHARGE RATIONING RESET BEHAVIOR (CONTINUED) Behavior Reset Actions Disconnect 1. and Go to Sleep 2. 3. Ignore Note 1: 7.4.1 1. 2. Reset the Total Accumulated Charge registers. Clear the RATION status bit. Check the M1, M2, EM_EN, S0, and PWR_EN controls and enter the indicated power state if the controls changed (Note 1). Reset the Total Accumulated Charge registers. Clear the RATION status bit. Any time the charge rationing circuitry checks the pin conditions when changing rationing behavior or resetting charge rationing, if the external pin conditions changed, then charger emulation is restarted (provided emulation is enabled via the pin states). If the pin conditions did not change, the UCS81003 returns to the previous power state as if the rationing threshold is not reached (for example, it does not discharge VBUS or restart emulation). CHARGE RATIONING INTERACTIONS When charge rationing is active, regardless of the specified behavior, the UCS81003 normally functions until the charge rationing threshold is reached. Note that charge rationing is only active when the UCS81003 is in the Active state, and it does not automatically resets when a Removal or Attach Detection event occurs. Charger emulation starts over if a Removal Detection event and Attach Detection event occur while charge rationing is active and the charge rationing threshold is not reached. This enables charging of sequential portable devices while charge is being rationed, which means that the accumulated power given to several portable devices is still held to the stated rationing limit. TABLE 7-3: EFFECTS OF CHANGING RATIONING BEHAVIOR AFTER THRESHOLD REACHED Previous Behavior Ignore Note 1: Changing the charge rationing behavior has no effect on the charge rationing data registers. If the behavior is changed prior to reaching the charge rationing threshold, this change occurs and become transparent to the user. When the charge rationing threshold is reached, the UCS81003 takes action as shown in Table 7-1. If the behavior is changed after the charge rationing threshold is reached, the UCS81003 immediately adopts the newly programmed behavior, clearing the ALERT# pin and restoring switch operation respectively (see Table 7-3). New Behavior Actions taken Report Assert ALERT# pin. Report and Disconnect 1. 2. 3. Assert ALERT# pin. Remove charger emulation profile. Open port power switch. See the Report and Disconnect (default) in Table 7-1. Disconnect and Go to Sleep 1. 2. 3. Remove charger emulation profile. Open port power switch. Enter the Sleep state. See the Disconnect and Go to Sleep entry in Table 7-1. Any time the charge rationing circuitry checks the pin conditions when changing rationing behavior or resetting charge rationing, if the external pin conditions have changed, then charger emulation is restarted (provided emulation is enabled via the pin states). If the pin conditions did not change, the UCS81003 returns to the previous power state as if the rationing threshold is not reached (for example, it does not discharge VBUS or restart emulation). DS20005334B-page 36  2014-2018 Microchip Technology Inc. UCS81003 TABLE 7-3: EFFECTS OF CHANGING RATIONING BEHAVIOR AFTER THRESHOLD REACHED Previous Behavior Report Report and Disconnect Disconnect and Go to Sleep Note 1: New Behavior Actions taken Ignore Release ALERT# pin. Report and Disconnect Open port power switch. See the Report and Disconnect (default) entry in Table 7-1. Disconnect and Go to Sleep 1. 2. 3. 4. Release the ALERT# pin. Remove charger emulation profile. Open the port power switch. Enter the Sleep state. See the Disconnect and Go to Sleep entry in Table 7-1. Ignore 1. 2. Release the ALERT# pin. Check the M1, M2, EM_EN, S0, and PWR_EN controls and enter the indicated power state if the controls changed (see Note 1). Report Check the M1, M2, EM_EN, S0, and PWR_EN controls and enter the indicated power state if the controls changed (see Note 1). Disconnect and Go to Sleep 1. 2. Ignore Check the M1, M2, EM_EN, S0, and PWR_EN controls and enter the indicated power state if the controls changed (see Note 1). Report 1. 2. Assert the ALERT# pin. Check the M1, M2, EM_EN, S0, and PWR_EN controls and enter the indicated power state if the controls changed (see Note 1). Report and Disconnect 1. 2. Assert the ALERT# pin. Check the M1, M2, EM_EN, S0, and PWR_EN controls to determine the power state, then enter that state except that the port power switch and bypass switch are not closed (see Note 1). Any time the charge rationing circuitry checks the pin conditions when changing rationing behavior or resetting charge rationing, if the external pin conditions have changed, then charger emulation is restarted (provided emulation is enabled via the pin states). If the pin conditions did not change, the UCS81003 returns to the previous power state as if the rationing threshold is not reached (for example, it does not discharge VBUS or restart emulation). If the RTN_EN control is set to ‘0’ prior to reaching the charge rationing threshold, rationing is disabled and the Total Accumulated Charge registers are cleared. If the RTN_EN control is set to ‘0’ after the charge rationing threshold is reached, the following are done: 1. 2. 3. Release the ALERT# pin. Enter the Sleep state. See the Disconnect and Go to Sleep entry in Table 7-1. RATION status bit is cleared. The ALERT# pin is released if asserted by the rationing circuitry and no other conditions are present. The M1, M2, EM_EN, S0 and PWR_EN controls are checked to determine the power state. See Note 1 in Table 7-3.  2014-2018 Microchip Technology Inc. Note: If the rationing behavior is set to “Report and Disconnect” when the charge rationing threshold is reached, and then the RTN_EN bit is cleared, the portable device may start charging sub-optimally because the charger emulation profile is removed. Toggle the PWR_EN control to restart charger emulation. Setting the RTN_RST control to ‘1’ automatically resets the Total Accumulated Charge registers to 00_00h. If this is done prior to reaching the charge rationing threshold, the data continues to be accumulated restarting from 00_00h. If this is done after the charge rationing threshold is reached, the UCS81003 takes action as shown in Table 7-2. DS20005334B-page 37 UCS81003 7.5 Fault Handling Mechanism 7.5.1 The UCS81003 has two modes for handling faults: AUTO-RECOVERY FAULT HANDLING When the LATCH control is low, Auto-Recovery Fault Handling is used. When an error condition is detected, the UCS81003 immediately enters the Error state and assert the ALERT# pin (see Section 5.1.5 “Error State Operation”). Independently from the host controller, the UCS81003 waits for a preset time (tCYCLE), checks error conditions (tTST) and restores Active operation if the error condition(s) no longer exist. If all other conditions that may cause the ALERT# pin to be asserted are removed, the ALERT# pin is released. • Latch (latch-upon-fault) • Auto-Recovery (automatically attempts to restore the Active power state after a fault occurs). If the SMBus is actively utilized, Auto-Recovery Fault Handling is the default error handler as determined by the LATCHS bit (see Section 10.4.3 “Switch Configuration Register”). Otherwise, the fault handling mechanism used depends on the state of the LATCH pin. Faults include overcurrent, overvoltage (on VS), undervoltage (on VBUS), back-voltage (VBUS to VS, or VBUS to VDD), discharge error, and maximum allowable internal die temperature (TTSD) exceeded (see Section 5.1.5 “Error State Operation”). tCYCLE VBUS tRST tCYCLE tRST VTEST tDISCHARGE SHORT applied. IBUS Short Detected. VBUS discharged. Enter Error state. FIGURE 7-1: 7.5.2 Wait tCYCLE. ITST ITST Check short condition. Short still present. Return to Error State. Check short condition. Short removed. Return to normal operation. Wait tCYCLE. Error Recovery Timing (Short Circuit Example). LATCHED FAULT HANDLING When the LATCH control is high, Latch Fault Handling is used. When an error condition is detected, the UCS81003 enters the Error power state and assert the ALERT# pin. Upon command from the host controller (by toggling the PWR_EN control from enabled to disabled or by clearing the ERR bit via SMBus), the UCS81003 checks error conditions once and restore Active operation if error conditions no longer exist. If an error condition still exists, the host controller is required to issue the command again to check error conditions. DS20005334B-page 38  2014-2018 Microchip Technology Inc. UCS81003 8.0 DETECT STATE 8.1 Device Attach/Removal Detection 8.4 The UCS81003 can detect the attachment and removal of a portable device on the USB port. Attach and Removal Detection does not perform any charger emulation or qualification of the device. The high-speed switch is OFF (by default) during the Detect power state. 8.2 The Removal Detection feature is active in the Active and Detect power states if S0 = ‘1’. This feature monitors the current load on the VBUS pin. If this load drops to less than IREM_QUAL_DET for longer than tREM_QUAL, a Removal Detection event is flagged. When this event occurs, the following are performed: 1. 2. VBUS Bypass Switch The UCS81003 contains circuitry to provide VBUS current as shown in Figure 8-1. In the Detect state, VDD is the voltage source, whereas in the Active state, VS is the voltage source. The bypass switch and the port power switch are both never ON at the same time. Removal Detection 3. 4. Disable the port power switch and the bypass switch. Deassert the A_DET# pin and set the REM status register bit. Enable an internal discharging device that discharges the VBUS line within tDISCHARGE. Once the VBUS pin is discharged, the device returns to the Detect state regardless of the PWR_EN control state. While the VBUS bypass switch is active, the current available to a portable device is limited to IBUS_BYP, and the Attach Detection feature is active. Bypass Switch VDD VS VBUS VS VBUS Port Power Switch VS FIGURE 8-1: 8.3 VBUS Detect State VBUS Biasing. Attach Detection The primary Attach Detection feature is only active in the Detect power state. When active, this feature constantly monitors the current load on the VBUS pin. If the current drawn by a portable device is greater than IDET_QUAL for longer than tDET_QUAL, an Attach Detection event occurs. This causes the A_DET# pin to assert low and the ADET_PIN and ATT status bits to be set. Until the port power switch is enabled, the current available to a portable device is limited to that used to detect device attachment (IDET_QUAL). Once an Attach Detection event occurs, the UCS81003 waits for the PWR_EN control to be enabled. When PWR_EN is enabled and VS is above the threshold, the UCS81003 activates the USB port power switch and operates in the selected Active mode (see Section 9.0 “Active State”).  2014-2018 Microchip Technology Inc. DS20005334B-page 39 UCS81003 9.0 ACTIVE STATE 9.1 Active State Overview The UCS81003 has the following modes of operation in the Active state: Data Pass-Through, BC1.2 DCP, BC1.2 SDP, BC1.2 CDP, and Dedicated Charger Emulation Cycle. The current limiting mode depends on the Active mode behavior (see Table 9-2). 9.2 Note 1: If it is desired that the Data Pass-Through mode operates as a traditional/standard port power switch, the S0 control must be set to ‘0’ to enable the port power switch to be closed without requiring an Attach Detection event. When entering this mode, there is no automatic VBUS discharge. 2: When the M1, M2, and EM_EN controls are set to ‘0’, ‘1’, ‘0’ or to ‘1’, ‘1’, ‘0’ respectively, Data Pass-Through mode persists if the PWR_EN control is disabled; however, the UCS81003 draws more current. To leave the Data PassThrough mode, the PWR_EN control must be enabled before the M1, M2 and EM_EN controls are changed to the desired mode. Active Mode Selection The Active mode selection is controlled by three controls: EM_EN, M1, and M2 as shown in Table 9-1. TABLE 9-1: ACTIVE MODE SELECTION M1 M2 EM_EN 0 0 1 Dedicated Charger Emulation Cycle 0 1 0 Data Pass-Through 0 1 1 BC1.2 DCP 1 0 0 BC1.2 SDP – Note 1 1 0 1 Dedicated Charger Emulation Cycle 1 1 0 Data Pass-Through 1 1 1 BC1.2 CDP Note 1: 9.3 Active mode BC1.2 SDP behaves the same as the Data Pass-Through mode with the exception that it is preceded by a VBUS discharge when the mode is entered per the BC1.2 specification. Data Pass-Through (No Charger Emulation) When commanded to Data Pass-Through mode, UCS81003 closes its USB high-speed data switch to enable USB communications between a portable device and host controller and operates using Trip Current Limiting. No charger emulation profiles are applied in this mode. Data Pass-Through mode persists until commanded otherwise by the M1, M2, and EM_EN controls. DS20005334B-page 40 BC1.2 SDP (No Charger Emulation) When commanded to BC1.2 SDP mode, UCS81003 discharges VBUS, closes its USB high-speed data switch to enable USB communications between a portable device and host controller, and operates using Trip Current Limiting. No charger emulation profiles are applied in this mode. BC1.2 SDP mode persists until commanded otherwise by the M1, M2, EM_EN, and PWR_EN controls. Note: BC1.2 Detection Renegotiation The BC1.2 specification enables a charger to act as an SDP, CDP or DCP and to change between these roles. To force an attached portable device to repeat the charging detection procedure, VBUS must be cycled. In compliance with this specification, the UCS81003 automatically cycles VBUS when switching between the BC1.2 SDP, BC1.2 DCP, and BC1.2 CDP modes. 9.4 9.5 9.6 If it is desired that the BC1.2 SDP mode operates as a traditional/standard port power switch, the S0 control must be set to ‘0’ to enable the port power switch to be closed without requiring an Attach Detection event. BC1.2 CDP When BC1.2 CDP is selected as the Active mode, UCS81003 discharges VBUS, closes its USB high-speed data switch (by default), and applies the BC1.2 CDP charger emulation profile which performs handshaking per the specification. The combination of the UCS81003 CDP handshake along with a standard USB host comprises a Charging Downstream Port. In BC1.2 CDP mode, there is no emulation timeout. If the handshake is successful, the UCS81003 operates using Constant Current Limiting (variable slope). If the handshake is not successful, the UCS81003 leaves the applied CDP profile in place, leaves the high-speed switch closed, enables Constant Current Limiting, and persists in this condition until commanded otherwise by the M1, M2, EM_EN, and PWR_EN controls.  2014-2018 Microchip Technology Inc. UCS81003 The UCS81003 responds per the BC1.2 specification to the portable device initiated charger renegotiation requests. Note 1: BC1.2 compliance testing may require the S0 control to be set to ‘0’ (Attach and Removal Detection feature disabled) while testing is in progress. 2: When the UCS81003 is in BC1.2 CDP mode and the Attach and Removal Detection feature is enabled, if a power thief (such as a USB light or fan) attaches but does not assert DP pin, a Removal event does not occur when the portable device is removed. However, if a standard USB device is subsequently attached, Removal Detection is fully functional again. Additionally, if PWR_EN is cycled or M1, M2 and/or EM_EN change state, a Removal event occurs and Attach Detection is reactivated. 9.6.1 1. 2. 3. 4. 9.7 Note: 9.7.1 1. 2. 3. All CDP handshaking is performed with the high-speed switch closed. VBUS voltage is applied. Primary Detection – when the portable device drives a voltage between 0.4V and 0.8V onto the DPOUT pin, the UCS81003 drives 0.6V onto the DMOUT pin within 20 ms. When the portable device drives the DPOUT pin back to ‘0’, the UCS81003 then drives the DMOUT pin back to ‘0’ within 20 ms. Optional Secondary Detection – If the portable device then drives a voltage of 0.6V (nominal) onto the DMOUT pin, the UCS81003 takes no other action. This causes the portable device to observe a ‘0’ on the DPOUT pin and detects the connection to a CDP. BC1.2 DCP When BC1.2 DCP is selected as the Active mode, UCS81003 discharges VBUS and applies the BC1.2 DCP charger emulation profile per the specification. In BC1.2 DCP mode, the emulation timeout and requirement for portable device current draw are automatically disabled. When the BC1.2 DCP charger emulation profile is applied within the Dedicated Charger Emulation Cycle (see Section 9.11.3 “Legacy 3 Charger Emulation Profile”), the timeout and current draw requirement are enabled.  2014-2018 Microchip Technology Inc. BC1.2 compliance testing may require the S0 control to be set to ‘0’ (Attach and Removal Detection feature disabled) while testing is in progress. BC1.2 DCP CHARGER EMULATION PROFILE The BC1.2 DCP charger emulation profile is described as follows: BC1.2 CDP CHARGER EMULATION PROFILE The BC1.2 CDP charger emulation profile acts in a reactionary manner based on stimulus from the portable device as described below and shown in Figure 2-1. Note: If the portable device is charging after the DCP charger emulation profile is applied, the UCS81003 leaves the resistive short in place, leaves the highspeed switch open and enables Constant Current Limiting (variable slope). 9.8 VBUS voltage is applied. A resistor (RDCP_RES) is connected between the DPOUT and DMOUT pins. Primary Detection – if the portable device drives 0.6V (nominal) onto the DPOUT pin, the UCS81003 takes no other action than to leave the resistor connected between DPOUT and DMOUT. This causes the portable device to see 0.6V (nominal) on the DMOUT pin and know that it is connected to a DCP. Optional Secondary Detection – If the portable device drives 0.6V (nominal) onto the DMOUT pin, the UCS81003 takes no other action than to leave the resistor connected between DPOUT and DMOUT. This causes the portable device to see 0.6V (nominal) on the DPOUT pin and know that it is connected to a DCP. Dedicated Charger When commanded to Dedicated Charger Emulation cycle mode, the UCS81003 enables an attached portable device to enter its charging mode by applying specific charger emulation profiles in a predefined sequence. Using these profiles, the UCS81003 is capable of generating and recognizing several signal levels on the DPOUT and DMOUT pins. The preloaded charger emulation profiles include ones compatible with YD/T-1591 (2009), 12W charging, Samsung and many RIM portable devices. Other levels, sequences and protocols are configurable via the SMBus/I2C. When a charger emulation profile is applied, a programmable timer for the emulation profile is started. When emulation timeout occurs, the UCS81003 checks the IBUS current against a programmable threshold. If the current is above the threshold, the charger emulation profile is accepted and the associated current limiting mode is applied. No active USB data communication is possible when charging in this mode (by default – see Section 10.4.5 “HighSpeed Switch Configuration Register”). DS20005334B-page 41 UCS81003 9.8.1 EMULATION RESET The UCS81003 applies a charger emulation profile until one of the following exit conditions occurs: Prior to applying any of the charger emulation profiles, the UCS81003 performs an Emulation Reset. This means that the UCS81003 resets the VBUS line by disconnecting the port power switch and connecting VBUS to ground via an internal 100 resistor for tDISCHARGE time. The port power switch is held open for a time equal to tEM_RESET at which point the port power switch is closed and the VBUS voltage is applied. The DPOUT and DMOUT pins are pulled low using internal 15 k pull-down resistors. Note: 9.8.2 • Current greater than IBUS_CHG is detected flowing out of VBUS at the respective emulation timeout time. In this case, the profile is assumed to be accepted and no other profiles is applied. • The respective emulation timeout (tEM_TIMEOUT) time is reached without current that exceeds the IBUS_CHG limit flowing out of VBUS (the emulation timeout is enabled by default, see Section 10.4.2 “Emulation Configuration Register” and Register 10-35). The profile is assumed to be rejected, and the UCS81003 performs the Emulation Reset and applies the next profile, if any. To help prevent possible damage to a portable device, the DPOUT and DMOUT pins have current limiting in place when the emulation profiles are applied. Emulation timeouts can be programmed for each charger emulation profile (see Section 10.11 “Preloaded Emulation Timeout Configuration Registers” and Register 10-35). EMULATION CYCLING In Dedicated Charger Emulation Cycle mode, the charger emulation profiles, if enabled, are applied in the following order: 1. 2. 3. 4. 5. 6. 7. 8. 9.8.3 Legacy 1 Legacy 2 Legacy 3 Legacy 4 Legacy 5 Legacy 6 Legacy 7 Custom (disabled by default). If the CS_FRST configuration bit is set, then the Custom charger emulation profile is tested first and the order proceeds as given. If none of the charger emulation profiles cause a charge current to be drawn, the UCS81003 performs the Emulation Reset and cycles through the profiles again if the EM_RETRY bit is set (default – see Section 10.4.2 “Emulation Configuration Register”). The UCS81003 continues to cycle through the profiles as long as charging current is not drawn and the PWR_EN control is enabled. If the Emulation Retry is not enabled, the UCS81003 flags “No Handshake” and end the DCE Cycle using Trip Current Limiting. 9.9 If S0 = ’0’ and a portable device is not attached in DCE Cycle mode, the UCS81003 is cycling through charger emulation profiles (by default). There is no guarantee which charger emulation profile is applied first when a portable device is attached. TABLE 9-2: DCE CYCLE RETRY Current Limit Mode Associations The UCS81003 closes the port power switch and use the Current Limiting mode as shown in Table 9-2. CURRENT LIMIT MODE OPTIONS Active Mode Current Limit Mode (See Section 10.14 “Current Limiting Behavior Configuration Registers”) Data Pass-Through Trip mode BC1.2 SDP Trip mode BC1.2 CDP CC mode if ILIM < 1.68A, otherwise, Trip mode BC1.2 DCP CC mode if ILIM < 1.68A, otherwise, Trip mode DCE Cycle During DCE Cycle when a charger emulation profile is CC mode if ILIM < 1.68A, otherwise, Trip mode being applied and the emulation timeout is active Note 1: As noted in the last three rows in Table 9-2, under those specific conditions with ILIM < 1.68A, it is the relationship of ILIM and IBUS_R2MIN that determines the current limiting mode. In these cases, the value of IBUS_R2MIN is determined by CS_R2_IMIN bits 4-2 in the Custom Current Limiting Behavior Configuration register – 51h (Register 10-49). DS20005334B-page 42  2014-2018 Microchip Technology Inc. UCS81003 TABLE 9-2: CURRENT LIMIT MODE OPTIONS (CONTINUED) Active Mode Current Limit Mode (See Section 10.14 “Current Limiting Behavior Configuration Registers”) Legacy 3 charger emulation profile accepted or the emulation timeout is disabled CC mode if ILIM < 1.68A, otherwise, Trip mode Legacy 1, Legacy 2 or Legacy 4 – Legacy 7 charger emulation profile accepted or the emulation timeout is disabled Trip mode if IBUS_R2MIN < ILIM or ILIM > 1.68A (normal operation), otherwise, CC mode (see Register 10-49) Custom charger emulation profile accepted or the emulation timeout is disabled Trip mode if IBUS_R2MIN < ILIM or ILIM > 1.68A (normal operation), otherwise, CC mode (see Register 10-49) No handshake (DCE Cycle with Emulation Retry not enabled) Trip mode if IBUS_R2MIN < ILIM or ILIM > 1.68A (normal operation), otherwise, CC mode (see Register 10-49) Note 1: 9.10 As noted in the last three rows in Table 9-2, under those specific conditions with ILIM < 1.68A, it is the relationship of ILIM and IBUS_R2MIN that determines the current limiting mode. In these cases, the value of IBUS_R2MIN is determined by CS_R2_IMIN bits 4-2 in the Custom Current Limiting Behavior Configuration register – 51h (Register 10-49). No Handshake 3. In DCE Cycle mode with emulation retry disabled, a “No Handshake” condition is flagged. The NO_HS status bit stays set (see Register 10-5) when the end of the DCE Cycle is reached without a handshake and without drawing current. All signatures/handshaking placed on the DPOUT and DMOUT pins are removed. The UCS81003 operates with the high-speed switch opened or closed as determined by the high-speed switch configuration, and uses Trip or Constant Current Limiting as setting determined by the IBUS_R2MIN (CS_R2_IMIN bits 4-2 in the Custom Current Limiting Behavior Configuration register 51h). 4. The portable devices that can cause this are generally the ones that pull up DPOUT to some voltage and leave it there, or apply the wrong voltage. 9.11 Preloaded Charger Emulation Profiles The following charger emulation profiles are resident to the UCS81003: • • • • • • Legacy 1 Charger Emulation Profile Legacy 2, 4, 5, and 7 Charger Emulation Profiles Legacy 3 Charger Emulation Profile Legacy 6 Charger Emulation Profile BC1.2 CDP Charger Emulation Profile BC1.2 DCP Charger Emulation Profile 9.11.1 LEGACY 1 CHARGER EMULATION PROFILE 9.11.2 2. The UCS81003 applies 900 mV to both the DPOUT and the DMOUT pins. VBUS voltage is applied.  2014-2018 Microchip Technology Inc. LEGACY 2, 4, 5, AND 7 CHARGER EMULATION PROFILES Legacy 2, 4, 5, and 7 Charger Emulation Profiles follow the same pattern of operation, although the voltage that is applied on the DPOUT and DMOUT pins varies. The profiles do the following: 1. 2. Legacy 1 Charger Emulation Profile does the following: 1. If the portable device draws more than IBUS_CHG current when the tEM_TIMEOUT timer expires, the UCS81003 accepts that the currently applied profile is the correct charger emulation profile for the attached portable device. Charging commences. The voltages applied to the DPOUT and DMOUT pins remains in place (unless EM_RESP is set to 0b). The UCS81003 begins to operate in Trip mode or CC mode as determined by the IBUS_R2MIN setting (see Section 10.14 “Current Limiting Behavior Configuration Registers”). If the portable device does not draw more than IBUS_CHG current when tEM_TIMEOUT timer expires, the UCS81003 stops the currently applied charger emulation profile. This causes all voltages put onto the DPOUT and DMOUT pins to be removed. Emulation Reset occurs, and the UCS81003 initiates the next charger emulation profile. 3. The UCS81003 applies a voltage on the DPOUT pin using either a current-limited voltage source or a voltage divider between VBUS and ground with the center tap on the DPOUT pin. The UCS81003 applies a possibly different voltage on the DMOUT pin, using either a current-limited voltage source or a voltage divider between VBUS and ground, with the center tap on the DMOUT pin. VBUS voltage is applied. DS20005334B-page 43 UCS81003 4. 5. If the portable device draws more than IBUS_CHG current when the tEM_TIMEOUT timer expires, the UCS81003 accepts that the currently applied profile is the correct charger emulation profile for the attached portable device. Charging commences. The voltages applied to the DPOUT and DMOUT pins remain in place (unless EM_RESP is set to 0b). The UCS81003 begins operating in Trip mode or CC mode as determined by the IBUS_R2MIN setting (see Section 10.14 “Current Limiting Behavior Configuration Registers”). If the portable device does not draw more than IBUS_CHG current when tEM_TIMEOUT timer expires, the UCS81003 stops the currently applied charger emulation profile. This causes all voltages put onto the DPOUT and DMOUT pins to be removed. Emulation Reset occurs, and the UCS81003 initiates the next charger emulation profile. Additionally, the user may build a charger emulation profile by determining the voltage and resistance characteristics that are placed on each of the DPOUT and DMOUT pins. See Section 9.12 “Custom Charger Emulation Profile”. 9.11.3 LEGACY 3 CHARGER EMULATION PROFILE The Legacy 3 Charger Emulation Profile does the following: 1. 2. 3. 4. The UCS81003 connects a resistor (RDCP_RES) between DPOUT and DMOUT. VBUS is applied. If the portable device draws more than IBUS_CHG current when the tEM_TIMEOUT timer expires (enabled by default), the UCS81003 accepts that this is the correct charger emulation profile for the attached portable device. Charging commences. The resistive short between the DPOUT and DMOUT pins is left in place. If the portable device does not draw more than IBUS_CHG current when tEM_TIMEOUT timer expires, the UCS81003 stops the Legacy 3 Charger Emulation. This causes resistive short between the DPOUT and DMOUT pins to be removed. Emulation Reset occurs, and the UCS81003 initiates the next charger emulation profile. DS20005334B-page 44 9.11.4 LEGACY 6 CHARGER EMULATION PROFILE The Legacy 6 Charger Emulation Profile does the following: 1. 2. 3. 4. The UCS81003 applies a voltage on the DPOUT pin using a voltage divider between VBUS and ground with the center tap on the DPOUT pin. VBUS voltage is applied. If the portable device draws more than IBUS_CHG current when the tEM_TIMEOUT timer expires, the UCS81003 accepts that Legacy 6 is the correct charger emulation profile for the attached portable device. Charging commences. The voltage applied to the DPOUT pin remains in place (unless EM_RESP is set to 0b). The UCS81003 begins operating in Trip mode or CC mode as determined by the IBUS_R2MIN setting (see Section 10.14 “Current Limiting Behavior Configuration Registers”). If the portable device does not draw more than IBUS_CHG current when tEM_TIMEOUT timer expires, the UCS81003 stops the Legacy 6 Charger Emulation Profile. This causes the voltage put onto the DPOUT pin to be removed. Emulation Reset occurs, and the UCS81003 initiates the next charger emulation profile. 9.12 Custom Charger Emulation Profile The UCS81003 enables the user to create a Custom Charger emulation profile to handshake as any type of charger. This profile can be included in the DCE Cycle. In addition, it can be placed first or last in the profile sequence in the DCE Cycle. See Register 10-35. The Custom charger emulation profile uses a number of registers to define stimuli and behaviors. The Custom Charger emulation profile uses three separate stimulus/response pairs that are detected and applied in sequence, enabling flexibility to build any of the preloaded emulation profiles, or tailor the profile to match a specific charger application. For details, see Application Note 24.14 – “UCS1002 Fundamentals of Custom Charger Emulation”.  2014-2018 Microchip Technology Inc. UCS81003 10.0 REGISTER DESCRIPTION The registers shown in Table 10-1 are accessible through the SMBus or I2C. While in the Sleep state, the UCS81003 retains configuration and charge rationing data as indicated in the text. If a register does not indicate that data is retained in the Sleep power state, this information is lost when the UCS81003 enters the Sleep power state. TABLE 10-1: Register Address REGISTER SET IN HEXADECIMAL ORDER Register Name R/W Function Default Value Page No. 00h Current Measurement R Stores the current measurement 00h 47 01h Total Accumulated Charge High Byte R Stores the total accumulated charge delivered high byte 00h 48 02h Total Accumulated Charge Middle High Byte R Stores the total accumulated charge delivered middle high byte 00h 48 03h Total Accumulated Charge Middle Low Byte R Stores the total accumulated charge delivered middle low byte 00h 48 04h Total Accumulated Charge Low Byte R Stores the total accumulated charge delivered low byte 00h 48 0Fh Other Status R Indicates emulation status as well as the ALERT# and A_DET# pin status 00h 49 10h Interrupt Status 00h 50 11h General Status R/R-C Indicates general status 00h 51 12h Profile Status 1 R Indicates which charger emulation profile is accepted 00h 52 See Indicates why ALERT# pin asserted Register 10-3 13h Profile Status 2 R 14h Pin Status R 00h 53 Indicates the pin states of the internal control pins 00h 54 15h General Configuration R/W Controls basic functionality 01h 55 16h Emulation Configuration 17h Switch Configuration R/W Controls emulation functionality 8Ch 56 R/W Controls advanced switch functions 04h 57 18h Attach Detect Configuration R/W Controls Attach Detect functionality 46h 58 19h Current Limit R/W Controls the maximum current limit 00h 60 1Ah Charge Rationing Threshold High Byte R/W Controls the Current Threshold ITHRESH used by the charge rationing circuitry FFh 60 1Bh Charge Rationing Threshold Low Byte R/W Controls the Current Threshold ITHRESH used by the charge rationing circuitry FFh 60 1Ch Auto-Recovery Configuration R/W Controls the Auto-Recovery functionality 2Ah 61 1Eh IBUS_CHG Configuration R/W Stores the limit for IBUS_CHG used to determine if emulation is successful 0Fh 62 1Fh tDET_CHARGE Configuration R/W Stores bits that define the tDET_CHARGE time 03h 63 20h BCS Emulation Enable R/W Enables BCS charger emulation profiles 16h 63 21h Legacy Emulation Enable R/W Enables Legacy charger emulation profiles 00h 64 22h BCS Emulation Timeout Config R/W Controls timeout for each BCS charger emulation profile 10h 65  2014-2018 Microchip Technology Inc. DS20005334B-page 45 UCS81003 TABLE 10-1: Register Address REGISTER SET IN HEXADECIMAL ORDER (CONTINUED) Register Name R/W Function Default Value Page No. 23h Legacy Emulation Timeout Config 1 R/W Controls timeout for Legacy charger emulation profiles 1 – 4 6Ch 65 24h Legacy Emulation Timeout Config 2 R/W Controls timeout for Legacy charger emulation profiles 5 – 7 01h 66 25h High-Speed Switch Configuration R/W Controls when the high-speed switch is enabled 14h 59 30h Applied Charger Emulation R Indicates which charger emulation profile is being applied 00h 67 31h Preloaded Emulation Stimulus 1 – Config 1 R Indicates the stimulus and timing for Stimulus 1 00h 67 32h Preloaded Emulation Stimulus 1 – Config 2 R Indicates the response and magnitude for Stimulus 1 26h 68 33h Preloaded Emulation Stimulus 1 – Config 3 R Indicates the threshold and pull-up/pull-down settings for Stimulus 1 00h 69 34h Preloaded Emulation Stimulus 1 – Config 4 R Indicates the resistor ratio for Stimulus 1 02h 70 35h Preloaded Emulation Stimulus 2 – Config 1 R Indicates the stimulus and timing for Stimulus 2 00h 71 36h Preloaded Emulation Stimulus 2 – Config 2 R Indicates the response and magnitude for Stimulus 2 09h 72 37h Preloaded Emulation Stimulus 2 – Config 3 R Indicates the threshold and pull-up/ pull-down settings for Stimulus 2 00h 73 38h Preloaded Emulation Stimulus 2 – Config 4 R Indicates the resistor ratio for Stimulus 2 04h 74 39h Preloaded Emulation Stimulus 3 – Config 1 R Indicates the stimulus and timing for Stimulus 3 (CDP only) 00h 75 3Ah Preloaded Emulation Stimulus 3 – Config 2 R Indicates the response and magnitude for Stimulus 3 (CDP only) 00h 76 3Bh Preloaded Emulation Stimulus 3 – Config 3 R Indicates the threshold and pull-up/ pull-down settings for Stimulus 3 (CDP only) 00h 77 40h Custom Emulation Config R/W Controls general configuration of the Custom charger emulation profile 01h 79 41h Custom Stimulus/Response Pair 1 – Config 1 R/W Sets the stimulus and timing for Stimulus 1 00h 80 42h Custom Stimulus/Response Pair 1 – Config 2 R/W Sets the response and magnitude for Stimulus 1 00h 81 43h Custom Stimulus/Response Pair 1 – Config 3 R/W Sets the threshold and pull-up/pull-down settings for Stimulus 1 00h 82 44h Custom Stimulus/Response Pair 1 – Config 4 R/W Sets the resistor ratio for Stimulus 1 00h 83 45h Custom Stimulus/Response Pair 2 – Config 1 R/W Sets the stimulus and timing for Stimulus 2 00h 84 46h Custom Stimulus/Response Pair 2 – Config 2 R/W Sets the response and magnitude for Stimulus 2 00h 85 47h Custom Stimulus/Response Pair 2 – Config 3 R/W Sets the threshold and pull-up/pull-down settings for Stimulus 2 00h 86 48h Custom Stimulus/Response Pair 2 – Config 4 R/W Sets the resistor ratio for Stimulus 2 00h 87 DS20005334B-page 46  2014-2018 Microchip Technology Inc. UCS81003 TABLE 10-1: Register Address REGISTER SET IN HEXADECIMAL ORDER (CONTINUED) Default Value Page No. Sets the stimulus and timing for Stimulus 3 00h 88 R/W Sets the response and magnitude for Stimulus 3 00h 89 Custom Stimulus/Response Pair 3 – Config 3 R/W Sets the threshold and pull-up/pull-down settings for Stimulus 3 00h 90 4Ch Custom Stimulus/Response Pair 3 – Config 4 R/W Sets the resistor ratio for Stimulus 3 00h 91 50h Applied Current Limiting Behavior R Indicates the applied current limiting behavior 82h 92 51h Custom Current Limiting Behavior Config R/W Controls the custom current limiting behavior 82h 93 FDh Product ID R Stores a fixed value that identifies each product 4Eh 94 FEh Manufacturer ID R Stores a fixed value that identifies Microchip 5Dh 94 FFh Revision R Stores a fixed value that represents the revision number 82h 94 Register Name R/W 49h Custom Emulation Stimulus 3 – Config 1 R/W 4Ah Custom Stimulus/Response Pair 3 – Config 2 4Bh During Power-On Reset (POR), the default values are stored in the registers. A POR is initiated when power is first applied to the part and the voltage on the VDD supply surpasses the VDD_TH level as specified in the electrical characteristics. Any reads to undefined registers returns 00h. Writes to undefined registers do not have an effect. When a bit is set, this means that the user writes a logic ‘1’ to it. When a bit is cleared, this means that the user writes a logic ‘0’ to it. 10.1 Current Measurement Register (Address 00h) Name Current Measurement Bits Address Cof Default 8 00h R 00h The Current Measurement register stores the measured current value delivered to the portable device (IBUS). This value is updated continuously while the device is in the Active power state. The bit weights are in mA and the range is from 0 mA to 2988.6A (the maximum value corresponds to 255 LSB, where 1 LSB = 11.72 mA). This data is cleared when the device enters the Sleep or Detect states. This data is also cleared whenever the port power switch is turned OFF (including during emulation or any time that VBUS is discharged).  2014-2018 Microchip Technology Inc. Function 10.2 Total Accumulated Charge Registers Name Bits Address Cof Default Total Accumulated Charge High Byte 8 01h R 00h Total Accumulated Charge Middle High 8 02h R 00h Total Accumulated Charge Middle Low Byte 8 03h R 00h Total Accumulated Charge Low Byte 8 04h R 00h The Total Accumulated Charge registers store the total accumulated charge delivered from the VS source to a portable device. The bit weighting of the registers is given in mAh. The register value is reset to 00_00h only when the RTN_RST bit is set or if the RTN_EN bit is cleared. This value is retained when the device transitions out of the Active state and resumes accumulation if the device returns to the Active state and charge rationing is still enabled. These registers are updated every one (1) second while the UCS81003 is in the Active power state. Whenever the value is updated, it is compared against the target value in the Charge Rationing Threshold registers (see Section 10.6 “Charge Rationing Threshold Registers”). DS20005334B-page 47 UCS81003 REGISTER 10-1: TOTAL ACCUMULATED CHARGE REGISTER (ADDRESSES 01H – 04H) R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 ACC ACC ACC ACC ACC ACC ACC ACC bit 31 bit 24 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 ACC ACC ACC ACC ACC ACC ACC ACC bit 23 bit 16 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 ACC ACC ACC ACC ACC ACC ACC ACC bit 15 bit 8 R-0 R-0 R-x R-x R-x R-x R-x R-x ACC ACC — — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 31-6 ACC: Total Accumulated Charge 1 LSB = 0.00325 mAh bit 5-0 Unimplemented 10.3 x = Bit is unknown Status Registers Bits Address Cof Default Other Status Name 8 0Fh R 00h Interrupt Status 8 10h R/W 00h General Status 8 11h R/R-C 00h Profile Status 1 8 12h R 00h Profile Status 2 8 13h R 00h Pin Status 8 14h R 00h The Status registers store bits that indicate error conditions as well as Attach Detection and Removal Detection. Unless otherwise noted, these bits operate as described when the UCS81003 is operating in Stand-Alone mode. DS20005334B-page 48  2014-2018 Microchip Technology Inc. UCS81003 REGISTER 10-2: OTHER STATUS REGISTER (ADDRESS 0FH) U-x U-x R-0 R-0 R-0 R-0 — — ALERT_PIN ADET_PIN CHG_ACT EM_ACT R-0 R-0 EM_STEP bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-6 Unimplemented bit 5 ALERT_PIN: Reflects the status of the ALERT# pin. This bit is set and cleared as the ALERT# pin changes states. 1 = ALERT# pin is asserted low 0 = ALERT# pin is released bit 4 ADET_PIN: Reflects the status of the A_DET# pin. When set, indicates that the A_DET# pin is asserted low. This bit is set and cleared as the A_DET# pin changes states. (Note 1) 1 = A_DET# pin is asserted low 0 = A_DET# pin is released bit 3 CHG_ACT: This bit is automatically set when IBUS > IBUS_CHG and cleared when IBUS < IBUS_CHG. (Note 2) 1 = IBUS > IBUS_CHG 0 = IBUS < IBUS_CHG bit 2 EM_ACT: Indicates that the UCS81003 is in the Active state and emulating. The actual profile that is being applied is identified by PRE_EM_SEL (see Section 10.12.1 “Applied Charger Emulation Register”). This bit is set and automatically cleared. (Note 3) 1 = Device is in Active state and emulating 0 = Device is not emulating bit 1-0 EM_STEP: Indicates which stimulus/response pair is currently being applied by the charger emulation profile as shown below. These bits are set and automatically cleared. Note that the Legacy charger emulation profiles and the BC1.2 DCP charger emulation profile do not use Stimulus/Response Pair #3. 00 = None Applied. Waiting for current. 01 = Stimulus/Response #1 10 = Stimulus/Response #2 00 = Stimulus/Response #3 if applicable Note 1: 2: 3: If S0 is '1', PWR_EN is enabled, and VS is not present, the ADET_PIN bit cycles if the current draw exceeds the current capacity of the bypass switch. The CHG_ACT bit does not indicate that a portable device has accepted one of the charger emulation profiles. This bit cycles during the Dedicated Charger Emulation Cycle. The EM_ACT bit does not indicate that a portable device has accepted one of the emulation profiles. This bit cycles during the Dedicated Charger Emulation Cycle.  2014-2018 Microchip Technology Inc. DS20005334B-page 49 UCS81003 REGISTER 10-3: INTERRUPT STATUS REGISTER (ADDRESS 10H) R/W-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 ERR DISCH_ERR RESET KEEP_OUT TSD OV_VOLT BACK_V OV_LIM bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 ERR: Indicates that an error is detected and the device has entered the Error state. Writing this bit to a ‘0’ clears the Error state and enables the device to return to the Active state. When written to ‘0’, all error conditions are checked. If all error conditions are removed, the UCS81003 returns to the Active state. This bit is automatically set by the UCS81003 when the Error state is entered. Regardless of the fault handling mechanism used, if any other bit is set in the Interrupt Status register (10h), the device does not leave the Error state. (Note 1 and Note 2) This bit is automatically cleared by the UCS81003 if the Auto-Recovery Fault Handling functionality is active and no error conditions are detected. Likewise, this bit is cleared when the PWR_EN control is disabled. 1 = One or more errors are detected, and the UCS81003 has entered the Error state. 0 = There are no errors detected. bit 6 DISCH_ERR: Indicates that the UCS81003 is unable to discharge the VBUS node. This bit is cleared when read if the error condition is removed or if the ERR bit is cleared. This bit causes the ALERT# pin to be asserted and the device to enter the Error state. 1 = UCS81003 is unable to discharge the VBUS node. 0 = No VBUS discharge error. bit 5 RESET: Indicates that the UCS81003 is on reset and must be reprogrammed. This bit is set at powerup. This bit is cleared when read or when the PWR_EN control is toggled. The ALERT# pin is not asserted when this bit is set. This data is retained in the Sleep state. 1 = UCS81003 is on reset. 0 = Reset did not occur. bit 4 KEEP_OUT: Indicates that the V-I output on the VBUS pins has dropped below VBUS_MIN. This bit is cleared when read if the error condition is removed or if the ERR bit is cleared. This bit causes the ALERT# pin to be asserted and the device to enter the Error state. 1 = VBUS < VBUS_MIN 0 = VBUS > VBUS_MIN bit 3 TSD: Indicates that the internal temperature has exceeded TTSD threshold and the device has entered the Error state. This bit is cleared when read if the error condition is removed or if the ERR bit is cleared. This bit causes the ALERT# pin to be asserted and the device to enter the Error state. 1 = Internal temperature > TTSD 0 = Internal temperature < TTSD bit 2 OV_VOLT: Indicates that the VS voltage has exceeded the VS_OV threshold and the device has entered the Error state. This bit is cleared when read, if the error condition is removed or if the ERR bit is cleared. This bit causes the ALERT# pin to be asserted and the device to enter the Error state. 1 = VS > VS_OV 0 = VS < VS_OV bit 1 BACK_V: Indicates that the VBUS voltage has exceeded the VS or VDD voltages by more than 150 mV. This bit is cleared when read if the error condition is removed or if the ERR bit is cleared. This bit causes the ALERT# pin to be asserted and the device to enter the Error state. 1 = VBUS > VS, or VBUS > VDD by more than 150 mV 0 = VBUS voltage did not exceed the VS and VDD voltages by more than 150 mV DS20005334B-page 50  2014-2018 Microchip Technology Inc. UCS81003 REGISTER 10-3: bit 0 INTERRUPT STATUS REGISTER (ADDRESS 10H) (CONTINUED) OV_LIM: Indicates that the IBUS current has exceeded both the ILIM threshold and the IBUS_R2MIN threshold settings. This bit is cleared when read if the error condition is removed or if the ERR bit is cleared. This bit causes the ALERT# pin to be asserted and the device to enter the Error state. 1 = IBUS > ILIM and IBUS_R2MIN 0 = IBUS did not exceed both ILIM threshold and the IBUS_R2MIN threshold settings Note 1: 2: If the Auto-Recovery Fault Handling is not used, the ERR bit must be written to a logic '0' to be cleared. It is also cleared when the PWR_EN control is disabled. Note that the ERR bit does not necessarily reflect the ALERT# pin status. The ALERT# pin may be cleared or asserted without the ERR bit changing states. REGISTER 10-4: GENERAL STATUS REGISTER (ADDRESS 11H) R-0 U-x U-x R-0 R-0 R-C R-C R-C RATION — — CC_MODE TREG LOW_CUR REM ATT bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown C = Clear on Read bit 7 bit 6-5 RATION: Indicates that the UCS81003 has delivered the programmed amount of power to a portable device. If the RATION_BEH bits are set to interrupt the host, this bit causes the ALERT# pin to be asserted. This bit is cleared when read. This bit is also automatically cleared when the RTN_RST bit is set or the RTN_EN bit is cleared (see Section 10.4.1 “General Configuration Register”). 1 = UCS81003 delivered the programmed amount of power to a portable device 0 = UCS81003 did not deliver the programmed amount of power to a portable device Unimplemented bit 4 CC_MODE: Indicates that the IBUS current has exceeded ILIM. Current is in Region 2 (IBUS_R2MIN). 1 = IBUS > ILIM 0 = IBUS < ILIM bit 3 TREG: Indicates that the internal temperature has exceeded TREG and that the current limit is reduced. This bit is cleared when read and does not cause the ALERT# pin to be asserted, unless the ALERT_LINK bit is set. 1 = Internal temperature > TREG 0 = Internal temperature < TREG bit 2 LOW_CUR: Indicates that a portable device has reduced its charge current to below ~6.4 mA and may be finished charging. This bit is cleared when read and does not cause the ALERT# pin to be asserted, unless the ALERT_LINK bit is set. 1 = IBUS < 6.4 mA 0 = IBUS > 6.4 mA bit 1 REM: Indicates that a Removal Detection event has occurred and there is no longer a portable device present. This bit is cleared when read and does not cause the ALERT# pin to be asserted. It causes the A_DET# pin to be released. 1 = Removal Detected 0 = No Removal Detected bit 0 ATT: Indicates that an Attach Detection event has occurred and there is a new portable device present. This bit is cleared when read and does not cause the ALERT# pin to be asserted. It causes the A_DET# pin to be asserted. 1 = Attach Detected 0 = No Attach Detected  2014-2018 Microchip Technology Inc. DS20005334B-page 51 UCS81003 10.3.1 PROFILE STATUS 1 REGISTER These bits are indicators only and do not cause the ALERT# pin or A_DET# pin to change states. REGISTER 10-5: The CUST, DCP, CDP and PT bits are cleared under the following circumstances: • the PWR_EN control is disabled • a new Active mode is selected • a Removal Detection event occurs. PROFILE STATUS 1 REGISTER (ADDRESS 12H) R-0 U-x U-x R-0 R-0 R-0 R-0 R-0 NO_HS — — VS_LOW CUST DCP CDP PT bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 NO_HS: The NO_HS bit is only set during the Dedicated Charger Emulation Cycle (see Section 9.10 “No Handshake”). This bit is automatically cleared whenever a new charger emulation profile is applied. (Note 1) 1 = No handshake at the end of the DCE Cycle. 0 = A new charger emulation profile is applied bit 6-5 Unimplemented bit 4 VS_LOW: Indicates that the VS voltage is below the VS_UVLO threshold and the port power switch is held OFF. This bit is automatically cleared when the VS voltage is above the VS_UVLO threshold. 1 = VS < VS_UVLO 0 = VS > VS_UVLO bit 3 CUST: Indicates that the portable device successfully performed a handshake with the user-defined Custom Charger Emulation Profile during the DCE Cycle and is charging. Based on the Custom Charger Emulation Profile configuration, the high-speed switch may either be open or closed (see Section 10.13 “Custom Emulation Configuration Registers”). The port power switch current limiting mode is determined by the Custom current limiting behavior settings (see Section 10.14.2 “Custom Current Limiting Behavior Configuration Register”). 1 = Custom Profile handshake complete 0 = No Custom Profile handshake bit 2 DCP: Indicates that the portable device accepted the BC1.2 DCP charger emulation profile and is charging. The high-speed switch is controlled via the HSW_DCE bit (see Section 10.4.5 “High-Speed Switch Configuration Register”), and the port power switch uses Constant Current Limiting. 1 = DCP handshake complete 0 = No DCP handshake bit 1 CDP: Indicates that the portable device successfully performed a handshake with the BC1.2 CDP charger emulation profile and is charging. The high-speed switch is closed, and the port power switch uses Trip Current Limiting. 1 = CDP handshake complete 0 = No CDP handshake bit 0 PT: Indicates that the UCS81003 is in the Data Pass-Through or BC1.2 SDP Active mode. The high-speed switch is closed, and the port power switch uses Trip Current Limiting. (Note 2) 1 = UCS81003 is in the Data Pass-Through or BC1.2 SDP Active mode. 0 = UCS81003 is not in the Data Pass-Through or BC1.2 SDP Active mode. Note 1: 2: The NO_HS bit does not indicate that a portable device is drawing current and it may be cleared to ‘0’ (indicating a handshake) and a portable device not charge. This bit is set at the end of each charger emulation profile if a portable device does not handshake with it. This bit is not set at the same time that any other Profile Status register bits are set. When the UCS81003 is configured as a Data Pass-Through and a Removal event and then an Attach event occur without changing the Active mode, the PT bit is not set again even though the UCS81003 is still operating as a Data Pass-Through as configured. Toggling the M1 control re-enables the PT status bit. DS20005334B-page 52  2014-2018 Microchip Technology Inc. UCS81003 10.3.2 PROFILE STATUS 2 REGISTER These bits indicate which profile is accepted. These bits are indicators only and do not cause the ALERT# pin or A_DET# pin to change states. REGISTER 10-6: These bits are cleared under the following circumstances: • the PWR_EN control is disabled • a new Active mode is selected • a Removal Detection event occurs. PROFILE STATUS 2 REGISTER (ADDRESS 13H) U-x R-0 R-0 R-0 R-0 R-0 R-0 R-0 — LG7 LG6 LG5 LG4 LG3 LG2 LG1 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 Unimplemented bit 6 LG7: Indicates that the portable device successfully performed a handshake with the Legacy 7 charger emulation profile and is charging. The high-speed switch is controlled via the HSW_DCE bit (see Section 10.4.5 “High-Speed Switch Configuration Register”). The port power switch current limiting mode is determined by the Custom current limiting behavior settings (see Section 10.14.2 “Custom Current Limiting Behavior Configuration Register”). 1 = Handshake successful with the Legacy 7 charger emulation profile and charging. 0 = Not charging with Legacy 7 charger emulation profile. bit 5 LG6: Indicates that the portable device successfully performed a handshake with the Legacy 6 charger emulation profile and is charging. The high-speed switch is controlled via the HSW_DCE bit (see Section 10.4.5 “High-Speed Switch Configuration Register”). The port power switch current limiting mode is determined by the Custom current limiting behavior settings (see Section 10.14.2 “Custom Current Limiting Behavior Configuration Register”). 1 = Handshake successful with the Legacy 6 charger emulation profile and charging. 0 = Not charging with Legacy 6 charger emulation profile. bit 4 LG5: Indicates that the portable device successfully performed a handshake with the Legacy 5 charger emulation profile and is charging. The high-speed switch is controlled via the HSW_DCE bit (see Section 10.4.5 “High-Speed Switch Configuration Register”). The port power switch current limiting mode is determined by the Custom current limiting behavior settings (see Section 10.14.2 “Custom Current Limiting Behavior Configuration Register”). 1 = Handshake successful with the Legacy 5 charger emulation profile and charging. 0 = Not charging with Legacy 5 charger emulation profile. bit 3 LG4: Indicates that the portable device successfully performed a handshake with the Legacy 4 charger emulation profile and is charging. The high-speed switch is controlled via the HSW_DCE bit (see Section 10.4.5 “High-Speed Switch Configuration Register”). The port power switch current limiting mode is determined by the Custom current limiting behavior settings (see Section 10.14.2 “Custom Current Limiting Behavior Configuration Register”). 1 = Handshake successful with the Legacy 4 charger emulation profile and charging. 0 = Not charging with Legacy 4 charger emulation profile. bit 2 LG3: Indicates that the portable device successfully performed a handshake with the Legacy 3 charger emulation profile and is charging. The high-speed switch is controlled via the HSW_DCE bit (see Section 10.4.5 “High-Speed Switch Configuration Register”). The port power switch current limiting mode is determined by the Custom current limiting behavior settings (see Section 10.14.2 “Custom Current Limiting Behavior Configuration Register”). 1 = Handshake successful with the Legacy 3 charger emulation profile and charging. 0 = Not charging with Legacy 3 charger emulation profile.  2014-2018 Microchip Technology Inc. DS20005334B-page 53 UCS81003 REGISTER 10-6: PROFILE STATUS 2 REGISTER (ADDRESS 13H) (CONTINUED) bit 1 LG2: Indicates that the portable device successfully performed a handshake with the Legacy 2 charger emulation profile and is charging. The high-speed switch is controlled via the HSW_DCE bit (see Section 10.4.5 “High-Speed Switch Configuration Register”). The port power switch current limiting mode is determined by the Custom current limiting behavior settings (see Section 10.14.2 “Custom Current Limiting Behavior Configuration Register”). 1 = Handshake successful with the Legacy 2 charger emulation profile and charging. 0 = Not charging with Legacy 2 charger emulation profile. bit 0 LG1: Indicates that the portable device successfully performed a handshake with the Legacy 1 charger emulation profile and is charging. The high-speed switch is controlled via the HSW_DCE bit (see Section 10.4.5 “High-Speed Switch Configuration Register”). The port power switch current limiting mode is determined by the Custom current limiting behavior settings (see Section 10.14.2 “Custom Current Limiting Behavior Configuration Register”). 1 = Handshake successful with the Legacy 1 charger emulation profile and charging. 0 = Not charging with Legacy 1 charger emulation profile. 10.3.3 PIN STATUS REGISTER The Pin Status register reflects the current pin state of the external control pins and identifies the power state. These bits are linked to the X_SET bits (see Section 10.4.3 “Switch Configuration Register”). REGISTER 10-7: PIN STATUS REGISTER (ADDRESS 14H) U-x R-0 R-0 R-0 R-0 R-0 — PWR_EN_PIN M2_PIN M1_PIN EM_EN_PIN SEL_PIN R-0 R-0 PWR_STATE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 Unimplemented bit 6 PWR_EN_PIN: Reflects the PWR_EN control state. This bit is set and automatically cleared as the PWR_EN pin/PWR_ENS bit state changes. 1 = PWR_EN is Logic 1 0 = PWR_EN is Logic 0 bit 5 M2_PIN: Reflects the M2 pin state. This bit is set and automatically cleared as the M2 pin/M2_SET state changes. 1 = M2 is Logic 1 0 = M2 is Logic 0 bit 4 M1_PIN: Reflects the M1 pin state. This bit is set and automatically cleared as the M1 pin/M1_SET state changes. 1 = M1 is Logic 1 0 = M1 is Logic 0 bit 3 EM_EN_PIN: Reflects the EM_EN pin state. This bit is set and automatically cleared as the EM_EN pin/EM_EN_SET state changes. 1 = EM_EN is Logic 1 0 = EM_EN Logic 0 bit 2 SEL_PIN: Reflects the polarity settings determined by the SEL pin decode. This bit is set or automatically cleared upon device power-up as the SEL pin is decoded. 1 = The PWR_EN control is active-high 0 = The PWR_EN control is active-low DS20005334B-page 54  2014-2018 Microchip Technology Inc. UCS81003 REGISTER 10-7: bit 1-0 PWR_STATE: Indicates the current power state. These bits are set and automatically cleared as the power state changes. (Note 1) 00 = Sleep 01 = Detect 10 = Active 11 = Error Note 1: 10.4 PIN STATUS REGISTER (ADDRESS 14H) (CONTINUED) Accessing the SMBus/I2C causes the UCS81003 to leave the Sleep state. As a result, the PWR_STATE bits are never read as 00b. Configuration Registers Bits Address Cof General Configuration Name 8 15h R/W Default 01h Emulation Configuration 8 16h R/W 8Ch Switch Configuration 8 17h R/W 04h Attach Detect Configuration 8 18h R/W 46h High-Speed Switch Configuration 8 25h R/W 14h The Configuration registers control basic device functionality. 10.4.1 GENERAL CONFIGURATION REGISTER The contents of this register are retained in Sleep. REGISTER 10-8: GENERAL CONFIGURATION REGISTER (ADDRESS 15H) R/W-0 U-x R/W-0 R/W-0 R/W-0 R/W-0 ALERT_MASK — ALERT_LINK DSCHG RTN_EN RTN_RST R/W-0 R/W-1 RATION_BEH bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 ALERT_MASK: Disables the ALERT# pin from asserting in the case of an error. 1 = The ALERT# pin is not asserted in the event of an error condition. 0 = The ALERT# pin is asserted if an error condition or an indicator event is detected. bit 6 Unimplemented bit 5 ALERT_LINK: Links the ALERT# pin to be asserted when the LOW_CUR and/or TREG bits are set. 1 = The ALERT# pin is asserted if the LOW_CUR or TREG indicator bit is set. 0 = The ALERT# pin is not asserted if the LOW_CUR or TREG indicator bit is set. bit 4 DSCHG: Forces the VBUS to reset and discharge when the UCS81003 is in the Active state. Writing this bit to a logic ‘1’ causes the port power switch to be opened and the discharge circuitry to activate discharging VBUS. The port power switch remains open while this bit is ‘1’. This bit is not self-clearing. bit 3 RTN_EN: Ration Enable – enables charge rationing functionality and power monitoring. 1 = Charge rationing is enabled (see Section 7.4 “Battery Full”). 0 = Charge rationing is disabled. The Total Accumulated Charge registers are cleared to 00_00h and current data is no longer accumulated. If the Total Accumulated Charge registers have reached the Charge Rationing Threshold (see Section 10.6 “Charge Rationing Threshold Registers”), the applied response is removed as though the charge rationing is placed on reset. This also clears the RATION status bit (if set).  2014-2018 Microchip Technology Inc. DS20005334B-page 55 UCS81003 REGISTER 10-8: GENERAL CONFIGURATION REGISTER (ADDRESS 15H) (CONTINUED) bit 2 RTN_RST: Ration Reset – resets the charge rationing functionality. When this bit is set to ‘1’, the Total Accumulated Charge registers are reset to 00_00h. In addition, when this bit is set, the RATION status bit is cleared and, if there are no other errors or active indicators, the ALERT# pin is released. 1 = EM_EN is Logic 1 0 = EM_EN is Logic 0 bit 1-0 RATION_BEH: Controls the behavior when the power rationing threshold is reached as shown in Table 7-1. 00 = Report 01 = Report and Disconnect 10 = Disconnect and Go to Sleep 11 = Ignore 10.4.2 EMULATION CONFIGURATION REGISTER The contents of this register are retained in Sleep. REGISTER 10-9: EMULATION CONFIGURATION REGISTER (ADDRESS 16H) R/W-1 U-x U-x R/W-0 R/W-1 R/W-1 DIS_TO — — EM_TO_DIS EM_RETRY EM_RESP R/W-0 R/W-0 EM_RESET_TIME bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 DIS_TO: Disable Timeout – Disables the Timeout and Idle Reset functionality (see Section 11.2.1.6 “SMBus Timeout and Idle Reset”). 1 = The Timeout and Idle Reset functionality is disabled. This is used for I2C compliance. 0 = The Timeout and Idle Reset functionality is enabled. bit 6-5 Unimplemented bit 4 EM_TO_DIS: Emulation Timeout Disable – disables the emulation circuitry timeout for all charger emulation profiles in the DCE Cycle. There is a separate bit to enable/disable the emulation timeout for the Custom Charger Emulation profile (Register 10-35); however, if the EM_TO_DIS bit is set, the emulation timeout is also disabled for the Custom charger emulation profile. (Note 1) 1 = Emulation timeout is disabled during the DCE Cycle. The applied charger emulation profile does not exit as a result of an emulation timeout event. The IBUS current is continuously checked and if it exceeds the IBUS_CHG threshold for any reason, the charger emulation profile is accepted. 0 = Emulation timeout is enabled during the DCE Cycle. An individual charger emulation profile is applied and maintained for the duration of the tEM_TIMEOUT value. When this timer expires, the UCS81003 determines whether the charger emulation profile is successful and takes appropriate action. bit 3 EM_RETRY: Configures whether the DCE Cycle must be reset or restarted if it reaches the final profile without the portable device drawing charging current and accepting one of the profiles. This bit is only used if the UCS81003 is configured to emulate a dedicated charger. 1 = Once the DCE Cycle is completed, it performs Emulation Reset and restarts from the first enabled charger emulation profile in the DCE Cycle. 0 = Once the DCE Cycle is completed, it does not restart. The DPOUT and DMOUT are left as High Z pins and the port power switch is closed. The Current Limiting mode is determined by the Custom Current Limiting Behavior settings (see Section 10.14.2 “Custom Current Limiting Behavior Configuration Register”). DS20005334B-page 56  2014-2018 Microchip Technology Inc. UCS81003 REGISTER 10-9: EMULATION CONFIGURATION REGISTER (ADDRESS 16H) (CONTINUED) bit 2 EM_RESP: Leave Emulation Response – enables the Dedicated Charger Emulation Cycle mode to hold the DPOUT and DMOUT stimulus response after the UCS81003 has finished emulation using the Legacy, BC1.2 DCP, or Custom charger emulation profiles (Note 2). 1 = If a portable device begins drawing charging current while the UCS81003 is applying the BC1.2 DCP, Custom or any of the Legacy charger emulation profiles during the DCE Cycle, the last response applied is kept in place until a Removal Detection event occurs, the internal temperature exceeds the TREG value, or emulation is restarted. In the case of the BC1.2 DCP or Legacy 3 charger emulation profiles, this is the short (RDCP_RES). In the case of the Legacy 1, Legacy 2 or Legacy 4-7 profiles, this is the DPOUT and DMOUT pin voltages. If a portable device does not draw charging current, the DCE Cycle behaves normally. 0 = The dedicated emulation circuitry behaves normally. It removes the short condition when the tEM_TIMEOUT timer has expired, regardless if the portable device has drawn charging current or not. bit 1-0 EM_RESET_TIME: Determines the length of the tEM_RESET time (see Section 9.8.1 “Emulation Reset”) as shown below. The value selected does not include discharge time; however, this value plus discharge result in the actual reset time. 00 = 50 ms 01 = 75 ms 10 = 125 ms 11 = 175 ms Note 1: 2: If the EM_TO_DIS bit is set and the Legacy 2, Legacy 4 or Custom charger emulation profiles are accepted during the DCE cycle, a removal is not detected. To avoid this issue, re-enable the emulation timeout after applying any test profiles and charging with the final profile. If the HSW_DCE bit is set, the high-speed switch is closed regardless of the status of the EM_RESP bit. Leaving the emulation response applied does not enable normal USB traffic. Therefore, prior to setting the HSW_DCE bit, this bit must be cleared. 10.4.3 SWITCH CONFIGURATION REGISTER The contents of this register are retained in Sleep. REGISTER 10-10: SWITCH CONFIGURATION REGISTER (ADDRESS 17H) R/W-0 U-x R/W-0 R/W-0 R/W-0 R/W-1 R/W-0 R/W-0 PIN_IGN — EM_EN_SET M2_SET M1_SET S0_SET PWR_ENS LATCHS bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 PIN_IGN: Ignores the M1, M2, PWR_EN, and EM_EN pin states when determining the Active mode selection and power state. 1 = The Active mode selection and power state are set by the individual control bits and not by the M1, M2, PWR_EN, and EM_EN pin states. These pin states are ignored. 0 = The Active mode selection and power state are set by the OR’d combination of the M1, M2, PWR_EN, and EM_EN pin states and the corresponding bit states. bit 6 Unimplemented bit 5 EM_EN_SET: In conjunction with other controls, determines the Active mode that is selected (see Section 9.2 “Active Mode Selection”) and power state (see Table 5-2). This bit is OR’d with the EM_EN pin. bit 4 M2_SET: In conjunction with other controls, determines the Active mode that is selected (see Section 9.2 “Active Mode Selection”) and power state (see Table 5-2). This bit is OR’d with the M2 pin. bit 3 M1_SET: In conjunction with other controls, determines the Active mode that is selected (see Section 9.2 “Active Mode Selection”) and power state (see Table 5-2). This bit is OR’d with the M1 pin.  2014-2018 Microchip Technology Inc. DS20005334B-page 57 UCS81003 REGISTER 10-10: SWITCH CONFIGURATION REGISTER (ADDRESS 17H) (CONTINUED) bit 2 S0_SET: In SMBus mode, enables the Attach and Removal Detection feature and affects the power state (see Section 9.2 “Active Mode Selection”). 1 = Detection is enabled. Also see Table 5-2. 0 = Detection is not enabled. Also see Table 5-2. bit 1 PWR_ENS: Controls whether the port power switch may be turned ON or not and affects the power state (see Section 5.3.4 “PWR_EN Input”). This bit is OR’d with the PWR_EN pin and the polarity of both are controlled by SEL pin decode. Thus, if the polarity is set to active-high, either the PWR_EN pin or this bit must be ‘1’ to enable the port power switch. bit 0 LATCHS: In SMBus mode, controls the fault handling routine that is used in case an error is detected (see Section 5.3.5 “Latch Input”). 1 = The UCS81003 latches its error conditions. In order for the device to return to normal Active state, the ERR bit must be cleared by the user. 0 = The UCS81003 automatically retries when an error condition is detected. 10.4.4 ATTACH DETECTION CONFIGURATION RESISTER The contents of this register are retained in Sleep. REGISTER 10-11: ATTACH DETECTION CONFIGURATION REGISTER (ADDRESS 18H) R/W-0 R/W-1 R/W-0 RESERVED R/W-0 R/W-0 R/W-1 DISCHG_TIME_SEL R/W-1 R/W-0 ATT_TH bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-4 RESERVED: Do not change. bit 3-2 DISCHG_TIME_SEL: Sets the tDISCHARGE time as follows: 00 = 100 ms 01 = 200 ms 10 = 300 ms 11 = 400 ms bit 1-0 ATT_TH: Determines the Attach Detection threshold (IDET_QUAL) and Removal Detection thresholds (IREM_QUAL_DET and IREM_QUAL_ACT) as shown below. (Note 1) 00 = 200 µA Attach, 100 µA Removal Threshold 01 = 400 µA Attach, 300 µA Removal Threshold 10 = 800 µA Attach, 700 µA Removal Threshold 11 = 1000 µA Attach, 900 µA Removal Threshold Note 1: The removal threshold is different when operating in the Active power state versus when operating in the Detect power state. DS20005334B-page 58  2014-2018 Microchip Technology Inc. UCS81003 10.4.5 HIGH-SPEED SWITCH CONFIGURATION REGISTER The contents of this register are retained in Sleep. REGISTER 10-12: HIGH-SPEED SWITCH CONFIGURATION REGISTER (ADDRESS 25H) U-x U-x U-x R/W-1 R/W-0 R/W-1 R/W-0 R/W-0 — — — RESERVED HSW_CUST HSW_CDP HSW_DET HSW_DCE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-5 Unimplemented bit 4 RESERVED: Do not change. bit 3 HSW_CUST: Enables the USB high-speed data switch to be active during the Custom handshake. This control is checked at the beginning o f charger emulation. Therefore, changing this control during emulation has no immediate effect. Upon restarting charger emulation (as a result of the EM_RETRY bit being set, a Removal Detection event, or change of emulation controls), the high-speed switch is closed. 1 = The USB high-speed data switch is enabled while the Custom charger emulation profile is applied. Also, if the Custom charger emulation profile is accepted during the Dedicated Charger Emulation Cycle, the high-speed switch stays closed. 0 = The USB high-speed data switch is disabled while the Custom charger emulation profile is applied. bit 2 HSW_CDP: Enables the USB high-speed data switch to be active during the CDP handshake. This control is checked at the beginning of charger emulation. Therefore, changing this control during emulation has no immediate effect. Upon restarting charger emulation (as a result of a Removal Detection event or change of emulation controls), the high-speed switch is closed. 1 = The USB high-speed data switch is enabled during the CDP handshake. 0 = The USB high-speed data switch is disabled during the CDP handshake. bit 1 HSW_DET: Enables the USB high-speed data switch to be active during the Detect power state. If the S0 control is set to ‘0’, this bit is ignored. 1 = The USB high-speed data switch is closed during the Detect power state. 0 = The USB high-speed data switch is open during the Detect power state. bit 0 HSW_DCE: Enables the USB high-speed data switch after the DCP charger emulation profile or one of the Legacy charger emulation profiles is accepted during the DCE Cycle and the portable device is charging. This bit is ignored if the UCS81003 is not in the Active state. This bit does not cause the highspeed switch to be closed during emulation when the DCP and Legacy profiles are applied, only after the DCP or a Legacy charger emulation profile is accepted. 1 = The USB high-speed data switch is closed. 0 = The USB high-speed data switch is open.  2014-2018 Microchip Technology Inc. DS20005334B-page 59 UCS81003 10.5 Current Limit Register Name Bits Address Cof Default 8 19h R/W 00h Current Limit The Current Limit register controls the ILIM used by the port power switch. The default setting is based on the resistor on the COMM_SEL/ILIM pin and this value cannot be changed to be higher than the hardware set value. The contents of this register are retained in Sleep. REGISTER 10-13: CURRENT LIMIT REGISTER (ADDRESS 19H) U-x U-x U-x U-x U-x — — — — — R/W-0 R/W-0 R/W-0 ILIM_SW bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-3 Unimplemented bit 2-0 ILIM_SW: Sets the ILIM value as follows: 000 = 0.57A 001 = 1.00A 010 = 1.13A 011 = 1.35A 100 = 1.68A 101 = 2.05A 110 = 2.28A 111 = 2.85A (3.0A maximum) Unless otherwise indicated, the values specified above are the typical ILIM in the Table 1-2. Note 1: 10.6 x = Bit is unknown Charge Rationing Threshold Registers Name Bits Address Cof Default Charge Rationing Threshold High Byte 8 1Ah R/W FFh Charge Rationing Threshold Low Byte 8 1Bh R/W FFh Charge registers are updated, the value is checked against this limit. If the value meets or exceeds this limit, the RATION bit is set (see Section 10.4.1 “General Configuration Register”) and action taken according to the RATION_BEH bits (see Section 10.4.1 “General Configuration Register”). The units are in mAh, with a range from 0 to ~218429. The contents of this register are retained in Sleep. The Charge Rationing Threshold registers set the maximum allowed charge that is delivered to a portable device. Whenever the Total Accumulated REGISTER 10-14: CHARGE RATIONING THRESHOLD (ADDRESS 1AH - 1BH) R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 CHTHR CHTHR CHTHR CHTHR CHTHR CHTHR CHTHR CHTHR R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 CHTHR CHTHR CHTHR CHTHR CHTHR CHTHR CHTHR CHTHR bit 15 bit 8 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-0 x = Bit is unknown CHTHR: Charge Rationing Threshold LSB = 3.333 mAh DS20005334B-page 60  2014-2018 Microchip Technology Inc. UCS81003 10.7 Auto-Recovery Configuration Register Name Auto-Recovery Configuration Bits Address Cof Default 8 1Ch R/W 2Ah Once the Auto-Recovery Fault Handling algorithm has checked the overtemperature and back-drive conditions, it sets the ILIM value to ITEST and then turns ON the port power switch and starts the tRST timer. If after the timer has expired, the VBUS voltage is less than VTEST, then it is assumed that a short-circuit condition is present and the Error state is reset. The contents of this register are retained in Sleep. The Auto-Recovery Configuration register sets the parameters used when the Auto-Recovery Fault Handling algorithm is invoked (see Section 7.5.1 “Auto-Recovery Fault Handling”). REGISTER 10-15: AUTO-RECOVERY CONFIGURATION REGISTER (ADDRESS 1CH) U-x R/W-0 — R/W-1 TCYCLE R/W-0 R/W-1 R/W-0 TRST_SW R/W-1 R/W-0 VTST_SW bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 Unimplemented bit 6-4 TCYCLE: Defines the delay (tCYCLE) after the Error state is entered before the Auto-Recovery Fault Handling algorithm is started as shown below. 000 = 15 ms 001 = 20 ms 010 = 25 ms 011 = 30 ms 101 = 40 ms 110 = 45 ms 111 = 50 ms bit 3-2 TRST_SW: Sets the tRST time as shown as shown below. 00 = 10 ms 01 = 15 ms 10 = 20 ms 11 = 25 ms bit 1-0 VTST_SW: Sets the VTEST value as shown below. 00 = 250 mV 01 = 500 mV 10 = 750 mV 11 = 1000 mV  2014-2018 Microchip Technology Inc. DS20005334B-page 61 UCS81003 10.8 IBUS_CHG Configuration Register Name Bits Address Cof Default 8 1Eh R/W 0Fh IBUS_CHG Configuration The IBUS_CHG Configuration register sets the IBUS_CHG current value. If current greater than IBUS_CHG is detected flowing out of VBUS, emulation is successful. The bit weights are in mA, and the range is from 11.72 mA to 175.8 mA. The contents of this register are not retained in Sleep. REGISTER 10-16: IBUS_CHG CONFIGURATION REGISTER (ADDRESS 1EH) U-x U-x U-x U-x R/W-1 R/W-1 R/W-1 R/W-1 — — — — ICHG ICHG ICHG ICHG bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-4 Unimplemented bit 3-0 ICHG 1 LSB = 11.72 mA 10.9 x = Bit is unknown TDET_CHARGE Configuration Register Name TDET_CHARGE Configuration Bits Address Cof Default 8 1Fh R/W 03h The TDET_CHARGE Configuration register controls the tDC_TEMP and tDET_CHARGE timing. The tDC_TEMP timer is started whenever the temperature exceeds TREG. This timer is meant to give the system time to cool at the lower ILIM setting before changing ILIM again. The tDET_CHARGE timer is started whenever the VBUS voltage is discharged and the bypass switch is reactivated. This timer is meant to be a time delay to enable the VBUS capacitor to charge before detecting an Attach Detection event. If tDET_CHARGE time is increased greater than 800 ms, larger bus capacitors can be accommodated; however, with a portable device present and PWR_EN disabled, a Removal Detection event and then another Attach Detection event occurs. The contents of this register are retained in Sleep. DS20005334B-page 62  2014-2018 Microchip Technology Inc. UCS81003 REGISTER 10-17: TDET_CHARGE CONFIGURATION REGISTER (ADDRESS 1FH) U-x U-x U-x R/W-0 — — — DC_TEMP_SET R/W-0 R/W-0 R/W-1 R/W-1 DET_CHARGE_SET bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-5 Unimplemented bit 4-3 DC_TEMP_SET: Determines the tDC_TEMP time as shown below. 00 = 200 ms 01 = 400 ms 10 = 800 ms 11 = 1600 ms bit 2-0 DET_CHARGE_SET: Determines the tDET_CHARGE time as shown below. 000 = 200 ms 001 = 400 ms 010 = 600 ms 011 = 800 ms 100 = 1000 ms 101 = 1200 ms 110 = 1400 ms 111 = 2000 ms 10.10 Preloaded Emulation Enable Registers Name Bits Address Cof Default BCS Emulation Enable 8 20h R/W 16h Legacy Emulation Enable 8 21h R/W 00h The Preloaded Emulation Enable registers enable the charger emulation profiles used by the emulation circuitry. The contents of these registers are retained in Sleep. REGISTER 10-18: BCS EMULATION ENABLE REGISTER (ADDRESS 20H) U-x U-x U-x R/W-1 U-x — — — DCP_EM_DIS — R/W-1 R/W-1 R/W-0 RESERVED bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-5 Unimplemented bit 4 DCP_EM_DIS: Disables the DCP charger emulation profile in the DCE Cycle. This bit is ignored if the M1, M2, and EM_EN control settings have selected the DCP mode (see Table 9-1). 1 = The BC1.2 DCP charger emulation profile is not enabled during the DCE Cycle. 0 = The BC1.2 DCP charger emulation profile is enabled during the Dedicated Charger Emulation Cycle. bit 3 Unimplemented bit 2-0 RESERVED: Do not change.  2014-2018 Microchip Technology Inc. DS20005334B-page 63 UCS81003 REGISTER 10-19: LEGACY EMULATION ENABLE REGISTER (ADDRESS 21H) U-x R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — L7EM_DIS L6EM_DIS L5EM_DIS L4EM_DIS L3EM_DIS L2EM_DIS L1EM_DIS bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 Unimplemented bit 6 L7EM_DIS: Disables the Legacy 7 charger emulation profile. 1 = The Legacy 7 charger emulation profile is not enabled. 0 = The Legacy 7 charger emulation profile is enabled. bit 5 L6EM_DIS: Disables the Legacy 6 charger emulation profile. 1 = The Legacy 6 charger emulation profile is not enabled. 0 = The Legacy 6 charger emulation profile is enabled. bit 4 L5EM_DIS: Disables the Legacy 5 charger emulation profile. 1 = The Legacy 5 charger emulation profile is not enabled. 0 = The Legacy 5 charger emulation profile is enabled. bit 3 L4EM_DIS: Disables the Legacy 4 charger emulation profile. 1 = The Legacy 4 charger emulation profile is not enabled. 0 = The Legacy 4 charger emulation profile is enabled. bit 2 L3EM_DIS: Disables the Legacy 3 charger emulation profile. 1 = The Legacy 3 charger emulation profile is not enabled. 0 = The Legacy 3 charger emulation profile is enabled. bit 1 L2EM_DIS: Disables the Legacy 2 charger emulation profile. 1 = The Legacy 2 charger emulation profile is not enabled. 0 = The Legacy 2 charger emulation profile is enabled. bit 0 L1EM_DIS: Disables the Legacy 1 charger emulation profile. 1 = The Legacy 1 charger emulation profile is not enabled. 0 = The Legacy 1 charger emulation profile is enabled. x = Bit is unknown 10.11 Preloaded Emulation Timeout Configuration Registers Bits Address Cof Default BCS Emulation Timeout Config Name 8 22h R/W 10h Legacy Emulation Timeout Config 1 8 23h R/W 6Ch Legacy Emulation Timeout Config 2 8 24h R/W 01h The Preloaded Emulation Timeout Configuration registers control the tEM_TIMEOUT setting that is applied whenever the indicated preloaded charger emulation profile is applied during the DCE Cycle. These settings are not used if the EM_TO_DIS bit is set. The contents of this registers are retained in Sleep. DS20005334B-page 64  2014-2018 Microchip Technology Inc. UCS81003 REGISTER 10-20: BCS EMULATION TIMEOUT CONFIG REGISTER (ADDRESS 22H) U-x U-x — — R/W-0 R/W-1 R/W-0 DCP_EM_TO R/W-0 R/W-0 R/W-0 RESERVED bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-6 Unimplemented bit 5-4 DCP_EM_TO: Defines the tEM_TIMEOUT setting as shown below. This is applied when the BC1.2 DCP charger emulation profile is used during the DCE Cycle. 00 = 0.8s 01 = 1.6s 10 = 6.4s 00 = 12.8s bit 3-0 RESERVED: Do not change. REGISTER 10-21: LEGACY EMULATION TIMEOUT CONFIG 1 REGISTER (ADDRESS 23H) R/W-0 R/W-1 R/W-1 L1EM_TO R/W-0 L2EM_TO R/W-1 R/W-1 L3EM_TO R/W-0 R/W-0 L4EM_TO bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-6 L1EM_TO: Defines the tEM_TIMEOUT setting as shown below. This is applied when the Legacy 1 charger emulation profile is used during the DCE Cycle. 00 = 0.8s 01 = 1.6s 10 = 6.4s 11 = 12.8s bit 5-4 L2EM_TO: Defines the tEM_TIMEOUT setting as shown below. This is applied when the Legacy 2 charger emulation profile is used during the DCE Cycle. 00 = 0.8s 01 = 1.6s 10 = 6.4s 11 = 12.8s bit 3-2 L3EM_TO: Defines the tEM_TIMEOUT setting as shown below. This is applied when the Legacy 3 charger emulation profile is used during the DCE Cycle. 00 = 0.8s 01 = 1.6s 10 = 6.4s 11 = 12.8s bit 1-0 L4EM_TO: Defines the tEM_TIMEOUT setting as shown below. This is applied when the Legacy 4 charger emulation profile is used during the DCE Cycle. 00 = 0.8s 01 = 1.6s 10 = 6.4s 11 = 12.8s  2014-2018 Microchip Technology Inc. DS20005334B-page 65 UCS81003 REGISTER 10-22: LEGACY EMULATION TIMEOUT CONFIG 2 REGISTER (ADDRESS 24H) U-x U-x — — R/W-0 R/W-0 L5EM_TO R/W-0 R/W-0 L6EM_TO R/W-0 R/W-1 L7EM_TO bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-6 Unimplemented bit 5-4 L5EM_TO: Defines the tEM_TIMEOUT setting as shown below. This is applied when the Legacy 5 charger emulation profile is used during the DCE Cycle. 00 = 0.8s 01 = 1.6s 10 = 6.4s 11 = 12.8s bit 3-2 L6EM_TOV: Defines the tEM_TIMEOUT setting as shown below. This is applied when the Legacy 6 charger emulation profile is used during the DCE Cycle. 00 = 0.8s 01 = 1.6s 10 = 6.4s 11 = 12.8s bit 1-0 L7EM_TO: Defines the tEM_TIMEOUT setting as shown below. This is applied when the Legacy 7 charger emulation profile is used during the DCE Cycle. 00 = 0.8s 01 = 1.6s 10 = 6.4s 11 = 12.8s 10.12 Preloaded Emulation Configuration Registers Name Bits Address Cof Default Applied Charger Emulation 8 30h R 00h Preloaded Emulation Stimulus 1 – Config 1 8 31h R 00h Preloaded Emulation Stimulus 1 – Config 2 8 32h R 26h Preloaded Emulation Stimulus 1 – Config 3 8 33h R 00h Preloaded Emulation Stimulus 1 – Config 4 8 34h R 02h Preloaded Emulation Stimulus 2 -– Config 1 8 35h R 00h Preloaded Emulation Stimulus 2 – Config 2 8 36h R 09h Preloaded Emulation Stimulus 2 – Config 3 8 37h R 00h Preloaded Emulation Stimulus 2 – Config 4 8 38h R 04h Preloaded Emulation Stimulus 3 – Config 1 8 39h R 00h Preloaded Emulation Stimulus 3 – Config 2 8 3Ah R 00h Preloaded Emulation Stimulus 3 – Config 3 8 3Bh R 00h DS20005334B-page 66 The Preloaded Emulation Configuration registers store the settings loaded from internal memory as required for the preloaded charger emulation profile that is actively being applied. These registers are read only. The Legacy charger emulation profiles, the BC1.2 SDP and the BC1.2 DCP, do not use the Stimulus 3 Configuration registers (39h-3Bh). Whenever these charger emulation profiles are applied, registers 39h-3Bh are not updated and their contents must be ignored. Whenever a Legacy charger emulation profile is applied within the DCE Cycle, these controls are not updated and must be ignored. These settings are only used by the BC1.2 CDP and BC1.2 DCP charger emulation profiles. The contents of registers 31h, 35h, and 39h are not retained in Sleep. These are updated as needed. The contents of registers 32h, 33h, 34h, 36h, 37h, 38h, 3Ah, 3Bh, and 40h are retained in Sleep. 10.12.1 APPLIED CHARGER EMULATION REGISTER The contents of this register are not retained in Sleep. The contents are updated as the charger emulation profile being applied changes.  2014-2018 Microchip Technology Inc. UCS81003 REGISTER 10-23: APPLIED CHARGER EMULATION REGISTER (ADDRESS 30H) U-x U-x U-x U-x — — — — R-0 R-0 R-0 R-0 PRE_EM_SEL bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-4 Unimplemented bit 3-0 PRE_EM_SEL: Indicates which of the charger emulation profiles is being actively applied as shown below. 0000 = Data Pass-Through or BC1.2 SDP 0001 = BC1.2 CDP 0010 = BC1.2 DCP 0011 = Legacy 1 0100 = Legacy 2 0101 = Legacy 3 0110 = Legacy 4 0111 = Legacy 5 1000 = Legacy 6 1001 = Legacy 7 1010 = Custom Profile All others = Not used REGISTER 10-24: PRELOADED EMULATION STIMULUS 1 CONFIGURATION 1 REGISTER (ADDRESS 31H) U-x R-0 — S1_TD_TYPE R-0 R-0 R-0 R-0 S1_TD R-0 R-0 STIM1 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 Unimplemented bit 6 S1_TD_TYPE: Determines the behavior of the stimulus timer. 1 = The stimulus timer controls how long the response is applied after the stimulus is detected. The response is immediately applied and held for the duration of the timer, and then removed if the stimulus is removed. 0 = The stimulus timer is a delay from when the stimulus is detected until the response is performed. bit 5-3 S1_TD: Determines the stimulus 1 tSTIM_DEL value as shown below. 000 = 0 ms 001 = 1 ms 010 = 5 ms 011 = 10 ms 100 = 20 ms 101 = 40 ms 110 = 80 ms 111 =100 ms  2014-2018 Microchip Technology Inc. DS20005334B-page 67 UCS81003 REGISTER 10-24: PRELOADED EMULATION STIMULUS 1 CONFIGURATION 1 REGISTER (ADDRESS 31H) (CONTINUED) bit 2-0 STIM1: Determines the Stimulus 1 that is used as shown below. Note that the lower threshold for the window comparator option is fixed at 400 mV (UCS81003AM), or 470 mV (UCS81003AB), and only applies to the DPOUT pin. This setting cannot be used for the DMOUT port. 000 = VBUS voltage ready to be applied before port power switch is closed. Next stimulus does not wait for this to be removed. 001 = DPOUT voltage is higher than the threshold (S1_TH). 010 = Window comparator. DPOUT voltage is lower than the threshold (S1_TH) and DPOUT voltage higher than the fixed threshold. 011 = DMOUT voltage is higher than the threshold (S1_TH). 100 = Do not use. 101 = Do not use. 110 = DPOUT voltage is higher than the threshold (S1_TH). 111 = VBUS voltage is present after port power switch is closed. Next stimulus does not wait for this to be removed. REGISTER 10-25: PRELOADED EMULATION STIMULUS 1 CONFIGURATION 2 REGISTER (ADDRESS 32H) R-0 R-0 R-1 R-0 R-0 S1_R1MAG R-1 R-1 R-0 S1_R1 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-4 x = Bit is unknown S1_R1MAG: Determines the magnitude of the response to the stimulus. The bit decode changes meaning based on which response is selected. Data written to any field that is identified as “Do not use” is not accepted. The data is not updated and the settings remain set at the previous value. • For S1_R1 settings 0000-0011, the response is a voltage applied on the DPOUT/DMOUT pins. The S1_R1MAG bits specify the voltage relative to ground: 0000 = Pull Down 0110 = 600 mV 1100 = 1800 mV 0001 = 400 mV 0111 = 700 mV 1101 = 2000 mV 0010 = 400 mV 1000 = 800 mV 1110 = 2200 mV 0011 = 400 mV 1001 = 900 mV 1111 = Do not use 0100 = 400 mV 1010 = 1400 mV 0101 = 500 mV 1011 = 1600 mV • For S1_R1 settings 0100, 0111, 1101-1111, the response is a resistor connected on the DPOUT/DMOUT to GND or VBUS. The S1_R1MAG bits specify the resistor value: 0000 = 1.8 k 0110 = 40 k 1100 = 100 k 0001 = 10 k 0111 = 43 k 1101 = 120 k 0010 = 15 k 1000 = 50 k 1110 = 150 k 0011 = 20 k 1001 = 60 k 1111 = Do not use 0100 = 25 k 1010 = 75 k 0101 = 30 k 1011 = 80 k • For S1_R1 settings 0110, 1001, 1100, the response is a voltage divider applied from VBUS to GND with the center tap at DPOUT/DMOUT. The S1_R1MAG bits specify the minimum resistance of the voltage divider (Sum of R1 + R2): 0000 = 93 k 0110 = 200 k 1100 = 200 k 0001 = 100 k 0111 = 200 k 1101 = 200 k 0010 = 125 k 1000 = 93 k 1110 = 200 k 0011 = 150 k 1001 = 100 k 1111 = Do not use 0100 = 200 k 1010 = 125 k 0101 = 200 k 1011 = 150 k DS20005334B-page 68  2014-2018 Microchip Technology Inc. UCS81003 REGISTER 10-25: PRELOADED EMULATION STIMULUS 1 CONFIGURATION 2 REGISTER (ADDRESS 32H) (CONTINUED) bit 3-0 S1_R1: Defines the stimulus response as shown below. 0000 = Remove previous response on DPOUT and DMOUT 0001 = Apply voltage on DPOUT (Note 1). 0010 = Apply voltage on DMOUT (Note 2). 0011 = Apply voltage on DPOUT and DMOUT. 0100 = Connect resistor from DPOUT to GND (Note 1). 0101 = Do not use. 0110 = Connect voltage divider from VBUS to GND with the center tap at DPOUT (Note 1). 0111 = Connect resistor form DMOUT to GND (Note 2). 1000 = Do not use. 1001 = Connect voltage divider from VBUS to GND with the center tap at DMOUT (Note 2). 1010 = Connect  200resistor from DPOUT to DMOUT. 1011 = Do not use. 1100 = Connect voltage divider from VBUS to GND with the center tap at DPOUT and DMOUT. 1101 = Connect resistor from DPOUT to GND and DMOUT to GND. 1110 = If STIM1 = 000, the 15 kpull-down resistors applied to DPOUT and DMOUT during Emulation Reset are not removed. If STIM1 = 111, the 15 k pull-down resistors applied to DPOUT and DMOUT during Emulation Reset are removed. For all other STIM1 settings, whatever is applied is not changed. 1111 = Same as 1110 case above. Note 1: 2: If STIM1 = 000b and no other response is applied to the DPOUT pin, the 15 k pull-down resistor applied to the DPOUT pin during Emulation Reset is not removed. Otherwise, the previous response is left on the DPOUT pin (if applicable) or the 15 k pull-down resistor is removed. If STIM1 = 000b and no other response is applied to the DMOUT pin, the 15 k pull-down resistor applied to the DMOUT pin during Emulation Reset is not removed. Otherwise, the previous response is left on the DMOUT pin (if applicable) or the 15 k pull-down resistor is removed. REGISTER 10-26: PRELOADED EMULATION STIMULUS 1 CONFIGURATION 3 REGISTER (ADDRESS 33H)(Note 1) U-x U-x — — R-0 R-0 R-0 S1_PUPD R-0 R-0 R-0 S1_TH bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-6 Unimplemented bit 5-4 S1_PUPD: Determines the magnitude of the pull-down current applied on the DPOUT and DMOUT pins when the stimulus response is to apply a voltage and the voltage magnitude is set at pull-down (0000b). The bit decode is given below. 00 = 10 µA 01 = 50 µA 10 = 100 µA 11 = 150 µA  2014-2018 Microchip Technology Inc. DS20005334B-page 69 UCS81003 REGISTER 10-26: PRELOADED EMULATION STIMULUS 1 CONFIGURATION 3 REGISTER (ADDRESS 33H)(Note 1) (CONTINUED) bit 3-0 Note 1: S1_TH: Defines the threshold value as shown below for the specified stimulus. If the stimulus is VBUS voltage is ready to be applied or applied (that is, STIM1 = 000b or 111b), the threshold value is ignored. 0000 = 400 mV 0001 = 400 mV 0010 = 400 mV 0011 = 300 mV 0100 = 400 mV 0101 = 500 mV 0110 = 600 mV 0111 = 700 mV 1000 = 800 mV 1001 = 900 mV 1010 = 1400 mV 1011 = 1600 mV 1100 = 1800 mV 1101 = 2000 mV 1110 = 2200 mV 1111 = Do not use. The Legacy charger emulation profiles do not use these settings. Whenever a Legacy charger emulation profile is applied within the DCE Cycle, these controls are not updated and must be ignored. These settings are only used by the BC1.2 CDP and DCP charger emulation profiles. REGISTER 10-27: PRELOADED EMULATION STIMULUS 1 CONFIGURATION 4 REGISTER (ADDRESS 34H)(Note 1) U-x U-x U-x U-x U-x — — — — — R-0 R-1 R-0 S1_RATIO bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-3 Unimplemented bit 2-0 S1_RATIO: Determines the voltage divider ratio as shown below when the stimulus response is set to connect a voltage divider (that is, S1_R1 = 0110b, 1001b, or 1100b). 000 = 0.25 001 = 0.33 010 = 0.4 011 = 0.5 100 = 0.54 101 = 0.6 110 = 0.66 111 = Do not use. Note 1: The BC1.2 DCP and CDP charger emulation profiles do not use this control. Whenever the BC1.2 CDP or DCP charger emulation profile is applied, these controls are not updated and must be ignored. These settings are only used by the Legacy charger emulation profiles. DS20005334B-page 70  2014-2018 Microchip Technology Inc. UCS81003 REGISTER 10-28: PRELOADED EMULATION STIMULUS 2 CONFIGURATION 1 REGISTER (ADDRESS 35H) U-x R-0 — S2_TD_TYPE R-0 R-0 R-0 R-0 S2_TD R-0 R-0 STIM2 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 Unimplemented bit 6 S2_TD_TYPE: Determines the behavior of the stimulus timer. 1 = The stimulus timer controls how long the response is applied after the stimulus is detected. The response is immediately applied and held for the duration of the timer, and then removed if the stimulus is removed. 0 = The stimulus timer is a delay from when the stimulus is detected until the response is performed. bit 5-3 S2_TD: Determines the Stimulus 2 tSTIM_DEL value as shown below. 000 = 0 ms 001 = 1 ms 010 = 5 ms 011 = 10 ms 100 = 20 ms 101 = 40 ms 110 = 80 ms 111 = 100 ms bit 2-0 STIM2: Determines the Stimulus 2 that is used as shown below. Note that the lower threshold for the window comparator option is fixed at 400 mV (UCS81003AM), or 470 mV (UCS81003AB), and only applies to the DPOUT pin. This setting cannot be used for the DMOUT port. 000 = VBUS voltage ready to be applied before port power switch is closed. Next stimulus does not wait for this to be removed. 001 = DPOUT voltage is greater than the threshold (S2_TH). 010 = Window comparator. DPOUT voltage is lower than the threshold (S2_TH) and DPOUT voltage greater than the fixed threshold. 011 = DMOUT voltage is greater than the threshold (S2_TH). 100 = Do not use. 101 = Do not use. 110 = DPOUT voltage is greater than the threshold (S2_TH). 111 = Voltage is present after the port power switch is closed. Next stimulus does not wait for this to be removed.  2014-2018 Microchip Technology Inc. DS20005334B-page 71 UCS81003 REGISTER 10-29: PRELOADED EMULATION STIMULUS 2 CONFIGURATION 2 REGISTER (ADDRESS 36H) R-0 R-0 R-0 R-0 R-1 S2_R2MAG R-0 R-0 R-1 S2_R2 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-4 x = Bit is unknown S2_R2MAG: Determines the magnitude of the response to the stimulus. The bit decode changes meaning based on which response is selected. Data written to any field that is identified as “Do not use” is not accepted. The data is not updated and the settings remain set at the previous value. • For S2_R2 settings 0000-0011, the response is a voltage applied on the DPOUT/DMOUT pins. The S2_R2MAG bits specify the voltage relative to ground: 0000 = Pull Down 0110 = 600 mV 1100 = 1800 mV 0001 = 400 mV 0111 = 700 mV 1101 = 2000 mV 0010 = 400 mV 1000 = 800 mV 1110 = 2200 mV 1111 = Do not use 0011 = 400 mV 1001 = 900 mV 0100 = 400 mV 1010 = 1400 mV 0101 = 500 mV 1011 = 1600 mV • For S2_R2 settings 0100, 0111, 1101-1111, the response is a resistor connected on the DPOUT/DMOUT to GND or VBUS. The S2_R2MAG bits specify the resistor value: 0000 = 1.8 k 0110 = 40 k 1100 = 100 k 0001 = 10 k 0111 = 43 k 1101 = 120 k 0010 = 15 k 1000 = 50 k 1110 = 150 k 0011 = 20 k 1001 = 60 k 1111 = Do not use 0100 = 25 k 1010 = 75 k 0101 = 30 k 1011 = 80 k • For S2_R2 settings 0110, 1001, 1100, the response is a voltage divider applied from VBUS to GND with the center tap at DPOUT/DMOUT. The S2_R2MAG bits specify the minimum resistance of the voltage divider (Sum of R1 + R2): 0000 = 93 k 0110 = 200 k 1100 = 200 k 0001 = 100 k 0111 = 200 k 1101 = 200 k 0010 = 125 k 1000 = 93 k 1110 = 200 k 0011 = 150 k 1001 = 100 k 1111 = Do not use 0100 = 200 k 1010 = 125 k 0101 = 200 k 1011 = 150 k DS20005334B-page 72  2014-2018 Microchip Technology Inc. UCS81003 REGISTER 10-29: PRELOADED EMULATION STIMULUS 2 CONFIGURATION 2 REGISTER (ADDRESS 36H) (CONTINUED) bit 3-0 Note 1: 2: S2_R2: Defines the stimulus response as shown below. 0000 = Remove previous response on DPOUT and DMOUT 0001 = Apply voltage on DPOUT (Note 1). 0010 = Apply voltage on DMOUT (Note 2). 0011 = Apply voltage on DPOUT and DMOUT. 0100 = Connect resistor from DPOUT to GND (Note 1). 0101 = Do not use. 0110 = Connect voltage divider from VBUS to GND with the center tap at DPOUT (Note 1). 0111 = Connect resistor form DMOUT to GND (Note 2). 1000 = Do not use. 1001 = Connect voltage divider from VBUS to GND with the center tap at DMOUT (Note 2). 1010 = Connect  200resistor from DPOUT to DMOUT. 1011 = Do not use. 1100 = Connect voltage divider from VBUS to GND with the center tap at DPOUT and DMOUT. 1101 = Connect resistor from DPOUT to GND and DMOUT to GND. 1110 = If STIM2 = 000, the 15 kpull-down resistors applied to DPOUT and DMOUT during Emulation Reset are not removed. If STIM2 = 111, the 15 kpull-down resistors applied to DPOUT and DMOUT during Emulation Reset are removed. For all other STIM2 settings, whatever is applied is not changed. 1111 = Same as 1110 case above. If STIM2 = 000b and no other response is applied to the DPOUT pin, the 15 k pull-down resistor applied to the DPOUT pin during Emulation Reset is not removed. Otherwise, the previous response is left on the DPOUT pin (if applicable) or the 15 k pull-down resistor is removed. If STIM2 = 000b and no other response is applied to the DMOUT pin, the 15 k pull-down resistor applied to the DMOUT pin during Emulation Reset is not removed. Otherwise, the previous response is left on the DMOUT pin (if applicable) or the 15 k pull-down resistor is removed. REGISTER 10-30: PRELOADED EMULATION STIMULUS 2 CONFIGURATION 3 REGISTER (ADDRESS 37H)(Note 1) U-x U-x — — R-0 R-0 R-0 S2_PUPD R-0 R-0 R-0 S2_TH bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-6 Unimplemented bit 5-4 S2_PUPD: Determines the magnitude of the pull-down current applied on the DPOUT and DMOUT pins when the stimulus response is to apply a voltage and the voltage magnitude is set at pull-down (0000b). The bit decode is as follows: 00 = 10 µA 01 = 50 µA 10 = 100 µA 11 = 150 µA  2014-2018 Microchip Technology Inc. DS20005334B-page 73 UCS81003 REGISTER 10-30: PRELOADED EMULATION STIMULUS 2 CONFIGURATION 3 REGISTER (ADDRESS 37H)(Note 1) (CONTINUED) bit 3-0 Note 1: S2_TH: Defines the threshold value as shown below for the specified stimulus. If the stimulus VBUS voltage is ready to be applied or applied (that is, STIM2 = 000b or 111b), the threshold value is ignored. 0000 = 400 mV 0001 = 400 mV 0010 = 400 mV 0011 = 300 mV 0100 = 400 mV 0101 = 500 mV 0110 = 600 mV 0111 = 700 mV 1000 = 800 mV 1001 = 900 mV 1010 = 1400 mV 1011 = 1600 mV 1100 = 1800 mV 1101 = 2000 mV 1110 = 2200 mV 1111 = Do not use. The Legacy charger emulation profiles do not use these settings. Whenever a Legacy charger emulation profile is applied within the DCE Cycle, these controls are not updated and must be ignored. These settings are only used by the BC1.2 CDP and DCP charger emulation profiles. REGISTER 10-31: PRELOADED EMULATION STIMULUS 2 CONFIGURATION 4 REGISTER (ADDRESS 38H)(Note 1) U-x U-x U-x U-x U-x — — — — — R-1 R-0 R-0 S2_RATIO bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-3 Unimplemented bit 2-0 S2_RATIO: Determines the voltage divider ratio as shown below when the stimulus response is set to connect a voltage divider (that is, S2_R2 = 0110b, 1001b, or 1100b). 000 = 0.25 001 = 0.33 010 = 0.4 011 = 0.5 100 = 0.54 101 = 0.6 110 = 0.66 111 = Do not use. Note 1: The BC1.2 DCP and CDP charger emulation profiles do not use this control. Whenever the BC1.2 CDP or DCP charger emulation profile is applied, these controls are not updated and must be ignored. These settings are only used by the Legacy charger emulation profiles. DS20005334B-page 74  2014-2018 Microchip Technology Inc. UCS81003 REGISTER 10-32: PRELOADED EMULATION STIMULUS 3 CONFIGURATION 1 REGISTER (ADDRESS 39H) U-x R-0 — S3_TD_TYPE R-0 R-0 R-0 R-0 S3_TD R-0 R-0 STIM3 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 Unimplemented bit 6 S3_TD_TYPE: Determines the behavior of the stimulus timer. 1 = The stimulus timer controls how long the response is applied after the stimulus is detected. The response is immediately applied and held for the duration of the timer, and then removed if the stimulus is removed. 0 = The stimulus timer is a delay from when the stimulus is detected until the response is performed. bit 5-3 S3_TD: Determines the Stimulus 3 tSTIM_DEL value as shown below. 000 = 0 ms 001 = 1 ms 010 = 5 ms 011 = 10 ms 100 = 20 ms 101 = 40 ms 110 = 80 ms 111 = 100 ms bit 2-0 STIM3: Determines the Stimulus 3 that is used as shown below. Note that the lower threshold for the window comparator option is fixed at 400 mV (UCS81003AM), or 470 mV (UCS81003AB), and only applies to the DPOUT pin. This setting cannot be used for the DMOUT port. 000 = VBUS voltage ready to be applied before port power switch is closed. Next stimulus does not wait for this to be removed. 001 = DPOUT voltage is greater than the threshold (S3_TH). 010 = Window comparator. DPOUT voltage is less than the threshold (S3_TH) and DPOUT voltage greater than the fixed threshold. 011 = DMOUT voltage is greater than the threshold (S3_TH). 100 = Do not use. 101 = Do not use. 110 = DPOUT voltage is greater than the threshold (S3_TH). 111 = Voltage is present after the port power switch is closed. Next stimulus does not wait for this to be removed.  2014-2018 Microchip Technology Inc. DS20005334B-page 75 UCS81003 REGISTER 10-33: PRELOADED EMULATION STIMULUS 3 CONFIGURATION 2 REGISTER (ADDRESS 3AH) R-0 R-0 R-0 R-0 R-0 S3_R3MAG R-0 R-0 R-0 S3_R3 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-4 x = Bit is unknown S3_R3MAG: Determines the magnitude of the response to the stimulus. The bit decode changes meaning based on which response is selected. Data written to any field that is identified as “Do not use” is not accepted. The data is not updated and the settings remain set at the previous value. • For S3_R3 settings 0000-0011, the response is a voltage applied on the DPOUT/DMOUT pins. The S3_R3MAG bits specify the voltage relative to ground. 0000 = Pull Down 0110 = 600 mV 1100 = 1800 mV 0001 = 400 mV 0111 = 700 mV 1101 = 2000 mV 0010 = 400 mV 1000 = 800 mV 1110 = 2200 mV 0011 = 400 mV 1001 = 900 mV 1111 = Do not use 0100 = 400 mV 1010 = 1400 mV 0101 = 500 mV 1011 = 1600 mV • For S3_R3 settings 0100, 0111, 1101-1111, the response is a resistor connected on the DPOUT/DMOUT to GND or VBUS. The S3_R3MAG bits specify the resistor value. 0000 = 1.8 k 0110 = 40 k 1100 = 100 k 0001 = 10 k 0111 = 43 k 1101 = 120 k 0010 = 15 k 1000 = 50 k 1110 = 150 k 0011 = 20 k 1001 = 60 k 1111 = Do not use 0100 = 25 k 1010 = 75 k 0101 = 30 k 1011 = 80 k • For S3_R3 settings 0110, 1001, 1100, the response is a voltage divider applied from VBUS to GND with the center tap at DPOUT/DMOUT. The S3_R3MAG bits specify the minimum resistance of the voltage divider (Sum of R1 + R2). 0000 = 93 k 0110 = 200 k 1100 = 200 k 0001 = 100 k 0111 = 200 k 1101 = 200 k 0010 = 125 k 1000 = 93 k 1110 = 200 k 0011 = 150 k 1001 = 100 k 1111 = Do not use 0100 = 200 k 1010 = 125 k 0101 = 200 k 1011 = 150 k DS20005334B-page 76  2014-2018 Microchip Technology Inc. UCS81003 REGISTER 10-33: PRELOADED EMULATION STIMULUS 3 CONFIGURATION 2 REGISTER (ADDRESS 3AH) (CONTINUED) bit 3-0 Note 1: 2: S3_R3: Defines the stimulus response as shown below. 0000 = Remove previous response on DPOUT and DMOUT 0001 = Apply voltage on DPOUT (Note 1). 0010 = Apply voltage on DMOUT (Note 2). 0011 = Apply voltage on DPOUT and DMOUT. 0100 = Connect resistor from DPOUT to GND (Note 1). 0101 = Do not use. 0110 = Connect voltage divider from VBUS to GND with the center tap at DPOUT (Note 1). 0111 = Connect resistor form DMOUT to GND (Note 2). 1000 = Do not use. 1001 = Connect voltage divider from VBUS to GND with the center tap at DMOUT (Note 2). 1010 = Connect  200resistor from DPOUT to DMOUT. 1011 = Do not use. 1100 = Connect voltage divider from VBUS to GND with the center tap at DPOUT and DMOUT. 1101 = Connect resistor from DPOUT to GND and DMOUT to GND. 1110 = If STIM3 = 000, the 15 kpull-down resistors applied to DPOUT and DMOUT during Emulation Reset are not removed. If STIM3 = 111, the 15 kpull-down resistors applied to DPOUT and DMOUT during Emulation Reset are removed. For all other STIM3 settings, whatever is applied is not changed. 1111 = Same as 1110 case above. If STIM3 = 000b and no other response is applied to the DPOUT pin, the 15 k pull-down resistor applied to the DPOUT pin during Emulation Reset is not removed. Otherwise, the previous response is left on the DPOUT pin (if applicable) or the 15 k pull-down resistor is removed. If STIM3 = 000b and no other response is applied to the DMOUT pin, the 15 k pull-down resistor applied to the DMOUT pin during Emulation Reset is not removed. Otherwise, the previous response is left on the DMOUT pin (if applicable) or the 15 k pull-down resistor is removed. REGISTER 10-34: PRELOADED EMULATION STIMULUS 3 CONFIGURATION 3 REGISTER (ADDRESS 3BH)(Note 1) U-x U-x — — R-0 R-0 R-0 S3_PUPD R-0 R-0 R-0 S3_TH bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-6 Unimplemented bit 5-4 S3_PUPD: Determines the magnitude of the pull-down current applied on the DPOUT and DMOUT pins when the stimulus response is to apply a voltage and the voltage magnitude is set at pull-down (0000b). The bit decode is as follows: 00 = 10 µA 01 = 50 µA 10 = 100 µA 11 = 150 µA  2014-2018 Microchip Technology Inc. DS20005334B-page 77 UCS81003 REGISTER 10-34: PRELOADED EMULATION STIMULUS 3 CONFIGURATION 3 REGISTER (ADDRESS 3BH)(Note 1) (CONTINUED) bit 3-0 Note 1: S3_TH: Defines the threshold value as shown below for the specified stimulus. If the stimulus is VBUS voltage is ready to be applied or applied (that is, STIM3 = 000b or 111b), the threshold value is ignored. 0000 = 400 mV 0001 = 400 mV 0010 = 400 mV 0011 = 300 mV 0100 = 400 mV 0101 = 500 mV 0110 = 600 mV 0111 = 700 mV 1000 = 800 mV 1001 = 900 mV 1010 = 1400 mV 1011 = 1600 mV 1100 = 1800 mV 1101 = 2000 mV 1110 = 2200 mV 1111 = Do not use. The Legacy charger emulation profiles do not use these settings. Whenever a Legacy charger emulation profile is applied within the DCE Cycle, these controls are not updated and must be ignored. These settings are only used by the BC1.2 CDP and DCP charger emulation profiles. 10.13 Custom Emulation Configuration Registers Bits Address Cof Default Custom Emulation Config 8 40h R/W 01h Custom Emulation Stimulus 1 – Config 1 8 41h R/W 00h Custom Emulation Stimulus 1 – Config 2 8 42h R/W 00h Custom Emulation Stimulus 1 – Config 3 8 43h R/W 00h Custom Emulation Stimulus 1 – Config 4 8 44h R/W 00h Custom Emulation Stimulus 2 – Config 1 8 45h R/W 00h Custom Emulation Stimulus 2 – Config 2 8 46h R/W 00h Custom Emulation Stimulus 2 – Config 3 8 47h R/W 00h Custom Emulation Stimulus 2 – Config 4 8 48h R/W 00h Custom Emulation Stimulus 3 – Config 1 8 49h R/W 00h Custom Emulation Stimulus 3 – Config 2 8 4Ah R/W 00h Custom Emulation Stimulus 3 – Config 3 8 4Bh R/W 00h Custom Emulation Stimulus 3 – Config 3 8 4Ch R/W 00h Name The Custom Emulation Configuration registers store the values used by the Custom Charger Emulation circuitry. The Custom Charger Emulation profile is set up as three stimuli and the respective responses. The contents of registers 40h to 4Ch are retained in Sleep. DS20005334B-page 78  2014-2018 Microchip Technology Inc. UCS81003 REGISTER 10-35: CUSTOM EMULATION CONFIGURATION REGISTER (ADDRESS 40H) U-x U-x R/W-0 — — CS_TO_DIS R/W-0 R/W-0 CS_EM_TO R/W-0 R-0 R/W-1 CS_FRST RESERVED CSEM_DIS bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-6 Unimplemented bit 5 CS_TO_DIS: Disables the Emulation Timeout timer when the Custom Charger Emulation profile is applied during the DCE Cycle. If the EM_TO_DIS is set, this bit has no effect (Note 1). 1 = The Emulation Timeout timer is disabled when the Custom charger emulation profile is applied during the DCE Cycle. When the Custom charger emulation profile is applied, the UCS81003 constantly monitors the IBUS current. When the IBUS current is greater than IBUS_CHG, regardless of the reason, then the Custom Charger Emulation profile is accepted. If the portable device does not draw more than IBUS_CHG current, then the UCS81003 continues to wait until this bit is cleared. 0 = The Emulation Timeout timer is enabled when the Custom charger emulation profile is applied during the DCE Cycle and the EM_TO_DIS bit is not set. bit 4-3 CS_EM_TO: Determines the tEM_TIMEOUT value as shown below. This is used when the Custom charger emulation profile is used during the DCE Cycle. 00 = 0.8s 01 = 1.6s 10 = 6.4s 11 = 12.8s bit 2 CS_FRST: Disables the Custom charger emulation profile. 1 = The Custom charger emulation profile is the first of the profiles applied during the DCE Cycle. 0 = The Custom charger emulation profile is the last of the profiles applied during the DCE Cycle. bit 1 RESERVED: Do not change. This bit reads as ‘0’ and must not be written to a logic ‘1’. bit 0 CSEM_DIS: Determines whether the Custom charger emulation profile is placed first or last in the DCE Cycle. 1 = The Custom charger emulation profile is not enabled. 0 = The Custom charger emulation profile is enabled. Note 1: If the CS_TO_DIS bit is set and the Custom charger emulation profile is accepted during the DCE cycle, a removal is not detected. To avoid this issue, re-enable the emulation timeout after applying any test profiles and charging with the final profile.  2014-2018 Microchip Technology Inc. DS20005334B-page 79 UCS81003 REGISTER 10-36: CUSTOM EMULATION STIMULUS 1 CONFIGURATION 1 REGISTER (ADDRESS 41H) U-x R/W-0 — CS_S1TYPE R/W-0 R/W-0 R/W-0 R/W--0 CS_S1_TD R/W--0 R/W--0 CS_STIM1 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 Unimplemented bit 6 CS_S1TYPE: Determines the behavior of the stimulus timer. 1 = The stimulus timer controls how long the response is applied after the stimulus is detected. The response is immediately applied and held for the duration of the timer, and then removed if the stimulus is removed. 0 = The stimulus timer is a delay from when the stimulus is detected until the response is performed. bit 5-3 CS_S1_TD: Determines the stimulus 1 tSTIM_DEL value as shown below. 000 = 0 ms 001 = 1 ms 010 = 5 ms 011 = 10 ms 100 = 20 ms 101 = 40 ms 110 = 80 ms 111 =100 ms bit 2-0 CS_STIM1: Determines the Stimulus 1 that is used as shown below. Note that the lower threshold for the window comparator option is fixed at 400 mV (UCS81003AM), or 470 mV (UCS81003AB), and only applies to the DPOUT pin. This setting cannot be used for the DMOUT port. 000 = VBUS voltage ready to be applied before port power switch is closed. Next stimulus does not wait for this to be removed. 001 = DPOUT voltage is greater than the threshold (CS_S1_TH). 010 = Window comparator. DPOUT voltage is lower than the threshold (CS_S1_TH) and DPOUT voltage greater than the fixed threshold. 011 = DMOUT voltage is greater than the threshold (CS_S1_TH). 100 = Do not use. 101 = Do not use. 110 = DPOUT voltage is greater than the threshold (CS_S1_TH). 111 = VBUS voltage is present after port power switch is closed. Next stimulus does not wait for this to be removed. DS20005334B-page 80  2014-2018 Microchip Technology Inc. UCS81003 REGISTER 10-37: CUSTOM EMULATION STIMULUS 1 CONFIGURATION 2 REGISTER (ADDRESS 42H) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CS_S1_R1MAG R/W-0 R/W-0 R/W-0 CS_S1_R1 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-4 x = Bit is unknown CS_S1_R1MAG: Determines the magnitude of the response to the stimulus. The bit decode changes meaning based on which response is selected. Data written to any field that is identified as ‘Do not use’ is not accepted. The data is not updated and the settings remain set at the previous value. • For CS_S1_R1 settings 0000-0011, the response is a voltage applied on the DPOUT/DMOUT pins. The CS_S1_R1MAG bits specify the voltage relative to ground: 0000 = Pull Down 0110 = 600 mV 1100 = 1800 mV 0001 = 400 mV 0111 = 700 mV 1101 = 2000 mV 0010 = 400 mV 1000 = 800 mV 1110 = 2200 mV 0011 = 400 mV 1001 = 900 mV 1111 = Do not use 0100 = 400 mV 1010 = 1400 mV 0101 = 500 mV 1011 = 1600 mV • For CS_S1_R1 settings 0100, 0111, 1101-1111, the response is a resistor connected on the DPOUT/DMOUT to GND or VBUS. The CS_S1_R1MAG bits specify the resistor value: 0000 = 1.8 k 0110 = 40 k 1100 = 100 k 0001 = 10 k 0111 = 43 k 1101 = 120 k 0010 = 15 k 1000 = 50 k 1110 = 150 k 0011 = 20 k 1001 = 60 k 1111 = Do not use 0100 = 25 k 1010 = 75 k 0101 = 30 k 1011 = 80 k • For CS_S1_R1 settings 0110, 1001, 1100, the response is a voltage divider applied from VBUS to GND with the center tap at DPOUT/DMOUT. The CS_S1_R1MAG bits specify the minimum resistance of the voltage divider (Sum of R1 + R2): 0000 = 93 k 0110 = 200 k 1100 = 200 k 0001 = 100 k 0111 = 200 k 1101 = 200 k 0010 = 125 k 1000 = 93 k 1110 = 200 k 0011 = 150 k 1001 = 100 k 1111 = Do not use 0100 = 200 k 1010 = 125 k 0101 = 200 k 1011 = 150 k  2014-2018 Microchip Technology Inc. DS20005334B-page 81 UCS81003 REGISTER 10-37: CUSTOM EMULATION STIMULUS 1 CONFIGURATION 2 REGISTER (ADDRESS 42H) (CONTINUED) bit 3-0 Note 1: 2: CS_S1_R1: Defines the stimulus response as shown below. 0000 = Remove previous response on DPOUT and DMOUT. 0001 = Apply voltage on DPOUT (Note 1). 0010 = Apply voltage on DMOUT (Note 2). 0011 = Apply voltage on DPOUT and DMOUT. 0100 = Connect resistor from DPOUT to GND (Note 1). 0101 = Do not use. 0110 = Connect voltage divider from VBUS to GND with the center tap at DPOUT (Note 1). 0111 = Connect resistor form DMOUT to GND (Note 2). 1000 = Do not use. 1001 = Connect voltage divider from VBUS to GND with the center tap at DMOUT (Note 2). 1010 = Connect  200resistor from DPOUT to DMOUT. 1011 = Do not use. 1100 = Connect voltage divider from VBUS to GND with the center tap at DPOUT and DMOUT. 1101 = Connect resistor from DPOUT to GND and DMOUT to GND. 1110 = If CS_STIM1 = 000, the 15 k pull-down resistors applied to DPOUT and DMOUT during Emulation Reset are not removed. If CS_STIM1 = 111, the 15 kpull-down resistors applied to DPOUT and DMOUT during Emulation Reset are removed. For all other CS_STIM1 settings, whatever is applied is not changed. 1111 = Same as 1110 case above. If CS_STIM1 = 000b and no other response is applied to the DPOUT pin, the 15 k pull-down resistor applied to the DPOUT pin during Emulation Reset is not removed. Otherwise, the previous response is left on the DPOUT pin (if applicable) or the 15 k pull-down resistor is removed. If CS_STIM1 = 000b and no other response is applied to the DMOUT pin, the 15 k pull-down resistor applied to the DMOUT pin during Emulation Reset is not removed. Otherwise, the previous response is left on the DMOUT pin (if applicable) or the 15 k pull-down resistor is removed. REGISTER 10-38: CUSTOM EMULATION STIMULUS 1 CONFIGURATION 3 REGISTER (ADDRESS 43H)(Note 1) U-x U-x — — R/W-0 R/W-0 R/W-0 CS_S1_PUPD R/W-0 R/W-0 R/W-0 CS_S1_TH bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-6 Unimplemented bit 5-4 CS_S1_PUPD: Determines the magnitude of the pull-down current applied on the DPOUT and DMOUT pins when the stimulus response is to apply a voltage and the voltage magnitude is set at pull-down (0000b). The bit decode is given below. 00 = 10 µA 01 = 50 µA 10 = 100 µA 11 = 150 µA DS20005334B-page 82  2014-2018 Microchip Technology Inc. UCS81003 REGISTER 10-38: CUSTOM EMULATION STIMULUS 1 CONFIGURATION 3 REGISTER (ADDRESS 43H)(Note 1) (CONTINUED) bit 3-0 Note 1: CS_S1_TH: Defines the threshold value as shown below for the specified stimulus. If the stimulus is VBUS voltage is ready to be applied or applied (that is, CS_STIM1 = 000b or 111b), the threshold value is ignored. 0000 = 400 mV 0001 = 400 mV 0010 = 400 mV 0011 = 300 mV 0100 = 400 mV 0101 = 500 mV 0110 = 600 mV 0111 = 700 mV 1000 = 800 mV 1001 = 900 mV 1010 = 1400 mV 1011 = 1600 mV 1100 = 1800 mV 1101 = 2000 mV 1110 = 2200 mV 1111 = Do not use. The Legacy charger emulation profiles do not use these settings. Whenever a Legacy charger emulation profile is applied within the DCE Cycle, these controls are not updated and must be ignored. These settings are only used by the BC1.2 CDP and DCP charger emulation profiles. REGISTER 10-39: CUSTOM EMULATION STIMULUS 1 CONFIGURATION 4 REGISTER (ADDRESS 44H)(Note 1) U-x U-x U-x U-x U-x — — — — — R/W-0 R/W-0 R/W-0 CS_S1_RATIO bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-3 Unimplemented bit 2-0 CS_S1_RATIO: Determines the voltage divider ratio as shown below when the stimulus response is set to connect a voltage divider (that is, CS_S1_R1 = 0110b, 1001b, or 1100b). 000 = 0.25 001 = 0.33 010 = 0.4 011 = 0.5 100 = 0.54 101 = 0.6 110 = 0.66 111 = Do not use. Note 1: The BC1.2 DCP and CDP charger emulation profiles do not use this control. Whenever the BC1.2 CDP or DCP charger emulation profile is applied, these controls are not updated and must be ignored. These settings are only used by the Legacy charger emulation profiles.  2014-2018 Microchip Technology Inc. DS20005334B-page 83 UCS81003 REGISTER 10-40: CUSTOM EMULATION STIMULUS 2 CONFIGURATION 1 REGISTER (ADDRESS 45H) U-x R/W-0 — CS_S2TYPE R/W-0 R/W-0 R/W-0 R/W-0 CS_S2_TD R/W-0 R/W-0 CS_STIM2 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 Unimplemented bit 6 CS_S2TYPE: Determines the behavior of the stimulus timer. 1 = The stimulus timer controls how long the response is applied after the stimulus is detected. The response is immediately applied and held for the duration of the timer, and then removed if the stimulus is removed. 0 = The stimulus timer is a delay from when the stimulus is detected until the response is performed. bit 5-3 CS_S2_TD: Determines the Stimulus 2 tSTIM_DEL value as shown below. 000 = 0 ms 001 = 1 ms 010 = 5 ms 011 = 10 ms 100 = 20 ms 101 = 40 ms 110 = 80 ms 111 = 100 ms bit 2-0 CS_STIM2: Determines the Stimulus 2 that is used as shown below. Note that the lower threshold for the window comparator option is fixed at 400 mV (UCS81003AM), or 470 mV (UCS81003AB), and only applies to the DPOUT pin. This setting cannot be used for the DMOUT port. 000 = VBUS voltage ready to be applied before port power switch is closed. Next stimulus does not wait for this to be removed. 001 = DPOUT voltage is greater than the threshold (CS_S2_TH). 010 = Window comparator. DPOUT voltage is less than the threshold (S1_TH) and DPOUT voltage greater than the fixed threshold. 011 = DMOUT voltage is greater than the threshold (CS_S2_TH). 100 = Do not use. 101 = Do not use. 110 = DPOUT voltage is greater than the threshold (CS_S2_TH). 111 = Voltage is present after the port power switch is closed. Next stimulus does not wait for this to be removed. DS20005334B-page 84  2014-2018 Microchip Technology Inc. UCS81003 REGISTER 10-41: CUSTOM EMULATION STIMULUS 2 CONFIGURATION 2 REGISTER (ADDRESS 46H) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CS_S2_R2MAG R/W-0 R/W-0 R/W-0 CS_S2_R2 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-4 x = Bit is unknown CS_S2_R2MAG: Determines the magnitude of the response to the stimulus. The bit decode changes meaning based on which response is selected. Data written to any field that is identified as “Do not use” is not accepted. The data is not updated and the settings remain set at the previous value. • For CS_S2_R2 settings 0000-0011, the response is a voltage applied on the DPOUT/DMOUT pins. The CS_S2_R2MAG bits specify the voltage relative to ground. 0000 = Pull Down 0110 = 600 mV 1100 = 1800 mV 0001 = 400 mV 0111 = 700 mV 1101 = 2000 mV 0010 = 400 mV 1000 = 800 mV 1110 = 2200 mV 0011 = 400 mV 1001 = 900 mV 1111 = Do not use 0100 = 400 mV 1010 = 1400 mV 0101 = 500 mV 1011 = 1600 mV • For CS_S2_R2 settings 0100, 0111, 1101-1111, the response is a resistor connected on the DPOUT/DMOUT to GND or VBUS. The CS_S2_R2MAG bits specify the resistor value. 0000 = 1.8 k 0110 = 40 k 1100 = 100 k 0001 = 10 k 0111 = 43 k 1101 = 120 k 0010 = 15 k 1000 = 50 k 1110 = 150 k 0011 = 20 k 1001 = 60 k 1111 = Do not use 0100 = 25 k 1010 = 75 k 0101 = 30 k 1011 = 80 k • For CS_S2_R2 settings 0110, 1001, 1100, the response is a voltage divider applied from VBUS to GND with the center tap at DPOUT/DMOUT. The CS_S2_R2MAG bits specify the minimum resistance of the voltage divider (Sum of R1 + R2). 0000 = 93 k 0110 = 200 k 1100 = 200 k 0001 = 100 k 0111 = 200 k 1101 = 200 k 0010 = 125 k 1000 = 93 k 1110 = 200 k 0011 = 150 k 1001 = 100 k 1111 = Do not use 0100 = 200 k 1010 = 125 k 0101 = 200 k 1011 = 150 k  2014-2018 Microchip Technology Inc. DS20005334B-page 85 UCS81003 REGISTER 10-41: CUSTOM EMULATION STIMULUS 2 CONFIGURATION 2 REGISTER (ADDRESS 46H) (CONTINUED) bit 3-0 Note 1: 2: CS_S2_R2: Defines the stimulus response as shown below. 0000 = Remove previous response on DPOUT and DMOUT 0001 = Apply voltage on DPOUT (Note 1). 0010 = Apply voltage on DMOUT (Note 2). 0011 = Apply voltage on DPOUT and DMOUT. 0100 = Connect resistor from DPOUT to GND (Note 1). 0101 = Do not use. 0110 = Connect voltage divider from VBUS to GND with the center tap at DPOUT (Note 1). 0111 = Connect resistor form DMOUT to GND (Note 2). 1000 = Do not use. 1001 = Connect voltage divider from VBUS to GND with the center tap at DMOUT (Note 2). 1010 = Connect  200resistor from DPOUT to DMOUT. 1011 = Do not use. 1100 = Connect voltage divider from VBUS to GND with the center tap at DPOUT and DMOUT. 1101 = Connect resistor from DPOUT to GND and DMOUT to GND. 1110 = If CS_STIM2 = 000, the 15 k pull-down resistors applied to DPOUT and DMOUT during Emulation Reset are not removed. If CS_STIM2 = 111, the 15 kpull-down resistors applied to DPOUT and DMOUT during Emulation Reset are removed. For all other CS_STIM2 settings, whatever is applied is not changed. 1111 = Same as 1110 case above. If CS_STIM2 = 000b and no other response is applied to the DPOUT pin, the 15 k pull-down resistor applied to the DPOUT pin during Emulation Reset is not removed. Otherwise, the previous response is left on the DPOUT pin (if applicable) or the 15 k pull-down resistor is removed. If CS_STIM2 = 000b and no other response is applied to the DMOUT pin, the 15 k pull-down resistor applied to the DMOUT pin during Emulation Reset is not removed. Otherwise, the previous response is left on the DMOUT pin (if applicable) or the 15 k pull-down resistor is removed. REGISTER 10-42: CUSTOM EMULATION STIMULUS 2 CONFIGURATION 3 REGISTER (ADDRESS 47H)(Note 1) U-x U-x — — R/W-0 R/W-0 R/W-0 CS_S2_PUPD R/W-0 R/W-0 R/W-0 CS_S2_TH bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-6 Unimplemented bit 5-4 CS_S2_PUPD: Determines the magnitude of the pull-down current applied on the DPOUT and DMOUT pins when the stimulus response is to apply a voltage and the voltage magnitude is set at pull-down (0000b). The bit decode is as follows. 00 = 10 µA 01 = 50 µA 10 = 100 µA 11 = 150 µA DS20005334B-page 86  2014-2018 Microchip Technology Inc. UCS81003 REGISTER 10-42: CUSTOM EMULATION STIMULUS 2 CONFIGURATION 3 REGISTER (ADDRESS 47H)(Note 1) (CONTINUED) bit 3-0 Note 1: CS_S2_TH: Defines the threshold value as shown below for the specified stimulus. If the stimulus is VBUS voltage is ready to be applied or applied (that is, CS_STIM2 = 000b or 111b), the threshold value is ignored. 0000 = 400 mV 0001 = 400 mV 0010 = 400 mV 0011 = 300 mV 0100 = 400 mV 0101 = 500 mV 0110 = 600 mV 0111 = 700 mV 1000 = 800 mV 1001 = 900 mV 1010 = 1400 mV 1011 = 1600 mV 1100 = 1800 mV 1101 = 2000 mV 1110 = 2200 mV 1111 = Do not use. The Legacy charger emulation profiles do not use these settings. Whenever a Legacy charger emulation profile is applied within the DCE Cycle, these controls are not updated and must be ignored. These settings are only used by the BC1.2 CDP and DCP charger emulation profiles. REGISTER 10-43: CUSTOM EMULATION STIMULUS 2 CONFIGURATION 4 REGISTER (ADDRESS 48H)(Note 1) U-x U-x U-x U-x U-x — — — — — R/W-0 R/W-0 R/W-0 CS_S2_RATIO bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-3 Unimplemented bit 2-0 CS_S2_RATIO: Determines the voltage divider ratio as shown below when the stimulus response is set to connect a voltage divider (that is, CS_S2_R2 = 0110b, 1001b, or 1100b). 000 = 0.25 001 = 0.33 010 = 0.4 011 = 0.5 100 = 0.54 101 = 0.6 110 = 0.66 111 = Do not use. Note 1: The BC1.2 DCP and CDP charger emulation profiles do not use this control. Whenever the BC1.2 CDP or DCP charger emulation profile is applied, these controls are not updated and must be ignored. These settings are only used by the Legacy charger emulation profiles.  2014-2018 Microchip Technology Inc. DS20005334B-page 87 UCS81003 REGISTER 10-44: CUSTOM EMULATION STIMULUS 3 CONFIGURATION 1 REGISTER (ADDRESS 49H) U-x R/W-0 — CS_S3TYPE R/W-0 R/W-0 R/W-0 R/W-0 CS_S3_TD R/W-0 R/W-0 CS_STIM3 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 Unimplemented bit 6 CS_S3TYPE: Determines the behavior of the stimulus timer. 1 = The stimulus timer controls how long the response is applied after the stimulus is detected. The response is immediately applied and held for the duration of the timer, and then removed if the stimulus is removed. 0 = The stimulus timer is a delay from when the stimulus is detected until the response is performed. bit 5-3 CS_S3_TD: Determines the Stimulus 3 tSTIM_DEL value as shown below. 000 = 0 ms 001 = 1 ms 010 = 5 ms 011 = 10 ms 100 = 20 ms 101 = 40 ms 110 = 80 ms 111 = 100 ms bit 2-0 CS_STIM3: Determines the Stimulus 3 that is used as shown below. Note that the lower threshold for the window comparator option is fixed at 400 mV (UCS81003AM), or 470 mV (UCS81003AB), and only applies to the DPOUT pin. This setting cannot be used for the DMOUT port. 000 = VBUS voltage ready to be applied before port power switch is closed. Next stimulus does not wait for this to be removed. 001 = DPOUT voltage is greater than the threshold (CS_S3_TH). 010 = Window comparator. DPOUT voltage is lower than the threshold (CS_S3_TH) and DPOUT voltage greater than the fixed threshold. 011 = DMOUT voltage is greater than the threshold (CS_S3_TH). 100 = Do not use. 101 = Do not use. 110 = DPOUT voltage is greater than the threshold (CS_S3_TH). 111 = Voltage is present after the port power switch is closed. Next stimulus does not wait for this to be removed. DS20005334B-page 88  2014-2018 Microchip Technology Inc. UCS81003 REGISTER 10-45: CUSTOM EMULATION STIMULUS 3 CONFIGURATION 2 REGISTER (ADDRESS 4AH) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CS_S3_R3MAG R/W-0 R/W-0 R/W-0 CS_S3_R3 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-4 x = Bit is unknown CS_S3_R3MAG: Determines the magnitude of the response to the stimulus. The bit decode changes meaning based on which response is selected. Data written to any field that is identified as “Do not use” is not accepted. The data is not updated and the settings remain set at the previous value. • For CS_S3_R3 settings 0000-0011, the response is a voltage applied on the DPOUT/DMOUT pins. The CS_S3_R3MAG bits specify the voltage relative to ground. 0000 = Pull Down 0110 = 600 mV 1100 = 1800 mV 0001 = 400 mV 0111 = 700 mV 1101 = 2000 mV 0010 = 400 mV 1000 = 800 mV 1110 = 2200 mV 0011 = 400 mV 1001 = 900 mV 1111 = Do not use 0100 = 400 mV 1010 = 1400 mV 0101 = 500 mV 1011 = 1600 mV • For CS_S3_R3 settings 0100, 0111, 1101-1111, the response is a resistor connected on the DPOUT/DMOUT to GND or VBUS. The CS_S3_R3MAG bits specify the resistor value. 0000 = 1.8 k 0110 = 40 k 1100 = 100 k 0001 = 10 k 0111 = 43 k 1101 = 120 k 0010 = 15 k 1000 = 50 k 1110 = 150 k 0011 = 20 k 1001 = 60 k 1111 = Do not use 0100 = 25 k 1010 = 75 k 0101 = 30 k 1011 = 80 k • For CS_S3_R3 settings 0110, 1001, 1100, the response is a voltage divider applied from VBUS to GND with the center tap at DPOUT/DMOUT. The CS_S3_R3MAG bits specify the minimum resistance of the voltage divider (Sum of R1 + R2). 0000 = 93 k 0110 = 200 k 1100 = 200 k 0001 = 100 k 0111 = 200 k 1101 = 200 k 0010 = 125 k 1000 = 93 k 1110 = 200 k 0011 = 150 k 1001 = 100 k 1111 = Do not use 0100 = 200 k 1010 = 125 k 0101 = 200 k 1011 = 150 k  2014-2018 Microchip Technology Inc. DS20005334B-page 89 UCS81003 REGISTER 10-45: CUSTOM EMULATION STIMULUS 3 CONFIGURATION 2 REGISTER (ADDRESS 4AH) (CONTINUED) bit 3-0 Note 1: 2: CS_S3_R3: Defines the stimulus response as shown below. 0000 = Remove previous response on DPOUT and DMOUT 0001 = Apply voltage on DPOUT (Note 1). 0010 = Apply voltage on DMOUT (Note 2). 0011 = Apply voltage on DPOUT and DMOUT. 0100 = Connect resistor from DPOUT to GND (Note 1). 0101 = Do not use. 0110 = Connect voltage divider from VBUS to GND with the center tap at DPOUT (Note 1). 0111 = Connect resistor form DMOUT to GND (Note 2). 1000 = Do not use. 1001 = Connect voltage divider from VBUS to GND with the center tap at DMOUT (Note 2). 1010 = Connect  200resistor from DPOUT to DMOUT. 1011 = Do not use. 1100 = Connect voltage divider from VBUS to GND with the center tap at DPOUT and DMOUT. 1101 = Connect resistor from DPOUT to GND and DMOUT to GND. 1110 = If CS_STIM3 = 000, the 15 k pull-down resistors applied to DPOUT and DMOUT during Emulation Reset are not removed. If CS_STIM3 = 111, the 15 kpull-down resistors applied to DPOUT and DMOUT during Emulation Reset are removed. For all other CS_STIM3 settings, whatever is applied is not changed. 1111 = Same as 1110 case above. If CS_STIM3 = 000b and no other response is applied to the DPOUT pin, the 15 k pull-down resistor applied to the DPOUT pin during Emulation Reset is not removed. Otherwise, the previous response is left on the DPOUT pin (if applicable) or the 15 k pull-down resistor is removed. If CS_STIM3 = 000b and no other response is applied to the DMOUT pin, the 15 k pull-down resistor applied to the DMOUT pin during Emulation Reset is not removed. Otherwise, the previous response is left on the DMOUT pin (if applicable) or the 15 k pull-down resistor is removed. REGISTER 10-46: CUSTOM EMULATION STIMULUS 3 CONFIGURATION 3 REGISTER (ADDRESS 4BH)(Note 1) U-x U-x — — R/W-0 R/W-0 R/W-0 CS_S3_PUPD R/W-0 R/W-0 R/W-0 CS_S3_TH bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-6 Unimplemented bit 5-4 CS_S3_PUPD: Determines the magnitude of the pull-down current applied on the DPOUT and DMOUT pins when the stimulus response is to apply a voltage and the voltage magnitude is set at pull-down (0000b). The bit decode is as follows. 00 = 10 µA 01 = 50 µA 10 = 100 µA 11 = 150 µA DS20005334B-page 90  2014-2018 Microchip Technology Inc. UCS81003 REGISTER 10-46: CUSTOM EMULATION STIMULUS 3 CONFIGURATION 3 REGISTER (ADDRESS 4BH)(Note 1) (CONTINUED) bit 3-0 Note 1: CS_S3_TH: Defines the threshold value as shown below for the specified stimulus. If the stimulus is VBUS voltage is ready to be applied or applied (that is, CS_STIM3 = 000b or 111b), the threshold value is ignored. 0000 = 400 mV 0001 = 400 mV 0010 = 400 mV 0011 = 300 mV 0100 = 400 mV 0101 = 500 mV 0110 = 600 mV 0111 = 700 mV 1000 = 800 mV 1001 = 900 mV 1010 = 1400 mV 1011 = 1600 mV 1100 = 1800 mV 1101 = 2000 mV 1110 = 2200 mV 1111 = Do not use. The Legacy charger emulation profiles do not use these settings. Whenever a Legacy charger emulation profile is applied within the DCE Cycle, these controls are not updated and must be ignored. These settings are only used by the BC1.2 CDP and DCP charger emulation profiles. REGISTER 10-47: CUSTOM EMULATION STIMULUS 3 CONFIGURATION 4 REGISTER (ADDRESS 4CH)(Note 1) U-x U-x U-x U-x U-x — — — — — R/W-0 R/W-0 R/W-0 CS_S3_RATIO bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-3 Unimplemented bit 2-0 CS_S3_RATIO: Determines the voltage divider ratio as shown below when the stimulus response is set to connect a voltage divider (that is, CS_S3_R3 = 0110b, 1001b, or 1100b). 000 = 0.25 001 = 0.33 010 = 0.4 011 = 0.5 100 = 0.54 101 = 0.6 110 = 0.66 111 = Do not use Note 1: The BC1.2 DCP and CDP charger emulation profiles do not use this control. Whenever the BC1.2 CDP or DCP charger emulation profile is applied, these controls are not updated and must be ignored. These settings are only used by the Legacy charger emulation profiles.  2014-2018 Microchip Technology Inc. DS20005334B-page 91 UCS81003 10.14 Current Limiting Behavior Configuration Registers Name Bits Address Cof Default Applied Current Limiting Behavior 8 50h R 82h Custom Current Limiting Behavior Config 8 51h R/W 82h 10.14.1 APPLIED CURRENT LIMITING BEHAVIOR REGISTER The Applied Current Limiting Behavior Register stores the values used by the applied current limiting mode (Trip or CC) when the custom settings are not used. The contents of this register are automatically updated when charger emulation is completed. REGISTER 10-48: APPLIED CURRENT LIMITING BEHAVIOR REGISTER (ADDRESS 50H) R-1 R-0 U-x SEL_VBUS_MIN — R-0 R-0 R-0 SEL_R2_IMIN R-1 R-0 RESERVED bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 SEL_VBUS_MIN: Define the VBUS_MIN voltage as follows: 00 = 1.5V 01 = 1.75V 10 = 2.0V 11 = 2.25V bit 5 Unimplemented bit 4-2 SEL_R2_IMIN: Define the IBUS_R2MIN current as follows: 000 = 120 mA 001 = 570 mA 010 = 1000 mA 011 = 1350 mA 100 = 1680 mA 101 = 2050 mA bit 1-0 RESERVED: Do not change. Note 1: x = Bit is unknown The values specified above are the typical ones. DS20005334B-page 92  2014-2018 Microchip Technology Inc. UCS81003 10.14.2 CUSTOM CURRENT LIMITING BEHAVIOR CONFIGURATION REGISTER The Custom Current Limiting Behavior Configuration Register enables programming of current limit parameters. These controls are used when a portable device handshakes using the Legacy charger emulation profiles (except Legacy 3), the Custom charger emulation profile, or does not handshake as a dedicated charger (that is, a power thief). The contents of this register are retained in Sleep. REGISTER 10-49: CUSTOM CURRENT LIMITING BEHAVIOR CONFIG REGISTER (ADDRESS 51H) R/W-1 R/W-0 U-x CS_VBUS_MIN — R/W-0 R/W-0 R/W-0 CS_R2_IMIN R/W-1 R/W-0 RESERVED bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-6 CS_VBUS_MIN: Defines the Custom VBUS_MIN voltage as shown below. Note that VBUS_MIN is checked even when operating with Trip Current Limiting. 00 = 1.5V 01 = 1.75V 10 = 2.0V 11 = 2.25V bit 5 Unimplemented bit 4-2 CS_R2_IMIN: Define the Custom IBUS_R2MIN threshold as shown below. The default is 120 mA. This value is used under the following conditions: when a portable device handshakes using the Legacy charger emulation profiles (except Legacy 3) the Custom charger emulation profile, or when it does not handshake in DCE Cycle (that is, a power thief). Under these conditions, the current limiting mode is determined by the relative value of IBUS_R2MIN and ILIM. When IBUS_R2MIN < ILIM or ILIM > 1.68 A, Trip Current Limiting used; otherwise, CC mode is used. Define the IBUS_R2MIN current as follows. 000 = 120 mA 001 = 570 mA 010 = 1000 mA 011 = 1350 mA 100 = 1680 mA 101 = 2050 mA bit 1-0 RESERVED: Do not change. Note 1: The values specified above are the typical ones.  2014-2018 Microchip Technology Inc. DS20005334B-page 93 UCS81003 10.15 Product ID Register Name Product ID Bits Address Cof Default 8 FDh R 4Eh The Product ID register stores a unique 8-bit value that identifies the UCS device family. 10.16 Manufacturer ID Register Name Manufacturer ID Bits Address Cof Default 8 FEh R 5Dh The Manufacturer ID register stores a unique 8-bit value that identifies Microchip Technology Inc. 10.17 Revision Register Name Revision Bits Address Cof Default 8 FFh R 82h The Revision register stores an 8-bit value that represents the part revision. DS20005334B-page 94  2014-2018 Microchip Technology Inc. UCS81003 11.0 COMMUNICATIONS 11.1 Operating Mode Note: The UCS81003 can operate in SMBus mode (see Section 11.2 “SMBus Operating Mode”) or StandAlone mode (see Section 11.3 “Stand-Alone Operating Mode”). The resistor on the COMM_SEL/ILIM pin determines the operating mode and the hardware-set ILIM setting as shown in Table 11-1. Unless connected to GND or VDD, the resistors in Table 11-1 are pull-down resistors. TABLE 11-1: If it is necessary to connect the COMM_SEL/ILIM pin to VDD via a pull-up resistor, it is recommended that this resistor value does not exceed 100 k. UCS81003 COMMUNICATION MODE AND ILIM SELECTION (Note 1) SELECTION Resistor ±5% ILIM Setting Communications Mode GND 570 mA SMBus – see Section 11.2.1.2 10 k pull-down resistor 1000 mA SMBus – see Section 11.2.1.2 12 k pull-down resistor 1130 mA SMBus – see Section 11.2.1.2 15 k pull-down resistor 1350 mA SMBus – see Section 11.2.1.2 18 k pull-down resistor 1680 mA SMBus – see Section 11.2.1.2 22 k pull-down resistor 2050 mA SMBus – see Section 11.2.1.2 27 kpull-down resistor 2280 mA SMBus – see Section 11.2.1.2 33 k pull-down resistor 2850 mA (3000 mA maximum) SMBus – see Section 11.2.1.2 47 k pull-down resistor 570 mA Stand-Alone mode 56 k pull-down resistor 1000 mA Stand-Alone mode 68 k pull-down resistor 1130 mA Stand-Alone mode 82 k pull-down resistor 1350 mA Stand-Alone mode 100 k pull-down resistor 1680 mA Stand-Alone mode 120 k pull-down resistor 2050 mA Stand-Alone mode 150 k pull-down resistor 2280 mA Stand-Alone mode VDD (If a pull-up resistor is used, its value must not exceed 100 k.) 2850 mA (3000 mA maximum) Stand-Alone mode Note 1: 11.2 Unless otherwise indicated, the values specified in this table are the typical ILIM in Table 1-2. SMBus Operating Mode When the COMM_SEL/ILIM pin is directly connected to ground or though a pull-down resistor with a value of 33 k or below as listed in Table 11-1, the UCS81003 communicates via the SMBus or I2C communications protocols.  2014-2018 Microchip Technology Inc. Note 1: Upon power-up, the UCS81003 does not respond to any SMBus communications for 5.5 ms. After this time, full functionality is available. 2: When in the Sleep state, the first SMBus read command sent to the UCS81003 device address wakes it. Any data sent to the UCS81003 is ignored and any data read from the UCS81003 must be considered invalid. The UCS81003 is fully functional 3 ms after this first read command is sent. See Section 5.1.2 “Sleep State Operation”. DS20005334B-page 95 UCS81003 11.2.1 SYSTEM MANAGEMENT BUS In SMBus mode, the UCS81003 communicates with a host controller. The SMBus is a 2-wire serial communication protocol between a computer host and its peripheral devices. A detailed timing diagram is shown in Figure 11-1. Stretching of the SMCLK signal is supported; however, the UCS81003 does not stretch the clock signal. THIGH TLOW THD:STA T SU:STO T FALL SMCLK T RISE THD:STA TSU:DAT THD:DAT T SU:STA SMDATA TBUF P S FIGURE 11-1: 11.2.1.1 P - Stop Condition P SMBus Timing Diagram. SMBus Start Bit The SMBus Start bit is defined as a transition of the SMBus data line from a logic ‘1’ state to a logic ‘0’ state while the SMBus clock line is in a logic ‘1’ state. 11.2.1.2 S S - Start Condition The SMBus address is determined based on the resistor connected on the SEL pin as shown in Table 11-2. Note: SMBus Address and RD/WR Bit If it is necessary to connect the SEL pin to VDD via a resistor, the pull-up resistor may be any value up to 100 k. The SMBus Address Byte consists of the 7-bit client address followed by the RD/WR indicator bit. If this RD/WR bit is a logic ‘0’, the SMBus host is writing data to the client device. If this RD/WR bit is a logic ‘1’, the SMBus host is reading data from the client device. TABLE 11-2: SEL PIN DECODE Resistor (±5%) PWR_EN Polarity SMBus Address GND Active-Low 1010_111(r/w) 10 k pull-down resistor Active-Low 1010_110(r/w) 12 k pull-down resistor Active-Low 1010_101(r/w) 15 k pull-down resistor Active-Low 1010_100(r/w) 18 k pull-down resistor Active-Low 0110_000(r/w) 22 k pull-down resistor Active-Low 0110_001(r/w) 27 k pull-down resistor Active-Low 0110_010(r/w) 33 k pull-down resistor Active-Low 0110_011(r/w) 47 k pull-down resistor Active-High 0110_011(r/w) 56 k pull-down resistor Active-High 0110_010(r/w) 68 k pull-down resistor Active-High 0110_001(r/w) 82 k pull-down resistor Active-High 0110_000(r/w) 100 k pull-down resistor Active-High 1010_100(r/w) 120 k pull-down resistor Active-High 1010_101(r/w) 150 k pull-down resistor Active-High 1010_110(r/w) VDD (If a pull-up resistor is used, its value must not exceed 100 k) Active-High 1010_111(r/w) DS20005334B-page 96  2014-2018 Microchip Technology Inc. UCS81003 11.2.1.3 SMBus Data Bytes All SMBus data bytes are sent most significant bit first and composed of eight bits of information. 11.2.1.4 SMBus ACK and NACK Bits The SMBus client acknowledges all data bytes that it receives. This is done by the client device pulling the SMBus data line low after the 8th bit of each byte that is transmitted. This applies to both the Write Byte and Block Write protocols. By holding the SMBus data line high after the 8th data bit is sent, the host NACK (not acknowledge) the last data byte received from the client. For the Block Read protocol, the host ACK each data byte that it receives except the last data byte. 11.2.1.5 SMBus Stop Bit The SMBus Stop bit is defined as a transition of the SMBus data line from a logic ‘0’ state to a logic ‘1’ state while the SMBus clock line is in a logic ‘1’ state. When the UCS81003 detects an SMBus Stop bit, and communicates with the SMBus protocol, it resets its client interface and prepares to receive further communications. 11.2.1.6 SMBus Timeout and Idle Reset The UCS81003 includes an SMBus timeout feature. If the clock is held at logic ‘0’ for tTIMEOUT, the device can timeout and reset the SMBus interface. The SMBus interface can also reset if both the clock and data lines are held at a logic ‘1’ for tIDLE_RESET. Communication is restored with a Start condition. This functionality defaults to disabled and can be enabled by clearing the DIS_TO bit in the Emulation Configuration register (Register 10-9).  2014-2018 Microchip Technology Inc. 11.2.2 SMBUS AND I2C COMPATIBILITY The major differences between SMBus and I2C devices are highlighted in this section. For more information, refer to the SMBus 2.0 and I2C specifications. • UCS81003 supports I2C fast mode at 400 kHz. This covers the SMBus maximum time of 100 kHz. • Minimum frequency for SMBus communications is 10 kHz. • The SMBus client protocol resets if the clock is held at a logic ‘0’ for longer than 30 ms. This time-out functionality is disabled by default in the UCS81003 and can be enabled by clearing the DIS_TO bit. I2C does not have a timeout. • Except when operating in Sleep mode, the SMBus client protocol resets if both the clock and data lines are held at a logic ‘1’ for longer than 200 µs (idle condition). This function is disabled by default in the UCS81003 device and can be enabled by clearing the DIS_TO bit. I2C does not have an idle condition. • I2C devices do not support the Alert Response Address functionality (optional for SMBus). • I2C devices support block read and write differently. I2C protocol enables for unlimited number of bytes to be sent in either direction. The SMBus protocol requires that an additional data byte indicating number of bytes to read/write is transmitted. The UCS81003 only supports I2C formatting. DS20005334B-page 97 UCS81003 11.2.3 SMBUS PROTOCOLS 11.2.3.1 The UCS81003 is SMBus 2.0-compatible and supports Write Byte, Read Byte, Send Byte, and Receive Byte as valid protocols as shown in the following sections. SMBus Write Byte The Write Byte is used to write one byte of data to a specific register as shown in Table 11-4. All protocols in these sections use the convention in Table 11-3. TABLE 11-3: PROTOCOL FORMAT Data Sent to Device Data Sent to the Host Data sent Data sent TABLE 11-4: WRITE BYTE PROTOCOL START Client Address WR ACK Register Address ACK Register Data ACK STOP 1 ->0 YYYY_YYY 0 0 XXh 0 XXh 0 0 -> 1 11.2.3.2 SMBus Read Byte The Read Byte protocol is used to read one byte of data from the registers as shown in Table 11-5. TABLE 11-5: READ BYTE PROTOCOL START Client Address WR ACK Register Address ACK START Client Address RD ACK Register Data NACK STOP 1->0 YYYY_YYY 0 0 XXh 0 1 ->0 YYYY_YYY 1 0 XXh 1 0 -> 1 11.2.3.3 SMBus Send Byte The Send Byte protocol is used to set the internal address register pointer to the correct address location. No data is transferred during the Send Byte protocol as shown in Table 11-6. TABLE 11-6: SEND BYTE PROTOCOL START Client Address WR ACK Register Address ACK STOP 1 -> 0 YYYY_YYY 0 0 XXh 0 0 -> 1 11.2.3.4 SMBus Receive Byte The Receive Byte protocol is used to read data from a register when the internal register address pointer is known to be at the right location (for example, set via Send Byte). This is used for consecutive reads of the same register as shown in Table 11-7. TABLE 11-7: RECEIVE BYTE PROTOCOL START CLIENT ADDRESS RD ACK Register Data NACK STOP 1 -> 0 YYYY_YYY 1 0 XXh 1 0 -> 1 DS20005334B-page 98  2014-2018 Microchip Technology Inc. UCS81003 I2C PROTOCOLS 11.2.4 The UCS81003 supports I2C Block Read and Block Write. The protocols listed below use the convention in Table 11-3. 11.2.4.1 Block Write The Block Write is used to write multiple data bytes to a group of contiguous registers as shown in Table 11-8. Note: When using the Block Write protocol, the internal address pointer is automatically incremented after every data byte is received. It wraps from FFh to 00h. TABLE 11-8: BLOCK WRITE PROTOCOL START Client Address WR ACK Register Address ACK Register Data ACK 1 ->0 YYYY_YYY 0 0 XXh 0 XXh 0 Register Data ACK Register Data ACK ... Register Data ACK STOP XXh 0 XXh 0 ... XXh 0 0 -> 1 11.2.4.2 Block Read The Block Read is used to read multiple data bytes from a group of contiguous registers as shown in Table 11-9. Note: When using the Block Read protocol, the internal address pointer is automatically incremented after every data byte is received. It wraps from FFh to 00h. TABLE 11-9: BLOCK READ PROTOCOL START Client Address WR ACK Register Address 1->0 YYYY_YYY 0 0 ACK Register Data 0 XXh Register ACK Data 0 XXh  2014-2018 Microchip Technology Inc. ACK START Client Address XXh 0 1 ->0 YYYY_YYY ACK Register Data ACK ... 0 XXh 0 ... RD ACK Register Data 1 0 XXh Register NACK Data XXh 1 STOP 0 -> 1 DS20005334B-page 99 UCS81003 11.3 Stand-Alone Operating Mode Stand-Alone mode enables the UCS81003 to operate without active SMBus/I2C communications. StandAlone mode can be enabled by connecting a pull-down resistor greater or equal to 47 k on the COMM_SEL/ILIM pin as shown in Table 11-1. When the device is configured to operate in StandAlone mode, the fault handling and Attach Detection controls are determined via the LATCH and S0 pins as shown in Table 11-10. Note: If it is necessary to connect the S0 or LATCH pins to VDD via a pull-up resistor, the pull-up resistor value must be 100 k in order to guarantee VIH specification. Similarly, if it is necessary to connect the S0 or LATCH pins to GND via a pull-down resistor, the pull-down resistor value must be 100 k in order to guarantee VIL specification. TABLE 11-10: STAND-ALONE FAULT AND ATTACH DETECTION SELECTION Latch Pin S0 Pin Command Low Low No Attach Detection. Auto-Recovery upon error detection. Low High Attach Detection in the Detect power state. Auto-Recovery upon error detection. High Low No Attach Detection. Error states are Latched and require host to change PWR_EN control to recover from Error state. High High Attach Detection in the Detect power state. Error states are Latched and require host to change PWR_EN control to recover from Error state. In the Stand-Alone operating mode, communications from and to the UCS81003 are limited to the PWR_EN, EM_EN, M2, M1, ALERT#, and A_DET# pins. DS20005334B-page 100  2014-2018 Microchip Technology Inc. UCS81003 12.0 PACKAGING INFORMATION 12.1 Package Marking Information 28-Lead VQFN (5x5x0.9 mm) 81003AM NNNYWW TYWWNNNA Legend: Y WW NNN e3 * Note: Example 81003AM C64C1A415 T415C64A e3 KR ^^ Year code (last digit of calendar year) Week code (week of January 1 is week ‘01’) Alphanumeric traceability code Package Country of origin Pb-free JEDEC® designator for Matte Tin (Sn) This package is Pb-free. The Pb-free JEDEC designator ( e3 ) can be found on the outer packaging for this package. In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information.  2014-2018 Microchip Technology Inc. DS20005334B-page 101 UCS81003 28-Lead Very Thin Plastic Quad Flat Pack, No Lead Package (PV) 5x5 mm Body [VQFN] With Rectangular Exposed Pad Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 2X 0.10 C A D D1 4X CH A B E1 E N 1 NOTE 1 2 (DATUM B) (DATUM A) 2X 0.10 C B 2X 0.10 C B 2X 0.10 C A TOP VIEW A1 0.10 C C SEATING PLANE A 28X (A3) SIDE VIEW 0.10 0.05 C C A B D2 0.10 C A B K NOTE 1 E2 2 1 N 28x b L e BOTTOM VIEW 0.10 0.05 C A B C Microchip Technology Drawing C04-334A Sheet 1 of 2 DS20005334B-page 102  2014-2018 Microchip Technology Inc. UCS81003 28-Lead Very Thin Plastic Quad Flat Pack, No Lead Package (PV) 5x5 mm Body [VQFN] With Rectangular Exposed Pad Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Units Dimension Limits Number of Terminals N e Pitch A Overall Height Standoff A1 (A3) Terminal Thickness D Overall Width Molded Cap Width D1 Exposed Pad Width D2 Overall Length E Molded Cap Length E1 Exposed Pad Length E2 Corner Chamfer CH b Terminal Width Terminal Length L K Terminal-to-Exposed-Pad MIN 0.80 0.00 2.50 2.80 0.24 0.18 0.50 0.20 MILLIMETERS NOM 28 0.50 BSC 0.85 0.01 0.20 REF 5.00 BSC 4.75 BSC 2.60 5.00 BSC 4.75 BSC 2.90 0.42 0.23 0.60 - MAX 0.90 0.05 2.70 3.00 0.60 0.30 0.70 - Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. Package is punch singulated 3. Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. Microchip Technology Drawing C04-334A Sheet 2 of 2  2014-2018 Microchip Technology Inc. DS20005334B-page 103 UCS81003 28-Lead Very Thin Plastic Quad Flat, No Lead Package (PV) - 5x5 mm Body [VQFN] With Rectangular Exposed Pad Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging C1 X2 EV 28 1 2 ØV C2 Y2 EV (G1) Y1 X1 SILK SCREEN E RECOMMENDED LAND PATTERN Units Dimension Limits E Contact Pitch Optional Center Pad Width X2 Optional Center Pad Length Y2 Contact Pad Spacing C1 Contact Pad Spacing C2 Contact Pad Width (X28) X1 Contact Pad Length (X28) Y1 (G1) Contact Pad to Center Pad (X28) Thermal Via Diameter V Thermal Via Pitch EV MIN MILLIMETERS NOM 0.50 BSC MAX 2.70 3.00 4.70 4.70 0.30 1.05 0.475 REF 0.30 1.00 Notes: 1. Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. Microchip Technology Drawing C04-2334A DS20005334B-page 104  2014-2018 Microchip Technology Inc. UCS81003 APPENDIX A: REVISION HISTORY Revision B (June 2018) • Added the specifications for UCS81003AB. • Corrected minor typographical errors and applied formatting changes throughout the document. Revision A (September 2014) • Original release of this document.  2014-2018 Microchip Technology Inc. DS20005334B-page 105 UCS81003 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. Device Device: [X](1) -XXX Tape and Reel Examples: a) UCS81003AM-C1A: Package UCS81003AM: UCS81003AB: Automotive USB Port Power Controller with Charger Emulation, automatic VBUS discharge at power-up, 400 mV lower threshold for the window comparator on the DPOUT pin. Automotive USB Port Power Controller with Charger Emulation, without automatic VBUS discharge at power-up, 470 mV lower threshold for the window comparator on the DPOUT pin. 28-pin, 5x5 VQFN LeadFree ROHS Compliant Package. b) UCS81003AMR-C1A: Tape and Reel, 28-pin, 5x5 VQFN LeadFree ROHS Compliant Package. Note 1: Tape and Reel identifier only appears in the catalog part number description. This identifier is used for ordering purposes and is not printed on the device package. Check with your Microchip sales office for package availability for the Tape and Reel option. Tape and Reel Option: Blank = Standard packaging (tube or tray) R Package: = Tape and Reel(1) C1A = Very Thin Plastic Quad Flat, No Lead Package – 5x5 mm Body with Rectangular Exposed Pad, 28-Lead (VQFN) DS20005334B-page 106  2014-2018 Microchip Technology Inc. Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. • Microchip is willing to work with the customer who is concerned about the integrity of their code. • Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer’s risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights unless otherwise stated. Microchip received ISO/TS-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified. QUALITY MANAGEMENT SYSTEM CERTIFIED BY DNV Trademarks The Microchip name and logo, the Microchip logo, AnyRate, AVR, AVR logo, AVR Freaks, BitCloud, CryptoMemory, CryptoRF, dsPIC, FlashFlex, flexPWR, Heldo, JukeBlox, KeeLoq, Kleer, LANCheck, LINK MD, maXStylus, maXTouch, MediaLB, megaAVR, MOST, MOST logo, MPLAB, OptoLyzer, PIC, picoPower, PICSTART, PIC32 logo, Prochip Designer, QTouch, SAM-BA, SpyNIC, SST, SST Logo, SuperFlash, tinyAVR, UNI/O, and XMEGA are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. ClockWorks, The Embedded Control Solutions Company, EtherSynch, Hyper Speed Control, HyperLight Load, IntelliMOS, mTouch, Precision Edge, and Quiet-Wire are registered trademarks of Microchip Technology Incorporated in the U.S.A. Adjacent Key Suppression, AKS, Analog-for-the-Digital Age, Any Capacitor, AnyIn, AnyOut, BodyCom, chipKIT, chipKIT logo, CodeGuard, CryptoAuthentication, CryptoAutomotive, CryptoCompanion, CryptoController, dsPICDEM, dsPICDEM.net, Dynamic Average Matching, DAM, ECAN, EtherGREEN, InCircuit Serial Programming, ICSP, INICnet, Inter-Chip Connectivity, JitterBlocker, KleerNet, KleerNet logo, memBrain, Mindi, MiWi, motorBench, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient Code Generation, PICDEM, PICDEM.net, PICkit, PICtail, PowerSmart, PureSilicon, QMatrix, REAL ICE, Ripple Blocker, SAM-ICE, Serial Quad I/O, SMART-I.S., SQI, SuperSwitcher, SuperSwitcher II, Total Endurance, TSHARC, USBCheck, VariSense, ViewSpan, WiperLock, Wireless DNA, and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. Silicon Storage Technology is a registered trademark of Microchip Technology Inc. in other countries. GestIC is a registered trademarks of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in other countries. All other trademarks mentioned herein are property of their respective companies. © 2014-2018, Microchip Technology Incorporated, All Rights Reserved. ISBN: 978-1-5224-3199-2 == ISO/TS 16949 ==  2014-2018 Microchip Technology Inc. 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