UPD360T-B/6HX

UPD360 Highly Integrated Small Form Factor USB Type-C™ Power Delivery 2.0 Port Controller Highlights • Small Form Factor 4 x 4 mm 44-WFBGA Package • Integrated Analog Discrete Components Reduce Bill of Materials and Design Footprint • USB Power Delivery 2.0 Compliant MAC • USB Type-CTM (1) Connector Support with Connection Detection and Control • I2C/SPI (2) Interface for CPU/SoC Communication • USB Type-C™ Alternate Mode Support • Dual Role Power (DRP) and Role Swap Support Target Applications • • • • • • • • Notebook Computers All-in-One/Desktop PCs Smartphones Tablets Monitors Docking Stations HDTVs Printers Key Benefits • Integrated Analog Discrete Components - VCONN FETs with Rp/Rd Switching - Dead Battery Rd termination - Programmable Current Sense for Overcurrent Conditions - Voltage Sense for Overvoltage Conditions • Integrated 5V/3A Port Power Controller (PPC) - Supports up to 5V/3A on VBUS - Supplies 500mA, 900mA, 1.5A, and 3.0A per USB Type-C™ Specification • Integrated 3.3V Power Switch - Provides Dead Battery Support - Automatically Switch between VBUS and Main +3.3V 1. USB Type-C™ and USB-C™ are trademarks of USB Implementers Forum. • USB Power Delivery MAC - Compliant with USB Power Delivery Specification Revision 2.0 - Power Delivery Packet Framing - CRC Checking/Generation - 4B/5B Encoding/Decoding - BMC Encoding/Decoding - EOP/SOP Generation for PD Frames - SOP Detection and SOP Header Processing - Separate RX/TX FIFOs - Automatic GoodCRC Message Generation - Automatic Retry Generation - Error Handling - Low Standby Power Support via Sleep State • USB Type-C Cable Detect Logic - Auto Cable Attach & Orientation Detection - Routes Baseband Communication to Respective CC Pin per Detected Orientation - VCONN Supply Control for Active Cable - Configurable Downstream Facing Port (DFP) and Upstream Facing Port (UFP) Modes - Charging Current Capability Detection - Detection of Debug Accessory Mode, Audio Adapter Accessory Mode • +1.8V I2C (1 MHz) Interface Supports Communication/Configuration via Companion CPU/SoC • Alternate Mode Support - DisplayPortTM, ThunderboltTM, and other Major Protocols • CFG_SEL0 Pin for Selection of Device Mode • CFG_SEL1 Pin for Selection of I2C addresses (2) • Power and I/Os - Integrated 1.8V Voltage Regulator - 16 Configurable General Purpose I/O Pins • Software - C Libraries • Package - 44-ball WFBGA (4 x 4 x 0.7 mm) • Environmental - Commercial Temperature Range (0°C to +70°C) 2. Available only in select UPD360 configurations.  2016-2017 Microchip Technology Inc. DS00002084C-page 1 UPD360 TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced. If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via E-mail at docerrors@microchip.com. We welcome your feedback. Most Current Documentation To obtain the most up-to-date version of this documentation, please register at our Worldwide Web site at: http://www.microchip.com You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page. The last character of the literature number is the version number, (e.g., DS30000000A is version A of document DS30000000). Errata An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of silicon and revision of document to which it applies. To determine if an errata sheet exists for a particular device, please check with one of the following: • Microchip’s Worldwide Web site; http://www.microchip.com • Your local Microchip sales office (see last page) When contacting a sales office, please specify which device, revision of silicon and data sheet (include -literature number) you are using. Customer Notification System Register on our web site at www.microchip.com to receive the most current information on all of our products. DS00002084C-page 2  2016-2017 Microchip Technology Inc. UPD360 Table of Contents 1.0 Preface ............................................................................................................................................................................................ 4 2.0 Introduction ..................................................................................................................................................................................... 7 3.0 Ball Descriptions and Configuration ................................................................................................................................................ 9 4.0 Register Map ................................................................................................................................................................................. 19 5.0 I2C Slave Controller (UPD360-A/UPD360-B Only) ....................................................................................................................... 20 6.0 SPI Slave Controller (UPD360-C Only) ........................................................................................................................................ 26 7.0 Clocks, Resets, and Power Management ..................................................................................................................................... 31 8.0 System Control ............................................................................................................................................................................. 35 9.0 Cable Plug Orientation and Detection ........................................................................................................................................... 68 10.0 Baseband CC Interface (BCI) ................................................................................................................................................... 107 11.0 Power Delivery MAC ................................................................................................................................................................. 111 12.0 USB Port Power Controller (PPC) ............................................................................................................................................ 171 13.0 Power Switch ............................................................................................................................................................................ 182 14.0 DisplayPort Hot Plug Detect (HPD) .......................................................................................................................................... 195 15.0 Watchdog Timer (WDT) ............................................................................................................................................................ 202 16.0 Operational Characteristics ....................................................................................................................................................... 206 17.0 Package Information ................................................................................................................................................................. 214 Appendix A: Data Sheet Revision History ......................................................................................................................................... 217 The Microchip Web Site .................................................................................................................................................................... 218 Customer Change Notification Service ............................................................................................................................................. 218 Customer Support ............................................................................................................................................................................. 218 Product Identification System ........................................................................................................................................................... 219  2016-2017 Microchip Technology Inc. DS00002084C-page 3 UPD360 1.0 PREFACE 1.1 Glossary of Terms TABLE 1-1: GLOSSARY OF TERMS Term Definition ADC Analog to Digital Converter AFE Analog Front End BCI Baseband CC Interface Billboard USB Billboard Device. A required USB device class for UFPs which support Alternate Modes in order to provide product information to the USB Host. BIST Built-In Self Test BMC Bi-phase Mark Coding Byte 8-bits CC Generic reference to USB Type-C™ Cable / Connector CC1/CC2 pins CSR Control and Status Register DB Dead Battery DFP Downstream Facing Port (USB Type-C™ Specification definition) DP DisplayPort (a VESA standard interface) DPM Device Policy Manager (PD Specification definition) DRP Dual Role Power (USB Type-C™ Specification definition) DWORD 32-bits EC Embedded Controller EP USB Endpoint FIFO First In First Out buffer FW Firmware FS Full-Speed Host External system (Includes processor, application software, etc.) HPD Hot-Plug Detect functionality as defined by DisplayPort and DisplayPort Alternate Mode specifications HS High-Speed HW Hardware (Refers to function implemented by the device) IC Integrated Circuit IFC InterFrame Gap LDO Linear Drop-Out regulator MAC Media Access Controller Microchip Microchip Technology Incorporated N/A Not Applicable OCS Over-Current Sense PCS Physical Coding Sublayer PD / UPD USB Power Delivery PIO General Purpose I/O PMIC Power Management Integrated Circuit POR Power-On Reset PRBS Pseudo Random Binary Sequence QWORD 64-bits SA Source Address DS00002084C-page 4  2016-2017 Microchip Technology Inc. UPD360 TABLE 1-1: GLOSSARY OF TERMS (CONTINUED) Term Definition SBU SideBand Use SCSR System Control and Status Register SPM System Policy Manager (PD Specification definition) SS SuperSpeed SVDM Standard/Vendor Defined Message (PD Specification definition) SVID Standard/Vendor IDentity (PD Specification definition) TCPC USB Type-C™ Port Controller UFP Upstream Facing Port (USB Type-C™ Specification definition) USB Universal Serial Bus USB Type-C™ USB Type-C™ Cable / Connector VDO Vendor-defined Object (PD Specification definition) VSM Vendor Specific Messaging WORD 16-bits ZLP Zero Length USB Packet 1.2 Buffer Types TABLE 1-2: BUFFER TYPES Buffer Type IS Description Schmitt-triggered input I2C I2C interface O8 Output with 8 mA sink and 8 mA source OD8 PU Open-drain output with 8 mA sink 70k (typical) internal pull-up. Unless otherwise noted in the pin description, internal pull-ups are always enabled. Note: PD 70k (typical) internal pull-down. Unless otherwise noted in the pin description, internal pulldowns are always enabled. Note: AIO P Internal pull-up resistors prevent unconnected inputs from floating. Do not rely on internal resistors to drive signals external to the device. When connected to a load that must be pulled high, an external resistor must be added. Internal pull-down resistors prevent unconnected inputs from floating. Do not rely on internal resistors to drive signals external to the device. When connected to a load that must be pulled low, an external resistor must be added. Analog bidirectional Power pin Note: Digital signals are not 5V tolerant unless specified. Note: Refer to Section 16.5, "DC Characteristics," on page 208 for the electrical characteristics of the various buffers.  2016-2017 Microchip Technology Inc. DS00002084C-page 5 UPD360 1.3 Register Nomenclature TABLE 1-3: REGISTER NOMENCLATURE Register Bit Type Notation 1.4 Register Bit Description R Read: A register or bit with this attribute can be read. W Write: A register or bit with this attribute can be written. RO Read only: Read only. Writes have no effect. RS Read to Set: This bit is set on read. WO Write only: If a register or bit is write-only, reads will return unspecified data. W1S Write One to Set: Writing a one sets the value. Writing a zero has no effect. W1C Write One to Clear: Writing a one clears the value. Writing a zero has no effect. WC Write Anything to Clear: Writing anything clears the value. LL Latch Low: Clear on read of register. LH Latch High: Clear on read of register. SC Self-Clearing: Contents are self-cleared after the being set. Writes of zero have no effect. Contents can be read. RO/LH Read Only, Latch High: Bits with this attribute will stay high until the bit is read. After it is read, the bit will remain high, but will change to low if the condition that caused the bit to go high is removed. If the bit has not been read, the bit will remain high regardless of a change to the high condition. NASR Not Affected by Software Reset. The state of NASR bits do not change on assertion of a software reset. RESERVED Reserved Field: Reserved fields must be written with zeros, unless otherwise indicated, to ensure future compatibility. The value of reserved bits is not guaranteed on a read. References • NXP I2C-Bus Specification (UM10204, April 4, 2014): www.nxp.com/documents/user_manual/UM10204.pdf • USB Power Delivery and USB Type-C™ Specifications: http://www.usb.org/developers/docs/usb_31_102015.zip • VESA DisplayPort Alternate Mode Specification 1.0: http://www.vesa.org DS00002084C-page 6  2016-2017 Microchip Technology Inc. UPD360 2.0 INTRODUCTION 2.1 General Description The UPD360 is a highly integrated, small form factor USB Type-C Power Delivery (PD) Port Controller designed to adhere to the USB Type-C™ Cable and Connector Specification and USB Power Delivery 2.0 Specification. The UPD360 provides cable plug orientation and detection for a USB Type-C receptacle and implements baseband communication with a partner USB Type-C device via the integrated USB Power Delivery 2.0 MAC. The device can function in Standalone UFP/DFP modes, or utilize the integrated I2C/SPI interface to connect to a companion CPU/SoC (dependent on device version, see Section 2.2, "UPD360 Family Differences Summary"). Additionally, the UPD360 integrates many of the analog discrete components required for USB Type-C PD applications, including two VCONN FETs with Rp/Rd switching, a port power controller that supports up to 5V/3A on VBUS, and current and voltage sense circuitry for over-voltage/current detection. By integrating many of the analog discrete components required for USB Type-C PD applications, the UPD360 provides a low cost, low power, small footprint (4 x 4 mm) solution for consumer (notebooks, desktop PCs, smartphones, tablets, monitors, docking stations) applications. To enable the UPD360 to efficiently support dead battery use cases, an integrated power switch is provided to select between two external 3.3V supplies (VBUS and main). This effectively allows connection detection and system wakeup without external processor intervention (external processor in sleep mode). The UPD360 is also capable of negotiating alternate modes over USB Type-C connectors using the Power Delivery 2.0 protocol. Both DisplayPort and Thunderbolt operation over USB Type-C connectors are supported in addition to other major protocols. A system diagram utilizing the UPD360 is shown in Figure 2-1. An internal block diagram of the UPD360 is shown in Figure 2-2. FIGURE 2-1: SYSTEM BLOCK DIAGRAM I2C/SPI CC1 CC2 Connector Microchip UPD360 TM SoC USB Type‐C VBUS USB Crossbar / Alternate Mode Switches  2016-2017 Microchip Technology Inc. DS00002084C-page 7 UPD360 FIGURE 2-2: INTERNAL BLOCK DIAGRAM Rp‐High CC1 FET Rd FET Mux Mux Rp‐Low CC2 VCONN(5V) Rp‐High Mux Mux Rp‐Low Rd 3V3_ALW Auto Power Switch 3V3_VBUS VCONN(5V) Baseband CC Interface Power Delivery 2.0 MAC 5V/3A Port  Power Controller I2C Controller SPI Controller GPIOs (16x) VBUS VSW 1.8V LDO  Regulator OCS_COMP1 Over‐ Current Detection OCS_COMP2 (UPD360‐A: +1.8V) (UPD360‐B: +3.3V) (UPD360‐C Only) UPD360 I2 C (UPD360‐A/B Only) 2.2 SPI (UPD360‐C Only) GPIO[0:15] (GPIO0 not available  in UPD360‐C) UPD360 Family Differences Summary The UPD360 is available in three versions: • UPD360-A • UPD360-B • UPD360-C A summary of the differences between these versions is provided in Table 2-1. Device specific features that do no pertain to the entire UPD360 family are called out independently throughout this document. For ordering information, refer to the Product Identification System on page 219. TABLE 2-1: UPD360 FAMILY DIFFERENCES Device UPD360-A UPD360-B UPD360-C DS00002084C-page 8 +1.8V I2C Interface +3.3V I2C Interface SPI Interface X Standalone UFP/DFP Mode X X X X  2016-2017 Microchip Technology Inc. UPD360 3.0 BALL DESCRIPTIONS AND CONFIGURATION 3.1 Ball Assignments The ball assignments for the UPD360-A/UPD360-B are detailed in Section 3.1.1, "UPD360-A/UPD360-B Ball Assignments," on page 9. The ball assignments for the UPD360-C are detailed in Section 3.1.1, "UPD360-A/UPD360-B Ball Assignments," on page 9. For information on the differences between the UPD360 family of devices, refer to Section 2.2, "UPD360 Family Differences Summary," on page 8. 3.1.1 UPD360-A/UPD360-B BALL ASSIGNMENTS The device ball diagram for the UPD360-A/UPD360-B can be seen in Figure 3-1. Table 3-1 provides a UPD360-A/ UPD360-B ball assignment table. Ball descriptions are provided in Section 3.2, "Ball Descriptions". FIGURE 3-1: UPD360-A/UPD360-B BALL ASSIGNMENTS (TOP VIEW) 1 2 3 4 5 6 7 A VBUS VS VS NC GPIO13* GPIO 14* GPIO15* B VBUS VBUS_DET GPIO9* GPO10* GPIO11*/ DISCHARGE VDD33IO GPIO12* C CC2 CC2_DB_EN GPIO5 GPIO 8 D CC1 CC1_DB_EN GPIO7 RESET_N E CFG_SEL 0 OCS_COMP1 GPIO4 GPIO 6 F 3V3_ALW PWR_DN VDD33IO IRQ_N CFG_SEL 1 GPO1 GPIO3/HPD G VSW 3V3_VBUS VDD18_CAP I2C_DAT I2C_CLK GPIO0 GPIO 2/ OCS_COMP2 VSS VSS VSS VSS Top of UPD360-A/UPD360-B 44-WFBGA Package *The GPIO[9:15] balls provide alternate functions when in Standalone DFP or Standalone UFP modes .  2016-2017 Microchip Technology Inc. DS00002084C-page 9 UPD360 TABLE 3-1: UPD360-A/UPD360-B BALL ASSIGNMENTS Ball Pin Name Ball Pin Name A1 VBUS D5 VSS A2 VS D6 GPIO7 A3 VS D7 RESET_N A4 NC E1 CFG_SEL0 A5 GPIO13 (Note 3-1) E2 OCS_COMP1 A6 GPIO14 (Note 3-1) E4 VSS GPIO4 A7 GPIO15 (Note 3-1) E6 B1 VBUS E7 GPIO6 B2 VBUS_DET F1 3V3_ALW B3 GPIO9 (Note 3-1) F2 PWR_DN B4 GPO10 (Note 3-1) (Note 3-2) F3 VDD33IO B5 GPIO11/DISCHARGE (Note 3-1) F4 IRQ_N B6 VDD33IO F5 CFG_SEL1 B7 GPIO12 (Note 3-1) F6 GPO1 (Note 3-2) C1 CC2 F7 GPIO3/HPD C2 CC2_DB_EN G1 VSW C4 VSS G2 3V3_VBUS C6 GPIO5 G3 VDD18_CAP C7 GPIO8 G4 I2C_DAT D1 CC1 G5 I2C_CLK D2 CC1_DB_EN G6 GPIO0 D3 VSS G7 GPIO2/OCS_COMP2 Note 3-1 This ball provides alternate functions when in Standalone DFP and Standalone UFP Modes. Refer to Section 3.1.1.1, "UPD360-A/UPD360-B GPIO[9:15] Functions in Standalone DFP/UFP Modes" for additional information. Note 3-2 This general purpose signal can only function as an output and must not be pulled-up externally during RESET_N assertion. DS00002084C-page 10  2016-2017 Microchip Technology Inc. UPD360 3.1.1.1 UPD360-A/UPD360-B GPIO[9:15] Functions in Standalone DFP/UFP Modes When the UPD360-A/UPD360-B is configured in Standalone DFP or Standalone UFP modes, the following GPIO balls are assigned specific alternate functions, as detailed in Table 3-2. TABLE 3-2: ALTERNATE GPIO[9:15] FUNCTIONS IN STANDALONE DFP/UFP MODES I2C Companion Mode Standalone DFP Mode Standalone UFP Mode B3 GPIO9 ORIENTATION ORIENTATION B4 GPO10 ATTACH ATTACH B5 GPIO11 OCS_N GPIO11 B7 GPIO12 PWR_EN SINK_5V_LEGACY_N A5 GPIO13 PWR_CAP0 SINK_5V_1A5_N A6 GPIO14 PWR_CAP1 SINK_5V_3A0_N A7 GPIO15 ERR_RECOVER GPIO15 Ball  2016-2017 Microchip Technology Inc. DS00002084C-page 11 UPD360 3.1.2 UPD360-C BALL ASSIGNMENTS The device ball diagram for the UPD360-C can be seen in Figure 3-2. Table 3-3 provides a UPD360-C ball assignment table. Ball descriptions are provided in Section 3.2, "Ball Descriptions". FIGURE 3-2: UPD360-C BALL ASSIGNMENTS (TOP VIEW) 1 2 3 4 5 6 7 A VBUS VS VS NC GPIO 13 GPIO14 GPIO 15 B VBUS VBUS_DET GPIO 9 GPO10 GPIO11/ DISCHARGE VDD33IO GPIO 12 C CC2 CC2_DB_EN GPIO5 GPIO8 D CC1 CC1_DB_EN GPIO7 RESET _N E CFG_SEL 0 OCS_COMP1 GPIO4 GPIO6 F 3V3_ALW PWR_DN VDD 33IO IRQ_N SPI_CLK GPO1 GPIO3/HPD G VSW 3V3_VBUS VDD18_CAP SPI _DO SPI_DI SPI_CS GPIO 2/ OCS_COMP2 VSS VSS VSS VSS Top of UPD360-C 44-WFBGA Package DS00002084C-page 12  2016-2017 Microchip Technology Inc. UPD360 TABLE 3-3: UPD360-C BALL ASSIGNMENTS Ball Pin Name Ball Pin Name A1 VBUS D5 VSS A2 VS D6 GPIO7 A3 VS D7 RESET_N A4 NC E1 CFG_SEL0 A5 GPIO13 E2 OCS_COMP1 A6 GPIO14 E4 VSS GPIO4 A7 GPIO15 E6 B1 VBUS E7 GPIO6 B2 VBUS_DET F1 3V3_ALW B3 GPIO9 F2 PWR_DN B4 GPO10 (Note 3-3) F3 VDD33IO B5 GPIO11/DISCHARGE F4 IRQ_N B6 VDD33IO F5 SPI_CLK B7 GPIO12 F6 GPO1 (Note 3-3) C1 CC2 F7 GPIO3/HPD C2 CC2_DB_EN G1 VSW C4 VSS G2 3V3_VBUS C6 GPIO5 G3 VDD18_CAP C7 GPIO8 G4 SPI_DO D1 CC1 G5 SPI_DI D2 CC1_DB_EN G6 SPI_CS D3 VSS G7 GPIO2/OCS_COMP2 Note 3-3 This general purpose signal can only function as an output and must not be pulled-up externally during RESET_N assertion.  2016-2017 Microchip Technology Inc. DS00002084C-page 13 UPD360 3.2 Ball Descriptions This sections details the functions of the various device signals. TABLE 3-4: BALL DESCRIPTIONS NAME SYMBOL BUFFER TYPE Configuration Channel 1 CC1 AIO Configuration Channel (CC) used in the discovery, configuration and management of connections across a USB Type-C cable. Refer to Section 9.1, "CC Comparator," on page 68 for additional information. Configuration Channel 2 CC2 AIO Configuration Channel (CC) used in the discovery, configuration and management of connections across a USB Type-C cable. Refer to Section 9.1, "CC Comparator," on page 68 for additional information. CC1 Dead Battery Enable CC1_DB_EN AIO Determines whether CC1 broadcasts Rd pull-down or Hi-Z. Refer to Section 9.6, "Dead Battery," on page 77 for additional information. DESCRIPTION USB Type-C™ Note: CC2 Dead Battery Enable CC2_DB_EN AIO Tie to CC1 if dead battery is supported. Otherwise, tie to ground. Determines whether CC2 broadcasts Rd pull-down or Hi-Z. Refer to Section 9.6, "Dead Battery," on page 77 for additional information. Note: Tie to CC2 if dead battery is supported. Otherwise, tie to ground. I2C Interface (UPD360-A/UPD360-B Only) I2C Clock I2C_CLK I2C I2C clock signal (+1.8V for UPD360-A, +3.3V for UPD360-B) I2C Data I2C_DAT I2C I2C data signal (+1.8V for UPD360-A, +3.3V for UPD360-B) SPI Clock SPI_CLK IS SPI clock. The maximum supported SPI clock frequency is 25 MHz. SPI Data Out SPI_DO O8 SPI output data. SPI Data In SPI_DI IS SPI input data. SPI Chip Enable SPI_CS IS Active low SPI chip enable input. Hot Plug Detect HPD IS/O8 DisplayPort Hot Plug Detection. Refer to Section 14.0, "DisplayPort Hot Plug Detect (HPD)," on page 195 for additional information. Discharge DISCHARGE O8 VBUS Discharge. Enables external VBUS discharge circuit when commanded by USB PD software. SPI Interface Pins (UPD360-C Only) Power Delivery Control DS00002084C-page 14  2016-2017 Microchip Technology Inc. UPD360 TABLE 3-4: BALL DESCRIPTIONS (CONTINUED) NAME SYMBOL BUFFER TYPE Type-C Attach ATTACH O8 DESCRIPTION In the Standalone UFP and Standalone DFP modes (UPD360-A/UPD360-B only), this signal indicates that the USB Type-C receptacles at the near and far end of the cable both have a plug-in. This pin is autonomously driven by the device in DFP standalone mode. 0b: Nothing attached 1b: USB Type-C port has an end-end attached Refer to Section 9.10, "Standalone DFP (UPD360-A/ UPD360-B Only)" and Section 9.11, "Standalone UFP (UPD360-A/UPD360-B Only)"for additional information. Type-C Orientation ORIENTATION O8 Note: Float this signal when unused. Note: This signal is not available in the UPD360-C. In the Standalone UFP and Standalone DFP modes (UPD360-A/UPD360-B only), this signal is used to indicate which CC pin is terminated by the attached DFP/UFP and is autonomously driven by the device in DFP standalone mode. DFP: 0b: CC1 pin is terminated by Rd. 1b: CC2 pin is terminated by Rd. UFP: 0b: CC1 pin is pulled to a higher voltage than CC2. 1b: CC2 pin is pulled to a higher voltage than CC1. Refer to Section 9.10, "Standalone DFP (UPD360-A/ UPD360-B Only)" and Section 9.11, "Standalone UFP (UPD360-A/UPD360-B Only)"for additional information. Over-current sense VBUS Power Enable OCS_N PWR_EN  2016-2017 Microchip Technology Inc. OD8 IS Note: Float this signal when unused. Note: This signal is not available in the UPD360-C. In the Standalone DFP mode (UPD360-A/UPD360-B only), this active-low signal indicates over-current sense. This signal maps to the PPC_INT interrupt. Note: This signal is active-low. Float this signal when unused. Note: This signal is not available in the UPD360-C. In the Standalone DFP mode (UPD360-A/UPD360-B only), this signal is used as a port power switch enable for USB hubs. Note: This signal should be tied to the Power Good signal from the VS supply. Note: Tie this signal to ground when unused. Note: This signal is not available in the UPD360-C. DS00002084C-page 15 UPD360 TABLE 3-4: BALL DESCRIPTIONS (CONTINUED) NAME SYMBOL BUFFER TYPE Power Capability 0 PWR_CAP0 IS In the Standalone DFP mode, these signals define the charging current supported by the device. Power Capability 1 PWR_CAP1 IS 00b: USB 2.0 Default Current 01b: USB 3.0 Default Current 10b: 1.5 A 11b: 3.0 A Error Recovery ERR_RECOVER IS DESCRIPTION Note: It is not valid to change the state of PWR_CAP0 and PWR_CAP1 pins after reset is de-asserted. Note: These signals are not available in the UPD360C. In Standalone DFP mode (UPD360-A/UPD360-B only), this pin determines whether or not the USB Type-C logic shall attempt to auto-recover from an OCS or other error. Sources from either the Port Power Switch or VCONN FET. Note: Sink Legacy Current SINK_5V_LEGACY_N Sink 1.5A Current Sink 3A Current SINK_5V_1A5_N SINK_5V_3A0_N OD8 OD8 OD8 This signal is not available in the UPD360-C. In the Standalone UFP mode (UPD360-A/UPD360-B only), this pin asserts autonomously when a source has been detected that provides legacy USB current. Note: Float this signal when unused. Note: This signal is not available in the UPD360-C. In the Standalone UFP mode (UPD360-A/UPD360-B only), this pin asserts autonomously when a source has been detected that provides 1.5A USB current. Note: Float this signal when unused. Note: This signal is not available in the UPD360-C. In the Standalone UFP mode (UPD360-A/UPD360-B only), this pin asserts autonomously when a source has been detected that provides 3.0A USB current. Note: Float this signal when unused. Note: This signal is not available in the UPD360-C. Miscellaneous Interrupt IRQ_N OD8 Active low interrupt signal. Note: Float this signal when unused. VBUS Detection VBUS_DET AIO Scaled down version of VBUS. Tie this signal to VBUS via a resistor divider. Configuration Select 0 CFG_SEL0 AIO This multi-level configuration signal is sampled after a system reset to select the device’s default mode of operation based on the connected 1% precision resistor value. Refer to Section 9.8.1, "Configuration Selection," on page 81 for additional information. DS00002084C-page 16  2016-2017 Microchip Technology Inc. UPD360 TABLE 3-4: BALL DESCRIPTIONS (CONTINUED) NAME SYMBOL BUFFER TYPE Configuration Select 1 CFG_SEL1 AIO DESCRIPTION This multi-level configuration signal is sampled after a system reset to select the device’s default I2C slave address based on the connected 1% precision resistor value (UPD360-A/UPD360-B only). Refer to Section 9.8.1, "Configuration Selection," on page 81 for additional information. Note: General Purpose I/O 0-15 GPIO0, GPO1, GPIO2, GPIO3, GPIO4, GPIO5, GPIO6, GPIO7, GPIO8, GPIO9, GPO10 IS/O8/ OD8 (PU) This signal is not available in the UPD360-C. The general purpose I/O signals are fully programmable as either a push-pull output, an open-drain output, or a Schmitt-triggered input (except GPO1 and GPO10). A programmable pull-up may optionally be enabled. Note: The GPO1 and GPO10 general purpose signals can only function as outputs and must be kept in a low state coincident with deasserting RESET_N. Note: Tie these signals to ground when unused. Note: External pull-ups and pull-downs shall be placed on GPIO pins to ensure that when in the reset state the inputs to external devices are driven to a valid state. Note: GPIO0 is not available in the UPD360-C. Note: In Standalone DFP/UFP modes (UPD360-A/ UPD360-B only), GPIOs 9-15 have alternate dedicated functions, as defined in Section 3.1.1.1, "UPD360-A/UPD360-B GPIO[9:15] Functions in Standalone DFP/UFP Modes," on page 11. Refer to Section 8.2, "General Purpose I/O," on page 37 for additional information. System Reset RESET_N IS Active low system reset. Note: If this signal is unused, it must be pulled up to VDD33IO. Refer to Section 7.7, "Reset Operation," on page 34 for additional information. Power Down PWR_DN AI When asserted, this signal places the device into the SLEEP state. Note: Tie this signal to ground when unused. Refer to Section 7.2.1, "SLEEP," on page 31 for additional information. Over-Current Sense Comparator 1 OCS_COMP1 AI This pin is used by the integrated OCS comparator to detect for error conditions. Note: Tie this signal to ground when unused. Refer to Section 8.3, "External Over-current Detection," on page 39 for additional information.  2016-2017 Microchip Technology Inc. DS00002084C-page 17 UPD360 TABLE 3-4: BALL DESCRIPTIONS (CONTINUED) NAME SYMBOL BUFFER TYPE Over-Current Sense Comparator 2 OCS_COMP2 AI DESCRIPTION This pin is used by the integrated OCS comparator to detect for error conditions. Note: Tie this signal to ground when unused. Refer to Section 8.3, "External Over-current Detection," on page 39 for additional information. No Connect NC - For proper operation, this pin must be left unconnected. +3.3V Voltage Switch Supply VSW P +3.3V VBUS Supply 3V3_VBUS Power/Ground +3.3V power supply output from the integrated power switch. Note: P +3.3V power supply input derived from VBUS to the integrated power switch. Note: +3.3V Always Supply 3V3_ALW P This pin also provides capacitance for integrated power switch and must be connected to a 1 uF ( 0.85V and < 2.45V. In this configuration the following thresholds are enabled for matching: • CC_THR3 (DFP_ACT_3A0) • CC_THR6 (DFP_UFP_3A0) The value programmed into CCx Debounce Clear Enable Registers (CCx_DBCLR_EN) and CCx Match Enable Registers (CCx_MATCH_EN) would therefore be 0x44. In this case only CC_THR3 would be matched. Bit 3 would be set in both CCx Match Registers (CCx_MATCH) or CCx Change Status Registers (CCx_CHG_STS) after the debounce interval. UFP: Connected to DFP advertising 3.0 A In this case the UFP is connected to a DFP advertising 3.0A. The vRd value measured will be > 1.3V and < 2.04 V. In this configuration the following thresholds are enabled for matching: • UFP_DFP_DEF (CC_THR0) • UFP_DFP_1A5 (CC_THR2) • UFP_DFP_3A0 (CC_THR4) The value programmed into CCx Debounce Clear Enable Registers (CCx_DBCLR_EN) and CCx Match Enable Registers (CCx_MATCH_EN) would therefore be 0x15. In this case all three thresholds would be matched since the value of vRd must exceed CC_THR4 which is 1.23V. Bits 0, 2 and 4 would be set in both CCx Match Registers (CCx_MATCH) or CCx Change Status Registers (CCx_CHG_STS). 9.2 DFP Operation The device implements current sources to advertise current charging capabilities on both CC pins when operating as a DFP. When a UFP connection is established, the current driven across the CC pins creates a voltage across the UFP’s Rd pull-down that can be detected by the integrated CC comparator. The voltages monitored are summarized in Table 94. When connected to an active cable, an alternative pull-down (Ra) appears on the CC pin. The DFP may provide the advertised VBUS power via the integrated Port Power Controller (PPC). The DFP also integrates two 5V FETs for implementing the VCONN function. This is further discussed in Section 9.7, "VCONN Operation". TABLE 9-4: CC1 SOURCE DETECTION CC2 Connection State CC Comparator State VBUS VCONN Open Open Nothing Attached Monitor both CC pins for attach Off Off Rd Open UFP Attached Monitor CC1 for detach On Off Open Rd UFP Attached Monitor CC2 for detach On Off Ra Open Powered Cable, No UFP attached Monitor CC2 for UFP attach. Monitor CC1 for cable detach. Off Off Open Ra Powered Cable, No UFP attached Monitor CC1 for UFP attach. Monitor CC2 for cable detach. Off Off DS00002084C-page 70  2016-2017 Microchip Technology Inc. UPD360 TABLE 9-4: CC1 SOURCE DETECTION (CONTINUED) CC2 Connection State CC Comparator State VBUS VCONN Ra Rd Powered Cable, UFP attached Monitor CC2 for UFP detach. CC1 is not monitored for detach. On On Rd Ra Powered Cable, UFP attached Monitor CC1 for UFP detach. CC2 is not monitored for detach. On On Rd Rd Debug accessory mode attached Monitor both CC pins for detach Off Off Ra Ra Audio accessory mode attached. Monitor both CC pins for detach Off Off 9.2.1 RP CURRENT SOURCES In order to advertise the current charging capabilities of the device via the integrated port power controller or external power circuit, Rp current sources are used. The current source can be selected by software using CC1 RP Value and CC2 RP Value in the CC Control Register (CC_CTL). Table 9-5 summarizes the values supported by the current sources in regards to the programmed value. TABLE 9-5: RP CURRENT SOURCES Current source (1.7V to 5.5V) RPx Value Default USB Power 80 uA +/-20% 01b 1.5A @ 5V 180 uA +/-8% 10b 3.0A @ 5V 330 uA +/-8% 11b DFP Advertisement Disabled 00b The current source coupled with the CC pins for RP advertisement is also used for sampling the CFG_SEL0 and CFG_SEL1 pins. When either of the CFG_SEL0/CFG_SEL1 pins are sampled, current is steered away from the CC pins and no RP value is advertised. See the VBUS Comparator Control field in VBUS Control Register (VBUS_CTL) for further details.  2016-2017 Microchip Technology Inc. DS00002084C-page 71 UPD360 9.2.2 SOURCE ATTACH DETECTION When configured as a Source, the following sections describe the steps that are taken to determine if an attach has occurred: 1. 2. 3. 4. 5. 6. 7. 8. 9. Software accesses the device via I2C/SPI which wakes the device up and enables the 48 MHz oscillator. Software programs the CC Comparator Control to 00b and disables the CC debouncer. Software polls CC_DB_ACTIVE until it reads back to indicate the CC debouncer is inactive. Software programs the Match Debounce Register (MATCH_DEB) as required for the tPDDebounce period. Software programs the VBUS Debounce Register (VBUS_DEB) as required. Software programs the CCx Debounce Clear Enable Registers (CCx_DBCLR_EN) and CCx Match Enable Registers (CCx_MATCH_EN) as required to match the thresholds of interest. Software programs the CCx Sample Enable Registers (CCx_SAMP_EN) and VBUS Match Enable Register (VBUS_MATCH_EN) to detect VBUS VSafe0v Match (VSAFE0V_THR_MATCH). Software enables the CC_MATCH_VLD, CC1_MATCH_CHG and CC2_MATCH_CHG interrupt via CC Interrupt Enable Register (CC_INT_EN). Software enables the VBUS_MATCH_VLD interrupt via the Power Interrupt Enable Register (PWR_INT_EN). Note: Assertion of CC_MATCH_VLD indicates that the initial CC debounce of both CC pins has completed and a valid value is available in the CCx Match Registers (CCx_MATCH). VBUS_MATCH_VLD indicates a valid value is available in the VBUS Match Register (VBUS_MATCH). 10. Software enables IRQ_N assertion by enabling the CC_INT, VBUS_INT and PWR_INT in the Interrupt Enable Register (INT_EN). 11. Software programs the RP current sources via CC1 RP Value and CC2 RP Value in the CC Control Register (CC_CTL). 12. Software programs the CC Threshold x Registers (CC_THRx), if required. 13. Software programs the CC Comparator Control to sample both CC pins and enables the CC debouncer. The CC_DB_ACTIVE bit will assert soon after. 14. Software sets the Clock Control Register (CLK_CTL) to disable all clock sources accept for the keep alive clock. 15. When a UFP is attached an Rd pull-down, or Ra pull-down from active cable, is connected to one of the CC pins. The CC comparator detects this. 16. Changes in state of the CC pin are recorded in the CCx Match Registers (CCx_MATCH) and CCx Change Status Registers (CCx_CHG_STS) after the programmed debounce period. 17. CC_MATCH_VLD and CC1_MATCH_CHG or CC2_MATCH_CHG interrupt assert and CC_INT asserts which in turn asserts IRQ_N pin. Likewise assertion of VBUS_MATCH_VLD causes PWR_INT to assert and also in turn asserts IRQ_N. 18. Software implements a further debounce of the CC match for tCCDebounce in order to detect the attachment. 19. Software must verify, after VBUS_MATCH_VLD assertion, that the VBUS Match Register (VBUS_MATCH) indicates vSafe0v is on VBUS. 20. After an attachment, software programs the device to power VBUS via the integrated PPC, if required. If the power source is external to the device, software configures that source as required. 21. In the event that an active cable is attached, per the CCx Match Registers (CCx_MATCH), VCONN power may be supplied by appropriately setting VCONN1 Control or VCONN2 Control in the VBUS Control Register (VBUS_CTL). 22. CC Communication Select in the CC Control Register (CC_CTL) is set by software to appropriately connect the baseband interface to the CC pin with the Rd pull-down. 23. The DFP may attempt to communicate with attached device utilizing the PD MAC if desired. DS00002084C-page 72  2016-2017 Microchip Technology Inc. UPD360 9.2.3 SOURCE DETACH DETECTION When configured as a source, the detachment of the partner UFP is determined by monitoring the appropriate CC pin (with the Rd pull-down) for a voltage exceeding DFP_UFP_DEF, DFP_UFP_1A5 or DFP_UFP_3A0, depending on the charging current advertised by the device. The following describes the steps that are taken to determine if a detach has occurred when operating in companion mode: APPLICATION NOTE: Software must not look at the CC detect status while a PD contract is in place, even though the Type-C spec permits doing so, in order to avoid false-disconnects in the Attached.SNK state during heavy PD message traffic. APPLICATION NOTE: Software should set a 3A advertisement while it's a source and a PD contract is in place in order to avoid false-disconnects in the Attached.SRC state during heavy PD message traffic; a 1.5A advertisement (even though permitted by the Type-C spec) is not sufficient to avoid this issue due to the lower vOPEN threshold. An exception to this recommendation is when “Collision Avoidance” is implemented. The following steps assume the CC debouncer has previously been used to detect attachment per the prior section. 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. Software accesses the device via I2C/SPI which wakes the device up and enables the 48 MHz oscillator. Software programs the CCx Debounce Clear Enable Registers (CCx_DBCLR_EN) as required to enable per threshold debouncing. Typically this only involves disabling the thresholds not corresponding to vOPEN. Software enables CC1_MATCH_CHG or CC2_MATCH_CHG interrupt via CC Interrupt Enable Register (CC_INT_EN). Software enables IRQ_N via asserting the respective CC_INT bit in the Interrupt Enable Register (INT_EN). Software programs the CC Comparator Control to sample appropriate CC pin. The device samples the respective CC pin while operating off of 20 kHz clock. Changes in state of the CC are reflected in the respective CCx Match Registers (CCx_MATCH) and CCx Change Status Registers (CCx_CHG_STS). CC1_MATCH_CHG, or CC2_MATCH_CHG, interrupt asserts, CC_INT asserts which in turn asserts the IRQ_N pin. Software implements a further debounce of the CC match for tCCDebounce in order to detect the detachment. If VCONN is being supplied, than the VCONN FET shall be disabled in software by appropriately setting the VCONN1 Control or VCONN2 Control in the VBUS Control Register (VBUS_CTL). In this case, software must also discharge VCONN as defined in Section 9.7.1, "VCONN Discharge Programming Model". Software disables the PPC which causes the internal 5V power switch to open if required. Power may have alternatively been provided by external power source. Internal 100 Ohm VBUS discharge switch is closed if required. Discharge switch remains closed until vSafe0V threshold is crossed. If vSafe0V threshold is not crossed within VBUS Off Register (VBUS_OFF) which asserts VBUS Discharge Error interrupt and asserts IRQ_N pin. Note: Occurrence of VBUS Discharge Error interrupt indicates a potentially catastrophic system power issue. 15. Internal discharge switch is opened. 16. The part is configured by software to detect a UFP attach. The 48 MHz oscillator is disabled. Only the keep-alive clock remains enabled.  2016-2017 Microchip Technology Inc. DS00002084C-page 73 UPD360 9.3 UFP Operation When operating as a UFP, the device applies an Rd pull-down on both CC lines and waits for a DFP connection from the assertion of VBUS. The CC comparator is used to determine the advertised current charger capabilities supported by the DFP. 9.3.1 SINK ATTACH DETECTION The following steps illustrate how the device may be programmed to detect an attachment when operating as a Sink. The following discussion does not cover dead-battery cases, which are described in Section 9.6, "Dead Battery". 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. 17. Software accesses the device via I2C/SPI which wakes the device up and enables the 48 MHz oscillator. Software programs the CC Comparator Control to 00b and disables the CC debouncer. Software programs the VBUS Comparator Control to 00b and disables the VBUS debouncer. Software polls CC_DB_ACTIVE and VBUS_DB_ACTIVE until they read back 0b to indicate that the CC debouncer and VBUS debouncer are inactive. Software programs the Match Debounce Register (MATCH_DEB) as required for the tPDDebounce interval. Software programs the CCx Debounce Clear Enable Registers (CCx_DBCLR_EN) as required to match the thresholds of interest. Software programs the CC1 Pull-Down Value and CC2 Pull-Down Value in the CC Control Register (CC_CTL) to advertise trimmed Rd. Software enables CC_MATCH_VLD, CC1_MATCH_CHG or CC2_MATCH_CHG interrupt via the CC Interrupt Enable Register (CC_INT_EN). Assertion of CC_MATCH_VLD indicates that the initial CC debounce of both CC pins has completed and a valid value is available in the CCx Match Registers (CCx_MATCH). Software programs the CCx Debounce Clear Enable Registers (CCx_DBCLR_EN) as required to enable the respective threshold(s) debouncing. Software enables VBUS_INT to detect VBUS by configuring the VBUS Match Register (VBUS_MATCH). Software enables VBUS_MATCH_VLD by configuring the Power Interrupt Enable Register (PWR_INT_EN). Software enables IRQ_N via configured respective bits, for CC_INT, PWR_INT and VBUS_INT, in the Interrupt Enable Register (INT_EN). Software programs the CC Comparator Control to sample both CC pins. Software programs VBUS Comparator/DAC to detect vSafe5V via the VBUS Comparator Control in the VBUS Control Register (VBUS_CTL) and setting VBUS_THR0 and VBUS_THR1 via the VBUS Threshold x Registers (VBUS_THRx). Software turns off all clock sources with the exception of 20 KHz keep-alive clock via Clock Control Register (CLK_CTL) to save power. Upon connection to a partner DFP VBUS is powered to 5V. After the programmed debounce interval, the respective CCx Change Status Registers (CCx_CHG_STS) is updated and the respective CC1_MATCH_CHG or CC2_MATCH_CHG interrupt asserts which in turn asserts CC_INT which in turn asserts IRQ_N. Note: Assertion of CC_MATCH_VLD indicates that the initial CC debounce of both CC pins has completed and a valid value is available in the CCx Match Registers (CCx_MATCH). 18. VBUS is detected by the VBUS_DET comparator and debounced for the period defined by the VBUS Debounce Register (VBUS_DEB). The VBUS_INT interrupt asserts which in turn asserts IRQ_N. Note: Assertion of VBUS_MATCH_VLD indicates that the initial CC debounce of both CC pins has completed and a valid value is available in the VBUS Match Register (VBUS_MATCH). 19. Software must debounce the CC match for tCCDebounce and VBUS for the PD Debounce Register (PD_DEB) in order to detect the attach condition. 20. After attachment, software configures CC Communication Select in the CC Control Register (CC_CTL) to appropriately connect the baseband interface to the CC with the Rp pull-up if PD communication is desired. 21. DFP may communicate with the device. DS00002084C-page 74  2016-2017 Microchip Technology Inc. UPD360 9.3.2 SINK DETACH DETECTION The DFP detach is detected by the removal of VBUS. The VBUS comparator must always be enabled for the UFP to detect this condition. 1. 2. 3. 4. Software programs the VBUS Comparator Control to 00b and disables the VBUS debouncer. Software polls VBUS_DB_ACTIVE until it reads back 0b to indicate that the VBUS debouncer is inactive. Software programs the VBUS Debounce Register (VBUS_DEB) as required. Software programs the CCx Sample Enable Registers (CCx_SAMP_EN) as required to enable the respective threshold(s) debouncing. Software enables VBUS_INT, which is then used to detect VBUS, via the VBUS Match Enable Register (VBUS_MATCH_EN). Software enables IRQ_N by configuring the respective bit for VBUS_INT in the Interrupt Enable Register (INT_EN). 5. 6. Note: VBUS_THR0 and VBUS_THR1 are adjusted via the VBUS Threshold x Registers (VBUS_THRx) to vSafe5V, if required. 7. Software enables the VBUS Comparator/DAC via the VBUS Comparator Control bit in the VBUS Control Register (VBUS_CTL). 8. Software turns off all clock sources with the exception of 20 KHz keep-alive clock via the Clock Control Register (CLK_CTL) to save power. 9. DFP removes VBUS. 10. After the VBUS debounce period, the VBUS Match Register (VBUS_MATCH) and VBUS Change Status Register (VBUS_CHG_STS) are updated. The VBUS_INT interrupt asserts which in turn asserts IRQ_N. 11. Software continues to monitor VBUS to determine if it stays below vSafe5V for a duration of tPdDebounce. 9.4 DRP Operation This section describes a usage of the device for implementing a DRP attach. In this configuration, software utilizes the device to alternate between a Source and Sink advertisement with an interval of tDRP per the USB Type-C Specification. The steps for initially configuring the device to advertise Source capabilities follows the steps defined in Section 9.2.2, "Source Attach Detection". Software must also implement the tDRP timer. If a Sink is not detected within this time, software shall change the device’s role to Sink and again attempt an attach detection. Software accesses the device via I2C/SPI which wakes the device up and enables the 48 MHz oscillator. Software programs the CC Comparator Control to 00b and disables the CC debouncer. Software polls CC_DB_ACTIVE until it reads back to indicate the CC debouncer is inactive. Software programs the Match Debounce Register (MATCH_DEB) as required for the tPDDebounce period. Software programs the CC Threshold x Registers (CC_THRx) if required. Software programs the CCx Debounce Clear Enable Registers (CCx_DBCLR_EN) and CCx Match Enable Registers (CCx_MATCH_EN) as required to match the thresholds of interest. 7. Software enables the CC_MATCH_VLD, CC1_MATCH_CHG and CC2_MATCH_CHG interrupts via the CC Interrupt Enable Register (CC_INT_EN). 8. Software enables IRQ_N assertion by enabling the CC_INT in the Interrupt Enable Register (INT_EN). 9. Software programs the RP current sources via the CC1 RP Value and CC2 RP Value in the CC Control Register (CC_CTL). 10. Software programs the CC Comparator Control to sample both CC pins and enable the CC debouncer. The CC_DB_ACTIVE bit will assert soon after. 11. Software sets the Clock Control Register (CLK_CTL) to disable all clock sources accept for the keep alive clock. 1. 2. 3. 4. 5. 6. Note: Assertion of CC_MATCH_VLD indicates that the initial CC debounce of both CC pins has completed and a valid value is available in the CCx Match Registers (CCx_MATCH). If after time tDRP an attachment is not detected, software shall configure the device to be a Sink and attempt to detect the presence of a Source. This is similar to the steps defined in Section 9.3.1, "Sink Attach Detection". 1. 2. Software accesses the device via I2C/SPI which wakes the device up and enables the 48 MHz oscillator Software programs the CC Comparator Control to 00b and disables the CC debouncer.  2016-2017 Microchip Technology Inc. DS00002084C-page 75 UPD360 3. 4. Software polls CC_DB_ACTIVE until it reads back 0b to indicate that the CC debouncer is inactive. Software programs the CCx Debounce Clear Enable Registers (CCx_DBCLR_EN) as required to match the thresholds of interest. 5. Software programs detection for vSafe5V by setting VBUS_THR0 and VBUS_THR1 in the VBUS Threshold x Registers (VBUS_THRx). The CCx Sample Enable Registers (CCx_SAMP_EN) is programmed debounce these thresholds. 6. Software programs CC1 Pull-Down Value and CC2 Pull-Down Value in the CC Control Register (CC_CTL) to advertise trimmed Rd. 7. Software enables the CC_MATCH_VLD, CC1_MATCH_CHG or CC2_MATCH_CHG interrupts via the CC Interrupt Enable Register (CC_INT_EN). 8. Software enables VBUS_MATCH_VLD by configuring the Power Interrupt Enable Register (PWR_INT_EN). 9. Software enables IRQ_N via the configured respective bits, for CC_INT, PWR_INT and VBUS_INT, in the Interrupt Enable Register (INT_EN). 10. Software programs the CC Comparator Control to sample both CC pins. 11. Software turns off all clock sources with the exception of 20 KHz keep-alive clock via the Clock Control Register (CLK_CTL) to save power. If after time tDRP an attachment is not detected, software shall configure the device to be a Source and attempt to detect the presence of a Sink. Note: Assertion of CC_MATCH_VLD indicates that the initial CC debounce of both CC pins has completed and a valid value is available in CCx Match Registers (CCx_MATCH). Note: Assertion of VBUS_MATCH_VLD indicates that the initial CC debounce of both CC pins has completed and a valid value is available in VBUS Match Register (VBUS_MATCH). 9.5 Collision Avoidance An alternative mode of operation is required to enable the CC detection circuit to facilitate software implementation of collision detection which was incorporated into version 3.0 of the USB PD Specification. In order to avoid message collisions due to asynchronous Messaging (AMS) sent from the Sink, the Source sets Rp to SinkTxOk (3A@5V) to indicate to the Sink that it is OK to initiate an AMS. When the Source wishes to initiate an AMS it sets Rp to SinkTxNG (1.5A@5V). When the Sink detects that Rp is set to SinkTxOk it may initiate an AMS. When the Sink detects that Rp is set to SinkTxNG it shall not initiate an AMS and shall only send Messages that are part of an AMS the Source has initiated. When operating as a Sink, a mechanism is required for quickly determining whether the Source is advertising SinkTxNG or SinkTxOK on Rp. A collision avoidance mechanism exists to enable software to instruct the device to sample only a single threshold on a single CC pin. This results in a cycle through both thresholds taking only 100 us, making it easier for software to meet the timing constraints mandated by SinkTxOk in the specification. Two CCx Sample Enable Registers (CCx_SAMP_EN) are provided to enable software to specify which subsets of the CC thresholds shall be sampled via setting the respective bit. In the case of collision avoidance, only the threshold corresponding to SinkTxOK shall be set on the connected CC pin. This corresponds to UFP_DFP_3A0 (CC_THR4). The CC Comparator Control field in CC Control Register (CC_CTL) shall be set to the CC pin utilized for PD communication. In order to prevent false positive detection of SinkTXOK when a PD packet is being transmitted or received, a debounce value in the order to 7 ms would need to be programmed into Match Debounce Register (MATCH_DEB). Such a large value would impair the ability of software, when operating as Sink, to detect SinkTXOK and transmit a PD message within the time defined in the PD specification by SinkTxTime. The BLK_PD_MSG bit in CC Hardware Control Register (CC_HW_CTL) has been incorporated to handle the above scenario and enable software to program a sub millisecond debounce value. A minimum value of 100 us shall be used for the Match Debounce Register (MATCH_DEB) when using this mode of operation. The below sequence illustrates the steps to enable Collision Avoidance for a Sink. This sequence is used after a connection and PD contract has been established. DS00002084C-page 76  2016-2017 Microchip Technology Inc. UPD360 Note: 1. 2. 3. 4. 5. 6. 7. 8. The units of the Match Debounce Register (MATCH_DEB) is determined by MATCH_DB_UNITS bit in CC Hardware Control Register (CC_HW_CTL). When this bit is clear, the units are 1.6 ms. When this bit is set the units are 100 us. Sink establishes connection with Source and a PD contract is negotiated. Sink wants to transmit AMS to Source. Via the CC Hardware Control Register (CC_HW_CTL), the MATCH_DB_UNITS is set to 1b to utilize 100 us units for the CC match debouncer. The BLK_PD_MSG bit is set to filter PD traffic from the debouncer. Software sets the Match Debounce Register (MATCH_DEB) to 400 us by writing four into the register. Software configures CC_THR4 to enable interrupt assertion via the CCx Match Enable Registers (CCx_MATCH_EN). Software configures CC_THR4 for sampling via the CCx Sample Enable Registers (CCx_SAMP_EN). Via the CC Control Register (CC_CTL), the CC Comparator Control selects the CC pin connected to the Source’s Rp. Software waits for indication that Source’s Rp is SinkTxOK via a match detected on CC_THR4. Software initiates transmission of PD message to Source. APPLICATION NOTE: Software must guarantee that a sufficient gap exists in between consecutively transmitted PD messages to enable the source RP value to settle on the CC line. Studies by USB-IF members have showed the settling time may take in excess of 40 us. 9.6 Dead Battery Two variations of the Rd resistor are implemented: Rd (Dead Battery) and Rd (Trimmed). The CC1_DB_EN and CC2_DB_EN pins exist to determine the operation of the CC pins in dead battery conditions and are to be connected externally via the PCB to the respective CC pin. The CC pins are configured to present either Hi-Z or an untrimmed Rd pull-down resistance when connected to a DFP advertising a pull-up resistance. Figure 9-1 illustrates the configuration for supporting dead battery cases via hair pining CCx_DB_EN and CCx together on the PCB. The UFP pull-up activates the FET in series with RD_DB and enables the untrimmed dead battery pulldown. FIGURE 9-1: CC RD (DEAD BATTERY) UFP DFP Rp CC_DB_ENx CCx RD_TRIM 5.1 KW EN_RD_TRIM EN_RD_DB_N 50 MW RD_DB 5.1 KW Hi-Z Hi-Z Figure 9-2 illustrates operation after the UFP has been powered over VBUS by the DFP. After the device is powered, EN_RD_DB asserts by default to keep the RD_DB pull-down activated.  2016-2017 Microchip Technology Inc. DS00002084C-page 77 UPD360 Upon powering the host CPU, software simultaneously deasserts EN_RD_DB and asserts EN_RD_TRIM. Going forward the device presents RD_TRIM. FIGURE 9-2: CC RD (TRIM) DFP UFP Rp CC_DB_ENx CCx RD_TRIM 5.1 KW 50 MW RD_DB 5.1 KW EN_RD_TRIM EN_RD_DB_N The Rd resistor presented, trimmed or untrimmed, is controlled by the CC1 Pull-Down Value and CC2 Pull-Down Value in the CC Control Register (CC_CTL). These register fields serve the basis for the EN_RD_TRIM and EN_RD_DB_N control signals depicted. 9.7 VCONN Operation VCONN is a 5V supply that is used to power circuitry in the USB Type-C plug, which is required to implement Electronically Marked Cables. By default, the DFP always sources VCONN when connected to an active cable. However, this may be changed by software by using PD VCONN_SWAP. The VCONN FETs are enabled/disabled by software via the VCONN1 Control and VCONN2 Control control bits in the CC Control Register (CC_CTL). In standalone DFP mode, the device independently enables/disables the VCONN FETs. This mode is intended for configurations where no host CPU is available or the CPU is not capable of managing VCONN. The Standalone Operation bit in the CC Hardware Control Register (CC_HW_CTL) enables this mode of operation. APPLICATION NOTE: It is not envisioned to ever enable both FETs simultaneously. VCONN is monitored for an over current condition via an internal monitoring circuit. A VCONN over current condition is recognized when the event persists for a time longer than specified in the VCONN OCS and Back-Drive Debounce Register (VCONN_DEB). VCONN OCS monitoring is enabled via the VCONN OCS Enable bit in the VBUS Control Register (VBUS_CTL). When an over-current VCONN event is detected, the VCONN Discharge Error (VCONN_DISCH_ERR) interrupt in the Power Interrupt Status Register (PWR_INT_STS) asserts. The device may be configured to automatically disable the VCONN FET upon detection of a CC1 Back-Drive Error/CC2 Back-Drive Error or VCONN Discharge Error (VCONN_DISCH_ERR). In the event of the detection of a debounced over-current VCONN event, the enabled VCONN FET will be disabled. The OCS event also results in an automatic disablement of the respective VCONN1 Control and VCONN2 Control control bits in the CC Control Register (CC_CTL). 9.7.1 VCONN DISCHARGE PROGRAMMING MODEL Software may use the following programming model for implementing VCONN discharge when the device is operating as a DFP and a UFP disconnect has been detected. This section does not apply to standalone DFP operation. 1. 2. Software determines the attached UFP has disconnected and disconnects the VCONN FET. Software disables monitoring the CC thresholds corresponding to the attached CC pin. DS00002084C-page 78  2016-2017 Microchip Technology Inc. UPD360 3. 4. The Rp current sources are disabled on both CC pins via CC1 RP Value or CC2 RP Value. The Ra pull-down on the CC pin previously sourcing VCONN is selected via CC1 Pull-Down Value or CC2 PullDown Value. This initiates the VCONN discharge. 5. Software sets the CC threshold 0 to 150 mv (41d), via the CC Threshold x Registers (CC_THRx), which is the VCONN discharge threshold. 6. Software programs 01h into the CCx Debounce Clear Enable Registers (CCx_DBCLR_EN). 7. Software programs 01h into the CCx Match Enable Registers (CCx_MATCH_EN). 8. Software enables CC1_MATCH_CHG or CC2_MATCH_CHG interrupt via the CC Interrupt Enable Register (CC_INT_EN). 9. Via the CC Control Register (CC_CTL), the CC Comparator Control selects the CC pin that was sourcing VCONN. 10. Changes in state of the CC pin are recorded in CCx Match Registers (CCx_MATCH) and CCx Change Status Registers (CCx_CHG_STS) after the programmed debounce period. 11. After VCONN discharges below 150mv, IRQ_N asserts which indicates VCONN has been discharged. IRQ_N assertion of CC_MATCH_VLD with no threshold matches is also indicative of a complete discharge. 12. After the discharge has been completed, the device is in the Unattached.SRC state. Note: Software should implement a timer to indicate a VCONN discharge error. This may be implemented using the General Purpose Timer. While there is no specific requirement in the Type-C specification for a maximum discharge time Note: After the UFP disconnect is detected, firmware must disconnect the VCONN supply within tVconnOff (35 ms) per release 1.1 of the Type-C specification. 9.8 VBUS Detection The device implements a comparator for determining when VBUS is within a programmed range, vSafe5V, or vSafe0v. VBUS is divided down externally via a 1:9 resistor divider to generate VBUS_DET. VBUS_DET is compared with an 8bit threshold generated by an integrated DAC. The comparator is also shared by the CFG_SEL0 and CFG_SEL1 pins which are sampled automatically after a system reset Figure 9-3 illustrates the VBUS_DET circuit. In a typical use case, VBUS_DET thresholds are programmed to track the following voltage ranges as defined in Table 9-6. Note: Table 9-6 illustrates the values of VBUS_DET utilizing +/-1% accurate resistors where R1 is 10K Ohms and R2 is 90 kOhms. FIGURE 9-3: VBUS_DET COMPARATOR VBUS 15 uA ZTC CFG_SEL1 R2 CFG_SEL0 VBUS_DET VBUS_MATCH/ CFG_MATCH 10-bits R1 R3 R4 DAC 20 KHz Clock VBUS and CFG_SEL Threshold Generation Bandgap Reference For a DFP, the VBUS comparator is useful to detect when VBUS is within the desired range per PD negotiations. This is the case when VBUS is generated by a source external to the device.  2016-2017 Microchip Technology Inc. DS00002084C-page 79 UPD360 For a UFP, the VBUS comparator is required to determine when a DFP is attached or detached. It may also use the comparator to determine when VBUS is within a new voltage range negotiated via PD. TABLE 9-6: VBUS DETECTION THRESHOLDS VBUS 20 12 8 5 0.8 Range VBUS_DET 21.5 2.11 18.5 1.82 13.1 1.29 10.9 1.07 8.9 0.88 7.1 0.69 Comments 5.5 0.51 3.67 0.33 vSafe5V 0.8 0.08 vSafe0V If supported, the ranges 8V, 12V and 20V may be programmed in VBUS Threshold 2 and VBUS Threshold 3 registers (see VBUS Threshold x Registers (VBUS_THRx)). Likewise 5V range, vSafe5v, can be programmed in VBUS Threshold 0 and VBUS Threshold 1 registers. The threshold for vSafe0V is programmable via the VBUS VSafe0V Threshold Register (VSAFE0V_THR). VBUS_DET monitoring logic operates off of the 20 KHz oscillator which cycles through each threshold. Including vSafe0v, a total of five values are compared. Results of the comparison adjust the respective bits of the VBUS Match Register (VBUS_MATCH) and VBUS Change Status Register (VBUS_CHG_STS) after a debounce period defined in VBUS Debounce Register (VBUS_DEB). The VBUS Match Register (VBUS_MATCH) indicates when the value on VBUS_DET is higher than the corresponding programmed threshold and can therefore be used to determine is VBUS is in the desired range. A change in the state of the VBUS Match Register (VBUS_MATCH) may trigger assertion of the IRQ_N pin if appropriately configured in the Power Interrupt Status Register (PWR_INT_STS). The VBUS Debounce Clear Enable Register (VBUS_DBCLR_EN) is functionality equivalent to the CCx Debounce Clear Enable Registers (CCx_DBCLR_EN), but it applies to the VBUS debouncer. Software programs the VBUS Debounce Clear Enable Register (VBUS_DBCLR_EN) as required to enable debouncing the thresholds of interest. The following example illustrates the programming model when it is desired to move VBUS from 5V to 20V after PD contract negotiation. Initially the VBUS de-bouncer is enabled and VSafe5v, VBUS_THR0 and VBUS_THR1, is sampled. VBUS_THR2 and VBUS_THR3 have an initial value in excess of 5V such as 25V. See Section 9.12.24 for details on the VBUS_THRx registers. 1. 2. 3. 4. 5. 6. 7. Software programs the VBUS Match Enable Register (VBUS_MATCH_EN) to include new thresholds (VBUS_THR2 and VBUS_THR3). Software programs the VBUS Debounce Clear Enable Register (VBUS_DBCLR_EN) as required to enable per threshold debouncing. Software programs new thresholds for 20V in VBUS_THR2 and VBUS_THR3 (e.g. 18.5V and 21.5V). This operation restarts the VBUS debouncer. Software waits until IRQ_N asserts. Software confirms the VBUS_MATCH_VLD bit is set. Software reads the VBUS Match Register (VBUS_MATCH) and VBUS Change Status Register (VBUS_CHG_STS). If VBUS Change Status Register (VBUS_CHG_STS) is non-zero, software clears the status bits. Note: 8. If no bits are set in the VBUS Match Register (VBUS_MATCH), after VBUS_MATCH_VLD asserts, then the voltage observed on VBUS is less than VSafe0V. Future changes in VBUS results in IRQ_N asserting with VBUS Match Register (VBUS_MATCH) and VBUS Change Status Register (VBUS_CHG_STS) being appropriately updated. DS00002084C-page 80  2016-2017 Microchip Technology Inc. UPD360 9.8.1 CONFIGURATION SELECTION The CFG_SEL0 and CFG_SEL1(UPD360-A/UPD360-B only) pins share the comparator with VBUS as shown in Figure 9-3. Each CFG_SELx pin is connected to a resistor divider, typically pulled up to VDDIO. After a system level reset (POR, RESET_N, Software Reset), both CFG_SELx pins are automatically sampled to configure the device. The CFG_SELx Match Registers (CFG_SELx_MATCH) are updated automatically and the device configures itself accordingly if standalone mode is detected. The various resistor settings for the CFG_SEL0 and CFG_SEL1 pins are detailed in Table 9-7 and Table 9-8, respectively. Note: For additional information on device resets, refer to Section 7.7, "Reset Operation," on page 34. TABLE 9-7: CONFIGURATION SELECT 0 (CFG_SEL0) SETTINGS Resistor (+/-1%) GND Description Standalone DFP / USB58xx/USB59xx Companion DFP Device operates in standalone DFP mode (UPD360-A/UPD360-B only) for applications where an I2C connection to the host is not be present. CFG_SEL0_MATCH Register 0000h The PWR_CAPx pins are used to select the USB Type-C™ current provided. 0.475 K Standalone UFP / USB58xx/USB59xx Companion UFP Device operates in standalone UFP mode (UPD360-A/UPD360-B only) for applications where an I2C connection to the host is not be present. 0001h 0.953 K I2C/SPI Companion Mode A (TBD) 0003h 1.43 K I2C/SPI Companion Mode B (TBD) 0007h 1.87 K I2C/SPI Companion Mode C (TBD) 000Fh 2.37 K I2C/SPI Companion Mode D (TBD) 001Fh 2.87 K I2C/SPI Companion Mode E (TBD) 003Fh 3.32 K I2C/SPI Companion Mode F (TBD) 007Fh 3.83 K I2C/SPI Companion Mode G (TBD) 00FFh 4.22 K I2C/SPI Companion Mode H (TBD) 01FFh 4.75 K I2C/SPI Companion Mode I (TBD) 03FFh 5.23 K I2C/SPI Companion Mode J (TBD) 07FFh 5.62 K I2C/SPI Companion Mode K (TBD) 0FFFh 6.19 K I2C/SPI Companion Mode L (TBD) 1FFFh 6.65 K I2C/SPI Companion Mode M (TBD) 3FFFh 7.15 K I2C/SPI Companion Mode N (TBD) 7FFFh >7.15 K I2C/SPI FFFFh Note: Companion Mode O (TBD) Any CFG_SEL0 value other than GND or 10.5K will select the I2C/SPI Companion mode.  2016-2017 Microchip Technology Inc. DS00002084C-page 81 UPD360 CONFIGURATION SELECT 1 (CFG_SEL1) I2C ADDRESS SETTINGS (UPD360-A/UPD360-B ONLY) TABLE 9-8: Resistor (+/-1%) Description CFG_SEL1_MATCH Register GND I2C Slave Address = 1011_111 0000h 0.475 K I2 C Slave Address = 1011_110 0001h 0.953 K I2C Slave Address = 1011_101 0003h 1.43 K I2 C Slave Address = 1011_100 0007h 1.87 K I2C Slave Address = 1101_011 000Fh 2 2.37 K I C Slave Address = 1101_010 001Fh 2.87 K I2C Slave Address = 1101_001 003Fh 3.32 K I2 C Slave Address = 1101_000 007Fh 3.83 K I2C Slave Address = 1110_111 00FFh 4.22 K I2C Slave Address = 1110_110 01FFh 4.75 K I2C Slave Address = 1110_101 03FFh 5.23 K I2C Slave Address = 1110_100 07FFh 5.62 K I2C Slave Address = 1110_001 0FFFh 6.19 K I2C Slave Address = 1110_011 1FFFh 6.65 K I2C Slave Address = 1110_000 3FFFh 7.15 K I2C Slave Address = 1110_010 7FFFh >7.15 K I2C Slave Address = 1001_000 FFFFh 9.9 Back-Drive Detection Back-drive detection is implemented on both CC pins, which prevents backwards current flow. The back-drive protection circuit is always operational and triggers when VCCx > VS. Detection of the back-drive condition causes the CC1 Back-Drive Error or CC2 Back-Drive Error bits in the Power Interrupt Status Register (PWR_INT_STS) to assert. Hardware supports automatically disabling a VCONN FET on a CC pin in which back-drive was detected after the debounce period specified in the VCONN OCS and Back-Drive Debounce Register (VCONN_DEB). This function is enabled by setting CC Back-Drive Enable in VBUS Control Register (VBUS_CTL). 9.10 9.10.1 Standalone DFP (UPD360-A/UPD360-B Only) OVERVIEW The device supports standalone DFP operation in which no CPU is available to configure the device. A key application for this mode is a USB Type-C DFP companion for the Microchip USB58xx/USB59xx family of USB Hubs. 9.10.2 CONFIGURATION This mode is entered by the appropriate setting of the CFG_SEL0 and CFG_SEL1 pins. The current charge advertised and supplied is defined by the PWR_CAP0 and PWR_CAP1 pins. The device auto configures itself after a system level reset event. APPLICATION NOTE: The Standalone Operation field in CC Hardware Control Register (CC_HW_CTL) may be used to disable standalone operation. DS00002084C-page 82  2016-2017 Microchip Technology Inc. UPD360 9.11 9.11.1 Standalone UFP (UPD360-A/UPD360-B Only) OVERVIEW The device supports standalone UFP operation in which no CPU is available to configure the device. A key application for this mode is a USB Type-C UFP companion for the Microchip USB58xx/USB59xx family of USB Hubs. 9.11.2 CONFIGURATION This mode is entered by the appropriate setting of the CFG_SEL0 and CFG_SEL1 pins. The device auto-configures itself after a system level reset event. APPLICATION NOTE: The Standalone Operation field in the CC Hardware Control Register (CC_HW_CTL) may be used to disable standalone operation.  2016-2017 Microchip Technology Inc. DS00002084C-page 83 UPD360 9.12 Cable Orientation and Detection Registers This section details the cable plug orientation and detection registers. For an overview of the entire device register map, refer to Section 4.0, "Register Map," on page 19. TABLE 9-9: SYSTEM CONTROL AND STATUS REGISTERS MAP Address Register Name (Symbol) 0800h CC Hardware Control Register (CC_HW_CTL) 0803h CC Interrupt Status Register (CC_INT_STS) 0804h CCx Change Status Registers (CCx_CHG_STS) x=1 0805h CCx Change Status Registers (CCx_CHG_STS) x=2 0806h CCx Match Registers (CCx_MATCH) x=1 0807h CCx Match Registers (CCx_MATCH) x=2 0808h VBUS Match Register (VBUS_MATCH) 0809h VBUS Change Status Register (VBUS_CHG_STS) 080Ah Power Interrupt Status Register (PWR_INT_STS) 080Bh Debug Interrupt Status Register (DBG_INT_STS) 080Ch – 0810h Reserved for future expansion 0811h CC Interrupt Enable Register (CC_INT_EN) 0812h CCx Match Enable Registers (CCx_MATCH_EN) x=1 0813h CCx Match Enable Registers (CCx_MATCH_EN) x=2 0814h VBUS Match Enable Register (VBUS_MATCH_EN) 0815h Power Interrupt Enable Register (PWR_INT_EN) 0816h Debug Interrupt Enable Register (DBG_ENT_EN) 0817h Match Debounce Register (MATCH_DEB) 0818h PD Debounce Register (PD_DEB) 0819h VCONN OCS and Back-Drive Debounce Register (VCONN_DEB) 081Ah CCx Debounce Clear Enable Registers (CCx_DBCLR_EN) x=1 081Bh CCx Debounce Clear Enable Registers (CCx_DBCLR_EN) x=2 081Ch VBUS Debounce Clear Enable Register (VBUS_DBCLR_EN) 081Dh CCx Sample Enable Registers (CCx_SAMP_EN) x=1 081Eh CCx Sample Enable Registers (CCx_SAMP_EN) x=2 081Fh Reserved for future expansion 0820h CC Control Register (CC_CTL) 0822h CC Threshold x Registers (CC_THRx) x=0 0824h CC Threshold x Registers (CC_THRx) x=1 0826h CC Threshold x Registers (CC_THRx) x=2 0828h CC Threshold x Registers (CC_THRx) x=3 082Ah CC Threshold x Registers (CC_THRx) x=4 082Ch CC Threshold x Registers (CC_THRx) x=5 082Eh CC Threshold x Registers (CC_THRx) x=6 0830h CC Threshold x Registers (CC_THRx) x=7 0832h CC Debounce Register (CC_DEB) 0834h – 083Fh 0840h Reserved for future expansion VBUS Control Register (VBUS_CTL) 0842h VBUS Threshold x Registers (VBUS_THRx) x=0 0844h VBUS Threshold x Registers (VBUS_THRx) x=1 0846h VBUS Threshold x Registers (VBUS_THRx) x=2 DS00002084C-page 84  2016-2017 Microchip Technology Inc. UPD360 TABLE 9-9: SYSTEM CONTROL AND STATUS REGISTERS MAP (CONTINUED) Address Register Name (Symbol) 0848h VBUS Threshold x Registers (VBUS_THRx) x=3 084Ah VBUS Debounce Register (VBUS_DEB) 084Bh VBUS Off Register (VBUS_OFF) 084Ch VBUS Error Register (VBUS_ERR) 084Dh Reserved for future expansion 084Eh VBUS VSafe0V Threshold Register (VSAFE0V_THR) 0850h CFG_SELx Match Registers (CFG_SELx_MATCH) x=0 0852h CFG_SELx Match Registers (CFG_SELx_MATCH) x=1 0854h CFG_SEL Threshold x Registers (CFG_SEL_THRx) x=0 0856h CFG_SEL Threshold x Registers (CFG_SEL_THRx) x=1 0858h CFG_SEL Threshold x Registers (CFG_SEL_THRx) x=2 085Ah CFG_SEL Threshold x Registers (CFG_SEL_THRx) x=3 085Ch CFG_SEL Threshold x Registers (CFG_SEL_THRx) x=4 085Eh CFG_SEL Threshold x Registers (CFG_SEL_THRx) x=5 0860h CFG_SEL Threshold x Registers (CFG_SEL_THRx) x=6 0862h CFG_SEL Threshold x Registers (CFG_SEL_THRx) x=7 0864h CFG_SEL Threshold x Registers (CFG_SEL_THRx) x=8 0866h CFG_SEL Threshold x Registers (CFG_SEL_THRx) x=9 0868h CFG_SEL Threshold x Registers (CFG_SEL_THRx) x=10 086Ah CFG_SEL Threshold x Registers (CFG_SEL_THRx) x=11 086Ch CFG_SEL Threshold x Registers (CFG_SEL_THRx) x=12 086Eh CFG_SEL Threshold x Registers (CFG_SEL_THRx) x=13 0870h CFG_SEL Threshold x Registers (CFG_SEL_THRx) x=14 0872h CFG_SEL Threshold x Registers (CFG_SEL_THRx) x=15 0874h CFG_SEL Debug Register (CFG_SEL_DBG) 0875h – 0885h Reserved for future expansion 0886h VCONN Discharge Threshold Register (VCONN_DIS_THR) 0888h VCONN Discharge Time Register (VCONN_DIS_TIME) 088Ah – 0BFFh Note: Reserved for future expansion RESERVED address space must not be written under any circumstances. Failure to heed this warning may result in untoward operation and unexpected results.  2016-2017 Microchip Technology Inc. DS00002084C-page 85 UPD360 9.12.1 CC HARDWARE CONTROL REGISTER (CC_HW_CTL) Address: Bits 15:14 0800h Size: 16 bits Description SHORT_DET Type Default R/W 00b Defines behavior in standalone DFP mode for handling the short circuit condition. 0xb: A0 functionality maintained where VBUS short is not checked before initiating VBUS discharge. 10b: Device initiates VBUS discharge only after short circuit condition has been removed. 11b: Device initiates VBUS discharge after short circuit condition has been removed or a time equal to TCYCLE. Note: This field only has meaning for standalone DFP operation. 13 RESERVED RO - 12 BLK_PD_MSG R/W 0b R/W 0b RO 0b RO 0b RO 0b This bit causes the CC debouncer to pause whenever a PD message is detected by the MAC. This applies for both transmit and receive messages. After the message is processed 0b: Disable PD message filtering. 1b: Enable PD message filtering. Note: 11 This must be enabled for collision detection. MATCH_DB_UNITS This bit defines the units of the Match Debounce Register (MATCH_DEB). 0b: Match debounce has units of 1.6 ms. 1b: Match debounce has units of 100 us. Note: 10 1.6 ms is derived from the time to cycle through all thresholds on both CC pins. DEVICE_MODE Indicates the current mode of the device. 0b: Device is in Companion Mode 1b: Device is in Standalone Mode (UPD360-A/UPD360-B only) 9 CC_DB_ACTIVE When this bit reads back 0b, the debouncer is disabled. The CC debouncer is enabled when it reads back 1b. Note: 8 Software may poll this bit to determine when the CC debouncer is disabled, which can be used as a condition for programming a new configuration. DEVICE_STATE Indicates the current state of the device attachment. 0b: Device is not attached 1b: Device is attached DS00002084C-page 86  2016-2017 Microchip Technology Inc. UPD360 Bits Description Type Default 7:6 Power Capability Indicates the charging current capacity of the device as defined by the PWR_CAPx pins. (UPD360-A/UPD360-B only) RO Note 9-2 Detach Threshold Select Defines which CC threshold shall be used for determining a detach when operating as a standalone DFP (UPD360-A/UPD360-B only). R/W Note 9-2 2 Device Role 0b: Device configured as UFP. 1b: Device configured as DFP. R/W Note 9-3 1 RESERVED RO - 0 Standalone Operation 0b: Companion Mode 1b: Standalone mode (UPD360-A/UPD360-B only) R/W Note 9-1 This field only has meaning for configurations where the PWR_CAPx pins are available (UPD360-A/UPD360-B only). 5:3 Note: This bit must not be modified while the CC debouncer is enabled. Standalone mode: This is the mode of operation supported for standalone operation. During standalone operation, the I2C interface may not be available and the host CPU is not capable of managing the UPD360. The following functions can be handled by the internal logic when this bit is set: • VCONN Enabled/Disable • Attach detection and assertion of ATTACH • Detach detection and de-assertion of ATTACH • Orientation detection and assertion/de-assertion of ORIENTATION pin • Enables CC de-bouncer. Note 9-1 Default is 1b when a standalone configuration is selected otherwise the default is 0b. Note 9-2 Default is a function of the PWR_CAP0 and PWR_CAP1 pins, when the configuration supports these pins. Otherwise the default is 0h. Note 9-3 Default is a function of the CFG_SEL0 and CFG_SEL1 pins. When the configuration indicates UFP configuration this bit defaults to 0b. For DFP operation this bit defaults to 1b. When neither UFP or DFP is specified the default shall be 0b.  2016-2017 Microchip Technology Inc. DS00002084C-page 87 UPD360 9.12.2 CC INTERRUPT STATUS REGISTER (CC_INT_STS) Address: Bits 0803h Size: 16 bits Description Type Default 7 CC_MATCH_VLD Asserts after the CC debouncer is first enabled, via CC Comparator Control, and the first match becomes valid in CCx Match Registers (CCx_MATCH). R/WC 0b 6 RP_CHG When operating as a standalone UFP, this interrupt indicates a change in the state of the RP value advertised by the DFP has been detected (UPD360-A/ UPD360-B only). R/WC 0b R/WC 0b R/WC 0b RESERVED RO - CC2_MATCH_CHG Indicates the a change occurred in the state of the respective CCx Change Status Registers (CCx_CHG_STS). RO 0b RO 0b 5 Note: This bit is RO when the device is not configured as a standalone UFP and will always read back 0b. Note: The source of this input is a pulse and does not persist after being cleared. Note: The updated current advertisement is available via the DFP Current Advertisement field in the CC Control Register (CC_CTL). DETACH Indicates a detach event has occurred when the device has been configured to support standalone mode per the Standalone Operation field in the CC Control Register (CC_CTL) (UPD360-A/UPD360-B only). DFP Operation: CC pins are monitored for detecting a detach. UFP Operation: VBUS is monitored for detecting a detach. Note: 4 The source of this input is a pulse and does not persist after being cleared. ATTACH Indicates an attach event has occurred when the device has been configured to support standalone mode per the Standalone Operation field in the CC Control Register (CC_CTL) (UPD360-A/UPD360-B only). DFP Operation: CC pins are monitored for an attach. UFP Operation: CC pins and VBUS are monitored for an attach. Note: 3:2 1 Note: 0 The source of this input is a pulse and does not persist after being cleared. The source of this input is a pulse and does not persist after being cleared. CC1_MATCH_CHG Indicates the a change occurred in the state of the respective CCx Change Status Registers (CCx_CHG_STS). Note: DS00002084C-page 88 The source of this input is a pulse and does not persist after being cleared.  2016-2017 Microchip Technology Inc. UPD360 9.12.3 CCX CHANGE STATUS REGISTERS (CCX_CHG_STS) Address: Bits 7:0 x=1: 0804h x=2: 0805h Size: 8 bits Description CCx Change Status When set, each bit indicates that the respective bit in the CCx Match Registers (CCx_MATCH) has changed. Type Default R/WC 0h A write of 1b clears the respective status bit. 9.12.4 CCX MATCH REGISTERS (CCX_MATCH) Address: x=1: 0806h x=2: 0807h Size: 8 bits Bits Description Type Default 7:0 CCx Threshold Match (CCx_MATCH) When set, each bit indicates that the respective threshold programmed in the CC Threshold x Registers (CC_THRx) was matched. A match is determined when the measured voltage exceeds the programmed threshold. RO Note 9-4 These registers are updated after the Match Debounce Register (MATCH_DEB) while in the Unattached state. While in AttachWait state, these registers are updated after the PD Debounce Register (PD_DEB) if vOpen is seen for a time greater than in the PD Debounce Register (PD_DEB). While in Attached Source / Attached Sink states (e.g. detecting detach) the match registers are updated after the PD Debounce Register (PD_DEB). Note: This register will always read the default value until the CC comparator is enabled when not operating in standalone mode. Note: Note 9-4 The contents of this register are debounced per the settings in the CCx Debounce Clear Enable Registers (CCx_DBCLR_EN), otherwise the raw value shall be shown. Defaults to FFh when the device is configured as a DFP and 00h when configured as a UFP, per the Device Role field in the CC Control Register (CC_CTL).  2016-2017 Microchip Technology Inc. DS00002084C-page 89 UPD360 9.12.5 VBUS MATCH REGISTER (VBUS_MATCH) Address: 0808h Size: 8 bits Indicates which VBUS thresholds are matched on VBUS_DET pin. A match is determined when the measured voltage exceeds the programmed threshold. Note: When not operating in standalone mode, this register will always read 0h until the VBUS comparator is enabled. Note: The contents of this register shall be debounced per the settings in VBUS Debounce Clear Enable Register (VBUS_DBCLR_EN). Bits Type Default RESERVED RO - 5 VBUS Threshold 3 Match (VBUS3_THR_MATCH) RO 0b 4 VBUS Threshold 2 Match (VBUS2_THR_MATCH) RO 0b 3 VBUS Threshold 1 Match (VBUS1_THR_MATCH) RO 0b 2 VBUS Threshold 0 Match (VBUS0_THR_MATCH) RO 0b 1 RESERVED RO - 0 VBUS VSafe0v Match (VSAFE0V_THR_MATCH) RO 0b Type Default R/WC 0h 7:6 9.12.6 Description VBUS CHANGE STATUS REGISTER (VBUS_CHG_STS) Address: Bits 7:0 0809h Size: 8 bits Description VBUS Change Status (VBUS_CHG_STS) When set, each bit indicates that the respective bit in VBUS Match Register (VBUS_MATCH) has changed. A write of 1b clears the respective status bit. DS00002084C-page 90  2016-2017 Microchip Technology Inc. UPD360 9.12.7 POWER INTERRUPT STATUS REGISTER (PWR_INT_STS) Address: 080Ah Size: 8 bits Bits Description Type Default 7 VBUS_MATCH_VLD Asserts after the VBUS debouncer is first enabled, via VBUS Comparator Control, and the first match becomes valid in VBUS Match Register (VBUS_MATCH). R/WC 0b 6 VCONN Discharge Error (VCONN_DISCH_ERR) When set this bit indicates that a VCONN discharge error has been detected. This bit is only available in standalone DFP mode and is otherwise reserved. R/WC 0b R/WC 0b R/WC 0b R/WC 0b R/WC 0b A discharge error is tracked when VCONN Discharge Control is set to 00b or 01b. A discharge error is asserted when VCONN fails to fall below VCONN Discharge Threshold (VCONN_DIS_THR) after a time greater than VCONN Discharge Time (VCONN_DIS_TIME) elapses. 5 CC2 Back-Drive Error When set, indicates that back-drive has been detected on the CC2 pin. Note: 4 VBUS Discharge Error When set, indicates that the an interval greater than defined in the VBUS Off Register (VBUS_OFF) has elapsed while attempting to discharge VBUS. Note: 3 The source of this input is a level and persists until the error condition stops. The source of this input is a pulse and does not persist after being cleared. VCONN2 FET Power The integrated VCONN2 FET is enabled and providing power. This bit only has usefulness for standalone operation or where VCONN is explicitly enabled by the host. Note: 2 The source of this input is a level and persists until the VCONN is no longer present. VCONN1 FET Power The integrated VCONN1 FET is enabled and providing power. This bit only has usefulness for standalone operation or where VCONN is explicitly enabled by the host. Note: The source of this input is a level and persists until the VCONN is no longer present. 1 CC1 Back-Drive Error When set indicates that back-drive has been detected on the CC1 pin. Note: The source of this input is a level and persists until the error condition stops. R/WC 0b 0 VCONN Over-Current Error Indicates an over-current has been detected on the integrated VCONN FET. R/WC 0b Note: The source of this input is a level and persists until the error condition stops.  2016-2017 Microchip Technology Inc. DS00002084C-page 91 UPD360 9.12.8 DEBUG INTERRUPT STATUS REGISTER (DBG_INT_STS) Address: Bits 7:4 3 080Bh Size: 8 bits Description RESERVED VCONN_DISCH_STS When set, indicates that the CC pin previously sourcing VCONN is being discharged. Type Default RO 0h R/WC 0b R/WC 0b R/WC 0b R/WC 0b Type Default R/W 0000b - 00b R/W 00b This bit only exists in standalone DFP mode and is otherwise reserved. 2 VBUS_DISCH When set indicates this indicates that VBUS is being discharged. Note: 1 The source of this input is a level and it persists until the discharge has completed. CFG_SEL1 Done When set, indicates that all CFG_SEL Threshold x Registers (CFG_SEL_THRx) have been measured in response to the request enabled by VBUS Comparator Control to sample the CFG_SEL1 pin and the results are readable in the respective CFG_SELx Match Registers (CFG_SELx_MATCH) (UPD360-A/UPD360-B only). Note: 0 The source of this input is a pulse and does not persist after being cleared. CFG_SEL0 Done When set, indicates that all CFG_SEL Threshold x Registers (CFG_SEL_THRx) have been measured in response to the request enabled by VBUS Comparator Control to sample the CFG_SEL0 pin and the results are readable in the respective CFG_SELx Match Registers (CFG_SELx_MATCH). Note: 9.12.9 The source of this input is a pulse and does not persist after being cleared. CC INTERRUPT ENABLE REGISTER (CC_INT_EN) Address: Bits 0811h Size: Description 7:4 CC Interrupt Enable When “0”, prevents generation of the respective interrupt. 3:2 RESERVED 1:0 CC Interrupt Enable When “0”, prevents generation of the respective interrupt. DS00002084C-page 92 8 bits  2016-2017 Microchip Technology Inc. UPD360 9.12.10 CCX MATCH ENABLE REGISTERS (CCX_MATCH_EN) Address: Bits 7:0 9.12.11 x=1: 0812h x=2: 0813h Size: 8 bits Description CCx Match Enable When set, the corresponding bit in the CCx Change Status Registers (CCx_CHG_STS) can cause the assertion of the respective CCx Match Change interrupt (CC1_MATCH_CHG/CC2_MATCH_CHG). Type Default R/W 00h VBUS MATCH ENABLE REGISTER (VBUS_MATCH_EN) Address: 0814h Size: 8 bits When set, the corresponding bit in the VBUS Change Status Register (VBUS_CHG_STS) can cause the assertion of the VBUS_INT interrupt. Bits Type Default RESERVED RO - 5 VBUS Match Enable[5] R/W 0b 4 VBUS Match Enable[4] R/W 0b 3 VBUS Match Enable[3] R/W 0b 2 VBUS Match Enable[2] R/W 0b 1 VBUS Match Enable[1] RO 0b 0 VBUS Match Enable[0] R/W 0b Type Default R/W 0h 7:6 9.12.12 Description POWER INTERRUPT ENABLE REGISTER (PWR_INT_EN) Address: Bits 7:0 0815h Size: Description Power Interrupt Enable [7:0] When “0”, prevents generation of the respective interrupt.  2016-2017 Microchip Technology Inc. 8 bits DS00002084C-page 93 UPD360 9.12.13 DEBUG INTERRUPT ENABLE REGISTER (DBG_ENT_EN) Address: Bits 0816h Size: 8 bits Type Default RESERVED RO 0h 3 Debug Interrupt Enable 3 When “0”, prevents generation of the respective interrupt. R/W 0b 2:0 Debug Interrupt Enable [2:0] When “0”, prevents generation of the respective interrupt. R/W 0h Type Default R/W 2h Type Default R/W Ah 7:4 Description This bit only exists in standalone DFP mode and is otherwise reserved. 9.12.14 MATCH DEBOUNCE REGISTER (MATCH_DEB) Address: Bits 7:0 0817h Size: 8 bits Description Match Debounce Defines the debounce period utilized before updating the CCx Match Registers (CCx_MATCH) when not operating in standalone mode. The units of this register is determined by MATCH_DB_UNITS bit in CC Hardware Control Register (CC_HW_CTL). When this bit is clear, the units are 1.6 ms. When this bit is set, the units are 100 us. Note: This register must not be modified while the CC debouncer is enabled. 9.12.15 Note: The actual debounce time may be +/-1 from the cycle time programmed. Note: The value programmed in this CSR should be at least equal to the number of thresholds enabled in CCx Sample Enable Registers (CCx_SAMP_EN). This is only an issue when MATCH_DB_UNITS is set to 1b. PD DEBOUNCE REGISTER (PD_DEB) Address: Bits 7:0 0818h Size: 8 bits Description PD Debounce (PD_DEB) Period used for implementing tPdDebounce. Note: This register must not be modified while the CC debouncer is enabled. Note: This register has units of 1 ms. DS00002084C-page 94  2016-2017 Microchip Technology Inc. UPD360 9.12.16 VCONN OCS AND BACK-DRIVE DEBOUNCE REGISTER (VCONN_DEB) Address: 0819h Size: 8 bits Bits Description Type Default 7:0 VCONN and Back-Drive Debounce (VCONN_DEB) Period used for implementing debounce of over-current detected on VCONN FET as well as back-drive detected on the CC pins. Note: This register has units of 1 ms. R/W 2h Type Default R/W Note 9-5 Note: 9.12.17 This register should not be changed when VCONN OCS Enable is set. CCX DEBOUNCE CLEAR ENABLE REGISTERS (CCX_DBCLR_EN) Address: Bits 7:0 x=1: 081Ah x=2: 081Bh Size: 8 bits Description CC Debounce Clear Enable (CC_DBCLR_DEB) When a bit is set, the respective threshold shall be included in the CC debouncer. Alternatively, when cleared the respective threshold shall no longer be considered by the debouncer. When CCx_DBCLR_EN bits are set on-the-fly, if a mismatch between the current raw match vector (for the new CCx_DBCLR_EN) and the previous raw match vector (for the old CCx_DBCLR_EN) exists, the DB will be reset. Note 9-5 Note: Clearing bits in this register at run time does not reset the debouncer. Note: The CC debouncer encompasses both CC1/CC2 pins. A detected change for a threshold on either pin results in the debouncer resetting. Note: Even though this register may change on-the-fly, the internal logic will enable the change only at the end of the scan cycle, which is a function of whether the CC1/CC2 pins are actively sampled and the CCx Sample Enable Registers (CCx_SAMP_EN). The default depends on the device’s configuration, as shown in table Table 9-10 which depends upon CFG_SEL0, PWR_CAP0, and PWR_CAP1 pins. APPLICATION NOTE: Clearing a bit in CCx Debounce Clear Enable Registers (CCx_DBCLR_EN) shall cause the respective bit in CCx Match Registers (CCx_MATCH) to be immediately updated upon a change in state of the associated threshold. This causes a state change in CCx Change Status Registers (CCx_CHG_STS) and assertion of CC_INT, if enabled. To prevent this CCx Match Enable Registers (CCx_MATCH_EN) should be updated before the CCx Debounce Clear Enable Registers (CCx_DBCLR_EN) by having the associated threshold cleared.  2016-2017 Microchip Technology Inc. DS00002084C-page 95 UPD360 TABLE 9-10: CCX_DBLCLR_DEB DEFAULTS Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Standalone UFP (UPD360-A/UPD360-B only) Configuration 1 0 1 0 1 0 0 0 Standalone DFP (Default Current) (UPD360-A/UPD360-B only) 1 0 0 0 0 1 0 0 Standalone DFP (1.5 A) (UPD360-A/UPD360-B only) 0 1 0 0 0 1 0 0 Standalone DFP (3.0 A) (UPD360-A/UPD360-B only) 0 0 0 1 0 0 1 0 Other 0 0 0 0 0 0 0 0 9.12.18 VBUS DEBOUNCE CLEAR ENABLE REGISTER (VBUS_DBCLR_EN) Address: 081Ch Size: 8 bits When a bit is set, the respective threshold shall be included in the VBUS debouncer. Alternatively, when cleared, the respective threshold shall no longer be considered by the debouncer. When VBUS_DBCLR_EN bits are set on-the-fly, if a mismatch between the current raw match vector (for the new VBUS_DBCLR_EN) and the previous raw match vector (for the old VBUS_DBCLR_EN) exists, the DB will be reset. Note: Clearing bits in this register at run time does not reset the debouncer. APPLICATION NOTE: Clearing a bit in VBUS Debounce Clear Enable Register (VBUS_DBCLR_EN) shall cause the respective bit in VBUS Match Register (VBUS_MATCH) to be immediately updated upon a change in state of the associated threshold. This causes a state change in VBUS Change Status Register (VBUS_CHG_STS) and assertion of VBUS_INT, if enabled. To prevent this, the VBUS Match Register (VBUS_MATCH) should be updated before the VBUS Debounce Clear Enable Register (VBUS_DBCLR_EN) by having the associated threshold cleared. BITS TYPE DEFAULT RESERVED RO - 5 VBUS Debounce Clear Enable (VBUS3_DBCLR_DEB) R/W Note 9-6 4 VBUS Debounce Clear Enable (VBUS2_DBCLR_DEB) R/W Note 9-6 3 VBUS Debounce Clear Enable (VBUS1_DBCLR_DEB) R/W Note 9-6 2 VBUS Debounce Clear Enable (VBUS0_DBCLR_DEB) R/W Note 9-6 1 RESERVED RO - 0 VSAFE0V Debounce Clear Enable 9 (VSAFE0V_DBCLR_DEB) R/W Note 9-6 7:6 Note 9-6 DESCRIPTION The default depends on the device’s configuration, as shown in table Table 9-11 which depends upon CFG_SEL0 pin. DS00002084C-page 96  2016-2017 Microchip Technology Inc. UPD360 TABLE 9-11: VBUS_DBCLR_EN DEFAULTS Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Standalone UFP (UPD360-A/UPD360-B only) Configuration 1 0 1 1 0 0 0 0 Standalone DFP (UPD360-A/UPD360-B only) 1 0 1 1 0 0 0 0 Other 0 0 0 0 0 0 0 0 9.12.19 CCX SAMPLE ENABLE REGISTERS (CCX_SAMP_EN) Address: BITS 7:0 x=1: 081Dh x=2: 081Eh Size: 8 bits DESCRIPTION CC Sample Enable (CC_SAMP_EN) When a bit is set, the respective CC threshold will be sampled by the CC debouncer. When a bit cleared to 0b, the corresponding bit(s) in the CCx Match Registers (CCx_MATCH) and CCx Change Status Registers (CCx_CHG_STS) will always read 0b. TYPE DEFAULT R/W FFh This register enables a reduction in latency for taking threshold measurements by only having thresholds of interest being sampled. Note: For standalone DFP/UFP operation this register may remain set to FFh, as latency for sampling CC thresholds in this case is not a limitation. Note: This register must be used to implement Collision Avoidance.  2016-2017 Microchip Technology Inc. DS00002084C-page 97 UPD360 9.12.20 CC CONTROL REGISTER (CC_CTL) Address: 0820h Size: 16 bits The register controls the pull-down resistors and current sources on the respective CC1/CC2 pin. Bits 15 Description RA Detect When set, indicates that an RA resistor has been detected. Type Default R/WC 0b Note 9-7 00b Note 9-7 0b R/W 00b Note 9-8 R/W 00b Note 9-8 This bit is set by the device when Standalone Operation is configured for standalone mode. The device updates this field after an attach has been detected. 14:13 12 CC Comparator Control 00b: CC Comparator and DAC powered-down 01b: CC Comparator samples CC1 10b: CC Comparator samples CC2 11b: CC Comparator samples CC1 and CC2 Note: A sample is taken every 100 us. The current source reference shall also be powered down when a value of 00b is set. Note: This field is RO and the contents are 11b when standalone mode is enabled. Note: This field is used in conjunction with the CCx Sample Enable Registers (CCx_SAMP_EN) which constrains the number of thresholds monitored on the enabled CC pin(s). CC Communication Select 0b: CC1 is used for baseband communication. 1b: CC2 is used for baseband communication. This bit is set by the device when Standalone Operation is configured for standalone mode. The device updates this field after an attach has been detected. This bit is RO and reflects the state determined by the internal logic. In standalone mode, this bit matches the state of the ORIENTATION pin (UPD360-A/ UPD360-B only). 11:10 CC2 RP Value 00b: RP current source disabled 01b: RP current source enabled, default USB power 10b: RP current source enabled, 1.5A 11b: RP current source enabled, 3.0A Controls RP value on CC2 pin. 9:8 CC1 RP Value 00b: RP current source disabled 01b: RP current source enabled, default USB power 10b: RP current source enabled, 1.5A 11b: RP current source enabled, 3.0A Controls RP value on CC1 pin. DS00002084C-page 98  2016-2017 Microchip Technology Inc. UPD360 Bits Description Type Default 7:6 DFP Current Advertisement When Standalone Operation is configured for standalone mode and the device is configured as UFP, Device Role, this field indicates the DFP’s advertised current. Otherwise this field shall be read back 00b. RO 00b RESERVED RO - CC2 Pull-Down Value 00b: Dead battery RD resistor selected 01b: Trimmed RD resistor selected 10b: Trimmed RA resistor selected. 11b: Open Disconnect. R/W Note 9-9 RESERVED RO - CC1 Pull-Down Value 00b: Dead battery RD resistor selected 01b: Trimmed RD resistor selected 10b: Trimmed RA resistor selected. 11b: Open Disconnect. R/W Note 9-9 The device updates this field after an attach has been detected. 0xb: RP current advertises default USB current 10b: RP current advertises 1.5A 11b: RP current advertises 3.0A 5 4:3 2 1:0 Note 9-7 This bit is RO when operating in standalone mode. Otherwise it is R/W. Note 9-8 This field’s default is a function of the PWR_CAP0 and PWR_CAP1 pins when in standalone DFP mode (see Section 9.8.1, "Configuration Selection") (UPD360-A/UPD360-B only). Otherwise the default is 00b. Note 9-9 For standalone DFP and standalone UFP, the value is 00b until the system reset completes. Afterwards, the default for standalone DFP is 11b and for standalone UFP is 01b. 9.12.21 CC THRESHOLD X REGISTERS (CC_THRX) Address: Bits 15:10 9:0 x=0: 0822h x=1: 0824h x=2: 0826h x=3: 0828h x=4: 082Ah x=5: 082Ch x=6: 082Eh x=7: 0830h Size: 16 bits Description Type Default RESERVED RO - CC Threshold X (CC_THRX) CC Threshold X register. R/W Note 9-10 Note 9-10 Note: The units of this register are ~2.44 mV from a 2.5V/1024. Note: This register must not be modified while the CC debouncer is enabled. The default varies as shown in Table 9-12.  2016-2017 Microchip Technology Inc. DS00002084C-page 99 UPD360 TABLE 9-12: CC_THR DEFAULTS CC_THR Type-C Threshold R/2R Divider VALUE 0.2 0.13 55 0 1 0.4 0.27 109 2 0.66 0.44 180 3 0.8 0.53 219 4 1.23 0.82 336 5 1.6 1.07 437 6 2.6 1.73 710 7 3 2 820 APPLICATION NOTE: The CC Comparator must be powered down before updating these registers. 9.12.22 CC DEBOUNCE REGISTER (CC_DEB) Address: Bits 7:0 9.12.23 8 bits Type Default R/W Fh Type Default RESERVED RO - CC Back-Drive Enable Enables the monitoring of the back-drive condition on both CC pins. R/W Note 9-11 R/W 0b CC Debounce (CC_DEB) Period used for implementing tCCDebounce. Note: This register must not be modified while the CC debouncer is enabled. Note: This register has units of 10 ms. VBUS CONTROL REGISTER (VBUS_CTL) Bits 11 Size: Description Address: 15:12 0832h 0840h Size: 16 bits Description When back-drive is detected, if the VCONN FET is enabled on the erred CC pin, it shall be automatically disabled. 0b: CC Back-Drive disabled 1b: CC Back-Drive enabled 10 IBUS_LOW Determines whether IBUS Low is asserted during standalone mode when PPC’s DISCH_SEL is cleared and a VBUS discharge is occurring. 0b: Do not assert IBUS Low 1b: Assert IBUS Low DS00002084C-page 100  2016-2017 Microchip Technology Inc. UPD360 Bits Description Type Default 9:8 OCS_MIN Defines the minimum guaranteed assertion time for OCS_N when operating in standalone DFP mode (UPD360-A/UPD360-B only). R/W 00b RO 0b R/W Note 9-11 R/W 00b R/W 0b 00b: 5 ms 01b: 10 ms 10b: 20 ms 11b: 30 ms 7 VBUS_DB_ACTIVE When this bit reads back 0b, the debouncer is disabled. The VBUS debouncer is enabled when it reads back 1b. Note: 6 Firmware polls this bit to determine when debouncer is disabled and a new configuration may be programmed. VCONN OCS Enable Enables the monitoring of over current condition on the internal VCONN FETs. 0b: VCONN OCS monitor is disabled 1b: VCONN OCS monitor is enabled 5:4 VCONN Discharge Control This field determines the VCONN discharge behavior. It only has meaning in DFP standalone mode and should not be used by firmware when operating in companion mode. The discharge occurs on the CC pin that was supplying VCONN. 00b: Discharge VCONN until either the threshold defined by the VCONN Discharge Threshold Register (VCONN_DIS_THR) is reached or the time specified by the VCONN Discharge Time Register (VCONN_DIS_TIME) has expired. 01b: VCONN discharge is not supported. 10b: Discharge VCONN until threshold defined by VCONN Discharge Threshold Register (VCONN_DIS_THR) is reached. 11b: Discharge VCONN for the time specified by VCONN Discharge Time Register (VCONN_DIS_TIME). Note: 3 For options 0xb a VCONN discharge error is detected if the timer expires and VCONN has not discharged below VCONN Discharge Time Register (VCONN_DIS_TIME). VCONN2 Control Enables the VCONN2 FET. 0b: VCONN2 FET is disabled 1b: VCONN2 FET is enabled This bit has no meaning when in standalone mode (see Standalone Operation). This bit automatically clears when a debounce VCONN OCS event occurs per the assertion of VCONN Discharge Error (VCONN_DISCH_ERR).  2016-2017 Microchip Technology Inc. DS00002084C-page 101 UPD360 Bits 2 Description Type Default R/W 0b Note 9-12 00b VCONN1 Control Enables the VCONN1 FET. 0b: VCONN1 FET is disabled 1b: VCONN1 FET is enabled This bit has no meaning when in standalone mode (see Standalone Operation). This bit automatically clears when a debounce VCONN OCS event occurs per the assertion of VCONN Discharge Error (VCONN_DISCH_ERR) 1:0 VBUS Comparator Control 00b: Comparator and DAC disabled 01b: Sample VBUS 10b: Sample CFG_SEL0 11b: Sample CFG_SEL1 (UPD360-A/UPD360-B only) After the sample of CFG_SEL0 or CFG_SEL1 has completed, this register resets itself to 00b and disables the VBUS comparator. Note: This field is forced to 01b by hardware when operating as a standalone UFP. Note 9-11 This default value is 1 when operating in standalone DFP mode. Otherwise, the default value is 0. Note 9-12 This field is RO and reads back 01b when operating in UFP standalone mode. In standalone mode this value does not indicate that VBUS is being actively measured. Whether or not VBUS is being actively measured can be determined by reading VBUS_DB_ACTIVE. 9.12.24 VBUS THRESHOLD X REGISTERS (VBUS_THRX) Address: Bits 15:10 9:0 x=0: 0842h x=1: 0844h x=2: 0846h x=3: 0848h Size: 16 bits Description Type Default RESERVED RO - VBUS Threshold X (VBUS_THRX) VBUS Threshold X register. R/W Note 9-13 The lower byte of the threshold must be written before the upper byte. The entire 10-bit threshold is updated when the second write occurs. Note: Note 9-13 TABLE 9-13: The units of this register are ~2.44 mV from a 2.5V FS. The defaults are defined in Table 9-13. VBUS_THR DEFAULTS VBUS_THR VBUS Threshold 1R/9R Divider VALUE 0 3.67 0.36 148 1 5.5 0.54 222 2 5.5 0.54 222 3 5.5 0.54 222 DS00002084C-page 102  2016-2017 Microchip Technology Inc. UPD360 9.12.25 VBUS DEBOUNCE REGISTER (VBUS_DEB) Address: 084Ah Size: 8 bits This register has units of 1 ms. Bits Type Default R/W 1h Type Default R/W 10h Type Default RESERVED RO - 3 VCONN Discharge When set the VBUS Discharge error shall be enabled to place the device in the error state. R/W 0b 2 VBUS Discharge When set, the VBUS Discharge error shall be enabled to place the device in the error state. R/W 0b 7:0 Description VBUS Debounce (VBUS_DEB) Indicates debounce interval for the VBUS threshold comparators. Note: 9.12.26 This register must not be modified while the VBUS debouncer is enabled. VBUS OFF REGISTER (VBUS_OFF) Address: 084Bh Size: 8 bits This register has units of 10 ms. Bits 7:0 9.12.27 Description VBUS Off Defines timing after VBUS_DET discharges below VSafe0V. VBUS ERROR REGISTER (VBUS_ERR) Address: Bits 7:3 084Ch Size: 8 bits Description Note: This bit is not applicable when the PPC is selected for VBUS discharge. 1 VCONN OCS When set, the CC OCS error shall be enabled to place the device in the error state. R/W 0b 0 CC Back-drive When set, the CC back-drive error shall be enabled to place the device in the error state. R/W 0b  2016-2017 Microchip Technology Inc. DS00002084C-page 103 UPD360 9.12.28 VBUS VSAFE0V THRESHOLD REGISTER (VSAFE0V_THR) Address: BITS 15:10 9:0 084Eh Size: 16 bits DESCRIPTION TYPE DEFAULT RESERVED RO - VSAFE0V Threshold (VSAFE0V_THR) VSAFE0V Threshold register. R/W Note 9-14 The lower byte of the threshold must be written before the upper byte. The entire 10-bit threshold is updated when the second write occurs. Note: Note 9-14 The units of this register are ~2.44 mV from a 2.5V FS. The defaults are defined in Table 9-14. TABLE 9-14: VSAFE0V_THR DEFAULTS VSAFE0V_THR VSAFE0V_THR VBUS Threshold 1R/9R Divider VALUE 0.8 0.08 32 APPLICATION NOTE: This register may be dynamically written to by software while the VBUS comparator is enabled, provided the rules for updating defined in the register description are followed. 9.12.29 CFG_SELX MATCH REGISTERS (CFG_SELX_MATCH) Address: Bits 15:0 x=0: 0850h x=1: 0852h Size: 16 bits Description Configuration Select X Match (CFG_SELX_MATCH) Indicates which configuration select thresholds are matched on the CFG_SELx pin. A match is determined when the measured voltage exceeds the programmed threshold. See Section 9.8.1, "Configuration Selection," on page 81. DS00002084C-page 104 Type Default RO 0h  2016-2017 Microchip Technology Inc. UPD360 9.12.30 CFG_SEL THRESHOLD X REGISTERS (CFG_SEL_THRX) Address: x=0: 0854h x=1: 0856h x=2: 0858h x=3: 085Ah x=4: 085Ch x=5: 085Eh x=6: 0860h x=7: 0862h x=8: 0864h x=9: 0866h x=10: 0868h x=11: 086Ah x=12: 086Ch x=13: 086Eh x=14: 0870h x=15: 0872h Size: 16 bits A total of 16 thresholds are supported for decoding the resistor value on the CFG_SELx pins. Bits 15:10 9:0 Description Type Default RESERVED RO - CFG_SEL Threshold (CFG_SEL_THR) Note: The units of this register are ~2.44 mV from a 2.5V FS. R/W Note 9-15 Note 9-15 TABLE 9-15: The defaults are defined in Table 9-15. CFG_SEL_THR DEFAULTS CFG_SEL_THR Default 0 32 1 96 2 160 3 224 4 288 5 352 6 416 7 480 8 544 9 608 10 672 11 736 12 800 13 864 14 928 15 992  2016-2017 Microchip Technology Inc. DS00002084C-page 105 UPD360 9.12.31 CFG_SEL DEBUG REGISTER (CFG_SEL_DBG) Address: 0874h Size: 8 bits Bits Description Type Default 7:4 CFG_SEL1_VAL This register stores a snapshot of the highest threshold matched when the device samples the CFG_SEL1 pin after a system level reset event (UPD360A/UPD360-B only). RO 0h 3:0 CFG_SEL0_VAL This register stores a snapshot of the highest threshold matched when the device samples the CFG_SEL0 pin after a system level reset event. RO 0h Type Default RESERVED RO - VCONN Discharge Threshold (VCONN_DIS_THR) R/W 41h Note 9-16 Type Default R/W 04h 9.12.32 VCONN DISCHARGE THRESHOLD REGISTER (VCONN_DIS_THR) Address: Bits 15:10 9:0 0886h Size: 16 bits Description This register defines the threshold used in standalone DFP mode for discharging VCONN. Note: Note 9-16 9.12.33 The units of this register are ~2.44 mV from a 2.5V/1024. 41 equates to 150mV after accounting for the R/2R divider. VCONN DISCHARGE TIME REGISTER (VCONN_DIS_TIME) Address: Bits 7:0 0888h Size: 16 bits Description VCONN Discharge Time (VCONN_DIS_TIME) Defines the amount of time the CC pin supplying VCONN is discharged. Note: The units of this register are 10 ms. DS00002084C-page 106  2016-2017 Microchip Technology Inc. UPD360 10.0 BASEBAND CC INTERFACE (BCI) The device integrates a Baseband CC Interface (BCI) to facilitate USB Power Delivery communication. This module bridges between the PD MAC/BMC and the analog front end. Baseband communication is initiated by the PD MAC, which interfaces to the BCI. The BCI implements the digital functions required to control TX baseband components. 10.1 Baseband TX Data-flow The key responsibility of the BCI is to generate the wave form required for baseband communication. To this end, the BMC has a group of eight registers that define the Lo-Hi and Hi-Lo transitions for the generated BMC signal. When instructed to transition from Lo-Hi, the BCI steps through all BB TX Risex Registers (BB_RX_RISEx). Likewise when instructed to transition from Hi-Lo, the BCI steps through all BB TX Fallx Registers (BB_TX_FALLx). The BCI always presents the value at BB_TX_RISE0 or BB_RX_FALL0 first. APPLICATION NOTE: The user may replicate values if it is desired to use less than twelve unique values for this purpose. The following steps should be followed to program the BCI for data transmission: 1. 2. 3. 4. 5. 6. Software programs the BB TX Risex Registers (BB_RX_RISEx) and BB TX Fallx Registers (BB_TX_FALLx) to define the slew rate for rising and falling transitions. Software enables the PD MAC. The PD MAC initiates, either via firmware, or autonomously via a data transmission (GoodCRC). The PD MAC instructs the BCI to take the BB TX analog components out of power-down. After a sufficient time elapses for the analog to power up, the PD MAC begins transmission to the BMC encoder which drives the analog components. If the MAC requests a rising transition, the BCI steps through the BB TX Risex Registers (BB_RX_RISEx). Alternatively, if the MAC requests a falling transition, the BCI steps through the BB TX Fallx Registers (BB_TX_FALLx). When the PD MAC indicates the transmission has completed, the BCI powers down the TX analog components. 10.2 Baseband RX Data-flow Baseband RX data is received by the BCI from the RX analog front end where it is compared to a threshold programmed by software. The CC RX DAC Value defines the trip point used for reception of baseband data. The field shall be programmed to be 175 mV below the RX Eye center, as defined in the PD Specification for the mode in which the device is operating (Sourcing Power, Sinking Power, Power Neutral). In order to program the required trip point, the RX DAC Enable bit must be set and the CC RX DAC Value field in the CC RX DAC Control Register (CC_RX_DAC_CTL) must be programmed.  2016-2017 Microchip Technology Inc. DS00002084C-page 107 UPD360 10.3 Baseband CC Interface Registers This section details the baseband CC interface registers. For an overview of the entire device register map, refer to Section 4.0, "Register Map," on page 19. TABLE 10-1: BASEBAND CC INTERFACE REGISTER MAP Address Register Name (Symbol) 2800h CC RX DAC Control Register (CC_RX_DAC_CTL) 2802h CC RX DAC Filter Register (CC_RX_DAC_FILT) 2803h Reserved for future expansion 2804h CC TX DAC Filter Register (CC_TX_DAC_FILT) 2805h – 280Fh 2810h Reserved for future expansion BB TX Risex Registers (BB_RX_RISEx) x=0 2812h BB TX Risex Registers (BB_RX_RISEx) x=1 2814h BB TX Risex Registers (BB_RX_RISEx) x=2 2816h BB TX Risex Registers (BB_RX_RISEx) x=3 2818h BB TX Risex Registers (BB_RX_RISEx) x=4 281Ah BB TX Risex Registers (BB_RX_RISEx) x=5 281Ch BB TX Risex Registers (BB_RX_RISEx) x=6 281Eh BB TX Risex Registers (BB_RX_RISEx) x=7 2820h BB TX Risex Registers (BB_RX_RISEx) x=8 2822h BB TX Risex Registers (BB_RX_RISEx) x=9 2824h BB TX Risex Registers (BB_RX_RISEx) x=10 2826h BB TX Risex Registers (BB_RX_RISEx) x=11 2828h – 282Fh Reserved for future expansion 2830h BB TX Fallx Registers (BB_TX_FALLx) x=0 2832h BB TX Fallx Registers (BB_TX_FALLx) x=1 2834h BB TX Fallx Registers (BB_TX_FALLx) x=2 2836h BB TX Fallx Registers (BB_TX_FALLx) x=3 2838h BB TX Fallx Registers (BB_TX_FALLx) x=4 283Ah BB TX Fallx Registers (BB_TX_FALLx) x=5 283Ch BB TX Fallx Registers (BB_TX_FALLx) x=6 283Eh BB TX Fallx Registers (BB_TX_FALLx) x=7 2840h BB TX Fallx Registers (BB_TX_FALLx) x=8 2842h BB TX Fallx Registers (BB_TX_FALLx) x=9 2844h BB TX Fallx Registers (BB_TX_FALLx) x=10 2846h BB TX Fallx Registers (BB_TX_FALLx) x=11 2848h – 2BFFh Note: Reserved for future expansion RESERVED address space must not be written under any circumstances. Failure to heed this warning may result in untoward operation and unexpected results. DS00002084C-page 108  2016-2017 Microchip Technology Inc. UPD360 10.3.1 CC RX DAC CONTROL REGISTER (CC_RX_DAC_CTL) Address: 2800h Bits 15 14:10 9:0 10.3.2 Size: 16 bits Description Type Default RX DAC Enable 0: Disable the CC RX DAC 1: Enable the CC RX DAC R/W 0b RESERVED RO - CC RX DAC Value This register defines the trip point used for reception of baseband data. R/W 0h Note: The full scale range of this DAC is 1.8V. Note: The DAC must be programmed to be 175mV below the desired RX Eye center. CC RX DAC FILTER REGISTER (CC_RX_DAC_FILT) Address: 2802h Bits Size: 8 bits Type Default RESERVED RO - 1 Select CC Rx Filter Configuration R/W 0b 0 CC RX DAC Filter Enable R/W 0b Type Default RESERVED RO - 4 CC TX Filter Enable Enables CC TX filter and driver. R/W 0 3:0 CC TX Filter Selects CC TX filter bandwidth. R/W 8h 7:2 10.3.3 Description CC TX DAC FILTER REGISTER (CC_TX_DAC_FILT) Address: 2804h Bits 7:5 Description  2016-2017 Microchip Technology Inc. Size: 8 bits DS00002084C-page 109 UPD360 10.3.4 BB TX RISEX REGISTERS (BB_RX_RISEX) Address: x=0: 2810h x=1: 2812h x=2: 2814h x=3: 2816h x=4: 2818h x=5: 281Ah x=6: 281Ch x=7: 281Eh x=8: 2820h x=9: 2822h x=10: 2824h x=11: 2826h Size: 16 bits The BB TX Rise registers define the characteristics of the baseband waveform on rising transitions. Bits 15:10 9:0 10.3.5 Description Type Default RESERVED RO - BB TX Rise Value Code presented to the CC TX DAC when implementing the rising transition for a baseband transmission. R/W 0h BB TX FALLX REGISTERS (BB_TX_FALLX) Address: x=0: 2830h x=1: 2832h x=2: 2834h x=3: 2836h x=4: 2838h x=5: 283Ah x=6: 283Ch x=7: 283Eh x=8: 2840h x=9: 2842h x=10: 2844h x=11: 2846h Size: 16 bits The BB TX Fall registers define the characteristics of the baseband waveform on rising transitions. Bits 15:10 9:0 Description Type Default RESERVED RO - BB TX Fall Value Code presented to the CC TX DAC when implementing the falling transition for a baseband transmission. R/W 0h DS00002084C-page 110  2016-2017 Microchip Technology Inc. UPD360 11.0 POWER DELIVERY MAC The PD MAC implements certain features of the protocol layer and physical layer of the Universal Serial Bus Power Delivery Specification. On one end the PD MAC interfaces to the software implementing the bulk of protocol and higher level layers and on the other end it interfaces to a BMC encoder / decoder module. In addition to the normal TX and RX functions, the PD MAC implements the test mode logic defined in the USB PD specification (BIST). The PD MAC supports the following features: • • • • • • • • • • • • • • • Automatic TX Mode for packet framing and CRC32 insertion. Raw TX Mode for bit level packet control. Automatic GoodCRC response to received messages. Automatic BIST Error Count Message in BIST RX Mode. GoodCRCTimer implementation. Automatic retries with programmable retry count. Redundant receive packets automatically dropped in auto response mode. 74 byte TX queue. 128 byte RX queue. Programmable TX Bit-time. Allows for changing operating frequency. Programmable preamble length. BIST TX and RX logic. Programmable TX and RX queue modes - buffer mode and FIFO mode. CRC32 generator for TX. CRC32 calculator and comparator for RX. 11.1 PD MAC Transmitter The PD MAC transmitter is comprised of three major blocks: • TX Queue • TX Control • TX Comm The TX Queue is where software loads the message to be transmitted. The TX Control implements the necessary control logic. It is responsible for reading the data from the TX queue and based on the data processing mode (automatic or raw), processing the data to make it suitable (nibbles with control information) for use by the TX Comm. It is also responsible for generating packet framing and terminating the packet in automatic mode, and generating messages for automatic response (GoodCRC and BIST Error Count). TX Control also handles the selection of the SOP type that is to be transmitted. The TX Comm is comprised of a TX CRC generator, a 4b5b encoder, serializer, preamble generator, and TX bit timer. It takes the nibble data, computes and inserts the CRC, 5b encodes, and generates the baseband serial data. Preamble insertion is also performed by this logic. The following sub-sections describe the various blocks and sub-blocks in more detail. Some of the supported TX features are also described. 11.1.1 TX QUEUE The TX Queue is where software loads the message to be transmitted. The following sub-sections describe the TX Queue in more detail. 11.1.1.1 TX Queue Modes of Operation The TX Queue's write interface (MCU side) has two modes of operation: FIFO Mode and Buffer Mode. 11.1.1.1.1 FIFO Mode This mode is enabled by setting the EN_FMQ bit in the TX Control Register A (TX_CTL_A). In this mode, software writes data into the TX Queue like a FIFO. Software can use any offset address in the range of 1800h-1849h (although 1800h would be logical to use). The FIFO is 74 entries deep. Data written to the FIFO cannot be read back by software.  2016-2017 Microchip Technology Inc. DS00002084C-page 111 UPD360 11.1.1.1.2 Buffer Mode This mode is selected when the EN_FMQ bit in the TX Control Register A (TX_CTL_A) is cleared (default after POR). In this mode, software writes data into the TX Queue as if it were writing to registers at different addresses. The offset address range is 1800h-1849h and the buffer has 74 locations. Only byte access should be used while accessing the TX Queue in this mode. Note that buffer offset address 1800h contains the least-significant-byte (LSB) (byte that goes out first). Buffer offset address 0x049 has the most-significantbyte (MSB) (byte that goes out last). Software can arbitrarily write or read any location in the buffer. Only one packet can be queued into the TX Queue at one time. Queuing of multiple packets is not supported. 11.1.1.2 TX Queue Data and Processing Modes The data placed in the TX Queue depends on the selected processing mode. Two modes are supported: “Auto Mode Data Processing” (AMDP) and “Raw Mode Data Processing” (RMDP). 11.1.1.2.1 Auto Mode Data Processing (AMDP) This mode is selected by clearing the EN_RMDP bit in the TX Control Register A (TX_CTL_A). In this mode, only the message data (header and data objects) to be transmitted is queued in the TX Queue. Further, the data is queued as bytes. Since there is no framing information with the data, the TX Packet Length Register (TX_PKT_LEN) is used to provide information about the length of message data. Hardware uses this information to determine when and where to append the CRC. Packet framing (preamble, SOP, and EOP) is automatically inserted by the hardware. 11.1.1.2.2 Raw Mode Data Processing (RMDP) This mode is selected by setting the EN_RMDP bit in the TX Control Register A (TX_CTL_A). In this mode, software is responsible for constructing the entire packet including framing, except the preamble and CRC. Since framing involves K-codes, the data placed in the queue is coded with control information. The data in each byte of the queue is treated as a “nibble” of packet data that either needs to be 5b encoded by hardware or a K-codes that should be transmitted without any 5b encoding. There are also some special control bytes to control insertion of CRC and termination of packet. When tx_queue_data[5] is “0” then tx_queue_data[3:0] is treated as 4b regular data. This 4b data goes through the CRC32 generator for CRC calculation and is encoded to 5b per Table 5-1 of USB PD Specification R1.0 (Table 11-1 shows the 4b5b encoding). When tx_queue_data[5] is “1” then tx_queue_data[4:0] is treated as 5b K-code (see Table 11-1). This data is eliminated from the CRC calculation and does not go through any further encoding prior to transmission. The tx_queue_data[7:0] values of 8'hFF and 8'hFE have special meaning. 8'hFF implies that the packet data is done and hardware should now insert the calculated CRC32 (TX_INS_CRC). 8'hFE implies that the transmission should be stopped immediately (TX_STOP). Note that in RMDP, software can compute its own CRC and place it in the Queue as encoded data. In this case, the TX_INS_CRC code would not be added to the Queue and instead software would proceed with adding the EOP and terminating the transfer with TX_STOP. Table 11-1 shows how the byte wide queued data is interpreted or encoded by the transmission logic in raw mode. DS00002084C-page 112  2016-2017 Microchip Technology Inc. UPD360 TABLE 11-1: RAW MODE DATA ENCODING tx_queue_data[5:0] Encoded Symbol tx_queue_data[5:0] Encoded Symbol 6’h00 5’b11110 6’h08 5’b10010 6’h01 5’b01001 6’h09 5’b10011 6’h02 5’b10100 6’h0A 5’b10110 6’h03 5’b10101 6’h0B 5’b10111 6’h04 5’b01010 6’h0C 5’b11010 6’h05 5’b01011 6’h0D 5’b11011 6’h06 5’b01110 6’h0E 5’b11100 6’h07 5’b01111 6’h0F 5’b11101 tx_queue_data[5:0] K-Code Transmitted Data 6’b1_11000 Sync-1 5’b11000 6’b1_10001 Sync-2 5’b10001 6’b1_01101 EOP 5’b01101 6’b1_00111 RST1 5’b00111 6’b1_11001 RST2 5’b11001 tx_queue_data[5:0] Special Meaning 8’hFE TX_STOP 8’hFF TX_INS_CRC Note that the tx_queue_data[4:0] is passed as-is when tx_queue_data[5] is set to 1. Thus, software can send reserved symbols for error testing. The only caveat is that hardware cannot be used to generate and insert CRC. In this case, software should compute the necessary CRC32 and add it the data packet and skip the 0xFF code in the queue for CRC insertion. 11.1.1.2.3 TX Queue Programming Sequence - AMDP The following sequence should be used when programming a sequence in AMDP. This example assumes hardware performs packet framing and CRC insertion. 1. 2. 3. 4. 5. 6. 7. Make sure the GO bit in the TX Control Register B (TX_CTL_B) is cleared, i.e., hardware is done with previous TX request. If using FIFO mode, clear the TX Queue WRI pointer by writing a “1” to the RST_TXQ_FIFO_WRI_PTR bit of the TX Control Register B (TX_CTL_B). Write the two header bytes. Write the payload data, if any. Write the number of bytes to the TX Packet Length Register (TX_PKT_LEN). Check to see if it is OK to transmit via the OK_TO_TX bit in the TX Control Register B (TX_CTL_B)). If OK_TO_TX: set the GO bit in the TX Control Register B (TX_CTL_B) to start transmission. Else: repeat step 6. Note: If an RX is in progress, the current TX may need to be abandoned.  2016-2017 Microchip Technology Inc. DS00002084C-page 113 UPD360 11.1.1.2.4 TX Queue Programming Sequence - RMDP The following sequence should be used when programming a sequence in RMDP. This example assumes hardware performs CRC insertion. 1. Make sure the GO bit in the TX Control Register B (TX_CTL_B) is cleared, i.e., hardware is done with previous TX request. 2. If using FIFO mode, clear the TX Queue WRI pointer by writing a “1” to the RST_TXQ_FIFO_WRI_PTR bit of the TX Control Register B (TX_CTL_B). 3. Write the SOP K-Codes to the FIFO *Sync-1, Sync-1, Sync-1, Sync-2). 4. Write two header bytes, splitting each byte into nibbles. 5. Write the payload data, if any, splitting each byte into nibbles. 6. Write the value “0xFF” to insert the CRC. 7. Write the EOP K-Code (EOP). 8. Write the value “0xFE” to terminate the transmission. Failure to write this value will cause transmission to continue indefinitely looping on the TX buffer. 9. Check to see if it is OK to transmit via the OK_TO_TX bit in the TX Control Register B (TX_CTL_B)). 10. If OK_TO_TX: set the GO bit in the TX Control Register B (TX_CTL_B) to start transmission. Else: repeat step 9. Note: If an RX is in progress, the current TX may need to be abandoned. Note: 11.1.2 The value of the TX Packet Length Register (TX_PKT_LEN) is ignored for this mode since hardware knows when to terminate the packet based on detection of TX_STOP control code. TX CONTROL The TX Control implements the necessary control logic. It is responsible for reading the data from the TX queue and based on the data processing mode (automatic or raw), processing the data to make it suitable (nibbles with control information) for use by the TX Comm. It is also responsible for generating packet framing and terminating the packet in automatic mode, and generating messages for automatic response (GoodCRC and BIST Error Count). TX Control also handles the selection of the SOP type that is to be transmitted. 11.1.2.1 Transmit Requests There are four sources of transmit requests: • • • • GoodCRC Ack from the receiver for a soft-reset GoodCRC Ack from the receiver for a normal packet BIST error count message from the BIST receiver Transmit go from the software 11.1.2.2 Transmit Aborts Once packet transmission is initiated, the device will power up the analog and then wait for the bus turn-around timers and power-up timers to expire. During this wait, the transmission can be aborted by software and will be aborted by the device, when a good packet (including soft-reset), a hard reset, or a cable reset (if enabled and the SOP type of the pending TX is SOP', SOP'', SOP'_Debug or SOP''_Debug) is received. Once the bus turn-around time has expired (or if it was already expired) and the power up time is expired, the bus is checked for idle. If the bus is idle, the transmission is started. If the bus is not idle, the transmission is discarded and, typically, an abort status set. This discard can be disabled with the WAIT4LINE_IDLE bit in the TX Control Register A (TX_CTL_A) for all packets and is also disabled for auto response triggered GoodCRC Acks for received soft-resets (unless the feature is disabled via the DIS_SPCL_SR_GCRC_ACK bit). If the transmission is not discarded due to the bus being non-idle, the device waits for the bus to become idle and then, once again, waits the turn-around time. During the wait for bus idle, the transmission can be aborted by software and will be aborted by the hardware if a good packet, a hard reset or a cable reset (if enabled and the SOP type of the pending TX is SOP', SOP'', SOP'_Debug or SOP''_Debug) is received. Software issued hard and cable resets are not aborted due to received good packets, hard resets or cable resets. DS00002084C-page 114  2016-2017 Microchip Technology Inc. UPD360 Note that for a received good packet to abort a pending transmission, the SOP type of the received packet must match the SOP type of the pending transmission, or the SOP type of the received packet must be SOP with the SOP type of the pending transmission being non-SOP (the latter can be disabled via the DIS_SOP_ABRTS_NON_SOP bit in the TX Control Register A (TX_CTL_A)) and, for messages other than Soft-Reset, the received message ID must indicate a non-duplicated packet (Soft-Resets are never considered duplicates). Ping and GoodCRC messages do not cause a transmission to abort. Separate TX interrupt abort bits and separate abort status registers are provided for software issued and auto-response packets. 11.1.2.3 Transmit Retries Transmitted packets are retried under two scenarios: bus idle violations, and GoodCRC response timeout. If the transmission is discarded due to the bus being non-idle, the option exists to retry instead of treating it as an abort. In order for this to occur, the packet must have been initiated by software, not be a hard or cable reset, auto response mode must be enabled, the retry count must be non-zero, and the RETRY_ON_LINE_BUSY bit in the TX Control Register A (TX_CTL_A) must be set. If after the specified number of retries, the transmission failed due to bus busy, the TX_FAILED status is set (not TX_ABORTED). Hard and Cable resets are not retried. Following the transmission of a software initiated frame (other than Hard and Cable resets), the device will start a timer and wait for a GoodCRC response to be indicated by the receiver. This assumes retries and / or the wait for GoodCRC are enabled. If a GoodCRC is received with the correct SOP type and message ID, then the wait is finished and the transmission is done. If a GoodCRC is received with the wrong SOP type or message ID, it is ignored by the transmitter (the transmitter is not even notified) and silently dropped by the receiver. If the wait for CRC timer expires and the remaining retry count is non-zero, the original packet is re-transmitted. If the remaining retry count is zero, then the packet is not retried and a failed status is indicated. The wait for GoodCRC will be aborted if any of the following are received: • A hard reset • A cable reset (if cable reset reception is enabled and the SOP type of the pending TX is SOP', SOP'', SOP'_Debug or SOP''_Debug) • A soft-reset (if the SOP type of the RX is the same as that of the pending TX or the SOP type of the RX is SOP with the SOP type of the pending transmission being non-SOP) • A good packet other than a GoodCRC or Ping (if the SOP type of the RX is the same as that of the pending TX or the SOP type of the RX is SOP with the SOP type of the pending transmission being non-SOP (the latter can be disabled via the DIS_SOP_ABRTS_NON_SOP bit in the TX Control Register A (TX_CTL_A)) and the package is not a duplicate message) The latter two causes are considered to be protocol errors. The wait for GoodCRC can also be aborted by software. An aborted wait for GoodCRC is not retried. 11.1.2.4 Transmitter Disable In order to avoid a race condition where the software is currently issuing a transmit and the hardware is receiving a packet, the EN_FWTX bit in the TX Parameters Register A (TX_PARAM_A) is automatically cleared if a hard reset to a cable reset (if enabled - no SOP type checking is done since a transmission may not be pending) has been received (based on the RX_CABLE_RST and RX_HARD_RST bits in the RX Interrupt Status Register (RX_IRQ_STAT)) or if there is any data in the RX FIFO. Using the interrupt and FIFO status (level sensitive) instead of the even occurrence (edge) avoids another race condition where the software has set the EN_FWTX bit just following the event. 11.1.3 TX COMM The TX Comm is responsible for taking the coded nibbles from TX Control, encoding it if necessary, and serializing to make it ready for transmission. It is responsible for preamble insertion, CRC calculation, and CRC insertion. It also provides the TX clock signal for the BMC encoder. 11.1.3.1 Preamble Insertion The device automatically adds the alternating “0” and “1” preamble to the transmitted packet. When the transmission of the preamble is completed, data from TX Queue is processed under direction of the TX Control.  2016-2017 Microchip Technology Inc. DS00002084C-page 115 UPD360 The number of preamble bits sent is programmable by the value of the PREAMBLE_LEN bit in the TX Parameters Register B (TX_PARAM_B). Note: Setting the PREAMBLE_LEN field to an odd value will cause violation of the USB PD Specification which states “The preamble shall start with a “0” and shall end with a “1”.” An odd value will cause preamble to start with a value of “0” but it will also end in a value of “0.” Setting this field to an odd value may or may not lead to functional issues. Therefore, this field should be set to an even value to remain USB PD Specification compliant. 11.1.3.2 TX CRC32 The transmit CRC is reset at the start of transmission (setting of the GO bit in the TX Control Register B (TX_CTL_B) or by triggering of automatic response by hardware). The coded nibble data is streamed into the TX CRC32 one nibble at a time for CRC calculation. Only valid D-Code data is used in CRC calculation. All framing data (invalid D-Code) is excluded from CRC calculation. Note: The CRC32 algorithm is described in the USB PD Specification. 11.1.3.3 TX Bit Timing The baseband transmit signal bit time is controlled by the value in the TX Bit-Time Count Register (TX_BITTIME_CNT). This value determines the transmit data rate. The count value is based on clock frequency and is given by: ((Clock Freq KHz / Bit Rate Kbps) - 1) For example: Clock Frequency = 48000KHz (48MHz) Nominal Bit Rate = 300 Kbps bit_time_cnt = (48000 / 300) - 1 = 159 11.1.4 AUTOMATIC RESPONSE MODE The device supports an Automatic Response Mode (not to be confused with automatic-data processing mode). In this mode, the device will automatically send a GoodCRC message upon successful packet reception, or a BIST Error Count message upon reception of a BIST PRBS frame. This mode can be enabled by setting the EN_AUTO_RSP_MODE bit in the TX Control Register A (TX_CTL_A). During normal auto-response, if the bus if found to be busy when the device attempts to send the auto-response (should not happen, except if there is noise) it will abort the transmission and the AUTO_RSP_ABORTED bit in the TX Interrupt Status Register (TX_IRQ_STAT) will be set. This behavior can be altered by setting the WAIT4LINE_IDLE bit in the TX Control Register A (TX_CTL_A). Setting this bit will force the device to wait until the bus becomes idle (refer to the WAIT4LINE_IDLE bit description for additional information). GoodCRCs and BIST Error Count messages are not retried even if RETRY_ON_LINE_BUSY in TX_CTL_A is set. In USB Power Delivery Revision 1.0, Soft Reset had a one-strike rule and failure of Soft Reset led to Hard Reset, leading to the link being brought down, therefore the transmission of GoodCRC ACK in response to reception of Soft Reset is handled a little differently. If hardware finds that the line is busy when it attempts to send the GoodCRC ACK it will wait until the line becomes idle and then re-try the transmission. This process will happen indefinitely. This behavior is same as what happens to normal GoodCRC ACK when WAIT4LINE_IDLE bit is set. GoodCRCs are not retried even if the RETRY_ON_LINE_BUSY bit in the TX Control Register A (TX_CTL_A) is set. For USB Power Delivery Revision 3.0, Soft Resets are normally retried, therefore this function should be disabled via the DIS_SPCL_SR_GCRC_ACK bit. The SOP type that is used for the automatically sent GoodCRC packet is the SOP type of the received packet (parsed by the receiver). The SOP type that is used for the BIST Error Count message, is selected via the TX_SOP_SELECT bit in the TX Parameters Register A (TX_PARAM_A). For both GoodCRC and BIST Error Count messages, bit 8 in the packet header is taken from either the PORT_POWER_ROLE (for SOPs) or the CABLE_PLUG (for SOP', SOP'' and _debugs) bits within the TX Parameters Register C (TX_PARAM_C), depending on the SOP type that was received. Bit 5 in the packet header is taken from either the PORT_DATA_ROLE bit (for SOPs) or set to zero (for SOP', SOP'' and _debugs), depending on the SOP type that was received. In order to avoid missing an auto response GoodCRC request, a flag is used. The flag is set with a request pulse from the receiver and is cleared when the response is sent or aborted. Along with the request flag being set, the SOP type and message ID of the request as well as the Soft Reset response indication are saved. In the event that there was a DS00002084C-page 116  2016-2017 Microchip Technology Inc. UPD360 pending auto response GoodCRC request and another packet was received resulting in another auto response GoodCRC request, the second request will replace the first request, unless the first request had a SOP type of SOP and the second request had a SOP type of SOP'_Debug or SOP'’_Debug. This replacement occurs regardless of the setting of the DIS_SOP_ABRTS_NON_SOP bit in the TX Control Register A (TX_CTL_A). Even if a received packet does not abort a pending auto response, the pending auto response may get replaced by a new auto response. 11.1.5 AUTOMATIC RETRY MODE The device also supports an Automatic Retry Mode. In this mode, when a GoodCRC message is not received in the appropriate time (i.e., before CRCReceiveTimer expires) the current message is retried. Hardware will retry the message until the retry value specified in the N_RETRY_CNT field in the TX Parameters Register C (TX_PARAM_C) is satisfied. If the N_RETRY_CNT is set to zero, Automatic Retry Mode is disabled. The number of retries used by the device to complete the transaction are tracked and made available to software via the N_HW_RETRIES field in the TX Status Register (TX_STAT). An N_RETRY_CNT value of zero implies the message is attempted only once, i.e., hardware will not retry it. N_RETRY_CNT specifies the number of retries so the number of attempts is (N_RETRY_CNT + 1). Stated another way, if you want hardware to make “N” attempts to send a message then the N_RETRY_CNT field must be set to “N-1.” Reception of Hard Reset or Cable reset (when enabled and the SOP type of the pending TX is SOP', SOP'', SOP'_Debug or SOP''_Debug) from port partner, messages other than GoodCRC or Ping message (if the SOP types of the RX and TX match or if the SOP type of the RX is SOP with the SOP type of TX being non-SOP (the latter can be disabled via the DIS_SOP_ABRTS_NON_SOP bit in the TX Control Register A (TX_CTL_A)) and the packet was not a duplicate), or issuance of abort by software will terminate any pending auto retries. Detection of bus collision will cause the device to abort the current transfer including any pending auto retries unless the RETRY_ON_LINE_BUSY bit in the TX Control Register A (TX_CTL_A) is set. Note that disabling of automatic-retry by setting N_RETRY_CNT to zero will also disable the device’s ability to wait for a GoodCRC message before a successful message transmission is indicated. This applies, for example, to the case when Soft Reset is transmitted. To circumvent this limitation, a EXPECT_GOODCRC bit in the TX Parameters Register A (TX_PARAM_A) is available. Setting this bit will cause the device to wait for a GoodCRC in response to a TX message, even when the N_RETRY_CNT field is set to zero. Note: Setting N_RETRY_CNT to zero after the GO bit has been set will have no effect for the current transfer. The expected message ID within the GoodCRC message is set by software via the MSG_ID field in the TX Parameters Register A (TX_PARAM_A). This is compared to the message ID within the received GoodCRC message. The expected SOP type within the GoodCRC message is set by software via the TX_SOP_SELECT field in the TX Parameters Register A (TX_PARAM_A). This is compared to the SOP type received in the GoodCRC message. In order for the GoodCRC message to be received, it is assumed that the SOP type has been enabled via the RX_SOP_ENABLE field in the RX Control Register B (RX_CTL_B). 11.1.6 IFG TIMER The TX turn-around timer is used to insure that a minimum bus idle time is guaranteed between packet reception and packet transmission, i.e., sending of GoodCRC message upon successful packet reception. The value of this timer is programmable via the TX Turnaround Time Register (TX_TA_TIME). The value is specified in uSec. This timer uses the free-running 1us pulse so the value of this register should be 1 more than desired to ensure the minimum time. 11.1.7 CRC RECEIVE TIMER This timer is enabled when the device is expected to wait for a GoodCRC ACK (i.e., automatic-retry mode is enabled by non-zero value in the N_RETRY_CNT field of the TX Parameters Register C (TX_PARAM_C) or if zero, EXPECT_GOODCRC bit in the TX Parameters Register A (TX_PARAM_A) is set) at the time transmission is requested. This timer can also be enabled for software usage via the EN_CRC_RCV_TMR bit in the RX Control Register A (RX_CTL_A). If enabled, the timer starts whenever a TX packet transmission stops. If software aborts a TX packet in between transmission with auto-retry mode enabled, this timer will not be triggered and will be disabled. If software aborts a TX packet with auto-retry disabled, then it should also disable the timer by clearing the EN_CRC_RCV_TMR bit in the RX Control Register A (RX_CTL_A).  2016-2017 Microchip Technology Inc. DS00002084C-page 117 UPD360 The timeout value for CRCReceiveTimer is programmable via the TRECEIVE field in the RX tReceive Time Register (RX_TRECEIVE_TIME) in multiples of 10 uSec. This timer can be used by software as the BISTReceiveErrorTimer in the BIST TX mode (the device does not automatically time BISTReceiveError) and as the CRCReceiveTimer when not using automatic retry or wait for GoodCRC modes. 11.1.8 ABORTING A TX IN PROCESS Software can abort a transmission that has already started by issuing an abort via the ABORT bit in the TX Control Register B (TX_CTL_B). The packet will be aborted as follows based on current phase of transmission: • If packet transmission had not yet started because the device was waiting for the turn-around timer to expire or line to become idle, transmission will be aborted immediately. • If the current phase is Preamble, the device will complete transfer of the current bit, append EOP, and turn the transmitter off. • If the current phase is SOP, Data, or CRC, the device will complete transfer of the current nibble, append EOP, and turn the transmitter off. A Hard Reset should follow this operation, which is the software's responsibility. 11.2 PD MAC Receiver The PD MAC receiver is comprised of three major blocks: • RX Queue • RX Control • RX Comm The RX Queue is where software reads the received messages. The RX Control implements the necessary control logic. It is responsible for validating the received packet, updating the RX Queue status, and triggering automatic responses, if required. The RX Comm is comprised of the Clock and Data Recovery (CDR), RX DES (de-serializer) (serial-to-parallel converter, 4b5b decoder, and framing detector), RX CRC32 (CRC calculator, receive timer), and other logic to detect valid packet reception. The following sub-sections describe the various blocks and sub-blocks in more detail. 11.2.1 RX QUEUE The decoded RX data (header, data objects, and CRC) is saved into an integrated 128 byte RX FIFO. The RX FIFO that is capable of storing multiple packets and provides read and write pointers. Two bytes are added to the beginning of each packet. Byte 0 holds the packet status (SOP type and the legacy “buffer” valid bit) and byte 1 holds the packet length. An option exists to swap these values (length in byte 0, status in byte 1) and add one to the packet length (to account for the status byte). This option is used for an SMBus like block read where the first byte read indicates the length of the transfer and the remaining bytes (the status and the packet) follow. Note that the packet includes the 4 byte CRC, which is included in the length. The following sub-sections present details of how the write and read interfaces to the FIFO appear. DS00002084C-page 118  2016-2017 Microchip Technology Inc. UPD360 11.2.1.1 RX FIFO Write Interface Figure 11-1 shows how the write interface (from receive hardware's perspective) appears at various points of reception. WRITE INTERFACE VIEW OF RX FIFO Ram Address 197Fh during packet reception after packet reception Ram Address 197Fh Ram Address 197Fh Free Space Free Space Free Space Free Space 1900h Packet 0 byte 0 Message Header Nbytes* Status*