USB2503/USB2503A
Integrated USB 2.0 Compatible 3-Port Hub
Highlights
• Integrated USB 2.0 Compatible 3-Port Hub
- 3 Transaction Translators for highest performance
- High-Speed (480Mbits/s), Full-Speed
(12Mbits/s) and Low-Speed (1.5Mbits/s)
compatible
- Full power management with per port or
ganged, selectable power control
- Detects Bus-Power/Self-Power source and
changes mode automatically
• Complete USB Specification 2.0 Compatibility
- Includes USB 2.0 Transceivers
• VID/PID/DID, and Port Configuration for Hub via:
- Single Serial I2C EEPROM
- SMBus Slave Port
• Default VID/PID/DID, allows functionality when
configuration EEPROM is absent
• Hardware Strapping options allow for configuration without an external EEPROM or SMBus Host
• On-Board 24MHz Crystal Driver Circuit or 24 MHz
external clock driver
• Internal PLL for 480MHz USB 2.0 Sampling
• Internal 1.8V Linear Voltage Regulator
• Integrated USB termination and Pull-up/Pull-down
resistors
• Internal Short Circuit protection of USB differential
signal pins
• 1.8 Volt Low Power Core Operation
• 3.3 Volt I/O with 5V Input Tolerance
• 48-Pin QFN RoHS compliant package
2007 - 2016 Microchip Technology Inc.
DS000002249A-page 1
USB2503/USB2503A
TO OUR VALUED CUSTOMERS
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http://www.microchip.com
You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page.
The last character of the literature number is the version number, (e.g., DS30000000A is version A of document DS30000000).
Errata
An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the
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To determine if an errata sheet exists for a particular device, please check with one of the following:
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DS000002249A-page 2
2007 - 2016 Microchip Technology Inc.
USB2503/USB2503A
Table of Contents
1.0 Introduction ..................................................................................................................................................................................... 4
2.0 Pin Table 3-Port .............................................................................................................................................................................. 5
3.0 Pin Configuration 3-Port Hub .......................................................................................................................................................... 6
4.0 3-Port Hub Block Diagram .............................................................................................................................................................. 7
5.0 Functional Block Description ......................................................................................................................................................... 12
6.0 XNOR Test .................................................................................................................................................................................... 30
7.0 DC Parameters ............................................................................................................................................................................. 31
8.0 AC Specifications .......................................................................................................................................................................... 34
9.0 Package Outline ............................................................................................................................................................................ 35
Appendix A: Data Sheet Revision History ........................................................................................................................................... 37
The Microchip Web Site ...................................................................................................................................................................... 38
Customer Change Notification Service ............................................................................................................................................... 38
Customer Support ............................................................................................................................................................................... 38
Product Identification System ............................................................................................................................................................. 40
2007 - 2016 Microchip Technology Inc.
DS000002249A-page 3
USB2503/USB2503A
1.0
INTRODUCTION
The Microchip 3-Port Hub is fully compliant with the USB 2.0 Specification and will attach to a USB host as a Full-Speed
Hub or as a Full-/High-Speed Hub. The 3-Port Hub supports Low-Speed, Full-Speed, and High-Speed (if operating as
a High-Speed Hub) downstream devices on all of the enabled downstream ports.
A dedicated Transaction Translator (TT) is available for each downstream facing port. This architecture ensures maximum USB throughput for each connected device when operating with mixed-speed peripherals.
The Hub works with an external USB power distribution switch device to control VBUS switching to downstream ports,
and to limit current and sense over-current conditions.
All required resistors on the USB ports are integrated into the Hub. This includes all series termination resistors on D+
and D– pins and all required pull-down and pull-up resistors on D+ and D– pins. The over-current sense inputs for the
downstream facing ports have internal pull-up resistors.
Throughout this document the upstream facing port of the hub will be referred to as the upstream port, and the downstream facing ports will be called the downstream ports.
1.1
OEM Selectable Features
A default configuration is available in the USB2503/USB2503A following a reset. This configuration may be sufficient
for some applications. Strapping option pins make it possible to modify a limited sub-set of the configuration options.
The USB2503/USB2503A may also be configured by an external EEPROM or a microcontroller. When using the microcontroller interface, the Hub appears as an SMBus slave device. If the Hub is pin-strapped for external EEPROM configuration but no external EEPROM is present, then a value of ‘0’ will be written to all configuration data bit fields (the
hub will attach to the host with all ‘0’ values).
The 3-Port Hub supports several OEM selectable features:
• Operation as a Self-Powered USB Hub or as a Bus-Powered USB Hub.
• Operation as a Dynamic-Powered Hub (Hub operates as a Bus-Powered device if a local power source is not
available and switches to Self-Powered operation when a local power source is available).
• Multiple Transaction Translator (Multi-TT) or Single-TT support.
• Optional OEM configuration via I2C EEPROM or via the industry standard SMBus interface from an external
SMBus Host.
• Port power switching on an individual or ganged basis.
• Port over-current monitoring on an individual or ganged basis.
• Compound device support (port is permanently hardwired to a downstream USB peripheral device).
• Hardware strapping options enable configuration of the following features.
- Non-Removable Ports
- Port Power Polarity (active high or active low logic)
- Port Disable
- Ganged Vs Port power switching and over-current sensing
DS000002249A-page 4
2007 - 2016 Microchip Technology Inc.
USB2503/USB2503A
2.0
PIN TABLE 3-PORT
TABLE 2-1:
3-PORT PIN TABLE
UPSTREAM USB 2.0 INTERFACE (3-PINS)
USBDP0
USBDN0
VBUS_DET
3-PORT USB INTERFACE (18-PINS)
USBDP1
USBDN1
USBDP2
USBDN2
USBDP3
USBDN3
GR1/
NON_REM0
GR2/
NON_REM1
GR3/
PRT_DIS0
PRTPWR1
PRTPWR2
PRTPWR3
PRTPWR_POL
OCS1_N
OCS2_N
OCS3_N
GANG_EN
RBIAS
SERIAL PORT (3-PINS)
SDA/SMBDATA
SCL/SMBCLK/CFG_SEL0
CFG_SEL1
MISC (8-PINS)
XTAL1/CLKIN
XTAL2
RESET_N
SELF_PWR
TEST1
TEST0
ATEST/
REG_EN
CLKIN_EN
POWER & GROUNDS (16-PINS)
2007 - 2016 Microchip Technology Inc.
DS000002249A-page 5
USB2503/USB2503A
PIN CONFIGURATION 3-PORT HUB
TEST1
CLKIN_EN
OCS1_N
PRTPWR1
OCS2_N
VDD18
VSS
VBUS_DET
SELF_PWR
CFG_SEL1
SCL/SMBCLK/CFG_SEL0
SDA/SMBDATA
35
34
33
32
31
30
29
28
27
26
25
3-PORT 48-PIN QFN
36
FIGURE 3-1:
RESET_N
37
24
TEST0
VSS
38
23
VDD18
VDD33CR
39
22
VSS
VDD18
40
21
GR1/NON_REM0
VSS
41
20
GANG_EN
XTAL2
42
19
GR2/NON_REM1
XTAL1/CLKIN
43
18
PRTPWR_POL
VDDA18PLL
44
17
GR3/PRT_DIS0
VDDA33PLL
45
16
PRTPWR2
ATEST/REG_EN
46
15
OCS3_N
RBIAS
47
14
PRTPWER3
VSS
48
13
VDDA33
SMSC
USB2503
&
USB2503A
(Top View QFN-48)
MICROCHIP
7
8
9
VDDA33
USBDP2
USBDN2
12
6
USBDP1
USBDP3
5
USBDN1
11
4
VSS
USBDN3
3
USBDN0
10
2
USBDP0
VSS
1
Thermal Slug
(must be connected to VSS)
VDDA33
3.0
Indicates pins on the bottom of the device.
DS000002249A-page 6
2007 - 2016 Microchip Technology Inc.
USB2503/USB2503A
4.0
3-PORT HUB BLOCK DIAGRAM
FIGURE 4-1:
3-PORT BLOCK DIAGRAM
Upstream Upstream 24 MHz
USB Data
VBUS
Crystal
Upstream
PHY
VBUS
Power
Detect
3.3V
To
EEPROM
Pin
1.8V Strapping or SMBus
Master
Cap Options
SD SCL
Internal
Defaults
Select
1.8V
Reg.
PLL
Controller
SIE
Repeater
TT
#1
Serial
Interface
TT
#2
TT
#3
Port
Controller
Routing Logic
Port #1
Downstream
OC Sense
PHY #1
Switch Driver
LED Drivers
...
Downstream OC Switch/LED
USB Data Sense Drivers
2007 - 2016 Microchip Technology Inc.
Port #3
Downstream
OC Sense
PHY #3
Switch Driver
LED Drivers
Downstream
USB Data
OC Switch/LED
Sense Drivers
DS000002249A-page 7
USB2503/USB2503A
TABLE 4-1:
3-PORT HUB PIN DESCRIPTIONS
Name
Symbol
Type
Function
USB Bus Data
USBDN0
USBDP0
IO-U
These pins connect to the USB bus data signals.
Detect Upstream
VBUS Power
VBUS_DET
I/O12
Detects state of Upstream VBUS power (indicates the powermanaged state of the upstream device).
UPSTREAM USB 2.0 INTERFACE
3-PORT USB 2.0 HUB INTERFACE
High-Speed USB
Data
USBDN[3:1]
USBDP[3:1]
IO-U
These pins connect to the downstream USB peripheral
devices attached to the Hub’s ports.
USB Power Enable
PRTPWR[3:1]
O12
Enables power to USB peripheral devices (downstream).
The active signal level of the PRTPWR[3:1] pins are
determined by the Power Polarity Strapping function of the
PRTPWR_POL pin.
Port 3 Green LED
&
Port Disable
strapping option.
GR3/
PRT_DIS0
I/O12
Green indicator LED for port 3. Will be active low when LED
support is enabled via EEPROM or SMBus.
If the hub is configured by the internal default configuration,
these pins will be sampled at RESET_N negation to
determine if port 3 will be permanently disabled. Also, the
active state of the LED will be determined as follows:
PRT_DIS0 = ‘0’, All ports are enabled,
GR3 is active high.
PRT_DIS0 = ‘1’, Port 3 is disabled,
GR3 is active low.
Port [2:1] Green
LED
&
Port NonRemovable
strapping option.
GR[2:1]/
NON_REM[1:0]
I/O12
Green indicator LED for ports 2 and 1. Will be active low
when LED support is enabled via EEPROM or SMBus.
If the hub is configured by the internal default configuration,
these pins will be sampled at RESET_N negation to
determine if ports [3:1] contain permanently attached (nonremovable) devices. Also, the active state of the LED’s will be
determined as follows:
NON_REM[1:0] = ‘00’, All ports are removable,
GR2 is active high,
GR1 is active high.
NON_REM1:0] = ‘01’, Port 1 is non-removable,
GR2 is active high,
GR1 is active low.
NON_REM[1:0] = ‘10’, Ports 1 & 2 are non-removable,
GR2 is active low,
GR1 is active high.
NON_REM[1:0] = ‘11’, Ports 1, 2, & 3 are non-removable,
GR2 is active low,
GR1 is active low.
Gang Power
Switching and
Current Sensing
strapping option.
GANG_EN
I/O12
If the hub is configured by the internal default configuration,
this pin will be sampled at RESET_N negation to determine
if downstream port power switching and current sensing are
ganged, or individual port-by-port.
‘0’ = Port-by-port sensing & switching.
‘1’ = Ganged sensing & switching.
DS000002249A-page 8
2007 - 2016 Microchip Technology Inc.
USB2503/USB2503A
TABLE 4-1:
3-PORT HUB PIN DESCRIPTIONS (CONTINUED)
Name
Symbol
Type
Port Power Polarity
strapping.
PRTPWR_POL
I/O12
Function
Port Power Polarity strapping determination for the active
signal polarity of the PRTPWR[3:1] pins.
While RESET_N is asserted, the logic state of this pin will
(though the use of internal combinatorial logic) determine the
active state of the PRTPWR[3:1] pins in order to ensure that
downstream port power is not inadvertently enabled to
inactive ports during a hardware reset.
When RESET_N is negated, the logic value will be latched
internally, and will retain the active signal polarity for
PRTPWR[3:1] pins.
‘1’ = PRTPWR[3:1] pins have an active ‘high’ polarity
‘0’ = PRTPWR[3:1] pins have an active ‘low’ polarity
Over Current
Sense
OCS[3:1]_N
IPU
Input from external current monitor indicating an over-current
condition. {Note: Contains internal pull-up to 3.3V supply}
USB Transceiver
Bias
RBIAS
I-R
A 12.0k (resistor is attached from ground to this pin
to set the transceiver’s internal bias settings.
SERIAL PORT INTERFACE
Serial Data/SMB
Data
SDA/SMBDATA
IOSD12
(Serial Data)/(SMB Data) signal.
Serial Clock/SMB
Clock
&
Chip Select /
EEPROM Select
SCL/SMBCLK/
CFG_SEL0
IOSD12
(Serial Clock)/(SMB Clock) signal. This multifunction pin is
read on the rising edge of RESET_N negation and will
determine the hub configuration method as described in
TABLE 4-2:.
SMB Programming
Select
CFG_SEL1
I
TABLE 4-2:
This pin is read on the rising edge of RESET_N negation and
will determine the hub configuration method as described in
TABLE 4-2:.
SMBUS OR EEPROM INTERFACE BEHAVIOR
CFG_SEL1
CFG_SEL0
0
X
Configured as an SMBus slave for external download of user-defined
descriptors. SMBus slave address is: 0101101
1
0
Internal Default Configuration via strapping options.
1
1
2-wire (I2C) EEPROMS are supported, and CFG_SEL0 has no other
functionality.
TABLE 4-3:
SMBus or EEPROM Interface Behavior
MISCELLANEOUS PINS
Name
Symbol
Type
Function
Crystal
Input/External
Clock Input
XTAL1/
CLKIN
ICLKx
24MHz crystal or external clock input.
This pin connects to either one terminal of the crystal or to
an external 24MHz clock when a crystal is not used.
Crystal Output
XTAL2
OCLKx
24MHz Crystal
This is the other terminal of the crystal, or left unconnected
when an external clock source is used to drive
XTAL1/CLKIN. It must not be used to drive any external
circuitry other than the crystal circuit.
Clock Input
Enable
CLKIN_EN
I
2007 - 2016 Microchip Technology Inc.
Clock In Enable:
Low = XTAL1 and XTAL2 pins configured for use with
external crystal
High = XTAL1 pin configured as CLKIN, and must be
driven by an external CMOS clock.
DS000002249A-page 9
USB2503/USB2503A
TABLE 4-3:
MISCELLANEOUS PINS (CONTINUED)
Name
Symbol
Type
Function
RESET Input
RESET_N
IS
This active low signal is used by the system to reset the
chip. The minimum active low pulse is 100ns.
Self-Power /
Bus-Power
Detect
SELF_PWR
I
Detects availability of local self-power source.
Low = Self/local power source is NOT available (i.e., 7Port Hub gets all power from Upstream USB VBus).
High = Self/local power source is available.
TEST Pins
TEST[1:0]
IPD
Used for testing the chip. User must treat as a no-connect
or connect to ground. For board testing, all signal pins are
included in an XNOR chain, Please see 6.0, "XNOR Test,"
on page 30 for more details on the configuration and use
of the XNOR mode.
Analog Test
&
Internal 1.8V
voltage regulator
enable
ATEST/
REG_EN
AIO
This signal is used for testing the analog section of the
chip, and to enable or disable the internal 1.8v regulator.
This pin must be connected to VDDA3P3 to enable the
internal 1.8V regulator, or to VSS to disable the internal
regulator.
When the internal regulator is enabled, the 1.8V power
pins must be left unconnected, except for the required
bypass capacitors.When the PHY is in test mode, the
internal regulator is disabled and the ATEST pin functions
as a test pin.
TABLE 4-4:
POWER, GROUND, AND NO CONNECT
Name
Symbol
VDD1P8
VDD18
Type
Function
+1.8V core power.
If the internal regulator is enabled, then VDD18 pin
closest to VDD33CR must have a 4.7F (or greater) ±20%
(ESR
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