USB3330E-GL-TR

USB333x Industry’s Smallest Hi-Speed USB Transceiver with Single Supply Operation Highlights • USB-IF Battery Charging 1.2 Specification Compliant • Link Power Management (LPM) Compliant • Integrated ESD protection circuits • Up to ±25kV IEC Air Discharge without external devices • Over-Voltage Protection circuit (OVP) protects the VBUS pin from continuous DC voltages up to 30V • Integrated USB Switch (USB3331, USB3336, and USB3338) - No degradation of Hi-Speed electrical characteristics - Allows single USB port of connection by providing switching function for: - Battery charging - Stereo and mono/mic audio - USB Full-Speed/Low-Speed data • RapidCharge Anywhere™ Provides: - 3-times the charging current through a USB port over traditional solutions - USB-IF Battery Charging 1.2 compliance to any portable device - Charging current up to 1.5Amps via compatible USB host or dedicated charger - Dedicated Charging Port (DCP), Charging (CDP) & Standard (SDP) Downstream Port support • flexPWR® Technology - Extremely low current design ideal for battery powered applications - “Sleep” mode tri-states all ULPI pins and places the part in a low current state - 1.8V to 3.3V IO Voltage (USB3333) • Single Power Supply Operation - Integrated 1.8V regulator - Integrated battery to 3.3V regulator - 100mV dropout voltage • PHYBoost - Programmable USB transceiver drive strength for recovering signal integrity • VariSenseTM - Programmable USB receiver sensitivity  2009 - 2015 Microchip Technology Inc. • “Wrapper-less” design for optimal timing performance and design ease - Low Latency Hi-Speed Receiver (43 HiSpeed clocks Max) allows use of legacy UTMI Links with a ULPI bridge • External Reference Clock operation available - ULPI Clock In Mode (60MHz sourced by Link) - 0 to 3.6V input drive tolerant - Able to accept “noisy” clock sources as reference to internal, low-jitter PLL - USB3330 and USB3333 support multiple frequencies • Smart detection circuits allow identification of USB charger, headset, or data cable insertion • Includes full support for the optional On-The-Go (OTG) protocol detailed in the On-The-Go Supplement Revision 2.0 specification • Supports the OTG Host Negotiation Protocol (HNP) and Session Request Protocol (SRP) • UART mode for non-USB serial data transfers • Internal 5V cable short-circuit protection of ID, DP and DM lines to VBUS or ground • Industrial Operating Temperature -40°C to +85°C • 25 ball, WLCSP RoHS Compliant package (1.97 x 1.97 x 0.53 mm height) Applications The USB333x is the solution of choice for any application where a Hi-Speed USB connection is desired and when board space, power, and interface pins must be minimized. • • • • • • • • • • • • • • Cell Phones PDAs MP3 Players GPS Personal Navigation Scanners External Hard Drives Digital Still and Video Cameras Portable Media Players Entertainment Devices Printers Set Top Boxes Video Record/Playback Systems IP and Video Phones Gaming Consoles DS00001880A-page 1 USB333x TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced. If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via E-mail at docerrors@microchip.com. We welcome your feedback. Most Current Data Sheet To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at: http://www.microchip.com You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page. The last character of the literature number is the version number, (e.g., DS30000000A is version A of document DS30000000). Errata An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of silicon and revision of document to which it applies. To determine if an errata sheet exists for a particular device, please check with one of the following: • Microchip’s Worldwide Web site; http://www.microchip.com • Your local Microchip sales office (see last page) When contacting a sales office, please specify which device, revision of silicon and data sheet (include -literature number) you are using. Customer Notification System Register on our web site at www.microchip.com to receive the most current information on all of our products. DS00001880A-page 2  2009 - 2015 Microchip Technology Inc. USB333x Table of Contents 1.0 Introduction ..................................................................................................................................................................................... 4 2.0 USB333x Pin Locations and Definitions ........................................................................................................................................ 8 3.0 Limiting Values .............................................................................................................................................................................. 14 4.0 Electrical Characteristics ............................................................................................................................................................... 15 5.0 Architecture Overview ................................................................................................................................................................... 22 6.0 ULPI Operation ............................................................................................................................................................................. 40 7.0 ULPI Register Map ........................................................................................................................................................................ 58 8.0 Application Notes .......................................................................................................................................................................... 70 9.0 Package Outlines, Tape & Reel Drawings, Package Marking ...................................................................................................... 75 Appendix A: Data Sheet Revision History ........................................................................................................................................... 80 Product Identification System ............................................................................................................................................................. 82 The Microchip Web Site ...................................................................................................................................................................... 83 Customer Change Notification Service ............................................................................................................................................... 83 Customer Support ............................................................................................................................................................................... 83  2009 - 2015 Microchip Technology Inc. DS00001880A-page 3 USB333x 1.0 INTRODUCTION 1.1 General Description Microchip’s USB333x is a family of High Speed USB 2.0 Transceivers that provides a physical layer (PHY) solution wellsuited for portable electronic devices. Both commercial and industrial temperature applications are supported. Each model in the USB333x family may use a 60MHz reference clock or the model-number specific reference clock as shown on the Product Identification System page. The USB3330 and USB3333 can support several different frequencies driven on the REFCLK pin. The configuration of the frequency selection pins set the desired reference frequency. Several advanced features make the USB333x the transceiver of choice by reducing both eBOM part count and printed circuit board (PCB) area. Outstanding ESD robustness eliminates the need for external ESD protection devices in typical applications. The internal Over-Voltage Protection circuit (OVP) protects the USB333x from voltages up to 30V on the VBUS pin. By using a reference clock from the Link, the USB333x removes the cost of a dedicated crystal reference from the design. The USB333x includes integrated 3.3V and 1.8V regulators, making it possible to operate the device from a single power supply. The USB333x is optimized for use in portable applications where a low operating current and standby current is essential. The USB333x also supports the Link Power Management protocol (LPM) to further reduce USB operating currents. The USB333x also includes integrated battery charger detection circuitry. These circuits are used to detect the attachment of a USB Charger as described in Section 5.8. By sensing the attachment to a USB Charger, a product using the USB333x can draw more than 500mA from the USB connector. The USB333x meets all of the electrical requirements for a High Speed USB Host, Device, or an On-the-Go (OTG) transceiver. In addition to the supporting USB signaling, the USB333x also provides USB UART mode and, in versions with the integrated USB switch, USB Audio mode. USB333x uses the industry standard UTMI+ Low Pin Interface (ULPI) to connect the USB PHY to the Link. ULPI uses a method of in-band signaling and status byte transfers between the Link and PHY to facilitate a USB session with only twelve pins. The USB333x uses Microchip’s “wrapper-less” technology to implement the ULPI interface. This “wrapper-less” technology allows the PHY to achieve a low latency transmit and receive time. Microchip’s low latency transceiver allows an existing UTMI Link to be reused by adding a UTMI to ULPI bridge. By adding a bridge to the ASIC the existing and proven UTMI Link IP can be reused. Versions of the USB333x with the integrated USB switch enable a single USB port of connection. DS00001880A-page 4  2009 - 2015 Microchip Technology Inc. USB333x 1.2 Block Diagrams FIGURE 1-1: BLOCK DIAGRAM (USB3331, USB3336, AND USB3338) REFCLK OVP ID DP ESD Protection VBUS DM OTG Hi-Speed USB Transceiver SPK_R SPK_L USB DP/DM Switch Low Jitter Integrated PLL ULPI Registers and State Machine BIAS RBIAS Integrated Power Management RESETB VBAT VDD33 VDD18 ULPI Interface STP NXT DIR CLKOUT DATA[7:0] In USB Audio mode, a switch connects the DP pin to the SPK_R pin, and another switch connects he DM pin to the SPK_L pin. These switches are shown in the lower left-hand corner of Figure 5-1.The USB333x can be configured to enter USB Audio mode as described in Section 6.7.2. In addition, these switches are on when the RESETB pin of the USB333x is asserted. The USB Audio mode enables audio signaling from a single USB port of connection, and the switches may also be used to connect Full Speed USB from another transceiver to the USB connector.  2009 - 2015 Microchip Technology Inc. DS00001880A-page 5 USB333x OVP ID DP OTG ESD Protection VBUS Hi-Speed USB Transceiver DM REF[1:0] BLOCK DIAGRAM (USB3330) REFCLK FIGURE 1-2: Low Jitter Integrated PLL ULPI Registers and State Machine BIAS RBIAS Integrated Power Management RESETB VBAT VDD33 VDD18 ULPI Interface STP NXT DIR CLKOUT DATA[7:0] OVP ID DP ESD Protection VBUS DM OTG Hi-Speed USB Transceiver REF[0] BLOCK DIAGRAM (USB3333) REFCLK FIGURE 1-3: Low Jitter Integrated PLL ULPI Registers and State Machine BIAS Integrated Power Management RBIAS RESETB VBAT VDD33 VDD18 VDDIO ULPI Interface STP NXT DIR CLKOUT DATA[7:0] DS00001880A-page 6  2009 - 2015 Microchip Technology Inc. USB333x The USB333x includes an integrated 3.3V LDO regulator that is used to generate 3.3V from power applied to the VBAT pin. The voltage on the VBAT pin can range from 3.0 to 5.5V. The regulator dropout voltage is less than 100mV which allows the PHY to continue USB signaling when the voltage on VBAT drops to 3.0V. The USB transceiver will continue to operate at lower voltages, although some parameters may be outside the limits of the USB-IF specification for Full Speed USB operation. The VBAT and VDD33 pins should never be connected together. In USB UART mode, the USB333x DP and DM pins are redefined to enable pass-through of asynchronous serial data. The USB333x will enter UART mode when programmed, as described in Section 6.7.1. 1.3 Reference Documents UTMI+ Low Pin Interface (ULPI) Specification, Revision 1.1 Universal Serial Bus Specification, Revision 2.0 On-The-Go Supplement to the USB2.0 Specification, Revision 1.3 On-The-Go Supplement to the USB2.0 Specification, Revision 2.0 USB Battery Charging Specification, Revision 1.2  2009 - 2015 Microchip Technology Inc. DS00001880A-page 7 USB333x 2.0 USB333X PIN LOCATIONS AND DEFINITIONS 2.1 Package Diagram with Ball Locations The illustration below is viewed from the top of the package. FIGURE 2-1: USB3331, USB3336, AND USB3338 BALL LOCATIONS - TOP VIEW 1 2 3 4 5 A RBIAS REFCLK STP DIR CLKOUT B ID RESETB VDD18 DATA[0] NXT C VBAT VBUS GND DATA[2] DATA[1] D DM VDD33 DATA[7] DATA[4] DATA[3] E DP SPK_R SPK_L DATA[6] DATA[5] TOP VIEW FIGURE 2-2: USB3330 BALL LOCATIONS - TOP VIEW 1 2 3 4 5 A RBIAS REFCLK STP DIR CLKOUT B ID RESETB VDD18 DATA[0] NXT C VBAT VBUS GND DATA[2] DATA[1] D DM VDD33 DATA[7] DATA[4] DATA[3] E DP REF[0] REF[1] DATA[6] DATA[5] TOP VIEW DS00001880A-page 8  2009 - 2015 Microchip Technology Inc. USB333x FIGURE 2-3: USB3333 BALL LOCATIONS - TOP VIEW 1 2 3 4 5 A RBIAS REFCLK STP DIR CLKOUT B ID VDD18 VDDIO DATA[0] NXT C VBAT RESETB GND DATA[2] DATA[1] D DM VBUS VDD33 DATA[4] DATA[3] E DP REF[0] DATA[7] DATA[6] DATA[5] TOP VIEW 2.2 Ball Definitions The following table details the ball definitions for the figure above. TABLE 2-1: USB3331, USB3336, AND USB3338 PIN DESCRIPTION Ball Name Direction/ Type Active Level B1 ID Input, Analog N/A For device applications the ID pin is connected to VDD33. For Host applications ID is grounded. For OTG applications the ID pin is connected to the USB connector. C2 VBUS I/O, Analog N/A This pin is used for the VBUS comparator inputs and for VBUS pulsing during session request protocol. An external resistor, RVBUS, is required between this pin and the USB connector. C1 VBAT Power N/A Regulator input. The regulator supply can be from 5.5V to 3.0V. D2 VDD33 Power N/A 3.3V Regulator Output. A 1.0uF ( 3.0V 2.47 2.75 3.03 V USB UART Mode & UART RegOutput[1:0] = 11 5.5V > VBAT > 3.0V 2.25 2.5 2.75 V 1.0 3.6V > VDD33 > 2.8V 1.6 uF 1.8 1 Ω 2.0 V 1.0 uF 1 Ω  2009 - 2015 Microchip Technology Inc. USB333x 4.12 ESD and Latch-Up Performance TABLE 4-13: Parameter ESD AND LATCH-UP PERFORMANCE Conditions MIN TYP MAX Units Comments ESD PERFORMANCE Note 4-10, Note 4-11 Human Body Model ±8 kV Device System EN/IEC 61000-4-2 Contact Discharge ±25 kV 3rd party system test System EN/IEC 61000-4-2 Air-gap Discharge ±25 kV 3rd party system test LATCH-UP PERFORMANCE All Pins EIA/JESD 78, Class II 150 mA Note 4-10 USB3331, USB3336, and USB3338: REFCLK, RESETB, VBUS, SPK_L and SPK_R pins: ±5kV Human Body Model Note 4-11 USB3330 and USB3333: REFCLK, RESETB, VBUS, REF[1] and REF[0] pins: ±5kV Human Body Model  2009 - 2015 Microchip Technology Inc. DS00001880A-page 21 USB333x 5.0 ARCHITECTURE OVERVIEW The USB333x consists of the blocks shown in the diagram below. FIGURE 5-1: USB333X SYSTEM DIAGRAM (USB3331, USB3336, AND USB3338) VDD18 Digital IO VDD33 DATA7 DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 DATA0 STP NXT DIR CLKOUT RESETB HS/FS/LS TX Encoding Integrated Low Jitter PLL REFCLK HS/FS/LS RX Decoding BIAS RID IdFloat Rid Value VDD33 SessValid RVPD LDO ULPI Digitial VbusValid Charger Detection RPU VDD33 RPU RCD VDD33 RCD VDD18 ESD Protection LDO RVB VBAT VDD33 SessEnd RX Data RVPU OVP VBUS TX Data ID OTG Module RIDW IdGnd TX DP RPD SPK_L RPD DM RX RBIAS SPK_R DS00001880A-page 22  2009 - 2015 Microchip Technology Inc. USB333x FIGURE 5-2: USB333X SYSTEM DIAGRAM (USB3330) VDD18 VDD33 RID Rid Value VDD33 RVPU OVP SessValid RVPD LDO ULPI Digitial VbusValid Charger Detection REF[1] REF[0] RPU VDD33 RPU RCD VDD33 RCD VDD18 ESD Protection LDO RVB VBAT VDD33 SessEnd TX DP DATA7 DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 DATA0 STP NXT DIR CLKOUT RESETB RX Data VBUS TX Data ID Digital IO IdFloat OTG Module RIDW IdGnd HS/FS/LS TX Encoding Integrated Low Jitter PLL HS/FS/LS RX Decoding BIAS REFCLK  2009 - 2015 Microchip Technology Inc. RPD RPD DM RX RBIAS DS00001880A-page 23 USB333x FIGURE 5-3: USB333X SYSTEM DIAGRAM (USB3333) VDD33 RID Rid Value VDD33 SessValid RVPD LDO ULPI Digitial VbusValid Charger Detection VDD33 REF[0] RPU RPU RCD VDD33 RCD VDD18 ESD Protection LDO RVB VBAT VDD33 SessEnd VDDIO DATA7 DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 DATA0 STP NXT DIR CLKOUT RESETB RX Data RVPU OVP TX Data VBUS Digital IO IdFloat ID OTG Module RIDW IdGnd TX DP HS/FS/LS TX Encoding Integrated Low Jitter PLL HS/FS/LS RX Decoding BIAS REFCLK 5.1 RPD RPD DM RX RBIAS ULPI Digital Operation and Interface This section of the USB333x is covered in detail in Section 6.0, "ULPI Operation". 5.2 USB 2.0 High Speed Transceiver The blocks in the lower left-hand corner of Figure 5-1 interface to the DP/DM pins. 5.2.1 USB TRANSCEIVER The USB333x transceiver includes a Universal Serial Bus Specification Rev 2.0 compliant receiver and transmitter. The DP/DM signals in the USB cable connect directly to the receivers and transmitters. The receiver consists of receivers for HS and FS/LS mode. Depending on the mode, the selected receiver provides the serial data stream through the multiplexer to the RX Logic block. For HS mode support, the HS RX block contains a squelch circuit to insure that noise is not interpreted as data. The RX block also includes a single-ended receiver on each of the data lines to determine the correct FS linestate. Data from the Link is encoded, bit stuffed, serialized and transmitted onto the USB cable by the transmitter. Separate differential FS/LS and HS transmitters are included to support all modes. The USB333x TX block meets the HS signalling level requirements in the USB 2.0 Specification when the PCB traces from the DP and DM pins to the USB connector are correctly designed. In some systems the proper 90 ohm differential impedance can not be maintained and it may be desirable to compensate for loss by adjusting the HS transmitter amplitude and this HS squelch threshold. The PHYBoost bits in the HS Compensation Register may be configured to adjust the HS transmitter amplitude at the DP and DM pins. The VariSense bits in the HS Compensation Register can also be used to lower the squelch threshold to compensate for losses on the PCB. To ensure proper operation of the USB transceiver the settings of Table 5-1 must be followed. DS00001880A-page 24  2009 - 2015 Microchip Technology Inc. USB333x 5.2.2 TERMINATION RESISTORS The USB333x transceiver fully integrates all of the USB termination resistors on both DP and DM. This includes 1.5kΩ pull-up resistors, 15kΩ pull-down resistors and the 45Ω High Speed termination resistors. These resistors require no tuning or trimming by the Link. The state of the resistors is determined by the operating mode of the transceiver when operating in synchronous mode. The XcvrSelect[1:0], TermSelect and OpMode[1:0] bits in the Function Control register, and the DpPulldown and DmPulldown bits in the OTG Control register control the configuration of the termination resistors. All possible valid resistor combinations are shown in Table 5-1, and operation is ensured in only the configurations shown. If a ULPI Register Setting is configured that does not match a setting in the table, the transceiver operation is not ensured and the settings in the last row of Table 5-1 will be used. RPU_DP_EN activates the 1.5kΩ DP pull-up resistor RPU_DM_EN activates the 1.5kΩ DM pull-up resistor RPD_DP_EN activates the 15kΩ DP pull-down resistor RPD_DM_EN activates the 15kΩ DM pull-down resistor HSTERM_EN activates the 45Ω DP and DM High Speed termination resistors DP/DM TERMINATION VS. SIGNALING MODE HSTERM_EN RPU_DP_EN DmPulldown DpPulldown OpMode[1:0] TermSelect XcvrSelect[1:0] Signaling Mode RPD_DM_EN USB333x Termination Resistor Settings ULPI Register Settings RPD_DP_EN TABLE 5-1: RPU_DM_EN • • • • • General Settings Tri-State Drivers, Note 5-1 XXb Xb 01b Xb Xb 0b 0b 0b 0b 0b Power-up or VBUS < VSESSEND 01b 0b 00b 1b 1b 0b 0b 1b 1b 0b Host Settings Host Chirp 00b 0b 10b 1b 1b 0b 0b 1b 1b 1b Host High Speed 00b 0b 00b 1b 1b 0b 0b 1b 1b 1b Host Full Speed X1b 1b 00b 1b 1b 0b 0b 1b 1b 0b Host HS/FS Suspend 01b 1b 00b 1b 1b 0b 0b 1b 1b 0b Host HS/FS Resume 01b 1b 10b 1b 1b 0b 0b 1b 1b 0b Host Low Speed 10b 1b 00b 1b 1b 0b 0b 1b 1b 0b Host LS Suspend 10b 1b 00b 1b 1b 0b 0b 1b 1b 0b Host LS Resume 10b 1b 10b 1b 1b 0b 0b 1b 1b 0b Host Test J/Test_K 00b 0b 10b 1b 1b 0b 0b 1b 1b 1b Peripheral Chirp 00b 1b 10b 0b 0b 1b 0b 0b 0b 0b Peripheral HS 00b 0b 00b 0b 0b 0b 0b 0b 0b 1b Peripheral Settings Peripheral FS 01b 1b 00b 0b 0b 1b 0b 0b 0b 0b Peripheral HS/FS Suspend 01b 1b 00b 0b 0b 1b 0b 0b 0b 0b Peripheral HS/FS Resume 01b 1b 10b 0b 0b 1b 0b 0b 0b 0b Peripheral LS 10b 1b 00b 0b 0b 0b 1b 0b 0b 0b Peripheral LS Suspend 10b 1b 00b 0b 0b 0b 1b 0b 0b 0b Peripheral LS Resume 10b 1b 10b 0b 0b 0b 1b 0b 0b 0b Peripheral Test J/Test K 00b 0b 10b 0b 0b 0b 0b 0b 0b 1b OTG device, Peripheral Chirp 00b 1b 10b 0b 1b 1b 0b 0b 1b 0b OTG device, Peripheral HS 00b 0b 00b 0b 1b 0b 0b 0b 1b 1b  2009 - 2015 Microchip Technology Inc. DS00001880A-page 25 USB333x DP/DM TERMINATION VS. SIGNALING MODE (CONTINUED) HSTERM_EN RPD_DM_EN RPU_DP_EN DmPulldown DpPulldown OpMode[1:0] TermSelect XcvrSelect[1:0] Signaling Mode RPD_DP_EN USB333x Termination Resistor Settings ULPI Register Settings RPU_DM_EN TABLE 5-1: OTG device, Peripheral FS 01b 1b 00b 0b 1b 1b 0b 0b 1b 0b OTG device, Peripheral HS/FS Suspend 01b 1b 00b 0b 1b 1b 0b 0b 1b 0b OTG device, Peripheral HS/FS Resume 01b 1b 10b 0b 1b 1b 0b 0b 1b 0b OTG device, Peripheral Test J/Test K 00b 0b 10b 0b 1b 0b 0b 0b 1b 1b 01b 0b 00b 0b 1b 0b 0b 0b 1b 0b 0b 0b 1b 1b 0b Charger Detection Connect Detect Any combination not defined above, Note 52 Note 1: This is equivalent to Table 40, Section 4.4 of the ULPI 1.1 specification. 2: USB333x does not support operation as an upstream hub port. See Section 6.4.1.3, "UTMI+ Level 3". Note 5-1 When RESETB = 0 The HS termination will tri-state the USB drivers. Note 5-2 The transceiver operation is not ensured in a combination that is not defined. The USB333x uses the 27% resistor ECN resistor tolerances. The resistor values are shown in Table 4-6. 5.3 Bias Generator This block consists of an internal bandgap reference circuit used for generating the driver current and the biasing of the analog circuits. This block requires an external 8.06KΩ, 1% tolerance, reference resistor connected from RBIAS to ground. This resistor should be placed as close as possible to the USB333x to minimize the trace length. The nominal voltage at RBIAS is 0.8V +/- 10% and therefore the resistor will dissipate approximately 80μW of power. 5.4 Integrated Low Jitter PLL The USB333x uses an integrated low jitter phase locked loop (PLL) to provide a clean 480MHz clock required for HS USB signal quality. This clock is used by the PHY during both transmit and receive. The USB333x PLL requires an accurate frequency reference to be driven on the REFCLK pin. 5.4.1 REFCLK FREQUENCY SELECTION The USB333x PLL is designed to operate in one of two reference clock modes. In the first mode, the 60MHz ULPI clock is driven on the REFCLK pin. In the second mode a reference clock is driven on the REFCLK pin. The Link is driving the ULPI clock, in the first mode, and this is referred to as ULPI Clock In Mode. In the second mode, the USB333x generates the ULPI clock, and this is referred to as ULPI Clock Out Mode. During start-up, the USB333x monitors the CLKOUT pin. If a connection to VDD18 (USB3330, USB3331, USB3336, and USB3338) or VDDIO (USB3333) is detected, the USB333x is configured for a 60MHz ULPI reference clock driven on the REFCLK pin. Section 5.4.1.2 and Section 5.4.1.1 describe how to configure the USB333x for either ULPI Clock In Mode or ULPI Clock Out Mode. For the USB3331, USB3336, and USB3338, the reference clock frequency required is shown on the Product Identification System page. For the USB3330 and USB3333, the reference clock frequency required is determined by the settings of the REF pins(s). The pins should either be connected to VDD33 or GND. The reference frequency selection options are shown in Table 5-2 and Table 5-3. DS00001880A-page 26  2009 - 2015 Microchip Technology Inc. USB333x TABLE 5-2: REF[1:0] VS. REQUIRED FREQUENCY AT REFCLK (USB3330) REF[1:0] REFCLK Frequency 00 19.2 MHz 01 26 MHz 10 13 MHz 11 24 MHz TABLE 5-3: 5.4.1.1 REF[0] VS. REQUIRED FREQUENCY AT REFCLK (USB3333) REF[0] REFCLK Frequency 0 19.2 MHz 1 26 MHz ULPI Clock Output Mode When using ULPI Clock Output Mode, the USB333x generates the 60MHz ULPI clock used by the Link. In this mode, the REFCLK pin must be driven with the model-specific frequency, and the CLKOUT pin sources the 60MHz ULPI clock to the Link. When using ULPI Clock Output Mode, the system must not drive the CLKOUT pin following POR or hardware reset with a voltage that exceeds the value of VIH_ED provided in Table 4-4. An example of ULPI Clock Out Mode is shown in Figure 8-1 After the PLL has locked to the correct frequency, the USB333x generates the 60MHz ULPI clock on the CLKOUT pin, and de-asserts DIR to indicate that the PLL is locked. The USB333x is set to start the clock within the time specified in Table 4-3, and it will be accurate to within ±500ppm. For Host applications the ULPI AutoResume bit should be enabled. This is described in Section 6.4.1.4. When using ULPI Clock Output Mode, the edges of the reference clock do not need to be aligned in any way to the ULPI interface signals. There is no need to align the phase of the REFCLK and the CLKOUT. FIGURE 5-4: CONFIGURING THE USB333X FOR ULPI CLOCK OUTPUT MODE ~~ ULPI Clk In CLKOUT From PLL Link Clock Source REFCLK To PLL ~~  2009 - 2015 Microchip Technology Inc. PHY DS00001880A-page 27 USB333x 5.4.1.2 ULPI Clock Input Mode (60MHz REFCLK Mode) When using ULPI Clock Input Mode, the Link must supply the 60MHz ULPI clock to the USB333x. In this mode the 60MHz ULPI Clock is connected to the REFCLK pin, and the CLKOUT pin is tied high to VDD18 (USB3330, USB3331, USB3336, and USB3338) or VDDIO (USB3333). An example of ULPI Clock In Mode is shown in Figure 8-2. After the PLL has locked to the correct frequency, the USB333x will de-assert DIR and the Link can begin using the ULPI interface. The USB333x is set to start the clock within the time specified in Table 4-3. For Host applications, the ULPI AutoResume bit should be enabled. This is described in Section 6.4.1.4. For the USB3330 and USB3333, the REF pin(s) should be tied to ground. FIGURE 5-5: CONFIGURING THE USB333X FOR ULPI CLOCK INPUT MODE VDD18/ VDDIO ~~ CLKOUT REFCLK ULPI Clk Out To PLL Link Reference Clk In 5.4.2 PHY ~~ Clock Source REFCLK AMPLITUDE The reference clock should be connected to the REFCLK pin as shown in the application diagrams, Figure 8-1 and Figure 8-2. The REFCLK pin is designed to be driven with a square wave from 0V to VDD18, but can be driven with a square wave from 0V to as high as 3.6V. The USB333x uses only the positive edge of the REFCLK. If a digital reference is not available, the REFCLK pin can be driven by an analog sine wave that is AC coupled into the REFCLK pin. If using an analog clock the DC bias should be set at the mid-point of the VDDIO supply or the VDD18 regulator output. Use a bias circuit as shown in Figure 5-6. The amplitude must be greater than 300mV peak to peak. The component values provided in Figure 5-6 are for example only. The actual values should be selected to satisfy system requirements. The REFCLK amplitude must comply with the signal amplitudes shown in Table 4-5 and the duty cycle in Table 4-3. FIGURE 5-6: EXAMPLE OF CIRCUIT USED TO SHIFT A REFERENCE CLOCK COMMONMODE VOLTAGE LEVEL. 47k VDDIO Supply or VDD18 To REFCLK pin 0.1uF DS00001880A-page 28 47k Clock  2009 - 2015 Microchip Technology Inc. USB333x 5.4.3 REFCLK JITTER The USB333x is tolerant to jitter on the reference clock. The REFCLK jitter should be limited to a peak to peak jitter of less than 1nS over a 10uS time interval. If this level of jitter is exceeded when configured for either ULPI Clock Input Mode or ULPI Clock Output Mode, the USB333x High Speed eye diagram may be degraded. The frequency accuracy of the REFCLK must meet the +/- 500ppm requirement as shown in Table 4-3. 5.4.4 REFCLK ENABLE/DISABLE The REFCLK should be enabled when the RESETB pin is brought high. The ULPI interface will start running after the time specified in Table 4-3. If the reference clock enable is delayed relative to the RESETB pin, the ULPI interface will start operation delayed by the same amount. The reference clock can be run at anytime the RESETB pin is low without causing the USB333x to start-up or draw current. When the USB333x is placed in Low Power Mode or Carkit Mode, the reference clock can be stopped after the final ULPI register write is complete. The STP pin is asserted to bring the USB333x out of Low Power Mode. The reference clock should be started at the same time STP is asserted to minimize the USB333x start-up time. If the reference clock is stopped while in ULPI Synchronous mode the PLL will come out of lock and the frequency of oscillation will decrease to the minimum allowed by the PLL design. If the reference clock is stopped during a USB session, the session may drop. 5.5 Internal Regulators and POR The USB333x includes integrated power management functions, including a Low-Dropout regulator that can be used to generate the 3.3V USB supply, an integrated 1.8V regulator, and a POR generator described in Section 5.5.2. 5.5.1 INTEGRATED LOW DROPOUT REGULATORS The USB333x includes two integrated linear regulators. Power sourced at the VBAT pin is regulated to 3.3V and 1.8V output on the VDD33 and VDD18 pins. To ensure stability, both regulators require an external bypass capacitor as specified in Table 4-12 placed as close to the pins as possible. VBAT and VDD33 should never be shorted together. The USB333x regulators are designed to generate the 3.3 Volt and 1.8 Volt supplies for the USB333x only. Using the regulators to provide current for other circuits is not recommended and Microchip does not guarantee USB performance or regulator stability. During USB UART mode the 3.3V regulator output voltage can be changed to allow the USB333x to work with UARTs operating at different operating voltages. The 3.3V regulator output is configured to the voltages shown in Table 4-12 with the UART RegOutput[1:0] bits in the USB IO & Power Management register. The regulators are enabled by the RESETB pin. When RESETB pin is low both regulators are disabled and the regulator outputs are pulled low by weak pull-down. The RESETB pin must be brought high to enable the regulators. For peripheral-only or host-only bus-powered applications, the VBAT supply shown below in Figure 5-7 may be connected to the VBUS pin of the USB connector for bus powered applications. In this configuration, external overvoltage protection is required to protect the VBAT supply from any transient voltage present at the VBUS pin of the USB connector. Additionally, the VBAT input must never be exposed to a voltage that exceeds VVBAT. (See Table 3-2.) Also in this configuration, the VBUS line must never be connected to a system utilizing a +30V VBUS level (i.e. Some USB battery chargers). Microchip does not recommend connecting the VBAT pin directly to the VBUS terminal of the USB connector.  2009 - 2015 Microchip Technology Inc. DS00001880A-page 29 USB333x FIGURE 5-7: POWERING THE USB333X FROM VBUS ~~ RVBUS VBUS VBUS To USB Con. To OTG VBAT OVP VDD33 COUT LDO GND ~~ 5.5.2 PHY POWER ON RESET (POR) The USB333x provides a POR circuit that generates an internal reset pulse after the VDD18 supply is stable. After the internal POR goes high the USB333x will release from reset and begin normal ULPI operation as described in Section 53. The ULPI registers will power up in their default state summarized in Table 7-1 when the 1.8V supply comes up. Cycling the RESETB pin can also be used to reset the ULPI registers to their default state (and reset all internal state machines) by bringing the pin low for a minimum of 1 microsecond and then high. It is not necessary to wait for the VDD33 and VDD18 pins to discharge to 0 volts to reset the part. The RESETB pin must be pulled high to enable the 3.3V and 1.8V regulators. A pull-down resistor is not present on the RESETB pin and therefore the system should drive the RESETB pin to the desired state at all times. If the system does not need to place the USB333x into reset mode the RESETB pin should be connected to VDD18 (USB3330, USB3331, USB3336, and USB3338) or VDDIO (USB3333). 5.5.3 RECOMMENDED POWER SUPPLY SEQUENCE For USB operation, the USB333x requires a valid voltage on the VBAT and VDDIO pins. The VDD33 and VDD18 regulators are automatically enabled when the RESETB pin is brought high. For the USB3333, Table 5-4 presents the power supply configurations in more detail. The RESETB pin can be held low until the VBAT supply is stable. If the Link is not ready to interface the USB333x, the Link may choose to hold the RESETB pin low until it is ready to control the ULPI interface. TABLE 5-4: OPERATING MODE VS. POWER SUPPLY CONFIGURATION VBAT VDDIO RESETB 0 0 0 Powered Off 1 X 0 RESET Mode. (Note 5-3) 1 1 1 Note 5-3 5.5.4 Operating Modes Available Full USB operation as described in Section 6.0, "ULPI Operation". VDDIO must be present for ULPI pins to tri-state. START-UP The power on default state of the USB333x is ULPI Synchronous mode. The USB333x requires the following conditions to begin operation: the power supplies must be stable, the REFCLK must be present and the RESETB pin must be high. After these conditions are met, the USB333x will begin ULPI operation that is described in Section 6.0. DS00001880A-page 30  2009 - 2015 Microchip Technology Inc. USB333x Figure 5-8 below shows a timing diagram to illustrate the start-up of the USB333x. At T0, the supplies are stable and the USB333x is held in reset mode. At T1, the Link drives RESETB high after the REFCLK has started. The RESETB pin may be brought high asynchronously to REFCLK. Once, the 3.3V and 1.8V internal supplies become stable the USB333x will apply the 15Kohm pull downs to the data bus and assert DIR until the internal PLL has locked. After the PLL has locked, the USB333x will check that the Link has de-asserted STP and at T2 it will de-assert DIR and begin ULPI operation. The ULPI bus will be available as shown in Figure 5-8 in the time defined as TSTART given in Table 4-3. If the REFCLK signal starts after the RESETB pin is brought high, then time T0 will begin when REFCLK starts. TSTART also assumes that the Link has de-asserted STP. If the Link has held STP high the USB333x will hold DIR high until STP is deasserted. When the LINK de-asserts STP, it must be ready drive the ULPI data bus to idle (00h) for a minimum of one clock cycle after DIR de-asserts. FIGURE 5-8: ULPI START-UP TIMING T0 SUPPLIES STABLE T1 REFCLK T2 REFCLK valid RESETB DATA[7:0] PHY Tri-States PHY Drives Idle DIR PHY Tri-States PHY Drives High STP IDLE RXCMD IDLE LINK Drives Low TSTART 5.6 USB On-The-Go (OTG) The USB333x provides support for the USB OTG protocol. OTG allows the USB333x to be dynamically configured as a host or peripheral depending on the type of cable inserted into the Micro-AB receptacle. When the Micro-A plug of a cable is inserted into the Micro-AB receptacle, the USB device becomes the A-device. When a Micro-B plug is inserted, the device becomes the B-device. The OTG A-device behaves similar to a Host while the B-device behaves similar to a peripheral. The differences are covered in the “On-The-Go Supplement to the USB 2.0 Specification”. In applications where only USB Host or USB Peripheral is required, the OTG Module is unused. 5.6.1 ID RESISTOR DETECTION The ID pin of the USB connector is monitored by the ID pin of the USB333x to detect the attachment of different types of USB devices and cables. For device only applications that do not use the ID signal the ID pin should be connected to VDD33. The block diagram of the ID detection circuitry is shown in Figure 5-9 and the related parameters are given in Table 4-9.  2009 - 2015 Microchip Technology Inc. DS00001880A-page 31 USB333x FIGURE 5-9: USB333X ID RESISTOR DETECTION CIRCUITRY ~~ VDD33 ID RID=100K RIDW>1M IdPullup To USB Con. IdGnd Vref IdGnd en IdGndDrv IdFloat Vref IdFloat en Rid ADC IdFloatRise or IdFloatFall RidValue OTG Module ~~ 5.6.1.1 IdGnd Rise or IdGnd Fall USB OTG Operation The USB333x can detect ID grounded and ID floating to determine if an A or B cable has been inserted. The A plug will ground the ID pin while the B plug will float the ID pin. These are the only two valid states allowed in the OTG Protocol. To monitor the status of the ID pin, the Link activates the IdPullup bit in the OTG Control register, waits 50mS and then reads the status of the IdGnd bit in the USB Interrupt Status register. If an A cable has been inserted the IdGnd bit will read 0. If a B cable is inserted, the ID pin is floating and the IdGnd bit will read 1. The USB333x provides an integrated weak pull-up resistor on the ID pin, RIDW. This resistor is present to keep the ID pin in a known state when the IdPullup bit is disabled and the ID pin is floated. In addition to keeping the ID pin in a known state, it enables the USB333x to generate an interrupt to inform the link when a cable with a resistor to ground has been attached to the ID pin. The weak pull-up is small enough that the largest valid RID resistor pulls the ID pin low and causes the IdGnd comparator to go low. After the link has detected an ID pin state change, the RID converter can be used to determine the resistor value as described in Section 5.6.1.2. 5.6.1.2 Measuring ID Resistance to Ground The Link can use the integrated resistance measurement capabilities of the USB333x to determine the value of an ID resistance to ground. Table 5-5 details the values of resistance to ground that the USB333x can detect. TABLE 5-5: VALID VALUES OF ID RESISTANCE TO GROUND ID Resistance to Ground RID Value Note: Ground 000 75Ω +/-1% 001 102kΩ +/-1% 010 200kΩ+/-1% 011 Floating 101 IdPullUp = 0 DS00001880A-page 32  2009 - 2015 Microchip Technology Inc. USB333x The ID resistance to ground can be read while the USB333x is in Synchronous Mode. When a resistor to ground is attached to the ID pin, the state of the IdGnd comparator will change. After the Link has detected ID transition to ground, it can use the methods described in Section 6.8 to operate the Rid converter. 5.6.1.3 Note: Using IdFloat Comparator (not recommended) The ULPI specification details a method to detect a 102kΩ resistance to ground using the IdFloat comparator. This method can only detect 0ohms, 102kΩ, and floating terminations of the ID pin. Due to this limitation it is recommended to use the RID Converter as described in Section 5.6.1.2. The ID pin can be either grounded, floated, or connected to ground with a 102kΩ external resistor. To detect the 102K resistor, set the idPullup bit in the OTG Control register, causing the USB333x to apply the 100K internal pull-up connected between the ID pin and VDD33. Set the idFloatRise and idFloatFall bits in the Carkit Interrupt Enable register to enable the IdFloat comparator to generate an RXCMD to the Link when the state of the IdFloat changes. As described in Figure 6-3, the alt_int bit of the RXCMD will be set. The values of IdGnd and IdFloat are shown for the three types cables that can attach to the USB Connector in Table 5-6. TABLE 5-6: IDGND AND IDFLOAT VS. ID RESISTANCE TO GROUND ID Resistance Note: IDGND IDFLOAT Float 1 1 102K 1 0 GND 0 0 The ULPI register bits IdPullUp, IdFloatRise, and IdFloatFall should be enabled. To save current when an A Plug is inserted, the internal 102kΩ pull-up resistor can be disabled by clearing the IdPullUp bit in the OTG Control register and the IdFloatRise and IdFloatFall bits in both the USB Interrupt Enable Rising and USB Interrupt Enable Falling registers. If the cable is removed the weak RIDW will pull the ID pin high. The IdGnd value can be read using the ULPI USB Interrupt Status register, bit 4. In host mode, it can be set to generate an interrupt when IdGnd changes by setting the appropriate bits in the USB Interrupt Enable Rising and USB Interrupt Enable Falling registers. The IdFloat value can be read by reading the ULPI Carkit Interrupt Status register bit 0. Note: 5.6.2 The IdGnd switch has been provided to ground the ID pin for future applications. VBUS MONITORING AND VBUS PULSING The USB333x includes all of the VBUS comparators required for OTG. The VbusValid, SessVld, and SessEnd comparators shown in Figure 5-10 are fully integrated into the USB333x. These comparators are used to monitor changes in the VBUS voltage, and the state of each comparator can be read from the USB Interrupt Status register. The VbusValid comparator is used by the Link, when configured as an A device, to ensure that the VBUS voltage on the cable is valid. The SessVld comparator is used by the Link when configured as both an A or B device to indicate a session is requested or valid. Finally the SessEnd comparator is used by the B-device to indicate a USB session has ended. Also included in the VBUS Monitor and Pulsing block are the resistors used for VBUS pulsing in SRP. The resistors used for VBUS pulsing include a pull-down to ground and a pull-up to VDD33. In some applications, voltages much greater than 5.5V may be present at the VBUS pin of the USB connector. The USB333x includes an over voltage protection circuit that protects the VBUS pin of the USB333x from excessive voltages as shown in Figure 5-10.  2009 - 2015 Microchip Technology Inc. DS00001880A-page 33 USB333x FIGURE 5-10: USB333X OTG VBUS BLOCK ~~ VDD33 ChrgVbus 0.5V SessEnd en RVPU SessEnd Rise or SessEnd Fall RVPD RVBUS 1.4V RVB To USB Con. SessValid VBUS Overvoltage Protection VBUS VbusValid 4.575V en DischrgVbus VbusValid Rise or VbusValid Fall [0, X] [1, 0] EXTVBUS (logic 1) IndicatorComplement RXCMD VbusValid [1, 1] [UseExternalVbusindicator, IndicatorPassThru] ~~ 5.6.2.1 PHY SessEnd Comparator The SessEnd comparator is used during the Session Request Protocol (SRP). The comparator is used by the B-device to detect when a USB session has ended and it is safe to start Vbus Pulsing to request a USB session from the A-device. When VBUS goes below the threshold in Table 4-8, the USB session is considered to be ended, and SessEnd will transition from 0 to 1. The SessEnd comparator can be disabled by clearing this bit in both the USB Interrupt Enable Rising and USB Interrupt Enable Falling registers. When disabled, the SessEnd bit in the USB Interrupt Status register will read 0. The SessEnd Comparator is only used when configured as an OTG device. If the USB333x is used as a Host or Device only the SessEnd Comparator should be disabled, using the method described above. 5.6.2.2 SessVld Comparator The SessVld comparator is used when the PHY is configured as both an A and B device. When configured as an A device, the SessVld is used to detect Session Request protocol (SRP). When configured as a B device, SessVld is used to detect the presence of VBUS. The SessVld comparator output can also be read from the USB Interrupt Status register. The SessVld comparator will also generate an RX CMD, as detailed in Section 6.3.1, anytime the comparator changes state. The SessVld interrupts can be disabled by clearing this bit in both the USB Interrupt Enable Rising and USB Interrupt Enable Falling registers. When the interrupts are disabled, the SessVld comparator is still operational and will generate RX CMD’s. The SessVld comparator trip point is detailed in Table 4-9. Note: The OTG Supplement specifies a voltage range for A-Device Session Valid and B-Device Session Valid comparator. The USB333x PHY combines the two comparators into one and uses the narrower threshold range. DS00001880A-page 34  2009 - 2015 Microchip Technology Inc. USB333x 5.6.2.3 VbusValid Comparator The VbusValid comparator is only used when the USB333x is configured as a host that can supply less than 100mA VBUS current. In the USB protocol, the A-device supplies the VBUS voltage and is responsible to ensure it remains within a specified voltage range. The VbusValid comparator can be disabled by clearing this bit in both the USB Interrupt Enable Rising and USB Interrupt Enable Falling registers. When disabled, bit 1 of the USB Interrupt Status register will return a 0. The VbusValid comparator threshold values are detailed in Table 4-9. If the USB333x is used as a Device only the VbusValid Comparator should be disabled, using the method described above. The USB333x includes the external VbusValid indicator logic as detailed in the ULPI Specification. The external VbusValid indicator is tied to a logic one. The decoding of this logic is shown in Table 5-7 below. By default this logic is disabled. TABLE 5-7: EXTERNAL VBUS INDICATOR LOGIC Typical Application Use External VBus Indicator Indicator Pass Thru Indicator Complement OTG Device 0 X X Internal VbusValid comparator (Default) 1 1 0 Fixed 1 1 1 1 Fixed 0 1 0 0 Internal VbusValid comparator. 1 0 1 Fixed 0 1 1 0 Fixed 1 1 1 1 Fixed 0 0 X X Internal VbusValid comparator. This information should not be used by the Link. (Note 5-4) Standard Host Standard Peripheral Note 5-4 5.6.2.4 RXCMD VBUSVALID Encoding Source A peripheral should not use VbusValid to detect a USB connection and begin operation. The peripheral should use SessValid to detect the presence of VBUS on the USB connector. VbusValid should only be used for USB Host and OTG A-device applications. VBUS Pulsing with Pull-up and Pull-down Resistors In addition to the internal VBUS comparators, the USB333x also includes the integrated VBUS pull-up and pull-down resistors used for VBUS Pulsing during OTG Session Request Protocol. To discharge the VBUS voltage so that a Session Request can begin, the USB333x provides a pull-down resistor from VBUS to GND. This resistor is controlled by the DischargeVbus bit 3 of the OTG Control register. The pull-up resistor is connected between VBUS and VDD33. This resistor is used to pull VBUS above 2.1 volts so that the A-Device knows that a USB session has been requested. The state of the pull-up resistor is controlled by the bit 4 ChargeVbus of the OTG Control register. The Pull-Up and Pull-Down resistor values are detailed in Table 4-9. The internal VBUS Pull-up and Pull-down resistors are designed to include the RVBUS external resistor in series. This external resistor is used by the VBUS Over voltage protection described below. 5.6.2.5 VBUS Input Impedance The OTG Supplement requires an A-Device that supports Session Request Protocol to have a VBUS input impedance less than 100kΩ and greater the 40kΩ to ground. The USB333x provides a 75kΩ resistance to ground, RVB. The RVB resistor tolerance is detailed in Table 4-9. 5.6.2.6 VBUS Over Voltage Protection (OVP) The USB333x provides an integrated over voltage protection circuit to protect the VBUS pin from excessive voltages that may be present at the USB connector. The over voltage protection circuit works with an external resistor (RVBUS) by drawing current across the resistor to reduce the voltage at the VBUS pin. When voltage at the VBUS pin exceeds 5.5V, the Over voltage Protection block will sink current to ground until VBUS is below 5.5V. The current drops the excess voltage across RVBUS and protects the USB333x VBUS pin. The required RVBUS value is dependent on the operating mode of the USB333x as shown in Table 5-8.  2009 - 2015 Microchip Technology Inc. DS00001880A-page 35 USB333x TABLE 5-8: REQUIRED RVBUS RESISTOR VALUE Operating Mode RVBUS Device only 20kΩ ±5% OTG Host Capable of less than 100mA of current on VBUS 1kΩ ±5% Host or OTG Host capable of >100mA UseExternalVbusIndicator = 1 1kΩ ±5% The Over voltage Protection circuit is designed to protect the USB333x from continuous voltages up to 30V on the RVBUS resistor. The RVBUS resistor must be sized to handle the power dissipated across the resistor. The resistor power can be found using the equation below: 2 ( Vprotect – 5.0 ) P RVBUS = -------------------------------------------R VBUS Where: • Vprotect is the VBUS protection required. • RVBUS is the resistor value, 1kΩ or 20kΩ. • PRVBUS is the required power rating of RVBUS. For example, protecting a peripheral or device only application to 15V would require a 20kΩ RVBUS resistor with a power rating of 0.01W. To protect an OTG product to 15V would require a 1kΩ RVBUS resistor with a power rating of 0.1W. 5.6.3 DRIVING EXTERNAL VBUS The USB333x monitors VBUS as described in VBUS Monitoring and VBUS Pulsing. The USB333x does not provide an external output for the DrvVbusExternal ULPI register. For OTG and Host applications, the external VBUS supply or power switch must be controlled by the Link as shown in Figure 8-2. 5.7 USB UART Support The USB333x provides support for the USB UART interface as detailed in the ULPI specification and the former CEA936A specification. The USB333x can be placed in UART Mode using the method described in Section 6.7, and the regulator output will automatically switch to the value configured by the UART RegOutput bits in the USB IO & Power Management register. While in UART mode, the Linestate signals cannot be monitored on the DATA[0] and DATA[1] pins. 5.8 USB Charger Detection Support The following blocks allow the USB333x to detect when a Battery Charger, Charging Host Port, or a USB Host is attached to the USB connector. The USB333x can also be configured to appear as a Charging Host Port. The charger detection circuitry should be disabled during USB operation. DS00001880A-page 36  2009 - 2015 Microchip Technology Inc. USB333x FIGURE 5-11: USB CHARGER DETECTION BLOCK DIAGRAM ~~ VDD33 C h a rg e rP u llu p E n D P RCD RCD C h a rg e rP u llu p E n D M C o n ta ctD e te ctE n en I D P _S R C DP V D A T_S R C T o U S B C on . V D a tS rcE n H o stC h rg E n DM V d a tD e t V D A T_R E F RPD RPD T o U S B C on . en ID a tS in kE n en I D A T_S IN K D p P u lld o w n D m P u lld o w n ~~ Note: SMSC PHY The italic names in the Figure 5-11 correspond to bits in the ULPI register set. The charger detection circuitry runs from the VDD33 supply and requires that the VDD33 supply to be present to run the charger detection circuitry. The VDD33 supply is present anytime the RESETB pin is pulled high and VBAT is present. The charger detection circuits are fully functional while in Low Power Mode (Suspendm = 0). The status of the VdatDet can be relayed back to the Link through the ULPI interrupts in both Synchronous mode and Low Power Mode. 5.8.1 ACTIVE ANALOG CHARGER DETECTION The USB333x includes the active analog charger detection specified in the USB-IF Battery Charging Specification. The additional analog circuitry will allow the USB333x to: 1. 2. 3. Detect a USB Charger that has shorted DP and DM together Detect a USB Host/Charger Behave as a USB Host/Charger The charger detection circuitry is shown in Figure 5-11. The VdatDet output is qualified with the Linestate[1:0] value. If the Linestate is not equal to 00 the VdatDet signal will not assert.  2009 - 2015 Microchip Technology Inc. DS00001880A-page 37 USB333x IDatSinkEn ContactDetEn HostChrgEn DpPulldown DmPulldown USB CHARGER SETTING VS. MODES VDatSrcEn TABLE 5-9: Device Connect Detect (The Connect Detect setting in Table 5-1 must be followed) 0 0 1 0 0 1 Device Charger Detection 1 1 0 0 0 0 Device USB Operation 0 0 0 0 0 0 Charging Host Port, no charging device attached and SE0 (VdatDet = 0) 0 1 0 1 1 1 Charger Detection Modes Charging Host Port, charging device attached (VdatDet = 1) 1 1 0 1 1 1 Charging Host Port USB Operation 0 0 0 1 1 1 5.8.2 Note: RESISTIVE CHARGER DETECTION The Resistive Charger Detection has been superseded by the Active Analog Charger Detection detailed above. It is recommended that new designs use the Active Analog Charger Detection. To support the detection and identification of different types of USB chargers the USB333x provides integrated pull-up resistors, RCD, on both DP and DM. These pull-up resistors along with the single ended receivers can be used to determine the type of USB charger attached. Reference information on implementing charger detection is provided in Section 8.2, "USB Charger Detection". TABLE 5-10: Note: 5.9 Note: USB WEAK PULL-UP ENABLE RESETB DP Pullup Enable DM Pullup Enable 0 0 0 1 ChargerPullupEnableDP ChargerPullupEnableDM ChargerPullupEnableDP and ChargerPullupEnableDM are enabled in the USB IO & Power Management register. USB Audio Support (USB3331, USB3336, and USB3338) The USB333x supports “USB Digital Audio” through the USB protocol in ULPI and USB Serial modes described in Section 6.0, "ULPI Operation". The USB333x provides two low resistance analog switches that allow analog audio to be multiplexed over the DP and DM terminals of the USB connector. The audio switches are shown in Figure 5-1. The electrical characteristics of the USB Audio Switches are provided in Table 4-11. During normal USB operation the switches are off. When USB Audio is desired the switches can be turned “on” by enabling the SpkLeftEn, SpkRightEn, or MicEn bits in the Carkit Control register as described in Section 6.7.2. These bits are disabled by default. The RESETB pin must be high when using the analog switches so that the VDD33 supply is present. If the VDD33 supply is applied externally and RESETB is held low the switches will be off. DS00001880A-page 38  2009 - 2015 Microchip Technology Inc. USB333x In addition to USB Audio support the switches could also be used to multiplex a second Full Speed USB PHY to the USB connector. The signal quality will be degraded slightly due to the “on” resistance of the switches. The USB333x single-ended receivers described in Section 5.2.1 are enabled while in synchronous mode and are disabled when Carkit Mode is entered. The USB333x does not provide the DC bias for the audio signals. The SPK_R and SPK_L pins should be biased to 1.65V when audio signals are routed through the USB333x. This DC bias is necessary to prevent the audio signal from swinging below ground and being clipped by ESD Diodes. When the system is not using the USB Audio switches, the SPK_R and SPK_L switches should be disabled.  2009 - 2015 Microchip Technology Inc. DS00001880A-page 39 USB333x 6.0 ULPI OPERATION 6.1 ULPI Introduction The USB333x uses the industry standard ULPI digital interface for communication between the transceiver and Link (device controller). The ULPI interface is designed to reduce the number of pins required to connect a discrete USB transceiver to an ASIC or digital controller. For example, a full UTMI+ Level 3 OTG interface requires 54 signals while a ULPI interface requires only 12 signals. The ULPI interface is documented completely in the “UTMI+ Low Pin Interface (ULPI) Specification Revision 1.1”. The following sections describe the operating modes of the USB333x digital interface. Figure 6-1 illustrates the block diagram of the ULPI digital functions. It should be noted that this USB333x does not use a “ULPI wrapper” around a UTMI+ PHY core as the ULPI specification implies. FIGURE 6-1: ULPI DIGITAL BLOCK DIAGRAM USB Transmit and Receive Logic High Speed TX Full Speed TX Low Speed TX NOTE: The ULPI interface is a wrapperless design. ULPI Protocol Block High Speed Data Recovery Full / Low Speed Data Recovery HS RX Data To OTG Analog To USB Audio Analog ChargerPullupEnDP ChargerPullupEnDM ChrgVbus IdGndDrv IdPullUp SpkLeftEn Interface Protect Disable UseExternal Vbus Indicator Indicator Complement Indicator Pass Thru DischrgVbus RidValue[2:0] RidCon...Start VbusValid SessionValid SessionEnd IdGnd IdFloat Linestates[1:0] Rid State Machine HostDisconnect SuspendM 6pinSerial Mode 3pinSerial Mode RegOutput[1:0] TxdEn RxdEn Reset DpPulldown DmPulldown SwapDP/DM XcvrSelect[1:0] TermSelect OpMode[1:0] ULPI Interupt To RX Analog FS/LS Data RidCon...Done Rx Data ULPI Register Access STP To TX Analog FS/LS Tx Data Transceiver Control NXT ClockSuspendM AutoResume CarkitMode DIR HS Tx Data SpkRightEn/MicEn Tx Data Data[7:0] Interrupt Control RESETB POR ULPI Register Array The advantage of a “wrapper-less” architecture is that the USB333x has a lower USB latency than a design which must first register signals into the PHY’s wrapper before the transfer to the transceiver core. A low latency PHY allows a wrapper around a UTMI Link to be used and still make the required USB turn-around timing required by the USB 2.0 specification. DS00001880A-page 40  2009 - 2015 Microchip Technology Inc. USB333x RxEndDelay maximum allowed by the UTMI+/ULPI for 8-bit data is 63 High Speed clocks. USB333x uses a low latency High Speed receiver path to lower the RxEndDelay to 43 High Speed clocks. This low latency design gives the Link more cycles to make decisions and reduces the Link complexity. This is the result of the “wrapper less” architecture of the USB333x. This low RxEndDelay should allow legacy UTMI Links to use a “wrapper” to convert the UTMI+ interface to a ULPI interface. In Figure 6-1, a single ULPI Protocol Block decodes the ULPI 8-bit bi-directional bus when the Link addresses the PHY. The Link must use the DIR output to determine direction of the ULPI data bus. The USB333x is the “bus arbitrator”. The ULPI Protocol Block will route data/commands to the transmitter or the ULPI register array. 6.1.1 ULPI INTERFACE SIGNALS The UTMI+ Low Pin Interface (ULPI) uses a 12-pin interface to connect a USB Transceiver to an external Link. The reduction of external pins, relative to UTMI+, is accomplished implementing the relatively static configuration pins (i.e. xcvrselect[1:0], termselect, opmode[1:0], and DpPullDown DmPulldown) as an internal register array. An 8-bit bi-directional data bus clocked at 60MHz allows the Link to access this internal register array and transfer USB packets to and from the PHY. The remaining 3 pins function to control the data flow and arbitrate the data bus. Direction of the 8-bit data bus is controlled by the DIR output from the PHY. Another output, NXT, is used to control data flow into and out of the device. Finally, STP, which is in input to the PHY, terminates transfers and is used to start up and resume from Low Power Mode. The ULPI Interface signals are described below in Table 6-1. TABLE 6-1: Signal ULPI INTERFACE SIGNALS Direction Description CLK I/O 60MHz ULPI clock. All ULPI signals are driven synchronous to the rising edge of this clock. This clock can be either driven by the PHY or the Link as described in Section 5.4.1 DATA[7:0] I/O 8-bit bi-directional data bus. Bus ownership is determined by DIR. The Link and PHY initiate data transfers by driving a non-zero pattern onto the data bus. ULPI defines interface timing for a single-edge data transfers with respect to rising edge of the ULPI clock. DIR OUT Controls the direction of the data bus. When the PHY has data to transfer to the Link, it drives DIR high to take ownership of the bus. When the PHY has no data to transfer it drives DIR low and monitors the bus for commands from the Link. The PHY will pull DIR high whenever the interface cannot accept data from the Link, such as during PLL start-up. STP IN The Link asserts STP for one clock cycle to stop the data stream currently on the bus. If the Link is sending data to the PHY, STP indicates the last byte of data was on the bus in the previous cycle. NXT OUT The PHY asserts NXT to throttle the data. When the Link is sending data to the PHY, NXT indicates when the current byte has been accepted by the PHY. The Link places the next byte on the data bus in the following clock cycle. USB333x implements a Single Data Rate (SDR) ULPI interface with all data transfers happening on the rising edge of the 60MHz ULPI Clock while operating in Synchronous Mode. The direction of the data bus is determined by the state of DIR. When DIR is high, the PHY is driving DATA[7:0]. When DIR is low, the Link is driving DATA[7:0]. Each time DIR changes, a “turn-around” cycle occurs where neither the Link nor PHY drive the data bus for one clock cycle. During the “turn-around“cycle, the state of DATA[7:0] is unknown and the PHY will not read the data bus. Because USB uses a bit-stuffing encoding, some means of allowing the PHY to throttle the USB transmit data is needed. The ULPI signal NXT is used to request the next byte to be placed on the data bus by the Link. The ULPI interface supports the two basic modes of operation: Synchronous Mode and Asynchronous Mode. Asynchronous Mode includes Low Power Mode, the Serial Modes, and Carkit Mode. In Synchronous Mode, all signals change synchronously with the 60MHz ULPI clock. In asynchronous modes the clock is off and the ULPI bus is redefined to bring out the signals required for that particular mode of operations. The description of synchronous Mode is described in the following sections while the descriptions of the asynchronous modes are described in Section 6.5, Section 6.6, and Section 6.7.  2009 - 2015 Microchip Technology Inc. DS00001880A-page 41 USB333x 6.1.2 ULPI INTERFACE TIMING IN SYNCHRONOUS MODE The control and data timing relationships are given in Figure 6-2 and Table 4-4. All timing is relative to the rising clock edge of the 60MHz ULPI Clock. FIGURE 6-2: ULPI SINGLE DATA RATE TIMING DIAGRAM IN SYNCHRONOUS MODE 60MHz ULPI CLK TSC THC Control In STP TSD THD Data In DATA[7:0] TDC TDC Control Out DIR, NXT TDD Data Out DATA[7:0] 6.2 ULPI Register Access The following section details the steps required to access registers through the ULPI interface. At any time DIR is low the Link may access the ULPI registers set using the Transmit Command byte. The ULPI registers retain their contents when the PHY is in Low Power Mode, Full Speed/Low Speed Serial Mode, or Carkit Mode. 6.2.1 TRANSMIT COMMAND BYTE (TX CMD) A command from the Link begins a ULPI transfer from the Link to the USB333x. Before reading a ULPI register, the Link must wait until DIR is low, and then send a Transmit Command Byte (TX CMD) byte. The TX CMD byte informs the USB333x of the type of data being sent. The TX CMD is followed by a data transfer to or from the USB333x. Table 6-2 gives the TX command byte (TX CMD) encoding for the USB333x. The upper two bits of the TX CMD instruct the PHY as to what type of packet the Link is transmitting. TABLE 6-2: ULPI TX CMD BYTE ENCODING Command Name CMD Bits[7:6] CMD Bits[5:0] Idle 00b 000000b ULPI Idle Transmit 01b Register Write 10b 000000b USB Transmit Packet with No Packet Identifier (NOPID) 00XXXXb USB Transmit Packet Identifier (PID) where DATA[3:0] is equal to the 4-bit PID. P3P2P1P0 where P3 is the MSB. XXXXXXb Immediate Register Write Command where: DATA[5:0] = 6-bit register address 101111b Register Read 11b XXXXXXb 101111b DS00001880A-page 42 Command Description Extended Register Write Command where the 8-bit register address is available on the next cycle. Immediate Register Read Command where: DATA[5:0] = 6-bit register address Extended Register Read Command where the 8-bit register address is available on the next cycle.  2009 - 2015 Microchip Technology Inc. USB333x 6.2.2 ULPI REGISTER WRITE A ULPI register write operation is given in Figure 6-3. The TX command with a register write DATA[7:6] = 10b is driven by the Link at T0. The register address is encoded into DATA[5:0] of the TX CMD byte. FIGURE 6-3: ULPI REGISTER WRITE IN SYNCHRONOUS MODE T0 T1 T2 T3 T4 T5 T6 CLK DATA[7:0] Idle TXD CMD (reg write) Reg Data[n] Idle DIR STP NXT ULPI Register Reg Data [n-1] Reg Data [n] To write a register, the Link will wait until DIR is low, and at T0, drive the TX CMD on the data bus. At T2 the PHY will drive NXT high. On the next rising clock edge, T3, the Link will write the register data. At T4, the PHY will accept the register data and drive NXT low. The Link will drive an Idle on the bus and drive STP high to signal the end of the data packet. Finally, at T5, the PHY will latch the data into the register and the Link will pull STP low. NXT is used to throttle when the Link drives the register data on the bus. DIR is low throughout this transaction since the PHY is receiving data from the Link. STP is used to end the transaction and data is registered after the de-assertion of STP. After the write operation completes, the Link must drive a ULPI Idle (00h) on the data bus. If the databus is not driven to idle the USB333x may decode the non-zero bus value as an RX Command. A ULPI extended register write operation is shown in Figure 6-4. To write an extended register, the Link will wait until DIR is low, and at T0, drive the TX CMD on the data bus. At T2 the PHY will drive NXT high. On the next clock T3 the Link will drive the extended address. On the next rising clock edge, T4, the Link will write the register data. At T5, the PHY will accept the register data and drive NXT low. The Link will drive an Idle on the bus and drive STP high to signal the end of the data packet. At T5, the PHY will latch the data into the register. Finally, at T6, the Link will drive STP low.  2009 - 2015 Microchip Technology Inc. DS00001880A-page 43 USB333x FIGURE 6-4: ULPI EXTENDED REGISTER WRITE IN SYNCHRONOUS MODE T0 T1 T2 T3 T4 T5 T6 T7 CLK DATA[7:0] TXD CMD (extended reg write) Idle Extended address Reg Data[n] Idle DIR STP NXT ULPI Register 6.2.3 Reg Data [n-1] Reg Data [n] ULPI REGISTER READ A ULPI register read operation is given in Figure 6-5. The Link drives a TX CMD byte with DATA[7:6] = 11h for a register read. DATA[5:0] of the ULPI TX command bye contain the register address. FIGURE 6-5: ULPI REGISTER READ IN SYNCHRONOUS MODE T0 T1 T2 T3 T4 T5 T6 CLK DATA[7:0] Idle TXD CMD reg read Turn around Reg Data Turn around Idle DIR STP NXT At T0, the Link will place the TX CMD on the data bus. At T2, the PHY will bring NXT high, signaling the Link it is ready to accept the data transfer. At T3, the PHY reads the TX CMD, determines it is a register read, and asserts DIR to gain control of the bus. The PHY will also de-assert NXT. At T4, the bus ownership has transferred back to the PHY and the DS00001880A-page 44  2009 - 2015 Microchip Technology Inc. USB333x PHY drives the requested register onto the data bus. At T5, the Link will read the data bus and the PHY will drop DIR low returning control of the bus back to the Link. After the turn around cycle, the Link must drive a ULPI Idle command at T6. A ULPI extended register read operation is shown in Figure 6-6.To read an extended register, the Link writes the TX CMD with the address set to 2Fh. At T2, the PHY will assert NXT, signaling the Link it is ready to accept the extended address. At T3, the Link places the extended register address on the bus. At T4, the PHY reads the extended address, and asserts DIR to gain control of the bus. The PHY will also de-assert NXT. At T5, the bus ownership has transferred back to the PHY and the PHY drives the requested register onto the data bus. At T6, the Link will read the data bus and the PHY will de-assert DIR returning control of the bus back to the Link. After the turn around cycle, the Link must drive a ULPI Idle command at T6. FIGURE 6-6: ULPI EXTENDED REGISTER READ IN SYNCHRONOUS MODE T0 T1 T2 T3 T4 T5 T6 T7 CLK DATA[7:0] Idle TXD CMD extended reg read Extended address Turn around Reg Data Turn around Idle DIR STP NXT 6.3 USB333x Receiver The following section describes how the USB333x uses the ULPI interface to receive USB signaling and transfer status information to the Link. This information is communicated to the Link using RX Commands to relay bus status and received USB packets. 6.3.1 ULPI RECEIVE COMMAND (RX CMD) The ULPI Link needs information which was provided by the following pins in a UTMI implementation: linestate[1:0], rxactive, rxvalid, rxerror, and VbusValid. When implementing the OTG functions, the VBUS and ID pin states must also be transferred to the Link. ULPI defines a Receive Command Byte (RXCMD) that contains this information. An RXCMD can be sent a any time the bus is idle. The RXCMD is initiated when the USB333x asserts DIR to take control of the bus. The timing of RXCMD is shown in the figure below. The USB333x can send single or back to back RXCMD’s as required. The Encoding of the RXCMD byte is given in the Table 6-3.  2009 - 2015 Microchip Technology Inc. DS00001880A-page 45 USB333x FIGURE 6-7: ULPI RXCMD TIMING T0 T1 T2 T3 T4 T5 T6 T7 T8 CLK DATA[7:0] Idle Turn around RXCMD Turn around Idle Turn around RXCMD RXCMD Turn around Idle DIR STP NXT Transfer of the RXCMD byte occurs in Synchronous Mode when the PHY has control of the bus. The ULPI Protocol Block shown in Figure 6-1 determines when to send an RXCMD. A RXCMD will occur: • • • • • When a linestate change occurs. When VBUS or ID comparators change state. During a USB receive when NXT is low. After the USB333x deasserts DIR and STP is low during start-up. After the USB333x exits Low Power Mode, Serial Modes, or Carkit Mode after detecting that the Link has deasserted STP, and DIR is low. When a USB Receive is occurring, RXCMD’s are sent whenever NXT = 0 and DIR = 1. During a USB Transmit, the RXCMD’s are returned to the Link after STP is asserted. If an RXCMD event occurs during a High Speed USB transmit, the RXCMD is blocked until STP de-asserts at the end of the transmit. The RXCMD contains the status that is current at the time the RXCMD is sent. TABLE 6-3: ULPI RX CMD ENCODING Data[7:0] Name [1:0] Linestate [3:2] Description and Value UTMI Linestate Signals. See Section 6.3.1.1 Encoded ENCODED VBUS VOLTAGE STATES VBUS State VALUE VBUS VOLTAGE DS00001880A-page 46 SESSEND SESSVLD VBUSVLD2 00 VVBUS < VSESS_END 1 0 0 01 VSESS_END < VVBUS < VSESS_VLD 0 0 0 10 VSESS_VLD < VVBUS < VVBUS_VLD X 1 0 11 VVBUS_VLD < VVBUS X X 1  2009 - 2015 Microchip Technology Inc. USB333x TABLE 6-3: ULPI RX CMD ENCODING (CONTINUED) Data[7:0] Name [5:4] Rx Event Encoding Description and Value ENCODED UTMI EVENT SIGNALS VALUE RXACTIVE RXERROR HOSTDISCONNECT 00 0 0 0 01 1 0 0 11 1 1 0 10 X X 1 State of ID Set to the logic state of the ID pin. A logic low indicates an A device. A logic high pin indicates a B device. [6] [7] alt_int Asserted when a non-USB interrupt occurs. This bit is set when an unmasked event occurs on any bit in the Carkit Interrupt Latch register. The Link must read the Carkit Interrupt Latch register to determine the source of the interrupt. Section 5.6.1 describes how a change on the ID pin can generate an interrupt. Section 6.8 describes how an interrupt can be generated when the RidConversionDone bit is set. Note 1: An ‘X’ is a do not care and can be either a logic 0 or 1. 2: The value of VbusValid is defined in Table 5-7. 6.3.1.1 Definition of Linestate The Linestate information is used to relay information back to the Link on the current status of the USB data lines, DP and DM. The definition of Linestate changes as the USB333x transitions between LS/FS mode, HS mode, and HS Chirp. 6.3.1.1.1 LS/FS Linestate Definitions In LS and FS operating modes the Linestate is defined by the outputs of the LS/FS Single Ended Receivers (SE RX). The logic thresholds for single ended receivers, VILSE and VILSE are shown in Table 4-6. TABLE 6-4: USB LINESTATE DECODING IN FS AND LS MODE Linestate[1:0] DP SE RX DM SE RX SE0 0 0 USB Reset 01 J (FS idle) 1 0 J State 10 K (LS Idle) 0 1 K State 11 SE1 1 1 SE1 00 State Low Speed uses the same Linestate decoding threshold as Full Speed. Low Speed re-defines the Idle state as an inversion of the Full Speed idle to account for the inversion which occurs in the hub repeater path. Linestates are decoded exactly as in Table 6-4 with the idle as a K state. 6.3.1.1.2 HS Linestate Definition In HS mode the data transmission is too fast for Linestate to be transmitted with each transition in the data packet. In HS operation the Linestate is redefined to indicate activity on the USB interface. The Linestate will signal the assertion and de-assertion of squelch in HS mode. TABLE 6-5: USB LINESTATE DECODING IN HS MODE Linestate[1:0] 00 SE0 DP SE RX DM SE RX 0 0 State HS Squelch asserted 01 J 1 0 HS Squelch de-asserted 10 K 0 1 Invalid State 11 SE1 1 1 Invalid State  2009 - 2015 Microchip Technology Inc. DS00001880A-page 47 USB333x 6.3.1.1.3 HS CHIRP Linestate Definition There is also a third use of Linestate in HS Chirp where when the Host and Peripheral negotiate the from FS mode to HS mode. While the transitions from K to J or SE0 are communicated to the Link through the Linestate information. TABLE 6-6: USB LINESTATE DECODING IN HS CHIRP MODE Linestate[1:0] DP SE RX DM SE RX State 00 SE0 0 0 HS Squelch asserted 01 J 1 0 HS Squelch de-asserted & HS differential Receiver = 1 10 K 0 1 HS Squelch de-asserted & HS differential Receiver = 0 11 SE1 1 1 Invalid State 6.3.2 USB RECEIVER The USB333x ULPI receiver fully supports HS, FS, and LS transmit operations. In all three modes the receiver detects the start of packet and synchronizes to the incoming data packet. In the ULPI protocol, a received packet has the priority and will immediately follow register reads and RXCMD transfers. Figure 6-8 shows a basic USB packet received by the USB333x over the ULPI interface. FIGURE 6-8: ULPI RECEIVE IN SYNCHRONOUS MODE CLK DATA[7:0] Idle Turn around Rxd Cmd PID D1 Rxd Cmd D2 Turn around DIR STP NXT In Figure 6-8 the PHY asserts DIR to take control of the data bus from the Link. The assertion of DIR and NXT in the same cycle contains additional information that Rxactive has been asserted. When NXT is de-asserted and DIR is asserted, the RXCMD data is transferred to the Link. After the last byte of the USB receive packet is transferred to the PHY, the linestate will return to idle. The ULPI Full Speed receiver operates according to the UTMI / ULPI specification. In the Full Speed case, the NXT signal will assert only when the Data bus has a valid received data byte. When NXT is low with DIR high, the RXCMD is driven on the data bus. In Full Speed, the USB333x will not issue a Rxactive de-assertion in the RXCMD until the DP/DM linestate transitions to idle. This prevents the Link from violating the two Full Speed bit times minimum turn around time. DS00001880A-page 48  2009 - 2015 Microchip Technology Inc. USB333x 6.3.2.1 Disconnect Detection A High Speed host must detect a disconnect by sampling the transmitter outputs during the long EOP transmitted during a SOF packet. The USB333x only looks for a High Speed disconnect during the long EOP where the period is long enough for the disconnect reflection to return to the host PHY. When a High Speed disconnect occurs, the USB333x will return a RXCMD and set the host disconnect bit in the USB Interrupt Status register. When in FS or LS modes, the Link is expected to handle all disconnect detection. 6.3.2.2 Link Power Management (LPM) Token Receive The USB333x is fully capable of receiving the Extended PID in the LPM token. When the LPM 0000b PID is received, this information is passed to the Link as a normal receive packet. If the Link chooses to enter LPM suspend, the procedure detailed in Section 6.5.3, "Link Power Management (LPM)," on page 53 can be followed. 6.4 USB333x Transmitter The USB333x ULPI transmitter fully supports HS, FS, and LS transmit operations. Figure 6-1 shows the High Speed, Full Speed, and Low Speed transmitter block controlled by ULPI Protocol Block. Encoding of the USB packet follows the bit-stuffing and NRZI outlined in the USB 2.0 specification. Many of these functions are reused between the HS and FS/LS transmitters. When using the USB333x, Table 5-1 should always be used as a guideline on how to configure for various modes of operation. The transmitter decodes the inputs of XcvrSelect[1:0], TermSelect, OpMode[1:0], DpPulldown, and DmPulldown to determine what operation is expected. Users must strictly adhere to the modes of operation given in Table 5-1. Several important functions for a device and host are designed into the transmitter blocks. The USB333x transmitter will transmit a 32-bit long High Speed sync before every High Speed packet. In Full and Low Speed modes a 8-bit sync is transmitted. When the device or host needs to chirp for High Speed port negotiation, the OpMode = 10 setting will turn off the bitstuffing and NRZI encoding in the transmitter. At the end of a chirp, the USB333x OpMode register bits should be changed only after the RXCMD linestate encoding indicates that the transmitter has completed transmitting. Should the opmode be switched to normal bit-stuffing and NRZI encoding before the transmit pipeline is empty, the remaining data in the pipeline may be transmitted in an bit-stuff encoding format. Please refer to the ULPI specification for a detailed discussion of USB reset and HS chirp. 6.4.1 USB333X HOST FEATURES The USB333x can also support USB Host operation and includes the following features that are required for Host operation. 6.4.1.1 High Speed Long EOP When operating as a High Speed host, the USB333x will automatically generate a 40 bit long End of Packet (EOP) after a SOF PID (A5h). The USB333x determines when to send the 40-bit long EOP by decoding the ULPI TX CMD bits [3:0] for the SOF. The 40-bit long EOP is only transmitted when the DpPulldown and DmPulldown bits in the OTG Control register are asserted. The High Speed 40-bit long EOP is used to detect a disconnect in mode. In device mode, the USB333x will not send a long EOP after a SOF PID. 6.4.1.2 Low Speed Keep-Alive Low Speed keep alive is supported by the USB333x. When in Low Speed mode, the USB333x will send out two Low Speed bit times of SE0 when a SOF PID is received. 6.4.1.3 UTMI+ Level 3 Pre-amble is supported for UTMI+ Level 3 compatibility. When XcvrSelect is set to (11b) in host mode, (DpPulldown and DmPulldown both asserted) the USB333x will pre-pend a Full Speed pre-amble before the Low Speed packet. Full Speed rise and fall times are used in this mode. The pre-amble consists of the following: Full Speed sync, the encoded pre-PID (C3h) and then Full Speed idle (DP=1 and DM = 0). A Low Speed packet follows with a sync, data and a LS EOP. The USB333x will only support UTMI+ Level 3 as a host. The USB333x does not support UTMI+ Level 3 as a peripheral. A UTMI+ Level 3 peripheral is an upstream hub port. The USB333x will not decode a pre-amble packet intended for a LS device when the USB333x is configured as the upstream port of a FS hub, XcvrSelect = 11b, DpPulldown = 0b, DmPulldown =0b.  2009 - 2015 Microchip Technology Inc. DS00001880A-page 49 USB333x 6.4.1.4 Host Resume K Resume K generation is supported by the USB333x. At the end of a USB Suspend the PHY will drive a K back to the downstream device. When the USB333x exits from Low Power Mode, when operating as a host, it will automatically transmit a Resume K on DP/DM. The transmitters will end the K with SE0 for two Low Speed bit times. If the USB333x was operating in High Speed mode before the suspend, the host must change to High Speed mode before the SE0 ends. SE0 is two Low Speed bit times which is about 1.2 us. For more details please see sections 7.1.77 and 7.9 of the USB Specification. In device mode, the resume K will not append an SE0, but release the bus to the correct idle state, depending upon the operational mode as shown in Table 5-1. The ULPI specification includes a detailed discussion of the resume sequence and the order of operations required. To support Host start-up of less than 1mS the USB333x implements the ULPI AutoResume bit in the Interface Control register. The default AutoResume state is 0 and this bit should be enabled for Host applications. 6.4.1.5 No SYNC and EOP Generation (OpMode = 11) UTMI+ defines OpMode = 11 where no sync and EOP generation occurs in High Speed operation. This is an option to the ULPI specification and not implemented in the USB333x. 6.4.2 TYPICAL USB TRANSMIT WITH ULPI Figure 6-9 shows a typical USB transmit sequence. A transmit sequence starts by the Link sending a TX CMD where DATA[7:6] = 01b, DATA[5:4] = 00b, and Data[3:0] = PID. The TX CMD with the PID is followed by transmit data. FIGURE 6-9: ULPI TRANSMIT IN SYNCHRONOUS MODE CLK DATA[7:0] Idle TXD CMD (USB tx) D0 D1 D2 D3 IDLE Turn Around RXD CMD Turn Around DIR NXT STP DP/DM SE0 !SQUELCH SE0 During transmit the PHY will use NXT to control the rate of data flow into the PHY. If the USB333x pipeline is full or bitstuffing causes the data pipeline to overfill NXT is de-asserted and the Link will hold the value on Data until NXT is asserted. The USB Transmit ends when the Link asserts STP while NXT is asserted. Note: The Link cannot assert STP with NXT de-asserted since the USB333x is expecting to fetch another byte from the Link. After the USB333x completes transmitting, the DP and DM lines return to idle and a RXCMD is returned to the Link so the inter-packet timers may be updated by linestate. While operating in Full Speed or Low Speed, an End-of-Packet (EOP) is defined as SE0 for approximately two bit times, followed by J for one bit time. The transceiver drives a J state for one bit time following the SE0 to complete the EOP. The Link must wait for one bit time following line state indication of the SE0 to J transition to allow the transceiver to complete the one bit time J state. All bit times are relative to the speed of transmission. In the case of Full Speed or Low Speed, after STP is asserted each FS/LS bit transition will generate a RXCMD since the bit times are relatively slow. DS00001880A-page 50  2009 - 2015 Microchip Technology Inc. USB333x 6.4.2.1 Link Power Management Token Transmit A Host Link can send a LPM command using the USB333x. When sending the LPM token the normal transmit method is not used. Sending a LPM token requires the USB333x to send a 0000b or ‘F0’ PID. When the ULPI specification was defined the ‘F0’ PID was not defined. The ULPI specification used the “Reserved” ‘F0’ PID to signal chirp and resume signaling while using OpMode 10b. While in OpMode 00b the USB333x is able to generate the ‘F0’ PID as shown below. FIGURE 6-10: LPM TOKEN TRANSMIT CLK DATA[7:0] Idle TXD CMD (40h TX NOPID ) PID (F0h) D0 D1 Turn Around IDLE Turn Around RXD CMD IDLE DIR NXT STP DP/DM SE0 !SQUELCH SE0 To send the ‘F0’ PID, the link will be required to use the TX CMD with NOPID to initiate the transmit and then follow up the TX CMD with the ‘F0’ PID. The data bytes follow as in a normal transmit, in OpMode 00b. The key difference is in that the link will have to send the PID the same as it would send a data packet. The USB333x is able to recognize the LPM transmit and correctly send the PID information. 6.5 Low Power Mode Low Power Mode is a power down state to save current when the USB session is suspended. The Link controls when the PHY is placed into or out of Low Power Mode. In Low Power Mode all of the circuits are powered down except the interface pins, Full Speed receiver, VBUS comparators, and IdGnd comparator. The VBUS and ID comparators can optionally be powered down to save current as shown in Section 6.5.5. Before entering Low Power Mode, the USB333x must be configured to set the desired state of the USB transceiver. The XcvrSelect[1:0], TermSelect and OpMode[1:0] bits in the Function Control register, and the DpPulldown and DmPulldown bits in the OTG Control register control the configuration as shown in Table 5-1. The DP and DM pins are configured to a high impedance state by configuring OpMode[1:0] = 01 as shown in the programming example in Table 6-8. Pull-down resistors with a value of approximately 2MΩ are present on the DP and DM pins to avoid false linestate indications that could result if the pins were allowed to float. 6.5.1 ENTERING LOW POWER/SUSPEND MODE To enter Low Power Mode, the Link will write a 0 or clear the SuspendM bit in the Function Control register. After this write is complete, the PHY will assert DIR high and after a minimum of five rising edges of CLKOUT, drive the clock low. After the clock is stopped, the PHY will enter a low power state to conserve current. Placing the PHY in Suspend Mode is not related to USB Suspend. To clarify this point, USB Suspend is initiated when a USB host stops data transmissions and enters Full-Speed mode with 15KΩ pull-down resistors on DP and DM. The suspended device goes to Full-Speed mode with a pull-up on DP. Both the host and device remain in this state until one of them drives DM high (this is called a resume).  2009 - 2015 Microchip Technology Inc. DS00001880A-page 51 USB333x FIGURE 6-11: ENTERING LOW POWER MODE FROM SYNCHRONOUS MODE T0 T1 T2 T3 T4 T5 T6 CLK DATA[7:0] Idle TXD CMD (reg write) Reg Data[n] Idle Turn Around ... T10 Low Power Mode DIR STP NXT SUSPENDM (ULPI Register Bit) While in Low Power Mode, the Data interface is redefined so that the Link can monitor Linestate and the VBUS voltage. In Low Power Mode DATA[3:0] are redefined as shown in Table 6-7. Linestate[1:0] is the combinational output of the Single-Ended Receivers. The “int” or interrupt signal indicates an unmasked interrupt has occurred. When an unmasked interrupt or linestate change has occurred, the Link is notified and can determine if it should wake-up the PHY. TABLE 6-7: Signal INTERFACE SIGNAL MAPPING DURING LOW POWER MODE Maps To Direction Description linestate[0] DATA[0] OUT Combinatorial LineState[0] driven directly by the Full-Speed single ended receiver. Note 6-1 linestate[1] DATA[1] OUT Combinatorial LineState[1] driven directly by the Full-Speed single ended receiver. Note 6-1 reserved DATA[2] OUT Driven Low int DATA[3] OUT Active high interrupt indication. Must be asserted whenever any unmasked interrupt occurs. reserved DATA[7:4] OUT Driven Low Note 6-1 LineState: These signals reflect the current state of the Full-Speed single ended receivers. LineState[0] directly reflects the current state of DP. LineState[1] directly reflects the current state of DM. When DP=DM=0 this is called "Single Ended Zero" (SE0). When DP=DM=1, this is called "Single Ended One" (SE1). An unmasked interrupt can be caused by the following comparators changing state: VbusVld, SessVld, SessEnd, and IdGnd. If any of these signals change state during Low Power Mode and the bits are enabled in either the USB Interrupt Enable Rising or USB Interrupt Enable Falling registers, DATA[3] will assert. During Low Power Mode, the VbusVld and SessEnd comparators can have their interrupts masked to lower the suspend current as described in Section 6.5.5. While in Low Power Mode, the Data bus is driven asynchronously because all of the PHY clocks are stopped during Low Power Mode. DS00001880A-page 52  2009 - 2015 Microchip Technology Inc. USB333x 6.5.2 EXITING LOW POWER MODE To exit Low Power Mode, the Link will assert STP. Upon the assertion of STP, the USB333x will begin its start-up procedure. After the PHY start-up is complete, the PHY will start the clock on CLKOUT and de-assert DIR. After DIR has been de-asserted, the Link can de-assert STP when ready and start operating in Synchronous Mode. The PHY will automatically set the SuspendM bit to a 1 in the Function Control register. FIGURE 6-12: EXITING LOW POWER MODE T0 ... CLK DATA[7:0] LOW POWER MODE T1 T2 TURN AROUND T3 DATA BUS IGNORED (SLOW LINK) IDLE (FAST LINK) Fast Link Drives Bus Idle and STP low DIR T4 T5 IDLE Slow Link Drives Bus Idle and STP low STP Note: Not to Scale TSTART The value for TSTART is given in Table 4-3. Should the Link de-assert STP before DIR is de-asserted, the USB333x will detect this as a false resume request and return to Low Power Mode. This is detailed in Section 3.9.4 of the UTMI+ Low Pin Interface (ULPI) Specification Revision 1.1. 6.5.3 LINK POWER MANAGEMENT (LPM) When the USB333x is operating with a Link capable of Link Power Management, the Link will place the USB333x in and out of suspend rapidly to conserve power. The USB333x provides a fast suspend recovery that allows the USB333x to meet the suspend recovery time detailed in the Link Power Management ECN to the USB 2.0 specification. When the Link places the USB333x into suspend during Link Power Management, the LPM Enable bit of the HS Compensation Register must be set to 1. This allows the USB333x to start-up in the time specified in Table 4-3. 6.5.4 INTERFACE PROTECTION ULPI protocol assumes that both the Link and PHY will keep the ULPI data bus driven by either the Link when DIR is low or the PHY when DIR is high. The only exception is when DIR has changed state and a turn around cycle occurs for 1 clock period. In the design of a USB system, there can be cases where the Link may not be driving the ULPI bus to a known state while DIR is low. Two examples where this can happen is because of a slow Link start-up or a hardware reset. 6.5.4.1 Start up Protection Upon start-up, when the PHY de-asserts DIR, the Link must be ready to receive commands and drive Idle on the data bus. If the Link is not ready to receive commands or drive Idle, it must assert STP before DIR is de-asserted. The Link can then de-assert STP when it has completed its start-up. If the Link doesn’t assert STP before it can receive commands, the PHY may interpret the data bus state as a TX CMD and transmit invalid data onto the USB bus, or make invalid register writes.  2009 - 2015 Microchip Technology Inc. DS00001880A-page 53 USB333x When the USB333x sends a RXCMD the Link is required to drive the data bus back to idle at the end of the turn around cycle. If the Link does not drive the databus to idle the USB333x may take the information on the data bus as a TXCMD and transmit data on DP and DM until the Link asserts stop. If the ID pin is floated the last RXCMD from the USB333x will remain on the bus after DIR is de-asserted and the USB333x will take this in as a TXCMD. A Link should be designed to have the default POR state of the STP output high and the data bus tri-stated. The USB333x has weak pull-downs on the data bus to prevent these inputs from floating when not driven. These resistors are only used to prevent the ULPI interface from floating during events when the link ULPI pins may be tri-stated. The strength of the pull down resistors can be found in Table 4-5. The pull downs are not strong enough to pull the data bus low after a ULPI RXCMD, the Link must drive the data bus to idle after DIR is de-asserted. In some cases, a Link may be software configured and not have control of its STP pin until after the PHY has started. In this case, the USB333x has in internal pull-up on the STP input pad which will pull STP high while the Link’s STP output is tri-stated. The STP pull-up resistor is enabled on POR and can be disabled by setting the InterfaceProtectDisable bit 7 of the Interface Control register. The STP pull-up resistor will pull-up the Link’s STP input high until the Link configures and drives STP high. After the Link completes its start-up, STP can be synchronously driven low. A Link design which drives STP high during POR can disable the pull-up resistor on STP by setting InterfaceProtectDisable bit to 1. A motivation for this is to reduce the suspend current. In Low Power Mode, STP is held low, which would draw current through the pull-up resistor on STP. 6.5.4.2 Warm Reset Designers should also consider the case of a warm restart of a Link with a PHY in Low Power Mode. After the PHY enters Low Power Mode, DIR is asserted and the clock is stopped. The USB333x looks for STP to be asserted to restart the clock and then resume normal synchronous operation. Should the USB333x be suspended in Low Power Mode, and the Link receives a hardware reset, the PHY must be able to recover from Low Power Mode and start its clock. If the Link asserts STP on reset, the PHY will exit Low Power Mode and start its clock. If the Link does not assert STP on reset, the interface protection pull-up can be used. When the Link is reset, its STP output will tri-state and the pull-up resistor will pull STP high, signaling the PHY to restart its clock. 6.5.5 MINIMIZING CURRENT IN LOW POWER MODE In order to minimize the suspend current in Low Power Mode, the VBUS and ID comparators can be disabled to reduce suspend current. In Low Power Mode, the VbusVld and SessEnd comparators are not needed and can be disabled by clearing the associated bits in both the USB Interrupt Enable Rising and USB Interrupt Enable Falling registers. By disabling the interrupt in BOTH the rise and fall registers, the SessEnd and VbusVld comparators are turned off. The IdFloatRise and IdFloatFall bits in Carkit Interrupt Enable register should also be disabled if they were set. When exiting Low Power Mode, the Link should immediately re-enable the VbusVld and SessEnd comparators if host or OTG functionality is required. In addition to disabling the OTG comparators in Low Power Mode, the Link may choose to disable the Interface Protect Circuit. By setting the InterfaceProtectDisable bit high in the Interface Control register, the Link can disable the pull-up resistor on STP. When RESETB is low the Interface Protect Circuit will be disabled. 6.6 Full Speed/Low Speed Serial Modes The USB333x includes two serial modes to support legacy Links which use either the 3pin or 6pin serial format. To enter either serial mode, the Link will need to write a 1 to the 6-pin FsLsSerialMode or the 3-pin FsLsSerialMode bits in the Interface control register. Serial Mode may be used to conserve power when attached to a device that is not capable of operating in High Speed. The serial modes are entered in the same manner as the entry into Low Power Mode. The Link writes the Interface Control register bit for the specific serial mode. The USB333x will assert DIR and shut off the clock after at least five clock cycles. Then the data bus goes to the format of the serial mode selected. Before entering Serial Mode the Link must set the ULPI transceiver to the appropriate mode as defined in Table 5-1. In ULPI Clock Out Mode, the PHY will shut off the 60MHz clock to conserve power. Should the Link need the 60MHz clock to continue during the serial mode of operation, the ClockSuspendM bit[3] of the Interface Control Register should be set before entering a serial mode. If set, the 60 MHz clock will be present during serial modes. DS00001880A-page 54  2009 - 2015 Microchip Technology Inc. USB333x In serial mode, interrupts are possible from unmasked sources. The state of each interrupt source is sampled prior to the assertion of DIR and this is compared against the asynchronous level from interrupt source. Exiting the serial modes is the same as exiting Low Power Mode. The Link must assert STP to signal the PHY to exit serial mode. When the PHY can accept a command, DIR is de-asserted and the PHY will wait until the Link de-asserts STP to resume synchronous ULPI operation. The RESETB pin can also be pulsed low to reset the USB333x and return it to Synchronous Mode. 6.6.1 3-PIN FS/LS SERIAL MODE Three pin serial mode utilizes the data bus pins for the serial functions shown in Table 6-8. TABLE 6-8: PIN DEFINITIONS IN 3 PIN SERIAL MODE Signal Connected To tx_enable DATA[0] IN Active High transmit enable. data DATA[1] I/O TX differential data on DP/DM when tx_enable is high. RX differential data from DP/DM when tx_enable is low. SE0 DATA[2] I/O TX SE0 on DP/DM when tx_enable is high. RX SE0_b from DP/DM when tx_enable is low. interrupt DATA[3] OUT Asserted when any unmasked interrupt occurs. Active high. Reserved DATA[7:4] OUT Driven Low. 6.6.2 Direction Description 6-PIN FS/LS SERIAL MODE Six pin serial mode utilizes the data bus pins for the serial functions shown in Table 6-9. TABLE 6-9: PIN DEFINITIONS IN 6 PIN SERIAL MODE Signal Connected To Direction tx_enable DATA[0] IN Active High transmit enable. tx_data DATA[1] IN Tx differential data on DP/DM when tx_enable is high. tx_se0 DATA[2] IN Tx SE0 on DP/DM when tx_enable is high. interrupt DATA[3] OUT Asserted when any unmasked interrupt occurs. Active high. rx_dp DATA[4] OUT Single ended receive data on DP. rx_dm DATA[5] OUT Single ended receive data on DM. rx_rcv DATA[6] OUT Differential receive data from DP and DM. Reserved DATA[7] OUT Driven Low. 6.7 Description Carkit Mode The USB333x includes Carkit Mode to support a USB UART and USB Audio Mode. By entering Carkit Mode, the USB333x current drain is minimized. The internal PLL is disabled and the 60MHz ULPI CLKOUT will be stopped to conserve power by default. The Link may configure the 60MHz clock to continue by setting the ClockSuspendM bit of the Interface Control register before entering Carkit Mode. If set, the 60 MHz clock will continue during the Carkit Mode of operation. In Carkit Mode, interrupts are possible if they have been enabled in the Carkit Interrupt Enable register. The state of each interrupt source is sampled prior to the assertion of DIR and this is compared against the asynchronous level from interrupt source. In Carkit Mode, the Linestate signals are not available per the ULPI specification. The ULPI interface is redefined to the following when Carkit Mode is entered.  2009 - 2015 Microchip Technology Inc. DS00001880A-page 55 USB333x TABLE 6-10: PIN DEFINITIONS IN CARKIT MODE Signal Connected To Direction Description txd DATA[0] IN UART TXD signal that is routed to the DM pin if the TxdEn is set in the Carkit Control register. rxd DATA[1] OUT UART RXD signal that is routed to the DP pin if the RxdEn bit is set in the Carkit Control register. reserved DATA[2] OUT Driven Low (CarkitDataMC = 0, default) IN Tri-state (CarkitDataMC = 1) OUT Asserted when any unmasked interrupt occurs. Active high. int DATA[3] DATA[4:7] OUT Driven Low. reserved Exiting Carkit Mode is the same as exiting Low Power Mode as described in Section 6.5.2. The Link must assert STP to signal the PHY to exit serial mode. When the PHY can accept a command, DIR is de-asserted and the PHY will wait until the Link de-asserts STP to resume synchronous ULPI operation. The RESETB pin can also be pulsed low to reset the USB333x and return it to Synchronous Mode. 6.7.1 ENTERING USB UART MODE The USB333x can be placed into UART Mode by first setting the TxdEn and RxdEn bits in the Carkit Control register. Then the Link can set the CarkitMode bit in the Interface Control register. The TxdEn and RxdEn bits must be written before the CarkitMode bit. TABLE 6-11: ULPI REGISTER PROGRAMMING EXAMPLE TO ENTER UART MODE R/W Address (HEX) Value (HEX) W 04 49 Description Result Configure Non-Driving mode Select FS transmit edge rates OpMode=01 XcvrSelect=01 W 39 00 Set regulator to 3.3V UART RegOutput=00 W 19 0C Enable UART connections RxdEn=1 TxdEn=1 W 07 04 Enable carkit mode CarkitMode=1 After the CarkitMode bit is set, the ULPI interface will become redefined as described in Table 6-10, and the USB333x will transmit data through the DATA[0] to DM of the USB connector and receive data on DP and pass the information the Link on DATA[1]. When entering UART mode, the regulator output will automatically switch to the value configured by the UART RegOutput bits in the USB IO & Power Management register and the RCD pull-up resistors will be applied internally to DP and DM. This will hold the UART in its default operating state. While in UART mode, the transmit edge rates can be set to either the Full Speed USB or Low Speed USB edge rates by using the XcvrSelect[1:0] bits in the Function Control register. 6.7.2 USB AUDIO MODE (USB3331, USB3336, AND USB3338) When the USB333x is powered in Synchronous Mode, the Audio switches can be enabled by asserting the SpkLeftEn, or SpkRightEn bits in the Carkit Control register. After the register write is complete, the USB333x will immediately enable or disable the audio switch. Then the Link can set the CarkitMode bit in the Interface Control register. The SpkLeftEn, or SpkRightEn bits must be written before the CarkitMode bit. TABLE 6-12: ULPI REGISTER PROGRAMMING EXAMPLE TO ENTER AUDIO MODE R/W Address (HEX) Value (HEX) Description Result W 04 48 Configure Non-Driving mode OpMode=01 W 19 30 Enable Audio connections SpkrRightEn=1, SpkrLeftEn=1 W 07 04 Enable carkit mode CarkitMode=1 After the CarkitMode bit is set, the ULPI interface will become redefined as described in Table 6-10. DS00001880A-page 56  2009 - 2015 Microchip Technology Inc. USB333x 6.8 RID Converter Operation The RID converter is designed to read the value of the ID resistance to ground and report back its value through the ULPI interface. When a resistor to ground is applied to the ID pin the state of the IdGnd comparator will change from a 1 to a 0 as described in Section 5.6.1. If the USB333x is in ULPI mode, an RXCMD will be generated with bit 6 low. If the USB333x is in Low Power Mode (or one of the other non-ULPI modes), the DATA[3] interrupt signal will go high. After the USB333x has detected the change of state on the ID pin, the RID converter can be used to determine the value of ID resistance. To start a ID resistance measurement, the RidConversionStart bit is set in the Vendor Rid Conversion register. The Link can use one of two methods to determine when the RID Conversion is complete. One method is polling the RidConversionStart bit as described in Section 7.1.3.4. The preferred method is to set the RidIntEn bit in the Vendor Rid Conversion register. When RidIntEn is set, an RXCMD will be generated after the RID conversion is complete. As described in Table 6-3, the alt_int bit of the RXCMD will be set. After the RID Conversion is complete, the Link can read RidValue from the Vendor Rid Conversion register. 6.9 Headset Audio Mode This mode is designed to allow a user to view the status of several signals while using an analog Audio headset with a USB connector. This mode is provided as an alternate mode to the CarKit Mode defined in Section 6.7, "Carkit Mode". In the CarKit mode the Link is unable to view the source of the interrupt on ID. For the Link to view the interrupt on ID the PHY must be returned to synchronous mode so the interrupt can be read. This will force the audio switches to be deactivated during the PHY start-up which may glitch the audio signals. In addition the Link can not change the resistance on the ID pin without starting up the PHY to access the ULPI registers. The Headset Audio Mode is entered by writing to the Headset Audio Mode register, and allows the Link access to the state of the VBUS and ID pins during audio without having to break the audio connection. The Headset Audio mode also allows for the Link to change the resistance on the ID pin to change the audio device attached from mono to stereo. TABLE 6-13: Signal PIN DEFINITIONS IN HEADSET AUDIO MODE Connected To Direction Description SessVld DATA[0] OUT Output of SessVld comparator VbusVld DATA[1] OUT Output of VbusVld Comparator (interrupt must be enabled) IdGndDrv DATA[2] IN Drives ID pin to ground when asserted 0b: Not connected 1b: Connects ID to ground. DATA[3] OUT Driven low IdGround DATA[4] OUT Asserted when the ID pin is grounded. 0b: ID pin is grounded 1b: ID pin is floating IdFloat DATA[5] OUT Asserted when the ID pin is floating. IdPullup or Id_pullup330 must be enabled. IdFloatRise and IdFloatFall must be enabled. IdPullup330 DATA[6] IN When enabled a 330kΩ pullup is applied to the ID pin. This bit will also change the trip point of the IdGnd comparator to the value shown in Table 4-9. 0b: Disables the pull-up resistor 1b: Enables the pull-up resistor Connects the 100kΩ pull-up resistor from the ID pin to VDD3.3 0b: Disables the pull-up resistor 1b: Enables the pull-up resistor Exiting Headset Audio Mode is the same as exiting Low Power Mode as described in Section 6.5.2. The RESETB pin can also be pulsed low to reset the USB333x and return to Synchronous Mode. IdPullup DATA[7] IN  2009 - 2015 Microchip Technology Inc. DS00001880A-page 57 USB333x 7.0 ULPI REGISTER MAP 7.1 ULPI Register Array The USB333x PHY implements all of the ULPI registers detailed in the ULPI revision 1.1 specification. The complete USB333x ULPI register set is shown in Table 7-1. All registers are 8 bits. This table also includes the default state of each register upon POR or de-assertion of RESETB, as described in Section 5.5.2. The RESET bit in the Function Control Register does not reset the bits of the ULPI register array. The Link should not read or write to any registers not listed in this table. The USB333x supports extended register access. The immediate register set (00-3Fh) can be accessed through either a immediate address or an extended register address. TABLE 7-1: ULPI REGISTER MAP Address (6bit) Default State Read Write Set Clear 24h 00h - - - Vendor ID High 04h 01h - - - Product ID Low 0Bh 02h - - - Product ID High 00h 03h - - - Function Control 41h 04-06h 04h 05h 06h Interface Control 00h 07-09h 07h 08h 09h OTG Control 06h 0A-0Ch 0Ah 0Bh 0Ch USB Interrupt Enable Rising 1Fh 0D-0Fh 0Dh 0Eh 0Fh USB Interrupt Enable Falling 1Fh 10-12h 10h 11h 12h USB Interrupt Status (Note 7-1) 00h 13h - - - USB Interrupt Latch 00h 14h - - - Debug 00h 15h - - - Scratch Register 00h 16-18h 16h 17h 18h Carkit Control 00h 19-1Bh 19h 1Ah 1Bh Reserved 00h Carkit Interrupt Enable 00h 1D-1Fh 1Dh 1Eh 1Fh Carkit Interrupt Status 00h 20h - - - Carkit Interrupt Latch 00h 21h - - - Reserved 00h HS Compensation Register 00h 31h 31h - - USB-IF Charger Detection 00h 32h 32h - - Headset Audio Mode 00 33 33 - - Reserved 00h Vendor Rid Conversion 00h 36-38h 36h 37h 38h USB IO & Power Management 04h 39-3Bh 39h 3Ah 3Bh Reserved 00h Register Name Vendor ID Low Note 7-1 1Ch 22-30h 34-35h 3C-3Fh Dynamically updates to reflect current status of interrupt sources. DS00001880A-page 58  2009 - 2015 Microchip Technology Inc. USB333x 7.1.1 ULPI REGISTER SET The following registers are used for the ULPI interface. 7.1.1.1 Vendor ID Low Address = 00h (read only) Field Name Vendor ID Low 7.1.1.2 Bit Access Default 7:0 rd 24h Bit Access Default 7:0 rd 04h Description MCHP Vendor ID Vendor ID High Address = 01h (read only) Field Name Vendor ID High 7.1.1.3 Description MCHP Vendor ID Product ID Low ARCHITECTURE NOTE: Address = 02h (read only) Field Name Product ID Low Note 7-2 7.1.1.4 Bit Access Default 7:0 rd Note 7-2 Description MCHP Product ID USB333x: Default = 0Bh Product ID High Address = 03h (read only) Field Name Product ID High 7.1.1.5 Bit Access Default 7:0 rd 00h Description MCHP Product ID Function Control Address = 04-06h (read), 04h (write), 05h (set), 06h (clear) Field Name XcvrSelect[1:0] TermSelect OpMode Reset Bit Access Default 1:0 rd/w/s/c 01b Selects the required transceiver speed. 00b: Enables HS transceiver 01b: Enables FS transceiver 10b: Enables LS transceiver 11b: Enables FS transceiver for LS packets (FS preamble automatically pre-pended) 2 rd/w/s/c 0b Controls the DP and DM termination depending on XcvrSelect, OpMode, DpPulldown, and DmPulldown. The DP and DM termination is detailed in Table 5-1. 4:3 rd/w/s/c 00b Selects the required bit encoding style during transmit. 00b: Normal Operation 01b: Non-Driving 10b: Disable bit-stuff and NRZI encoding 11b: Reserved 5 rd/w/s/c 0b Active high transceiver reset. This reset does not reset the ULPI interface or register set. Automatically clears after reset is complete.  2009 - 2015 Microchip Technology Inc. Description DS00001880A-page 59 USB333x Bit Access Default Description SuspendM Field Name 6 rd/w/s/c 1b Active low PHY suspend. When cleared the PHY will enter Low Power Mode as detailed in Section 6.5 “Low Power Mode”. Automatically set when exiting Low Power Mode. LPM Enable 7 rd/w/s/c 0b When enabled the PLL start-up time is shortened to allow fast start-up for LPM. The reduced PLL start-up time is achieved by bypassing the VCO process compensation which was done on initial start-up. 7.1.1.6 Interface Control Address = 07-09h (read), 07h (write), 08h (set), 09h (clear) Field Name Bit Access Default Description 6-pin FsLsSerialMode 0 rd/w/s/c 0b When asserted the ULPI interface is redefined to the 6-pin Serial Mode. The PHY will automatically clear this bit when exiting serial mode. 3-pin FsLsSerialMode 1 rd/w/s/c 0b When asserted the ULPI interface is redefined to the 3-pin Serial Mode. The PHY will automatically clear this bit when exiting serial mode. CarkitMode 2 rd/w/s/c 0b When asserted the ULPI interface is redefined to the Carkit interface. The PHY will automatically clear this bit when exiting Carkit Mode. ClockSuspendM 3 rd/w/s/c 0b Enables Link to turn on 60MHz CLKOUT in Serial Mode or Carkit Mode. 0b: Disable clock in serial or Carkit Mode. 1b: Enable clock in serial or Carkit Mode. AutoResume 4 rd/w/s/c 0b Only applicable in Host mode. Enables the PHY to automatically transmit resume signaling. This function is detailed in Section 6.4.1.4. IndicatorComplement 5 rd/w/s/c 0b Inverts the EXTVBUS signal. This function is detailed in Section 5.6.2. Note: IndicatorPassThru 6 rd/w/s/c 0b Disables and’ing the internal VBUS comparator with the EXTVBUS signal when asserted. This function is detailed in Section 5.6.2. Note: InterfaceProtectDisable DS00001880A-page 60 7 rd/w/s/c 0b The EXTVBUS signal is always high on the USB333x. The EXTVBUS signal is always high on the USB333x. Used to disable the integrated STP pull-up resistor used for interface protection. This function is detailed in Section 6.5.4.  2009 - 2015 Microchip Technology Inc. USB333x 7.1.1.7 OTG Control Address = 0A-0Ch (read), 0Ah (write), 0Bh (set), 0Ch (clear) Field Name Bit Access Default Description IdPullup 0 rd/w/s/c 0b Connects a 100kΩ pull-up resistor from the ID pin to VDD33 0b: Disables the pull-up resistor 1b: Enables the pull-up resistor DpPulldown 1 rd/w/s/c 1b Enables the 15k Ohm pull-down resistor on DP. 0b: Pull-down resistor not connected 1b: Pull-down resistor connected DmPulldown 2 rd/w/s/c 1b Enables the 15k Ohm pull-down resistor on DM. 0b: Pull-down resistor not connected 1b: Pull-down resistor connected DischrgVbus 3 rd/w/s/c 0b This bit is only used during SRP. Connects a resistor from VBUS to ground to discharge VBUS. 0b: disconnect resistor from VBUS to ground 1b: connect resistor from VBUS to ground ChrgVbus 4 rd/w/s/c 0b This bit is only used during SRP. Connects a resistor from VBUS to VDD33 to charge VBUS above the SessValid threshold. 0b: disconnect resistor from VBUS to VDD33 1b: connect resistor from VBUS to VDD33 DrvVbus 5 rd/w/s/c 0b Not Implemented. DrvVbusExternal 6 rd/w/s/c 0b Not Implemented. UseExternalVbus Indicator 7 rd/w/s/c 0b Tells the PHY to use an external VBUS over-current or voltage indicator. This function is detailed in Section 5.6.2. 0b: Use the internal VbusValid comparator 1b: Use the EXTVBUS input as for VbusValid signal. Note: 7.1.1.8 The EXTVBUS signal is always high on the USB333x. USB Interrupt Enable Rising Address = 0D-0Fh (read), 0Dh (write), 0Eh (set), 0Fh (clear) Field Name Bit Access Default Description HostDisconnect Rise 0 rd/w/s/c 1b Generate an interrupt event notification when Hostdisconnect changes from low to high. Applicable only in host mode. VbusValid Rise 1 rd/w/s/c 1b Generate an interrupt event notification when Vbusvalid changes from low to high. SessValid Rise 2 rd/w/s/c 1b Generate an interrupt event notification when SessValid changes from low to high. SessEnd Rise 3 rd/w/s/c 1b Generate an interrupt event notification when SessEnd changes from low to high. IdGnd Rise 4 rd/w/s/c 1b Generate an interrupt event notification when IdGnd changes from low to high. 7:5 rd 0h Read only, 0. Reserved  2009 - 2015 Microchip Technology Inc. DS00001880A-page 61 USB333x 7.1.1.9 USB Interrupt Enable Falling Address = 10-12h (read), 10h (write), 11h (set), 12h (clear) Field Name Bit Access Default Description HostDisconnect Fall 0 rd/w/s/c 1b Generate an interrupt event notification when Hostdisconnect changes from high to low. Applicable only in host mode. VbusValid Fall 1 rd/w/s/c 1b Generate an interrupt event notification when Vbusvalid changes from high to low. SessValid Fall 2 rd/w/s/c 1b Generate an interrupt event notification when SessValid changes from high to low. SessEnd Fall 3 rd/w/s/c 1b Generate an interrupt event notification when SessEnd changes from high to low. IdGnd Fall 4 rd/w/s/c 1b Generate an interrupt event notification when IdGnd changes from high to low. Reserved 7:5 rd 0h Read only, 0. 7.1.1.10 USB Interrupt Status Address = 13h (read only) This register dynamically updates to reflect current status of interrupt sources. Field Name Bit Access Default Description HostDisconnect 0 0b Current value of the UTMI+ HS Hostdisconnect output. Applicable only in host mode. VbusValid 1 0b Current value of the UTMI+ Vbusvalid output. If VbusValid Rise and VbusValid Fall are set this register will read 0. SessValid 2 0b Current value of the UTMI+ SessValid output. This register will always read the current status of the Session Valid comparator regardless of the SessValid Rise and SessValid Fall settings. 3 0b Current value of the UTMI+ SessEnd output. If SessEnd Rise and SessEnd Fall are set this register will read 0. 4 0b Current value of the UTMI+ IdGnd output. 7:5 0h Read only, 0. rd (read only) SessEnd IdGnd Reserved Note: The default value is only valid after POR. When the register is read it will match the current status of the comparators at the moment the register is read. DS00001880A-page 62  2009 - 2015 Microchip Technology Inc. USB333x 7.1.1.11 USB Interrupt Latch Address = 14h (read only with auto clear) Field Name Bit Access Default Description HostDisconnect Latch 0 0b Set to 1b by the PHY when an unmasked event occurs on Hostdisconnect. Cleared when this register is read. Applicable only in host mode. VbusValid Latch 1 0b Set to 1b by the PHY when an unmasked event occurs on VbusValid. Cleared when this register is read. SessValid Latch 2 0b Set to 1b by the PHY when an unmasked event occurs on SessValid. Cleared when this register is read. SessEnd Latch 3 0b Set to 1b by the PHY when an unmasked event occurs on SessEnd. Cleared when this register is read. IdGnd Latch 4 0b Set to 1b by the PHY when an unmasked event occurs on IdGnd. Cleared when this register is read. 0h Read only, 0. rd (Note 7-3) Reserved 7:5 Note 7-3 rd: Read Only with auto clear. 7.1.1.12 rd Debug Address = 15h (read only) Field Name Bit Access Default Linestate[1:0] 1:0 rd 00b Reserved 7:2 rd 000000b 7.1.1.13 Description Contains the current value of Linestate[1:0]. Read only, 0. Scratch Register Address = 16-18h (read), 16h (write), 17h (set), 18h (clear) Field Name Scratch Bit Access Default 7:0 rd/w/s/c 00h  2009 - 2015 Microchip Technology Inc. Description Empty register byte for testing purposes. Software can read, write, set, and clear this register and the PHY functionality will not be affected. DS00001880A-page 63 USB333x 7.1.2 CARKIT CONTROL REGISTERS The following registers are used to set-up and enable the USB UART and USB Audio functions. 7.1.2.1 Carkit Control Address = 19-1Bh (read), 19h (write), 1Ah (set), 1Bh (clear) This register is used to program the USB333x into and out of the Carkit Mode. When entering the UART mode the Link must first set the desired TxdEn and the RxdEn bits and then transition to Carkit Mode by setting the CarkitMode bit in the Interface Control Register. When RxdEn is not set then the DATA[1] pin is held to a logic high. Field Name Bit Access Default CarkitPwr 0 rd 0b Read only, 0. IdGndDrv 1 rd/w/s/c 0b Drives ID pin to ground TxdEn 2 rd/w/s/c 0b Connects UART TXD (DATA[0]) to DM RxdEn 3 rd/w/s/c 0b Connects UART RXD (DATA[1]) to DP SpkLeftEn 4 rd/w/s/c 0b Connects DM pin to SPK_L pin SpkRightEn 5 rd/w/s/c 0b Connects DP pin to SPK_R pin. See Note below. MicEn 6 rd/w/s/c 0b Connects DP pin to SPK_R pin. See Note below. CarkitDataMC 7 rd/w/s/c 0b When set the UPLI DATA[2] pin is changed from a driven 0 to tri-state, when carkit mode is entered. Note: Description USB3331, USB3336, and USB3338 Only: If SpkRightEn or MicEn are asserted the DP pin will be connected to SPK_R. To disconnect the DP pin from the SPK_R pin both SpkrRightEn and MicEn must be set to de-asserted. If using USB UART mode, the UART data will appear at the SPK_L and SPK_R pins if the corresponding SpkLeftEn, SpkRightEn, or MicEn switches are enabled. If using USB Audio ((USB3331, USB3336, and USB3338 only), the TxdEn and RxdEn bits should not be set when the SpkLeftEn, SpkRightEn, or MicEn switches are enabled. The USB single-ended receivers described in Section 5.2.1 are disabled when either SpkLeftEn, SpkRightEn, or MicEn are set. 7.1.2.2 Carkit Interrupt Enable Address = 1D-1Fh (read), 1Dh (write), 1Eh (set), 1Fh (clear) Field Name Bit Access Default Description IdFloatRise 0 rd/w/s/c 0b When enabled an interrupt will be generated on the alt_int of the RXCMD byte when the ID pin transitions from non-floating to floating. The IdPullup bit in the OTG Control register should be set. IdFloatFall 1 rd/w/s/c 0b When enabled an interrupt will be generated on the alt_int of the RXCMD byte when the ID pin transitions from floating to non-floating. The IdPullup bit in the OTG Control register should be set. VdatDetIntEn 2 rd/w/s/c 0b When enabled an interrupt will be generated on the alt_int of the RXCMD byte when the VDAT_DET Comparator changes state. CarDpRise 3 rd 0b Not Implemented. Reads as 0b. DS00001880A-page 64  2009 - 2015 Microchip Technology Inc. USB333x Bit Access Default CarDpFall Field Name 4 rd 0b Not Implemented. Reads as 0b. Description RidIntEn 5 rd/w/s/c 0b When enabled an interrupt will be generated on the alt_int of the RXCMD byte when RidConversionDone bit is asserted. Note: This register bit is or’ed with the RidIntEn bit of the Vendor Rid Conversion register described in Section 7.1.3.4. Reserved 6 rd/w/s/c 0b Read only, 0. Reserved 7 rd 0b Read only, 0. Bit Access Default Description IdFloat 0 rd 0b Asserted when the ID pin is floating. IdPullup must be enabled. VdatDet 1 rd 0b VDAT_DET Comparator output 0b: No voltage is detected on DP 1b: Voltage detected on DP, IdatSinkEn must be set to 1. 7.1.2.3 Carkit Interrupt Status Address = 20h (read only) Field Name Note: CarDp RidValue 2 rd 0b Not Implemented. Reads as 0b. 5:3 rd 000b Conversion value of Rid resistor 000: 0 ohms 001: 75 ohms 010: 102K ohms 011: 200K ohms 100: Reserved 101: ID floating 111: Error Note: RidConversionDone 6 rd 0b 7  2009 - 2015 Microchip Technology Inc. rd 0b RidValue can also be read from the Vendor Rid Conversion register described in Section 7.1.3.4. Automatically asserted by the USB333x when the Rid Conversion is finished. The conversion will take 282uS. This bit will auto clear when the RidValue is read from the Rid Conversion Register. Reading the RidValue from the Carkit Interrupt Status register will not clear either RidConversionDone status bit. Note: Reserved VdatDet can also be read from the USB-IF Charger Detection register described in Section 7.1.3.4. RidConversionDone can also be read from the Vendor Rid Conversion register described in Section 7.1.3.4. Read only, 0. DS00001880A-page 65 USB333x 7.1.2.4 Carkit Interrupt Latch Address = 21h (read only with auto-clear) Field Name Bit Access Default Description IdFloat Latch 0 rd (Note 74) 0b Asserted if the state of the ID pin changes from nonfloating to floating while the IdFloatRise bit is enabled or if the state of the ID pin changes from floating to non-floating while the IdFloatFall bit is enabled. VdatDet Latch 1 rd 0b If VdatDetIntEn is set and the VdatDet bit changes state, this bit will be asserted. CarDp Latch 2 rd 0b Not Implemented. Reads as 0b. RidConversionLatch 3 rd (Note 7-4) 0b If RidIntEn is set and the state of the RidConversionDone bit changes from a 0 to 1 this bit will be asserted. 7:4 rd 0000b Reserved Note 7-4 7.1.3 Read only, 0. rd: Read Only with auto clear VENDOR REGISTER ACCESS The vendor specific registers include the range from 30h to 3Fh. These can be accessed by the ULPI immediate register read / write. 7.1.3.1 HS Compensation Register Address = 31h (read / write) The USB333x is designed to meet the USB specifications and requirements when the DP and DM signals are properly designed on the PCB. The DP and DM trace impedance should be 45ohm single ended and 90ohm differential. In cases where the DP and DM traces are not able to meet these requirements the HS Compensation register can be used to compensate for the losses in signal amplitude. Field Name Bit Access Default VariSense 1:0 rd/w 00b Used to lower the threshold of the squelch detector. 00: 100% (default) 01: 83% 10: 66.7% 11: 55% Reserved 2 rd 0b Read only, 0. Reserved 3 rd 0b Read only, 0. PHYBoost 6:4 rd/w 000b Reserved 7 rd 0b DS00001880A-page 66 Description Used to change the output voltage of the High Speed transmitter 000: Nominal 001: +3.7% 010: -7.4% 011: -3.7% 100: +14.7% 101: +18.3% 110: +7.4% 111: +11.0% Read only, 0.  2009 - 2015 Microchip Technology Inc. USB333x 7.1.3.2 USB-IF Charger Detection Address = 32h (read / write) Field Name Bit Access Default Description VDatSrcEn 0 rd/w 0 VDAT_SRC voltage enable 0b: Disabled 1b: Enabled IDatSinkEn 1 rd/w 0 IDAT_SINK current sink and VDAT_DET comparator enable 0b: Disabled, VDAT_DET = 0. 1b: Enabled ContactDetectEn 2 rd/w 0 IDP_SRC Enable 0b: Disabled 1b: Enabled HostChrgEn 3 rd/w 0 Enable Charging Host Port Mode. 0b: Portable Device 1b: Charging Host Port. When the charging host port bit is set the connections of VDAT_SRC, IDAT_SINK, IDP_SRC, and VDAT_DET are reversed between DP and DM. VdatDet 4 rd 0 VDAT_DET Comparator output. IdatSinkEn must be set to 1 to enable the comparator. 0b: No voltage is detected on DP or Linestate[1:0] is not equal to 00b. 1b: Voltage detected on DP, and Linestate[1:0] = 00b. Note: 5-7 Reserved Note: 7.1.3.3 rd VdatDet can also be read from the Carkit Interrupt Status register described in Section 7.1.2.3. Read only, 0. The charger detection should be turned off before beginning USB operation. USB-IF Charger Detection Bits 2:0 should be set to 000b. Headset Audio Mode Address = 33h (read / write) Field Name Bit Access Default Description When this field is set to a value of ‘1010’, the Headset Audio Mode is enabled as described in Section 6.9. HeadsetAudioEn 3:0 rd/w 0000b Reserved 7:4 rd 0h  2009 - 2015 Microchip Technology Inc. Read only, 0. DS00001880A-page 67 USB333x 7.1.3.4 Vendor Rid Conversion Address = 36-38h (read), 36h (write), 37h (set), 38h (clear) Field Name RidValue Bit Access Default 2:0 rd/w 000b Description Conversion value of Rid resistor 000: 0 ohms 001: 75 ohms 010: 100K ohms 011: 200K ohms 100: Reserved 101: ID floating 111: Error Note: RidConversionDone 3 rd (Note 75) 0b RidValue can also be read from the Carkit Interrupt Status Register. Automatically asserted by the USB333x when the Rid Conversion is finished. The conversion will take 282uS. This bit will auto clear when the RidValue is read from the Rid Conversion Register. Reading the RidValue from the Carkit Interrupt Status Register will not clear either RidConversionDone status bit. Note: RidConversionDone can also be read from the Carkit Interrupt Status Register. RidConversionStart 4 rd/w/s/c 0b When this bit is asserted either through a register write or set, the Rid converter will read the value of the ID resistor. When the conversion is complete this bit will auto clear. Reserved 5 rd/w/s/c 0b This bit must remain at 0. RidIntEn 6 rd/w/s/c 0b When enabled an interrupt will be generated on the alt_int of the RXCMD byte when RidConversionDone bit is asserted. Note: Reserved Note 7-5 7 rd rd: Read Only with auto clear DS00001880A-page 68 0b This register bit is or’ed with the RidIntEn bit of the Carkit Interrupt Status register. Read only, 0.  2009 - 2015 Microchip Technology Inc. USB333x 7.1.3.5 USB IO & Power Management Address = 39-3Bh (read), 39h (write), 3Ah (set), 3Bh (clear) Field Name Bit Access Default Reserved 0 rd/w/s/c 0b Read only, 0. SwapDP/DM 1 rd/w/s/c 0b When asserted, the DP and DM pins of the USB PHY are swapped. This bit can be used to prevent crossing the DP/DM traces on the board. In UART mode, it swaps the routing to the DP and DM pins. In USB Audio Mode, it does not affect the SPK_L and SPK_R pins. 3:2 rd/w/s/c 01b Controls the output voltage of the VBAT to VDD33 regulator in UART mode. When the PHY is switched from USB mode to UART mode regulator output will automatically change to the value specified in this register when TxdEn is asserted. 00: 3.3V 01: 3.0V (default) 10: 2.75V 11: 2.5V UART RegOutput Description Note: When in USB Audio Mode the regulator will remain at 3.3V. When using this register it is recommended that the Link exit UART mode by using the RESETB pin. ChargerPullupEnDP 4 rd/w/s/c 0b Enables the RCD Pull-up resistor on the DP pin. (The pull-up is automatically enabled in UART mode) ChargerPullupEnDM 5 rd/w/s/c 0b Enables the RCD Pull-up resistor on the DM pin. (The pull-up is automatically enabled in UART mode) 7:6 rd/w/s/c 00b Controls the output voltage of the VBAT to VDD33 regulator in USB mode. When the PHY is in Synchronous Mode, Serial Mode, or Low Power Mode, the regulator output will be the value specified in this register. 00: 3.3V (default) 01: 3.0V 10: 2.75V 11: 2.5V USB RegOutput  2009 - 2015 Microchip Technology Inc. DS00001880A-page 69 USB333x 8.0 APPLICATION NOTES 8.1 Application Diagram The USB333x requires few external components as shown in the application diagrams. The USB 2.0 Specification restricts the voltage at the VBUS pin to a maximum value of 5.25V. In some applications, the voltage will exceed this limit, so the USB333x provides an integrated over voltage protection circuit. The over voltage protection circuit works with an external resistor (RVBUS) to lower the voltage at the VBUS pin. TABLE 8-1: COMPONENT VALUES IN APPLICATION DIAGRAMS Reference Designator Value Description Notes COUT See Table 4-12 Bypass capacitor to ground (