USB3450
Hi-Speed USB Host or Device PHY With UTMI+ Interface
• Internal PLL for 480MHz Hi-Speed USB operation
• Supports Hi-Speed USB and legacy USB 1.1
devices
• 55mA Unconfigured Current (typical) - ideal for
bus powered applications
• 83uA suspend current (typical) - ideal for battery
powered applications
• Full Commercial operating temperature range
from 0C to +70C
• 40 pin QFN RoHS compliant package
(6 x 6 x 0.9mm height)
Highlights
• USB-IF “Hi-Speed” certified to the Universal Serial
Bus Specification Rev. 2.0
• Interface compliant with the UTMI+ Specification,
Rev. 1.0
• Functional as a host or device PHY
• Supports HS, FS, and LS data rates
• Supports FS pre-amble for FS hubs with a LS
device attached (UTMI+ Level 3)
• Supports HS SOF and LS keep alive pulse
• Low Latency Hi-Speed Receiver (43 Hi-Speed
clocks Max)
• Internal 1.8 volt regulators allow operation from a
single 3.3 volt supply
• Internal short circuit protection of DP and DM
lines to VBUS or ground
• Integrated 24MHz Crystal Oscillator supports
either crystal operation or 24MHz external clock
input
Functional Overview
The USB3450 is a highly integrated USB transceiver
system. It contains a complete Hi-Speed PHY with the
UTMI+ industry standard interface to support fast time
to market for a USB controller. The USB3450 is composed of the functional blocks shown below.
VDD3.3
Internal
Regulator &
POR
24 MHz
XTAL
XO
m
XI
VDDA1.8
VDD1.8
USB3450 Block Diagram
XTAL &
PLL
Rpu_dm
HS XCVR
Rpd_dm
UTMI+
Digital
Rpu_dp
XCVRSEL[1:0]
TERMSEL
TXREADY
SUSPENDN
TXVALID
RESET
RXACTIVE
OPMODE[1:0]
CLKOUT
LINESTATE[1:0]
HOSTDISC
DATA[7:0]
HOST
RXERROR
Rpd_dp
VDD3.3
DP
DM
Mini-AB
USB
Connector
Resistors
FS/LS
XCVR
Bias
Gen.
RBIAS
USB3450
2005 - 2016 Microchip Technology Inc.
DS00002105A-page 1
USB3450
TO OUR VALUED CUSTOMERS
It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip
products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and
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If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via
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http://www.microchip.com
You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page.
The last character of the literature number is the version number, (e.g., DS30000000A is version A of document DS30000000).
Errata
An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the
revision of silicon and revision of document to which it applies.
To determine if an errata sheet exists for a particular device, please check with one of the following:
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When contacting a sales office, please specify which device, revision of silicon and data sheet (include -literature number) you are
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DS00002105A-page 2
2005 - 2016 Microchip Technology Inc.
USB3450
Table of Contents
1.0 General Description ........................................................................................................................................................................ 4
2.0 Pin Configuration and Pin Definitions ............................................................................................................................................. 6
3.0 Limiting Values .............................................................................................................................................................................. 10
4.0 Electrical Characteristics ............................................................................................................................................................... 11
5.0 Detailed Functional Overview ....................................................................................................................................................... 14
6.0 Application Notes .......................................................................................................................................................................... 21
7.0 Package Outline ............................................................................................................................................................................ 33
Appendix A: Data Sheet Revision History ........................................................................................................................................... 35
The Microchip Web Site ...................................................................................................................................................................... 36
Customer Change Notification Service ............................................................................................................................................... 36
Customer Support ............................................................................................................................................................................... 36
Product Identification System ............................................................................................................................................................. 37
2005 - 2016 Microchip Technology Inc.
DS00002105A-page 3
USB3450
1.0
GENERAL DESCRIPTION
The USB3450 is a stand-alone Hi-Speed USB Physical Layer Transceiver (PHY). The USB3450 uses a UTMI+ interface
to connect to an SOC or ASIC or FPGA. Microchip’s advanced proprietary technology minimizes power dissipation,
resulting in maximum battery life for portable applications. The USB3450 is a flexible solution for adding USB to new
designs without integrating the analog PHY block.
FIGURE 1-1:
BASIC UTMI+ USB DEVICE BLOCK DIAGRAM
SOC/FPGA/ASIC
USB3450
Including Device Controller
V BUS
Hi-Speed
USB App.
UTMI+
Link
UTMI+
Interface
UTMI+
Digital
Logic
HiSpeed
Analog
ID
DM
DP
USB
Connector
(Standard
or Mini)
The USB3450 provides a fully compliant Hi-Speed interface, and supports Hi-Speed (HS), Full-Speed (FS), and LowSpeed (LS) USB. The USB3450 supports all levels of the UTMI+ specification as shown in Figure 1-2.
FIGURE 1-2:
UTMI+ LEVEL 3 SUPPORT
ADDED FEATURES
UTMI+ Level 3
Hi-Speed Peripheral, host controllers, Onthe-Go devices
(HS, FS, LS, preamble packet)
UTMI+ Level 2
Hi-Speed Peripheral, host controllers, Onthe-Go devices
(HS, FS, and LS but no preamble packet)
UTMI+ Level 1
Hi-Speed Peripheral, host controllers,
and On-the-Go devices
(HS and FS Only)
UTMI+ Level 0
Hi-Speed Peripherals Only
DS00002105A-page 4
USB3450
USB3500
USB3280
USB3250
2005 - 2016 Microchip Technology Inc.
USB3450
1.1
Applications
The USB3450 is targeted for any application where a high speed USB connection is desired.
The USB3450 is well suited for:
•
•
•
•
•
•
•
•
•
Cell Phones
MP3 Players
Scanners
Set Top Boxes
Printers
External Hard Drives
Still and Video Cameras
Portable Media Players
Entertainment Devices
1.2
Reference Documents
• Universal Serial Bus Specification, Revision 2.0, April 27, 2000
• Hi-Speed Transceiver Macrocell Interface (UTMI) Specification, Version 1.02, May 27, 2000
• UTMI+ Specification, Revision 1.0, February 2, 2004
2005 - 2016 Microchip Technology Inc.
DS00002105A-page 5
USB3450
2.0
PIN CONFIGURATION AND PIN DEFINITIONS
The USB3450 is offered in a 40 pin QFN package. The pin definitions and locations are documented below.
USB3450 Pin Locations
RBIAS
VDD3.3
VDD3.3
VDDA1.8
XI
XO
VDD1.8
VDD3.3
RXERROR
HOST
39
38
37
36
35
34
33
32
31
USB3450 PINOUT - TOP VIEW
40
FIGURE 2-1:
XCVRSEL0
1
30
RXVALID
TERMSEL
2
29
DATA[0]
TXREADY
3
28
DATA[1]
SUSPENDN
4
27
DATA[2]
TXVALID
5
26
DATA[3]
RESET
6
25
DATA[4]
VDD3.3
7
24
DATA[5]
DP
8
23
DATA[6]
DM
9
22
DATA[7]
NC
10
21
HOSTDISC
USB3450
Hi-Speed USB
UTMI+ PHY
40 Pin QFN
11
12
13
14
15
16
17
18
19
20
XCVRSEL1
RXACTIVE
OPMODE[1]
OPMODE[0]
CLKOUT
LINESTATE[1]
LINESTATE[0]
VDD1.8
VDD3.3
GND FLAG
VDD3.3
2.1
The flag of the QFN package must be connected to ground.
DS00002105A-page 6
2005 - 2016 Microchip Technology Inc.
USB3450
2.2
Pin Definitions
TABLE 2-1:
USB3450 PIN DEFINITIONS
Pin
Name
Direction,
Type
Active
Level
1
XCVRSEL[0]
Input
N/A
Transceiver Select. These signals select between the
FS and HS transceivers:
Transceiver select.
00: HS
01: FS
10: LS
11: LS data, FS rise/fall times
2
TERMSEL
Input
N/A
Termination Select. This signal selects between the
FS and HS terminations:
0: HS termination enabled
1: FS termination enabled
3
TXREADY
Output
High
Transmit Data Ready. If TXVALID is asserted, the Link
must always have data available for clocking into the
TX Holding Register on the rising edge of CLKOUT.
TXREADY is an acknowledgment to the Link that the
transceiver has clocked the data from the bus and is
ready for the next transfer on the bus. If TXVALID is
negated, TXREADY can be ignored by the Link.
4
SUSPENDN
Input
Low
Suspend. Places the transceiver in a mode that draws
minimal power from supplies. In host mode, RPU is
removed during suspend. In device mode, RPD is
controlled by TERMSEL. In suspend mode the clocks
are off.
0: PHY in suspend mode
1: PHY in normal operation
5
TXVALID
Input
High
Transmit Valid. Indicates that the DATA bus is valid for
transmit. The assertion of TXVALID initiates the
transmission of SYNC on the USB bus. The negation
of TXVALID initiates EOP on the USB.
Description
Control inputs (OPMODE[1:0],
TERMSEL,XCVERSEL) must not be changed on the
de-assertion or assertion of TXVALID.
6
RESET
Input
High
Reset. Reset all state machines. After coming out of
reset, must wait 5 rising edges of clock before
asserting TXValid for transmit.
Assertion of Reset: May be asynchronous to CLKOUT
De-assertion of Reset: Must be synchronous to
CLKOUT
7
VDD3.3
N/A
N/A
3.3V PHY Supply. Provides power for Hi-Speed
Transceiver, UTMI+ Digital, Digital I/O, and
Regulators.
8
DP
I/O,
Analog
N/A
D+ pin of the USB cable.
9
DM
I/O,
Analog
N/A
D- pin of the USB cable.
10
NC
N/A
N/A
No Connect.
11
VDD3.3
N/A
N/A
3.3V PHY Supply.
12
XCVRSEL[1]
Input
N/A
Transceiver Select. These signals select between the
FS and HS transceivers:
Transceiver select.
00: HS
01: FS
10: LS
11: LS data, FS rise/fall times
13
RXACTIVE
Output
High
Receive Active. Indicates that the receive state
machine has detected Start of Packet and is active.
2005 - 2016 Microchip Technology Inc.
DS00002105A-page 7
USB3450
TABLE 2-1:
USB3450 PIN DEFINITIONS (CONTINUED)
Pin
Name
Direction,
Type
Active
Level
14
OPMODE[1]
Input
N/A
15
OPMODE[0]
Input
N/A
16
CLKOUT
Output,
CMOS
N/A
60MHz reference clock output. All UTMI+ signals are
driven synchronous to this clock.
17
LINESTATE[1]
Output
N/A
18
LINESTATE[0]
Output
N/A
Line State. These signals reflect the current state of
the USB data bus in FS mode. Bit [0] reflects the state
of DP and bit [1] reflects the state of DM. When the
device is suspended or resuming from a suspended
state, the signals are combinatorial. Otherwise, the
signals are synchronized to CLKOUT.
[1] [0] Description
0
0
0: SEO
0
1
1: J State
1
0
2: K State
1
1
3: SE1
19
VDD1.8
N/A
N/A
1.8V regulator output for digital circuitry on chip. Place
a 0.1uF capacitor near this pin and connect the
capacitor from this pin to ground. Connect pin 19 to
pin 34.
20
VDD3.3
N/A
N/A
3.3V PHY Supply. Provides power for Hi-Speed
Transceiver, UTMI+ Digital, Digital I/O, and
Regulators.
21
HOSTDISC
Output
High
Host Disconnect. Indicates that a downstream device
has been disconnected from this host PHY when
operating in HS host mode. Automatically reset to 0b
when Low Power Mode is entered.
22
DATA[7]
I/O,
CMOS,
Pull-low
N/A
8-bit bi-directional data bus. Data[7] is the MSB and
Data[0] is the LSB.
23
DATA[6]
I/O,
CMOS,
Pull-low
N/A
24
DATA[5]
I/O,
CMOS,
Pull-low
N/A
25
DATA[4]
I/O,
CMOS,
Pull-low
N/A
26
DATA[3]
I/O,
CMOS,
Pull-low
N/A
27
DATA[2]
I/O,
CMOS,
Pull-low
N/A
28
DATA[1]
I/O,
CMOS,
Pull-low
N/A
29
DATA[0]
I/O,
CMOS,
Pull-low
N/A
DS00002105A-page 8
Description
Operational Mode. These signals select between the
various operational modes:
[1] [0] Description
0
0
0: Normal Operation
0
1
1: Non-driving (all terminations removed)
1
0
2: Disable bit stuffing and NRZI encoding
1
1
3: Reserved
2005 - 2016 Microchip Technology Inc.
USB3450
TABLE 2-1:
USB3450 PIN DEFINITIONS (CONTINUED)
Pin
Name
Direction,
Type
Active
Level
30
RXVALID
Output
High
Receive Data Valid. Indicates that the DATA bus has
received valid data. The Receive Data Holding
Register is full and ready to be unloaded. The Link is
expected to register the DATA bus on the rising edge
of CLKOUT.
31
HOST
Input
N/A
Host Pull-down Select. This signal enables the 15k
Ohm pull-down resistor on the DM line.
0: Pull-down resistor not connected to DM
1: Pull-down resistor connected to DM
32
RXERROR
Output
High
Receive Error. This output is clocked with the same
timing as the receive DATA lines and can occur at
anytime during a transfer.
0: Indicates no error.
1: Indicates a receive error has been detected.
33
VDD3.3
N/A
N/A
3.3V PHY Supply. Provides power for Hi-Speed
Transceiver, UTMI+ Digital, Digital I/O, and
Regulators.
34
VDD1.8
N/A
N/A
1.8V regulator output for digital circuitry on chip. Place
a 4.7uF low ESR capacitor near this pin and connect
the capacitor from this pin to ground. Connect pin 34
to pin 19. See Section 5.6.1, "Internal Regulators".
35
XO
Output,
Analog
N/A
Crystal pin. If using an external clock on XI this pin
should be floated.
36
XI
Input,
Analog
N/A
Crystal pin. A 24MHz crystal is supported. The crystal
is placed across XI and XO. An external 24MHz clock
source may be driven into XI in place of a crystal.
37
VDDA1.8
N/A
N/A
1.8V regulator output for analog circuitry on chip.
Place a 0.1uF capacitor near this pin and connect the
capacitor from this pin to ground. In parallel, place a
4.7uF low ESR capacitor near this pin and connect the
capacitor from this pin to ground. See Section 5.6.1,
"Internal Regulators".
38
VDD3.3
N/A
N/A
3.3V PHY Supply. Provides power for Hi-Speed
Transceiver, UTMI+ Digital, Digital I/O, and
Regulators.
39
VDD3.3
N/A
N/A
3.3V PHY Supply. Should be connected directly to pin
39.
40
RBIAS
Analog,
CMOS
N/A
External 1% bias resistor. Requires a 12KΩ resistor to
ground.
GND FLAG
Ground
N/A
Ground. The flag must be connected to the ground
plane.
2005 - 2016 Microchip Technology Inc.
Description
DS00002105A-page 9
USB3450
3.0
LIMITING VALUES
TABLE 3-1:
MAXIMUM RATINGS
Parameter
Symbol
Conditions
MIN
TYP
MAX
Units
Maximum VBUS, ID, DP,
and DM voltage to GND
VMAX_5V
-0.5
+5.5
V
Maximum VDD1.8 and
VDDA1.8 voltage to
Ground
VMAX_1.8V
-0.5
2.5
V
Maximum 3.3V supply
voltage to Ground
VMAX_3.3V
-0.5
4.0
V
Maximum I/O voltage to
Ground
VMAX_IN
-0.5
4.0
V
Operating Temperature
TMAX_OP
0
70
C
Storage Temperature
TMAX_STG
-55
150
C
Note:
Stresses above those listed could cause damage to the device. This is a stress rating only and functional
operation of the device at any other condition above those indicated in the operation sections of this specification is not implied. When powering this device from laboratory or system power supplies, it is important
that the Absolute Maximum Ratings not be exceeded or device failure can result. Some power supplies
exhibit voltage spikes on their outputs when the AC power is switched on or off. In addition, voltage transients on the AC power line may appear on the DC output. If this possibility exists, it is suggested that a
clamp circuit be used.
TABLE 3-2:
RECOMMENDED OPERATING CONDITIONS
Parameter
Symbol
Conditions
MIN
TYP
MAX
Units
3.3
3.6
V
3.3V Supply Voltage
VDD3.3
3.0
Input Voltage on Digital Pins
VI
0.0
VDD3.3
V
Input Voltage on Analog I/O
Pins (DP, DM)
VI(I/O)
0.0
VDD3.3
V
Ambient Temperature
TA
0
+70
oC
TABLE 3-3:
RECOMMENDED EXTERNAL CLOCK CONDITIONS
Parameter
Symbol
Conditions
System Clock Frequency
XI driven by the external clock;
and no connection at XO
System Clock Duty Cycle
XI driven by the external clock;
and no connection at XO
DS00002105A-page 10
MIN
TYP
MAX
MHz
24
(±100ppm)
45
50
Units
55
%
2005 - 2016 Microchip Technology Inc.
USB3450
4.0
ELECTRICAL CHARACTERISTICS
ELECTRICAL CHARACTERISTICS: SUPPLY PINS (Note 4-1)
TABLE 4-1:
Parameter
Symbol
Unconfigured Current
IAVG(UCFG)
Device Unconfigured
FS Idle Current
IAVG(FS)
FS idle not data transfer
55
mA
FS Transmit Current
IAVG(FSTX)
FS current during data
transmit
60.5
mA
FS Receive Current
IAVG(FSRX)
FS current during data
receive
57.5
mA
HS Idle Current
IAVG(HS)
FS idle not data transfer
60.6
mA
HS Transmit Current
IAVG(HSTX)
FS current during data
transmit
62.4
mA
HS Receive Current
IAVG(HSRX)
FS current during data
receive
61.5
mA
Low Power Mode
IDD(LPM)
VBUS 15kΩ pull-down and
83
1.5kΩ pull-up resistor
currents not included.
VDD3.3 = 3.0 to 3.6V; VSS = 0V; TA = 0C to +70C; unless otherwise specified.
uA
Note 4-1
TABLE 4-2:
Suspend Recovery Time
Symbol
TYP
MAX
55
Conditions
MIN
Units
mA
TYP
MAX
Units
2.25
3.5
ms
TYP
MAX
Units
VSS
0.8
V
2.0
VDD3.3
V
0.4
V
TSTART
DC ELECTRICAL CHARACTERISTICS: LOGIC PINS
Parameter
Symbol
Conditions
Low-Level Input Voltage
VIL
High-Level Input Voltage
VIH
Low-Level Output Voltage
VOL
IOL = 8mA
High-Level Output Voltage
VOH
IOH = -8mA
Input Leakage Current
ILI
Pin Capacitance
Cpin
Note:
MIN
ELECTRICAL CHARACTERISTICS: CLKOUT START-UP
Parameter
TABLE 4-3:
Conditions
MIN
VDD3.3 0.4
V
±10
uA
4
pF
VDD3.3 = 3.0 to 3.6V; VSS = 0V; TA = 0C to +70C; unless otherwise specified.
2005 - 2016 Microchip Technology Inc.
DS00002105A-page 11
USB3450
TABLE 4-4:
DC ELECTRICAL CHARACTERISTICS: ANALOG I/O PINS (DP/DM)
Parameter
Symbol
Conditions
MIN
TYP
MAX
Units
FS FUNCTIONALITY
Input levels
Differential Receiver Input
Sensitivity
VDIFS
Differential Receiver
Common-Mode Voltage
VCMFS
Single-Ended Receiver Low
Level Input Voltage
VILSE
Single-Ended Receiver High
Level Input Voltage
VIHSE
Single-Ended Receiver
Hysteresis
VHYSSE
| V(DP) - V(DM) |
0.2
V
0.8
2.5
V
0.8
V
2.0
V
0.050
0.150
V
0.3
V
3.6
V
45
49.5
Ù
Output Levels
Low Level Output Voltage
VFSOL
Pull-up resistor on DP;
RL = 1.5kΩ to VDD3.3
High Level Output Voltage
VFSOH
Pull-down resistor on DP,
DM;
RL = 15kΩ to GND
2.8
ZHSDRV
Steady state drive
40.5
Termination
Driver Output Impedance for
HS and FS
Input Impedance
ZINP
TX, RPU disabled
Pull-up Resistor Impedance
ZPU
Bus Idle
0.900
1.0
1.24
1.575
MΩ
kΩ
Pull-up Resistor Impedance
ZPURX
Device Receiving
1.425
2.26
3.09
kΩ
Pull-dn Resistor Impedance
ZPD
14.25
15.0
15.75
kΩ
500
mV
100
mV
HS FUNCTIONALITY
Input levels
HS Differential Input Sensitivity VDIHS
HS Data Signaling Common
Mode Voltage Range
HS Squelch Detection
Threshold (Differential)
| V(DP) - V(DM) |
VCMHS
VHSSQ
100
-50
Squelch Threshold
Un-squelch Threshold
150
mV
mV
Output Levels
Hi-Speed Low Level
Output Voltage (DP/DM
referenced to GND)
VHSOL
45Ω load
-10
10
mV
Hi-Speed High Level
Output Voltage (DP/DM
referenced to GND)
VHSOH
45Ω load
360
440
mV
Hi-Speed IDLE Level
Output Voltage (DP/DM
referenced to GND)
VOLHS
45Ω load
-10
10
mV
Chirp-J Output Voltage
(Differential)
VCHIRPJ
HS termination resistor
disabled, pull-up resistor
connected. 45Ω load.
700
1100
mV
Chirp-K Output Voltage
(Differential)
VCHIRPK
HS termination resistor
disabled, pull-up resistor
connected. 45Ω load.
-900
-500
mV
DS00002105A-page 12
2005 - 2016 Microchip Technology Inc.
USB3450
TABLE 4-4:
DC ELECTRICAL CHARACTERISTICS: ANALOG I/O PINS (DP/DM) (CONTINUED)
Parameter
Symbol
Conditions
MIN
TYP
MAX
Units
±10
uA
10
pF
Leakage Current
OFF-State Leakage Current
ILZ
Port Capacitance
Transceiver Input Capacitance CIN
Pin to GND
5
VDD3.3 = 3.0 to 3.6V; VSS = 0V; TA = 0C to +70C; unless otherwise specified.
Note:
TABLE 4-5:
DYNAMIC CHARACTERISTICS: ANALOG I/O PINS (DP/DM)
Parameter
Symbol
Conditions
MIN
TYP
MAX
Units
FS Output Driver Timing
Rise Time
TFSR
CL = 50pF; 10 to 90% of
|VOH - VOL|
4
20
ns
Fall Time
TFFF
CL = 50pF; 10 to 90% of
|VOH - VOL|
4
20
ns
Output Signal Crossover
Voltage
VCRS
Excluding the first transition
from IDLE state
1.3
2.0
V
Differential Rise/Fall Time
Matching
FRFM
Excluding the first transition
from IDLE state
90
111.1
%
HS Output Driver Timing
Differential Rise Time
THSR
500
ps
Differential Fall Time
THSF
500
ps
Driver Waveform
Requirements
Eye pattern of Template 1
in Hi-Speed specification
Hi-Speed Mode Timing
Receiver Waveform
Requirements
Eye pattern of Template 4
in Hi-Speed specification
Data Source Jitter and
Receiver Jitter Tolerance
Eye pattern of Template 4
in Hi-Speed specification
Note:
VDD3.3 = 3.0 to 3.6V; VSS = 0V; TA = 0C to +70C; unless otherwise specified.
TABLE 4-6:
REGULATOR OUTPUT VOLTAGES
Parameter
Symbol
Condition
VDDA1.8
VDDA1.8
Normal Operation
(SUSPENDN = 1)
VDDA1.8
VDDA1.8
Low Power mode
(SUSPENDN = 0)
VDD1.8
VDD1.8
Note:
MIN
TYP
MAX
Units
1.6
1.8
2.0
V
0
1.6
1.8
V
2.0
V
VDD3.3 = 3.0 to 3.6V; VSS = 0V; TA = 0C to +70C; unless otherwise specified.
2005 - 2016 Microchip Technology Inc.
DS00002105A-page 13
USB3450
5.0
DETAILED FUNCTIONAL OVERVIEW
FIGURE 2-1: on page 5 shows the functional block diagram of the USB3450. Each of the functions is described in detail
below.
5.1
8bit Bi-Directional Data Bus Operation
The USB3450 supports an 8-bit bi-directional parallel interface.
• CLKOUT runs at 60MHz
• The 8-bit data bus (DATA[7:0]) is used for transmit when TXVALID = 1
• The 8-bit data bus (DATA[7:0]) is used for receive when TXVALID = 0
Figure 5-1 shows the relationship between CLKOUT and the transmit data transfer signals in FS mode. TXREADY is
only asserted for one CLKOUT per byte time to signal the Link that the data on the DATA lines has been read by the
PHY. The Link may hold the data on the DATA lines for the duration of the byte time. Transitions of TXVALID must meet
the defined setup and hold times relative to CLKOUT.
FIGURE 5-1:
FS CLK RELATIONSHIP TO TRANSMIT DATA AND CONTROL SIGNALS
Figure 5-2 shows the relationship between CLKOUT and the receive data control signals in FS mode. RXACTIVE
“frames” a packet, transitioning only at the beginning and end of a packet. However transitions of RXVALID may take
place any time 8 bits of data are available. Figure 5-2 also shows how RXVALID is only asserted for one CLKOUT cycle
per byte time even though the data may be presented for the full byte time. The XCVRSELECT signal determines
whether the HS or FS timing relationship is applied to the data and control signals.
FIGURE 5-2:
DS00002105A-page 14
FS CLK RELATIONSHIP TO RECEIVE DATA AND CONTROL SIGNALS
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USB3450
5.2
TX Logic
This block receives parallel data bytes placed on the DATA bus and performs the necessary transmit operations. These
operations include parallel to serial conversion, bit stuffing and NRZI encoding. Upon valid assertion of the proper TX
control lines by the Link and TX State Machine, the TX LOGIC block will synchronously shift, at either the FS or HS rate,
the data to the FS/HS TX block to be transmitted on the USB cable. Data transmit timing is shown in Figure 5-3.
FIGURE 5-3:
TRANSMIT TIMING FOR A DATA PACKET
The behavior of the Transmit State Machine is described below.
• The Link asserts TXVALID to begin a transmission.
• After the Link asserts TXVALID it can assume that the transmission has started when it detects TXREADY has
been asserted.
• The Link must assume that the USB3450 has consumed a data byte if TXREADY and TXVALID are asserted on
the rising edge of CLKOUT.
• The Link must have valid packet information (PID) asserted on the DATA bus coincident with the assertion of
TXVALID.
• TXREADY is sampled by the Link on the rising edge of CLKOUT.
• The Link negates TXVALID to complete a packet. Once negated, the transmit logic will never reassert TXREADY
until after the EOP has been generated. (TXREADY will not re-assert until TXVALD asserts again.
• The USB3450 is ready to transmit another packet immediately, however the Link must conform to the minimum
inter-packet delays identified in the Hi-Speed specification.
• Supports high speed disconnect detect through the HOSTDISC pin. In Host mode the USB3450 will sample the
disconnect comparator at the 32nd bit of the 40 bit long EOP during SOF packets.
• Supports FS pre-amble for FS hubs with a LS device.
• Supports LS keep alive by receiving the SOF PID.
• Supports Host mode resume K which ends with two low speed times of SE0 followed by 1 FS “J”.
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DS00002105A-page 15
USB3450
5.3
RX Logic
This block receives serial data from the clock recovery circuits and processes it to be transferred to the Link on the DATA
bus. The processing involved includes NRZI decoding, bit unstuffing, and serial to parallel conversion. Upon valid assertion of the proper RX control lines, the RX Logic block will provide bytes to the DATA bus as shown in the figures below.
The behavior of the receiver is described below.
FIGURE 5-4:
RECEIVE TIMING FOR DATA WITH UNSTUFFED BITS
The assertion of RESET will cause the USB3450 to deasserts RXACTIVE and RXVALID. When the RESET signal is
deasserted the Receive State Machine starts looking for a SYNC pattern on the USB. When a SYNC pattern is detected
the receiver will assert RXACTIVE. The length of the received Hi-Speed SYNC pattern varies and can be up to 32 bits
long or as short as 12 bits long when at the end of five hubs.
After valid serial data is received, the data is loaded into the RX Holding Register on the rising edge of CLKOUT and
RXVALID is asserted. The Link must clock the data off the DATA bus on the next rising edge of CLKOUT. In normal
mode (OPMODE = 00), then stuffed bits are stripped from the data stream. Each time 8 stuffed bits are accumulated
the USB3450 will negate RXVALID for one clock cycle, thus skipping a byte time.
When the EOP is detected the USB3450 will negate RXACTIVE and RXVALID. After the EOP has been stripped the
USB3450 will begin looking for the next packet.
The behavior of the USB3450 receiver is described below:
•
•
•
•
•
•
RXACTIVE and RXREADY are sampled on the rising edge of CLKOUT.
After a EOP is complete the receiver will begin looking for SYNC.
The USB3450 asserts RXACTIVE when SYNC is detected.
The USB3450 negates RXACTIVE when an EOP is detected and the elasticity buffer is empty.
When RXACTIVE is asserted, RXVALID will be asserted if the RX Holding Register is full.
RXVALID will be negated if the RX Holding Register was not loaded during the previous byte time. This will occur
if 8 stuffed bits have been accumulated.
• The Link must be ready to consume a data byte if RXACTIVE and RXVALID are asserted (RX Data state).
• Figure 5-5 shows the timing relationship between the received data (DP/DM), RXVALID, RXACTIVE, RXERROR
and DATA signals.
Note:
• Figure 5-5, Figure 5-6 and Figure 5-7 are timing examples of a HS/FS PHY when it is in HS mode. When a
HS/FS PHY is in FS Mode there are approximately 40 CLKOUT cycles every byte time. The Receive State
Machine assumes that the Link captures the data on the DATA bus if RXACTIVE and RXVALID are asserted. In
FS mode, RXVALID will only be asserted for one CLKOUT per byte time.
• In Figure 5-5, Figure 5-6 and Figure 5-7 the SYNC pattern on DP/DM is shown as one byte long. The SYNC pattern received by a device can vary in length. These figures assume that all but the last 12 bits have been consumed by the hubs between the device and the host controller.
DS00002105A-page 16
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USB3450
FIGURE 5-5:
RECEIVE TIMING FOR A HANDSHAKE PACKET (NO CRC)
FIGURE 5-6:
RECEIVE TIMING FOR SETUP PACKET
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DS00002105A-page 17
USB3450
FIGURE 5-7:
RECEIVE TIMING FOR DATA PACKET (WITH CRC-16)
The receivers connect directly to the USB cable. The block contains a separate differential receiver for HS and FS mode.
Depending on the mode, the selected receiver provides the serial data stream through the mulitplexer to the RX Logic
block. The FS mode section of the FS/HS RX block also consists of a single-ended receiver on each of the data lines
to determine the correct FS LINESTATE. For HS mode support, the FS/HS RX block contains a squelch circuit to insure
that noise is never interpreted as data.
5.4
Hi-Speed Transceiver
The Microchip Hi-Speed Transceiver consists of four blocks in the lower left corner of FIGURE 2-1: on page 5. These
four blocks are labeled HS XCVR, FS/LS XCVR, Resistors, and Bias Gen.
5.4.1
HIGH SPEED AND FULL SPEED TRANSCEIVERS
The USB3450 transceiver meets all requirements in the Hi-Speed specification.
The receivers connect directly to the USB cable. This block contains a separate differential receiver for HS and FS
mode. Depending on the mode, the selected receiver provides the serial data stream through the multiplexer to the RX
Logic block. The FS mode section of the FS/HS RX block also consists of a single-ended receiver on each of the data
lines to determine the correct FS linestate. For HS mode support, the FS/HS RX block contains a squelch circuit to
insure that noise is never interpreted as data.
The transmitters connect directly to the USB cable. The block contains a separate differential FS and HS transmitter
which receive encoded, bit stuffed, serialized data from the TX Logic block and transmit it on the USB cable.
5.4.2
TERMINATION RESISTORS
The USB3450 transceiver fully integrates all of the USB termination resistors. The USB3450 includes two 1.5kΩ pullup resistors on DP and DM and a 15kΩ pull-down resistor on both DP and DM. In addition the 45Ω high speed termination resistors are also integrated. These integrated resistors require no tuning or trimming by the Link. The state of
the resistors is determined by the operating mode of the PHY. The possible valid resistor combinations are shown in
Figure 5-8. Operation is provided in the configurations given in Table 5-8, "DP/DM termination vs. Signaling Mode".
•
•
•
•
•
RPU_DP_EN activates the 1.5kΩ DP pull-up resistor
RPU_DM_EN activates the 1.5kΩ DM pull-up resistor
RPD_DP_EN activates the 15kΩ DP pull-down resistor
RPD_DM_EN activates the 15kΩ DM pull-down resistor
HSTERM_EN activates the 45Ω DP and DM high speed termination resistors
DS00002105A-page 18
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USB3450
FIGURE 5-8:
DP/DM TERMINATION VS. SIGNALING MODE
Xb
0b
0b
0b
0b
0b
00b
1b
0b
0b
1b
1b
0b
00b
0b
10b
1b
0b
0b
1b
1b
1b
HSTERM_EN
01b
0b
RPD_DM_EN
Xb
01b
RPD_DP_EN
HOST
XXb
Power-up or Vbus < VSESSEND
RPU_DM_EN
OPMODE[1:0]
Tri-State Drivers
Signaling Mode
RPU_DP_EN
TERMSEL
Resistor Settings
XCVRSEL[1:0]
UTMI+ Interface Settings
General Settings
Host Settings
Host Chirp
Host Hi-Speed
00b
0b
00b
1b
0b
0b
1b
1b
1b
Host Full Speed
X1b
1b
00b
1b
0b
0b
1b
1b
0b
Host HS/FS Suspend
01b
1b
00b
1b
0b
0b
1b
1b
0b
Host HS/FS Resume
01b
1b
10b
1b
0b
0b
1b
1b
0b
Host low Speed
10b
1b
00b
1b
0b
0b
1b
1b
0b
Host LS Suspend
10b
1b
00b
1b
0b
0b
1b
1b
0b
Host LS Resume
10b
1b
10b
1b
0b
0b
1b
1b
0b
Host Test J/Test_K
00b
0b
10b
1b
0b
0b
1b
1b
1b
Peripheral Chirp
00b
1b
10b
0b
1b
0b
0b
0b
0b
Peripheral HS
00b
0b
00b
0b
0b
0b
0b
0b
1b
Peripheral FS
01b
1b
00b
0b
1b
0b
0b
0b
0b
Peripheral Settings
Peripheral HS/FS Suspend
01b
1b
00b
0b
1b
0b
0b
0b
0b
Peripheral HS/FS Resume
01b
1b
10b
0b
1b
0b
0b
0b
0b
Peripheral LS
10b
1b
00b
0b
0b
1b
0b
0b
0b
Peripheral LS Suspend
10b
1b
00b
0b
0b
1b
0b
0b
0b
Peripheral LS Resume
10b
1b
10b
0b
0b
1b
0b
0b
0b
Peripheral Test J/Test K
00b
0b
10b
0b
0b
0b
0b
0b
1b
5.4.3
BIAS GENERATOR
This block consists of an internal bandgap reference circuit used for generating the high speed driver currents and the
biasing of the analog circuits. This block requires an external 12K, 1% tolerance, external reference resistor connected
from RBIAS to ground.
5.5
Crystal Oscillator and PLL
The USB3450 uses an internal crystal driver and PLL sub-system to provide a clean 480MHz reference clock that is
used by the PHY during both transmit and receive. The USB3450 requires a clean 24MHz crystal or clock as a frequency
reference. If the 24MHz reference is noisy or off frequency the PHY may not operate correctly.
The USB3450 can use either a crystal or an external clock oscillator for the 24MHz reference. The crystal is connected
to the XI and XO pins as shown in the application diagram, Figure 6-9. If a clock oscillator is used the clock should be
connected to the XI input and the XO pin left floating. When an external clock is used the XI pin is designed to be driven
with a 0 to 3.3 volt signal. When using an external clock the user needs to take care to ensure the external clock source
is clean enough to not degrade the high speed eye performance.
Once, the 480MHz PLL has locked to the correct frequency it will drive the CLKOUT pin with a 60MHz clock. The
USB3450 will start the clock within the time specified in Table 4-2.
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DS00002105A-page 19
USB3450
5.6
Internal Regulators and POR
The USB3450 includes an integrated set of built in power management functions. These power management features
include a POR generation and allow the USB3450 to be powered from a single 3.3 volt power supply. This reduces the
bill of materials and simplifies product design.
5.6.1
INTERNAL REGULATORS
The USB3450 has two internal regulators that create two 1.8V outputs (labeled VDD1.8 and VDDA1.8) from the 3.3volt
power supply input (VDD3.3). Each regulator requires an external 4.7uF +/-20% low ESR bypass capacitor to ensure
stability. X5R or X7R ceramic capacitors are recommended since they exhibit an ESR lower that 0.1ohm at frequencies
greater than 10kHz.
The specific capacitor recommendations for each pin are detailed in Table 2-1, “USB3450 Pin Definitions,” on page 7,
and shown in FIGURE 6-9: USB3450 Application Diagram (Top View) on page 32.
Note:
5.6.2
The USB3450 regulators are designed to generate a 1.8 volt supply for the USB3450 only. Using the regulators to provide current for other circuits is not recommended and Microchip does not ensure USB performance or regulator stability.
POWER ON RESET (POR)
The USB3450 provides an internal POR circuit that generates a reset pulse once the PHY supplies are stable. The
UTMI+ Digital can be reset at any time with the RESET pin.
DS00002105A-page 20
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USB3450
6.0
APPLICATION NOTES
The following sections consist of select functional explanations to aid in implementing the USB3450 into a system. For
complete description and specifications consult the Hi-Speed Transceiver Macrocell Interface Specification and Universal Serial Bus Specification Revision 2.0.
6.1
Linestate
The voltage thresholds that the LINESTATE[1:0] signals use to reflect the state of DP and DM depend on the state of
XCVRSELECT. LINESTATE[1:0] uses HS thresholds when the HS transceiver is enabled (XCVRSELECT = 0) and FS
thresholds when the FS transceiver is enabled (XCVRSELECT = 1). There is not a concept of variable single-ended
thresholds in the Hi-Speed specification for HS mode.
The HS receiver is used to detect Chirp J or K, where the output of the HS receiver is always qualified with the Squelch
signal. If squelched, the output of the HS receiver is ignored. In the USB3450, as an alternative to using variable thresholds for the single-ended receivers, the following approach is used.
TABLE 6-1:
LINESTATE STATES
State of DP/DM Lines
Linestate[1:0]
Full Speed
XCVRSELECT =1
TERMSELECT=1
High Speed
XCVRSELECT =0
TERMSELECT=0
Chirp Mode
XCVRSELECT =0
TERMSELECT=1
LS[1]
LS[0]
0
0
SE0
Squelch
Squelch
0
1
J
Squelch
Squelch &
HS Diff. Receiver Output
1
0
K
Invalid
Squelch &
HS Diff. Receiver Output
1
1
SE1
Invalid
Invalid
In HS mode, 3ms of no USB activity (IDLE state) signals a reset. The Link monitors LINESTATE[1:0] for the IDLE state.
To minimize transitions on LINESTATE[1:0] while in HS mode, the presence of Squelch is used to force LINESTATE[1:0]
to a J state.
6.2
OPMODES
The OPMODE[1:0] pins allow control of the operating modes.
TABLE 6-2:
OPERATIONAL MODES
Mode[1:0]
State#
State Name
Description
00
0
Normal Operation
Transceiver operates with normal USB data encoding and
decoding
01
1
Non-Driving
Allows the transceiver logic to support a soft disconnect feature
which tri-states both the HS and FS transmitters, and removes
any termination from the USB making it appear to an upstream
port that the device has been disconnected from the bus
10
2
Disable Bit Stuffing
and NRZI encoding
Disables bitstuffing and NRZI encoding logic so that 1's loaded
from the DATA bus become 'J's on the DP/DM and 0's become
'K's
11
3
Reserved
N/A
The OPMODE[1:0] signals are normally changed only when the transmitter and the receiver are quiescent, i.e. when
entering a test mode or for a device initiated resume.
When using OPMODE[1:0] = 10 the SYNC and EOP patterns are not transmitted.
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DS00002105A-page 21
USB3450
The only exception to this is when OPMODE[1:0] is set to state 2 while TXVALID has been asserted (the transceiver is
transmitting a packet), in order to flag a transmission error. In this case, the USB3450 has already transmitted the SYNC
pattern so upon negation of TXVALID the EOP must also be transmitted to properly terminate the packet. Changing the
OPMODE[1:0] signals under all other conditions, while the transceiver is transmitting or receiving data will generate
undefined results.
6.3
Test Mode Support
TABLE 6-3:
HI-SPEED TEST MODES
USB3450 Setup
Hi-Speed Test Modes
6.4
Operational Mode
Link Transmitted Data
XCVRSELECT &
TERMSELECT
SE0_NAK
State 0
No transmit
HS
J
State 2
All '1's
HS
K
State 2
All '0's
HS
Test_Packet
State 0
Test Packet data
HS
SE0 Handling
For FS operation, IDLE is a J state on the bus. SE0 is used as part of the EOP or to indicate reset. When asserted in
an EOP, SE0 is never asserted for more than 2 bit times. The assertion of SE0 for more than 2.5us is interpreted as a
reset by the device operating in FS mode.
For HS operation, IDLE is a SE0 state on the bus. SE0 is also used to reset a HS device. A HS device cannot use the
2.5us assertion of SE0 (as defined for FS operation) to indicate reset since the bus is often in this state between packets.
If no bus activity (IDLE) is detected for more than 3ms, a HS device must determine whether the downstream facing
port is signaling a suspend or a reset. The following section details how this determination is made. If a reset is signaled,
the HS device will then initiate the HS Detection Handshake protocol.
6.5
Reset Detection
If a device in HS mode detects bus inactivity for more than 3ms (T1), it reverts to FS mode. This enables the FS pull-up
on the DP line in an attempt to assert a continuous FS J state on the bus. The Link must then check LINESTATE for the
SE0 condition. If SE0 is asserted at time T2, then the upstream port is forcing the reset state to the device (i.e., a Driven
SE0). The device will then initiate the HS detection handshake protocol.
FIGURE 6-1:
DS00002105A-page 22
RESET TIMING BEHAVIOR (HS MODE)
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USB3450
TABLE 6-4:
RESET TIMING VALUES (HS MODE)
Timing Parameter
Description
HS Reset T0
Bus activity ceases, signaling either a reset or
a SUSPEND.
0 (reference)
T1
Earliest time at which the device may place
itself in FS mode after bus activity stops.
HS Reset T0 + 3. 0ms < T1 < HS Reset T0 +
3.125ms
T2
Link samples LINESTATE. If LINESTATE =
T1 + 100µs < T2 <
SE0, then the SE0 on the bus is due to a Reset T1 + 875µs
state. The device now enters the HS Detection
Handshake protocol.
6.6
Value
Suspend Detection
If a HS device detects SE0 asserted on the bus for more than 3ms (T1), it reverts to FS mode. This enables the FS pullup on the DP line in an attempt to assert a continuous FS J state on the bus. The Link must then check LINESTATE for
the J condition. If J is asserted at time T2, then the upstream port is asserting a soft SE0 and the USB is in a J state
indicating a suspend condition. By time T4 the device must be fully suspended.
FIGURE 6-2:
TABLE 6-5:
SUSPEND TIMING BEHAVIOR (HS MODE)
SUSPEND TIMING VALUES (HS MODE)
Timing Parameter
Description
HS Reset T0
End of last bus activity, signaling either a reset
or a SUSPEND.
Value
0 (reference)
T1
The time at which the device must place itself in HS Reset T0 + 3. 0ms < T1 < HS Reset T0
FS mode after bus activity stops.
+ 3.125ms
T2
Link samples LINESTATE. If LINESTATE = 'J',
then the initial SE0 on the bus (T0 - T1) had
been due to a Suspend state and the Link
remains in HS mode.
T1 + 100 µs < T2 <
T1 + 875µs
T3
The earliest time where a device can issue
Resume signaling.
HS Reset T0 + 5ms
T4
The latest time that a device must actually be
suspended, drawing no more than the suspend
current from the bus.
HS Reset T0 + 10ms
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DS00002105A-page 23
USB3450
6.7
HS Detection Handshake
The High Speed Detection Handshake process is entered from one of three states: suspend, active FS or active HS.
The downstream facing port asserting an SE0 state on the bus initiates the HS Detection Handshake. Depending on
the initial state, an SE0 condition can be asserted from 0 to 4 ms before initiating the HS Detection Handshake. These
states are described in the Hi-Speed specification.
There are three ways in which a device may enter the HS Handshake Detection process:
1.
2.
3.
If the device is suspended and it detects an SE0 state on the bus it may immediately enter the HS handshake
detection process.
If the device is in FS mode and an SE0 state is detected for more than 2.5µs. it may enter the HS handshake
detection process.
If the device is in HS mode and an SE0 state is detected for more than 3.0ms. it may enter the HS handshake
detection process. In HS mode, a device must first determine whether the SE0 state is signaling a suspend or a
reset condition. To do this the device reverts to FS mode by placing XCVRSELECT and TERMSELECT into FS
mode. The device must not wait more than 3.125ms before the reversion to FS mode. After reverting to FS mode,
no less than 100µs and no more than 875µs later the Link must check the LINESTATE signals. If a J state is
detected the device will enter a suspend state. If an SE0 state is detected, then the device will enter the HS Handshake detection process.
In each case, the assertion of the SE0 state on the bus initiates the reset. The minimum reset interval is 10ms. Depending on the previous mode that the bus was in, the delay between the initial assertion of the SE0 state and entering the
HS Handshake detection can be from 0 to 4ms.
This transceiver design pushes as much of the responsibility for timing events on to the Link as possible, and the Link
requires a stable CLKOUT signal to perform accurate timing. In case 2 and 3 above, CLKOUT has been running and is
stable, however in case 1 the USB3450 is reset from a suspend state, and the internal oscillator and clocks of the transceiver are assumed to be powered down. A device has up to 6ms after the release of SUSPENDN to assert a minimum
of a 1ms Chirp K.
6.8
HS Detection Handshake – FS Downstream Facing Port
Upon entering the HS Detection process (T0) XCVRSELECT and TERMSELECT are in FS mode. The DP pull-up is
asserted and the HS terminations are disabled. The Link then sets OPMODE to Disable Bit Stuffing and NRZI encoding,
XCVRSELECT to HS mode, and begins the transmission of all 0's data, which asserts a HS K (chirp) on the bus (T1).
The device chirp must last at least 1.0ms, and must end no later than 7.0ms after HS Reset T0. At time T1 the device
begins listening for a chirp sequence from the host port.
If the downstream facing port is not HS capable, then the HS K asserted by the device is ignored and the alternating
sequence of HS Chirp K’s and J’s is not generated. If no chirps are detected (T4) by the device, it will enter FS mode
by returning XCVRSELECT to FS mode.
DS00002105A-page 24
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USB3450
FIGURE 6-3:
TABLE 6-6:
HS DETECTION HANDSHAKE TIMING BEHAVIOR (FS MODE)
HS DETECTION HANDSHAKE TIMING VALUES (FS MODE)
Timing
Parameter
Description
Value
T0
HS Handshake begins. DP pull-up enabled, HS
terminations disabled.
0 (reference)
T1
Device enables HS Transceiver and asserts Chirp K T0 < T1 < HS Reset T0 + 6.0ms
on the bus.
T2
Device removes Chirp K from the bus. 1ms
minimum width.
T1 + 1.0 ms < T2 <
HS Reset T0 + 7.0ms
T3
Earliest time when downstream facing port may
assert Chirp KJ sequence on the bus.
T2 < T3 < T2+100µs
T4
Chirp not detected by the device. Device reverts to
FS default state and waits for end of reset.
T2 + 1.0ms < T4 <
T2 + 2.5ms
T5
Earliest time at which host port may end reset
HS Reset T0 + 10ms
Note:
• T0 may occur to 4ms after HS Reset T0.
• The Link must assert the Chirp K for 66000 CLKOUT cycles to ensure a 1ms minimum duration.
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USB3450
6.9
HS Detection Handshake – HS Downstream Facing Port
Upon entering the HS Detection process (T0) XCVRSELECT and TERMSELECT are in FS mode. The DP pull-up is
asserted and the HS terminations are disabled. The Link then sets OPMODE to Disable Bit Stuffing and NRZI encoding,
XCVRSELECT to HS mode, and begins the transmission of all 0's data, which asserts a HS K (chirp) on the bus (T1).
The device chirp must last at least 1.0ms, and must end no later than 7.0ms after HS Reset T0. At time T1 the device
begins listening for a chirp sequence from the downstream facing port. If the downstream facing port is HS capable then
it will begin generating an alternating sequence of Chirp K’s and Chirp J’s (T3) after the termination of the chirp from the
device (T2). After the device sees the valid chirp sequence Chirp K-J-K-J-K-J (T6), it will enter HS mode by setting
TERMSELECT to HS mode (T7).
Figure 6-4 provides a state diagram for Chirp K-J-K-J-K-J validation. Prior to the end of reset (T9) the device port must
terminate the sequence of Chirp K’s and Chirp J’s (T8) and assert SE0 (T8-T9). Note that the sequence of Chirp K’s
and Chirp J’s constitutes bus activity.
FIGURE 6-4:
CHIRP K-J-K-J-K-J SEQUENCE DETECTION STATE DIAGRAM
Start Chirp
K-J-K-J-K-J
detection
!K
Chirp
Invalid
K State
Chirp Count
=0
Detect K?
INC Chirp
Count
SE0
Chirp Count != 6
& !SE0
!J
Chirp Count
J State
Detect J?
INC Chirp
Count
Chirp Valid
Chirp Count != 6
& !SE0
The Chirp K-J-K-J-K-J sequence occurs too slow to propagate through the serial data path, therefore LINESTATE signal
transitions must be used by the Link to step through the Chirp K-J-K-J-K-J state diagram, where “K State” is equivalent
to LINESTATE = K State and “J State” is equivalent to LINESTATE = J State. The Link must employ a counter (Chirp
Count) to count the number of Chirp K and Chirp J states. Note that LINESTATE does not filter the bus signals so the
requirement that a bus state must be “continuously asserted for 2.5µs” must be verified by the Link sampling the LINESTATE signals.
DS00002105A-page 26
2005 - 2016 Microchip Technology Inc.
USB3450
FIGURE 6-5:
TABLE 6-7:
HS DETECTION HANDSHAKE TIMING BEHAVIOR (HS MODE)
RESET TIMING VALUES
Timing Parameter
Description
Value
T0
HS Handshake begins. DP pull-up enabled, HS
terminations disabled.
0 (reference)
T1
Device asserts Chirp K on the bus.
T0 < T1 < HS Reset T0 + 6.0ms
T2
Device removes Chirp K from the bus. 1 ms minimum T0 + 1.0ms < T2 <
width.
HS Reset T0 + 7.0ms
T3
Downstream facing port asserts Chirp K on the bus. T2 < T3 < T2+100µs
T4
Downstream facing port toggles Chirp K to Chirp J on T3 + 40µs < T4 < T3 + 60µs
the bus.
T5
Downstream facing port toggles Chirp J to Chirp K on T4 + 40µs < T5 < T4 + 60µs
the bus.
T6
Device detects downstream port chirp.
T6
T7
Chirp detected by the device. Device removes DP
pull-up and asserts HS terminations, reverts to HS
default state and waits for end of reset.
T6 < T7 < T6 + 500µs
T8
Terminate host port Chirp K-J sequence (Repeating
T4 and T5)
T9 - 500µs < T8 < T9 - 100µs
T9
The earliest time at which host port may end reset. HS Reset T0 + 10ms
The latest time, at which the device may remove the
DP pull-up and assert the HS terminations, reverts to
HS default state.
Note:
• T0 may be up to 4ms after HS Reset T0.
• The Link must use LINESTATE to detect the downstream port chirp sequence.
• Due to the assertion of the HS termination on the host port and FS termination on the device port, between T1
and T7 the signaling levels on the bus are higher than HS signaling levels and are less than FS signaling levels.
2005 - 2016 Microchip Technology Inc.
DS00002105A-page 27
USB3450
6.10
HS Detection Handshake – Suspend Timing
If reset is entered from a suspended state, the internal oscillator and clocks of the transceiver are assumed to be powered down. Figure 6-6 shows how CLKOUT is used to control the duration of the chirp generated by the device.
When reset is entered from a suspended state (J to SE0 transition reported by LINESTATE), SUSPENDN is combinatorially negated at time T0 by the Link. It takes approximately 5 milliseconds for the transceiver's oscillator to stabilize.
The device does not generate any transitions of the CLKOUT signal until it is “usable” (where “usable” is defined as
stable to within ±10% of the nominal frequency and the duty cycle accuracy 50±5%).
The first transition of CLKOUT occurs at T1. The Link then sets OPMODE to Disable Bit Stuffing and NRZI encoding,
XCVRSELECT to HS mode, and must assert a Chirp K for 66000 CLKOUT cycles to ensure a 1ms minimum duration.
If CLKOUT is 10% fast (66MHz) then Chirp K will be 1.0ms. If CLKOUT is 10% slow (54 MHz) then Chirp K will be 1.2ms.
The 5.6ms requirement for the first CLKOUT transition after SUSPENDN, ensures enough time to assert a 1ms Chirp
K and still complete before T3. Once the Chirp K is completed (T3) the Link can begin looking for host chirps and use
CLKOUT to time the process. At this time, the device follows the same protocol as in Section 6.9, "HS Detection Handshake – HS Downstream Facing Port" for completion of the High Speed Handshake.
FIGURE 6-6:
HS DETECTION HANDSHAKE TIMING BEHAVIOR FROM SUSPEND
T0
T1
T2
T3
T4
time
OPMODE 0
OPMODE 1
XCVRSELECT
TERMSELECT
SUSPENDN
TXVALID
CLK60
DP/DM
J
SE0
CLK power up time
Device Chirp K
Look for host chirps
To detect the assertion of the downstream Chirp K's and Chirp J's for 2.5us {TFILT}, the Link must see the appropriate
LINESTATE signals asserted continuously for 165 CLKOUT cycles.
DS00002105A-page 28
2005 - 2016 Microchip Technology Inc.
USB3450
TABLE 6-8:
HS DETECTION HANDSHAKE TIMING VALUES FROM SUSPEND
Timing Parameter
6.11
Description
Value
T0
While in suspend state an SE0 is detected on the USB. HS
Handshake begins. D+ pull-up enabled, HS terminations
disabled, SUSPENDN negated.
0 (HS Reset T0)
T1
First transition of CLKOUT. CLKOUT "Usable" (frequency
accurate to ±10%, duty cycle accurate to 50±5).
T0 < T1 < T0 + 5.6ms
T2
Device asserts Chirp K on the bus.
T1 < T2 < T0 + 5.8ms
T3
Device removes Chirp K from the bus. (1 ms minimum width)
and begins looking for host chirps.
T2 + 1.0 ms < T3 <
T0 + 7.0 ms
T4
CLK "Nominal" (CLKOUT is frequency accurate to ±500 ppm, T1 < T3 < T0 + 20.0ms
duty cycle accurate to 50±5).
Assertion of Resume
In this case, an event internal to the device initiates the resume process. A device with remote wake-up capability must
wait for at least 5ms after the bus is in the idle state before sending the remote wake-up resume signaling. This allows
the hubs to get into their suspend state and prepare for propagating resume signaling.
The device has 10ms where it can draw a non-suspend current before it must drive resume signaling. At the beginning
of this period the Link may negate SUSPENDN, allowing the transceiver (and its oscillator) to power up and stabilize.
Figure 6-7 illustrates the behavior of a device returning to HS mode after being suspended. At T4, a device that was
previously in FS mode would maintain TERMSELECT and XCVRSELECT high.
To generate resume signaling (FS 'K') the device is placed in the "Disable Bit Stuffing and NRZI encoding" Operational
Mode (OPMODE [1:0] = 10), TERMSELECT and XCVRSELECT must be in FS mode, TXVALID asserted, and all 0's
data is presented on the DATA bus for at least 1ms (T1 - T2).
FIGURE 6-7:
RESUME TIMING BEHAVIOR (HS MODE)
2005 - 2016 Microchip Technology Inc.
DS00002105A-page 29
USB3450
TABLE 6-9:
RESUME TIMING VALUES (HS MODE)
Timing Parameter
6.12
Description
Value
T0
Internal device event initiating the resume process 0 (reference)
T1
Device asserts FS 'K' on the bus to signal resume T0 < T1 < T0 + 10ms.
request to downstream port
T2
The device releases FS 'K' on the bus. However
by this time the 'K' state is held by downstream
port.
T1 + 1.0ms < T2 < T1 + 15ms
T3
Downstream port asserts SE0.
T1 + 20ms
T4
Latest time at which a device, which was
previously in HS mode, must restore HS mode
after bus activity stops.
T3 + 1.33µs {2 Low-speed bit times}
Detection of Resume
Resume signaling always takes place in FS mode (TERMSELECT and XCVRSELECT = FS enabled), so the behavior
for a HS device is identical to that of a FS device. The Link uses the LINESTATE signals to determine when the USB
transitions from the 'J' to the 'K' state and finally to the terminating FS EOP (SE0 for 1.25us-1.5µs.).
The resume signaling (FS 'K') will be asserted for at least 20ms. At the beginning of this period the Link may negate
SUSPENDN, allowing the transceiver (and its oscillator) to power up and stabilize.
The FS EOP condition is relatively short. Links that simply look for an SE0 condition to exit suspend mode do not necessarily give the transceiver’s clock generator enough time to stabilize. It is recommended that all Link implementations
key off the 'J' to 'K' transition for exiting suspend mode (SUSPENDN = 1). And within 1.25µs after the transition to the
SE0 state (low-speed EOP) the Link must enable normal operation, i.e. enter HS or FS mode depending on the mode
the device was in when it was suspended.
If the device was in FS mode: then the Link leaves the FS terminations enabled. After the SE0 expires, the downstream
port will assert a J state for one low-speed bit time, and the bus will enter a FS Idle state (maintained by the FS terminations).
If the device was in HS mode: then the Link must switch to the FS terminations before the SE0 expires (< 1.25µs). After
the SE0 expires, the bus will then enter a HS IDLE state (maintained by the HS terminations).
6.13
HS Device Attach
Figure 6-8 demonstrates the timing of the USB3450 control signals during a device attach event. When a HS device is
attached to an upstream port, power is asserted to the device and the device sets XCVRSELECT and TERMSELECT
to FS mode (time T1).
VBUS is the +5V power available on the USB cable. Device Reset in Figure 6-8 indicates that VBUS is within normal operational range as defined in the Hi-Speed specification. The assertion of Device Reset (T0) by the upstream port will initialize the device. By monitoring LINESTATE, the Link state machine knows to set the XCVRSELECT and
TERMSELECT signals to FS mode (T1).
The standard FS technique of using a pull-up resistor on DP to signal the attach of a FS device is employed. The Link
must then check the LINESTATE signals for SE0. If LINESTATE = SE0 is asserted at time T2 then the upstream port is
forcing the reset state to the device (i.e. Driven SE0). The device will then reset itself before initiating the HS Detection
Handshake protocol.
DS00002105A-page 30
2005 - 2016 Microchip Technology Inc.
USB3450
FIGURE 6-8:
TABLE 6-10:
DEVICE ATTACH BEHAVIOR
ATTACH AND RESET TIMING VALUES
Timing Parameter
Description
Value
T0
Vbus Valid.
T1
Maximum time from Vbus valid to when the device must T0 + 100ms < T1
signal attach.
T2
(HS Reset T0)
Debounce interval. The device now enters the HS
Detection Handshake protocol.
2005 - 2016 Microchip Technology Inc.
0 (reference)
T1 + 100ms < T2
DS00002105A-page 31
USB3450
Application Diagram
Device
1uF
10uF
OTG Device
1uF
6.5uF
DS00002105A-page 32
4.7uF
HOST
31
DATA[1]
DATA[2]
DATA[3]
DATA[4]
DATA[5]
DATA[6]
DATA[7]
HOSTDISC
20
19
DATA[0]
0.1uF
32
VDD3.3
33
VDD1.8
XO
35
XI
36
VDDA1.8
37
VDD3.3
38
34
18
RXVALID
VDD3.3
Max
VDD3.3
21
10
VDD1.8
100uF
22
LINESTATE[0]
Min
Host
24
GND FLAG
9
VDD3.3
CVBUS
25
23
11
NC
26
8
17
DM
7
16
DM
6
CLKOUT
DP
5
LINESTATE[1]
DP
27
USB3450
Hi-Speed USB
UTMI+ PHY
40 Pin QFN
15
VDD3.3
4
OPMODE[0]
ID
28
14
RESET
3
OPMODE[1]
USB
Connector
(Standard
or Mini)
TXVALID
29
13
Host Only
2
RXACTIVE
SUSPENDN
CVBUS
30
12
VBUS
1
XCVRSEL1
TXREADY
39
RBIAS
40
TERMSEL
RXERROR
CLOAD
XCVRSEL0
5 Volt
Supply
1M
CLOAD
12K
4.7uF
0.1uF
VDD3.3
3.3 Volt
Supply
24MHz
USB3450 APPLICATION DIAGRAM (TOP VIEW)
4.7uF
FIGURE 6-9:
0.1uF
6.14
25
UTMI+
Interface
to Link
2005 - 2016 Microchip Technology Inc.
USB3450
7.0
PACKAGE OUTLINE
USB3450-FZG 40 PIN QFN PACKAGE OUTLINE, 6 X 6 X 0.9 MM BODY
Note: For the most current package drawings,
see the Microchip Packaging Specification at
http://www.microchip.com/packaging
FIGURE 7-1:
2005 - 2016 Microchip Technology Inc.
DS00002105A-page 33
USB3450
USB3450-FZG 40 PIN QFN PACKAGE OUTLINE, 6 X 6 X 0.9 MM BODY
Note: For the most current package drawings,
see the Microchip Packaging Specification at
http://www.microchip.com/packaging
FIGURE 7-1:
DS00002105A-page 34
2005 - 2016 Microchip Technology Inc.
USB3450
APPENDIX A:
TABLE A-1:
DATA SHEET REVISION HISTORY
REVISION HISTORY
Revision
DS00002105A (02-19-16)
Section/Figure/Entry
Correction
Replaces previous SMSC version Rev. 0.1 (06-06-08)
2005 - 2016 Microchip Technology Inc.
DS00002105A-page 35
USB3450
THE MICROCHIP WEB SITE
Microchip provides online support via our WWW site at www.microchip.com. This web site is used as a means to make
files and information easily available to customers. Accessible by using your favorite Internet browser, the web site contains the following information:
• Product Support – Data sheets and errata, application notes and sample programs, design resources, user’s
guides and hardware support documents, latest software releases and archived software
• General Technical Support – Frequently Asked Questions (FAQ), technical support requests, online discussion
groups, Microchip consultant program member listing
• Business of Microchip – Product selector and ordering guides, latest Microchip press releases, listing of seminars and events, listings of Microchip sales offices, distributors and factory representatives
CUSTOMER CHANGE NOTIFICATION SERVICE
Microchip’s customer notification service helps keep customers current on Microchip products. Subscribers will receive
e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or
development tool of interest.
To register, access the Microchip web site at www.microchip.com. Under “Support”, click on “Customer Change Notification” and follow the registration instructions.
CUSTOMER SUPPORT
Users of Microchip products can receive assistance through several channels:
•
•
•
•
Distributor or Representative
Local Sales Office
Field Application Engineer (FAE)
Technical Support
Customers should contact their distributor, representative or field application engineer (FAE) for support. Local sales
offices are also available to help customers. A listing of sales offices and locations is included in the back of this document.
Technical support is available through the web site at: http://www.microchip.com/support
DS00002105A-page 36
2005 - 2016 Microchip Technology Inc.
USB3450
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
Example:
PART NO.
Device
-
[X]
Temperature
Range
Device:
USB3450
Temperature Range:
Blank
Package:
FZG =
=
XXX
USB3450-FZG
Commercial Temperature,
40-pin QFN RoHS Compliant Package
Tray
Package
0C to
+70C
(Commercial)
40-QFN
2005 - 2016 Microchip Technology Inc.
DS00002105A-page 37
USB3450
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
•
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE,
MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer’s risk, and the buyer agrees to defend, indemnify and hold
harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or
otherwise, under any Microchip intellectual property rights unless otherwise stated.
Trademarks
The Microchip name and logo, the Microchip logo, AnyRate, dsPIC, FlashFlex, flexPWR, Heldo, JukeBlox, KeeLoq, KeeLoq logo, Kleer,
LANCheck, LINK MD, MediaLB, MOST, MOST logo, MPLAB, OptoLyzer, PIC, PICSTART, PIC32 logo, RightTouch, SpyNIC, SST, SST
Logo, SuperFlash and UNI/O are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.
ClockWorks, The Embedded Control Solutions Company, ETHERSYNCH, Hyper Speed Control, HyperLight Load, IntelliMOS, mTouch,
Precision Edge, and QUIET-WIRE are registered trademarks of Microchip Technology Incorporated in the U.S.A.
Analog-for-the-Digital Age, Any Capacitor, AnyIn, AnyOut, BodyCom, chipKIT, chipKIT logo, CodeGuard, dsPICDEM, dsPICDEM.net,
Dynamic Average Matching, DAM, ECAN, EtherGREEN, In-Circuit Serial Programming, ICSP, Inter-Chip Connectivity, JitterBlocker,
KleerNet, KleerNet logo, MiWi, motorBench, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach,
Omniscient Code Generation, PICDEM, PICDEM.net, PICkit, PICtail, PureSilicon, RightTouch logo, REAL ICE, Ripple Blocker, Serial
Quad I/O, SQI, SuperSwitcher, SuperSwitcher II, Total Endurance, TSHARC, USBCheck, VariSense, ViewSpan, WiperLock, Wireless
DNA, and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated in the U.S.A.
Silicon Storage Technology is a registered trademark of Microchip Technology Inc. in other countries.
GestIC is a registered trademarks of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in
other countries.
All other trademarks mentioned herein are property of their respective companies.
© 2005 - 2016, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved.
ISBN: 9781522402886
QUALITY MANAGEMENT SYSTEM
CERTIFIED BY DNV
== ISO/TS 16949 ==
DS00002105A-page 38
Microchip received ISO/TS-16949:2009 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
2005 - 2016 Microchip Technology Inc.
Worldwide Sales and Service
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Technical Support:
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DS00002105A-page 39
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