USB3803
USB 2.0 High-Speed Hub Controller Optimized
for Portable Applications
Features
• Integrated USB 2.0 Compatible 3-Port Hub
• Advanced power saving features:
- 1 A Typical Standby Current
- Port goes into power saving state when no
devices are connected downstream
- Port is shut down when port is disabled
- Digital core shutdown in Bypass and Standby
Modes
• Provides USB Battery Charger Detection for:
- USB-IF Battery Charging 1.1 compliant Dedicated Charging Ports (DCP)
- USB-IF Battery Charging 1.1 compliant
Charging Downstream Port (CDP)
- Standard Downstream Port (SDP); that is,
USB host or downstream hub port
- Downstream Hub Ports Support USB-IF Battery Charging 1.1 as Charging Downstream
Port (CDP)
• Supports either Single-TT or Multi-TT configurations for Full-Speed and Low-Speed connections
(when connected to a High-Speed host)
• Bypass Switch for low power single port operation
- Battery charging detection using a PMIC
- Stereo and mono/mic audio
- USB1.1 Data
• Enhanced configuration options available through
serial I2C Slave Port
- VID/PID/DID
- String Descriptors
- Configuration options for Hub
• Internal Default configuration option when serial
I2C host is not available
• MultiTRAKTM
- Dedicated Transaction Translator per port
• PortMap
- Configurable port mapping and disable
sequencing
• PortSwap
- Configurable differential intra-pair signal
swapping
• PHYBoost
- Programmable USB transceiver drive
strength for recovering signal integrity
2014-2020 Microchip Technology Inc.
• VariSenseTM
- Programmable USB receiver sensitivity
• flexPWR® Technology
- Low current design ideal for battery powered
applications
- Internal supply switching provides low power
modes
• External 12, 19.2, 26, or 38.4 MHz clock input
• Internal 3.3V & 1.2V Voltage Regulators for single
supply operation
- External VBAT and 1.8V dual supply input
option
• Internal Short Circuit protection of USB differential
signal pins
• ±5kV HBM ESD Protection
• 25-pin WLCS (1.95mm x 1.95mm Wafer Level
Chip Scale) Package - 0.4mm ball pitch
Target Applications
The USB3803 is targeted for applications where more
than one USB port is required. As mobile devices add
more features and the systems become more complex,
it is necessary to have more than one USB port to communicate with internal and peripheral devices.
•
•
•
•
•
•
•
•
•
•
Mobile Phones
Ultra Mobile PCs
Tablet Computers
Digital Still Cameras
Digital Video Camcorders
Gaming Consoles
PDAs
Portable Media Players
GPS Personal Navigation Devices
Media Players/Viewers
DS00001691D-page 1
USB3803
TO OUR VALUED CUSTOMERS
It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip
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The last character of the literature number is the version number, (e.g., DS30000000A is version A of document DS30000000).
Errata
An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the
revision of silicon and revision of document to which it applies.
To determine if an errata sheet exists for a particular device, please check with one of the following:
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When contacting a sales office, please specify which device, revision of silicon and data sheet (include -literature number) you are
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DS00001691D-page 2
2014-2020 Microchip Technology Inc.
USB3803
Table of Contents
1.0 General Description ........................................................................................................................................................................ 4
2.0 Acronyms and Definitions ............................................................................................................................................................... 7
3.0 USB3803 Pin Definitions ................................................................................................................................................................. 8
4.0 Modes of Operation ...................................................................................................................................................................... 15
5.0 Configuration Options ................................................................................................................................................................... 21
6.0 Serial Slave Interface .................................................................................................................................................................... 40
7.0 USB Descriptors ........................................................................................................................................................................... 44
8.0 Battery Charging ........................................................................................................................................................................... 63
9.0 Integrated Power Regulators ........................................................................................................................................................ 69
10.0 Specifications .............................................................................................................................................................................. 70
11.0 Application Reference ................................................................................................................................................................. 78
12.0 Package Outlines, Tape & Reel Drawings, Package Marking .................................................................................................... 82
Appendix A: Revision History .............................................................................................................................................................. 87
The Microchip Web Site ...................................................................................................................................................................... 88
Customer Change Notification Service ............................................................................................................................................... 88
Customer Support ............................................................................................................................................................................... 88
Product Identification System ............................................................................................................................................................. 89
2014-2020 Microchip Technology Inc.
DS00001691D-page 3
USB3803
1.0
GENERAL DESCRIPTION
The USB3803 is a family of low-power, USB 2.0 hub controllers with three downstream ports. “USB3803” is a generic
term referring to the entire family, which includes the following devices:
• USB3803C
• USB3803Ci
The USB3803 is available in two temperature ranges (commercial and industrial) and is recommended for new designs.
The USB3803 device includes an integrated USB bypass switch. This device-specific feature is called out independently
throughout the document. Table 1-1 provides a summary of the feature differences between USB3803C and
USB3803Ci:
TABLE 1-1:
USB3803 FAMILY DIFFERENCES
Part Number
USB Bypass Switch
0°C to +70°C
USB3803C
X
X
USB3803Ci
X
-40°C to +85°C
X
The USB3803 can attach to an upstream port as a full-speed hub or as a full-/hi-speed hub and supports low-speed,
full-speed, and hi-speed (if operating as a hi-speed hub) downstream devices on all of the enabled downstream ports.
The USB3803 has been specifically optimized for mobile embedded applications. The pin-count has been reduced by
optimizing the USB3803 for mobile battery-powered embedded systems where power consumption, small package
size, minimal BOM, and battery charger detection capabilities are critical design requirements. Standby mode and
Bypass mode power has been minimized. Instead of a dedicated crystal, reference clock inputs are aligned to mobile
applications. Flexible integrated power regulators ease integration into battery powered devices. Automatic battery
charger detection is available on the upstream port. All required resistors on the USB ports are integrated into the hub.
This includes all series termination resistors on D+ and D– pins and all required pull-down and pull-up resistors on D+
and D– pins.
The integrated USB switch allows the USB3803 to bypass the USB Hub and directly connect the upstream and Port 3
downstream USB port for operational modes that do not require Hi-Speed media transfers. The bypass switch enables
multiple connectivity options to the USB port while preserving the high speed signal quality in USB Hub Mode.
The USB3803 integrated battery charger detection circuitry supports USB-IF 1.1 charger detection methods. These circuits are used to detect the attachment and type of a USB Charger and provide an interrupt output to the portable device
indicating that charger information is available to be read from USB3803 status registers via the serial interface.
The USB3803 includes programmable features such as:
MultiTRAKTM Technology which utilizes a dedicated Transaction Translator (TT) per port to maintain consistent fullspeed data throughput regardless of the number of active downstream connections. MultiTRAKTM outperforms conventional USB 2.0 hubs with a single TT in USB full-speed data transfers.
PortMap which provides flexible port mapping and disable sequences. The downstream ports of a USB3803 hub can
be reordered or disabled in any sequence to support multiple platform designs with minimum effort. For any port that is
disabled, the USB3803 hub controllers automatically reorder the remaining ports to match the USB host controller’s port
numbering scheme.
PortSwap which adds per-port programmability to USB differential-pair pin locations. PortSwap allows direct alignment
of USB signals (D+/D-) to connectors to avoid uneven trace length or crossing of the USB differential signals on the
PCB.
PHYBoost which provides programmable levels of Hi-Speed USB signal drive
strength in the upstream and downstream port transceivers. PHYBoost attempts to
restore USB signal integrity in a compromised system environment. The graphic on
the right shows an example of Hi-Speed USB eye diagrams before and after PHYBoost signal integrity restoration.
VariSenseTM which controls the USB receiver sensitivity enabling programmable levels of USB signal receive sensitivity. This capability allows operation in a sub-optimal system environment, such as
when a captive USB cable is used.
DS00001691D-page 4
2014-2020 Microchip Technology Inc.
USB3803
1.1
Customer Selectable Features
A default configuration is available in the USB3803 following a reset. This configuration may be sufficient for most applications. The USB3803 hub may also be configured by an external microcontroller. When using the microcontroller interface, the hub appears as an I2C slave device.
The USB3803 hub supports customer selectable features including:
Optional customer configuration via I2C
Compound devices on a port-by-port basis
Customizable vendor ID, product ID, and device ID
Configurable downstream port power-on time reported to the host
Indication of the maximum current that the hub consumes from the USB upstream port
Indication of the maximum current required for the hub controller
Configurable as a Self-Powered and Bus-Powered Hub
Custom string descriptors (up to 30 characters):
- Product string
- Manufacturer string
- Serial number string
• When available, I2C configurable options for default configuration may include:
- Downstream ports as non-removable ports
- Downstream ports as disabled ports
- USB signal drive strength
- USB receiver sensitivity
- USB differential pair pin location
•
•
•
•
•
•
•
•
2014-2020 Microchip Technology Inc.
DS00001691D-page 5
USB3803
1.1.1
BLOCK DIAGRAM
FIGURE 1-1:
USB3803 BLOCK DIAGRAM
From PMIC/SOC
BYPASS_N
RESET_N
Mode
Control
-
Upstream
VBAT
VDD_CORE_REG
VDD12_BYP
3.3V Reg
SCL INT_N
Serial
Interface
1.2V Reg
SIE
Repeater
Bypass Switch
SDA
VDD33_BYP
Upstream
PHY
Standby
Bypass
Hub Mode
To I2C Master
USB
TT #1
TT #2
Controller
TT #3
Port Controller
Routing & Port Re-Ordering Logic
Upstream Battery
Charger Detection
PHY#3
PHY#2
PHY#1
PLL
Bypass/
USB Data
Downstream
DS00001691D-page 6
USB Data
USB Data
Downstream
Downstream
REF_CLK
HUB_CONNECT
2014-2020 Microchip Technology Inc.
USB3803
2.0
ACRONYMS AND DEFINITIONS
2.1
Acronyms
EP:
Endpoint
FS:
Full-Speed
HS:
Hi-Speed
I2C:
Inter-Integrated Circuit
LS:
Low-Speed
2.2
Reference Documents
1.
2.
3.
4.
USB Engineering Change Notice dated December 29th, 2004, UNICODE UTF-16LE For String Descriptors
Universal Serial Bus Specification, Revision 2.0, Dated April 27th, 2000
Battery Charging Specification, Revision 1.1, Release Candidate 10, Dated Sept. 22, 2008
High-Speed Inter-Chip USB Electrical Specification, Version 1.0, Dated Sept. 23, 2007
2014-2020 Microchip Technology Inc.
DS00001691D-page 7
USB3803
3.0
USB3803 PIN DEFINITIONS
3.1
Pin Configuration
The illustration below shows the package diagram.
FIGURE 3-1:
USB3803 25-BALL PACKAGE
1
2
3
4
5
A
B
C
D
E
TOP VIEW
DS00001691D-page 8
2014-2020 Microchip Technology Inc.
USB3803
3.2
Signal Definitions
TABLE 3-1:
WLCSP Pin
SIGNAL DEFINITIONS
Name
Description
E2
USBUP_DP
Upstream D+ data pin of the USB Interface
E1
USBUP_DM
Upstream D- data pin of the USB Interface
Control signal to select between HUB MODE and BYPASS MODE
A5
BYPASS_N
C4
I2C_ASEL0
B4
I2C_ASEL1
A1
USBDN1_DP
USB downstream Port 1 D+ data pin
I2C Address Select Bit 0
I2C Address Select Bit 1
B1
USBDN1_DM
USB downstream Port 1 D- data pin
C2
USBDN2_DP
USB downstream Port 2 D+ data pin
D2
USBDN2_DM
USB downstream Port 2 D- data pin
C1
USBDN3_DP
USB downstream Port 3 D+ data pin
D1
USBDN3_DM
USB downstream Port 3 D- data pin
E5
SCL
D5
SDA
E3
RESET_N
I2C clock input
I2C bi-directional data pin
Active low reset signal
B5
HUB_CONNECT
C5
INT_N
Hub Connect
D4
REF_SEL1
Reference Clock Select 1 input
E4
REF_SEL0
Reference Clock Select 0 input
B3
REFCLK
Active low interrupt signal
Reference Clock input
A4
RBIAS
D3
VDD12_BYP
1.2V Regulator
A2
VDD33_BYP
3.3V Regulator
B2
VBAT
A3
VDD_CORE_REG
C3
VSS
2014-2020 Microchip Technology Inc.
Bias Resistor pin
Voltage input from the battery supply
Power supply input to 1.2V regulator for digital logic core
Ground
DS00001691D-page 9
USB3803
3.3
Pin Descriptions
This section provides a detailed description of each signal. The signals are arranged in functional groups according to
their associated interface.
The terms assertion and negation are used. This is done to avoid confusion when working with a mixture of “active low”
and “active high” signal. The term “assert” or “assertion” indicates that a signal is active, independent of whether that
level is represented by a high or low voltage. The term “negate” or “negation” indicates that a signal is inactive.
3.3.1
PIN DEFINITION
TABLE 3-2:
PIN DESCRIPTIONS
Name
Symbol
Type
Description
Upstream USB 2.0 / Bypass Interface
USB Bus Data
USBUP_DP
USBUP_DM
A-I/O
Bypass Select for Analog
Switch
BYPASS_N
I
These pins connect to the upstream USB bus data
signals (Host port or upstream hub)
Control signal to select between Hub Mode and
Bypass Mode. When asserted low, the device transitions to Bypass Mode, connects the Bypass Port to
the upstream USB Port, places Port 1 and Port 2 in
high impedance state, and places the core logic in a
reduced power state. When negated high, the device
transitions to HUB MODE and enables operation as a
USB hub.
Downstream USB 2.0 / Bypass Interface
High-Speed USB Data
&
Port Disable Strap Option
USBDN_DP[2:1]
&
USBDN_DM[2:1]
A-I/O
HS USB Data
&
Bypass Port
USBDN_DP[3]
&
USBDN_DM[3]
A-I/O
These pins connect to the downstream USB peripheral devices attached to the hub’s ports
Downstream Port Disable Strap option:
This pin is sampled at RESET_N negation to determine if the port is disabled.
Both USB data pins for the corresponding port must
be tied to VDD33_BYP to disable the associated
downstream port.
When BYPASS_N is negated high, these pins connect to the downstream USB peripheral devices
attached to the hub’s ports.
There is no downstream Port Disable Strap option on
these ports.
When BYPASS_N is asserted low, USBDN_DP[3]
and USBDN_DM[3] respectively are connected
through the analog switch to the upstream port
USBUP_DP and USBUP_DM. PortSwap setting has
no effect in Bypass Mode.
Serial Port Interface
Serial Data
SDA
I/OD
Serial Clock
SCL
I
DS00001691D-page 10
I2C Serial Data
Serial Clock (SCL)
2014-2020 Microchip Technology Inc.
USB3803
TABLE 3-2:
PIN DESCRIPTIONS (CONTINUED)
Name
Symbol
Type
Description
Interrupt
INT_N
OD
Interrupt
The function of this pin is determined by the setting in
the CFGP.INTSUSP configuration register.
When CFGP.INTSUSP = 0 (General Interrupt)
A transition from high to low identifies when one of
the interrupt enabled status registers has been
updated.
SOC must update the Serial Port Interrupt Status
Register to reset the interrupt pin high.
When CFGP.INTSUSP = 1 (Suspend Interrupt)
Indicates USB state of the hub.
‘Asserted’ low = Unconfigured or configured and in
USB Suspend
‘Negated’ high = Hub is configured, and is active (that
is, not in suspend)
The Suspend Interrupt can be used by the system to
determine whether the full current based on the USB
descriptor can be drawn on VBUS or whether a
reduced current should be drawn in accordance with
the USB specification for unconfigured or suspend
mode.
If unused, this pin must be tied to VDD33_BYP.
Serial Address Select
I2C_ASEL[1:0]
I
Address Select – the USB3803 has the ability to be
programmed with four different I2C slave addresses
as part of the configuration in order to provide flexibility. When sharing the serial bus in the system with
another part that conflicts with one of the address settings, these pins may be used to change the selection
to a non-conflicting I2C address. The customer should
tie these pins to ground or VDD33_BYP. This input is
latched during HUB.Init stage.
I2C_ASEL[1] selects between the I2C addresses
defined in registers I2CADD0 and I2CADD1.
I2C_ASEL[0] determines the LSB of the I2C address.
Misc
Reference Clock Input
REFCLK
I
Reference clock input.
Reference Clock Select
REF_SEL[1:0]
I
The reference select input must be set to correspond
to the frequency applied to the REFCLK input. The
customer should tie these pins to ground or
VDD33_BYP. This input is latched during HUB.Init
stage.
Selects the input reference clock frequency per
Table 3-4.
RESET Input
RESET_N
I
This active low signal is used by the system to reset
the chip and hold the chip in low power STANDBY
MODE.
USB Transceiver Bias
RBIAS
A-I/O
A 12.0 k (+/- 1%) resistor is attached from ground to
this pin to set the transceiver’s internal bias settings.
2014-2020 Microchip Technology Inc.
DS00001691D-page 11
USB3803
TABLE 3-2:
PIN DESCRIPTIONS (CONTINUED)
Name
Symbol
Type
Description
Hub Connect
HUB_CONNECT
I
Hub transitions to the Hub Communication Stage
when this pin is asserted high. It can be used in three
different ways:
• Tied to Ground - Hub does not transition to the
Hub Communication Stage until connect_n bit of
the SP_ILOCK register is negated.
• Tied to VDD33_BYP - Hub automatically transitions to the Hub Communication Stage regardless of the setting of the connect_n bit and
without pausing for the SOC to reference status
registers.
• Transition from low to high - Hub transitions to
the Hub Communication Stage after this pin transitions from low to high. HUB_CONNECT should
never be driven high when USB3803 is in
Standby mode.
Power
1.2V VDD Power
VDD12_BYP
Power
1.2V Regulator. A 1.0 F ( VDD33 > 2.8V
—
1.2
—
V
Regulator Capacitor
CBYP12
—
1.0
—
—
F
Capacitor ESR
CESR12
—
—
—
1
Ω
10.11 ESD and Latch-Up Performance
TABLE 10-13: ESD AND LATCH-UP PERFORMANCE
Parameter
Conditions
Min
Typ
Max
Units
Comments
Human Body Model
—
—
±5
kV
Device
System
EN/IEC 61000-4-2 Contact Discharge
—
—
±15
kV
Third party system
test
System
EN/IEC 61000-4-2 Air-gap Discharge
—
—
±15
kV
Third party system
test
—
150
—
mA
—
ESD Performance
Latch-Up Performance
All Pins
EIA/JESD 78, Class II
10.12 ESD Performance
The USB3803 is protected from ESD strikes. By eliminating the requirement for external ESD protection devices, board
space is conserved, and the board manufacturer is enabled to reduce cost. The advanced ESD structures integrated
into the USB3803 protect the device whether or not it is powered up.
10.12.1
HUMAN BODY MODEL (HBM) PERFORMANCE
HBM testing verifies the ability to withstand the ESD strikes like those that occur during handling and manufacturing,
and is done without power applied to the IC. To pass the test, the device must have no change in operation or performance due to the event. All pins on the USB3803 provide ±5 kV HBM protection, as shown in Table 10-13.
10.12.2
EN 61000-4-2 PERFORMANCE
The EN 61000-4-2 ESD specification is an international standard that addresses system-level immunity to ESD strikes
while the end equipment is operational. In contrast, the HBM ESD tests are performed at the device level with the device
powered down.
DS00001691D-page 76
2014-2020 Microchip Technology Inc.
USB3803
Microchip contracts with Independent laboratories to test the USB3803 to EN 61000-4-2 in a working system. Reports
are available upon request. Please contact your Microchip representative and request information on third party ESD
test results. The reports show that systems designed with the USB3803 can safely provide the ESD performance shown
in Table 10-13 without additional board level protection.
In addition to defining the ESD tests, EN 61000-4-2 also categorizes the impact to equipment operation when the strike
occurs (ESD Result Classification). The USB3803 maintains an ESD Result Classification 1 or 2 when subjected to an
EN 61000-4-2 (level 4) ESD strike.
Both air discharge and contact discharge test techniques for applying stress conditions are defined by the EN 61000-42 ESD document.
10.12.3
AIR DISCHARGE
To perform this test, a charged electrode is moved close to the system being tested until a spark is generated. This test
is difficult to reproduce because the discharge is influenced by such factors as humidity, the speed of approach of the
electrode, and construction of the test equipment.
10.12.4
CONTACT DISCHARGE
The uncharged electrode first contacts the pin to prepare this test, and then the probe tip is energized. This yields more
repeatable results, and is the preferred test method. The independent test laboratories contracted by Microchip provide
test results for both types of discharge methods.
10.13 AC Specifications
10.13.1
REFCLK
External Clock:50% duty cycle ± 10%, ± 350ppm, Jitter < 100ps rms.
10.13.2
SERIAL INTERFACE
The Microchip Hub conforms to AC specifications as set forth in the I2C Specification for Slave-Only devices.
10.13.3
USB 2.0
The Microchip Hub conforms to all voltage, power, and timing characteristics and specifications as set forth in the USB
2.0 Specification. Please refer to the USB 2.0 Specification that is available from the www.usb.org web site.
2014-2020 Microchip Technology Inc.
DS00001691D-page 77
USB3803
11.0
APPLICATION REFERENCE
11.1
Application Diagram
The USB3803 requires several external components to function and ensure compliance with the USB 2.0 Specification.
TABLE 11-1:
COMPONENT VALUES IN APPLICATION DIAGRAMS
Reference
Designator
Value
Description
Notes
CVDD12BYP
1.0 F
Capacitor to ground for regulator stability
Place as close to the
USB3803 as possible
CVDD33BYP
4.7 F
Capacitor to ground for regulator stability
Place as close to the
USB3803 as possible
COUT
0.1 F
Bypass capacitor to ground
Place as close to the
USB3803 as possible
RBIAS
12.0k
Series resistor to establish reference voltage
used by analog circuits
RPU1
10k or 1k
Pull-up for I2C bus. 10k for 100 kHz or 400 kHz
operation, 1k for 1 MHz operation
Place as close to the
USB3803 as possible
—
RPU2
10k (or greater)
Pull-up for open-drain outputs
—
TABLE 11-2:
CAPACITANCE VALUES AT VBUS OF USB CONNECTOR
Port
Downstream
Upstream
DS00001691D-page 78
MIN Value
MAX Value
120 F
—
1 F
10 F
2014-2020 Microchip Technology Inc.
USB3803
FIGURE 11-1:
INTERNAL CHIP-TO-CHIP INTERFACE
USB3803
Port 1 Disabled
VDD33_BYP
USBUP_DP
USBUP_DM
REFCLK
BYPASS_N
RESET_N
HUB_CONNECT
LTE
Baseband
Processor
USBDN1_DP
USBDN1_DM
USBDN2_DP
USBDN2_DM
USBDN3_DP
3G
Baseband
Processor
USBDN3_DM
VDD_INTN
RBIAS
Applications
Processor
R BIAS
RPU2
INT_N
VDD_I2C
VBAT
SCL
SDA
R PU1
VBAT
COUT
+1.8V
RPU1
VDD_CORE_REG
VDD33_BYP
Connect pins to
either
VDD33_BYP or
GND.
REF_SEL1
REF_SEL0
I2C_ASEL1
I2C_ASEL0
VDD33_BYP
VDD12_BYP
VSS
2014-2020 Microchip Technology Inc.
COUT
CVDD12BYP
C VDD33BYP
DS00001691D-page 79
USB3803
FIGURE 11-2:
DUAL USB DEVICE AND HOST APPLICATION
VBUS
VBUS
DP
DM
GND
USB 2.0
Host/OTG
Port
USB3740 High
Speed 2:1 Switch
Port 1 Disabled
USB3803
Applications
Processor
VDD33_BYP
USBUP_DP
USBUP_DM
From
Applications
Processor
REFCLK
USBDN1_DP
USB 2.0
Device
Port
USBDN1_DM
USBDN2_DP
USBDN2_DM
BYPASS_N
RESET_N
HUB_CONNECT
USBDN3_DP
3G
Baseband
Processor
USBDN3_DM
VDD_INTN
RBIAS
RBIAS
RPU2
INT_N
VDD_I2C
VBAT
SCL
SDA
PMIC
R PU1
VBAT
VDD_CORE_REG
VDD33_BYP
Connect pins to
either
VDD33_BYP or
GND.
REF_SEL1
REF_SEL0
I2C_ASEL1
I2C_ASEL0
COUT
VDD33_BYP
VDD12_BYP
VSS
Note:
COUT
+1.8V
R PU1
CVDD12BYP
CVDD33BYP
While RESET_N is driven low, all other inputs from Applications Processor should also be driven low to
minimize current draw.
To disable a downstream port, tie DP and DM to VDD33_BYP pin of the USB3803.
DS00001691D-page 80
2014-2020 Microchip Technology Inc.
USB3803
FIGURE 11-3:
APPLICATION WITH USB PORT ACCESS TO THREE INTERNAL DEVICES
Audio
Codec
VBUS
VBUS
DP
DM
GND
USB3803
USBUP_DP
USBUP_DM
REFCLK
From
Applications
Processor
Note: Grounding HUB_CONNECT
requires that SP_ILOCK register
bit connect_n be cleared to allow
hub to exit Hub Connect Stage.
BYPASS_N
RESET_N
HUB_CONNECT
USBDN3_DP
USBDN2_DP
USBDN2_DM
USBDN1_DP
VDD_INTN
RBIAS
RBIAS
INT_N
VDD_I2C
VBAT
SCL
SDA
RPU1
3G
Baseband
Processor
USBDN1_DM
RPU2
PMIC
Applications
Processor
USBDN3_DM
VBAT
COUT
+1.8V
RPU1
VDD_CORE_REG
VDD33_BYP
Connect pins to
either
VDD33_BYP or
GND.
REF_SEL1
REF_SEL0
I2C_ASEL1
I2C_ASEL0
VDD33_BYP
VDD12_BYP
VSS
2014-2020 Microchip Technology Inc.
COUT
CVDD12BYP
CVDD33BYP
DS00001691D-page 81
USB3803
12.0
Note:
PACKAGE OUTLINES, TAPE & REEL DRAWINGS, PACKAGE MARKING
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging.
25WLCSP, 1.95X1.95MM BODY, 0.4MM PITCH
Note: For the most current package drawings,
see the Microchip Packaging Specification at
http://www.microchip.com/packaging
FIGURE 12-1:
DS00001691D-page 82
2014-2020 Microchip Technology Inc.
USB3803
FIGURE 12-2:
25WLCSP, 1.95X1.95 TAPE AND REEL
2014-2020 Microchip Technology Inc.
DS00001691D-page 83
USB3803
FIGURE 12-3:
DS00001691D-page 84
25WLCSP, 1.95X1.95 REEL DIMENSIONS
2014-2020 Microchip Technology Inc.
USB3803
FIGURE 12-4:
25WLCSP, 1.95X1.95 TAPE SECTIONS
FIGURE 12-5:
REFLOW PROFILE AND CRITICAL PARAMETERS FOR ROHS COMPLIANT
SOLDER
2014-2020 Microchip Technology Inc.
DS00001691D-page 85
USB3803
FIGURE 12-6:
PACKAGE MARKING
Family/Device Number
Note:
The Family/Device Number for the USB3803 is “03”.
DS00001691D-page 86
2014-2020 Microchip Technology Inc.
USB3803
APPENDIX A:
TABLE A-1:
REVISION HISTORY
REVISION HISTORY
Revision Level & Date
DS00001691D (02-17-20)
Section/Figure/Entry
Table 10-1, “Absolute Maximum Ratings,” on page 70
Correction
Added junction temperature information.
Table 10-3, “25-BALL WLCSP Added package thermal parameters table.
PACKAGE THERMAL
PARAMETERS,” on page 71
DS00001691C (01-08-18)
DS00001691B (03-16-15)
Section 4.4.7, "Hub Mode
Timing Diagram," on page 19
Updated the section with timing diagram and
parameters included in the previous revision.
All
Removed references to USB3803B and USB3803Bi
revisions.
Removed mentions of “(USB3803C Only)” in texts
and graphics.
Other minor text changes throughout.
Figure 12-1, "25WLCSP,
1.95x1.95mm Body, 0.4mm
Pitch"
Package diagram updated.
Section 10.6, "Dynamic Char- Changed RESET_N minimum active low pulse from
acteristics: Digital I/O Pins,"
100s to 1ms.
on page 74
FIGURE 12-6: Package
marking on page 86
Added note under figure: “Note: The Family/Device
Number for the USB3803 is “03”.”
Cover
Updated ESD bullet for consistency.
Section 1.0, "General
Description," on page 4
Added new section detailing differences between
USB3803 family members, including functional
revision B and C information.
All
Simplified part number throughout document:
“USB3803C” -> “USB3803”
Added “(USB3803C Only)” caveats throughout
document in sections specific to Bypass Mode.
DS00001691A replaces the previous SMSC version, Revision 1.1
2014-2020 Microchip Technology Inc.
DS00001691D-page 87
USB3803
THE MICROCHIP WEB SITE
Microchip provides online support via our WWW site at www.microchip.com. This web site is used as a means to make
files and information easily available to customers. Accessible by using your favorite Internet browser, the web site contains the following information:
• Product Support – Data sheets and errata, application notes and sample programs, design resources, user’s
guides and hardware support documents, latest software releases and archived software
• General Technical Support – Frequently Asked Questions (FAQ), technical support requests, online discussion
groups, Microchip consultant program member listing
• Business of Microchip – Product selector and ordering guides, latest Microchip press releases, listing of seminars and events, listings of Microchip sales offices, distributors and factory representatives
CUSTOMER CHANGE NOTIFICATION SERVICE
Microchip’s customer notification service helps keep customers current on Microchip products. Subscribers will receive
e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or
development tool of interest.
To register, access the Microchip web site at www.microchip.com. Under “Support”, click on “Customer Change Notification” and follow the registration instructions.
CUSTOMER SUPPORT
Users of Microchip products can receive assistance through several channels:
•
•
•
•
Distributor or Representative
Local Sales Office
Field Application Engineer (FAE)
Technical Support
Customers should contact their distributor, representative or field application engineer (FAE) for support. Local sales
offices are also available to help customers. A listing of sales offices and locations is included in the back of this document.
Technical support is available through the web site at: http://microchip.com/support
DS00001691D-page 88
2014-2020 Microchip Technology Inc.
USB3803
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, for example, on pricing or delivery, refer to the factory or the listed sales office.
X(1)
PART NO.
Device
[X]
-1-
Device:
USB3803
Functional
Revision:
C
= Functional Revision C
Temperature
Range:
Blank
i
=
0C to
= -40C to
Package:
GL
= 25-Ball WLCSP
Tape and Reel:( 1)
TR
= Tape and Reel
2014-2020 Microchip Technology Inc.
TR(2)
Package Tape & Reel
Temp.
Range
Func.
Rev.
-
GL
+70C
+85C
Examples:
a)
USB3803Ci-1-GL-TR
Functional Revision C (Bypass Mode)
Industrial temperature,
25-Ball WLCSP
Tape & Reel
(Commercial)
(Industrial)
Note 1:
Tape and Reel identifier only appears in the
catalog part number description. This
identifier is used for ordering purposes and is
not printed on the device package. Check
with your Microchip Sales Office for package
availability with the Tape and Reel option.
Reel size is 3,000.
DS00001691D-page 89
USB3803
NOTES:
DS00001691D-page 90
2014-2020 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
•
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Trademarks
The Microchip name and logo, the Microchip logo, Adaptec, AnyRate, AVR, AVR logo, AVR Freaks, BesTime, BitCloud, chipKIT, chipKIT logo,
CryptoMemory, CryptoRF, dsPIC, FlashFlex, flexPWR, HELDO, IGLOO, JukeBlox, KeeLoq, Kleer, LANCheck, LinkMD, maXStylus, maXTouch,
MediaLB, megaAVR, Microsemi, Microsemi logo, MOST, MOST logo, MPLAB, OptoLyzer, PackeTime, PIC, picoPower, PICSTART, PIC32 logo,
PolarFire, Prochip Designer, QTouch, SAM-BA, SenGenuity, SpyNIC, SST, SST Logo, SuperFlash, Symmetricom, SyncServer, Tachyon,
TempTrackr, TimeSource, tinyAVR, UNI/O, Vectron, and XMEGA are registered trademarks of Microchip Technology Incorporated in the U.S.A.
and other countries.
APT, ClockWorks, The Embedded Control Solutions Company, EtherSynch, FlashTec, Hyper Speed Control, HyperLight Load, IntelliMOS, Libero,
motorBench, mTouch, Powermite 3, Precision Edge, ProASIC, ProASIC Plus, ProASIC Plus logo, Quiet-Wire, SmartFusion, SyncWorld, Temux,
TimeCesium, TimeHub, TimePictra, TimeProvider, Vite, WinPath, and ZL are registered trademarks of Microchip Technology Incorporated in the
U.S.A.
Adjacent Key Suppression, AKS, Analog-for-the-Digital Age, Any Capacitor, AnyIn, AnyOut, BlueSky, BodyCom, CodeGuard,
CryptoAuthentication, CryptoAutomotive, CryptoCompanion, CryptoController, dsPICDEM, dsPICDEM.net, Dynamic Average Matching, DAM,
ECAN, EtherGREEN, In-Circuit Serial Programming, ICSP, INICnet, Inter-Chip Connectivity, JitterBlocker, KleerNet, KleerNet logo, memBrain,
Mindi, MiWi, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient Code Generation, PICDEM, PICDEM.net,
PICkit, PICtail, PowerSmart, PureSilicon, QMatrix, REAL ICE, Ripple Blocker, SAM-ICE, Serial Quad I/O, SMART-I.S., SQI, SuperSwitcher,
SuperSwitcher II, Total Endurance, TSHARC, USBCheck, VariSense, ViewSpan, WiperLock, Wireless DNA, and ZENA are trademarks of
Microchip Technology Incorporated in the U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated in the U.S.A.
The Adaptec logo, Frequency on Demand, Silicon Storage Technology, and Symmcom are registered trademarks of Microchip Technology Inc. in
other countries.
GestIC is a registered trademark of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in other
countries.
All other trademarks mentioned herein are property of their respective companies.
© 2014-2020, Microchip Technology Incorporated, All Rights Reserved.
ISBN: 9781522456278
For information regarding Microchip’s Quality Management Systems,
please visit www.microchip.com/quality.
2014-2020 Microchip Technology Inc.
DS00001691D-page 91
Worldwide Sales and Service
AMERICAS
ASIA/PACIFIC
ASIA/PACIFIC
EUROPE
Corporate Office
2355 West Chandler Blvd.
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Fax: 480-792-7277
Technical Support:
http://www.microchip.com/
support
Web Address:
www.microchip.com
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Tel: 61-2-9868-6733
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Tel: 631-435-6000
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Tel: 408-735-9110
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Tel: 905-695-1980
Fax: 905-695-2078
DS00001691D-page 92
China - Xiamen
Tel: 86-592-2388138
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Tel: 45-4450-2828
Fax: 45-4485-2829
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Tel: 46-8-5090-4654
UK - Wokingham
Tel: 44-118-921-5800
Fax: 44-118-921-5820
2014-2020 Microchip Technology Inc.
05/14/19
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