USB4624
USB 2.0 HSIC Hi-Speed 4-Port Hub Controller
Highlights
Additional Features
• Hub Controller IC with 4 downstream ports
• High-Speed Inter-Chip (HSIC) support
- Upstream port selectable between HSIC or
USB 2.0
- 2 downstream HSIC ports
• USB-IF Battery Charger revision 1.2 support on
up & downstream ports (DCP, CDP, SDP)
• Battery charging support for Apple devices
• FlexConnect: Downstream port 1 able to swap
with upstream port, allowing master capable
devices to control other devices on the hub
• USB to I2C/SPI bridge endpoint support
• USB Link Power Management (LPM) support
• SUSPEND pin for remote wakeup indication to
host
• Start Of Frame (SOF) synchronized clock output
pin
• Vendor Specific Messaging (VSM) support
• Enhanced OEM configuration options available
through OTP or SMBus Slave Port
• Flexible power rail support
- VBUS or VBAT only operation
- 3.3V only operation
- VBAT + 1.8V operation
- 3.3V + 1.8V operation
• 48-pin (7x7mm) SQFN, RoHS compliant package
• MultiTRAK™
- Dedicated Transaction Translator per port
• PortMap
- Configurable port mapping and disable
sequencing
• PortSwap
- Configurable differential intra-pair signal
swapping
• PHYBoost™
- Programmable USB transceiver drive
strength for recovering signal integrity
• VariSense™
- Programmable USB receiver sensitivity
• Low power operation
• Full Power Management with individual or ganged
power control of each downstream port
• Built-in Self-Powered or Bus-Powered internal
default settings provide flexibility in the quantity of
USB expansion ports utilized without redesign
• Supports “Quad Page” configuration OTP flash
- Four consecutive 200 byte configuration
pages
• Fully integrated USB termination and Pull-up/Pulldown resistors
• On-chip Power On Reset (POR)
• Internal 3.3V and 1.2V voltage regulators
• On Board 24MHz Crystal Driver, Resonator, or
External 24MHz clock input
• USB host/device speed indicator. Per-port 3-color
LED drivers indicate the speed of USB host and
device connection - hi-speed (480 Mbps), fullspeed (12 Mbps), low-speed (1.5 Mbps)
• Environmental
- Commercial temperature range support (0ºC
to 70ºC)
- Industrial temperature range support (-40ºC
to 85ºC)
Target Applications
•
•
•
•
•
•
•
•
•
LCD monitors and TVs
Multi-function USB peripherals
PC mother boards
Set-top boxes, DVD players, DVR/PVR
Printers and scanners
PC media drive bay
Portable hub boxes
Mobile PC docking
Embedded systems
2012 - 2019 Microchip Technology Inc.
DS00001717C-page 1
USB4624
TO OUR VALUED CUSTOMERS
It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip
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The last character of the literature number is the version number, (e.g., DS30000000A is version A of document DS30000000).
Errata
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To determine if an errata sheet exists for a particular device, please check with one of the following:
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When contacting a sales office, please specify which device, revision of silicon and data sheet (include -literature number) you are
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DS00001717C-page 2
2012 - 2019 Microchip Technology Inc.
USB4624
Table of Contents
1.0 Introduction ..................................................................................................................................................................................... 4
2.0 Acronyms and Definitions ............................................................................................................................................................... 6
3.0 Pin Descriptions .............................................................................................................................................................................. 7
4.0 Power Connections ....................................................................................................................................................................... 16
5.0 Modes of Operation ...................................................................................................................................................................... 18
6.0 Device Configuration ..................................................................................................................................................................... 22
7.0 Device Interfaces .......................................................................................................................................................................... 25
8.0 Functional Descriptions ................................................................................................................................................................. 30
9.0 Operational Characteristics ........................................................................................................................................................... 35
10.0 Package Outline
................................................................................................................................................................................................... 44
Appendix A: Data sheet Revision History ........................................................................................................................................... 45
The Microchip Web Site ...................................................................................................................................................................... 46
Customer Change Notification Service ............................................................................................................................................... 46
Customer Support ............................................................................................................................................................................... 46
Product Identification System ............................................................................................................................................................. 47
2012 - 2019 Microchip Technology Inc.
DS00001717C-page 3
USB4624
1.0
INTRODUCTION
The USB4624 is a low-power, OEM configurable, MTT (Multi-Transaction Translator) USB 2.0 hub controller with 4
downstream ports and advanced features for embedded USB applications. The USB4624 is fully compliant with the
USB 2.0 Specification, USB 2.0 Link Power Management Addendum, High-Speed Inter-Chip (HSIC) USB Electrical
Specification Revision 1.0, and will attach to an upstream port as a Full-Speed hub or as a Full-/Hi-Speed hub. The 4port hub supports Low-Speed, Full-Speed, and Hi-Speed (if operating as a Hi-Speed hub) downstream devices on all of
the enabled downstream (non-HSIC) ports. HSIC ports support only Hi-Speed operation.
The USB4624 has been specifically optimized for embedded systems where high performance, and minimal BOM costs
are critical design requirements. Standby mode power has been minimized and reference clock inputs can be aligned
to the customer’s specific application. Flexible power rail options ease integration into energy efficient designs by allowing the USB4624 to be powered in a single-source (VBUS, VBAT, 3.3V) or a dual-source (VBAT + 1.8, 3.3V + 1.8) configuration. Additionally, all required resistors on the USB ports are integrated into the hub, including all series termination
and pull-up/pull-down resistors on the D+ and D– pins.
The USB4624 supports both upstream battery charger detection and downstream battery charging. The USB4624 integrated battery charger detection circuitry supports the USB-IF Battery Charging (BC1.2) detection method and most
Apple devices. These circuits are used to detect the attachment and type of a USB charger and provide an interrupt
output to indicate charger information is available to be read from the device’s status registers via the serial interface.
The USB4624 provides the battery charging handshake and supports the following USB-IF BC1.2 charging profiles:
•
•
•
•
DCP: Dedicated Charging Port (Power brick with no data)
CDP: Charging Downstream Port (1.5A with data)
SDP: Standard Downstream Port (0.5A with data)
Custom profiles loaded via SMBus or OTP
The USB4624 provides an additional USB endpoint dedicated for use as a USB to I2C/SPI interface, allowing external
circuits or devices to be monitored, controlled, or configured via the USB interface. Additionally, the USB4624 includes
many powerful and unique features such as:
FlexConnect, which provides flexible connectivity options. The USB4624’s downstream port 1 can be swapped with
the upstream port, allowing master capable devices to control other devices on the hub.
MultiTRAK™ Technology, which utilizes a dedicated Transaction Translator (TT) per port to maintain consistent fullspeed data throughput regardless of the number of active downstream connections. MultiTRAKTM outperforms conventional USB 2.0 hubs with a single TT in USB full-speed data transfers.
PortMap, which provides flexible port mapping and disable sequences. The downstream ports of a USB4624 hub can
be reordered or disabled in any sequence to support multiple platform designs with minimum effort. For any port that is
disabled, the USB4624 hub controllers automatically reorder the remaining ports to match the USB host controller’s port
numbering scheme.
PortSwap, which adds per-port programmability to USB differential-pair pin locations. PortSwap allows direct alignment
of USB signals (D+/D-) to connectors to avoid uneven trace length or crossing of the USB differential signals on the
PCB.
PHYBoost, which provides programmable levels of Hi-Speed USB signal drive
strength in the downstream port transceivers. PHYBoost attempts to restore USB signal integrity in a compromised system environment. The graphic on the right shows
an example of Hi-Speed USB eye diagrams before and after PHYBoost signal integrity restoration.
VariSense, which controls the USB receiver sensitivity enabling programmable levels of USB signal receive sensitivity. This capability allows operation in a sub-optimal
system environment, such as when a captive USB cable is used.
The USB4624 is available in commercial (0°C to +70°C) and industrial (-40°C to +85°C) temperature range versions.
As shown in the ordering code matrix, two USB4624 firmware revisions are available: “-1080” and “-1070”. The -1080
version enables the internal Hub Controller, while the -1070 version disables it. There are no additional differences
between these two versions.
DS00001717C-page 4
2012 - 2019 Microchip Technology Inc.
USB4624
The Hub Controller adds advanced functionality to the USB4624 by enabling the host to send commands directly to it
via the upstream USB connection. Commands to the Hub Controller must be sent to the virtual 5th port in the hub. The
following functions can be controlled via commands through the Hub Controller:
• USB to SMBus Bridging: The host can send commands through USB to any device connected to the hub through
the SMBus.
• USB to UART Bridging: The host can send commands through SUB to any device connected to the hub through
the UART.
• GPIO Control: The GPIOs on the hub can be dynamically configured and controlled by the host.
• OTP Programming: Permanent customer configurations can be loaded to the One Time Programmable memory.
1.1
Block Diagram
Figure 1-1 details the internal block diagram of the USB4624.
FIGURE 1-1:
SYSTEM BLOCK DIAGRAM
Up or
Downstream
HSIC/USB
RESET_N
VDDCOREREG
VBAT
VDDA33
VDD33
SDA
SCL
VDDCR12
Serial
Interface
1.2V Reg
3.3V Reg
Flex HSIC Flex PHY
To I2C Master/Slave
Controller
SIE
Repeater
TT #1
TT #2 TT #3 TT #4 TT #5
Routing & Port Re-Ordering Logic
Bridge
UDC
20
2KB
DP
SRAM
256B
IRAM
Swap HSIC
HSIC
PHY
HSIC
HSIC
PHY
Port Power
OCS
8051
Controller
GPIO
SPI
GPIO
SPI/I2C
PHY
2KB
OTP
Down or
Upstream
Port Controller
4KB
SRAM
32KB
ROM
PHY
Downstream Downstream Downstream
2012 - 2019 Microchip Technology Inc.
DS00001717C-page 5
USB4624
2.0
ACRONYMS AND DEFINITIONS
2.1
Acronyms
EOP:
End of Packet
EP:
Endpoint
FS:
Full-Speed
GPIO:
General Purpose I/O (that is input/output to/from the device)
HS:
Hi-Speed
HSOS: High Speed Over Sampling
HSIC:
2
High-Speed Inter-Chip
I C:
Inter-Integrated Circuit
LS:
Low-Speed
OTP:
One Time Programmable
PCB:
Printed Circuit Board
PCS:
Physical Coding Sublayer
PHY:
Physical Layer
SMBus: System Management Bus
UUID:
Universally Unique IDentification
2.2
Reference Documents
1.
2.
3.
4.
5.
6.
UNICODE UTF-16LE For String Descriptors USB Engineering Change Notice, December 29th, 2004, http://
www.usb.org
Universal Serial Bus Specification, Revision 2.0, April 27th, 2000, http://www.usb.org
Battery Charging Specification, Revision 1.2, Dec. 07, 2010, http://www.usb.org
High-Speed Inter-Chip USB Electrical Specification, Version 1.0, Sept. 23, 2007, http://www.usb.org
I2C-Bus Specification, Version 1.1, http://www.nxp.com
System Management Bus Specification, Version 1.0, http://smbus.org/specs
DS00001717C-page 6
2012 - 2019 Microchip Technology Inc.
USB4624
PIN DESCRIPTIONS
RESET_N
PIO10
SCL/SMBCLK
VDD33
SDA/SMBDATA
UART_TX/OCS4_N
PRTPWR4/PRTCTL4
UART_RX/OCS3_N
SPI_CLK
SPI_DO/SPI_SPD_SEL
SPI_CE_N
35
34
33
32
31
30
29
28
27
26
25
48-SQFN PIN ASSIGNMENTS
VBUS_DET
FIGURE 3-1:
36
3.0
VDDA33
37
24
SPI_DI
NC
VDD12
38
23
FLEX_HSIC_UP_STROBE
39
22
NC
FLEX_USBUP_DM/PRT_DIS_M0
40
21
PRTPWR3/PRTCTL3/PIO43
FLEX_USBUP_DP/PRT_DIS_P0
41
20
NC
FLEX_HSIC_UP_DATA
42
19
HSIC_EN2
XTAL2
43
18
VDD33
XTAL1/REFCLK
44
17
VDDCR12
NC
45
16
NC
RBIAS
46
15
HSIC_EN1
VDDCOREREG
47
14
SUSPEND
VDDA33
48
13
SOF
USB4624
(Top View)
3
4
5
6
7
8
9
10
11
SWAP_HSIC_DN_STROBE1
SWAP_HSIC_DN_DATA1
HSIC_DN_DATA2
HSIC_DN_STROBE2
VDD12
USBDN3_DM/PRT_DIS_M3
USBDN3_DP/PRT_DIS_P3
USBDN4_DM/PRT_DIS_M4
USBDN4_DP/PRT_DIS_P4
12
2
VDD12
VDDA33
1
VBAT
Ground Pad
(must be connected to VSS)
Indicates pins on the bottom of the device.
2012 - 2019 Microchip Technology Inc.
DS00001717C-page 7
USB4624
3.1
Pin Descriptions
This section provides a detailed description of each pin. The signals are arranged in functional groups according to their
associated interface.
The “_N” symbol in the signal name indicates that the active, or asserted, state occurs when the signal is at a low voltage
level. For example, RESET_N indicates that the reset signal is active low. When “_N” is not present after the signal
name, the signal is asserted when at the high voltage level.
The terms assertion and negation are used exclusively. This is done to avoid confusion when working with a mixture of
“active low” and “active high” signals. The term assert, or assertion, indicates that a signal is active, independent of
whether that level is represented by a high or low voltage. The term negate, or negation, indicates that a signal is inactive.
Note:
The buffer type for each signal is indicated in the BUFFER TYPE column of Table 3-1. A description of the
buffer types is provided in Section 3.3.
TABLE 3-1:
PIN DESCRIPTIONS
Num Pins
Buffer
Type
Name
Symbol
Upstream USB
D+
(Flex Port 0)
FLEX_USBUP_DP
AIO
Port 0 D+
Disable
Configuration
Strap
PRT_DIS_P0
IS
Description
USB/HSIC INTERFACES
1
Upstream USB Port 0 D+ data signal.
See Note 3-1.
Note:
The upstream Port 0 signals can be
optionally swapped with the downstream Port 1 signals.
This strap is used in conjunction with
PRT_DIS_M0 to disable USB Port 0.
0 = Port 0 D+ Enabled
1 = Port 0 D+ Disabled
Note:
Both PRT_DIS_P0 and PRT_DIS_M0
must be tied to VDD33 at reset to place
Port 0 into HSIC mode.
See Note 3-2 for more information on configuration
straps.
1
Upstream USB
D(Flex Port 0)
FLEX_USBUP_DM
AIO
Upstream USB Port 0 D- data signal.
See Note 3-1.
Note:
The upstream Port 0 signals can be
optionally swapped with the downstream Port 1 signals.
Port 0 DDisable
Configuration
Strap
PRT_DIS_M0
IS
This strap is used in conjunction with PRT_DIS_P0
to disable USB Port 0.
0 = Port 0 D- Enabled
1 = Port 0 D- Disabled
Note:
Both PRT_DIS_P0 and PRT_DIS_M0
must be tied to VDD33 at reset to place
Port 0 into HSIC mode.
See Note 3-2 for more information on configuration
straps.
1
Upstream
HSIC Data
(Flex Port 0)
DS00001717C-page 8
FLEX_HSIC_UP_
DATA
HSIC
Upstream HSIC Port 0 DATA signal.
See Note 3-1.
Note:
The upstream Port 0 signals can be
optionally swapped with the downstream Port 1 signals.
2012 - 2019 Microchip Technology Inc.
USB4624
TABLE 3-1:
PIN DESCRIPTIONS (CONTINUED)
Num Pins
Name
Symbol
Buffer
Type
FLEX_HSIC_UP_
STROBE
HSIC
1
Upstream
HSIC Strobe
(Flex Port 0)
Upstream HSIC Port 0 STROBE signal.
See Note 3-1.
Note:
The upstream Port 0 signals can be
optionally swapped with the downstream Port 1 signals.
SWAP_HSIC_DN_D
ATA1
HSIC
1
Downstream
HSIC Data
(Swap Port 1)
Downstream HSIC Port 1 DATA signal.
Note:
The downstream Port 1 signals can be
optionally swapped with the upstream
Port 0 signals.
SWAP_HSIC_DN_S
TROBE1
HSIC
1
Downstream
HSIC Strobe
(Swap Port 1)
Downstream HSIC Port 1 STROBE signal.
Note:
The downstream Port 1 signals can be
optionally swapped with the upstream
Port 0 signals.
1
Downstream
HSIC Data
(Port 2)
HSIC_DN_DATA2
HSIC
Downstream HSIC Port 2 DATA signal.
1
Downstream
HSIC Strobe
(Port 2)
HSIC_DN_STROBE2
HSIC
Downstream HSIC Port 2 STROBE signal.
Downstream
USB D+
(Port 3)
USBDN3_DP
AIO
Port 3 D+
Disable
Configuration
Strap
PRT_DIS_P3
IS
1
Description
Downstream USB Port 3 D+ data signal.
This strap is used in conjunction with
PRT_DIS_M3 to disable USB Port 3.
0 = Port 3 D+ Enabled
1 = Port 3 D+ Disabled
Note:
Both PRT_DIS_P3 and PRT_DIS_M3
must be tied to VDD33 at reset to disable the associated port.
See Note 3-2 for more information on configuration
straps.
1
Downstream
USB D(Port 3)
USBDN3_DM
AIO
Port 3 DDisable
Configuration
Strap
PRT_DIS_M3
IS
Downstream USB Port 3 D- data signal.
This strap is used in conjunction with PRT_DIS_P3
to disable USB Port 3.
0 = Port 3 D- Enabled
1 = Port 3 D- Disabled
Note:
Both PRT_DIS_P3 and PRT_DIS_M3
must be tied to VDD33 at reset to disable the associated port.
See Note 3-2 for more information on configuration
straps.
2012 - 2019 Microchip Technology Inc.
DS00001717C-page 9
USB4624
TABLE 3-1:
PIN DESCRIPTIONS (CONTINUED)
Name
Symbol
Buffer
Type
Downstream
USB D+
(Port 4)
USBDN4_DP
AIO
Port 4 D+
Disable
Configuration
Strap
PRT_DIS_P4
IS
Num Pins
1
Description
Downstream USB Port 4 D+ data signal.
This strap is used in conjunction with
PRT_DIS_M4 to disable USB Port 4.
0 = Port 4 D+ Enabled
1 = Port 4 D+ Disabled
Note:
Both PRT_DIS_P4 and PRT_DIS_M4
must be tied to VDD33 at reset to disable the associated port.
See Note 3-2 for more information on configuration
straps.
1
Downstream
USB D(Port 4)
USBDN4_DM
AIO
Port 4 DDisable
Configuration
Strap
PRT_DIS_M4
IS
Downstream USB Port 4 D- data signal.
This strap is used in conjunction with PRT_DIS_P4
to disable USB Port 4.
0 = Port 4 D- Enabled
1 = Port 4 D- Disabled
Note:
Both PRT_DIS_P4 and PRT_DIS_M4
must be tied to VDD33 at reset to disable the associated port.
See Note 3-2 for more information on configuration
straps.
2
1
1
I2C/SMBUS INTERFACE
SCL
SMBus Clock
SMBCLK
I_SMB
SDA
IS/OD8
I2C bidirectional serial data
SMBus Serial
Data
SMBDATA
IS/OD8
SMBus bidirectional serial data
SPI Chip
Enable Output
SPI_CE_N
O12
Active-low SPI chip enable output.
Note:
If the SPI is enabled, this pin will be
driven high in powerdown states.
SPI Clock
Output
SPI_CLK
O12
SPI clock output
SPI Data
Output
SPI_DO
O12
SPI data output
SPI Speed
Select
Configuration
Strap
SPI_SPD_SEL
IS
(PD)
This strap is used to select the speed of the SPI.
I2C Serial Data
I_SMB
I2C serial clock input
I C Serial
Clock Input
SMBus serial clock input
SPI MASTER INTERFACE
1
1
1
0 = 30MHz (default)
1 = 60MHz
Note:
If the latched value on reset is 1, this pin
is tri-stated when the chip is in the suspend state. If the latched value on reset
is 0, this pin is driven low during a suspend state.
See Note 3-2 for more information on configuration
straps.
DS00001717C-page 10
2012 - 2019 Microchip Technology Inc.
USB4624
TABLE 3-1:
Num Pins
PIN DESCRIPTIONS (CONTINUED)
Buffer
Type
Name
Symbol
SPI Data Input
SPI_DI
UART Receive
Input
UART_RX
IS
Port 3 OverCurrent Sense
Input
OCS3_N
IS
(PU)
UART Transmit
Output
UART_TX
O8
Port 4 OverCurrent Sense
Input
OCS4_N
IS
(PU)
System Reset
Input
RESET_N
I_RST
Crystal Input
XTAL1
ICLK
External 24 MHz crystal input
1
Reference
Clock Input
REFCLK
ICLK
Reference clock input. The device may be
alternatively driven by a single-ended clock
oscillator. When this method is used, XTAL2
should be left unconnected.
1
Crystal Output
XTAL2
OCLK
External 24 MHz crystal output
1
External USB
Transceiver
Bias Resistor
RBIAS
AI
A 12.0k (+/- 1%) resistor is attached from ground
to this pin to set the transceiver’s internal bias
settings.
Suspend
Output
SUSPEND
PU
This signal is used to indicate that the entire hub
has entered the USB suspend state and that
VBUS current consumption should be reduced in
accordance with the USB specification. Refer to
Section 8.6, "Suspend (SUSPEND)," on page 34
for additional information.
Note:
SUSPEND must be enabled via the
Protouch configuration tool.
SOF
Synchronized
8KHz Clock
Output
SOF
O8
This signal outputs an 8KHz clock synchronized
with the USB Host SOF.
Note:
SOF output is controlled via the
SOF_ENABLE bit in the UTIL_CONFIG1 register
1
IS
(PD)
Description
SPI data input
MISC.
1
1
1
1
1
2012 - 2019 Microchip Technology Inc.
Internal UART receive input
Note:
This is a 3.3V signal. For RS232 operation, an external 12V translator is
required.
This active-low signal is input from an external
current monitor to indicate an over-current
condition on USB Port 3.
Internal UART transmit output
Note:
This is a 3.3V signal. For RS232 operation, an external 12V driver is required.
This active-low signal is input from an external
current monitor to indicate an over-current
condition on USB Port 4.
This active-low signal allows external hardware to
reset the device.
Note:
The active-low pulse must be at least
5us wide. Refer to Section 8.4.2, "External Chip Reset (RESET_N)," on
page 33 for additional information.
DS00001717C-page 11
USB4624
TABLE 3-1:
Num Pins
PIN DESCRIPTIONS (CONTINUED)
Name
Symbol
Buffer
Type
Detect
Upstream
VBUS Power
VBUS_DET
IS
Description
Detects state of upstream bus power.
When designing a detachable hub, this pin must
be connected to the VBUS power pin of the
upstream USB port through a resistor divider
(50k by 100k) to provide 3.3V.
For self-powered applications with a permanently
attached host, this pin must be connected to either
3.3V or 5.0V through a resistor divider to provide
3.3V.
1
In embedded applications, VBUS_DET may be
controlled (toggled) when the host desires to
renegotiate a connection without requiring a full
reset of the device.
Port 1 HSIC
Enable
HSIC_EN1
O8/
OD8
1
0 = Disconnect Port 1 HSIC
1 = Device ready to negotiate or sustain an HSIC
connection on Port 1.
Port 2 HSIC
Enable
HSIC_EN2
O8/
OD8
1
1
5
Used to indicate the connection state to the
downstream HSIC device attached to Port 2.
0 = Disconnect Port 2 HSIC
1 = Device ready to negotiate or sustain an HSIC
connection on Port 2.
Port 3 Power
Output
1
Used to indicate the connection state to the
downstream HSIC device attached to Port 1.
PRTPWR3
O8
Enables power to a downstream USB device
attached to Port 3.
0 = Power disabled on downstream Port 3
1 = Power enabled on downstream Port 3
Port 3 Control
PRTCTL3
OD8/IS
(PU)
Port 4 Power
Output
PRTPWR4
O8
When configured as PRTCTL3, this pin functions
as both the Port 3 power enable output
(PRTPWR3) and the Port 3 over-current sense
input (OCS3_N). Refer to the PRTPWR3 and
OCS3_N descriptions for additional information.
Enables power to a downstream USB device
attached to Port 4.
0 = Power disabled on downstream Port 4
1 = Power enabled on downstream Port 4
Port 4 Control
PRTCTL4
OD8/IS
(PU)
No Connect
NC
-
When configured as PRTCTL4, this pin functions
as both the Port 4 power enable output
(PRTPWR4) and the Port 4 over-current sense
input (OCS4_N). Refer to the PRTPWR4 and
OCS4_N descriptions for additional information.
This pin must be left floating for normal device
operation.
POWER
Battery Power
Supply Input
1
DS00001717C-page 12
VBAT
P
Battery power supply input. When VBAT is
connected directly to a +3.3V supply from the
system, the internal +3.3V regulator runs in
dropout and regulator power consumption is
eliminated. A 4.7 F (
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