USB5537B-5000AKZE

USB5537B 7-Port SS/HS USB Hub Controller General Description The USB5537B hub is a 7-port SuperSpeed/Hi-Speed, low-power, configurable hub controller family fully compliant with the USB 3.0 Specification. The USB5537B supports 5 Gbps SuperSpeed (SS), 480 Mbps HiSpeed (HS), 12 Mbps Full-Speed (FS) and 1.5 Mbps Low-Speed (LS) USB signaling for complete coverage of all defined USB operating speeds. The USB5537B supports USB 2.0 speeds through its USB 2.0 hub controller. The new SuperSpeed hub controller (available on 4 of the 7 ports) operates in parallel with the USB 2.0 controller, so the 5 Gbps SuperSpeed data transfers are not affected by the slower USB 2.0 traffic. The USB5537B supports battery charging on a per port basis. On battery charging enabled ports, the devices provide automatic USB data line handshaking. The handshaking supports USB 1.2 Charging Downstream Port (CDP), Dedicated Charging Port (DCP) and nonUSB 1.2 devices. The USB5537B is configured for operation through internal default settings, where custom configurations are supported through an on-chip OTP ROM, an external SPI ROM, or SMBus. Product Features • USB 3.0 compliant 5 Gbps, 480 Mbps, 12 Mbps and 1.5 Mbps operation, USB pins are 5 V tolerant - Integrated termination and pull-up/pull-down resistors • Four downstream USB 3.0 ports • Three additional USB 2.0 ports for use cases where SS is not required • Supports battery charging of most popular battery powered devices - USB-IF Battery Charging rev. 1.2 support (DCP & CDP) - Apple Portable product charger emulation - Blackberry charger emulation - Chinese YD/T 1591-2006 charger emulation - Chinese YD/T 1591-2009 charger emulation - Supports additional portable devices  2012 - 2015 Microchip Technology Inc. • Emulates portable/handheld native wall chargers - Charging profiles emulate a handheld device’s wall charger to enable fast charging (minutes vs. hours) • Enables charging from a mobile platform that is off • Support tablets’ high current requirements • Optimized for low-power operation and low thermal dissipation • Vendor Specific Messaging (VSM) support for firmware upload over USB • Configuration via OTP ROM, SPI ROM, or SMBus • On-chip 8051 µC manages VBUS, and other hub signals • 8 KB RAM, 32 KB ROM • One Time programmable (OTP) ROM: 8 kbit - Includes on-chip charge pump • Single 25 MHz XTAL or clock input for all on-chip PLL and clocking requirements • Supports JTAG boundary scan • PHYBoost (USB 2.0) - Selectable drive strength for improved signal integrity • VariSense (USB 2.0) - controls the receiver sensitivity enabling four programmable levels of USB signal receive sensitivity • IETF RFC 4122 compliant 128-bit UUID Software Features • Compatible with Microsoft Windows 7, Vista, XP, Mac OSX10.4+, and Linux Hub Drivers DS00001682C-page 1 USB5537B TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced. If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via E-mail at docerrors@microchip.com. We welcome your feedback. Most Current Data Sheet To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at: http://www.microchip.com You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page. The last character of the literature number is the version number, (e.g., DS30000000A is version A of document DS30000000). Errata An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of silicon and revision of document to which it applies. To determine if an errata sheet exists for a particular device, please check with one of the following: • Microchip’s Worldwide Web site; http://www.microchip.com • Your local Microchip sales office (see last page) When contacting a sales office, please specify which device, revision of silicon and data sheet (include -literature number) you are using. Customer Notification System Register on our web site at www.microchip.com to receive the most current information on all of our products. DS00001682C-page 2  2012 - 2015 Microchip Technology Inc. USB5537B Table of Contents 1.0 Introduction ..................................................................................................................................................................................... 4 2.0 Block Diagram ................................................................................................................................................................................. 6 3.0 Pin Information ................................................................................................................................................................................ 7 4.0 Standard Interface Connections ................................................................................................................................................... 13 5.0 Functional Operation ..................................................................................................................................................................... 24 6.0 DC Parameters ............................................................................................................................................................................. 63 7.0 AC Specifications .......................................................................................................................................................................... 67 8.0 Package Drawing .......................................................................................................................................................................... 70 Appendix A: Data Sheet Revision History ........................................................................................................................................... 72 Appendix B: Acronyms ........................................................................................................................................................................ 74 Appendix C: References ..................................................................................................................................................................... 75 The Microchip Web Site ...................................................................................................................................................................... 76 Customer Change Notification Service ............................................................................................................................................... 76 Customer Support ............................................................................................................................................................................... 76 Product Identification System ............................................................................................................................................................. 77  2012 - 2015 Microchip Technology Inc. DS00001682C-page 3 USB5537B 1.0 INTRODUCTION 1.1 Conventions Within this manual, the following abbreviations and symbols are used to improve readability. Example BIT FIELD.BIT x…y BITS[m:n] PIN Name of a single bit within a field Name of a single bit (BIT) in FIELD Range from x to y, inclusive Groups of bits from m to n, inclusive Pin Name zzzzb Binary number (value zzzz) 0xzzz Hexadecimal number (value zzz) zzh Hexadecimal number (value zz) rsvd Reserved memory location. Must write 0, read value indeterminate code Instruction code, or API function or parameter Multi Word Name Used for multiple words that are considered a single unit, such as: Resource Allocate message, or Connection Label, or Decrement Stack Pointer instruction. Section Name Section or Document name. x 1.2 Description Don’t care indicate a Parameter is optional or is only used under some conditions {,Parameter} Braces indicate Parameter(s) that repeat one or more times. [Parameter] Brackets indicate a nested Parameter. This Parameter is not real and actually decodes into one or more real parameters. Overview The USB5537B hub is a 7-port, low-power, configurable Hub Controller fully compliant with the USB 3.0 Specification 2. The USB5537B supports 5 Gbps SuperSpeed (SS), 480 Mbps Hi-Speed (HS), 12 Mbps Full-Speed (FS) and 1.5 Mbps Low-Speed (LS) USB signaling for complete coverage of all defined USB operating speeds. All required resistors on the USB ports are integrated into the hub. This includes all series termination resistors and all required pull-down and pull-up resistors on D+ and D- pins. The over-current sense inputs for the downstream facing ports have internal pull-up resistors. The USB5537B hub includes programmable features such as: • MultiTRAKTM Technology (USB 2.0): implements a dedicated Transaction Translator (TT) for each port. Dedicated TTs help maintain consistent full-speed data throughput regardless of the number of active downstream connections. • PortSwap (USB 2.0): allows direct alignment of USB signals (D+/D-) to connectors to avoid uneven trace length or crossing of the USB differential signals on the PCB. • PHYBoost (USB 2.0): enables 4 programmable levels of USB signal drive strength in downstream port transceivers (HS, FS, LS USB only). PHYBoost will also attempt to restore USB signal integrity. DS00001682C-page 4  2012 - 2015 Microchip Technology Inc. USB5537B Note: At the time of this writing, products with a USB Host (or products such as docking stations with USB hubs that must be submitted with an attached host enabled platform) are eligible for USB logo with a mixture of USB2.0 and USB3.0 ports. An example of such a product is a dedicated docking station that can only be used with a specific model or family of laptops. In this example, the docking station is submitted for USB logo testing with a laptop and it is tested as a system. USB devices containing a hub with an exposed upstream port that can be plugged into any host platform through USB cables and connectors (examples are USB enabled monitors, printers, hard drives, etc.) are not eligible for logo with a mixture of USB 3.0 and USB 2.0 ports. These devices will need to consume the USB 2.0-only ports internally in order to be eligible for a USB logo. As shown on the Product Identification System page, three USB5537B firmware versions are available: “-5000”, “-6070”, and “-6080”. These options differ in the following ways: • The Dynamic Charging Port feature and related DYNCPDIS_N pin function are only available on the -6070 and 6080 devices. Refer to Section 5.1.3, "Dynamic Charging Port (6070 and 6080 Only)" for additional details. • The TRST/DYNCPDIS_N/UCS_SMBALERT_N pin buffer type is “IPU” in the -6070 and -6080 devices and “I” in the -5000 device. Refer to Pin Information on page 7 for additional details. • The Global Suspend power consumption has been significantly lowered in the -6070 and -6080 device. Refer to Section 6.3, "Power Consumption" for additional details. • The three USB 2.0 ports are configured as removable by default in the -6070 device. The three USB 2.0 ports are configured as non-removable by default in the -5000 and -6080 devices. 1.3 Configurable Features The USB5537B hub controller provides a default configuration that is sufficient for most applications. When initialized in the default configuration, the following features may be configured: • • • • • Downstream non-removable ports, where the hub will automatically report as a compound device Downstream disabled ports Downstream port power control and over-current detection on a ganged or individual basis USB signal drive strength USB differential pair pin location The USB5537B hub controllers can alternatively be configured by OTP or as an SMBus slave device. When configured by an OTP or over SMBus, the following configurable features are provided: • Support for compound devices on a port-by-port basis • Selectable over-current sensing and port power control on an individual or ganged basis to match the circuit board component selection • Customizable vendor ID, product ID, and device ID • Configurable delay time for filtering the over-current sense inputs • Indication of the maximum current that the hub consumes from the USB upstream port • Indication of the maximum current required for the hub controller • Custom string descriptors (up to 30 characters): Product, manufacturer, and serial number  2012 - 2015 Microchip Technology Inc. DS00001682C-page 5 DS00001682C-page 6 RX SS PHY TX SS PHY Buffer Buffer USB2.0 PHY Downstream USB Port 1 Buffer SS PHY SS PHY Registers & Hub I/O USB2.0 PHY SS PHY RX Buffer USB2.0 PHY Downstream USB Port 2 SS PHY TX Buffer Registers & Hub I/O APB Bus 2k OTP Reset & 8051 Boot Seq. XData to APB Bridge SS PHY RX Buffer USB2.0 PHY SS PHY RX Buffer Timer SPI Master USB2.0 PHY Downstream USB Port 4 SS PHY TX Buffer HS/FS/LS Routing Logic Downstream USB Port 3 SS PHY TX Buffer Downstream RX SS bus Downstream TX SS bus VBUS Control XData USB 2.0 Hub Controller 8k RAM 32k ROM Embedded 8051 µC USB2.0 PHY USB2.0 PHY Downstream USB 2.0 Ports 5, 6, & 7 USB2.0 PHY SPI FIGURE 2-1: USB 3.0 Hub Controller RX TX 2.0 Buffer Common Block & PLL Upstream USB Port USB5537B BLOCK DIAGRAM USB5537B BLOCK DIAGRAM  2012 - 2015 Microchip Technology Inc. USB5537B 3.0 PIN INFORMATION This chapter outlines the pinning configurations for each chip. The detailed pin descriptions are listed by function in Section 3.2, "Pin Descriptions (Grouped by Function)," on page 8. Pin Configurations TEST VBUS TMS/OCS2 TCK/OCS1 TRST/DYNCPDIS_N/ UCS_SMBALERT_N TDI/OCS3 TDO/OCS4 SPI_DI SPI_DO SPI_CLK SPI_CE_N SM_CLK PRT_PWR5/PRT_CTL5/ SM_DAT PRT_PWR1/PRT_CTL1 PRT_PWR2/PRT_CTL2 VDD33 PRT_PWR3/PRT_CTL3 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 USB5537B 72-PIN QFN RESET_N FIGURE 3-1: 54 3.1 VDD12 55 36 PRT_PWR4/PRT_CTL4 VDD33 56 35 VDD12 USB2DM_DN6 57 34 USB2DM_DN5 USB2DP_DN6 58 33 USB2DP_DN5 USB2DM_DN7 59 32 USB3DM_RXDN4 USB2DP_DN7 60 31 USB3DP_RXDN4 USB2DP_UP 61 30 VDD12 USB2DM_UP 62 29 USB3DM_TXDN4 28 USB3DP_TXDN4 27 USB2DM_DN4 26 USB2DP_DN4  2012 - 2015 Microchip Technology Inc. 17 18 USB3DM_RXDN2 VDD33 USB2DP_DN3 16 19 USB3DP_RXDN2 72 15 RBIAS VDD12 USB2DM_DN3 14 20 USB3DM_TXDN2 (must be connected to VSS with a via field) 13 71 USB3DP_TXDN2 VDD33 12 USB3DP_TXDN3 USB2DM_DN2 21 11 Ground Pad USB2DP_DN2 70 10 XTALIN/CLK_IN VDD12 USB3DM_TXDN3 USB3DM_RXDN1 22 9 VDD12 69 8 ATEST XTALOUT USB3DP_RXDN1 USB3DP_RXDN3 23 7 24 68 VDD12 67 6 USB3DM_RXUP USB3DM_TXDN1 USB3DM_RXDN3 5 25 USB3DP_TXDN1 66 4 USB3DP_RXUP USB2DP_DN1 (Top View QFN-72) USB2DM_DN1 65 3 VDD12 2 USB5537B PRT_PWR6/PRT_CTL6 64 1 USB3DM_TXUP PRT_PWR7/PRT_CTL7 USB3DP_TXUP 63 Indicates pins on the bottom of the device. DS00001682C-page 7 USB5537B 3.2 Pin Descriptions (Grouped by Function) An N at the end of a signal name indicates that the active (asserted) state occurs when the signal is at a low voltage level. When the N is not present, the signal is asserted when it is at a high voltage level. The terms assertion and negation are used exclusively in order to avoid confusion when working with a mixture of active low and active high signals. The term assert, or assertion, indicates that a signal is active, independent of whether that level is represented by a high or low voltage. The term negate, or negation, indicates that a signal is inactive. TABLE 3-1: USB5537B PIN DESCRIPTIONS Symbol Buffer Type Description USB 3.0 INTERFACE USB3DP_TXUP IO-U USB 3 Upstream Upstream SuperSpeed transmit data plus USB3DM_TXUP IO-U USB 3 Upstream Upstream SuperSpeed transmit data minus USB3DP_RXUP IO-U USB 3 Upstream Upstream SuperSpeed receive data plus USB3DM_RXUP IO-U USB 3 Upstream Upstream SuperSpeed receive data minus USB3DP_TXDN[4:1] IO-U USB 3 Downstream Downstream SuperSpeed transmit data plus for ports 1 through 4. USB3DM_TXDN[4:1] IO-U USB 3 Downstream Downstream SuperSpeed transmit data minus for ports 1 through 4. USB3DP_RXDN[4:1] IO-U USB 3 Downstream Downstream SuperSpeed receive data plus for ports 1 through 4. USB3DM_RXDN[4:1] IO-U USB 3 Downstream Downstream SuperSpeed receive data minus for ports 1 through 4. USB 2.0 INTERFACE USB2DP_UP USB2DM_UP USB2DP_DN[7:1] USB2DM_DN[7:1] DS00001682C-page 8 IO-U IO-U IO-U IO-U USB Bus Data These pins connect to the upstream USB bus data signals. USB Bus Data These pins connect to the upstream USB bus data signals. Hi-Speed USB Data Downstream Hi-Speed data plus for ports 1 through 7. Hi-Speed USB Data Downstream Hi-Speed data minus for ports 1 through 7.  2012 - 2015 Microchip Technology Inc. USB5537B TABLE 3-1: USB5537B PIN DESCRIPTIONS (CONTINUED) Symbol Buffer Type Description USB PORT CONTROL PRT_PWR[7:1]/ PRT_CTL[7:1] O12 USB Power Enable Enables power to USB peripheral devices downstream. Note: VBUS I This pin also provides configuration strap functions. See Note 3-1. Upstream VBUS Power Detect This pin can be used to detect the state of the upstream bus power. The device monitors this pin to determine when to assert the internal D+ pullup resistor (signaling a connect event). When designing a detachable hub, this pin should be connected to VBUS on the upstream port via a 2:1 voltage divider. Two 100 k resistors are suggested. For self-powered applications with a permanently attached host, this pin must be connected to a dedicated host control output, or connected to the 3.3 V domain that powers the host (typically VDD33). SPI INTERFACE SPI_CE_N O12 SPI_CLK O12 SPI Enable SPI Clock SPI Serial Data Out SPI_DO O12 The output for the SPI port. Note: SPI_DI I This pin also provides configuration strap functions. See . SPI Serial Data In The SPI data in to the controller from the ROM. This pin has a weak internal pull-down applied at all times to prevent floating. JTAG/OCS INTERFACE JTAG Asynchronous Reset TRST Note: DYNCPDIS_N IPU (Note 3-4) If using the SMBus interface, a pull-up on this signal will enable Legacy Mode, while leaving it unconnected or pulled-down will enable Advanced Mode. Dynamic Charging Port Disable This active-low signal is used to globally disable charging port support. Note: This signal available in -6070 and -6080 versions only UCS1002 SMBus Alert UCS_SMBALERT_N When charging port is enabled and SMBus devices are used, this signal acts as an active-low SMBus alert. JTAG Clock TCK OCS1 I This input is used for JTAG boundary scan and has a weak pull-down. It can be left floating or grounded when not used. If the JTAG is connected, then this signal will be detected high, and the software disables the pull up after reset. Over-Current Sense 1 Input from external current monitor indicating an over-current condition. Note:  2012 - 2015 Microchip Technology Inc. This pin also provides configuration strap functions. See Note 3-3. DS00001682C-page 9 USB5537B TABLE 3-1: USB5537B PIN DESCRIPTIONS (CONTINUED) Symbol Buffer Type Description JTAG TMS TMS Used for JTAG boundary scan. OCS2 I Over-Current Sense 2 Input from external current monitor indicating an over-current condition. Note: This pin also provides configuration strap functions. See Note 3-3. JTAG TDI TDI Used for JTAG boundary scan. OCS3 I Over-Current Sense 3 Input from external current monitor indicating an over-current condition. Note: This pin also provides configuration strap functions. See Note 3-3. JTAG TDO TDO Used for JTAG boundary scan. OCS4 O12 Over-Current Sense 4 Input from external current monitor indicating an over-current condition. Note: This pin also provides configuration strap functions. See Note 3-3. MISC RESET_N IS Reset Input The system uses this active low signal to reset the chip. The active low pulse should be at least 1 s wide. Crystal Input: 25 MHz crystal. XTALIN CLK_IN ICLKx This pin connects to either one terminal of the crystal or to an external 25 MHz clock when a crystal is not used. External Clock Input This pin connects to either one terminal of the crystal or to an external 25 MHz clock when a crystal is not used. XTALOUT OCLKx Crystal Output The clock output, providing a crystal 25 MHz. When an external clock source is used to drive XTALIN/CLKIN, this pin becomes a no connect. TEST IPD Test Pin Treat as a no connect pin or connect to ground. No trace or signal should be routed or attached to this pin. RBIAS I-R USB Transceiver Bias A12.0 k (+/- 1%) resistor is attached from ground to this pin to set the transceiver’s internal bias settings. ATEST A Analog Test Pin This signal is used for testing the chip and must always be connected to ground. SM_CLK I/O12 SMBus Clock SM_DAT I/O12 SMBus Data Pin Note: DS00001682C-page 10 This pin is MUXed with PRT_CTRL5  2012 - 2015 Microchip Technology Inc. USB5537B TABLE 3-1: USB5537B PIN DESCRIPTIONS (CONTINUED) Symbol Buffer Type Description DIGITAL AND POWER (12 PINS AND 1 GROUND PAD) (4) VDD33 3.3 V Power (8) VDD12 1.25 V Power Ground Pad VSS This exposed pad is the device’s only connection to VSS and the primary thermal conduction path. Connect to an appropriate via field. Note 3-1 The PRT_PWR[4:1] pins can optionally provide additional configuration strap functions to enable/disable the associated port and configure its battery charging capabilities. Configuration strap values are latched on device reset. Table 3-2 details the functions associated with the various strap settings. Strapping features are enabled by default and can be optionally disabled via the Pro-Touch software programming tool. For additional information on the Pro-Touch programming tool, contact your local sales representative. Strapping functions are not supported for designs that support OCS but not power switching. TABLE 3-2: PRT_PWR[4:1] CONFIGURATION STRAP STATES PRT_PWR[4:1] Strap Setting Port State Battery Charging No Pull-Up or Pull-Down Enabled Disabled Pull-Down: