USB5734
4-Port SS/HS USB Controller Hub
Highlights
Key Benefits
• USB Hub Feature Controller IC with 4 USB 3.2
Gen 1 / USB 2.0 downstream ports
• USB-IF Battery Charger revision 1.2 support on
up & downstream ports (DCP, CDP, SDP)
• FlexConnect: Downstream port able to swap with
upstream port, allowing master capable devices
to control other devices on the hub
• USB to I2C/UART/SPI/GPIO bridge endpoint support
• USB Link Power Management (LPM) support
• Enhanced OEM configuration options available
through either OTP or SPI ROM
• USB-IF certified (TID 330000076), supporting latest Engineering Change Notices for compliance
with USB-IF logo testing for new USB Type-C®
industry initiative
- Header Packet Timer (TD7.9, TD7.11, TD7.26)
- Power Management Timer (TD7.18, TD7.20, TD7.23)
- Unacknowledged Connect and Remote
Wake Test Failure (TD10.25)
• Available in 64-pin (9 x 9 mm) VQFN lead-free,
RoHS compliant package
• Commercial and industrial grade temperature
support
• Configuration Straps: Predefined configuration of
system level functions including GPIOs
• USB 3.2 Gen 1 compliant 5 Gbps, 480 Mbps,
12 Mbps and 1.5 Mbps operation
Target Applications
•
•
•
•
•
Standalone USB Hubs
Laptop Docks
PC Motherboards
PC Monitor Docks
Multi-function USB 3.2 Gen 1 Peripherals
- 5 V tolerant USB 2.0 pins
- 1.32 V tolerant USB 3.2 Gen 1 pins
- Integrated termination & pull-up/pull-down resistors
• Supports per port battery charging of most popular battery powered devices
- USB-IF Battery Charging rev. 1.2 support
(DCP, CDP, SDP)
- Apple portable product charger emulation
- Chinese YD/T 1591-2006 charger emulation
- Chinese YD/T 1591-2009 charger emulation
- European Union universal mobile charger support
- Support for Microchip USC100x family of battery
charging controllers
- Supports additional portable devices
• Smart port controller operation
- Firmware handling of companion port controllers
• On-chip microcontroller
- Manages I/Os, VBUS, and other signals
• 8 KB RAM, 64 KB ROM
• 8 KB One Time Programmable (OTP) ROM
- Includes on-chip charge pump
• Configuration programming via OTP ROM, SPI
ROM, or SMBus
• PortSwap
- Configurable differential intro-pair signal swapping
• PHYBoost™
- Programmable USB transceiver drive strength for
recovering signal integrity
• VariSense™
- Programmable USB receiver sensitivity
• Compatible with Microsoft Windows 8, 7, XP,
Apple OS X 10.4+, and Linux hub drivers
• Optimized for low-power operation and
low thermal dissipation
• Package
- 64-pin VQFN (9 x 9 mm)
• Environmental
- 3 kV HBM JESD22-A114F ESD protection
- Commercial temperature range (0°C to +70°C)
- Industrial temperature range (-40°C to +85°C)
* USB Type-C® and USB-C® are trademarks of USB Implementation Forum.
2015-2020 Microchip Technology Inc.
DS00001854H-page 1
USB5734
TO OUR VALUED CUSTOMERS
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The last character of the literature number is the version number, (e.g., DS30000000A is version A of document DS30000000).
Errata
An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the
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To determine if an errata sheet exists for a particular device, please check with one of the following:
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DS00001854H-page 2
2015-2020 Microchip Technology Inc.
USB5734
Table of Contents
1.0 Preface ............................................................................................................................................................................................ 4
2.0 Introduction ..................................................................................................................................................................................... 6
3.0 Pin Description and Configuration .................................................................................................................................................. 8
4.0 Device Connections ...................................................................................................................................................................... 26
5.0 Modes of Operation ...................................................................................................................................................................... 28
6.0 Device Configuration ..................................................................................................................................................................... 31
7.0 Device Interfaces .......................................................................................................................................................................... 33
8.0 Functional Descriptions ................................................................................................................................................................. 35
9.0 Compliance Update ...................................................................................................................................................................... 41
10.0 Operational Characteristics ......................................................................................................................................................... 42
11.0 Package Information ................................................................................................................................................................... 51
2015-2020 Microchip Technology Inc.
DS00001854H-page 3
USB5734
1.0
PREFACE
1.1
General Terms
TABLE 1-1:
GENERAL TERMS
Term
Description
ADC
Analog-to-Digital Converter
Byte
8 bits
CDC
Communication Device Class
CSR
Control and Status Registers
DWORD
32 bits
EOP
End of Packet
EP
Endpoint
FIFO
First In First Out buffer
FS
Full-Speed
FSM
Finite State Machine
GPIO
General Purpose I/O
HS
Hi-Speed
HSOS
High Speed Over Sampling
Hub Feature Controller
The Hub Feature Controller, sometimes called a Hub Controller for short is the internal
processor used to enable the unique features of the USB Controller Hub. This is not to
be confused with the USB Hub Controller that is used to communicate the hub status
back to the Host during a USB session.
I2C
Inter-Integrated Circuit
LS
Low-Speed
lsb
Least Significant Bit
LSB
Least Significant Byte
msb
Most Significant Bit
MSB
Most Significant Byte
N/A
Not Applicable
NC
No Connect
OTP
One Time Programmable
PCB
Printed Circuit Board
PCS
Physical Coding Sublayer
PHY
Physical Layer
PLL
Phase Lock Loop
RESERVED
Refers to a reserved bit field or address. Unless otherwise noted, reserved bits must
always be zero for write operations. Unless otherwise noted, values are not guaranteed when reading reserved bits. Unless otherwise noted, do not read or write to
reserved addresses.
SDK
Software Development Kit
SMBus
System Management Bus
UUID
Universally Unique IDentifier
WORD
16 bits
DS00001854H-page 4
2015-2020 Microchip Technology Inc.
USB5734
1.2
1.
2.
3.
4.
5.
Reference Documents
UNICODE UTF-16LE For String Descriptors USB Engineering Change Notice, December 29th, 2004, http://
www.usb.org
Universal Serial Bus Revision 3.2 Specification, http://www.usb.org/developers/docs/
Battery Charging Specification, Revision 1.2, Dec. 07, 2010, http://www.usb.org
I2C-Bus Specification, Version 1.1, http://www.nxp.com
System Management Bus Specification, Version 1.0, http://smbus.org/specs
2015-2020 Microchip Technology Inc.
DS00001854H-page 5
USB5734
2.0
INTRODUCTION
2.1
General Description
The Microchip USB5734 hub is low-power, OEM configurable, USB 3.2 Gen 1 hub feature controller with 4 downstream
ports and advanced features for embedded USB applications. The USB5734 is fully compliant with the Universal Serial
Bus Revision 3.2 Specification and USB 2.0 Link Power Management Addendum. The USB5734 supports 5 Gbps
SuperSpeed (SS), 480 Mbps Hi-Speed (HS), 12 Mbps Full-Speed (FS), and 1.5 Mbps Low-Speed (LS) USB downstream devices on all enabled downstream ports.
The USB5734 supports the legacy USB speeds (HS/FS/LS) through a dedicated USB 2.0 hub feature controller that is
the culmination of five generations of Microchip hub feature controller design and experience with proven reliability,
interoperability, and device compatibility. The SuperSpeed hub feature controller operates in parallel with the USB 2.0
controller, decoupling the 5 Gbps SS data transfers from bottlenecks due to the slower USB 2.0 traffic.
The USB5734 enables OEMs to configure their system using “Configuration Straps.” These straps simplify the configuration process assigning default values to USB 3.2 Gen 1 ports and GPIOs OEMs can disable ports, enable battery
charging and define GPIO functions as default assignments on power up removing the need for OTP or external SPI
ROM.
The USB5734 supports downstream battery charging. The USB5734 integrated battery charger detection circuitry supports the USB-IF Battery Charging (BC1.2) detection method and most Apple devices. The USB5734 provides the battery charging handshake and supports the following USB-IF BC1.2 charging profiles:
•
•
•
•
DCP: Dedicated Charging Port (Power brick with no data)
CDP: Charging Downstream Port (1.5A with data)
SDP: Standard Downstream Port (0.5A with data)
Custom profiles loaded via SMBus or OTP
The USB5734 provides an additional USB endpoint dedicated for use as a USB to I2C/UART/SPI/GPIO interface, allowing external circuits or devices to be monitored, controlled, or configured via the USB interface. Additionally, the
USB5734 includes many powerful and unique features such as:
FlexConnect, which provides flexible connectivity options. One of the USB5734’s downstream ports can be reconfigured to become the upstream port, allowing master capable devices to control other devices on the hub.
PortSwap, which adds per-port programmability to USB differential-pair pin locations. PortSwap allows direct alignment
of USB signals (D+/D-) to connectors to avoid uneven trace length or crossing of the USB differential signals on the
PCB.
PHYBoost, which provides programmable levels of Hi-Speed USB signal drive strength
in the downstream port transceivers. PHYBoost attempts to restore USB signal integrity
in a compromised system environment. The graphic on the right shows an example of
Hi-Speed USB eye diagrams before and after PHYBoost signal integrity restoration. in
a compromised system environment
VariSense, which controls the USB receiver sensitivity enabling programmable levels of USB signal receive sensitivity.
This capability allows operation in a sub-optimal system environment, such as when a captive USB cable is used.
The USB5734 can be configured for operation through internal default settings. Custom OEM configurations are supported through external SPI ROM or OTP ROM. All port control signal pins are under firmware control in order to allow
for maximum operational flexibility, and are available as GPIOs for customer specific use.
The USB5734 is available in commercial (0°C to +70°C) and industrial (-40°C to +85°C) temperature ranges. An internal
block diagram of the USB5734 is shown in Figure 2-1.
DS00001854H-page 6
2015-2020 Microchip Technology Inc.
2015-2020 Microchip Technology Inc.
RX
TX
USB2.0
PHY
(or Upstream Port via FlexC onnect)
Downstream USB Port 1
SS
PHY
Buffer
Buffer
Buffer
Registers
& Hub I/O
SS
PHY
RX
Buffer
USB2.0
PHY
SS
PHY
RX
Buffer
USB2.0
PHY
Downstream USB Port 3
SS
PHY
TX
Buffer
Downstream RX SS bus
Downstream USB Port 2
SS
PHY
TX
Buffer
Registers
& Hub I/O
APB Bus
8k OTP
Reset & 8051
Boot Seq.
Xdata-toAPB Bridge
HS/FS/LS Routing Logic
VBUS
Control
XData
USB 2.0 Hub Controller
8k RAM
64k ROM
Embedded
8051 µC
Downstream TX SS bus
USB 3.2 Gen 1
Hub Controller
Buffer
TX
RX
Com mon
USB 2.0
Block
Flex
SS Flex SS Flex
& PLL
PHY
PHY
PHY
SS
PHY
RX
Buffer
USB2.0
PHY
Downstream USB Port 4
SS
PHY
TX
Buffer
Programmable
Functions
UART
SPI/SMBus
PROG_FUNC[7:1]
SPI/
SMBus/
UART
FIGURE 2-1:
SS
PHY
Upstream USB Port 0
(or Downstream Port 1 via FlexConnect)
USB5734
INTERNAL BLOCK DIAGRAM
DS00001854H-page 7
USB5734
3.0
PIN DESCRIPTION AND CONFIGURATION
3.1
Pin Assignments
RBIAS
VDD33
XTALI/CLK_IN
XTALO
ATEST
USB3UP_RXDM
USB3UP_RXDP
VDD12
USB3UP_TXDM
USB3UP_TXDP
USB2UP_DM
USB2UP_DP
VDD33
VDD12
PROG_FUNC1
PROG_FUNC6
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
64-VQFN PIN ASSIGNMENTS
64
FIGURE 3-1:
CFG_STRAP
1
48
RESET_N
USB2DN_DP1/PRT_DIS_P1
2
47
PROG_FUNC5
USB2DN_DM1/PRT_DIS_M1
3
46
PROG_FUNC4
USB3DN_TXDP1
4
45
SPI_CE_N/GPIO7/CFG_NON_REM
USB3DN_TXDM1
5
44
SPI_DI/GPIO9/CFG_BC_EN
VDD12
6
43
SPI_DO/UART_TX/GPIO5/I2C_SLV_CFG1
USB3DN_RXDP1
7
42
SPI_CLK/UART_RX/GPIO4/I2C_SLV_CFG0
41
VBUS_DET/GPIO16
40
PROG_FUNC3
PROG_FUNC2
USB5734
USB3DN_RXDM1
8
USB2DN_DP2/PRT_DIS_P2
9
USB2DN_DM2/PRT_DIS_M2
10
39
USB3DN_TXDP2
11
38
PRT_CTL1
USB3DN_TXDM2
12
37
PRT_CTL2
36
PRT_CTL3
VDD12
13
USB3DN_RXDP2
14
USB3DN_RXDM2
PROG_FUNC7
64 -VQFN
(T o p V ie w)
VSS
35
VDD12
15
34
PRT_CTL4/GANG_PWR
16
33
VDD33
28
29
30
31
USB3DN_TXDP4
USB3DN_TXDM4
VDD12
USB3DN_RXDP4
32
27
USB2DN_DM4/PRT_DIS_M4
USB3DN_RXDM4
26
24
USB3DN_RXDP3
25
23
VDD12
USB3DN_RXDM3
22
USB2DN_DP4/PRT_DIS_P4
21
20
USB2DN_DM3/PRT_DIS_M3
USB3DN_TXDP3
19
USB2DN_DP3/PRT_DIS_P3
USB3DN_TXDM3
18
17
VDD12
VDD33
(Connect exposed pad to ground with a via field)
Note: Exposed pad (VSS) on bottom of package must be connected to ground with a via
field.
Note 1: Configuration straps are identified by an underlined symbol name. Signals that function as configurations
traps must be augmented with an external resistor when connected to a load. Refer to Section 3.4, "Configuration Straps and Programmable Functions" for additional information.
DS00001854H-page 8
2015-2020 Microchip Technology Inc.
USB5734
Table 3-1 details the package pin assignments in table format.
TABLE 3-1:
64-VQFN PIN ASSIGNMENTS
Pin
Num.
Pin Name
Reset
State
Pin
Num.
Pin Name
Reset
State
1
CFG_STRAP
Z
33
VDD33
A/P
2
USB2DN_DP1/PRT_DIS_P1
PD-15k
34
PRT_CTL4/GANG_PWR
PD-50k
3
USB2DN_DM1/PRT_DIS_M1
PD-15k
35
VDD12
A/P
4
USB3DN_TXDP1
Z
36
PRT_CTL3
PD-50k
5
USB3DN_TXDM1
Z
37
PRT_CTL2
PD-50k
6
VDD12
A/P
38
PRT_CTL1
PD-50k
7
USB3DN_RXDP1
Z
39
PROG_FUNC2
Z
8
USB3DN_RXDM1
Z
40
PROG_FUNC3
Z
9
USB2DN_DP2/PRT_DIS_P2
PD-15k
41
VBUS_DET/GPIO16
Z
10
USB2DN_DM2/PRT_DIS_M2
PD-15k
42
SPI_CLK/UART_RX/GPIO4/I2C_SLV_CFG0
Z
11
USB3DN_TXDP2
Z
43
SPI_DO/UART_TX/GPIO5/I2C_SLV_CFG1
PD-50k
12
USB3DN_TXDM2
Z
44
SPI_DI/GPIO9/CFG_BC_EN
Z
13
VDD12
A/P
45
SPI_CE_N/GPIO7/CFG_NON_REM
PU-50k
14
USB3DN_RXDP2
Z
46
PROG_FUNC4
Z
15
USB3DN_RXDM2
Z
47
PROG_FUNC5
Z
16
PROG_FUNC7
Z
48
RESET_N
R
17
VDD12
A/P
49
PROG_FUNC6
Z
18
VDD33
A/P
50
PROG_FUNC1
Z
19
USB2DN_DP3/PRT_DIS_P3
PD-15k
51
VDD12
A/P
20
USB2DN_DM3/PRT_DIS_M3
PD-15k
52
VDD33
A/P
21
USB3DN_TXDP3
Z
53
USB2UP_DP
PD-1M
22
USB3DN_TXDM3
Z
54
USB2UP_DM
PD-1M
23
VDD12
A/P
55
USB3UP_TXDP
Z
24
USB3DN_RXDP3
Z
56
USB3UP_TXDM
Z
25
USB3DN_RXDM3
Z
57
VDD12
A/P
26
USB2DN_DP4/PRT_DIS_P4
PD-15k
58
USB3UP_RXDP
Z
27
USB2DN_DM4/PRT_DIS_M4
PD-15k
59
USB3UP_RXDM
Z
28
USB3DN_TXDP4
Z
60
ATEST
Z
29
USB3DN_TXDM4
Z
61
XTALO
A/P
30
VDD12
A/P
62
XTALI/CLK_IN
A/P
31
USB3DN_RXDP4
Z
63
VDD33
A/P
32
USB3DN_RXDM4
Z
64
RBIAS
A/P
The pin reset state definitions are detailed in Table 3-2.
2015-2020 Microchip Technology Inc.
DS00001854H-page 9
USB5734
TABLE 3-2:
PIN RESET STATE LEGEND
Symbol
Description
A/P
Analog/Power Input
R
Reset Control Input
Z
Hardware disables output driver (high impedance)
PU-50k
Hardware enables internal 50kΩ pull-up
PD-50k
Hardware enables internal 50kΩ pull-down
PD-15k
Hardware enables internal 15kΩ pull-down
PD-1M
Hardware enables internal 1M pull-down
3.2
Pin Descriptions
This section contains descriptions of the various USB5734 pins. This pin descriptions have been broken into functional
groups as follows:
•
•
•
•
•
•
•
USB 3.2 Gen 1 Pin Descriptions
USB 2.0 Pin Descriptions
USB Port Control Pin Descriptions
SPI/UART Pin Descriptions
Programmable Function Pin Descriptions
Miscellaneous Pin Descriptions
Power and Ground Pin Descriptions
The “_N” symbol in the signal name indicates that the active, or asserted, state occurs when the signal is at a low voltage
level. For example, RESET_N indicates that the reset signal is active low. When “_N” is not present after the signal
name, the signal is asserted when at the high voltage level.
The terms assertion and negation are used exclusively. This is done to avoid confusion when working with a mixture of
“active low” and “Active high” signals. The term assert, or assertion, indicates that a signal is active, independent of
whether that level is represented by a high or low voltage. The term negate, or negation, indicates that a signal is inactive.
Note:
The buffer type for each signal is indicated in the “Buffer Type” column of the pin description tables. A
description of the buffer types is provided in Section 3.3, "Buffer Types," on page 15.
For additional information on configuration straps and configurable pins, refer to Section 3.4, "Configuration
Straps and Programmable Functions".
DS00001854H-page 10
2015-2020 Microchip Technology Inc.
USB5734
TABLE 3-3:
USB 3.2 GEN 1 PIN DESCRIPTIONS
Num
Pins
Symbol
Buffer
Type
1
USB3UP_TXDP
IO-U
USB 3.2 Gen 1 upstream SuperSpeed transmit data plus.
1
USB3UP_TXDM
IO-U
USB 3.2 Gen 1 upstream SuperSpeed transmit data minus.
1
USB3UP_RXDP
IO-U
USB 3.2 Gen 1 upstream SuperSpeed receive data plus.
1
USB3UP_RXDM
IO-U
USB 3.2 Gen 1 upstream SuperSpeed receive data minus.
4
USBDN_TXDP[4:1]
IO-U
4
USBDN_TXDM[4:1]
IO-U
Description
USB 3.2 Gen 1 downstream ports 4-1 SuperSpeed transmit data plus.
Note:
USB 3.2 Gen 1 downstream ports 4-1 SuperSpeed transmit data
minus.
Note:
4
USBDN_RXDP[4:1]
IO-U
4
USBDN_RXDM[4:1]
IO-U
Num
Pins
If unused, leave floating.
USB 3.2 Gen 1 downstream ports 4-1 SuperSpeed receive data plus.
Note:
If unused, leave floating.
USB 3.2 Gen 1 downstream ports 4-1 SuperSpeed receive data
minus.
Note:
TABLE 3-4:
If unused, leave floating.
If unused, leave floating.
USB 2.0 PIN DESCRIPTIONS
Symbol
Buffer
Type
1
USB2UP_DP
IO-U
1
USB2UP_DM
IO-U
USB 2.0 upstream data minus (D-).
USB2DN_DP[4:1]
IO-U
USB 2.0 downstream ports 4-1 data plus (D+).
Description
USB 2.0 upstream data plus (D+).
Port 4-1 D+ Disable Configuration Strap.
4
PRT_DIS_P[4:1]
I
These configuration straps are used in conjunction with the corresponding PRT_DIS_M[4:1] straps to disable the related port (4-1).
Refer to Section 3.4.2, "Port Disable Configuration (PRT_DIS_P[4:1] /
PRT_DIS_M[4:1])" for more information.
See Note 2.
USB2DN_DM[4:1]
IO-U
USB 2.0 downstream ports 4-1 data minus (D-).
Port 4-1 D- Disable Configuration Strap.
4
PRT_DIS_M[4:1]
I
These configuration straps are used in conjunction with the corresponding PRT_DIS_P[4:1] straps to disable the related port (4-1).
Refer to Section 3.4.2, "Port Disable Configuration (PRT_DIS_P[4:1] /
PRT_DIS_M[4:1])" for more information.
See Note 2.
2015-2020 Microchip Technology Inc.
DS00001854H-page 11
USB5734
TABLE 3-4:
Num
Pins
USB 2.0 PIN DESCRIPTIONS (CONTINUED)
Symbol
Buffer
Type
Description
This signal detects the state of the upstream bus power.
When designing a detachable hub, this pin must be connected to the
VBUS power pin of the upstream USB port through a resistor divider
(50 k by 100 k) to provide 3.3 V.
1
VBUS_DET
IS
For self-powered applications with a permanently attached host, this
pin must be connected to either 3.3 V or 5.0 V through a resistor
divider to provide 3.3 V.
In embedded applications, VBUS_DET may be controlled (toggled)
when the host desires to renegotiate a connection without requiring a
full reset of the device.
GPIO16
I/O6
General purpose input/output 16.
Note 2: Configuration strap values are latched on Power-On Reset (POR) and the rising edge of RESET_N (external
chip reset). Configuration straps are identified by an underlined symbol name. Signals that function as configurations traps must be augmented with an external resistor when connected to a load. Refer to Section
3.4, "Configuration Straps and Programmable Functions" for additional information.
TABLE 3-5:
Num
Pins
USB PORT CONTROL PIN DESCRIPTIONS
Symbol
Buffer
Type
Description
Port 1 Power Enable / Overcurrent Sense.
1
PRT_CTL1
I
(PU)
Note:
If unused, leave floating.
As an output, this signal is an active high control signal used to enable
power to the downstream port 1. As an input, this signal indicates an
overcurrent condition from an external current monitor on USB port 1.
Port 2 Power Enable / Overcurrent Sense.
1
PRT_CTL2
I
(PU)
Note:
If unused, leave floating.
As an output, this signal is an active high control signal used to enable
power to the downstream port 2. As an input, this signal indicates an
overcurrent condition from an external current monitor on USB port 2.
Port 3 Power Enable / Overcurrent Sense.
1
PRT_CTL3
I
(PU)
Note:
If unused, leave floating.
As an output, this signal is an active high control signal used to enable
power to the downstream port 3. As an input, this signal indicates an
overcurrent condition from an external current monitor on USB port 3.
Port 4 Power Enable / Overcurrent Sense.
PRT_CTL4
I
(PU)
GANG_PWR
I
(PU)
1
DS00001854H-page 12
Note:
If unused, leave floating.
As an output, this signal is an active high control signal used to enable
power to the downstream port 4. As an input, this signal indicates an
overcurrent condition from an external current monitor on USB port 4.
When pulled high enables gang mode. Gang power pin when used in
gang mode.
2015-2020 Microchip Technology Inc.
USB5734
TABLE 3-6:
Num
Pins
SPI/UART PIN DESCRIPTIONS
Symbol
Buffer
Type
SPI_CE_N
O12
GPIO7
I/O12
Description
Active low SPI chip enable output.
General purpose input/output 7.
Non-Removable Port Configuration Strap.
1
CFG_NON_REM
I
This configuration strap is used to configure the number of nonremovable ports. Refer to Section 3.4.3, "Non-Removable Port Configuration (CFG_NON_REM)" for more information.
See Note 3.
SPI_CLK
1
O6
UART_RX
I
GPIO4
I/O6
SPI clock output to the serial ROM, when configured for SPI operation.
UART receive pin, when configured for UART operation.
General purpose input/output 4.
I2C Slave 0 Configuration Strap.
I2C_SLV_CFG0
I
This configuration strap is used to configure I2C controller 0. Refer to
Section 3.4.1, "SPI/SMBus/I2C/UART Configuration
(I2C_SLV_CFG[1:0])" for additional information.
SPI_DO
O6
SPI data output, when configured for SPI operation.
UART_TX
O12
UART transmit pin, when configured for UART operation.
GPIO5
I/O6
General purpose input/output 5.
I2C Slave 1 Configuration Strap.
1
I2C_SLV_CFG1
I
SPI_DI
IS
GPIO9
I/O12
This configuration strap is used to configure I2C controller 1. Refer to
Section 3.4.1, "SPI/SMBus/I2C/UART Configuration
(I2C_SLV_CFG[1:0])" for additional information.
SPI data input, when configured for SPI operation.
General purpose input/output 9.
Battery Charging Configuration Strap.
1
CFG_BC_EN
I
This configuration strap is used to enable battery charging. Refer to
Section 3.4.4, "Battery Charging Configuration (CFG_BC_EN)" for
more information.
See Note 3.
Note 3: Configuration strap values are latched on Power-On Reset (POR) and the rising edge of RESET_N (external
chip reset). Configuration straps are identified by an underlined symbol name. Signals that function as configurations traps must be augmented with an external resistor when connected to a load. Refer to Section
3.4, "Configuration Straps and Programmable Functions" for additional information.
2015-2020 Microchip Technology Inc.
DS00001854H-page 13
USB5734
TABLE 3-7:
Num
Pins
PROGRAMMABLE FUNCTION PIN DESCRIPTIONS
Symbol
Buffer
Type
Description
Programmable function pins 7-1.
7
PROG_FUNC[7:1]
Note 4
The functions of these pins are configured via the CFG_STRAP pin.
Refer to Section 3.4.5, "Device Mode / PROG_FUNC[7:1] Configuration (CFG_STRAP)" for additional information.
Device Mode Configuration Strap.
1
CFG_STRAP
I
This configuration strap is used to set the device mode. Refer to Section 3.4.5, "Device Mode / PROG_FUNC[7:1] Configuration
(CFG_STRAP)" for more information.
See Note 5.
Note 4: The PROG_FUNC2 buffer type is I/O6. The PROG_FUNC7 buffer type is I/O10. All other PROG_FUNCx
pins have a buffer type of I/O12.
Note 5: Configuration strap values are latched on Power-On Reset (POR) and the rising edge of RESET_N (external
chip reset). Configuration straps are identified by an underlined symbol name. Signals that function as configurations traps must be augmented with an external resistor when connected to a load. Refer to Section
3.4, "Configuration Straps and Programmable Functions" for additional information.
TABLE 3-8:
MISCELLANEOUS PIN DESCRIPTIONS
Num
Pins
Symbol
Buffer
Type
1
RESET_N
IS
XTALI
ICLK
1
1
1
Description
The RESET_N pin puts the device into Reset Mode.
External 25 MHz crystal input
External reference clock input.
CLK_IN
ICLK
XTALO
OCLK
RBIAS
AI
The device may alternatively be driven by a single-ended clock oscillator. When this method is used, XTALO should be left unconnected.
External 25 MHz crystal output
A 12.0 k (+/- 1%) resistor is attached from ground to this pin to set
the transceiver’s internal bias settings.
Analog test pin.
1
ATEST
DS00001854H-page 14
AI
This signal is used for test purposes and must always be connected to
ground.
2015-2020 Microchip Technology Inc.
USB5734
TABLE 3-9:
Num
Pins
POWER AND GROUND PIN DESCRIPTIONS
Buffer
Type
Symbol
Description
+3.3 V power and internal regulator input
4
P
VDD33
Refer to Section 4.1, "Power Connections" for power connection information.
+1.2 V core power
8
P
VDD12
Refer to Section 4.1, "Power Connections" for power connection information.
Common ground.
Pad
3.3
P
VSS
This exposed pad must be connected to the ground plane with a via
array.
Buffer Types
TABLE 3-10:
BUFFER TYPES
Buffer Type
I
Input
IS
Schmitt-triggered input
O6
Output with 6 mA sink and 6 mA source
O10
Output with 10 mA sink and 10 mA source
O12
Output with 12 mA sink and 12 mA source
OD12
Open-drain output with 12 mA sink
PU
50 µA (typical) internal pull-up. Unless otherwise noted in the pin description, internal pullups are always enabled.
Internal pull-up resistors prevent unconnected inputs from floating. Do not rely on internal
resistors to drive signals external to the device. When connected to a load that must be
pulled high, an external resistor must be added.
PD
50 µA (typical) internal pull-down. Unless otherwise noted in the pin description, internal
pull-downs are always enabled.
Internal pull-down resistors prevent unconnected inputs from floating. Do not rely on internal
resistors to drive signals external to the device. When connected to a load that must be
pulled low, an external resistor must be added.
IO-U
AI
Analog input/output as defined in USB specification
Analog input
ICLK
Crystal oscillator input pin
OCLK
Crystal oscillator output pin
P
Note:
Description
Power pin
Refer to Section 10.5, "DC Specifications" for individual buffer DC electrical characteristics.
2015-2020 Microchip Technology Inc.
DS00001854H-page 15
USB5734
3.4
Configuration Straps and Programmable Functions
Configuration straps are multi-function pins that are used during Power-On Reset (POR) or external chip reset
(RESET_N) to determine the default configuration of a particular feature. The state of the signal is latched following deassertion of the reset. Configuration straps are identified by an underlined symbol name. This section details the various
device configuration straps and associated programmable pin functions.
Note:
3.4.1
The system designer must guarantee that configuration straps meet the timing requirements specified in
Section 10.6.2, "Power-On and Configuration Strap Timing," on page 46 and Section 10.6.3, "Reset and
Configuration Strap Timing," on page 47. If configuration straps are not at the correct voltage level prior to
being latched, the device may capture incorrect strap values.
SPI/SMBUS/I2C/UART CONFIGURATION (I2C_SLV_CFG[1:0])
The SPI/SMBus/I2C//UART pins can be configured into one of four functional modes:
•
•
•
•
SPI Mode
SMBus Slave Enable Mode
I2C Bridging Mode
UART Mode
If 10 k pull-up resistors are detected on SPI_DO and SPI_CLK, the SPI/SMBus/I2C/UART pins are configured into
SMBus Slave Enable Mode. If a 10 k pull-down resistor is detected on SPI_DO, the SPI/SMBus/I2C/UART pins are
configured into UART Mode. If no pull-ups or pull-downs are detected on SPI_DO and SPI_CLK, the SPI/SMBus/I2C/
UART pins are first configured into SPI Mode. If no valid SPI ROM is detected, the SPI/SMBus/I2C/UART pins are configured into I2C Bridging Mode. The strap settings for these supported modes are detailed in Table 3-11. The individual
pin function assignments for each mode are detailed in Table 3-12. For additional device connection information, refer
to Section 4.0, "Device Connections".
Note:
The following interfaces cannot be used simultaneously:
• UART and SMBus Slave
• UART and SPI
• SMBus Slave and I2C Bridging interface
TABLE 3-11:
SPI/SMBUS/I2C/UART MODE CONFIGURATION SETTINGS
Pin
SPI Mode
(Note 6)
SMBus Slave Enable
Mode (Note 7)
I2C Bridging
Mode (Note 8)
UART
Mode
43
(SPI_DO)
No pull-up/down
10 k pull-up
No pull-up/down
10 k pull-down
42
(SPI_CLK)
No pull-up/down
10 k pull-up
No pull-up/down
No pull-up/down
Note 6: In order to use the SPI interface, an SPI ROM containing a valid signature of 2DFU (device firmware
upgrade) beginning at address 0xFFFA must be present. Refer to Section 7.1, "SPI Master Interface" for
additional information.
Note 7: In order to use the SMBus slave interface, the SPI_DO and SPI_CLK pins must be configured for SMBus
Slave Enable Mode and CFG_STRAP must be configured to Configuration 1, 2, 3, or 6, which programs the
PROG_FUNC4 and PROG_FUNC5 pins as SMDAT and SMCLK, respectively. When in Configuration 4 or
5, the SMBus slave interface is not usable. Refer to Section 3.4.5, "Device Mode / PROG_FUNC[7:1] Configuration (CFG_STRAP)" for additional information.
Note 8: In order to use the I2C Bridging interface, the SPI_DO and SPI_CLK pins must be configured for I2C Bridging Mode and CFG_STRAP must be configured to Configuration 1, 2, 3, or 6, which programs the PROG_FUNC4 and PROG_FUNC5 pins as SMDAT and SMCLK, respectively. When in Configuration 4 or 5, the
I2C Bridging interface is not usable. Additional hub register configuration is also required. Refer to Section
3.4.5, "Device Mode / PROG_FUNC[7:1] Configuration (CFG_STRAP)" and Section 7.3, "I2C Bridge Interface" for additional information.
DS00001854H-page 16
2015-2020 Microchip Technology Inc.
USB5734
TABLE 3-12:
SPI/SMBUS/I2C/UART MODE PIN ASSIGNMENTS
Pin
SPI
Mode
SMBus Slave Enable
Mode
I2C Bridging
Mode
UART
Mode
45
SPI_CE_N
CFG_NON_REM
CFG_NON_REM
CFG_NON_REM
44
SPI_DI
CFG_BC_EN
CFG_BC_EN
CFG_BC_EN
43
SPI_DO
I2C_SLV_CFG1
-
UART_TX
42
SPI_CLK
I2C_SLV_CFG0
-
UART_RX
3.4.2
PORT DISABLE CONFIGURATION (PRT_DIS_P[4:1] / PRT_DIS_M[4:1])
The PRT_DIS_P[4:1] and PRT_DIS_M[4:1] configuration straps are used in conjunction to disable the related port (4-1).
For PRT_DIS_Px (where x is the corresponding port 4-1):
0 = Port x D+ Enabled
1 = Port x D+ Disabled
For PRT_DIS_Mx (where x is the corresponding port 4-1):
0 = Port x D- Enabled
1 = Port x D- Disabled
Note:
3.4.3
Both PRT_DIS_Px and PRT_DIS_Mx (where x is the corresponding port) must be tied to 3.3 V to disable
the associated downstream port. Disabling the USB 2.0 port will also disable the corresponding USB 3.2
Gen 1 port.
NON-REMOVABLE PORT CONFIGURATION (CFG_NON_REM)
The CFG_NON_REM configuration strap is used to configure the non-removable port settings of the device to one of
five settings. These modes are selected by the configuration of an external resistor on the CFG_NON_REM pin. The
resistor options are a 200 kΩ pull-down, 200 kΩ pull-up, 10 kΩ pull-down, 10 kΩ pull-up, and 10 Ω pull-down, as shown
in Table 3-13.
TABLE 3-13:
CFG_NON_REM RESISTOR ENCODING
CFG_NON_REM Resistor Value
200 kΩ Pull-Down
Setting
All ports removable
200 kΩ Pull-Up
Port 1 non-removable
10 kΩ Pull-Down
Port 1, 2 non-removable
10 kΩ Pull-Up
Port 1, 2, 3, non-removable
10 Ω Pull-Down
Port 1, 2, 3, 4 non-removable
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DS00001854H-page 17
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3.4.4
BATTERY CHARGING CONFIGURATION (CFG_BC_EN)
The CFG_BC_EN configuration strap is used to configure the battery charging port settings of the device to one of five
settings. These modes are selected by the configuration of an external resistor on the CFG_BC_EN pin. The resistor
options are a 200 kΩ pull-down, 200 kΩ pull-up, 10 kΩ pull-down, 10 kΩ pull-up, and 10 Ω pull-down, as shown in
Table 3-14.
TABLE 3-14:
CFG_BC_EN RESISTOR ENCODING
CFG_BC_EN Resistor Value
Setting
200 kΩ Pull-Down
No battery charging
200 kΩ Pull-Up
Port 1 battery charging
10 kΩ Pull-Down
Port 1, 2 battery charging
10 kΩ Pull-Up
Port 1, 2, 3, battery charging
10 Ω Pull-Down
Port 1, 2, 3, 4 battery charging
3.4.5
DEVICE MODE / PROG_FUNC[7:1] CONFIGURATION (CFG_STRAP)
The CFG_STRAP is used to configure the programmable function pins (PROG_FUNC[7:1]) into one of six modes.
These modes are selected by the configuration of an external resistor on the CFG_STRAP pin. The resistor options are
a 200 kΩ pull-down, 200 kΩ pull-up, 10 kΩ pull-down, 10 kΩ pull-up, 10 Ω pull-down, and 10 Ω pull-up, as shown in
Table 3-15. For details on each device mode, including pin assignments, refer to the following subsections.
TABLE 3-15:
CFG_STRAP RESISTOR ENCODING
CFG_STRAP Resistor Value
Mode
200 kΩ Pull-Down
Configuration 1 - Mixed Mode
200 kΩ Pull-Up
Configuration 2 - FlexConnect Mode
10 kΩ Pull-Down
Configuration 3 - Speed Indicator Mode
10 kΩ Pull-Up
Configuration 4 - GPIO Mode (Reserved)
10 Ω Pull-Down
Configuration 5 - Battery Charging / Power Delivery Indicator Mode
10 Ω Pull-Up
Configuration 6 - Full UART Mode
DS00001854H-page 18
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USB5734
3.4.5.1
Configuration 1 - Mixed Mode
When the CFG_STRAP is configured to this mode, the programmable function pins (PROG_FUNC[7:1]) are set to provide an SMBus/I2C interface, 3 GPIOs, and FlexConnect capabilities. Table 3-16 details the PROG_FUNC[7:1] pin
assignments in this mode.
TABLE 3-16:
CONFIGURATION 1 PROG_FUNC[7:1] FUNCTION ASSIGNMENT
Pin
Function
Buffer
Type
PROG_FUNC1
GPIO1
I/O12
General Purpose Input/Output 1
PROG_FUNC2
GPIO2
I/O6
General Purpose Input/Output 2
Description
PROG_FUNC3
GPIO3
I/O12
General Purpose Input/Output 3
PROG_FUNC4
SMDAT
OD12
SMBus/I2C Data
The SMBus/I2C interface acts as SMBus slave or I2C bridge
dependent on the device configuration. Refer to Section 3.4.1,
"SPI/SMBus/I2C/UART Configuration (I2C_SLV_CFG[1:0])".
PROG_FUNC5
SMCLK
OD12
SMBus/I2C Clock
The SMBus/I2C interface acts as SMBus slave or I2C bridge
dependent on the device configuration. Refer to Section 3.4.1,
"SPI/SMBus/I2C/UART Configuration (I2C_SLV_CFG[1:0])".
PROG_FUNC6
FLEXCMD
IS
FlexConnect Control
0: Normal Operation (Port 0 upstream, Port 1 downstream)
1: Flex Operation (Port 1 upstream, Port 0 downstream)
Note:
PROG_FUNC7
USB2_SUSP_IND
O10
USB2.0 Suspend Indicator
USB2_SUSP_IND can be used as a sideband remote wakeup
signal for the host when in USB2.0 suspend.
Note:
2015-2020 Microchip Technology Inc.
Refer to Section 8.2, "FlexConnect" for additional
information.
Refer to Section 8.5, "Remote Wakeup Indicator"
for additional information.
DS00001854H-page 19
USB5734
3.4.5.2
Configuration 2 - FlexConnect Mode
When the CFG_STRAP is configured to this mode, the programmable function pins (PROG_FUNC[7:1]) are set to provide FlexConnect, an SMBus/I2C interface, and other additional features. Table 3-17 details the PROG_FUNC[7:1] pin
assignments in this mode.
TABLE 3-17:
CONFIGURATION 2 PROG_FUNC[7:1] FUNCTION ASSIGNMENT
Pin
Function
Buffer
Type
PROG_FUNC1
HOST_TYPE0
O12
Description
Port 0 USB Host Type
Tri-state: No USB host detected on Port 0
0: USB 3.2 Gen 1 Host detected on Port 0
1: USB 2.0 or USB 1.1 Host detected on Port 0
A USB 2.0 Host is considered detected when the USB 2.0 hub
address register holds a non-zero value. A USB 3.2 Gen 1
Host is considered detected when the USB 3.2 Gen 1 hub
address register holds a non-zero value.
PROG_FUNC2
HOST_TYPE1
O6
Port 1 USB Host Type
Tri-state: No USB host detected on Port 1
0: USB 3.2 Gen 1 Host detected on Port 1
1: USB 2.0 or USB 1.1 Host detected on Port 1
A USB 2.0 Host is considered detected when the USB 2.0 hub
address register holds a non-zero value. A USB 3.2 Gen 1
Host is considered detected when the USB 3.2 Gen 1 hub
address register holds a non-zero value.
PROG_FUNC3
FLEX_STATE_N
O12
FlexConnect State Compliment Indicator
This signal reflects the inverse of the current state of FLEXCMD.
0: Flex Operation (Port 1 upstream, Port 0 downstream)
1: Normal Operation (Port 0 upstream, Port 1 downstream)
Note:
Refer to Section 8.2, "FlexConnect" for additional
information.
PROG_FUNC4
SMDAT
OD12
SMBus/I2C Data
The SMBus/I2C interface acts as SMBus slave or I2C bridge
dependent on the device configuration. Refer to Section 3.4.1,
"SPI/SMBus/I2C/UART Configuration (I2C_SLV_CFG[1:0])".
PROG_FUNC5
SMCLK
OD12
SMBus/I2C Clock
The SMBus/I2C interface acts as SMBus slave or I2C bridge
dependent on the device configuration. Refer to Section 3.4.1,
"SPI/SMBus/I2C/UART Configuration (I2C_SLV_CFG[1:0])".
PROG_FUNC6
FLEXCMD
IS
FlexConnect Control
0: Normal Operation (Port 0 upstream, Port 1 downstream)
1: Flex Operation (Port 1 upstream, Port 0 downstream)
Note:
PROG_FUNC7
FLEX_STATE
O10
FlexConnect State Indicator
This signal reflects the current state of FLEXCMD.
0: Normal Operation (Port 0 upstream, Port 1 downstream)
1: Flex Operation (Port 1 upstream, Port 0 downstream)
Note:
DS00001854H-page 20
Refer to the Section 8.2, "FlexConnect" for additional information.
Refer to Section 8.2, "FlexConnect" for additional
information.
2015-2020 Microchip Technology Inc.
USB5734
3.4.5.3
Configuration 3 - Speed Indicator Mode
When the CFG_STRAP is configured to this mode, the programmable function pins (PROG_FUNC[7:1]) are set to indicate speed status, host type, and provide an SMBus/I2C interface. Table 3-18 details the PROG_FUNC[7:1] pin assignments in this mode.
TABLE 3-18:
CONFIGURATION 3 PROG_FUNC[7:1] FUNCTION ASSIGNMENT
Pin
Function
Buffer
Type
PROG_FUNC1
SPEED_IND1
O12
Port 1 Speed Indicator
Tri-state: Not connected
0: USB 2.0 / USB 1.1
1: USB 3.2 Gen 1
PROG_FUNC2
SPEED_IND2
O6
Port 2 Speed Indicator
Tri-state: Not connected
0: USB 2.0 / USB 1.1
1: USB 3.2 Gen 1
PROG_FUNC3
SPEED_IND3
O12
Port 3 Speed Indicator
Tri-state: Not connected
0: USB 2.0 / USB 1.1
1: USB 3.2 Gen 1
PROG_FUNC4
SMDAT
OD12
SMBus/I2C Data
The SMBus/I2C interface acts as SMBus slave or I2C bridge
dependent on the device configuration. Refer to Section 3.4.1,
"SPI/SMBus/I2C/UART Configuration (I2C_SLV_CFG[1:0])".
PROG_FUNC5
SMCLK
OD12
SMBus/I2C Clock
The SMBus/I2C interface acts as SMBus slave or I2C bridge
dependent on the device configuration. Refer to Section 3.4.1,
"SPI/SMBus/I2C/UART Configuration (I2C_SLV_CFG[1:0])".
PROG_FUNC6
SPEED_IND4
O12
Port 4 Speed Indicator
Tri-state: Not connected
0: USB 2.0 / USB 1.1
1: USB 3.2 Gen 1
PROG_FUNC7
HOST_TYPE
O10
Port 0 USB Host Type
Tri-state: No USB host detected on Port 0
0: USB 3.2 Gen 1 Host detected on Port 0
1: USB 2.0 or USB 1.1 Host detected on Port 0
Description
A USB 2.0 Host is considered detected when the USB 2.0 hub
address register holds a non-zero value. A USB 3.2 Gen 1
Host is considered detected when the USB 3.2 Gen 1 hub
address register holds a non-zero value.
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DS00001854H-page 21
USB5734
FIGURE 3-2:
CONFIGURATION 3 PROG_FUNC[7:1] PIN CONNECTIONS
3.3 V Rail
MMBD914LT1G
PROG_FUNC1
SPEED_IND1
330
A
B
Speed LED Indication:
PROG_FUNC2
SPEED_IND2
A
PROG_FUNC3
SPEED_IND3
PROG_FUNC5
PROG_FUNC6
SMCLK
SPEED_IND4
330
HOST_TYPE
B
330
A
DS00001854H-page 22
B
SMDAT
A
PROG_FUNC7
B
330
A
PROG_FUNC4
OFF – Port Not Connected
A – USB2.0/1.1 Connection
B – USB 3.2 Gen 1 Connection
330
B
2015-2020 Microchip Technology Inc.
USB5734
3.4.5.4
Configuration 4 - GPIO Mode (Reserved)
When the CFG_STRAP is configured to this mode, the programmable function pins (PROG_FUNC[7:1]) are set to provide 7 general purpose I/Os that can be used for GPIO bridging. Table 3-19 details the PROG_FUNC[7:1] pin assignments in this mode.
TABLE 3-19:
CONFIGURATION 4 PROG_FUNC[7:1] FUNCTION ASSIGNMENT
Pin
Function
Buffer
Type
PROG_FUNC1
GPIO1
I/O12
General Purpose Input/Output 1
PROG_FUNC2
GPIO2
I/O6
General Purpose Input/Output 2
PROG_FUNC3
GPIO3
I/O12
General Purpose Input/Output 3
PROG_FUNC4
GPIO6
I/O12
General Purpose Input/Output 4
Description
PROG_FUNC5
GPIO8
I/O12
General Purpose Input/Output 5
PROG_FUNC6
GPIO10
I/O12
General Purpose Input/Output 6
PROG_FUNC7
GPIO11
I/O10
General Purpose Input/Output 7
3.4.5.5
Configuration 5 - Battery Charging / Power Delivery Indicator Mode
When the CFG_STRAP is configured to this mode, the programmable function pins (PROG_FUNC[7:1]) are set to indicate battery charging and 3 general purpose I/Os. Table 3-20 details the PROG_FUNC[7:1] pin assignments in this
mode.
TABLE 3-20:
CONFIGURATION 5 PROG_FUNC[7:1] FUNCTION ASSIGNMENT
Pin
Function
Buffer
Type
PROG_FUNC1
BC_IND1
O12
Port 1 Battery Charging Indicator
Tri-state: Battery Charging not enabled
0: In BC 1.2 Mode
1: Battery Charging enabled
PROG_FUNC2
BC_IND2
O6
Port 2 Battery Charging Indicator
Tri-state: Battery Charging not enabled
0: In BC 1.2 Mode
1: Battery Charging enabled
PROG_FUNC3
BC_IND3
O12
Port 3 Battery Charging Indicator
Tri-state: Battery Charging not enabled
0: In BC 1.2 Mode
1: Battery Charging enabled
PROG_FUNC4
BC_IND4
O12
Port 4 Battery Charging Indicator
Tri-state: Battery Charging not enabled
0: In BC 1.2 Mode
1: Battery Charging enabled
Description
PROG_FUNC5
GPIO8
I/O12
General Purpose Input/Output 8
PROG_FUNC6
GPIO10
I/O12
General Purpose Input/Output 10
PROG_FUNC7
GPIO11
I/O10
General Purpose Input/Output 11
2015-2020 Microchip Technology Inc.
DS00001854H-page 23
USB5734
FIGURE 3-3:
CONFIGURATION 5 PROG_FUNC[7:1] PIN CONNECTIONS
3.3 V Rail
MMBD914LT1G
PROG_FUNC1
BC_STATUS_1
330
A
PROG_FUNC2
BC_STATUS_2
BC_STATUS_3
BC_STATUS_4
PROG_FUNC6
PROG_FUNC7
DS00001854H-page 24
B
330
A
PROG_FUNC5
B
330
A
PROG_FUNC4
BC LED Indication:
OFF – BC In not Enabled
A – BC Enabled
B – BC in 1.2 Mode
330
A
PROG_FUNC3
B
B
GPIO8
GPIO10
GPIO11
2015-2020 Microchip Technology Inc.
USB5734
3.4.5.6
Configuration 6 - Full UART Mode
When the CFG_STRAP is configured to this mode, the programmable function pins (PROG_FUNC[7:1]) are set for full
UART configuration and also provide an SMBus/I2C interface. In this mode the PROG_FUNCx pins are used in conjunction with the UART_TX and UART_RX pins for a full UART interface. Table 3-21 details the PROG_FUNC[7:1] pin
assignments in this mode.
Note:
When flow control is disabled, UART_nCTS, UART_nDCD, and UART_nDSR must not be left floating. In
this case, these pins should include external pull-downs to maintain UART communication in Full UART
Mode with no flow control.
TABLE 3-21:
CONFIGURATION 6 PROG_FUNC[7:1] FUNCTION ASSIGNMENT
Pin
Function
Buffer
Type
PROG_FUNC1
UART_nRTS
I/O12
UART Request To Send
PROG_FUNC2
UART_nCTS
I/O6
UART Clear To Send
PROG_FUNC3
UART_nDCD
I/O12
UART Data Carrier Detect
PROG_FUNC4
SMDAT
OD12
SMBus/I2C Data
The SMBus/I2C interface acts as SMBus slave or I2C bridge
dependent on the device configuration. Refer to Section 3.4.1,
"SPI/SMBus/I2C/UART Configuration (I2C_SLV_CFG[1:0])".
PROG_FUNC5
SMCLK
OD12
SMBus/I2C Clock
The SMBus/I2C interface acts as SMBus slave or I2C bridge
dependent on the device configuration. Refer to Section 3.4.1,
"SPI/SMBus/I2C/UART Configuration (I2C_SLV_CFG[1:0])".
PROG_FUNC6
UART_nDTR
I/O12
UART Data Terminal Ready
PROG_FUNC7
UART_nDSR
I/O10
UART Data Set Ready
2015-2020 Microchip Technology Inc.
Description
DS00001854H-page 25
USB5734
4.0
DEVICE CONNECTIONS
4.1
Power Connections
Figure 4-1 illustrates the device power connections.
FIGURE 4-1:
POWER CONNECTIONS
+3.3V
Supply
+1.2V
Supply
VDD33
(4x)
3.3V Internal Logic
USB5734
4.2
1.2V Internal Logic
VDD12
(8x)
VSS
SPI ROM Connections
Figure 4-2 illustrates the device SPI ROM connections. Refer to Section 7.1, "SPI Master Interface," on page 33 for
additional information on this device interface.
FIGURE 4-2:
SPI ROM CONNECTIONS
SPI_CE_N
CE#
SPI_CLK
CLK
SPI ROM
USB5734
DS00001854H-page 26
SPI_DO
DI
SPI_DI
DO
2015-2020 Microchip Technology Inc.
USB5734
4.3
SMBus Slave Connections
Figure 4-3 illustrates the device SMBus slave connections. Refer to Section 7.2, "SMBus Slave Interface," on page 33
for additional information on this device interface.
FIGURE 4-3:
SMBUS SLAVE CONNECTIONS
+3.3V
+3.3V
10K
10K
I2C_SLV_CFG1
+3.3V
Clock
SMCLK
+3.3V
USB5734
10K
10K
I2C_SLV_CFG0
4.4
SMBus
Master
Data
SMDAT
I2C Bridge Connections
Figure 4-4 illustrates the device I2C bridge connections. Refer to Section 7.3, "I2C Bridge Interface," on page 33 for
additional information on this device interface.
FIGURE 4-4:
I2C BRIDGE CONNECTIONS
+3.3V
10K
X
I2C_SLV_CFG1
4.5
+3.3V
USB5734
No
Connect
X
Clock
SMCLK
10K
Data
SMDAT
I2C_SLV_CFG0
I2C
Slave
UART Bridge Connections
Figure 4-5 illustrates the device UART bridge connections. Refer to Section 7.4, "Two Pin Serial Port (UART) Interface,"
on page 34 for additional information on this device interface.
FIGURE 4-5:
UART BRIDGE CONNECTIONS
TX
UART_RX
10K
UART
USB5734
UART_TX
2015-2020 Microchip Technology Inc.
RX
DS00001854H-page 27
USB5734
5.0
MODES OF OPERATION
The device provides two main modes of operation: Standby Mode and Hub Mode. These modes are controlled via the
RESET_N pin, as shown in Table 5-1.
TABLE 5-1:
MODES OF OPERATION
RESET_N Input
Summary
0
Standby Mode: This is the lowest power mode of the device. No functions are active
other than monitoring the RESET_N input. All port interfaces are high impedance and
the PLL is halted. Refer to Section 8.3.2, "External Chip Reset (RESET_N)" for additional information on RESET_N.
1
Hub (Normal) Mode: The device operates as a configurable USB hub with battery
charger detection. This mode has various sub-modes of operation, as detailed in
Figure 5-1. Power consumption is based on the number of active ports, their speed,
and amount of data received.
The flowchart in Figure 5-1 details the modes of operation and details how the device traverses through the Hub Mode
stages (shown in bold). The remaining sub-sections provide more detail on each stage of operation.
FIGURE 5-1:
HUB MODE FLOWCHART
RESET_N deasserted
(SPI_INIT)
(CFG_RD)
In SPI Mode &
Ext. SPI ROM
present?
NO
Load Config from
Internal ROM
YES
Modify Config
Based on Config
Straps
Run From
External SPI ROM
Perform SMBus/I2C
Initialization
YES
SMBus Host Present?
NO
NO
SOC Done?
(SOC_CFG)
YES
UART Present?
(STRAP)
NO
Expose CDC
Interface
YES
(CDC)
Combine OTP
Config Data
(OTP_CFG)
Hub Connect
(Hub.Connect)
Normal operation
DS00001854H-page 28
2015-2020 Microchip Technology Inc.
USB5734
5.1
5.1.1
Boot Sequence
STANDBY MODE
If the RESET_N pin is asserted, the hub will be in Standby Mode. This mode provides a very low power state for maximum power efficiency when no signaling is required. This is the lowest power state. In Standby Mode all downstream
ports are disabled, the USB data pins are held in a high-impedance state, all transactions immediately terminate (no
states saved), all internal registers return to their default state, the PLL is halted, and core logic is powered down in order
to minimize power consumption. Because core logic is powered off, no configuration settings are retained in this mode
and must be re-initialized after RESET_N is negated high.
5.1.2
SPI INITIALIZATION STAGE (SPI_INIT)
The first stage, the initialization stage, occurs on the deassertion of RESET_N. In this stage, the internal logic is reset,
the PLL locks if a valid clock is supplied, and the configuration registers are initialized to their default state. The internal
firmware then checks for an external SPI ROM. The firmware looks for an external SPI flash device that contains a valid
signature of “2DFU” (device firmware upgrade) beginning at address 0xFFFA. If a valid signature is found, then the
external ROM is enabled and the code execution begins at address 0x0000 in the external SPI device. If a valid signature is not found, then execution continues from internal ROM (CFG_RD stage).
When using an external SPI ROM, a 1 Mbit, 60 MHz or faster ROM must be used. Both 1- and 2-bit SPI operation are
supported. For optimum throughput, a 2-bit SPI ROM is recommended. Both mode 0 and mode 3 SPI ROMs are also
supported.
If the system is not strapped for SPI Mode, code execution will continue from internal ROM (CFG_RD stage).
5.1.3
CONFIGURATION READ STAGE (CFG_RD)
In this stage, the internal firmware loads the default values from the internal ROM and then uses the configuration strapping options to override the default values. Refer to Section 3.4, "Configuration Straps and Programmable Functions"
for information on usage of the various device configuration straps.
5.1.4
STRAP READ STAGE (STRAP)
In this stage, the firmware registers the configuration strap settings on the SPI_DO and SPI_CLK pins. Refer to Section
3.4.1, "SPI/SMBus/I2C/UART Configuration (I2C_SLV_CFG[1:0])" for information on configuring these straps. If configured for SMBus Slave Mode, the next state will be SOC_CFG. If configured for UART Mode, the device will become a
UART bridging combination device and the next state will be CDC. If neither condition is met, the next state is
OTP_CFG.
5.1.5
SOC CONFIGURATION STAGE (SOC_CFG)
In this stage, the SOC can modify any of the default configuration settings specified in the integrated ROM, such as USB
device descriptors and port electrical settings.
There is no time limit on this mode. In this stage the firmware will wait indefinitely for the SMBus/I2C configuration. When
the SOC has completed configuring the device, it must write to register 0xFF to end the configuration.
5.1.6
CDC CONFIGURATION STAGE (CDC)
If the device is configured in UART Mode, (UART Bridge), the hub feature controller will identify itself as a CDC UART
device and move to the OTP_CFG. Refer to Section 3.4.1, "SPI/SMBus/I2C/UART Configuration (I2C_SLV_CFG[1:0])"
for information on configuring the UART Mode.
5.1.7
OTP CONFIGURATION STAGE (OTP_CFG)
Once the SOC has indicated that it is done with configuration, all configuration data is combined in this stage. The
default data, the SOC configuration data, and the OTP data are all combined in the firmware and the device is programmed.
After the device is fully configured, it will go idle and then into suspend if there is no VBUS or Hub.Connect present.
Once VBUS is present, and battery charging is enabled, the device will transition to the Battery Charger Detection
Stage. If VBUS is present, and battery charging is not enabled, the device will transition to the Connect stage.
2015-2020 Microchip Technology Inc.
DS00001854H-page 29
USB5734
5.1.8
HUB CONNECT STAGE (HUB.CONNECT)
Once the CHGDET stage is completed, the device enters the Hub Connect stage. USB connect can be initiated by
asserting the VBUS pin function high. The device will remain in the Hub Connect stage indefinitely until the VBUS pin
function is deasserted.
5.1.9
NORMAL MODE
Lastly, the hub enters Normal Mode of operation. In this stage full USB operation is supported under control of the USB
Host on the upstream port. The device will remain in the normal mode until the operating mode is changed by the system.
If RESET_N is asserted low, then Standby Mode is entered. The device may then be placed into any of the designated
hub stages. Asserting a soft disconnect on the upstream port will cause the hub to return to the Hub.Connect stage until
the soft disconnect is negated.
DS00001854H-page 30
2015-2020 Microchip Technology Inc.
USB5734
6.0
DEVICE CONFIGURATION
The device supports a large number of features (some mutually exclusive), and must be configured in order to correctly
function when attached to a USB host controller. The hub can be configured either internally or externally depending on
the implemented interface.
Microchip provides a comprehensive software programming tool, Pro-Touch, for configuring the USB5734 functions,
registers and OTP memory. All configuration is to be performed via the Pro-Touch programming tool. For additional information on the Pro-Touch programming tool, refer to the Software Libraries within the Microchip USB5734 product page
at www.microchip.com/USB5734.
Note:
6.1
Device configuration straps and programmable pins are detailed in Section 3.4, "Configuration Straps and
Programmable Functions," on page 16.
Refer to Section 7.0, "Device Interfaces" for detailed information on each device interface.
Customer Accessible Functions
The following USB or SMBus accessible functions are available to the customer via the Pro-Touch Programming Tool.
Note:
6.1.1
6.1.1.1
For additional programming details, refer to the Pro-Touch programming tool.
USB ACCESSIBLE FUNCTIONS
I2C Bridging Access over USB
Access to I2C devices is performed as a pass-through operation from the USB Host. The device firmware has no knowledge of the operation of the attached I2C device. For more information, refer to the Microchip USB5734 product page
and SDK at www.microchip.com/USB5734.
Note:
6.1.1.2
Refer to Section 7.3, "I2C Bridge Interface," on page 33 for additional information on the I2C interface.
SPI Access over USB
Access to an attached SPI device is performed as a pass-through operation from the USB Host. The device firmware
has no knowledge of the operation of the attached SPI device. For more information, refer to the Microchip USB5734
product page and SDK at www.microchip.com/USB5734.
Note:
6.1.1.3
Refer to Section 7.1, "SPI Master Interface," on page 33 for additional information on the SPI.
UART Access over USB
Access to UART devices is performed as a pass-through operation from the USB Host. The device firmware has no
knowledge of the operation of the attached UART device. For more information, refer to the Microchip USB5734 product
page and SDK at www.microchip.com/USB5734.
Note:
6.1.1.4
Refer to Section 7.4, "Two Pin Serial Port (UART) Interface," on page 34 for additional information on the
UART interface.
OTP Access over USB
The OTP ROM in the device is accessible via the USB bus. All OTP parameters can be modified to the USB Host. The
OTP operates in Single Ended mode. For more information, refer to the Microchip USB5734 product page and SDK at
www.microchip.com/USB5734.
6.1.1.5
Battery Charging Access over USB
The Battery charging behavior of the device can be dynamically changed by the USB Host when something other than
the preprogrammed or OTP programmed behavior is desired. For more information, refer to the Microchip USB5734
product page and SDK at www.microchip.com/USB5734.
2015-2020 Microchip Technology Inc.
DS00001854H-page 31
USB5734
6.1.2
SMBUS ACCESSIBLE FUNCTIONS
OTP access and configuration of specific device functions are possible via the USB5734 SMBus. All OTP parameters
can be modified via the SMBus Host. The OTP can be programmed to operate in Single-Ended, Differential, Redundant,
or Differential Redundant mode, depending on the level of reliability required. For more information, refer to AN1903 “Configuration Options for the USB5734 and USB5744” application note at www.microchip.com/AN1903.
DS00001854H-page 32
2015-2020 Microchip Technology Inc.
USB5734
7.0
DEVICE INTERFACES
The USB5734 provides multiple interfaces for configuration and external memory access. This section details the various device interfaces and their usage:
•
•
•
•
SPI Master Interface
SMBus Slave Interface
I2C Bridge Interface
Two Pin Serial Port (UART) Interface
Note:
For details on how to enable each interface, refer to Section 3.4.1, "SPI/SMBus/I2C/UART Configuration
(I2C_SLV_CFG[1:0])".
For information on device connections, refer to Section 4.0, "Device Connections". For information on
device configuration, refer to Section 6.0, "Device Configuration".
Microchip provides a comprehensive software programming tool, Pro-Touch, for configuring the USB5734
functions, registers and OTP memory. All configuration is to be performed via the Pro-Touch programming
tool. For additional information on the Pro-Touch programming tool, refer to Software Libraries within Microchip USB5734 product page at www.microchip.com/USB5734.
7.1
SPI Master Interface
The device is capable of code execution from an external SPI ROM. When configured for SPI Mode, on power up the
firmware looks for an external SPI flash device that contains a valid signature of 2DFU (device firmware upgrade) beginning at address 0xFFFA. If a valid signature is found, then the external ROM is enabled and the code execution begins
at address 0x0000 in the external SPI device. If a valid signature is not found, then execution continues from internal
ROM.
Note:
7.2
For SPI timing information, refer to Section 10.6.7, "SPI Timing".
SMBus Slave Interface
The device includes an integrated SMBus slave interface, which can be used to access internal device run time registers
or program the internal OTP memory. SMBus slave detection is accomplished by detection of pull-up resistors on both
the SMDAT and SMCLK signals. Refer to Section 3.4.1, "SPI/SMBus/I2C/UART Configuration (I2C_SLV_CFG[1:0])"
for additional information.
Note:
7.3
All device configuration must be performed via the Pro-Touch Programming Tool. For additional information
on the Pro-Touch programming tool, refer to Software Libraries within Microchip USB5734 product page at
www.microchip.com/USB5734.
I2C Bridge Interface
The I2C Bridge interface implements a subset of the I2C Master Specification (Please refer to the Philips Semiconductor
Standard I2C-Bus Specification for details on I2C bus protocols). The I2C Bridge conforms to the Fast-Mode I2C Specification (400 kbit/s transfer rate and 7-bit addressing) for protocol and electrical compatibility. The device acts as the
master and generates the serial clock SCL, controls the bus access (determines which device acts as the transmitter
and which device acts as the receiver), and generates the START and STOP conditions. The I2C Bridge interface frequency is configurable through the I2C Bridging commands. I2C Bridge frequencies are derived from the formula
626KHz/n, where n is any integer from 1 to 256. Refer to Section 3.4.1, "SPI/SMBus/I2C/UART Configuration
(I2C_SLV_CFG[1:0])" for additional information.
2015-2020 Microchip Technology Inc.
DS00001854H-page 33
USB5734
Note:
Extensions to the I2C Specification are not supported.
All device configuration must be performed via the Pro-Touch Programming Tool. For additional information
on the Pro-Touch programming tool, contact your local sales representative.
7.4
Two Pin Serial Port (UART) Interface
The device incorporates a fully programmable, universal asynchronous receiver/transmitter (UART) that is functionally
compatible with the NS 16550AF, 16450, 16450 ACE registers and the 16C550A. The UART performs serial-to-parallel
conversion on received characters and parallel-to-serial conversion on transmit characters. Two sets of baud rates are
provided: 24 Mhz and 16 MHz. When the 24 Mhz source clock is selected, standard baud rates from 50 to 115.2 K are
available. When the source clock is 16 MHz, baud rates from 125 K to 1,000 K are available. The character options are
programmable for the transmission of data in word lengths of from five to eight, 1 start bit; 1, 1.5 or 2 stop bits; even,
odd, sticky or no parity; and prioritized interrupts. The UART contains a programmable baud rate generator that is capable of dividing the input clock or crystal by a number from 1 to 65535. The UART is also capable of supporting the MIDI
data rate.
7.4.1
TRANSMIT OPERATION
Transmission is initiated by writing the data to be sent to the TX Holding Register or TX FIFO (if enabled). The data is
then transferred to the TX Shift Register together with a start bit and parity and stop bits as determined by settings in
the Line Control Register. The bits to be transmitted are then shifted out of the TX Shift Register in the order Start bit,
Data bits (LSB first), Parity bit, Stop bit, using the output from the Baud Rate Generator (divided by 16) as the clock.
If enabled, a TX Holding Register Empty interrupt will be generated when the TX Holding Register or the TX FIFO (if
enabled) becomes empty.
When FIFOs are enabled (i.e. bit 0 of the FIFO Control Register is set), the UART can store up to 16 bytes of data for
transmission at a time. Transmission will continue until the TX FIFO is empty. The FIFO’s readiness to accept more data
is indicated by interrupt.
7.4.2
RECEIVE OPERATION
Data is sampled into the RX Shift Register using the Receive clock, divided by 16. The Receive clock is provided by the
Baud Rate Generator. A filter is used to remove spurious inputs that last for less than two periods of the Receive clock.
When the complete word has been clocked into the receiver, the data bits are transferred to the RX Buffer Register or
to the RX FIFO (if enabled) to be read by the CPU. (The first bit of the data to be received is placed in bit 0 of this register.) The receiver also checks that the parity bit and stop bits are as specified by the Line Control Register.
If enabled, an RX Data Received interrupt will be generated when the data has been transferred to the RX Buffer Register or, if FIFOs are enabled, when the RX Trigger Level has been reached. Interrupts can also be generated to signal
RX FIFO Character Timeout, incorrect parity, a missing stop bit (frame error) or other Line Status errors.
When FIFOs are enabled (i.e. bit 0 of the FIFO Control Register is set), the UART can store up to 16 bytes of received
data at a time. Depending on the selected RX Trigger Level, interrupt will go active to indicate that data is available when
the RX FIFO contains 1, 4, 8 or 14 bytes of data.
DS00001854H-page 34
2015-2020 Microchip Technology Inc.
USB5734
8.0
FUNCTIONAL DESCRIPTIONS
This section details various USB5734 functions, including:
•
•
•
•
•
•
Downstream Battery Charging
FlexConnect
Resets
Link Power Management (LPM)
Remote Wakeup Indicator
Port Control Interface
8.1
Downstream Battery Charging
The device can be configured by an OEM to have any of the downstream ports support battery charging. The hub’s role
in battery charging is to provide acknowledgment to a device’s query as to whether the hub system supports USB battery
charging. The hub silicon does not provide any current or power FETs or any additional circuitry to actually charge the
device. Those components must be provided externally by the OEM.
FIGURE 8-1:
BATTERY CHARGING EXTERNAL POWER SUPPLY
DC Power
INT
SCL
Microchip
SOC
Hub
SDA
PRT_CTL[n]
VBUS[n]
If the OEM provides an external supply capable of supplying current per the battery charging specification, the hub can
be configured to indicate the presence of such a supply from the device. This indication, via the PRT_CTL[4:1] pins, is
on a per port basis. For example, the OEM can configure two ports to support battery charging through high current
power FETs and leave the other two ports as standard USB ports.
For additional information, refer to the Microchip USB5734 Battery Charging application note on the Microchip.com
USB5734 product page at www.microchip.com/USB5734.
8.2
FlexConnect
This feature allows the upstream port to be swapped with downstream physical port 1. Only downstream port 1 can be
swapped physically. Using port remapping, any logical port (number assignment) can be swapped with the upstream
port (non-physical).
FlexConnect is enabled/disabled via the FLEXCONNECT control bit in the Connect Configuration register (address
0x318E). The FLEXCONNECT configuration bit switches the port. This bit can be controlled via the I2C interface or via
the FLEXCMD pin (PROG_FUNC6 in configurations 1 or 2). Toggling of FLEXCMD will cause an interrupt to the device
firmware. The firmware will then change the port direction based on the input value. Refer to Section 3.4.5, "Device
Mode / PROG_FUNC[7:1] Configuration (CFG_STRAP)" for additional information.
For additional information, refer to the Microchip USB5734 FlexConnect application note on the Microchip.com
USB5734 product page.
2015-2020 Microchip Technology Inc.
DS00001854H-page 35
USB5734
8.3
Resets
The device includes the following chip-level reset sources:
• Power-On Reset (POR)
• External Chip Reset (RESET_N)
• USB Bus Reset
8.3.1
POWER-ON RESET (POR)
A power-on reset occurs whenever power is initially supplied to the device, or if power is removed and reapplied to the
device. A timer within the device will assert the internal reset per the specifications listed in Section 10.6.2, "Power-On
and Configuration Strap Timing," on page 46.
8.3.2
EXTERNAL CHIP RESET (RESET_N)
A valid hardware reset is defined as assertion of RESET_N, after all power supplies are within operating range, per the
specifications in Section 10.6.3, "Reset and Configuration Strap Timing," on page 47. While reset is asserted, the device
(and its associated external circuitry) enters Standby Mode and consumes minimal current.
Assertion of RESET_N causes the following:
1.
2.
3.
4.
5.
The PHY is disabled and the differential pairs will be in a high-impedance state.
All transactions immediately terminate; no states are saved.
All internal registers return to the default state.
The external crystal oscillator is halted.
The PLL is halted.
Note:
All power supplies must have reached the operating levels mandated in Section 10.2, "Operating Conditions**," on page 42, prior to (or coincident with) the assertion of RESET_N.
8.3.3
USB BUS RESET
In response to the upstream port signaling a reset to the device, the device performs the following:
Note:
1.
2.
3.
4.
The device does not propagate the upstream USB reset to downstream devices.
Sets default address to 0.
Sets configuration to Unconfigured.
Moves device from suspended to active (if suspended).
Complies with the USB Specification for behavior after completion of a reset sequence.
The host then configures the device in accordance with the USB Specification.
8.4
Link Power Management (LPM)
The device supports the L0 (On), L1 (Sleep), and L2 (Suspend) link power management states. These supported LPM
states offer low transitional latencies in the tens of microseconds versus the much longer latencies of the traditional USB
suspend/resume in the tens of milliseconds. The supported LPM states are detailed in Table 8-1.
TABLE 8-1:
LPM STATE DEFINITIONS
State
Description
Entry/Exit Time to L0
L2
Suspend
Entry: ~3 ms
Exit: ~2 ms (from start of RESUME)
L1
Sleep
Entry:
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