USB5744
4-Port SS/HS USB Controller Hub
Highlights
Key Benefits
• USB Hub Feature Controller IC with 4 USB 3.2
Gen 1 / USB 2.0 downstream ports
• USB-IF Battery Charger revision 1.2 support on
up & downstream ports (DCP, CDP, SDP)
• USB Link Power Management (LPM) support
• Enhanced OEM configuration options available
through either OTP or SPI ROM
• USB-IF certified (TID 330000076), supporting latest Engineering Change Notices for compliance
with USB-IF logo testing for new USB Type-C®
industry initiative
- Header Packet Timer (TD7.9, TD7.11, TD7.26)
- Power Management Timer (TD7.18, TD7.20, TD7.23)
- Unacknowledged Connect and Remote
Wake Test Failure (TD10.25)
• Available in 56-pin (7 x 7 mm) VQFN lead-free,
RoHS compliant package
• Commercial and industrial grade temperature
support
• Configuration Straps: Predefined configuration of
system level functions
• USB 3.2 Gen 1 compliant 5 Gbps, 480 Mbps,
12 Mbps and 1.5 Mbps operation
Target Applications
•
•
•
•
•
Standalone USB Hubs
Laptop Docks
PC Motherboards
PC Monitor Docks
Multi-function USB 3.2 Gen 1 Peripherals
- 5 V tolerant USB 2.0 pins
- 1.32 V tolerant USB 3.2 Gen 1 pins
- Integrated termination & pull-up/pull-down resistors
• Supports per port battery charging of most popular battery powered devices
- USB-IF Battery Charging rev. 1.2 support
(DCP, CDP, SDP)
- Apple portable product charger emulation
- Chinese YD/T 1591-2006 charger emulation
- Chinese YD/T 1591-2009 charger emulation
- European Union universal mobile charger support
- Support for Microchip USC100x family of battery
charging controllers
- Supports additional portable devices
• Smart port controller operation
- Firmware handling of companion port controllers
• On-chip microcontroller
- Manages I/Os, VBUS, and other signals
• 8 KB RAM, 64 KB ROM
• 8 KB One Time Programmable (OTP) ROM
- Includes on-chip charge pump
• Configuration programming via OTP ROM, SPI
ROM, or SMBus
• PortSwap
- Configurable differential intro-pair signal swapping
• PHYBoost™
- Programmable USB transceiver drive strength for
recovering signal integrity
• VariSense™
- Programmable USB receiver sensitivity
• Compatible with Microsoft Windows 8, 7, XP,
Apple OS X 10.4+, and Linux hub drivers
• Optimized for low-power operation and
low thermal dissipation
• Package
- 56-pin VQFN (7 x 7 mm)
• Environmental
- 3 kV HBM JESD22-A114F ESD protection
- Commercial temperature range (0°C to +70°C)
- Industrial temperature range (-40°C to +85°C)
* USB Type-C® and USB-C® are trademarks of USB Implementation Forum.
2022 Microchip Technology Inc. and its subsidiaries
DS00001855L-page 1
USB5744
TO OUR VALUED CUSTOMERS
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The last character of the literature number is the version number, (e.g., DS30000000A is version A of document DS30000000).
Errata
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To determine if an errata sheet exists for a particular device, please check with one of the following:
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DS00001855L-page 2
2022 Microchip Technology Inc. and its subsidiaries
USB5744
Table of Contents
1.0 Preface ............................................................................................................................................................................................ 4
2.0 Introduction ..................................................................................................................................................................................... 6
3.0 Pin Description and Configuration .................................................................................................................................................. 8
4.0 Device Connections ...................................................................................................................................................................... 18
5.0 Modes of Operation ...................................................................................................................................................................... 20
6.0 Device Configuration ..................................................................................................................................................................... 23
7.0 Device Interfaces .......................................................................................................................................................................... 24
8.0 Functional Descriptions ................................................................................................................................................................. 25
9.0 Compliance Update ...................................................................................................................................................................... 31
10.0 Operational Characteristics ......................................................................................................................................................... 32
11.0 Package Information ................................................................................................................................................................... 41
2022 Microchip Technology Inc. and its subsidiaries
DS00001855L-page 3
USB5744
1.0
PREFACE
1.1
General Terms
TABLE 1-1:
GENERAL TERMS
Term
Description
ADC
Analog-to-Digital Converter
Byte
8 bits
CDC
Communication Device Class
CSR
Control and Status Registers
DWORD
32 bits
EOP
End of Packet
EP
Endpoint
FIFO
First In First Out buffer
FS
Full-Speed
FSM
Finite State Machine
GPIO
General Purpose I/O
HS
Hi-Speed
HSOS
High Speed Over Sampling
Hub Feature Controller
The Hub Feature Controller, sometimes called a Hub Controller for short is the internal
processor used to enable the unique features of the USB Controller Hub. This is not to
be confused with the USB Hub Controller that is used to communicate the hub status
back to the Host during a USB session.
I2C
Inter-Integrated Circuit
LS
Low-Speed
lsb
Least Significant Bit
LSB
Least Significant Byte
msb
Most Significant Bit
MSB
Most Significant Byte
N/A
Not Applicable
NC
No Connect
OTP
One Time Programmable
PCB
Printed Circuit Board
PCS
Physical Coding Sublayer
PHY
Physical Layer
PLL
Phase Lock Loop
RESERVED
Refers to a reserved bit field or address. Unless otherwise noted, reserved bits must
always be zero for write operations. Unless otherwise noted, values are not guaranteed when reading reserved bits. Unless otherwise noted, do not read or write to
reserved addresses.
SDK
Software Development Kit
SMBus
System Management Bus
UUID
Universally Unique IDentifier
WORD
16 bits
DS00001855L-page 4
2022 Microchip Technology Inc. and its subsidiaries
USB5744
1.2
1.
2.
3.
4.
5.
Reference Documents
UNICODE UTF-16LE For String Descriptors USB Engineering Change Notice, December 29th, 2004, http://
www.usb.org
Universal Serial Bus Revision 3.2 Specification, http://www.usb.org/developers/docs/
Battery Charging Specification, Revision 1.2, Dec. 07, 2010, http://www.usb.org
I2C-Bus Specification, Version 1.1, http://www.nxp.com
System Management Bus Specification, Version 1.0, http://smbus.org/specs
2022 Microchip Technology Inc. and its subsidiaries
DS00001855L-page 5
USB5744
2.0
INTRODUCTION
2.1
General Description
The Microchip USB5744 hub is low-power, OEM configurable, USB 3.2 Gen 1 hub feature controller with 4 downstream
ports and advanced features for embedded USB applications. The USB5744 is fully compliant with the Universal Serial
Bus Revision 3.2 Specification and USB 2.0 Link Power Management Addendum. The USB5744 supports 5 Gbps
SuperSpeed (SS), 480 Mbps Hi-Speed (HS), 12 Mbps Full-Speed (FS), and 1.5 Mbps Low-Speed (LS) USB downstream devices on all enabled downstream ports.
The USB5744 supports the legacy USB speeds (HS/FS/LS) through a dedicated USB 2.0 hub feature controller that is
the culmination of five generations of Microchip hub feature controller design and experience with proven reliability,
interoperability, and device compatibility. The SuperSpeed hub feature controller operates in parallel with the USB 2.0
controller, decoupling the 5 Gbps SS data transfers from bottlenecks due to the slower USB 2.0 traffic.
The USB5744 supports downstream battery charging. The USB5744 integrated battery charger detection circuitry supports the USB-IF Battery Charging (BC1.2) detection method and most Apple devices. The USB5744 provides the battery charging handshake and supports the following USB-IF BC1.2 charging profiles:
•
•
•
•
DCP: Dedicated Charging Port (Power brick with no data)
CDP: Charging Downstream Port (1.5A with data)
SDP: Standard Downstream Port (0.5A with data)
Custom profiles loaded via SMBus or OTP
Additionally, the USB5744 includes many powerful and unique features such as:
PortSwap, which adds per-port programmability to USB differential-pair pin locations. PortSwap allows direct alignment
of USB signals (D+/D-) to connectors to avoid uneven trace length or crossing of the USB differential signals on the
PCB.
PHYBoost, which provides programmable levels of Hi-Speed USB signal drive strength
in the downstream port transceivers. PHYBoost attempts to restore USB signal integrity
in a compromised system environment. The graphic on the right shows an example of
Hi-Speed USB eye diagrams before and after PHYBoost signal integrity restoration. in
a compromised system environment
VariSense, which controls the USB receiver sensitivity enabling programmable levels of USB signal receive sensitivity.
This capability allows operation in a sub-optimal system environment, such as when a captive USB cable is used.
The USB5744 can be configured for operation through internal default settings. Custom OEM configurations are supported through external SPI ROM or OTP ROM. All port control signal pins are under firmware control in order to allow
for maximum operational flexibility, and are available as GPIOs for customer specific use.
The USB5744 is available in commercial (0°C to +70°C) and industrial (-40°C to +85°C) temperature ranges. An internal
block diagram of the USB5744 is shown in Figure 2-1.
DS00001855L-page 6
2022 Microchip Technology Inc. and its subsidiaries
2022 Microchip Technology Inc. and its subsidiaries
Buffer
Buffer
USB2.0
PHY
Downstream USB Port 1
SS
PHY
RX
TX
SS
PHY
Buffer
SS
PHY
SS
PHY
Registers
& Hub I/O
USB 2.0
PHY
SS
PHY
RX
Buffer
USB2.0
PHY
SS
PHY
RX
Buffer
USB2.0
PHY
Downstream USB Port 3
SS
PHY
TX
Buffer
Downstream RX SS bus
Downstream USB Port 2
SS
PHY
TX
Buffer
Registers
& Hub I/O
APB Bus
8k OTP
Reset & 8051
Boot Seq.
Xdata-toAPB Brid ge
HS/FS/LS Routing Logic
VBUS
Control
XData
USB 2.0 Hub Controller
8k RAM
64k ROM
Embedded
8051 µC
Downstream TX SS bus
USB 3.2 Gen 1
Hub Controller
RX
TX
SS
PHY
RX
Buffer
USB2.0
PHY
Downstream USB Port 4
SS
PHY
TX
Buffer
SPI/SMBus
SPI/
SMBus
FIGURE 2-1:
Buffer
Comm on
Block
& PLL
Upstream USB Port 0
USB5744
INTERNAL BLOCK DIAGRAM
DS00001855L-page 7
USB5744
3.0
PIN DESCRIPTION AND CONFIGURATION
3.1
Pin Assignments
RBIAS
VDD33
XTALI/CLK_IN
XTALO
ATEST
USB3UP_RXDM
USB3UP_RXDP
VDD12
USB3UP_TXDM
USB3UP_TXDP
USB2UP_DM
USB2UP_DP
VDD33
VDD12
55
54
53
52
51
50
49
48
47
46
45
44
43
56-VQFN PIN ASSIGNMENTS
56
FIGURE 3-1:
USB2DN_DP1/PRT_DIS_P1
1
42
RESET_N
USB2DN_DM1/PRT_DIS_M1
2
41
SPI_CE_N/CFG_NON_REM
USB3DN_TXDP1
3
40
SPI_DI/CFG_BC_EN
USB3DN_TXDM1
4
39
SPI_DO/SMDAT
VDD12
5
38
SPI_CLK/SMCLK
USB3DN_RXDP1
6
37
VBUS_DET
USB3DN_RXDM1
7
36
PRT_CTL1
35
PRT_CTL2
USB2DN_DP2/PRT_DIS_P2
USB5744
56-VQ FN
8
( To p Vi ew )
USB2DN_DM2/PRT_DIS_M2
9
34
PRT_CTL3
USB3DN_TXDP2
10
33
VDD12
USB3DN_TXDM2
11
32
PRT_CTL4/GANG_PWR
VSS
(Connect exposed pad to ground with a via field)
28
VDD12
USB2DN_DP4/PRT_DIS_P4
USB3DN_TXDM4
24
27
23
USB3DN_RXDM3
26
22
USB3DN_RXDP3
USB3DN_TXDP4
21
VDD12
25
20
USB3DN_TXDM3
USB2DN_DM4/PRT_DIS_M4
19
USB3DN_TXDP3
USB3DN_RXDP4
18
29
17
14
USB2DN_DP3/PRT_DIS_P3
USB3DN_RXDM2
USB2DN_DM3/PRT_DIS_M3
USB3DN_RXDM4
16
VDD33
30
VDD33
31
13
15
12
VDD12
VDD12
USB3DN_RXDP2
Note: Exposed pad (VSS) on bottom of package must be connected to ground with a via field .
Note 1: Configuration straps are identified by an underlined symbol name. Signals that function as configurations
traps must be augmented with an external resistor when connected to a load. Refer to Section 3.4, "Configuration Straps and Programmable Functions" for additional information.
DS00001855L-page 8
2022 Microchip Technology Inc. and its subsidiaries
USB5744
Table 3-1 details the package pin assignments in table format.
TABLE 3-1:
56-VQFN PIN ASSIGNMENTS
Pin
Num.
Pin Name
Reset
State
Pin
Num.
Pin Name
Reset
State
1
USB2DN_DP1/PRT_DIS_P1
PD-15k
29
USB3DN_RXDP4
Z
2
USB2DN_DM1/PRT_DIS_M1
PD-15k
30
USB3DN_RXDM4
Z
3
USB3DN_TXDP1
Z
31
VDD33
A/P
4
USB3DN_TXDM1
Z
32
PRT_CTL4/GANG_PWR
PD-50k
5
VDD12
A/P
33
VDD12
A/P
6
USB3DN_RXDP1
Z
34
PRT_CTL3
PD-50k
7
USB3DN_RXDM1
Z
35
PRT_CTL2
PD-50k
8
USB2DN_DP2/PRT_DIS_P2
PD-15k
36
PRT_CTL1
PD-50k
9
USB2DN_DM2/PRT_DIS_M2
PD-15k
37
VBUS_DET
Z
10
USB3DN_TXDP2
Z
38
SPI_CLK/SMCLK
Z
11
USB3DN_TXDM2
Z
39
SPI_DO/SMDAT
PD-50k
12
VDD12
A/P
40
SPI_DI/CFG_BC_EN
Z
13
USB3DN_RXDP2
Z
41
SPI_CE_N/CFG_NON_REM
PU-50k
14
USB3DN_RXDM2
Z
42
RESET_N
R
15
VDD12
A/P
43
VDD12
A/P
16
VDD33
A/P
44
VDD33
A/P
17
USB2DN_DP3/PRT_DIS_P3
PD-15k
45
USB2UP_DP
PD-1M
18
USB2DN_DM3/PRT_DIS_M3
PD-15k
46
USB2UP_DM
PD-1M
19
USB3DN_TXDP3
Z
47
USB3UP_TXDP
Z
20
USB3DN_TXDM3
Z
48
USB3UP_TXDM
Z
21
VDD12
A/P
49
VDD12
A/P
22
USB3DN_RXDP3
Z
50
USB3UP_RXDP
Z
23
USB3DN_RXDM3
Z
51
USB3UP_RXDM
Z
24
USB2DN_DP4/PRT_DIS_P4
PD-15k
52
ATEST
Z
25
USB2DN_DM4/PRT_DIS_M4
PD-15k
53
XTALO
A/P
26
USB3DN_TXDP4
Z
54
XTALI/CLK_IN
A/P
27
USB3DN_TXDM4
Z
55
VDD33
A/P
28
VDD12
A/P
56
RBIAS
A/P
The pin reset state definitions are detailed in Table 3-2.
2022 Microchip Technology Inc. and its subsidiaries
DS00001855L-page 9
USB5744
TABLE 3-2:
PIN RESET STATE LEGEND
Symbol
Description
A/P
Analog/Power Input
R
Reset Control Input
Z
Hardware disables output driver (high impedance)
PU-50k
Hardware enables internal 50kΩ pull-up
PD-50k
Hardware enables internal 50kΩ pull-down
PD-15k
Hardware enables internal 15kΩ pull-down
PD-1M
Hardware enables internal 1M pull-down
3.2
Pin Descriptions
This section contains descriptions of the various USB5744 pins. This pin descriptions have been broken into functional
groups as follows:
•
•
•
•
•
•
USB 3.2 Gen 1 Pin Descriptions
USB 2.0 Pin Descriptions
USB Port Control Pin Descriptions
SPI/SMBus Pin Descriptions
Miscellaneous Pin Descriptions
Power and Ground Pin Descriptions
The “_N” symbol in the signal name indicates that the active, or asserted, state occurs when the signal is at a low voltage
level. For example, RESET_N indicates that the reset signal is active low. When “_N” is not present after the signal
name, the signal is asserted when at the high voltage level.
The terms assertion and negation are used exclusively. This is done to avoid confusion when working with a mixture of
“active low” and “Active high” signals. The term assert, or assertion, indicates that a signal is active, independent of
whether that level is represented by a high or low voltage. The term negate, or negation, indicates that a signal is inactive.
Note:
The buffer type for each signal is indicated in the “Buffer Type” column of the pin description tables. A
description of the buffer types is provided in Section 3.3, "Buffer Types," on page 15.
For additional information on configuration straps and configurable pins, refer to Section 3.4, "Configuration
Straps and Programmable Functions".
DS00001855L-page 10
2022 Microchip Technology Inc. and its subsidiaries
USB5744
TABLE 3-3:
USB 3.2 GEN 1 PIN DESCRIPTIONS
Num
Pins
Symbol
Buffer
Type
1
USB3UP_TXDP
IO-U
USB 3.2 Gen 1 upstream SuperSpeed transmit data plus.
1
USB3UP_TXDM
IO-U
USB 3.2 Gen 1 upstream SuperSpeed transmit data minus.
1
USB3UP_RXDP
IO-U
USB 3.2 Gen 1 upstream SuperSpeed receive data plus.
1
USB3UP_RXDM
IO-U
USB 3.2 Gen 1 upstream SuperSpeed receive data minus.
4
USBDN_TXDP[4:1]
IO-U
4
USBDN_TXDM[4:1]
IO-U
Description
USB 3.2 Gen 1 downstream ports 4-1 SuperSpeed transmit data plus.
Note:
USB 3.2 Gen 1 downstream ports 4-1 SuperSpeed transmit data
minus.
Note:
4
USBDN_RXDP[4:1]
IO-U
4
USBDN_RXDM[4:1]
IO-U
Num
Pins
If unused, leave floating.
USB 3.2 Gen 1 downstream ports 4-1 SuperSpeed receive data plus.
Note:
If unused, leave floating.
USB 3.2 Gen 1 downstream ports 4-1 SuperSpeed receive data
minus.
Note:
TABLE 3-4:
If unused, leave floating.
If unused, leave floating.
USB 2.0 PIN DESCRIPTIONS
Symbol
Buffer
Type
1
USB2UP_DP
IO-U
1
USB2UP_DM
IO-U
USB 2.0 upstream data minus (D-).
USB2DN_DP[4:1]
IO-U
USB 2.0 downstream ports 4-1 data plus (D+).
Description
USB 2.0 upstream data plus (D+).
Port 4-1 D+ Disable Configuration Strap.
4
PRT_DIS_P[4:1]
I
These configuration straps are used in conjunction with the corresponding PRT_DIS_M[4:1] straps to disable the related port (4-1).
Refer to Section 3.4.2, "Port Disable Configuration (PRT_DIS_P[4:1] /
PRT_DIS_M[4:1])" for more information.
See Note 2.
USB2DN_DM[4:1]
IO-U
USB 2.0 downstream ports 4-1 data minus (D-).
Port 4-1 D- Disable Configuration Strap.
4
PRT_DIS_M[4:1]
I
These configuration straps are used in conjunction with the corresponding PRT_DIS_P[4:1] straps to disable the related port (4-1).
Refer to Section 3.4.2, "Port Disable Configuration (PRT_DIS_P[4:1] /
PRT_DIS_M[4:1])" for more information.
See Note 2.
2022 Microchip Technology Inc. and its subsidiaries
DS00001855L-page 11
USB5744
TABLE 3-4:
Num
Pins
USB 2.0 PIN DESCRIPTIONS (CONTINUED)
Symbol
Buffer
Type
Description
This signal detects the state of the upstream bus power.
When designing a detachable hub, this pin must be connected to the
VBUS power pin of the upstream USB port through a resistor divider
(50 k by 100 k) to provide 3.3 V.
1
VBUS_DET
IS
For self-powered applications with a permanently attached host, this
pin must be connected to either 3.3 V or 5.0 V through a resistor
divider to provide 3.3 V.
In embedded applications, VBUS_DET may be controlled (toggled)
when the host desires to renegotiate a connection without requiring a
full reset of the device.
GPIO16
I/O6
General purpose input/output 16.
Note 2: Configuration strap values are latched on Power-On Reset (POR) and the rising edge of RESET_N (external
chip reset). Configuration straps are identified by an underlined symbol name. Signals that function as configurations traps must be augmented with an external resistor when connected to a load. Refer to Section
3.4, "Configuration Straps and Programmable Functions" for additional information.
TABLE 3-5:
Num
Pins
USB PORT CONTROL PIN DESCRIPTIONS
Symbol
Buffer
Type
Description
Port 1 Power Enable / Overcurrent Sense.
1
PRT_CTL1
I
(PU)
Note:
If unused, leave floating.
As an output, this signal is an active high control signal used to enable
power to the downstream port 1. As an input, this signal indicates an
overcurrent condition from an external current monitor on USB port 1.
Port 2 Power Enable / Overcurrent Sense.
1
PRT_CTL2
I
(PU)
Note:
If unused, leave floating.
As an output, this signal is an active high control signal used to enable
power to the downstream port 2. As an input, this signal indicates an
overcurrent condition from an external current monitor on USB port 2.
Port 3 Power Enable / Overcurrent Sense.
1
PRT_CTL3
I
(PU)
Note:
If unused, leave floating.
As an output, this signal is an active high control signal used to enable
power to the downstream port 3. As an input, this signal indicates an
overcurrent condition from an external current monitor on USB port 3.
Port 4 Power Enable / Overcurrent Sense.
PRT_CTL4
I
(PU)
GANG_PWR
I
(PU)
1
DS00001855L-page 12
Note:
If unused, leave floating.
As an output, this signal is an active high control signal used to enable
power to the downstream port 4. As an input, this signal indicates an
overcurrent condition from an external current monitor on USB port 4.
When pulled high enables gang mode. Gang power pin when used in
gang mode.
2022 Microchip Technology Inc. and its subsidiaries
USB5744
TABLE 3-6:
Num
Pins
SPI/SMBUS PIN DESCRIPTIONS
Symbol
Buffer
Type
SPI_CE_N
O12
GPIO7
I/O12
Description
Active low SPI chip enable output.
General purpose input/output 7.
Non-Removable Port Configuration Strap.
1
CFG_NON_REM
I
This configuration strap is used to configure the number of nonremovable ports. Refer to Section 3.4.3, "Non-Removable Port Configuration (CFG_NON_REM)" for more information.
See Note 3.
1
1
SPI_CLK
O6
SMCLK
OD12
GPIO4
I/O6
SPI_DO
O6
SMDAT
I/O12
GPIO5
I/O6
SPI_DI
IS
GPIO9
I/O12
SPI clock output to the serial ROM, when configured for SPI operation.
SMBus clock pin, when configured for SMBus slave operation.
General purpose input/output 4.
SPI data output, when configured for SPI operation.
SMBus data pin, when configured for SMBus slave operation.
General purpose input/output 5.
SPI data input, when configured for SPI operation.
General purpose input/output 9.
Battery Charging Configuration Strap.
1
CFG_BC_EN
I
This configuration strap is used to enable battery charging. Refer to
Section 3.4.4, "Battery Charging Configuration (CFG_BC_EN)" for
more information.
See Note 3.
Note 3: Configuration strap values are latched on Power-On Reset (POR) and the rising edge of RESET_N (external
chip reset). Configuration straps are identified by an underlined symbol name. Signals that function as configurations traps must be augmented with an external resistor when connected to a load. Refer to Section
3.4, "Configuration Straps and Programmable Functions" for additional information.
2022 Microchip Technology Inc. and its subsidiaries
DS00001855L-page 13
USB5744
TABLE 3-7:
MISCELLANEOUS PIN DESCRIPTIONS
Num
Pins
Symbol
Buffer
Type
1
RESET_N
IS
XTALI
ICLK
1
1
1
Description
The RESET_N pin puts the device into Reset Mode.
External 25 MHz crystal input
External reference clock input.
CLK_IN
ICLK
XTALO
OCLK
RBIAS
AI
The device may alternatively be driven by a single-ended clock oscillator. When this method is used, XTALO should be left unconnected.
External 25 MHz crystal output
A 12.0 k (+/- 1%) resistor is attached from ground to this pin to set
the transceiver’s internal bias settings.
Analog test pin.
1
TABLE 3-8:
Num
Pins
ATEST
AI
This signal is used for test purposes and must always be connected to
ground.
POWER AND GROUND PIN DESCRIPTIONS
Symbol
Buffer
Type
Description
+3.3 V power and internal regulator input
4
VDD33
P
Refer to Section 4.1, "Power Connections" for power connection information.
+1.2 V core power
8
VDD12
P
Refer to Section 4.1, "Power Connections" for power connection information.
Common ground.
Pad
VSS
DS00001855L-page 14
P
This exposed pad must be connected to the ground plane with a via
array.
2022 Microchip Technology Inc. and its subsidiaries
USB5744
3.3
Buffer Types
TABLE 3-9:
BUFFER TYPES
Buffer Type
I
Input
IS
Schmitt-triggered input
O6
Output with 6 mA sink and 6 mA source
O12
Output with 12 mA sink and 12 mA source
OD12
Open-drain output with 12 mA sink
PU
50 µA (typical) internal pull-up. Unless otherwise noted in the pin description, internal pullups are always enabled.
Internal pull-up resistors prevent unconnected inputs from floating. Do not rely on internal
resistors to drive signals external to the device. When connected to a load that must be
pulled high, an external resistor must be added.
PD
50 µA (typical) internal pull-down. Unless otherwise noted in the pin description, internal
pull-downs are always enabled.
Internal pull-down resistors prevent unconnected inputs from floating. Do not rely on internal
resistors to drive signals external to the device. When connected to a load that must be
pulled low, an external resistor must be added.
IO-U
AI
Analog input/output as defined in USB specification
Analog input
ICLK
Crystal oscillator input pin
OCLK
Crystal oscillator output pin
P
Note:
Description
Power pin
Refer to Section 10.5, "DC Specifications" for individual buffer DC electrical characteristics.
2022 Microchip Technology Inc. and its subsidiaries
DS00001855L-page 15
USB5744
3.4
Configuration Straps and Programmable Functions
Configuration straps are multi-function pins that are used during Power-On Reset (POR) or external chip reset
(RESET_N) to determine the default configuration of a particular feature. The state of the signal is latched following deassertion of the reset. Configuration straps are identified by an underlined symbol name. This section details the various
device configuration straps and associated programmable pin functions.
Note:
3.4.1
The system designer must guarantee that configuration straps meet the timing requirements specified in
Section 10.6.2, "Power-On and Configuration Strap Timing," on page 36 and Section 10.6.3, "Reset and
Configuration Strap Timing," on page 37. If configuration straps are not at the correct voltage level prior to
being latched, the device may capture incorrect strap values.
SPI/SMBUS CONFIGURATION
The SPI/SMBus pins can be configured into one of two functional modes:
• SPI Mode
• SMBus Slave Mode
If 10 k pull-up resistors are detected on SPI_DO and SPI_CLK, the SPI/SMBus pins are configured into SMBus Slave
Mode. If no pull-ups or pull-downs are detected on SPI_DO and SPI_CLK, the SPI/SMBus pins are first configured into
SPI Mode. The strap settings for these supported modes are detailed in Table 3-10. The individual pin function assignments for each mode are detailed in Table 3-11. For additional device connection information, refer to Section 4.0,
"Device Connections".
TABLE 3-10:
SPI/SMBUS MODE CONFIGURATION SETTINGS
Pin
SPI Mode
(Note 4)
SMBus Slave Mode
39
(SPI_DO)
No pull-up/down
10 k pull-up
38
(SPI_CLK)
No pull-up/down
10 k pull-up
Note 4: In order to use the SPI interface, an SPI ROM containing a valid signature of 2DFU (device firmware
upgrade) beginning at address 0xFFFA must be present. Refer to Section 7.1, "SPI Master Interface" for
additional information.
TABLE 3-11:
SPI/SMBUS MODE PIN ASSIGNMENTS
Pin
SPI Mode
SMBus Slave Mode
41
SPI_CE_N
CFG_NON_REM
40
SPI_DI
CFG_BC_EN
39
SPI_DO
SMDAT
38
SPI_CLK
SMCLK
DS00001855L-page 16
2022 Microchip Technology Inc. and its subsidiaries
USB5744
3.4.2
PORT DISABLE CONFIGURATION (PRT_DIS_P[4:1] / PRT_DIS_M[4:1])
The PRT_DIS_P[4:1] and PRT_DIS_M[4:1] configuration straps are used in conjunction to disable the related port (4-1).
For PRT_DIS_Px (where x is the corresponding port 4-1):
0 = Port x D+ Enabled
1 = Port x D+ Disabled
For PRT_DIS_Mx (where x is the corresponding port 4-1):
0 = Port x D- Enabled
1 = Port x D- Disabled
Note:
3.4.3
Both PRT_DIS_Px and PRT_DIS_Mx (where x is the corresponding port) must be tied to 3.3 V to disable
the associated downstream port. Disabling the USB 2.0 port will also disable the corresponding USB 3.2
Gen 1 port.
NON-REMOVABLE PORT CONFIGURATION (CFG_NON_REM)
The CFG_NON_REM configuration strap is used to configure the non-removable port settings of the device to one of
five settings. These modes are selected by the configuration of an external resistor on the CFG_NON_REM pin. The
resistor options are a 200 kΩ pull-down, 200 kΩ pull-up, 10 kΩ pull-down, 10 kΩ pull-up, and 10 Ω pull-down, as shown
in Table 3-12.
TABLE 3-12:
CFG_NON_REM RESISTOR ENCODING
CFG_NON_REM Resistor Value
Setting
200 kΩ Pull-Down
All ports removable
200 kΩ Pull-Up
Port 1 non-removable
10 kΩ Pull-Down
Port 1, 2 non-removable
10 kΩ Pull-Up
Port 1, 2, 3, non-removable
10 Ω Pull-Down
Port 1, 2, 3, 4 non-removable
3.4.4
BATTERY CHARGING CONFIGURATION (CFG_BC_EN)
The CFG_BC_EN configuration strap is used to configure the battery charging port settings of the device to one of five
settings. These modes are selected by the configuration of an external resistor on the CFG_BC_EN pin. The resistor
options are a 200 kΩ pull-down, 200 kΩ pull-up, 10 kΩ pull-down, 10 kΩ pull-up, and 10 Ω pull-down, as shown in
Table 3-13.
TABLE 3-13:
CFG_BC_EN RESISTOR ENCODING
CFG_BC_EN Resistor Value
Setting
200 kΩ Pull-Down
No battery charging
200 kΩ Pull-Up
Port 1 battery charging
10 kΩ Pull-Down
Port 1, 2 battery charging
10 kΩ Pull-Up
Port 1, 2, 3, battery charging
10 Ω Pull-Down
Port 1, 2, 3, 4 battery charging
2022 Microchip Technology Inc. and its subsidiaries
DS00001855L-page 17
USB5744
4.0
DEVICE CONNECTIONS
4.1
Power Connections
Figure 4-1 illustrates the device power connections.
FIGURE 4-1:
POWER CONNECTIONS
+3.3V
Supply
+1.2V
Supply
VDD33
(4x)
3.3V Internal Logic
USB5744
4.2
1.2V Internal Logic
VDD12
(8x)
VSS
SPI ROM Connections
Figure 4-2 illustrates the device SPI ROM connections. Refer to Section 7.1, "SPI Master Interface," on page 24 for
additional information on this device interface.
FIGURE 4-2:
SPI ROM CONNECTIONS
SPI_CE_N
CE#
SPI_CLK
CLK
SPI ROM
USB5744
DS00001855L-page 18
SPI_DO
DI
SPI_DI
DO
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USB5744
4.3
SMBus Slave Connections
Figure 4-3 illustrates the device SMBus slave connections. Refer to Section 7.2, "SMBus Slave Interface," on page 24
for additional information on this device interface.
FIGURE 4-3:
SMBUS SLAVE CONNECTIONS
+3.3V
10K
Clock
SMCLK
USB5744
+3.3V
10K
SMDAT
2022 Microchip Technology Inc. and its subsidiaries
SMBus
Master
Data
DS00001855L-page 19
USB5744
5.0
MODES OF OPERATION
The device provides two main modes of operation: Standby Mode and Hub Mode. These modes are controlled via the
RESET_N pin, as shown in Table 5-1.
TABLE 5-1:
MODES OF OPERATION
RESET_N Input
Summary
0
Standby Mode: This is the lowest power mode of the device. No functions are active
other than monitoring the RESET_N input. All port interfaces are high impedance and
the PLL is halted. Refer to Section 8.2.2, "External Chip Reset (RESET_N)" for additional information on RESET_N.
1
Hub (Normal) Mode: The device operates as a configurable USB hub with battery
charger detection. This mode has various sub-modes of operation, as detailed in
Figure 5-1. Power consumption is based on the number of active ports, their speed,
and amount of data received.
The flowchart in Figure 5-1 details the modes of operation and details how the device traverses through the Hub Mode
stages (shown in bold). The remaining sub-sections provide more detail on each stage of operation.
FIGURE 5-1:
HUB MODE FLOWCHART
RESET_N deasserted
(SPI_INIT)
(CFG_RD)
In SPI Mode &
Ext. SPI ROM
present?
NO
Load Config from
Internal ROM
YES
Modify Config
Based on Config
Straps
Run From
External SPI ROM
Perform SMBus/I2C
Initialization
YES
SMBus Host Present?
NO
(STRAP)
NO
SOC Done?
(SOC_CFG)
YES
Combine OTP
Config Data
(OTP_CFG)
Hub Connect
(Hub.Connect)
Normal operation
DS00001855L-page 20
2022 Microchip Technology Inc. and its subsidiaries
USB5744
5.1
5.1.1
Boot Sequence
STANDBY MODE
If the RESET_N pin is asserted, the hub will be in Standby Mode. This mode provides a very low power state for maximum power efficiency when no signaling is required. This is the lowest power state. In Standby Mode all downstream
ports are disabled, the USB data pins are held in a high-impedance state, all transactions immediately terminate (no
states saved), all internal registers return to their default state, the PLL is halted, and core logic is powered down in order
to minimize power consumption. Because core logic is powered off, no configuration settings are retained in this mode
and must be re-initialized after RESET_N is negated high.
5.1.2
SPI INITIALIZATION STAGE (SPI_INIT)
The first stage, the initialization stage, occurs on the deassertion of RESET_N. In this stage, the internal logic is reset,
the PLL locks if a valid clock is supplied, and the configuration registers are initialized to their default state. The internal
firmware then checks for an external SPI ROM. The firmware looks for an external SPI flash device that contains a valid
signature of “2DFU” (device firmware upgrade) beginning at address 0xFFFA. If a valid signature is found, then the
external ROM is enabled and the code execution begins at address 0x0000 in the external SPI device. If a valid signature is not found, then execution continues from internal ROM (CFG_RD stage).
When using an external SPI ROM, a 1 Mbit, 60 MHz or faster ROM must be used. Both 1- and 2-bit SPI operation are
supported. For optimum throughput, a 2-bit SPI ROM is recommended. Both mode 0 and mode 3 SPI ROMs are also
supported.
If the system is not strapped for SPI Mode, code execution will continue from internal ROM (CFG_RD stage).
5.1.3
CONFIGURATION READ STAGE (CFG_RD)
In this stage, the internal firmware loads the default values from the internal ROM and then uses the configuration strapping options to override the default values. Refer to Section 3.4, "Configuration Straps and Programmable Functions"
for information on usage of the various device configuration straps.
5.1.4
STRAP READ STAGE (STRAP)
In this stage, the firmware registers the configuration strap settings on the SPI_DO and SPI_CLK pins. Refer to Section
3.4.1, "SPI/SMBus Configuration" for information on configuring these straps. If configured for SMBus Slave Mode, the
next state will be SOC_CFG. Otherwise, the next state is OTP_CFG.
5.1.5
SOC CONFIGURATION STAGE (SOC_CFG)
In this stage, the SOC can modify any of the default configuration settings specified in the integrated ROM, such as USB
device descriptors and port electrical settings.
There is no time limit on this mode. In this stage the firmware will wait indefinitely for the SMBus/I2C configuration. When
the SOC has completed configuring the device, it must write to register 0xFF to end the configuration.
5.1.6
OTP CONFIGURATION STAGE (OTP_CFG)
Once the SOC has indicated that it is done with configuration, all configuration data is combined in this stage. The
default data, the SOC configuration data, and the OTP data are all combined in the firmware and the device is programmed.
After the device is fully configured, it will go idle and then into suspend if there is no VBUS or Hub.Connect present.
Once VBUS is present, and battery charging is enabled, the device will transition to the Battery Charger Detection
Stage. If VBUS is present, and battery charging is not enabled, the device will transition to the Connect stage.
5.1.7
HUB CONNECT STAGE (HUB.CONNECT)
Once the CHGDET stage is completed, the device enters the Hub Connect stage. USB connect can be initiated by
asserting the VBUS pin function high. The device will remain in the Hub Connect stage indefinitely until the VBUS pin
function is deasserted.
2022 Microchip Technology Inc. and its subsidiaries
DS00001855L-page 21
USB5744
5.1.8
NORMAL MODE
Lastly, the hub enters Normal Mode of operation. In this stage full USB operation is supported under control of the USB
Host on the upstream port. The device will remain in the normal mode until the operating mode is changed by the system.
If RESET_N is asserted low, then Standby Mode is entered. The device may then be placed into any of the designated
hub stages. Asserting a soft disconnect on the upstream port will cause the hub to return to the Hub.Connect stage until
the soft disconnect is negated.
DS00001855L-page 22
2022 Microchip Technology Inc. and its subsidiaries
USB5744
6.0
DEVICE CONFIGURATION
The device supports a large number of features (some mutually exclusive), and must be configured in order to correctly
function when attached to a USB host controller. The hub can be configured either internally or externally depending on
the implemented interface.
Microchip provides a comprehensive software programming tool, Pro-Touch, for configuring the USB5744 functions,
registers and OTP memory. All configuration is to be performed via the Pro-Touch programming tool. For additional information on the Pro-Touch programming tool, refer to the Software Libraries within the Microchip USB5744 product page
at www.microchip.com/USB5744.
Note:
6.1
Device configuration straps and programmable pins are detailed in Section 3.4, "Configuration Straps and
Programmable Functions," on page 16.
Refer to Section 7.0, "Device Interfaces" for detailed information on each device interface.
Customer Accessible Functions
The following USB or SMBus accessible functions are available to the customer via the Pro-Touch Programming Tool.
Note:
6.1.1
6.1.1.1
For additional programming details, refer to the Pro-Touch programming tool.
USB ACCESSIBLE FUNCTIONS
OTP Access over USB
The OTP ROM in the device is accessible via the USB bus. All OTP parameters can be modified to the USB Host. The
OTP operates in Single Ended mode. For more information, refer to the Microchip USB5744 product page and SDK at
www.microchip.com/USB5744
6.1.1.2
Battery Charging Access over USB
The Battery charging behavior of the device can be dynamically changed by the USB Host when something other than
the preprogrammed or OTP programmed behavior is desired. For more information, refer to the Microchip USB5744
product page and SDK at www.microchip.com/USB5744
6.1.2
SMBUS ACCESSIBLE FUNCTIONS
OTP access and configuration of specific device functions are possible via the USB5744 SMBus. All OTP parameters
can be modified via the SMBus Host. The OTP can be programmed to operate in Single-Ended, Differential, Redundant,
or Differential Redundant mode, depending on the level of reliability required. For more information, refer to AN1903 “Configuration Options for the USB5734 and USB5744” application note at www.microchip.com/AN1903.
2022 Microchip Technology Inc. and its subsidiaries
DS00001855L-page 23
USB5744
7.0
DEVICE INTERFACES
The USB5744 provides multiple interfaces for configuration and external memory access. This section details the various device interfaces and their usage:
• SPI Master Interface
• SMBus Slave Interface
Note:
For details on how to enable each interface, refer to Section 3.4.1, "SPI/SMBus Configuration".
For information on device connections, refer to Section 4.0, "Device Connections". For information on
device configuration, refer to Section 6.0, "Device Configuration".
Microchip provides a comprehensive software programming tool, Pro-Touch, for configuring the USB5744
functions, registers and OTP memory. All configuration is to be performed via the Pro-Touch programming
tool. For additional information on the Pro-Touch programming tool, refer to Software Libraries within Microchip USB5744 product page at www.microchip.com/USB5744.
7.1
SPI Master Interface
The device is capable of code execution from an external SPI ROM. When configured for SPI Mode, on power up the
firmware looks for an external SPI flash device that contains a valid signature of 2DFU (device firmware upgrade) beginning at address 0xFFFA. If a valid signature is found, then the external ROM is enabled and the code execution begins
at address 0x0000 in the external SPI device. If a valid signature is not found, then execution continues from internal
ROM.
Note:
7.2
For SPI timing information, refer to Section 10.6.7, "SPI Timing".
SMBus Slave Interface
The device includes an integrated SMBus slave interface, which can be used to access internal device run time registers
or program the internal OTP memory. SMBus slave detection is accomplished by detection of pull-up resistors on both
the SMDAT and SMCLK signals. Refer to Section 3.4.1, "SPI/SMBus Configuration" for additional information.
Note:
All device configuration must be performed via the Pro-Touch Programming Tool. For additional information
on the Pro-Touch programming tool, refer to Software Libraries within Microchip USB5744 product page at
www.microchip.com/USB5744.
DS00001855L-page 24
2022 Microchip Technology Inc. and its subsidiaries
USB5744
8.0
FUNCTIONAL DESCRIPTIONS
This section details various USB5744 functions, including:
•
•
•
•
Downstream Battery Charging
Resets
Link Power Management (LPM)
Port Control Interface
8.1
Downstream Battery Charging
The device can be configured by an OEM to have any of the downstream ports support battery charging. The hub’s role
in battery charging is to provide acknowledgment to a device’s query as to whether the hub system supports USB battery
charging. The hub silicon does not provide any current or power FETs or any additional circuitry to actually charge the
device. Those components must be provided externally by the OEM.
FIGURE 8-1:
BATTERY CHARGING EXTERNAL POWER SUPPLY
DC Power
INT
SCL
Microchip
SOC
Hub
SDA
PRT_CTL[n]
VBUS[n]
If the OEM provides an external supply capable of supplying current per the battery charging specification, the hub can
be configured to indicate the presence of such a supply from the device. This indication, via the PRT_CTL[4:1] pins, is
on a per port basis. For example, the OEM can configure two ports to support battery charging through high current
power FETs and leave the other two ports as standard USB ports.
For additional information, refer to the Microchip USB5744 Battery Charging application note on the Microchip.com
USB5744 product page at www.microchip.com/USB5744.
2022 Microchip Technology Inc. and its subsidiaries
DS00001855L-page 25
USB5744
8.2
Resets
The device includes the following chip-level reset sources:
• Power-On Reset (POR)
• External Chip Reset (RESET_N)
• USB Bus Reset
8.2.1
POWER-ON RESET (POR)
A power-on reset occurs whenever power is initially supplied to the device, or if power is removed and reapplied to the
device. A timer within the device will assert the internal reset per the specifications listed in Section 10.6.2, "Power-On
and Configuration Strap Timing," on page 36.
8.2.2
EXTERNAL CHIP RESET (RESET_N)
A valid hardware reset is defined as assertion of RESET_N, after all power supplies are within operating range, per the
specifications in Section 10.6.3, "Reset and Configuration Strap Timing," on page 37. While reset is asserted, the device
(and its associated external circuitry) enters Standby Mode and consumes minimal current.
Assertion of RESET_N causes the following:
1.
2.
3.
4.
5.
The PHY is disabled and the differential pairs will be in a high-impedance state.
All transactions immediately terminate; no states are saved.
All internal registers return to the default state.
The external crystal oscillator is halted.
The PLL is halted.
Note:
All power supplies must have reached the operating levels mandated in Section 10.2, "Operating Conditions**," on page 32, prior to (or coincident with) the assertion of RESET_N.
8.2.3
USB BUS RESET
In response to the upstream port signaling a reset to the device, the device performs the following:
Note:
1.
2.
3.
4.
The device does not propagate the upstream USB reset to downstream devices.
Sets default address to 0.
Sets configuration to Unconfigured.
Moves device from suspended to active (if suspended).
Complies with the USB Specification for behavior after completion of a reset sequence.
The host then configures the device in accordance with the USB Specification.
8.3
Link Power Management (LPM)
The device supports the L0 (On), L1 (Sleep), and L2 (Suspend) link power management states. These supported LPM
states offer low transitional latencies in the tens of microseconds versus the much longer latencies of the traditional USB
suspend/resume in the tens of milliseconds. The supported LPM states are detailed in Table 8-1.
TABLE 8-1:
LPM STATE DEFINITIONS
State
Description
Entry/Exit Time to L0
L2
Suspend
Entry: ~3 ms
Exit: ~2 ms (from start of RESUME)
L1
Sleep
Entry:
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