USB5816
6-Port USB 3.2 Gen 1 SmartHubTM IC
with Support for a Single USB Type-C® DFP
Highlights
• USB Hub Feature Controller IC Hub with:
-
1 USB 3.1 Gen 1 USB Type-C® downstream port
4 USB 3.1 Gen 1 legacy downstream ports
1 USB 2.0 downstream port
Legacy upstream port
• USB-IF Battery Charger revision 1.2 support on
up & downstream ports (DCP, CDP, SDP)
• Internal Hub Feature Controller device enables:
- USB to I2C/SPI/GPIO bridge endpoint support
- USB to internal hub register write and read
• USB Link Power Management (LPM) support
• Enhanced OEM configuration options available
through either OTP or SPI ROM
• USB-IF certified (TID 963), supporting latest Engineering Change Notices for compliance with
USB-IF logo testing for new USB Type-C®
industry initiative (Revision C or newer only)
- Header Packet Timer (TD7.9, TD7.11, TD7.26)
- Power Management Timer (TD7.18, TD7.20, TD7.23)
- Unacknowledged Connect and Remote
Wake Test Failure (TD10.25)
• Available in 100-pin (12mm x 12mm) VQFN
RoHS compliant package
• Commercial and industrial grade temperature
support
Target Applications
•
•
•
•
•
Standalone USB Hubs
Laptop Docks
PC Motherboards
PC Monitor Docks
Multi-function USB 3.2 Gen 1 Peripherals
Key Benefits
• USB 3.2 Gen 1 compliant 5 Gbps, 480 Mbps,
12 Mbps, and 1.5Mbps operation
- 5V tolerant USB 2.0 pins
- 1.32V tolerant USB 3.2 Gen 1 pins
- Integrated termination and pull-up/down resistors
• Native USB Type-C Support
- Integrated Multiplexer on USB Type-C enabled
ports
- USB 3.1 Gen 1 PHYs are disabled until a valid
USB Type-C attach is detected, saving idle power
2016-2021 Microchip Technology Inc.
• Supports battery charging of most popular battery
powered devices on all ports
- USB-IF Battery Charging rev. 1.2 support
(DCP, CDP, SDP)
- Apple® portable product charger emulation
- Chinese YD/T 1591-2006 charger emulation
- Chinese YD/T 1591-2009 charger emulation
- European Union universal mobile charger support
- Support for Microchip UCS100x family of battery
charging controllers
- Supports additional portable devices
• Smart port controller operation
- Firmware handling of companion port power
controllers
• On-chip microcontroller
- manages I/Os, VBUS, and other signals
• 8 KB RAM, 64 KB ROM
• 8 KB One-Time-Programmable (OTP) ROM
- Includes on-chip charge pump
• Configuration programming via OTP ROM,
SPI ROM, or SMBus
• PortSwap
- Configurable USB 2.0 differential pair signal swap
• PHYBoostTM
- Programmable USB transceiver drive strength for
recovering signal integrity
- USB 2.0 Hi-Speed disconnect threshold adjust
(Revision C or newer only)
• VariSenseTM
- Programmable USB receive sensitivity
• Port Split
- USB2.0 and USB 3.2 Gen1 port operation can be
split for custom applications using embedded
USB3.x devices in parallel with USB2.0 devices.
• USB Power Delivery Billboard Device Support
- Internal port can enumerate as a Power Delivery
Billboard device to communicate Power Delivery
Alternate Mode negotiation failure cases to USB
host
• Compatible with Microsoft Windows 10, 8, 7, XP,
Apple OS X 10.4+, and Linux hub drivers
• Optimized for low-power operation and low thermal dissipation
• Package
- 100-pin VQFN (12mm x 12mm)
DS00002238E-page 1
USB5816
TO OUR VALUED CUSTOMERS
It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip
products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and
enhanced as new volumes and updates are introduced.
If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via
E-mail at docerrors@microchip.com or fax the Reader Response Form in the back of this data sheet to (480) 792-4150. We
welcome your feedback.
Most Current Data Sheet
To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at:
http://www.microchip.com
You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page.
The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000).
Errata
An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current
devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision
of silicon and revision of document to which it applies.
To determine if an errata sheet exists for a particular device, please check with one of the following:
• Microchip’s Worldwide Web site; http://www.microchip.com
• Your local Microchip sales office (see last page)
When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are
using.
Customer Notification System
Register on our web site at www.microchip.com to receive the most current information on all of our products.
DS00002238E-page 2
2016-2021 Microchip Technology Inc.
USB5816
TABLE OF CONTENTS
Introduction ........................................................................................................................................................................................... 7
Pin Descriptions and Configuration ....................................................................................................................................................... 6
Functional Descriptions ......................................................................................................................................................................... 9
Operational Characteristics................................................................................................................................................................. 13
System Application ............................................................................................................................................................................. 19
Package Outlines ................................................................................................................................................................................ 26
Revision History ................................................................................................................................................................................... 29
The Microchip Web Site ...................................................................................................................................................................... 30
Customer Change Notification Service ............................................................................................................................................... 30
Customer Support ............................................................................................................................................................................... 30
Product Identification System ............................................................................................................................................................. 31
2016-2021 Microchip Technology Inc.
DS00002238E-page 3
USB5816
1.0
PREFACE
1.1
General Terms
TABLE 1-1:
GENERAL TERMS
Term
Description
ADC
Analog-to-Digital Converter
Byte
8 bits
CDC
Communication Device Class
CSR
Control and Status Registers
DWORD
32 bits
EOP
End of Packet
EP
Endpoint
FIFO
First In First Out buffer
FS
Full-Speed
FSM
Finite State Machine
GPIO
General Purpose I/O
HS
Hi-Speed
HSOS
High Speed Over Sampling
Hub Feature Controller
The Hub Feature Controller, sometimes called a Hub Controller for short is the internal
processor used to enable the unique features of the USB Controller Hub. This is not to
be confused with the USB Hub Controller that is used to communicate the hub status
back to the Host during a USB session.
I2C
Inter-Integrated Circuit
LS
Low-Speed
lsb
Least Significant Bit
LSB
Least Significant Byte
msb
Most Significant Bit
MSB
Most Significant Byte
N/A
Not Applicable
NC
No Connect
OTP
One Time Programmable
PCB
Printed Circuit Board
PCS
Physical Coding Sublayer
PHY
Physical Layer
PLL
Phase Lock Loop
RESERVED
Refers to a reserved bit field or address. Unless otherwise noted, reserved bits must
always be zero for write operations. Unless otherwise noted, values are not guaranteed when reading reserved bits. Unless otherwise noted, do not read or write to
reserved addresses.
SDK
Software Development Kit
SMBus
System Management Bus
UUID
Universally Unique IDentifier
WORD
16 bits
DS00002238E-page 4
2016-2021 Microchip Technology Inc.
USB5816
1.2
1.
2.
3.
4.
5.
Reference Documents
UNICODE UTF-16LE For String Descriptors USB Engineering Change Notice, December 29th, 2004, http://
www.usb.org
Universal Serial Bus Revision 3.2 Specification, http://www.usb.org/developers/docs/
Battery Charging Specification, Revision 1.2, Dec. 07, 2010, http://www.usb.org
I2C-Bus Specification, Version 1.1, http://www.nxp.com
System Management Bus Specification, Version 1.0, http://smbus.org/specs
2016-2021 Microchip Technology Inc.
DS00002238E-page 5
USB5816
2.0
INTRODUCTION
2.1
General Description
The Microchip USB5816 hub is a low-power, OEM configurable, USB 3.2 Gen 1 hub controller with 6 downstream ports
and advanced features for embedded USB applications. The USB5816 is fully compliant with the Universal Serial Bus
Revision 3.2 Specification and USB 2.0 Link Power Management Addendum. The USB5816 supports 5 Gbps SuperSpeed (SS), 480 Mbps Hi-Speed (HS), 12 Mbps Full-Speed (FS), and 1.5 Mbps Low-Speed (LS) USB downstream
devices on all enabled downstream ports.
The USB5816 supports the legacy USB speeds (HS/FS/LS) through a dedicated USB 2.0 hub controller that is the culmination of five generations of Microchip hub controller design and experience with proven reliability, interoperability,
and device compatibility. The SuperSpeed hub controller operates in parallel with the USB 2.0 hub controller, decoupling
the 5 Gbps SS data transfers from bottlenecks due to the slower USB 2.0 traffic.
The USB5816 hub feature controller enables OEMs to configure their system using “Configuration Straps.” These straps
simplify the configuration process, assigning default values to USB 3.2 Gen 1 ports and GPIOs. OEMs can disable ports,
enable battery charging, and define GPIO functions as default assignments on power-up, removing the need for OTP
or external SPI ROM.
The USB5816 supports downstream battery charging via the integrated battery charger detection circuitry, which supports the USB-IF Battery Charging (BC1.2) detection method and most Apple devices. The USB5816 provides the battery charging handshake and supports the following USB-IF BC1.2 charging profiles:
•
•
•
•
DCP: Dedicated Charging Port (Power brick with no data)
CDP: Charging Downstream Port (1.5A with data)
SDP: Standard Downstream Port (0.5A with data)
Custom profiles loaded via SMBus or OTP
Additionally, the USB5816 includes many powerful and unique features such as:
The Hub Feature Controller, which provides an internal USB device dedicated for use as a USB to I2C/UART/SPI/
GPIO interface, allowing external circuits or devices to be monitored, controlled, or configured via the USB interface.
PortSwap, which adds per-port programmability to USB differential-pair pin locations. PortSwap allows direct alignment
of USB signals (D+/D-) to connectors to avoid uneven trace length or crossing of the USB differential signals on the
PCB.
PHYBoost, which provides programmable levels of Hi-Speed USB signal drive strength
in the downstream port transceivers. PHYBoost attempts to restore USB signal integrity
in a compromised system environment. The graphic on the right shows an example of
Hi-Speed USB eye diagrams before and after PHYBoost signal integrity restoration. in
a compromised system environment.
VariSense, which controls the USB receiver sensitivity enabling programmable levels of USB signal receive sensitivity.
This capability allows operation in a sub-optimal system environment, such as when a captive USB cable is used.
Port Split, which allows for the USB 3.2 Gen1 and USB2.0 portions of downstream ports 4 and 5to operate independently and enumerate two separate devices in parallel in special applications.
USB Power Delivery Billboard Device, which allows an internal device to enumerate as a Billboard class device when
a Power Delivery Alternate Mode negotiation has failed. The Billboard device will enumerate temporarily to the host PC
when a failure occurs, as indicated by a digital signal from an external Power Delivery controller.
The USB5816 can be configured for operation through internal default settings. Custom OEM configurations are supported through external SPI ROM or OTP ROM. All port control signal pins are under firmware control in order to allow
for maximum operational flexibility, and are available as GPIOs for customer specific use.
The USB5816 is available in commercial (0°C to +70°C) and industrial (-40°C to +85°C) temperature ranges. An internal
block diagram of the USB5816 is shown in Figure 2-1.
DS00002238E-page 6
2016-2021 Microchip Technology Inc.
USB5816
FIGURE 2-1:
INTERNAL BLOCK DIAGRAM
P0 ‘B’
I2C from Master
+3.3 V
AFE0 AFE0
I2C/SMB
USB3 USB2
+1.2 V
Hub Controller Logic
25 Mhz
AFE1 AFE1 AFE1
AFE2 AFE2
AFE3 AFE3
AFE4 AFE4
AFE5 AFE5
AFE6
AFE7
OTP
Hub Feature
Controller
GPIO
P1
‘C’
2016-2021 Microchip Technology Inc.
P2
‘A’
P3
‘A’
P4
‘A’
P5
‘A’
SMB
SPI
P6
‘A’
DS00002238E-page 7
USB5816
3.0
PIN DESCRIPTIONS
3.1
Pin Diagram
HOST_TYPE0/GPIO23
PRT_CTL5/GPIO22
51
54
PRT_CTL4/GPIO21
VDD33
55
52
HOST_TYPE1/GPIO67
56
53
PRT_CTL3/GANG_PWR/GPIO20
C_ATTACH2/GPIO2
57
VDD12
PRT_CTL2/GPIO19
58
GPIO3
60
59
PRT_CTL6/GPIO18
CC_POL/GPIO71
ALT_MUX_EN/GPIO70
63
61
VDD33
64
62
SPI_DO/GPIO5
SPI_CLK/GPIO4
65
SPI_DI/GPIO9/CFG_BC_EN
67
66
GPIO69
SPI_CE_N/GPIO7/CFG_NON_REM
68
70
69
GPIO66
PRT_CTL1/GPIO17
71
C_ATTACH1/ATTACHMUX1A/GPIO1
VDD33
72
SMBDATA/GPIO6
73
SMBCLK/GPIO8
74
PIN ASSIGNMENTS (TOP VIEW)
75
FIGURE 3-1:
C_ATTACH0/GPIO64
76
50
AB1/ATTACHMUX1B/GPIO65
SUSP_IND/GPIO68
77
49
USB3DN_RXDM4
VDD12
78
48
USB3DN_RXDP4
NC
79
47
VDD12
NC
80
46
USB3DN_TXDM4
NC
81
45
USB3DN_TXDP4
NC
82
44
USB2DN_DM4/PRT_DIS_M4
VDD12
83
43
USB2DN_DP4/PRT_DIS_P4
NC
84
42
VDD33
NC
85
41
USB3DN_RXDM3
40
USB3DN_RXDP3
USB2DN_DP5/PRT_DIS_P5
86
USB2DN_DM5/PRT_DIS_M5
87
USB3DN_TXDP5
88
USB3DN_TXDM5
89
37
USB3DN_TXDP3
VDD12
90
36
USB2DN_DM3/PRT_DIS_M3
Microchip
USB5816
(Top View 100-VQFN)
39
VDD12
38
USB3DN_TXDM3
USB3DN_RXDP5
91
35
USB2DN_DP3/PRT_DIS_P3
USB3DN_RXDM5
92
34
USB3DN_RXDM2
VDD33
93
33
USB3DN_RXDP2
USB2UP_DP
94
32
VDD12
USB2UP_DM
95
31
USB3DN_TXDM2
USB3DN_TXDP2
thermal slug connects to VSS
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
VDD12
USB3DN_RXDP1A
USB3DN_RXDM1A
USB2DN_DP6/PRT_DIS_P6
USB2DN_DM6/PRT_DIS_M6
USB3DN_TXDP1B
USB3DN_TXDM1B
VDD12
USB3DN_RXDP1B
USB3DN_RXDM1B
GPIO12/CFG_STRAP
NC
NC
TESTEN
VBUS_DET
RESET_N
8
USB3DN_TXDP1A
USB3DN_TXDM1A
7
USB2DN_DM1/PRT_DIS_M1
VDD12
6
VDD33
26
5
27
VDD33
99
100
USB2DN_DP1/PRT_DIS_P1
USB3UP_RXDP
USB3UP_RXDM
4
USB2DN_DP2/PRT_DIS_P2
XTALO
28
3
98
XTALI/CLKIN
USB2DN_DM2/PRT_DIS_M2
VDD12
2
29
1
30
97
RBIAS
96
VDD33
USB3UP_TXDP
USB3UP_TXDM
Note 1: Configuration straps are identified by an underlined symbol name. Signals that function as configuration
straps must be augmented with an external resistor when connected to a load. Refer to Section 3.5, Configuration Straps and Programmable Functions
DS00002238E-page 8
2016-2021 Microchip Technology Inc.
USB5816
3.2
Pin Symbols
Pin Num.
Pin Name
Reset
Pin Num.
Pin Name
Reset
1
RBIAS
A/P
51
PRT_CTL5/GPIO22
PD-50k
2
VDD33
A/P
52
PRT_CTL4/GPIO21
PD-50k
3
XTALI/CLKIN
A/P
53
HOST_TYPE0/GPIO23
PD-50k
4
XTALO
A/P
54
VDD33
A/P
5
VDD33
A/P
55
HOST_TYPE1/GPIO67
Z
6
USB2DN_DP1/PRT_DIS_P1
PD-15k
56
C_ATTACH2/GPIO2
Z
7
USB2DN_DM1/PRT_DIS_M1
PD-15k
57
PRT_CTL3/GANG_PWR/GPIO20
PD-50k
8
USB3DN_TXDP1A
Z
58
PRT_CTL2/GPIO19
PD-50k
9
USB3DN_TXDM1A
Z
59
VDD12
A/P
10
VDD12
A/P
60
GPIO3
Z
11
USB3DN_RXDP1A
Z
61
CC_POL/GPIO71
Z
12
USB3DN_RXDM1A
Z
62
PRT_CTL6/GPIO18
PD-50k
13
USB2DN_DP6/PRT_DIS_P6
PD-15k
63
ALT_MUX_EN/GPIO70
Z
14
USB2DN_DM6/PRT_DIS_M6
PD-15k
64
VDD33
A/P
15
USB3DN_TXDP1B
Z
65
SPI_CLK/GPIO4
Z
16
USB3DN_TXDM1B
Z
66
SPI_DO/GPIO5
PD-50k
17
VDD12
A/P
67
SPI_DI/GPIO9/CFG_BC_EN
Z
18
USB3DN_RXDP1B
Z
68
SPI_CE_N/GPIO7/CFG_NON_REM
PU-50k
19
USB3DN_RXDM1B
Z
69
GPIO69
Z
20
GPIO12/CFG_STRAP
Z
70
PRT_CTL1/GPIO17
PD-50k
21
NC
Z
71
GPIO66
Z
22
NC
Z
72
VDD33
A/P
23
TESTEN
Z
73
C_ATTACH1/ATTACHMUX1A/GPIO1
Z
24
VBUS_DET
Z
74
SMBDATA/GPIO6
Z
25
RESET_N
R
75
SMBCLK/GPIO8
Z
26
VDD12
A/P
76
C_ATTACH0/GPIO64
Z
27
VDD33
A/P
77
SUSP_IND/GPIO68
Z
28
USB2DN_DP2/PRT_DIS_P2
PD-15k
78
VDD12
A/P
29
USB2DN_DM2/PRT_DIS_M2
PD-15k
79
NC
PD-15k
30
USB3DN_TXDP2
Z
80
NC
PD-15k
31
USB3DN_TXDM2
Z
81
NC
Z
32
VDD12
A/P
82
NC
Z
33
USB3DN_RXDP2
Z
83
VDD12
A/P
Z
34
USB3DN_RXDM2
Z
84
NC
35
USB2DN_DP3/PRT_DIS_P3
PD-15k
85
NC
Z
36
USB2DN_DM3/PRT_DIS_M3
PD-15k
86
USB2DN_DP5/PRT_DIS_P5
PD-15k
37
USB3DN_TXDP3
Z
87
USB2DN_DM5/PRT_DIS_M5
PD-15k
38
USB3DN_TXDM3
Z
88
USB3DN_TXDP5
Z
39
VDD12
A/P
89
USB3DN_TXDM5
Z
40
USB3DN_RXDP3
Z
90
VDD12
A/P
41
USB3DN_RXDM3
Z
91
USB3DN_RXDP5
Z
42
VDD33
A/P
92
USB3DN_RXDM5
Z
43
USB2DN_DP4/PRT_DIS_P4
PD-15k
93
VDD33
A/P
44
USB2DN_DM4/PRT_DIS_M4
PD-15k
94
USB2UP_DP
PD-1M
45
USB3DN_TXDP4
Z
95
USB2UP_DM
PD-1M
46
USB3DN_TXDM4
Z
96
USB3UP_TXDP
Z
47
VDD12
A/P
97
USB3UP_TXDM
Z
48
USB3DN_RXDP4
Z
98
VDD12
A/P
49
USB3DN_RXDM4
Z
99
USB3UP_RXDP
Z
50
AB1/ATTACHMUX1B/GPIO65
Z
100
USB3UP_RXDM
Z
2016-2021 Microchip Technology Inc.
DS00002238E-page 9
USB5816
The pin reset state definitions are detailed in Table 3-1.
TABLE 3-1:
PIN RESET STATE LEGEND
Symbol
3.3
Description
A/P
Analog/Power Input
R
Reset Control Input
Z
Hardware disables output driver (high impedance)
PU-50k
Hardware enables internal 50kΩ pull-up
PD-50k
Hardware enables internal 50kΩ pull-down
PD-15k
Hardware enables internal 15kΩ pull-down
PD-1M
Hardware enables internal 1M pull-down
USB5816 Pin Descriptions
This section contains descriptions of the various USB5816 pins. The pin descriptions have been broken into functional
groups as follows:
•
•
•
•
•
•
•
•
USB 3.2 Gen 1 Pin Descriptions
USB 2.0 Pin Descriptions
Port Control Pin Descriptions
SPI Interface
USB Type-C Connector Controls
Miscellaneous Pin Descriptions
Configuration Strap Pin Descriptions
Power and Ground Pin Descriptions
The “_N” symbol in the signal name indicates that the active, or asserted, state occurs when the signal is at a low voltage
level. For example, RESET_N indicates that the reset signal is active low. When “_N” is not present after the signal
name, the signal is asserted when at the high voltage level.
The terms assertion and negation are used exclusively. This is done to avoid confusion when working with a mixture of
“active low” and “active high” signal. The term assert, or assertion, indicates that a signal is active, independent of
whether that level is represented by a high or low voltage. The term negate, or negation, indicates that a signal is inactive.
TABLE 3-2:
USB 3.2 GEN 1 PIN DESCRIPTIONS
Name
Symbol
Buffer
Type
USB 3.2 Gen 1
Upstream D+ TX
USB3UP_TXDP
I/O-U
Upstream USB 3.2 Gen 1 Transmit Data Plus
USB 3.2 Gen 1
Upstream D- TX
USB3UP_TXDM
I/O-U
Upstream USB 3.2 Gen 1 Transmit Data Minus
USB 3.2 Gen 1
Upstream D+ RX
USB3UP_RXDP
I/O-U
Upstream USB 3.2 Gen 1 Receive Data Plus
USB 3.2 Gen 1
Upstream D- RX
USB3UP_RXDM
I/O-U
Upstream USB 3.2 Gen 1 Receive Data Minus
DS00002238E-page 10
Description
2016-2021 Microchip Technology Inc.
USB5816
TABLE 3-2:
USB 3.2 GEN 1 PIN DESCRIPTIONS (CONTINUED)
Name
Symbol
Buffer
Type
USB 3.2 Gen 1
Ports 5-2
D+ TX
USB3DN_TXDP[5:2]
I/O-U
Downstream Super Speed Transmit Data Plus,
ports 5 through 2.
USB 3.2 Gen 1
Ports 5-2
D- TX
USB3DN_TXDM[5:2]
I/O-U
Downstream Super Speed Transmit Data Minus,
ports 5 through 2.
USB 3.2 Gen 1
Ports 5-2
D+ RX
USB3DN_RXDP[5:2]
I/O-U
Downstream Super Speed Receive Data Plus,
ports 5 through 2.
USB 3.2 Gen 1
Ports 5-2
D- RX
USB3DN_RXDM[5:2]
I/O-U
Downstream Super Speed Receive Data Minus,
ports 5 through 2.
USB 3.1 Gen 1
Port 1 A
D+ TX
USB3DN_TXDP1A
I/O-U
Downstream USB Type-C “Orientation A” Super Speed
Transmit Data Plus, port 1.
USB 3.1 Gen 1
Port 1 A
D- TX
USB3DN_TXDM1A
I/O-U
Downstream USB Type-C “Orientation A” Super Speed
Transmit Data Minus, port 1.
USB 3.1 Gen 1
Port 1 A
D+ RX
USB3DN_RXDP1A
I/O-U
Downstream USB Type-C “Orientation A” Super Speed
Receive Data Plus, port 1.
USB 3.1 Gen 1
Port 1 A
D- RX
USB3DN_RXDM1A
I/O-U
Downstream USB Type-C “Orientation A” Super Speed
Receive Data Minus, port 1.
USB 3.1 Gen 1
Port 1 B
D+ TX
USB3DN_TXDP1B
I/O-U
Downstream USB Type-C “Orientation B” Super Speed
Transmit Data Plus, port 1.
USB 3.1 Gen 1
Port 1 B
D- TX
USB3DN_TXDM1B
I/O-U
Downstream USB Type-C “Orientation B” Super Speed
Transmit Data Minus, port 1.
USB 3.1 Gen 1
Port 1 B
D+ RX
USB3DN_RXDP1B
I/O-U
Downstream USB Type-C “Orientation B” Super Speed
Receive Data Plus, port 1.
USB 3.1 Gen 1
Port 1 B
D- RX
USB3DN_RXDM1B
I/O-U
Downstream USB Type-C “Orientation B” Super Speed
Receive Data Minus, port 1.
2016-2021 Microchip Technology Inc.
Description
DS00002238E-page 11
USB5816
TABLE 3-3:
USB 2.0 PIN DESCRIPTIONS
Name
Symbol
Buffer
Type
Description
USB 2.0
Upstream
D+
USB2UP_DP
I/O-U
Upstream USB 2.0 Data Plus (D+)
USB 2.0
Upstream
D-
USB2UP_DM
I/O-U
Upstream USB 2.0 Data Minus (D-)
USB 2.0
Ports 6 D+
USB2DN_DP[6:1]
I/O-U
Downstream USB 2.0 Ports 6-1 Data Plus (D+)
USB 2.0
Ports 6 D-
USB2DN_DM[6:1]
I/O-U
Downstream USB 2.0 Ports 6-1 Data Minus (D-)
VBUS Detect
VBUS_DET
IS
This signal detects the state of the upstream bus power.
When designing a detachable hub, this pin must be connected to the VBUS power pin of the upstream USB port
through a resistor divider (50 kΩ by 100 kΩ) to provide
3.3 V.
For self-powered applications with a permanently
attached host, this pin must be connected to either 3.3 V
or 5.0 V through a resistor divider to provide 3.3 V.
In embedded applications, VBUS_DET may be controlled
(toggled) when the host desires to renegotiate a connection without requiring a full reset of the device.
TABLE 3-4:
PORT CONTROL PIN DESCRIPTIONS
Name
Symbol
Port 6
Power Enable /
Overcurrent
Sense
PRT_CTL6
Buffer
Type
I/OD12
(PU)
Description
Port 6 Power Enable / Overcurrent Sense.
When the downstream port is enabled, this pin is set as
an input with an internal pull-up resistor applied. The
internal pull-up enables power to the downstream port
while the pin monitors for an active low overcurrent signal
assertion from an external current monitor on USB port 6.
This pin will change to an output and be driven low when
the port is disabled by configuration or by the host control.
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USB5816
TABLE 3-4:
PORT CONTROL PIN DESCRIPTIONS (CONTINUED)
Name
Symbol
Port 5
Power Enable /
Overcurrent
Sense
PRT_CTL5
Buffer
Type
I/OD12
(PU)
Description
Port 5 Power Enable / Overcurrent Sense.
When the downstream port is enabled, this pin is set as
an input with an internal pull-up resistor applied. The
internal pull-up enables power to the downstream port
while the pin monitors for an active low overcurrent signal
assertion from an external current monitor on USB port 5.
This pin will change to an output and be driven low when
the port is disabled by configuration or by the host control.
Port 4
Power Enable /
Overcurrent
Sense
PRT_CTL4
I/OD12
(PU)
Port 4 Power Enable / Overcurrent Sense.
When the downstream port is enabled, this pin is set as
an input with an internal pull-up resistor applied. The
internal pull-up enables power to the downstream port
while the pin monitors for an active low overcurrent signal
assertion from an external current monitor on USB port 4.
This pin will change to an output and be driven low when
the port is disabled by configuration or by the host control.
Port 3
Power Enable /
Overcurrent
Sense
PRT_CTL3
I/OD12
(PU)
Port 3 Power Enable / Overcurrent Sense.
When the downstream port is enabled, this pin is set as
an input with an internal pull-up resistor applied. The
internal pull-up enables power to the downstream port
while the pin monitors for an active low overcurrent signal
assertion from an external current monitor on USB port 3.
This pin will change to an output and be driven low when
the port is disabled by configuration or by the host control.
Port 2
Power Enable /
Overcurrent
Sense
PRT_CTL2
I/OD12
(PU)
Port 2 Power Enable / Overcurrent Sense.
When the downstream port is enabled, this pin is set as
an input with an internal pull-up resistor applied. The
internal pull-up enables power to the downstream port
while the pin monitors for an active low overcurrent signal
assertion from an external current monitor on USB port 2.
This pin will change to an output and be driven low when
the port is disabled by configuration or by the host control.
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DS00002238E-page 13
USB5816
TABLE 3-4:
PORT CONTROL PIN DESCRIPTIONS (CONTINUED)
Name
Symbol
Port 1
Power Enable /
Overcurrent
Sense
PRT_CTL1
Buffer
Type
I/OD12
(PU)
Description
Port 1 Power Enable / Overcurrent Sense.
When the downstream port is enabled, this pin is set as
an input with an internal pull-up resistor applied. The
internal pull-up enables power to the downstream port
while the pin monitors for an active low overcurrent signal
assertion from an external current monitor on USB port 1.
This pin will change to an output and be driven low when
the port is disabled by configuration or by the host control.
GANG_PWR
Gang Power
I
GANG_PWR becomes the port control (PRTCTL) pin for
all downstream ports when the hub is configured for
ganged port power control mode. All port power controllers should be controlled from this pin when the hub is
configured for ganged port power mode.
TABLE 3-5:
SPI INTERFACE
Name
Symbol
Buffer
Type
SPI Chip Enable
SPI_CE_N
I/O12
This is the active low SPI chip enable output. If the SPI
interface is enabled, this pin must be driven high in
power-down states.
SPI Clock
SPI_CLK
I/O-U
This is the SPI clock out to the serial ROM. If the SPI
interface is disabled, by setting the SPI_DIS-ABLE bit in
the UTIL_CONFIG1 register, this pin becomes GPIO4. If
the SPI interface is enabled this pin must be driven low
during reset.
SPI Data Output
SPI_DO
I/O-U
SPI data output, when configured for SPI operation.
SPI Data Input
SPI_DI
I/O-U
SPI data input, when configured for SPI operation.
Note:
Description
If SPI memory device is not used, these pins may not be simply floated. These pins must be handled per
their respective alternate pin functions descriptions (CFG_BC_EN and CFG_NON_REM).
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USB5816
TABLE 3-6:
USB TYPE-C CONNECTOR CONTROLS
Name
Symbol
USB Type-C
Attach Control
Input 0-2
C_ATTACH[0:2]
Buffer
Type
I
(PD)
Description
“Type-C Control Mode 1” USB Type-C attach control
input.
This pin indicates to the hub when a valid USB Type-C
attach has been detected. This pin is used by the hub to
enable the USB 3.2 Gen 1 PHY when a Type-C connection is present. When there is no USB Type-C connection
present, the USB 3.2 Gen 1 PHY is disabled to reduce
power consumption.
The polarity of this input is controlled via the CC_POL
pin. If CC_POL is low, this pin behaves as follows:
- 1: USB Type-C attach detected, turn respective
USB 3.2 Gen 1 PHY on.
- 0: No USB Type-C attach detected, turn respective USB 3.2 Gen 1 PHY off.
If CC_POL is high, this pin behaves as follows:
- 1: No USB Type-C attach detected, turn respective USB3.1 Gen 1 PHY off.
- 0: USB Type-C attach detected, turn respective
USB3.1 Gen 1 PHY on.
When using legacy USB Type-A and Type-B connectors,
pull these pins to 3.3V to permanently enable all USB 3.2
PHYs.
USB Type-C
Orientation
Control Input 1
AB1
I
(PD)
“Type-C Control Mode 1” USB Type-C orientation control
input.
This pin signals to the hub the orientation of the USB
Type-C connector. The hub enables the appropriate USB
3.1 Gen 1 PHY based upon the polarity of this signal, and
the assertion of the associated C_ATTACH[0:2] pin.
The polarity of this input is controlled via the CC_POL
pin. If CC_POL is low, this pin behaves as follows:
- 1: Enable USB 3.1 Gen 1 PHY B.
- 0: Enable USB 3.1 Gen 1 PHY A.
If CC_POL is high, this pin behaves as follows:
- 1: Enable USB 3.1 Gen 1 PHY A.
- 0: Enable USB 3.1 Gen 1 PHY B.
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USB5816
TABLE 3-6:
USB TYPE-C CONNECTOR CONTROLS (CONTINUED)
Name
Symbol
USB Type-C
Alternative
Orientation A
Attach 1
ATTACH_MUX1A
Buffer
Type
Description
I
(PD)
“Type-C Control Mode 2” Alternative USB Type-C attach
for “Orientation A” USB Type-C connections.
This mode of control is an alternative to the C_ATTACH[0:2] and AB1 pins. To select this mode, the
ALT_MUX_EN pin must be high.
When this pin asserted, the hub enables the “Orientation
A” USB 3.1 Gen 1 PHY of the associated port. When
there is no USB Type-C connection present and this pin
is not asserted, the associated USB 3.1 Gen 1 PHY is
disabled to reduce power consumption.
The polarity of this input is controlled via the CC_POL
pin.
If CC_POL is low, this pin behaves as follows:
- 1: USB Type-C attach detected, turn respective
“Orientation A” USB 3.1 Gen 1 PHY on.
- 0: No USB Type-C attach detected, turn respective “Orientation A” USB 3.1 Gen 1 PHY off.
If CC_POL is high, this pin behaves as follows:
- 1: No USB Type-C attach detected, turn respective “Orientation A” USB 3.1 Gen 1 PHY off.
- 0: USB Type-C attach detected, turn respective
“Orientation A” USB 3.1 Gen 1 PHY on.
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USB5816
TABLE 3-6:
USB TYPE-C CONNECTOR CONTROLS (CONTINUED)
Name
Symbol
USB Type-C
Alternative
Orientation B
Attach 1
ATTACH_MUX1B
Buffer
Type
Description
I
(PD)
“Type-C Control Mode 2” USB Type-C attach for “Orientation B” USB Type-C connections.
This mode of control is an alternative to the C_ATTACH[0:2] and AB1 pins.To select this mode, the
ALT_MUX_EN pin must be high.
When this pin asserted, the hub enables the “Orientation
B” USB 3.1 Gen 1 PHY of the associated port. When
there is no USB Type-C connection present and this pin
is not asserted, the associated USB 3.1 Gen 1 PHY is
disabled to reduce power consumption.
The polarity of this input is controlled via the CC_POL
pin.
If CC_POL is low, this pin behaves as follows:
- 1: USB Type-C attach detected, turn respective
“Orientation B” USB 3.1 Gen 1 PHY on.
- 0: No USB Type-C attach detected, turn respective “Orientation B” USB 3.1 Gen 1 PHY off.
If CC_POL is high, this pin behaves as follows:
- 1: No USB Type-C attach detected, turn respective “Orientation B” USB 3.1 Gen 1 PHY off.
- 0: USB Type-C attach detected, turn respective
“Orientation A” USB 3.1 Gen 1 PHY on.
Attach Polarity
Control
CC_POL
I
(PD)
USB C_ATTACH polarity control input.
If this pin is low, the C_ATTACH[0:2], AB1,
ATTACH_MUX1A, and ATTACH_MUX1B pins are
active high.
If this pin is high, the C_ATTACH[0:2], AB1,
ATTACH_MUX1A, and ATTACH_MUX1B pins are
active low.
This pin has an internal pull-down enabled. If the desired
strapping is to pull this pin low, then this pin may be left
unconnected.
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USB5816
TABLE 3-6:
USB TYPE-C CONNECTOR CONTROLS (CONTINUED)
Name
Symbol
USB Type-C
Control Mode
Selection
ALT_MUX_EN
Buffer
Type
I
(PD)
Description
USB Type-C control mode selection.
If this pin is low, the hub operates in “Type-C Control
Mode 1”. In “Type-C Control Mode 1”, the C_ATTACH[0:2] and AB1 pin functions are used.
If this pin is high, the hub operates in “Type-C Control
Mode 2”. In “Type-C Control Mode 2”, the
ATTACH_MUX1A and ATTACH_MUX1B pin functions
are used.
This pin has an internal pull-down enabled. If the desired
mode is “Type-C Control Mode 1”, then this pin may be
left unconnected.
TABLE 3-7:
MISCELLANEOUS PIN DESCRIPTIONS
Name
Symbol
Buffer
Type
SMBus/I2C
Clock
SMBCLK
I/O12
Description
SMBus/I2C Clock
The SMBus/I2C interface acts as SMBus slave or I2C
bridge dependent on the device configuration.
For information on how to configure this interface refer to
Section 3.5.1, CFG_STRAP Configuration.
SMBus/I2C Data
SMBDATA
I/O12
SMBus/I2C Data
The SMBus/I2C interface acts as SMBus slave or I2C
bridge dependent on the device configuration.
For information on how to configure this interface refer to
Section 3.5.1, CFG_STRAP Configuration.
USB Host
Port 1-0
Speed Indicator
HOST_TYPE_[1:0]
General
Purpose I/O
GPIO[1:9],
GPIO12,
GPIO[17:23],
GPIO[64:71]
I/O12
(PU/
PD)
General Purpose Inputs/Outputs
USB 2.0
Suspend State
Indicator
SUSP_IND
O12
USB 2.0 Suspend State Indicator
DS00002238E-page 18
O12
USB Host Port Speed Indicator
Tri-state: Not connected
0: USB 3.2 Gen 1
1: USB 2.0 / USB 1.1
Refer to Section 3.5.5, General Purpose input/Output
Configuration (GPIOx) for details.
SUSP_IND can be used as a sideband remote wakeup
signal for the host when in USB 2.0 suspend.
2016-2021 Microchip Technology Inc.
USB5816
TABLE 3-7:
MISCELLANEOUS PIN DESCRIPTIONS (CONTINUED)
Name
Symbol
Buffer
Type
Reset Control
Input
RESET_N
IS
Bias Resistor
RBIAS
I-R
External 25 MHz
Crystal Input
XTALI
ICLK
External 25 MHz crystal input
External 25 MHz
Reference Clock
Input
CLKIN
ICLK
External reference clock input.
External 25 MHz
Crystal Output
XTALO
OCLK
External 25 MHz crystal output
Test
TESTEN
I/O12
Test pin.
Description
Reset Control Input
This pin places the hub into Reset Mode when pulled low.
A 12.0 kΩ (+/- 1%) resistor is attached from ground to
this pin to set the transceiver’s internal bias settings.
Place the resistor as close to the device as possible with
a dedicated, low impedance connection to the GND
plane.
The device may alternatively be driven by a single-ended
clock oscillator. When this method is used, XTALO
should be left unconnected.
This signal is used for test purposes and must always be
connected to ground.
No Connect
NC
-
No connect.
For proper operation, this signal must be left unconnected.
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USB5816
TABLE 3-8:
CONFIGURATION STRAP PIN DESCRIPTIONS
Name
Symbol
Buffer
Type
Device Mode
Configuration
Strap
CFG_STRAP
I
Description
Device Mode Configuration Strap.
This configuration strap is used to set the device mode.
Refer to Section 3.5.1, CFG_STRAP Configuration for
details.
See Note 2
Port 6-1 D+
Disable
Configuration
Strap
PRT_DIS_P[6:1]
I
Port 6-1 D+ Disable Configuration Strap.
These configuration straps are used in conjunction with
the corresponding PRT_DIS_M[6:1] straps to disable the
related port (6-1). Refer to Section Section 3.5.2, Port
Disable Configuration (PRT_DIS_P[6:1] /
PRT_DIS_M[6:1]) for more information.
See Note 2
Port 6-1 DDisable
Configuration
Strap
PRT_DIS_M[6:1]
I
Port 6-1 D- Disable Configuration Strap.
These configuration straps are used in conjunction with
the corresponding PRT_DIS_P[6:1] straps to disable the
related port (6-1). Refer to Section 3.5.2, Port Disable
Configuration (PRT_DIS_P[6:1] / PRT_DIS_M[6:1]) for
more information.
See Note 2
Non-Removable
Ports
Configuration
Strap
CFG_NON_REM
Battery Charging
Configuration
Strap
CFG_BC_EN
I
Configuration strap to control number of reported nonremoval ports. See Section 3.5.3, Non-Removable Port
Configuration (CFG_NON_REM)
See Note 2
I
Configuration strap to control number of BC 1.2 enabled
downstream ports. See Section 3.5.4, Battery Charging
Configuration (CFG_BC_EN)
See Note 2
Note 2:Configuration strap values are latched on Power-On Reset (POR) and the rising edge of RESET_N
(external chip reset). Configuration straps are identified by an underlined symbol name. Signals that function
as configuration straps must be augmented with an external resistor when connected to a load. Refer to
Section 3.5, Configuration Straps and Programmable Functions for additional information.
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USB5816
TABLE 3-9:
POWER AND GROUND PIN DESCRIPTIONS
Name
Symbol
Buffer
Type
+3.3V Power
Supply Input
VDD33
P
+1.2V Core
Power Supply
Input
VDD12
Ground
GND
Description
+3.3 V power and internal regulator input
Refer to Section 4.1, Power Connections for power connection information
P
+1.2 V core power
Refer to Section 4.1, Power Connections for power connection information.
P
Common ground.
This exposed pad must be connected to the ground plane
with a via array.
3.4
Buffer Type Descriptions
TABLE 3-10:
USB5816 BUFFER TYPE DESCRIPTIONS
BUFFER
DESCRIPTION
I
Input.
IS
Input with Schmitt trigger.
O12
Output buffer with 12 mA sink and 12 mA source.
OD12
Open-drain output with 12 mA sink
PU
50 μA (typical) internal pull-up. Unless otherwise noted in the pin description, internal
pull-ups are always enabled.
Internal pull-up resistors prevent unconnected inputs from floating. Do not rely on
internal resistors to drive signals external to the device. When connected to a load that
must be pulled high, an external resistor must be added.
PD
50 μA (typical) internal pull-down. Unless otherwise noted in the pin description,
internal pull-downs are always enabled.
Internal pull-down resistors prevent unconnected inputs from floating. Do not rely on
internal resistors to drive signals external to the device. When connected to a load that
must be pulled low, an external resistor must be added.
ICLK
Crystal oscillator input pin
OCLK
Crystal oscillator output pin
I/O-U
Analog input/output defined in USB specification.
I-R
RBIAS.
Note:
Refer to Section 10.5, DC Specifications for individual buffer DC electrical characteristics.
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USB5816
3.5
Configuration Straps and Programmable Functions
Configuration straps are multi-function pins that are used during Power-On Reset (POR) or external chip reset
(RESET_N) to determine the default configuration of a particular feature. The state of the signal is latched following deassertion of the reset. Configuration straps are identified by an underlined symbol name. This section details the various
device configuration straps and associated programmable pin functions.
Note:
3.5.1
The system designer must guarantee that configuration straps meet the timing requirements specified in
Section 10.6.2, Power-On and Configuration Strap Timing and Section 10.6.3, Reset and Configuration
Strap Timing. If configuration straps are not at the correct voltage level prior to being latched, the device
may capture incorrect strap values.
CFG_STRAP CONFIGURATION
The CFG_STRAP pin is used to place the hub into preset modes of operation. The resistor options are a 200 kΩ pulldown, 200 kΩ pull-up, 10 kΩ pull-down, 10 kΩ pull-up, 10 Ω pull-down, and 10 Ω pull-up as shown in Table 3-11.
TABLE 3-11:
CFG_STRAP RESISTOR ENCODING
CFG_STRAP
Resistor Value
Config
200 kΩ Pull-Down
CONFIG1
Setting
I2C Bridging Mode
The SMBus interface will operate in Master Mode for use with USB to I2C bridging function. For more information on USB to I2C bridging with the USB5806,
refer to the “USB to I2C Using Microchip USB 3.1 Gen 1 Hubs” application note.
200 kΩ Pull-Up
CONFIG2
SMBus Slave Mode
The SMBus interface will operate in Slave Mode for use with hub configuration.
10 kΩ Pull-Down
CONFIG3
Unused, Reserved
10 kΩ Pull-Up
CONFIG4
Unused, Reserved
10 Ω Pull-Down
CONFIG5
Unused, Reserved
10 Ω Pull-Up
CONFIG6
Unused, Reserved
3.5.2
PORT DISABLE CONFIGURATION (PRT_DIS_P[6:1] / PRT_DIS_M[6:1])
The PRT_DIS_P[6:1] and PRT_DIS_M[6:1] configuration straps are used in conjunction to disable the related port (6-1).
For PRT_DIS_Px (where x is the corresponding port 6-1):
0 = Port x D+ Enabled
1 = Port x D+ Disabled
For PRT_DIS_Mx (where x is the corresponding port 6-1):
0 = Port x D- Enabled
1 = Port x D- Disabled
Note:
Both PRT_DIS_Px and PRT_DIS_Mx (where x is the corresponding port) must be tied to 3.3 V to disable
the associated downstream port. Disabling the USB 2.0 port will also disable the corresponding USB 3.2
Gen 1 port.
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USB5816
3.5.3
NON-REMOVABLE PORT CONFIGURATION (CFG_NON_REM)
The CFG_NON_REM configuration strap is used to configure the non-removable port settings of the device to one of
five settings. These modes are selected by the configuration of an external resistor on the CFG_NON_REM pin. The
resistor options are a 200 kΩ pull-down, 200 kΩ pull-up, 10 kΩ pull-down, 10 kΩ pull-up, 10 Ω pull-down and 10 Ω pullup as shown in Table 3-12.
TABLE 3-12:
CFG_NON_REM RESISTOR ENCODING
CFG_NON_REM Resistor Value
200 kΩ Pull-Down
Setting
All ports removable
200 kΩ Pull-Up
Port 2 non-removable
10 kΩ Pull-Down
Port 2, 3 non-removable
10 kΩ Pull-Up
Port 2, 3, 4, non-removable
10 Ω Pull-Down
Port 2, 3, 4, 5 non-removable
10 Ω Pull-Up
Port 2, 3, 4, 5, 6 non-removable
3.5.4
BATTERY CHARGING CONFIGURATION (CFG_BC_EN)
The CFG_BC_EN configuration strap is used to configure the battery charging port settings of the device to one of five
settings. These modes are selected by the configuration of an external resistor on the CFG_BC_EN pin. The resistor
options are a 200 kΩ pull-down, 200 kΩ pull-up, 10 kΩ pull-down, 10 kΩ pull-up, 10 Ω pull-down and 10 Ω pull-up as
shown in Table 3-13.
TABLE 3-13:
CFG_BC_EN RESISTOR ENCODING
CFG_BC_EN Resistor Value
Setting
200 kΩ Pull-Down
No battery charging
200 kΩ Pull-Up
Port 1 battery charging
10 kΩ Pull-Down
Port 1, 2 battery charging
10 kΩ Pull-Up
Port 1, 2, 3, battery charging
10 Ω Pull-Down
Port 1, 2, 3, 4 battery charging
10 Ω Pull-Up
Port 1, 2, 3, 4, 5, 6 battery charging
3.5.5
GENERAL PURPOSE INPUT/OUTPUT CONFIGURATION (GPIOx)
General Purpose Inputs/Outputs may be used for application specific purposes. Any given GPIO may operate as an
input or an output. Inputs can apply an internal 50kΩ pull-down or pull-up resistor. Outputs may drive low or drive high
(3.3V). GPIOs may be configured and manipulated during runtime (while enumerated to a host) in one of two ways:
• SMBus configuration
• USB to GPIO bridging
3.5.5.1
SMBus configuration
The SMBus slave interface may be used to write to internal registers that configure the state of the GPIO. Refer to the
“Configuration Options for Microchip USB58xx and USB59xx Hubs” application note for additional details.
3.5.5.2
USB to GPIO Bridging
USB to GPIO Bridging may be used to write to internal registers that configure the state of the GPIO. USB to GPIO
bridging operates via host communication to the hub’s internal Hub Feature Controller. Refer to the “USB to GPIO Bridging for Microchip USB 3.2 Gen 1 Hubs” application note for additional details.
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USB5816
4.0
DEVICE CONNECTIONS
4.1
Power Connections
Figure 4-1 illustrates the device power connections.
FIGURE 4-1:
DEVICE POWER CONNECTIONS
+3.3V
Supply
+1.2V
Supply
VDD33
3.3V Internal Logic
USB5816
4.2
VDD12
1.2V Internal Logic
VSS
SPI ROM Connections
Figure 4-2 illustrates the device SPI ROM connections. Refer to Section 7.1 “SPI Master Interface” for additional information on this device interface.
FIGURE 4-2:
SPI ROM CONNECTIONS
SPI_CE_N
CE#
SPI_CLK
CLK
USB5816
4.3
SPI ROM
SPI_DO
DI
SPI_DI
DO
SMBus Slave Connections
Figure 4-3 illustrates the device SMBus slave connections. Refer to Section 7.2 “SMBus Slave Interface” for additional information on this device interface.
FIGURE 4-3:
SMBUS SLAVE CONNECTIONS
+3.3V
10K
Clock
SMCLK
USB5816
+3.3V
10K
SMDAT
DS00002238E-page 24
SMBus
Master
Data
2016-2021 Microchip Technology Inc.
USB5816
5.0
MODES OF OPERATION
The device provides two main modes of operation: Standby Mode and Hub Mode. These modes are controlled via the
RESET_N pin, as shown in Table 5-1.
TABLE 5-1:
MODES OF OPERATION
RESET_N Input
Summary
0
Standby Mode: This is the lowest power mode of the device. No functions are active
other than monitoring the RESET_N input. All port interfaces are high impedance and
the PLL is halted. Refer to Section 8.3.2, External Chip Reset (RESET_N) for additional
information on RESET_N.
1
Hub (Normal) Mode: The device operates as a configurable USB hub with battery
charger detection. This mode has various sub-modes of operation, as detailed in
Figure 5-1. Power consumption is based on the number of active ports, their speed,
and amount of data transferred.
The flowchart in Figure 5-1 details the modes of operation and how the device traverses through the Hub Mode stages
(shown in bold). The remaining sub-sections provide more detail on each stage of operation.
FIGURE 5-1:
HUB BOOT FLOWCHART
RESET_N deasserted
SPI
Signature
Present?
YES
Run from
External ROM
NO
(SPI_INIT)
Load Config from
Internal ROM
Modify Config
Based on OTP
(CFG_RD)
Do SMBus or I2C
initialization
YES
Load Config from
External ROM
Modify Config
Based on psuedoOTP
(Ext_CFG
_RD)
CFG_STRAP for
SMBus Slave?
NO
(STRAP)
No
SOC Done?
YES
(SOC_CFG)
Combine OTP
Config Data
(OTP_CFG)
Hub Connect
NORMAL operation
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USB5816
5.1
Standby Mode
If the RESET_N pin is asserted, the hub will be in Standby Mode. This mode provides a very low power state for maximum power efficiency when no signaling is required. This is the lowest power state. In Standby Mode all downstream
ports are disabled, the USB data pins are held in a high-impedance state, all transactions immediately terminate (no
states saved), all internal registers return to their default state, the PLL is halted, and core logic is powered down in order
to minimize power consumption. Because core logic is powered off, no configuration settings are retained in this mode
and must be re-initialized after RESET_N is negated high.
5.2
SPI Initialization Stage (SPI_INIT)
The first stage, the initialization stage, occurs on the deassertion of RESET_N. In this stage, the internal logic is reset,
the PLL locks if a valid clock is supplied, and the configuration registers are initialized to their default state. The internal
firmware then checks for an external SPI ROM. The firmware looks for an external SPI flash device that contains a valid
signature of “2DFU” (device firmware upgrade) beginning at address 0xFFFA. If a valid signature is found, then the
external ROM is enabled and the code execution begins at address 0x0000 in the external SPI device. If a valid signature is not found, then execution continues from internal ROM (CFG_RD stage).
When using an external SPI ROM, a 1 Mbit, 60 MHz or faster ROM must be used. Both 1- and 2-bit SPI operation are
supported. For optimum throughput, a 2-bit SPI ROM is recommended. Both mode 0 and mode 3 SPI ROMs are also
supported.
If the system is not strapped for SPI Mode, code execution will continue from internal ROM (CFG_RD stage).
5.3
Configuration Read Stage (CFG_RD)
In this stage, the internal firmware loads the default values from the internal ROM and then uses the configuration strapping options to override the default values. Refer to Section 3.5, Configuration Straps and Programmable Functions for
information on usage of the various device configuration straps.
5.4
Strap Read Stage (STRAP)
In this stage, the firmware registers the configuration strap settings and checks the state of CFG_STRAP. If
CFG_STRAP is set for CONFIG2, then the hub will check the state of the SMBDATA and SMBCLK pins. If 10k pull-up
resistors are detected on both pins, the device will enter the SOC_CFG stage. If 10k pull-up resistors are not detected
on both pins, the hub will transition to the OTP_CFG stage instead.
5.5
SOC Configuration Stage (SOC_CFG)
In this stage, the SOC can modify any of the default configuration settings specified in the integrated ROM, such as USB
device descriptors and port electrical settings.
There is no time limit on this mode. In this stage the firmware will wait indefinitely for the SMBus/I2C configuration. When
the SOC has completed configuring the device, it must write to register 0xFF to end the configuration.
5.6
OTP Configuration Stage (OTP_CFG)
Once the SOC has indicated that it is done with configuration, all configuration data is combined in this stage. The
default data, the SOC configuration data, and the OTP data are all combined in the firmware and the device is programmed.
After the device is fully configured, it will go idle and then into suspend if there is no VBUS or Hub.Connect present.
Once VBUS is present, and battery charging is enabled, the device will transition to the Battery Charger Detection
Stage. If VBUS is present, and battery charging is not enabled, the device will transition to the Connect stage.
5.7
Hub Connect Stage (Hub.Connect)
Once the CHGDET stage is completed, the device enters the Hub Connect stage. USB connect can be initiated by
asserting the VBUS pin function high. The device will remain in the Hub Connect stage indefinitely until the VBUS pin
function is deasserted.
DS00002238E-page 26
2016-2021 Microchip Technology Inc.
USB5816
5.8
Normal Mode
Lastly, the hub enters Normal Mode of operation. In this stage full USB operation is supported under control of the USB
Host on the upstream port. The device will remain in the normal mode until the operating mode is changed by the system.
2016-2021 Microchip Technology Inc.
DS00002238E-page 27
USB5816
6.0
DEVICE CONFIGURATION
The device supports a large number of features (some mutually exclusive), and must be configured in order to correctly
function when attached to a USB host controller. The hub can be configured either internally or externally depending on
the implemented interface.
Microchip provides a comprehensive software programming tool, Pro-Touch2, for configuring the USB5816 functions,
registers and OTP memory. All configuration is to be performed via the Pro-Touch2 programming tool. For additional
information on the Pro-Touch2 programming tool, refer to Software Libraries within Microchip USB5816 product page
at www.microchip.com/USB5816.
Note:
6.1
Device configuration straps and programmable pins are detailed in Section 3.5, Configuration Straps and
Programmable Functions.
Refer to Section 7.0, Device Interfaces for detailed information on each device interface.
Customer Accessible Functions
The following functions are available to the customer via the Pro-Touch2 Programming Tool.
Note:
6.1.1
6.1.1.1
For additional programming details, refer to the Pro-Touch2 programming tool User’s Guide.
USB ACCESSIBLE FUNCTIONS
I2C Bridging Access over USB
Access to I2C devices is performed as a pass-through operation from the USB Host. The device firmware has no knowledge of the operation of the attached I2C device. For more information, refer to the Microchip USB5816 product page
and Pro-Touch2 at www.microchip.com/USB5816.
Note:
6.1.1.2
Refer to Section 7.3, I2C Bridge Interface for additional information on the I2C interface.
SPI Access over USB
Access to an attached SPI device is performed as a pass-through operation from the USB Host. The device firmware
has no knowledge of the operation of the attached SPI device. For more information, refer to the Microchip USB5816
product page and SDK at www.microchip.com/USB5816.
Note:
6.1.1.3
Refer to Section 7.1, SPI Master Interface for additional information on the SPI.
OTP Access
The OTP ROM in the device is accessible via the USB bus during normal runtime operation or SMBus during the
SOC_CFG stage. For more information, refer to the Microchip USB5816product page or the Pro-Touch2 User’s Guide.
6.1.1.4
Battery Charging Access over USB
The Battery charging behavior of the device can be dynamically changed by the USB Host when something other than
the preprogrammed or OTP programmed behavior is desired. For more information, refer to the Microchip
USB5816product page or the Pro-Touch2 User’s Guide.
6.1.2
SMBUS ACCESSIBLE FUNCTIONS
OTP access and configuration of specific device functions are possible via the USB5816 SMBus slave interface. All OTP
parameters can be modified via the SMBus Host. For more information refer to the Microchip USB5816 product page.
DS00002238E-page 28
2016-2021 Microchip Technology Inc.
USB5816
7.0
DEVICE INTERFACES
The USB5816 provides multiple interfaces for configuration and external memory access. This section details the various device interfaces and their usage:
• SPI Master Interface
• SMBus Slave Interface
• I2C Bridge Interface
Note:
For details on how to enable each interface, refer to Section 3.5, Configuration Straps and Programmable
Functions.
For information on device connections, refer to Section 4.0, Device Connections. For information on device
configuration, refer to Section 6.0, Device Configuration.
Microchip provides a comprehensive software programming tool, Pro-Touch2, for configuring the USB5816
functions, registers and OTP memory. All configuration is to be performed via the Pro-Touch2 programming
tool. For additional information on the Pro-Touch2 programming tool, refer to Software Libraries within
Microchip USB5816 product page at www.microchip.com/USB5816.
7.1
SPI Master Interface
The device is capable of code execution from an external SPI ROM. When configured for SPI Mode, on power up the
firmware looks for an external SPI flash device that contains a valid signature of 2DFU (device firmware upgrade) beginning at address 0xFFFA. If a valid signature is found, then the external ROM is enabled and the code execution begins
at address 0x0000 in the external SPI device. If a valid signature is not found, then execution continues from internal
ROM.
Note:
7.2
For SPI timing information, refer to Section 10.6.7, SPI Timing.
SMBus Slave Interface
The device includes an integrated SMBus slave interface, which can be used to access internal device run time registers
or program the internal OTP memory. SMBus slave detection is accomplished by setting the CFG_STRAP in the correct
configuration followed by detection of pull-up resistors on both the SMDAT and SMCLK signals during the hub’s bootup sequence. Refer to Section 3.5.1, CFG_STRAP Configuration for additional information.
Note:
7.3
All configuration is to be performed via the Pro-Touch2 programming tool. For additional information on the
Pro-Touch2 programming tool, refer to Software Libraries within Microchip USB5816 product page at
www.microchip.com/USB5816.
I2C Bridge Interface
The I2C Bridge interface implements a subset of the I2C Master Specification (Please refer to the Philips Semiconductor
Standard I2C-Bus Specification for details on I2C bus protocols). The I2C Bridge conforms to the Fast-Mode I2C Specification (400 kbit/s transfer rate and 7-bit addressing) for protocol and electrical compatibility. The device acts as the
master and generates the serial clock SCL, controls the bus access (determines which device acts as the transmitter
and which device acts as the receiver), and generates the START and STOP conditions. The I2C Bridge interface frequency is configurable through the I2C Bridging commands. I2C Bridge frequencies are derived from the formula
626KHz/n, where n is any integer from 1 to 256. Refer to Section 3.5.1, CFG_STRAP Configuration for additional information.
Note:
Extensions to the I2C Specification are not supported.
All configuration is to be performed via the Pro-Touch2 programming tool. For additional information on the
Pro-Touch2 programming tool, refer to Software Libraries within Microchip USB5816 product page at
www.microchip.com/USB5816.
2016-2021 Microchip Technology Inc.
DS00002238E-page 29
USB5816
8.0
FUNCTIONAL DESCRIPTIONS
This section details various USB5816 functions, including:
•
•
•
•
•
•
•
USB Type-C Receptacle Support
Battery Charging
Resets
Link Power Management (LPM)
Remote Wakeup Indicator
Port Control Interface
Port Split
8.1
USB Type-C Receptacle Support
The USB5816 has built-in support for the USB Type-C receptacle. There are 3 fundamental configurations:
• External USB 3.2 Gen 1 Multiplexer
• Internal USB3.1 Gen 1 Multiplexer, “Type-C Control Mode 1”
• Internal USB 3.1 Gen 1 Multiplexer, “Type-C Control Mode 2”
8.1.1
EXTERNAL USB 3.2 GEN 1 MULTIPLEXER
C_ATTACH[0:2] pins are used to signal to the hub when a valid USB Type-C connection has been detected. This functionality requires an external USB Type-C controller such as a Microchip UTC2000 to monitor the USB Type-C receptacle for a valid attach. This signal is used to enable and disable clocking to the USB 3.2 Gen 1 PHY in order to reduce
power consumption when there is no USB Type-C attach.
The polarity of the C_ATTACH[0:2] pins are controlled by the CC_POL pin. See Table 3-6 for details.
A diagram of a USB Type-C Downstream Facing Port with a USB5816, Microchip UTC2000, and external multiplexer
is shown in Figure 8-1.
A diagram of a USB Type-C Upstream Facing Port with a USB5816, Microchip UTC2000, and external multiplexer is
shown in Figure 8-2.
FIGURE 8-1:
DFP TYPE-C PORT WITH MICROCHIP UTC2000 AND EXTERNAL MUX
USB Type-C®
USB Type-C
GENERIC
PORT PWR
CTLR
PO WER
External Mux
Downstream Port
OCS
SSTX+
SSTX-
SSTX+
SSTX-
SSRX+
SSRX-
SSRX+
SSRX-
A/B
VBUS
SSTXA+
SSTXA-
SSTXA+
SSTXA-
SSRXA+
SSRXA-
SSRXA+
SSRXA-
SSTXB+
SSTXB-
SSTXB+
SSTXB-
SSRXB+
SSRXB-
SSRXB+
SSRXB-
MUX
D+
DPRTCTL
C_ATTACH
ALT_MUX_EN
CC_PO L
DS00002238E-page 30
D+
D-
3.3V
ENABLE
OCS#
PLUG_OR#
PPC_EN
CC1
CC2
CC1
CC2
UTC2000
DFP Mode
2016-2021 Microchip Technology Inc.
USB5816
FIGURE 8-2:
UFP TYPE-C PORT WITH MICROCHIP UTC2000 & EXTERNAL MUX
USB Type-C
USB Type-C
External Mux
Upstream Port
VBUS
SSTXA+
SSTXA-
SSTXA+
SSTXA-
SSRXA+
SSRXA-
SSRXA+
SSRXA-
SSTXB+
SSTXB-
SSTXB+
SSTXB-
SSRXB+
SSRXB-
SSRXB+
SSRXBA/B
VBUS_DET
SSTX+
SSTX-
SSTX+
SSTX-
SSRX+
SSRX-
SSRX+
SSRX-
MUX
D+
DPLUG_
ORIENTATION#
CC1
CC2
CC1
CC2
UTC2000
UFP Mode
3.3V
D+
D-
C_ATTACH0
CONNECTED#
8.1.2
INTERNAL USB3.1 GEN 1 MULTIPLEXER, “TYPE-C CONTROL MODE 1”
“Type-C Control Mode 1” is enabled by setting the ALT_MUX_EN signal low or leaving it floating. While in “Type-C Control Mode 1”, the C_ATTACH1 and AB1 pins are used together to signal to the hub when a valid USB Type-C connection
has been detected and in what orientation the connection has been detected. This functionality requires an external
USB Type-C controller such as a Microchip UTC2000 to monitor the USB Type-C receptacle for a valid attach. These
signal are used to enable/disable the USB 3.1 Gen 1 PHYs appropriately according to the detected Type-C attach and
orientation. Unused USB 3.1 Gen 1 PHYs are disabled to conserve power.
The polarity of the C_ATTACH1 pins and AB1 are controlled by the CC_POL pin. See Table 3-6 for details.
A diagram of a USB Type-C Downstream Facing Port with the USB5816, Microchip UTC2000, and internal multiplexer
operating in “Type-C Control Mode 1” is shown in Figure 8-3.
2016-2021 Microchip Technology Inc.
DS00002238E-page 31
USB5816
FIGURE 8-3:
DFP TYPE-C PORT WITH MICROCHIP UTC2000 & INTERNAL MUX (MODE 1)
USB Type-C®
USB Type-C
GENERIC
PORT PWR
CTLR
POWER
Internal Mux
Downstream Port
OCS
VBUS
SSTXA+
SSTXASSRXA+
SSRXA-
SSTXA+
SSTXASSRXA+
SSRXA-
SSTXB+
SSTXBSSRXB+
SSRXB-
SSTXB+
SSTXBSSRXB+
SSRXB-
D+
D-
D+
D-
PRTCTL
3.3V
ENABLE
OCS#
AB
C_ATTACH
USB Type-C
Control Mode 1
PLUG_OR#
PPC_EN
CC1
CC2
CC1
CC2
ALT_MUX_EN
CC_POL
UTC2000
UFP Mode
8.1.3
INTERNAL USB 3.1 GEN 1 MULTIPLEXER, “TYPE-C CONTROL MODE 2”
“Type-C Control Mode 2” is enabled by setting the ALT_MUX_EN signal high. While in “Type-C Control Mode 2”, the
ATTACH_MUX1A and ATTACH_MUX1B pins are used to signal to the hub when a valid USB Type-C connection has
been detected and in what orientation the connection has been detected. This functionality requires an external USB
Type-C controller (this mode not directly supported by UTC2000) to monitor the USB Type-C receptacle for a valid
attach. These signal are used to enable/disable the USB 3.1 Gen 1 PHYs appropriately according to the detected TypeC attach and orientation. Unused USB 3.1 Gen 1 PHYs are disabled to conserve power.
The polarity of the ATTACH_MUX1A pins and ATTACH_MUX1B are controlled by the CC_POL pin. See Table 3-6 for
details.
A diagram of a USB Type-C Downstream Facing Port with internal multiplexer operating in “Type-C Control Mode 2”
with the USB5816 is shown in Figure 8-4.
DS00002238E-page 32
2016-2021 Microchip Technology Inc.
USB5816
FIGURE 8-4:
DFP TYPE-C PORT WITH GENERIC TYPE-C CONTROLLER AND INTERNAL MUX
(MODE 2)
USB Type-C®
USB Type-C
GENERIC
PORT PWR
CTLR
PO WER
Internal Mux
Downstream Port
OCS
VBUS
SSTXA+
SSTXASSRXA+
SSRXA-
SSTXA+
SSTXASSRXA+
SSRXA-
SSTXB+
SSTXBSSRXB+
SSRXB-
SSTXB+
SSTXBSSRXB+
SSRXB-
D+
D-
D+
D-
PRTCTL
3.3V
ENABLE
OCS#
AB
C_ATTACH
ALT_MUX_EN
CC_PO L
8.2
PLUG_OR#
PPC_EN
CC1
CC2
CC1
CC2
UTC2000
UFP Mode
Battery Charging
The device can be configured by an OEM to have any of the downstream ports support battery charging. The hub’s role
in battery charging is to provide acknowledgment to a device’s query as to whether the hub system supports USB battery
charging. The hub silicon does not provide any current or power FETs or any additional circuitry to actually charge the
device. Those components must be provided externally by the OEM.
FIGURE 8-5:
BATTERY CHARGING EXTERNAL POWER SUPPLY
INT
DC Power
SCL
Microchip
SOC
Hub
SDA
VBUS[n]
If the OEM provides an external supply capable of supplying current per the battery charging specification, the hub can
be configured to indicate the presence of such a supply from the device. This indication, via the PRT_CTL[6:1] pins, is
on a per port basis. For example, the OEM can configure two ports to support battery charging through high current
power FETs and leave the other two ports as standard USB ports.
For additional information, refer to the Microchip USB5816 Battery Charging application note on the Microchip.com
USB5816 product page www.microchip.com/USB5816.
2016-2021 Microchip Technology Inc.
DS00002238E-page 33
USB5816
8.3
Resets
• Power-On Reset (POR)
• External Chip Reset (RESET_N)
• USB Bus Reset
8.3.1
POWER-ON RESET (POR)
A power-on reset occurs whenever power is initially supplied to the device, or if power is removed and reapplied to the
device. A timer within the device will assert the internal reset per the specifications listed in Section 10.6.2, Power-On
and Configuration Strap Timing.
8.3.2
EXTERNAL CHIP RESET (RESET_N)
A valid hardware reset is defined as assertion of RESET_N, after all power supplies are within operating range, per the
specifications in Section 10.6.3, Reset and Configuration Strap Timing. While reset is asserted, the device (and its associated external circuitry) enters Standby Mode and consumes minimal current.
Assertion of RESET_N causes the following:
1.
2.
3.
4.
5.
The PHY is disabled and the differential pairs will be in a high-impedance state.
All transactions immediately terminate; no states are saved.
All internal registers return to the default state.
The external crystal oscillator is halted.
The PLL is halted.
Note:
All power supplies must have reached the operating levels mandated in Section 10.2, Operating Conditions**, prior to (or coincident with) the assertion of RESET_N.
8.3.3
USB BUS RESET
In response to the upstream port signaling a reset to the device, the device performs the following:
1.
2.
3.
4.
Sets default address to 0.
Sets configuration to Unconfigured.
Moves device from suspended to active (if suspended).
Complies with the USB Specification for behavior after completion of a reset sequence.
The host then configures the device in accordance with the USB Specification.
Note:
8.4
The device does not propagate the upstream USB reset to downstream devices.
Link Power Management (LPM)
The device supports the L0 (On), L1 (Sleep), and L2 (Suspend) link power management states. These supported LPM
states offer low transitional latencies in the tens of microseconds versus the much longer latencies of the traditional USB
suspend/resume in the tens of milliseconds. The supported LPM states are detailed in Table 8-1.
TABLE 8-1:
LPM STATE DEFINITIONS
State
Description
Entry/Exit Time to L0
L2
Suspend
Entry: ~3 ms
Exit: ~2 ms (from start of RESUME)
L1
Sleep
Entry:
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