USB7206
6-Port USB 3.2 Gen 2 Controller Hub
Highlights
• 6-Port USB Smart Hub with:
- ®Five Standard USB 3.2 Gen 2 downstream ports
- One Standard USB 2.0 downstream port
- Internal Hub Feature Controller enables:
-USB to I2C/SPI/I2S/GPIO bridge endpoint support
-USB to internal hub register write and read
• USB Link Power Management (LPM) support
• Programming of firmware image to external SPI
memory device from USB host
• USB-IF Battery Charger revision 1.2 support on
downstream ports (DCP, CDP, SDP)
• Enhanced OEM configuration options available
through either OTP or external SPI memory
• Available in 100-pin (12mm x 12mm) VQFN
RoHS compliant package
• Commercial and industrial grade temperature
support
Target Applications
•
•
•
•
•
Standalone USB Hubs
Laptop Docks
PC Motherboards
PC Monitor Docks
Multi-function USB 3.2 Gen 2 Peripherals
Key Benefits
• USB 3.2 Gen 2 compliant 10 Gbps, 5 Gbps,
480 Mbps, 12 Mbps, and 1.5Mbps operation
- 5V tolerant USB 2.0 pins
- 1.21V tolerant USB 3.2 Gen 2 pins
- Integrated termination and pull-up/down resistors
-
2018 - 2020 Microchip Technology Inc.
• Supports battery charging of most popular battery
powered devices on all ports
- USB-IF Battery Charging rev. 1.2 support
(DCP, CDP, SDP)
- Apple® portable product charger emulation
- Chinese YD/T 1591-2006/2009 charger emulation
- European Union universal mobile charger support
- Supports additional portable devices
• On-chip Microcontroller
- manages I/Os, VBUS, and other signals
• 96kB RAM, 256kB ROM
• 8kB One-Time-Programmable (OTP) ROM
- Includes on-chip charge pump
• Configuration programming via OTP Memory, SPI
external memory, or SMBus
• FlexConnect
- The roles of the upstream and all downstream
ports are reversible on command
• USB Bridging
- USB to I2C, SPI, I2S, and GPIO
• PortSwap
- Configurable USB 2.0 differential pair signal swap
• PHYBoost
- Programmable USB transceiver drive strength for
recovering signal integrity
• VariSense
- Programmable USB receive sensitivity
• PortSplit
- USB 2.0 and USB 3.2 Gen 2 port operation can be
split for custom applications using embedded USB
3.x devices in parallel with USB 2.0 devices
• Compatible with Microsoft Windows 10, 8, 7, XP,
Apple OS X 10.4+, and Linux hub drivers
• Optimized for low-power operation and low thermal dissipation
• 100-pin VQFN package (12mm x 12mm)
DS00002875C-page 1
USB7206
TO OUR VALUED CUSTOMERS
It is our intention to provide our valued customers with the best documentation possible to ensure successful use of
your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced.
If you have any questions or comments regarding this publication, please contact the Marketing Communications
Department via E-mail at docerrors@microchip.com or fax the Reader Response Form in the back of this data
sheet to (480) 792-4150. We welcome your feedback.
Most Current Data Sheet
To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at:
http://www.microchip.com
You can determine the version of a data sheet by examining its literature number found on the bottom outside corner
of any page. The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000).
Errata
An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may
exist for current devices. As device/documentation issues become known to us, we will publish an errata sheet. The
errata will specify the revision of silicon and revision of document to which it applies.
To determine if an errata sheet exists for a particular device, please check with one of the following:
• Microchip’s Worldwide Web site; http://www.microchip.com
• Your local Microchip sales office (see last page)
When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using.
Customer Notification System
Register on our web site at www.microchip.com to receive the most current information on all of our products.
DS00002875C-page 2
2018 - 2020 Microchip Technology Inc.
USB7206
1.0
PREFACE
1.1
General Terms
TABLE 1-1:
GENERAL TERMS
Term
Description
ADC
Analog-to-Digital Converter
Byte
8 bits
CDC
Communication Device Class
CSR
Control and Status Registers
DFP
Downstream Facing Port
DWORD
32 bits
EOP
End of Packet
EP
Endpoint
FIFO
First In First Out buffer
FS
Full-Speed
FSM
Finite State Machine
GPIO
General Purpose I/O
HS
Hi-Speed
HSOS
High Speed Over Sampling
Hub Feature Controller
The Hub Feature Controller, sometimes called a Hub Controller for short is the internal
processor used to enable the unique features of the USB Controller Hub. This is not to
be confused with the USB Hub Controller that is used to communicate the hub status
back to the Host during a USB session.
I2C
Inter-Integrated Circuit
LS
Low-Speed
lsb
Least Significant Bit
LSB
Least Significant Byte
msb
Most Significant Bit
MSB
Most Significant Byte
N/A
Not Applicable
NC
No Connect
OTP
One Time Programmable
PCB
Printed Circuit Board
PCS
Physical Coding Sublayer
PHY
Physical Layer
PLL
Phase Lock Loop
RESERVED
Refers to a reserved bit field or address. Unless otherwise noted, reserved bits must
always be zero for write operations. Unless otherwise noted, values are not guaranteed when reading reserved bits. Unless otherwise noted, do not read or write to
reserved addresses.
SDK
Software Development Kit
SMBus
System Management Bus
UFP
Upstream Facing Port
UUID
Universally Unique IDentifier
WORD
16 bits
2018 - 2020 Microchip Technology Inc.
DS00002875C-page 3
USB7206
1.2
Buffer Types
TABLE 1-2:
BUFFER TYPES
Buffer Type
Description
I
Input.
IS
Input with Schmitt trigger.
O12
Output buffer with 12 mA sink and 12 mA source.
OD12
Open-drain output with 12 mA sink
PU
50 μA (typical) internal pull-up. Unless otherwise noted in the pin description, internal pullups are always enabled.
Internal pull-up resistors prevent unconnected inputs from floating. Do not rely on internal
resistors to drive signals external to the device. When connected to a load that must be
pulled high, an external resistor must be added.
PD
50 μA (typical) internal pull-down. Unless otherwise noted in the pin description, internal
pull-downs are always enabled.
Internal pull-down resistors prevent unconnected inputs from floating. Do not rely on
internal resistors to drive signals external to the device. When connected to a load that
must be pulled low, an external resistor must be added.
ICLK
Crystal oscillator input pin
OCLK
Crystal oscillator output pin
I/O-U
Analog input/output defined in USB specification.
I-R
RBIAS.
A
Analog.
AIO
Analog bidirectional.
P
Power pin.
DS00002875C-page 4
2018 - 2020 Microchip Technology Inc.
USB7206
1.3
Pin Reset States
The pin reset state definitions are detailed in Table 1-3. Refer to Section 3.1, Pin Assignments for details on individual
pin reset states.
TABLE 1-3:
PIN RESET STATE LEGEND
Symbol
AI
Analog input
AIO
Analog input/output
AO
Analog output
PD
Hardware enables pull-down
PU
Hardware enables pull-up
Y
Hardware enables function
Z
Hardware disables output driver (high impedance)
PU
Hardware enables internal pull-up
PD
Hardware enables internal pull-down
1.4
1.
2.
3.
4.
5.
Description
Reference Documents
Universal Serial Bus Revision 3.2 Specification, http://www.usb.org
Battery Charging Specification, Revision 1.2, Dec. 07, 2010, http://www.usb.org
I2C-Bus Specification, Version 1.1, http://www.nxp.com/documents/user_manual/UM10204.pdf
I2S-Bus Specification, http://www.sparkfun.com/datasheets/BreakoutBoards/I2SBUS.pdf
System Management Bus Specification, Version 1.0, http://smbus.org/specs
Note:
Additional USB7206 resources can be found on the Microchip USB7206 product page at www.microchip.com/USB7206.
2018 - 2020 Microchip Technology Inc.
DS00002875C-page 5
USB7206
2.0
INTRODUCTION
2.1
General Description
The Microchip USB7206 hub is a low-power, OEM configurable, USB 3.2 Gen 2 hub controller with 6 downstream ports
and advanced features for embedded USB applications. The USB7206 is fully compliant with the Universal Serial Bus
Revision 3.2 Specification and USB 2.0 Link Power Management Addendum. The USB7206 supports 10 Gbps SuperSpeed+ (SS+), 5 Gbps SuperSpeed (SS), 480 Mbps Hi-Speed (HS), 12 Mbps Full-Speed (FS), and 1.5 Mbps LowSpeed (LS) USB downstream devices on five standard USB 3.2 Gen 2 downstream ports and only legacy speeds (HS/
FS/LS) on one standard USB 2.0 downstream port.
The USB7206 supports the legacy USB speeds (HS/FS/LS) through a dedicated USB 2.0 hub controller that is the culmination of seven generations of Microchip hub feature controller design and experience with proven reliability, interoperability, and device compatibility. The SuperSpeed hub controller operates in parallel with the USB 2.0 controller,
decoupling the 10/5 Gbps SS+/SS data transfers from bottlenecks due to the slower USB 2.0 traffic.
The USB7206 enables OEMs to configure their system using “Configuration Straps.” These straps simplify the configuration process assigning default values to USB 3.2 Gen 2 ports and GPIOs. OEMs can disable ports, enable battery
charging and define GPIO functions as default assignments on power up removing the need for OTP or external SPI
ROM.
The USB7206 supports downstream battery charging. The USB7206 integrated battery charger detection circuitry supports the USB-IF Battery Charging (BC1.2) detection method and most Apple devices. The USB7206 provides the battery charging handshake and supports the following USB-IF BC1.2 charging profiles:
• DCP: Dedicated Charging Port (Power brick with no data)
• CDP: Charging Downstream Port (1.5A with data)
• SDP: Standard Downstream Port (0.5A[USB 2.0]/0.9A[USB 3.2] with data)
Additionally, the USB7206 includes many powerful and unique features such as:
The Hub Feature Controller, an internal USB device dedicated for use as a USB to I2C/SPI/GPIO interface that allows
external circuits or devices to be monitored, controlled, or configured via the USB interface.
FlexConnect, which provides flexible connectivity options. One of the USB7206’s downstream ports can be reconfigured to become the upstream port, allowing master capable devices to control other devices on the hub.
PortSwap, which adds per-port programmability to USB differential-pair pin locations. PortSwap allows direct alignment
of USB signals (D+/D-) to connectors to avoid uneven trace length or crossing of the USB differential signals on the
PCB.
PHYBoost, which provides programmable levels of Hi-Speed USB signal drive strength
in the downstream port transceivers. PHYBoost attempts to restore USB signal integrity
in a compromised system environment. The graphic on the right shows an example of
Hi-Speed USB eye diagrams before and after PHYBoost signal integrity restoration. in
a compromised system environment.
VariSense, which controls the Hi-Speed USB receiver sensitivity enabling programmable levels of USB signal receive
sensitivity. This capability allows operation in a sub-optimal system environment, such as when a captive USB cable is
used.
Port Split, which allows for the USB 3.2 Gen 2 and USB 2.0 portions of downstream ports 3, 4, and 5 to operate independently and enumerate two separate devices in parallel in special applications.
DS00002875C-page 6
2018 - 2020 Microchip Technology Inc.
USB7206
The USB7206 can be configured for operation through internal default settings. Custom OEM configurations are supported through external SPI ROM or OTP ROM. All port control signal pins are under firmware control in order to allow
for maximum operational flexibility and are available as GPIOs for customer specific use.
The USB7206 is available in commercial (0°C to +70°C) and industrial (-40°C to +85°C) temperature ranges. An internal
block diagram of the USB7206 in an upstream Type-B application is shown in Figure 2-1.
FIGURE 2-1:
USB7206 INTERNAL BLOCK DIAGRAM - UPSTREAM TYPE-B APPLICATION
P0
B
+3.3 V
PHY0 PHY0
VCORE
USB3 USB2
Hub Controller Logic
25 Mhz
PHY1 PHY1
PHY2 PHY2
PHY3 PHY3
PHY4 PHY4
PHY5 PHY5
HFC
PHY
PHY6
Hub Feature Controller OTP
GPIO
I2 C
SPI
I2S
Mux
P1
A
Note:
P2
A
P3
A
P4
A
P5
A
P6
A
All port numbering in this document is LOGICAL port numbering with the device in the default configuration.
LOGICAL port numbering is the numbering as communicated to the USB host. It is the end result after any
port number remapping or port disabling. The PHYSICAL port number is the port number with respect to
the physical PHY on the chip. PHYSICAL port numbering is fixed and the settings are not impacted by
LOGICAL port renumbering/remapping. Certain port settings are made with respect to LOGICAL port numbering, and other port settings are made with respect to PHYSICAL port numbering. Refer to the “Configuration of USB7202/USB7206/USB725x” application note for details on the LOGICAL vs. PHYSICAL
mapping and additional configuration details.
2018 - 2020 Microchip Technology Inc.
DS00002875C-page 7
USB7206
3.0
PIN DESCRIPTIONS
3.1
Pin Assignments
RBIAS
VDD33
XTALI/CLK_IN
XTALO
ATEST
USB3UP_RXDM
USB3UP_RXDP
VCORE
USB3UP_TXDM
USB3UP_TXDP
USB2UP_DM
USB2UP_DP
VDD33
USB3DN_RXDM5
USB3DN_RXDP5
VCORE
USB3DN_TXDM5
USB3DN_TXDP5
USB2DN_DM5/PRT_DIS_M5
USB2DN_DP5/PRT_DIS_P5
NC
VDD33
VCORE
PF28
PF27
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
USB7206 100-VQFN PIN ASSIGNMENTS
100
FIGURE 3-1:
RESET_N
1
75
PF26
PF30/VBUS_MON_UP
2
74
PF29
PF31
3
73
SPI_D3/PF25
NC
4
72
SPI_D2/PF24
USB2DN_DP1/PRT_DIS_P1
5
71
USB2DN_DM1/PRT_DIS_M1
6
70
SPI_D0/CFG_BC_EN/PF22
USB3DN_TXDP1
7
69
SPI_CE_N/CFG_NON_REM/PF20
USB3DN_TXDM1
8
68
SPI_CLK/PF21
VCORE
9
67
VDD33
USB3DN_RXDP1
10
66
PF19
USB3DN_RXDM1
11
65
TEST3
NC
12
64
TEST2
NC
13
63
TEST1
USB2DN_DP2/PRT_DIS_P2
14
62
VDD33
USB2DN_DM2/PRT_DIS_M2
15
61
PF18
USB3DN_TXDP2
16
60
PF17
USB3DN_TXDM2
17
59
PF16
VCORE
18
58
PF15
USB3DN_RXDP2
19
57
PF14
USB3DN_RXDM2
20
56
PF13
CFG_STRAP1
21
55
VCORE
CFG_STRAP2
22
54
PF12
CFG_STRAP3
23
53
VDD33
TESTEN
24
52
PF11
VCORE
25
51
PF10
Note:
Microchip
USB7206
(Top View 100-VQFN)
34
35
36
37
38
39
40
41
42
43
44
45
46
USB2DN_DP4/PRT_DIS_P4
USB2DN_DM4/PRT_DIS_M4
USB3DN_TXDP4
USB3DN_TXDM4
VCORE
USB3DN_RXDP4
USB3DN_RXDM4
USB2DN_DM6/PRT_DIS_M6
USB2DN_DP6/PRT_DIS_P6
VDD33
PF3
PF4
PF5
50
33
USB3DN_RXDM3
PF9
32
USB3DN_RXDP3
49
31
VCORE
PF8
30
USB3DN_TXDM3
48
29
USB3DN_TXDP3
PF7
28
USB2DN_DM3/PRT_DIS_M3
47
27
PF6
26
VDD33
USB2DN_DP3/PRT_DIS_P3
Thermal slug connects to VSS
Configuration straps are identified by an underlined symbol name. Signals that function as configuration
straps must be augmented with an external resistor when connected to a load.
DS00002875C-page 8
2018 - 2020 Microchip Technology Inc.
USB7206
Pin Num
Pin Name
Reset
Pin Num
Pin Name
Reset
1
RESET_N
Z
51
PF10
PD
2
PF30/VBUS_MON_UP
Z
52
PF11
PD
3
PF31
Z
53
VDD33
Z
4
NC
AI
54
PF12
PD
5
USB2DN_DP1/PRT_DIS_P1
AIO PD
55
VCORE
Z
6
USB2DN_DM1/PRT_DIS_M1
AIO PD
56
PF13
PD
7
USB3DN_TXDP1
AO PD
57
PF14
PD
8
USB3DN_TXDM1
AO PD
58
PF15
PD
9
VCORE
Z
59
PF16
PD
10
USB3DN_RXDP1
AI PD
60
PF17
PD
11
USB3DN_RXDM1
AI PD
61
PF18
Z
12
NC
AI
62
VDD33
Z
13
NC
AI
63
TEST1
Z
14
USB2DN_DP2/PRT_DIS_P2
AIO PD
64
TEST2
Z
15
USB2DN_DM2/PRT_DIS_M2
AIO PD
65
TEST3
Z
16
USB3DN_TXDP2
AO PD
66
PF19
Z
17
USB3DN_TXDM2
AO PD
67
VDD33
Z
18
VCORE
Z
68
SPI_CLK/PF21
Z
19
USB3DN_RXDP2
AI PD
69
SPI_CE_N/CFG_NON_REM/PF20
PU
20
USB3DN_RXDM2
AI PD
70
SPI_D0/CFG_BC_EN/PF22
Z
21
CFG_STRAP1
Z
71
SPI_D1/PF23
Z
22
CFG_STRAP2
Z
72
SPI_D2/PF24
Z
23
CFG_STRAP3
Z
73
SPI_D3/PF25
Z
24
TESTEN
Z
74
PF29
Z
25
VCORE
Z
75
PF26
Z
26
VDD33
Z
76
PF27
Z
27
USB2DN_DP3/PRT_DIS_P3
AIO PD
77
PF28
Z
28
USB2DN_DM3/PRT_DIS_M3
AIO PD
78
VCORE
Z
29
USB3DN_TXDP3
AO PD
79
VDD33
Z
30
USB3DN_TXDM3
AO PD
80
NC
AI
31
VCORE
Z
81
USB2DN_DP5/PRT_DIS_P5
AIO PD
32
USB3DN_RXDP3
AI PD
82
USB2DN_DM5/PRT_DIS_M5
AIO PD
33
USB3DN_RXDM3
AI PD
83
USB3DN_TXDP5
AO PD
34
USB2DN_DP4/PRT_DIS_P4
AIO PD
84
USB3DN_TXDM5
AO PD
35
USB2DN_DM4/PRT_DIS_M4
AIO PD
85
VCORE
Z
36
USB3DN_TXDP4
AO PD
86
USB3DN_RXDP5
AI PD
37
USB3DN_TXDM4
AO PD
87
USB3DN_RXDM5
AI PD
38
VCORE
Z
88
VDD33
Z
39
USB3DN_RXDP4
AI PD
89
USB2UP_DP
AIO Z
40
USB3DN_RXDM4
AI PD
90
USB2UP_DM
AIO Z
41
USB2DN_DM6/PRT_DIS_M6
AIO PD
91
USB3UP_TXDP
AO PD
42
USB2DN_DP6/PRT_DIS_P6
AIO PD
92
USB3UP_TXDM
AO PD
43
VDD33
Z
93
VCORE
Z
44
PF3
Z
94
USB3UP_RXDP
AI PD
45
PF4
Z
95
USB3UP_RXDM
AI PD
46
PF5
Z
96
ATEST
AO
47
PF6
Z
97
XTALO
AO
48
PF7
Z
98
XTALI/CLK_IN
AI
49
PF8
Z
99
VDD33
Z
50
PF9
Z
100
RBIAS
AI
Exposed Pad (VSS) must be connected to ground.
2018 - 2020 Microchip Technology Inc.
DS00002875C-page 9
USB7206
3.2
Pin Descriptions
This section contains descriptions of the various USB7206 pins. The “_N” symbol in the signal name indicates that the
active, or asserted, state occurs when the signal is at a low voltage level. For example, RESET_N indicates that the
reset signal is active low. When “_N” is not present after the signal name, the signal is asserted when at the high voltage
level.
The terms assertion and negation are used exclusively. This is done to avoid confusion when working with a mixture of
“active low” and “active high” signal. The term assert, or assertion, indicates that a signal is active, independent of
whether that level is represented by a high or low voltage. The term negate, or negation, indicates that a signal is inactive.
The “If Unused” column provides information on how to terminate pins if they are unused in a customer design.
Buffer type definitions are detailed in Section 1.2, Buffer Types.
TABLE 3-1:
PIN DESCRIPTIONS
Name
Symbol
Buffer
Type
Description
If Unused
USB 3.2 Gen 2 Interfaces
Upstream USB
3.2 Gen 2 TX D+
USB3UP_TXDP
I/O-U
Upstream USB 3.2 Gen 2 Transmit Data
Plus.
Float
Upstream USB
3.2 Gen 2 TX D-
USB3UP_TXDM
I/O-U
Upstream USB 3.2 Gen 2 Transmit Data
Minus.
Float
Upstream USB
3.2 Gen 2 RX D+
USB3UP_RXDP
I/O-U
Upstream USB 3.2 Gen 2 Receive Data
Plus.
Weak pulldown to
GND
Upstream USB
3.2 Gen 2 RX D-
USB3UP_RXDM
I/O-U
Upstream USB 3.2 Gen 2 Receive Data
Minus.
Weak pulldown to
GND
Downstream
Ports 1-5 USB
3.2 Gen 2 TX D+
USB3DN_TXDP[1:5]
I/O-U
Downstream SuperSpeed+ Transmit Data
Plus, ports 1 through 5.
Float
Downstream
Ports 1-5 USB
3.2 Gen 2 TX D-
USB3DN_TXDM[1:5]
I/O-U
Downstream SuperSpeed+ Transmit Data
Minus, ports 1 through 5.
Float
Downstream
Ports 1-5 USB
3.2 Gen 2 RX D+
USB3DN_RXDP[1:5]
I/O-U
Downstream SuperSpeed+ Receive Data
Plus, ports 1 through 5.
Weak pulldown to
GND
Downstream
Ports 1-5 USB
3.2 Gen 2 RX D-
USB3DN_RXDM[1:5]
I/O-U
Downstream SuperSpeed+ Receive Data
Minus, ports 1 through 5.
Weak pulldown to
GND
USB 2.0 Interfaces
Upstream USB
2.0 D+
USB2UP_DP
I/O-U
Upstream USB 2.0 Data Plus (D+).
Mandatory
Note 3-6
Upstream USB
2.0 D-
USB2UP_DM
I/O-U
Upstream USB 2.0 Data Minus (D-).
Mandatory
Note 3-6
Downstream
Ports 1-6 USB
2.0 D+
USB2DN_DP[1:6]
I/O-U
Downstream USB 2.0 Ports 1-6 Data Plus
(D+).
Connect
directly to
3.3V
DS00002875C-page 10
2018 - 2020 Microchip Technology Inc.
USB7206
TABLE 3-1:
PIN DESCRIPTIONS (CONTINUED)
Name
Symbol
Buffer
Type
Downstream
Ports 1-6 USB
2.0 D-
USB2DN_DM[1:6]
I/O-U
Downstream USB 2.0 Ports 1-6 Data Minus
(D-)
Connect
directly to
3.3V
VBUS Detect
VBUS_MON_UP
IS
This signal detects the state of the upstream
bus power.
Not
Recommended.
If unused,
tie to a
3.3V rail
through a
10-100k
pull-up
resistor.
Description
If Unused
Externally, VBUS can be as high as 5.25 V,
which can be damaging to this pin. The
amplitude of VBUS must be reduced by a
voltage divider. The recommended voltage
divider is shown below.
43K
49.9K
VBUS_UP
VBUS_MON
_UP
For self-powered applications with a permanently attached host, this pin must be connected to either 3.3 V or 5.0 V through a
resistor divider to provide 3.3 V.
In embedded applications, VBUS_MON_UP
may be controlled (toggled) when the host
desires to renegotiate a connection without
requiring a full reset of the device.
SPI Interface
SPI Clock
SPI_CLK
I/O-U
SPI clock. If the SPI interface is enabled,
this pin must be driven low during reset.
Weak pulldown to
GND
SPI Data 3-0
SPI_D[3:0]
I/O-U
SPI Data 3-0. If the SPI interface is enabled,
these signals function as Data 3 through 0.
Note 3-1
Note 3-1
SPI Chip
Enable
SPI_CE_N
I/O12
Active low SPI chip enable input. If the SPI
interface is enabled, this pin must be driven
high in powerdown states.
Note 3-2
2018 - 2020 Microchip Technology Inc.
SPI_D0 operates as the
CFG_BC_EN strap if
external SPI memory is not
used. It must be terminated
with the selected strap
resistor to 3.3V or GND.
SPI_ D[1 :3] sh ou ld b e
connected to GND through
a weak pull-down.
Note 3-2
Operates
as
the
CFG_NON_REM strap if
external SPI memory is not
used. It must be terminated
with the selected strap
resistor to 3.3V or GND.
DS00002875C-page 11
USB7206
TABLE 3-1:
PIN DESCRIPTIONS (CONTINUED)
Name
Symbol
Buffer
Type
Description
If Unused
Miscellaneous
Programmable
Function Pins
PF[31:3]
Test 1
TEST1
I/O12
Programmable function pins.
Note 3-3
A
Test 1 pin.
This signal is used for test purposes and
must always be pulled-up to 3.3V via a 10
k resistor.
Test 2
TEST2
A
Test 2 pin.
This signal is used for test purposes and
must always be pulled-up to 3.3V via a 10
k resistor.
Test 3
TEST3
A
Note 3-3
If unused: depends on the
configured pin function.
R efe r to S e ctio n 3.3 .4,
P F [3 1 : 3 ] C o n fi g ur a ti o n
(CFG_STRAP[2:1])
Test 3 pin.
This signal is used for test purposes and
must always be pulled-up to 3.3V via a 10
k resistor.
Pull to 3.3V
through a
10 k
resistor
Pull to 3.3V
through a
10 k
resistor
Pull to 3.3V
through a
10 k
resistor
Reset Input
RESET_N
IS
This active low signal is used by the system
to reset the device.
Mandatory
Note 3-6
Bias Resistor
RBIAS
I-R
A 12.0 k 1.0% resistor is attached from
ground to this pin to set the transceiver’s
internal bias settings. Place the resistor as
close the device as possible with a dedicated, low impedance connection to the
ground plane.
Mandatory
Note 3-6
Test
TESTEN
I/O12
Test pin.
Connect to
GND
This signal is used for test purposes and
must always be connected to ground.
Analog Test
ATEST
A
Float
Analog test pin.
This signal is used for test purposes and
must always be left unconnected.
External 25 MHz
Crystal Input
XTALI
ICLK
External 25 MHz crystal input
Mandatory
Note 3-6
External 25 MHz
Reference Clock
Input
CLK_IN
ICLK
External reference clock input.
Mandatory
Note 3-6
DS00002875C-page 12
The device may alternatively be driven by a
single-ended clock oscillator. When this
method is used, XTALO should be left
unconnected.
2018 - 2020 Microchip Technology Inc.
USB7206
TABLE 3-1:
PIN DESCRIPTIONS (CONTINUED)
Name
Symbol
Buffer
Type
External 25 MHz
Crystal Output
XTALO
OCLK
No Connect
NC
-
Description
If Unused
External 25 MHz crystal output
Float
(only if single-ended
clock is
connected
to CLK_IN)
No connect.
No connect
For proper operation, this pin must be left
unconnected.
Configuration Straps
Port 6-1 D+
Disable
Configuration
Strap
PRT_DIS_P[6:1]
I
Port 6-1 D+ Disable Configuration Strap.
N/A
These configuration straps are used in conjunction with the corresponding
PRT_DIS_M[6:1] straps to disable the
related port (6-1). See Note 3-7.
Both USB data pins for the corresponding
port must be tied to 3.3V to disable the
associated downstream port.
Port 6-1 DDisable
Configuration
Strap
PRT_DIS_M[6:1]
I
Port 6-1 D- Disable Configuration Strap.
These configuration straps are used in conjunction with the corresponding
PRT_DIS_P[6:1] straps to disable the
related port (6-1). See Note 3-7.
Mandatory
Note 3-6
Both USB data pins for the corresponding
port must be tied to 3.3V to disable the
associated downstream port.
Non-Removable
Ports
Configuration
Strap
CFG_NON_REM
I
Non-Removable Ports Configuration Strap.
This configuration strap controls the number
of reported non-removable ports. See
Note 3-7 .
Note 3-4
2018 - 2020 Microchip Technology Inc.
Note 3-4
Mandatory if external SPI
memory is not used for
firmware execution. If
external SPI m emory is
used
for
firmware
execution,
then
configuration strap resistor
should be omitted.
DS00002875C-page 13
USB7206
TABLE 3-1:
PIN DESCRIPTIONS (CONTINUED)
Name
Symbol
Buffer
Type
Battery Charging
Configuration
Strap
CFG_BC_EN
I/O12
Description
Battery Charging Configuration Strap.
This configuration strap controls the number
of BC 1.2 enabled downstream ports. See
Note 3-7.
Note 3-5
Device Mode
Configuration
Straps 3-1
CFG_STRAP[3:1]
I
If Unused
Mandatory
Note 3-6
Mandatory if external SPI
memory is not used for
firmware execution. If
external SPI m emory is
used
for
firmware
execution,
then
configuration strap resistor
should be omitted.
Device Mode Configuration Straps 3-1.
These configuration straps are used to
select the device’s mode of operation. See
Note 3-7.
Mandatory
Note 3-6
Power/Ground
+3.3V I/O Power
Supply Input
VDD33
P
+3.3 V power and internal regulator input.
Mandatory
Note 3-6
Digital Core
Power Supply
Input
VCORE
P
Digital core power supply input.
Mandatory
Note 3-6
Ground
VSS
P
Common ground.
Mandatory
Note 3-6
This exposed pad must be connected to the
ground plane with a via array.
Note 3-6
Configuration strap values are latched on Power-On Reset (POR) and the rising edge of RESET_N
(external chip reset). Configuration straps are identified by an underlined symbol name. Signals that
function as configuration straps must be augmented with an external resistor when connected to a
load. For additional information, refer to Section 3.3, Configuration Straps and Programmable
Functions.
Note 3-7
Pin use is mandatory. Cannot be left unused.
DS00002875C-page 14
2018 - 2020 Microchip Technology Inc.
USB7206
3.3
Configuration Straps and Programmable Functions
Configuration straps are multi-function pins that are used during Power-On Reset (POR) or external chip reset
(RESET_N) to determine the default configuration of a particular feature. The state of the signal is latched following
deassertion of the reset. Configuration straps are identified by an underlined symbol name. This section details the various device configuration straps and associated programmable pin functions.
Note:
3.3.1
The system designer must guarantee that configuration straps meet the timing requirements specified in
Section 9.6.2, Power-On and Configuration Strap Timing and Section 9.6.3, Reset and Configuration Strap
Timing. If configuration straps are not at the correct voltage level prior to being latched, the device may
capture incorrect strap values.
PORT DISABLE CONFIGURATION (PRT_DIS_P[6:1] / PRT_DIS_M[6:1])
The PRT_DIS_P[6:1] / PRT_DIS_M[6:1] configuration straps are used in conjunction to disable the related port (6-1)
For PRT_DIS_Px (where x is the corresponding port 6-1):
0 = Port x D+ Enabled
1 = Port x D+ Disabled
For PRT_DIS_Mx (where x is the corresponding port 6-1):
0 = Port x D- Enabled
1 = Port x D- Disabled
Note:
3.3.2
Both PRT_DIS_Px and PRT_DIS_Mx (where x is the corresponding port) must be tied to 3.3 V to disable
the associated downstream port. Disabling the USB 2.0 port will also disable the corresponding USB 3.0
port.
NON-REMOVABLE PORT CONFIGURATION (CFG_NON_REM)
The CFG_NON_REM configuration strap is used to configure the non-removable port settings of the device to one of
six settings. These modes are selected by the configuration of an external resistor on the CFG_NON_REM pin. The
resistor options are a 200 kΩ pull-down, 200 kΩ pull-up, 10 kΩ pull-down, 10 kΩ pull-up, 10 Ω pull-down, and 10 Ω pullup, as shown in Table 3-2.
TABLE 3-2:
CFG_NON_REM RESISTOR ENCODING
CFG_NON_REM Resistor Value
Setting
200 kΩ Pull-Down
All ports removable
200 kΩ Pull-Up
Port 1 non-removable
10 kΩ Pull-Down
Ports 1, 2 non-removable
10 kΩ Pull-Up
Ports 1, 2, 3 non-removable
10 Ω Pull-Down
Ports 1, 2, 3, 4 non-removable
10 Ω Pull-Up
Ports 1, 2, 3, 4, 5, 6 non-removable
2018 - 2020 Microchip Technology Inc.
DS00002875C-page 15
USB7206
3.3.3
BATTERY CHARGING CONFIGURATION (CFG_BC_EN)
The CFG_BC_EN configuration strap is used to configure the battery charging port settings of the device to one of six
settings. These modes are selected by the configuration of an external resistor on the CFG_BC_EN pin. The resistor
options are a 200 kΩ pull-down, 200 kΩ pull-up, 10 kΩ pull-down, 10 kΩ pull-up, 10 Ω pull-down, and 10 Ω pull-up, as
shown in Table 3-3.
TABLE 3-3:
CFG_BC_EN RESISTOR ENCODING
CFG_BC_EN Resistor Value
Setting
200 kΩ Pull-Down
Battery charging not enable on any port
200 kΩ Pull-Up
BC1.2 DCP and CDP battery charging enabled on Port 1
10 kΩ Pull-Down
BC1.2 DCP and CDP battery charging enabled on Ports 1, 2
10 kΩ Pull-Up
BC1.2 DCP and CDP battery charging enabled on Ports 1, 2, 3
10 Ω Pull-Down
BC1.2 DCP and CDP battery charging enabled on Ports 1, 2, 3, 4
10 Ω Pull-Up
BC1.2 DCP and CDP battery charging enabled on Ports 1, 2, 3, 4, 5, 6
PF[31:3] CONFIGURATION (CFG_STRAP[2:1])
3.3.4
The USB7206 provides 29 programmable function pins (PF[31:3]). These pins can only be configured to 1 predefined
configuration via the CFG_STRAP[2:1] pins. This configuration is selected via external resistors on the
CFG_STRAP[2:1] pins, as detailed in Table 3-4. Resistor values and combinations not detailed in Table 3-4 are reserved
and should not be used.
Note:
CFG_STRAP3 is not used and must be pulled-down to ground via a 200 k resistor.
TABLE 3-4:
CFG_STRAP[2:1] RESISTOR ENCODING
Mode
CFG_STRAP2
Resistor Value
CFG_STRAP1
Resistor Value
Configuration 3
200 kΩ Pull-Down
10 kΩ Pull-Down
Note:
Configurations 1 and 2 are not used in the USB7206.
A summary of the configuration pin assignments is provided in Table 3-5. For details on behavior of each programmable
function, refer to Table 3-6.
DS00002875C-page 16
2018 - 2020 Microchip Technology Inc.
USB7206
TABLE 3-5:
Pin
PF[31:3] FUNCTION ASSIGNMENT
Configuration 3
PF3
I2S_SDI
PF4
I2S_SDO
PF5
I2S_SCK
PF6
I2S_LRCK
PF7
I2S_MCLK
PF8
NC
PF9
NC
PF10
PRT_CTL3_U3
PF11
PRT_CTL4_U3
PF12
PRT_CTL5_U3
PF13
PRT_CTL5
PF14
PRT_CTL4
PF15
PRT_CTL3
PF16
PRT_CTL2
PF17
PRT_CTL1
PF18
MSTR_I2C_CLK
PF19
MIC_DET
PF20
SPI_CE_N
PF21
SPI_CLK
PF22
SPI_D0
PF23
SPI_D1
PF24
SPI_D2
PF25
SPI_D3
PF26
SLV_I2C_CLK
PF27
SLV_I2C_DATA
PF28
PRT_CTL6
PF29
(Note
3-1)
PF30
VBUS_DET
PF31
MSTR_I2C_DATA
Note 3-1
Note:
The default function is not used in the USB7206.
The default PFx pin functions can be overridden with additional configuration by modification of the pin mux
registers. These changes can be made during the SMBus configuration stage, by programming to OTP
memory, or during runtime (after hub has attached and enumerated) by register writes via the SMBus slave
interface or USB commands to the internal Hub Feature Controller Device.
2018 - 2020 Microchip Technology Inc.
DS00002875C-page 17
USB7206
TABLE 3-6:
PROGRAMMABLE FUNCTIONS DESCRIPTIONS
Function
Buffer
Type
Description
If Unused
Master SMBus/I2C Interface
MSTR_I2C_CLK
I/O12
Bridging Master SMBus/I2C controller clock (SMBus/I2C controller
1). External 1k-10k pull-up resistors to 3.3V are required if the I2C
Master Interface is to be used.
Weak pulldown to
GND
MSTR_I2C_DATA
I/O12
Bridging Master SMBus/I2C controller data (SMBus/I2C controller
1). External 1k-10k pull-up resistors to 3.3V are required if the I2C
Master Interface is to be used.
Weak pulldown to
GND
Slave SMBus/I2C Interface
SLV_I2C_CLK
I/O12
Slave SMBus/I2C controller clock (SMBus/I2C controller 2). External 1k-10k pull-up resistors to 3.3V are required if the I2C Slave
Interface is to be used.
Weak pulldown to
GND
SLV_I2C_DATA
I/O12
Slave SMBus/I2C controller data (SMBus/I2C controller 2). External
1k-10k pull-up resistors to 3.3V are required if the I2C Slave Interface is to be used.
Weak pulldown to
GND
I2S Interface
I2S Serial Data In
Weak pulldown to
GND
O12
I2S Serial Data Out
Weak pulldown to
GND
I2S_SCK
O12
I2S Continuous Serial Clock
Weak pulldown to
GND
I2S_LRCK
O12
I2S Word Select / Left-Right Clock
Weak pulldown to
GND
I2S_MCLK
O12
I2S Master Clock
Weak pulldown to
GND
MIC_DET
I
I2S Microphone Plug Detect
Weak pulldown to
GND
I2S_SDI
I
I2S_SDO
0 = No microphone plugged into the audio jack
1 = Microphone plugged into the audio jack
DS00002875C-page 18
2018 - 2020 Microchip Technology Inc.
USB7206
TABLE 3-6:
Function
PROGRAMMABLE FUNCTIONS DESCRIPTIONS (CONTINUED)
Buffer
Type
Description
If Unused
Miscellaneous
PRT_CTL6
I/O12
(PU)
Port 6 power enable / overcurrent sense
When the downstream port is enabled, this pin is set as an input
with an internal pull-up resistor applied. The internal pull-up
enables power to the downstream port while the pin monitors for an
active low overcurrent signal assertion from an external current
monitor on USB port 6.
Float
(Note 3-1)
This pin will change to an output and be driven low when the port is
disabled by configuration or by the host control.
Note:
Note 3-1
PRT_CTL5
I/O12
(PU)
This signal controls both the USB 2.0 and USB 3.2 portions of the port.
This pin can be left unused only if Port 6 is
disabled via strap/OTP/SMBus/SPI configuration.
Port 5 power enable / overcurrent sense
When the downstream port is enabled, this pin is set as an input
with an internal pull-up resistor applied. The internal pull-up
enables power to the downstream port while the pin monitors for an
active low overcurrent signal assertion from an external current
monitor on USB port 5.
Float
(Note 3-2)
This pin will change to an output and be driven low when the port is
disabled by configuration or by the host control.
Note:
Note 3-2
PRT_CTL4
I/O12
(PU)
When PortSplit is disabled, this signal controls both the
USB 2.0 and USB 3.2 portions of the port. When
PortSplit is enabled, this signal controls the USB 2.0
portion of the port only.
This pin can be left unused only if Port 5 is
disabled via strap/OTP/SMBus/SPI configuration.
Port 4 power enable / overcurrent sense
When the downstream port is enabled, this pin is set as an input
with an internal pull-up resistor applied. The internal pull-up
enables power to the downstream port while the pin monitors for an
active low overcurrent signal assertion from an external current
monitor on USB port 4.
Float
(Note 3-3)
This pin will change to an output and be driven low when the port is
disabled by configuration or by the host control.
Note:
Note 3-3
2018 - 2020 Microchip Technology Inc.
When PortSplit is disabled, this signal controls both the
USB 2.0 and USB 3.2 portions of the port. When
PortSplit is enabled, this signal controls the USB 2.0
portion of the port only.
This pin can be left unused only if Port 4 is
disabled via strap/OTP/SMBus/SPI configuration.
DS00002875C-page 19
USB7206
TABLE 3-6:
PROGRAMMABLE FUNCTIONS DESCRIPTIONS (CONTINUED)
Function
PRT_CTL3
Buffer
Type
I/O12
(PU)
Description
If Unused
Port 3 power enable / overcurrent sense
When the downstream port is enabled, this pin is set as an input
with an internal pull-up resistor applied. The internal pull-up
enables power to the downstream port while the pin monitors for an
active low overcurrent signal assertion from an external current
monitor on USB port 3.
Float
(Note 3-4)
This pin will change to an output and be driven low when the port is
disabled by configuration or by the host control.
Note:
Note 3-4
PRT_CTL2
I/O12
(PU)
When PortSplit is disabled, this signal controls both the
USB 2.0 and USB 3.2 portions of the port. When
PortSplit is enabled, this signal controls the USB 2.0
portion of the port only.
This pin can be left unused only if Port 3 is
disabled via strap/OTP/SMBus/SPI configuration.
Port 2 power enable / overcurrent sense
When the downstream port is enabled, this pin is set as an input
with an internal pull-up resistor applied. The internal pull-up
enables power to the downstream port while the pin monitors for an
active low overcurrent signal assertion from an external current
monitor on USB port 2.
Float
(Note 3-1)
This pin will change to an output and be driven low when the port is
disabled by configuration or by the host control.
Note:
Note 3-5
PRT_CTL1
I/O12
(PU)
When PortSplit is disabled, this signal controls both the
USB 2.0 and USB 3.2 portions of the port. When
PortSplit is enabled, this signal controls the USB 2.0
portion of the port only.
This pin can be left unused only if Port 2 is
disabled via strap/OTP/SMBus/SPI configuration.
Port 1 power enable / overcurrent sense
When the downstream port is enabled, this pin is set as an input
with an internal pull-up resistor applied. The internal pull-up
enables power to the downstream port while the pin monitors for an
active low overcurrent signal assertion from an external current
monitor on USB port 1.
Float
(Note 3-1)
This pin will change to an output and be driven low when the port is
disabled by configuration or by the host control.
Note:
Note 3-6
DS00002875C-page 20
When PortSplit is disabled, this signal controls both the
USB 2.0 and USB 3.2 portions of the port. When
PortSplit is enabled, this signal controls the USB 2.0
portion of the port only.
This pin can be left unused only if Port 1 is
disabled via strap/OTP/SMBus/SPI configuration.
2018 - 2020 Microchip Technology Inc.
USB7206
TABLE 3-6:
PROGRAMMABLE FUNCTIONS DESCRIPTIONS (CONTINUED)
Function
Buffer
Type
PRT_CTL5_U3
O12
Description
If Unused
Float
Port 5 USB 3.2 PortSplit power enable
This signal is an active high control signal used to enable to the
USB 3.2 portion of the downstream port 5 when PortSplit is
enabled. When PortSplit is disabled, this pin is not used.
Note:
PRT_CTL4_U3
O12
This signal should only be used to control an embedded
USB 3.2 device.
Float
Port 4 USB 3.2 PortSplit power enable
This signal is an active high control signal used to enable to the
USB 3.2 portion of the downstream port 4 when PortSplit is
enabled. When PortSplit is disabled, this pin is not used.
Note:
PRT_CTL3_U3
O12
This signal should only be used to control an embedded
USB 3.2 device.
Float
Port 3 USB 3.2 PortSplit power enable
This signal is an active high control signal used to enable to the
USB 3.2 portion of the downstream port 3 when PortSplit is
enabled. When PortSplit is disabled, this pin is not used.
Note:
3.4
This signal should only be used to control an embedded
USB 3.2 device.
Physical and Logical Port Mapping
The USB72xx family of devices are based upon a common architecture, but all have different modifications and/or pin
bond outs to achieve the various device configurations. The base chip is composed of a total of 6 USB3 PHYs and 7
USB2 PHYs. These PHYs are physically arranged on the chip in a certain way, which is referred to as the PHYSICAL
port mapping.
The actual port numbering is remapped by default in different ways on each device in the family. This changes the way
that the ports are numbered from the USB host’s perspective. This is referred to as LOGICAL mapping.
The various configuration options available for these devices may, at times, be with respect to PHYSICAL mapping or
LOGICAL mapping. Each individual configuration option which has a PHYSICAL or LOGICAL dependency is declared
as such within the register description.
The PHYSICAL vs. LOGICAL mapping is described for all port related pins in Table 3-7. A system design in schematics
and layout is generally performed using the pinout in Section 3.1, Pin Assignments, which is assigned by the default
LOGICAL mapping. Hence, it may be necessary to cross reference the PHYSICAL vs. LOGICAL look up tables when
determining the hub configuration.
Note:
The MPLAB Connect tool makes configuration simple; the settings can be selected by the user with respect
to the LOGICAL port numbering. The tool handles the necessary linking to the PHYSICAL port settings.
Refer to Section 6.0, Device Configuration for additional information.
2018 - 2020 Microchip Technology Inc.
DS00002875C-page 21
USB7206
TABLE 3-7:
Device
Pin
USB7206 PHYSICAL VS. LOGICAL PORT MAPPING
Pin Name (as in datasheet)
LOGICAL PORT NUMBER
0
1
2
3
4
5
PHYSICAL PORT NUMBER
6
0
1
2
3
4
5
6
5
USB2DN_DP1
X
X
6
USB2DN_DM1
X
X
7
USB3DN_TXDP1
X
X
8
USB3DN_TXDM1
X
X
10
USB3DN_RXDP1
X
X
11
USB3DN_RXDM1
X
X
14
USB2DN_DP2
X
X
15
USB2DN_DM2
X
X
16
USB3DN_TXDP2
X
X
17
USB3DN_TXDM2
X
X
19
USB3DN_RXDP2
X
X
20
USB3DN_RXDM2
X
X
27
USB2DN_DP3
X
X
28
USB2DN_DM3
X
X
29
USB3DN_TXDP3
X
X
30
USB3DN_TXDM3
X
X
32
USB3DN_RXDP3
X
X
33
USB3DN_RXDM3
X
X
34
USB2DN_DP4
X
X
35
USB2DN_DM4
X
X
36
USB3DN_TXDP4
X
X
37
USB3DN_TXDM4
X
X
39
USB3DN_RXDP4
X
X
40
USB3DN_RXDM4
X
X
41
USB2DN_DM6
X
X
42
USB2DN_DP6
X
X
81
USB2DN_DP5
X
X
82
USB2DN_DM5
X
X
83
USB3DN_TXDP5
X
X
84
USB3DN_TXDM5
X
X
86
USB3DN_RXDP5
X
X
87
USB3DN_RXDM5
X
X
89
USB2UP_DP
X
X
90
USB2UP_DM
X
X
91
USB3UP_TXDP
X
X
92
USB3UP_TXDM
X
X
94
USB3UP_RXDP
X
X
95
USB3UP_RXDM
X
X
DS00002875C-page 22
2018 - 2020 Microchip Technology Inc.
USB7206
4.0
DEVICE CONNECTIONS
4.1
Power Connections
Figure 4-1 illustrates the device power connections.
FIGURE 4-1:
POWER CONNECTIONS
+3.3V
Supply
VCORE
Supply
VDD33 (x8)
USB7206
F
u
1
0
.0
0
VCORE (x9)
Digital Core
Internal Logic
3.3V Internal Logic
VSS (exposed pad)
+3.3V
+3.3V
F
u
1
.
0
F
u
7
.
4
F
u
1
0
.0
0
x8
4.2
VCORE
VCORE
F
u
1
.
0
F
u
7
.
4
x9
SPI Flash Connections
Figure 4-2 illustrates the Quad-SPI flash connections.
FIGURE 4-2:
QUAD-SPI FLASH CONNECTIONS
10K
+3.3V
SPI_CE_N
CE#
SPI_CLK
CLK
SPI_D0
SIO0
SPI_D1
SIO1
SPI_D2
SIO2/WPn
SPI_D3
SIO3/HOLDn
USB7206
2018 - 2020 Microchip Technology Inc.
Quad-SPI Flash
DS00002875C-page 23
USB7206
4.3
SMBus/I2C Connections
Figure 4-3 illustrates the SMBus/I2C connections.
FIGURE 4-3:
SMBUS/I2C CONNECTIONS
+3.3V
4.7K
Clock
x_I2C_CLK
USB7206
SMBus/I2C
+3.3V
4.7K
Data
x_I2C_DAT
4.4
I2S Connections
Figure 4-4 illustrates the I2S connections.
FIGURE 4-4:
I2S CONNECTIONS
10K
USB7206
10K
+3.3V
CODEC
I2S_MCLK
I2S_SCK
I2 S
I2S_LRCK
I2S_SDO
I2S_SD
MSTR_I2C_CLK
2
IC
MSTR_I2C_DAT
MIC_DET
DS00002875C-page 24
Audio Jack
2018 - 2020 Microchip Technology Inc.
USB7206
5.0
MODES OF OPERATION
The device provides two main modes of operation: Standby Mode and Hub Mode. These modes are controlled via the
RESET_N pin, as shown in Table 5-1.
TABLE 5-1:
MODES OF OPERATION
RESET_N Input
Summary
0
Standby Mode: This is the lowest power mode of the device. No functions are active
other than monitoring the RESET_N input. All port interfaces are high impedance and
the PLL is halted. Refer to Section 8.9, Resets for additional information on RESET_N.
1
Hub (Normal) Mode: The device operates as a configurable USB hub. This mode has
various sub-modes of operation, as detailed in Figure 5-1. Power consumption is based
on the number of active ports, their speed, and amount of data received.
The flowchart in Figure 5-1 details the modes of operation and details how the device traverses through the Hub Mode
stages (shown in bold). The remaining sub-sections provide more detail on each stage of operation.
FIGURE 5-1:
HUB MODE FLOWCHART
RESET_N deasserted
(SPI_INIT)
(CFG_ROM)
In SPI Mode
& Ext. SPI ROM
present?
NO
Load Config from
Internal ROM
YES
(CFG_STRAP)
Modify Config
Based on Config
Straps
Run From
External SPI ROM
YES
Perform SMBus/I2C
Initialization
YES
Configuration 1?
NO
SMBus Slave Pull-ups?
NO
(SMBUS_CHECK)
NO
SOC Done?
(CFG_SMBUS) YES
Combine OTP
Config Data
(CFG_OTP)
Hub Connect
(USB_ATTACH)
Normal Operation
(NORMAL_MODE)
2018 - 2020 Microchip Technology Inc.
DS00002875C-page 25
USB7206
5.1
5.1.1
Boot Sequence
STANDBY MODE
If the RESET_N pin is asserted, the hub will be in Standby Mode. This mode provides a very low power state for maximum power efficiency when no signaling is required. This is the lowest power state. In Standby Mode all downstream
ports are disabled, the USB data pins are held in a high-impedance state, all transactions immediately terminate (no
states saved), all internal registers return to their default state, the PLL is halted, and core logic is powered down in order
to minimize power consumption. Because core logic is powered off, no configuration settings are retained in this mode
and must be re-initialized after RESET_N is negated high.
5.1.2
SPI INITIALIZATION STAGE (SPI_INIT)
The first stage, the initialization stage, occurs on the deassertion of RESET_N. In this stage, the internal logic is reset,
the PLL locks if a valid clock is supplied, and the configuration registers are initialized to their default state. The internal
firmware then checks for an external SPI ROM. The firmware looks for an external SPI flash device that contains a valid
signature of “2DFU” (device firmware upgrade) beginning at address 0x3FFFA. If a valid signature is found, then the
external SPI ROM is enabled and the code execution begins at address 0x0000 in the external SPI device. If a valid
signature is not found, then execution continues from internal ROM (CFG_ROM stage).
The required SPI ROM must be a minimum of 1 Mbit, and 60 MHz or faster. Both 1, 2, and 4-bit SPI operation is supported. For optimum throughput, a 2-bit SPI ROM is recommended. Both mode 0 and mode 3 SPI ROMs are also supported.
If the system is not strapped for SPI Mode, code execution will continue from internal ROM (CFG_ROM stage).
5.1.3
CONFIGURATION FROM INTERNAL ROM STAGE (CFG_ROM)
In this stage, the internal firmware loads the default values from the internal ROM. Most of the hub configuration registers, USB descriptors, electrical settings, etc. will be initialized in this state.
5.1.4
CONFIGURATION STRAP READ STAGE (CFG_STRAP)
In this stage, the firmware reads the following configuration straps to override the default values:
•
•
•
•
•
CFG_STRAP[3:1]
PRT_DIS_P[6:1]
PRT_DIS_M[6:1]
CFG_NON_REM
CFG_BC_EN
If the CFG_STRAP[3:1] pins are set to Configuration 1, the device will move to the SMBUS_CHECK stage, otherwise
it will move to the CFG_OTP stage. Refer to Section 3.3, Configuration Straps and Programmable Functions for information on usage of the various device configuration straps.
5.1.5
SMBUS CHECK STAGE (SMBUS_CHECK)
Based on the PF[31:3] configuration selected (refer to Section 3.3.4, PF[31:3] Configuration (CFG_STRAP[2:1])), the
firmware will check for the presence of external pull up resistors on the SMBus slave programmable function pins. If 10K
pull-ups are detected on both pins, the device will be configured as an SMBus slave, and the next state will be CFG_SMBUS. If a pull-up is not detected in either of the pins, the next state is CFG_OTP.
5.1.6
SMBUS CONFIGURATION STAGE (CFG_SMBUS)
In this stage, the external SMBus master can modify any of the default configuration settings specified in the integrated
ROM, such as USB device descriptors, port electrical settings, and control features such as downstream battery
charging.
There is no time limit on this mode. In this stage the firmware will wait indefinitely for the SMBus/I2C configuration. The
external SMBus master writes to register 0xFF to end the configuration in legacy mode. In non-legacy mode, the SMBus
command USB_ATTACH (opcode 0xAA55) or USB_ATTACH_WITH_SMBUS (opcode 0xAA56) will finish the configuration.
DS00002875C-page 26
2018 - 2020 Microchip Technology Inc.
USB7206
5.1.7
OTP CONFIGURATION STAGE (CFG_OTP)
Once the SOC has indicated that it is done with configuration, all configuration data is combined in this stage. The
default data, the SOC configuration data, and the OTP data are all combined in the firmware and the device is programmed.
Note:
5.1.8
If the same register is modified in both CFG_SMBUS and CFG_OTP stages, the value from CFG_OTP will
overwrite any value written during CFG_SMBUS.
HUB CONNECT STAGE (USB_ATTACH)
Once the hub registers are updated through default values, SMBus master, and OTP, the device firmware will enable
attaching the USB host by setting the USB_ATTACH bit in the HUB_CMD_STAT register (for USB 2.0) and the
USB3_HUB_ENABLE bit (for USB 3.2). The device will remain in the Hub Connect stage indefinitely.
5.1.9
NORMAL MODE (NORMAL_MODE)
Lastly, the hub enters Normal Mode of operation. In this stage full USB operation is supported under control of the USB
Host on the upstream port. The device will remain in the normal mode until the operating mode is changed by the system.
If RESET_N is asserted low, then Standby Mode is entered. The device may then be placed into any of the designated
hub stages. Asserting a soft disconnect on the upstream port will cause the hub to return to the Hub Connect stage until
the soft disconnect is negated.
2018 - 2020 Microchip Technology Inc.
DS00002875C-page 27
USB7206
6.0
DEVICE CONFIGURATION
The device supports a large number of features (some mutually exclusive), and must be configured in order to correctly
function when attached to a USB host controller. Microchip provides a comprehensive software programming tool,
MPLAB Connect Configurator (formerly ProTouch2), for OTP configuration of various USB7206 functions and registers.
All configuration is to be performed via the MPLAB Connect Configurator programming tool. For additional information
on this tool, refer to the MPLAB Connect Configurator programming tool product page at http://www.microchip.com/
design-centers/usb/mplab-connect-configurator.
Additional information on configuring the USB7206 is also provided in the “Configuration of the USB7202/USB725x”
application note, which contains details on the hub operational mode, SOC configuration stage, OTP configuration, USB
configuration, and configuration register definitions. This application note, along with additional USB7206 resources,
can be found on the Microchip USB7206 product page at www.microchip.com/USB7206.
Note:
Device configuration straps and programmable pins are detailed in Section 3.3, Configuration Straps and
Programmable Functions.
Refer to Section 7.0, Device Interfaces for detailed information on each device interface.
DS00002875C-page 28
2018 - 2020 Microchip Technology Inc.
USB7206
7.0
DEVICE INTERFACES
The USB7206 provides multiple interfaces for configuration, external memory access, etc.. This section details the various device interfaces:
• SPI/SQI Master Interface
• SMBus/I2C Master/Slave Interfaces
• I2S Interface
Note:
For details on how to enable each interface, refer to Section 3.3, Configuration Straps and Programmable
Functions.
For information on device connections, refer to Section 4.0, Device Connections. For information on device
configuration, refer to Section 6.0, Device Configuration.
Microchip provides a comprehensive software programming tool, MPLAB Connect Configurator (formerly
ProTouch2), for configuring the USB7206 functions, registers and OTP memory. All configuration is to be
performed via the MPLAB Connect Configurator programming tool. For additional information on this tool,
refer to th MPLAB Connect Configurator programming tool product page at http://www.microchip.com/
design-centers/usb/mplab-connect-configurator.
7.1
SPI/SQI Master Interface
The SPI/SQI controller has two basic modes of operation: execution of an external hub firmware image, or the USB to
SPI bridge. On power up, the firmware looks for an external SPI flash device that contains a valid signature of 2DFU
(device firmware upgrade) beginning at address 0x3FFFA. If a valid signature is found, then the external ROM mode is
enabled and the code execution begins at address 0x0000 in the external SPI device. If a valid signature is not found,
then execution continues from internal ROM and the SPI interface can be used as a USB to SPI bridge.
The entire firmware image is then executed in place entirely from the SPI interface. The SPI interface will remain continuously active while the hub is in the runtime state. The hub configuration options are also loaded entirely out of the
SPI memory device. Both the internal ROM firmware image and internal OTP memory are completely ignored while executing the firmware and configuration from the external SPI memory.
The second mode of operation is the USB to SPI bridge operation. Additional details on this feature can be found in
Section 8.7, USB to SPI Bridging.
Table 7-1 details how the associated pins are mapped in SPI vs. SQI mode
TABLE 7-1:
Note:
SPI/SQI PIN USAGE
SPI Mode
SQI Mode
Description
SPI_CE_N
SQI_CE_N
SPI/SQI Chip Enable (Active Low)
SPI_CLK
SQI_CLK
SPI/SQI Clock
SPI_D0
SQI_D0
SPI Data Out; SQI Data I/O 0
SPI_D1
SQI_D1
SPI Data In; SQI Data I/O 1
-
SQI_D2
SQI Data I/O 2
-
SQI_D3
SQI Data I/O 3
For SPI/SQI master timing information, refer to Section 9.6.10, SPI/SQI Master Timing.
2018 - 2020 Microchip Technology Inc.
DS00002875C-page 29
USB7206
7.2
SMBus/I2C Master/Slave Interfaces
The device provides twothree independent SMBus/I2C controllers (Slave, and Master) which can be used to access
internal device run time registers or program the internal OTP memory. The device contains two 128 byte buffers to
enable simultaneous master/slave operation and to minimize firmware overhead in processed I2C packets. The I2C
interfaces support 100KHz Standard-mode (Sm) and 400KHz Fast Mode (Fm) operation.
The SMBus/I2C interfaces are assigned to programmable pins (PFx). Refer to Section 3.3.4, PF[31:3] Configuration
(CFG_STRAP[2:1]) for additional information.
Note:
7.3
For SMBus/I2C timing information, refer to Section 9.6.7, SMBus Timing and Section 9.6.8, I2C Timing.
I2S Interface
The device provides an integrated I2S interface to facilitate the connection of digital audio devices. The I2S interface
conforms to the voltage, power, and timing characteristics/specifications as set forth in the I2S-Bus Specification, and
consists of the following signals:
•
•
•
•
•
•
I2S_SDI: Serial Data Input
I2S_SDO: Serial Data Output
I2S_SCK: Serial Clock
I2S_LRCK: Left/Right Clock (SS/FSYNC)
I2S_MCLK: Master Clock
MIC_DET: Microphone Plug Detect
Each audio connection is half-duplex, so I2S_SDO exists only on the transmit side and I2S_SDI exists only on the
receive side of the interface. Some codecs refer to the Serial Clock (I2S_SCK) as Baud/Bit Clock (BCLK). Also, the Left/
Right Clock is commonly referred to as LRC or LRCK. The I2S and other audio protocols refer to LRC as Word Select
(WS).
The following codec is supported by default:
• Analog Devices ADAU1961 (24-bit 96KHz)
The I2S interface is assigned to programmable pins (PFx). Refer to Section 3.3.4, PF[31:3] Configuration
(CFG_STRAP[2:1]) for additional information.
Note:
7.3.1
For I2S timing information, refer to Section 9.6.9, I2S Timing. For detailed information on utilizing the I2S
interface, including support for other codecs, refer to the application note “USB7202/USB725x I2S Operation”, which can be found on the Microchip USB7206 product page at www.microchip.com/USB7206.
MODES OF OPERATION
The USB audio class operates in three ways: Asynchronous, Synchronous and Adaptive. There are also multiple operating modes, such as hi-res, streaming, etc.. Typically for USB devices, inputs such as microphones are Asynchronous,
and output devices such as speakers are Adaptive. The hardware is set up to handle all three modes of operation. It is
recommended that the following configuration be used: Asynchronous IN; Adaptive OUT; 48Khz streaming mode; Two
channels: 16 bits per channel.
7.3.1.1
Asynchronous IN 48KHz Streaming
In this mode, the codec sampling clock is set to 48Khz based on the local oscillator. This clock is never changed. The
data from the codec is fed into the input FIFO. Since the sampling clock is asynchronous to the host clock, the amount
of data captured in every USB frame will vary. This issue is left for the host to handle. The input FIFO has two markers,
a low water mark (THRESHOLD_LOW_VAL), and a high water mark (THRESHOLD_HIGH_VAL). There are three registers to determine how much data to send back in each frame. If the amount of data in the FIFO exceeds the high water
mark, then HI_PKT_SIZE worth of data is sent. If the data is between the high and low water mark, the normal MID_PKT_SIZE amount of data is sent. If the data is below the low water mark, LO_PKT_SIZE worth of data is sent.
DS00002875C-page 30
2018 - 2020 Microchip Technology Inc.
USB7206
7.3.1.2
Adaptive OUT 48KHz Streaming
In this mode, the codec sampling clock is initially set to 48Khz based on the local oscillator. The host data is fed into the
OUT FIFO. The host will send the same amount of data on every frame, i.e. 48KHz of data based on the host clock. The
codec sampling clock is asynchronous to the host clock. This will cause the amount of data in the OUT FIFO to vary. If
the amount of data in the FIFO exceeds the high water mark, then the sampling clock is increased. If the data is between
the high and low water mark, the sampling clock does not change. If the data is below the low water mark, the sampling
clock is decreased.
7.3.1.3
Synchronous Operation
For synchronous operation, the internal clock must be synchronized with the host SOF. The Frame SOF is nominally
1mS. Since there is significant jitter in the SOFs, there is circuitry provided to measure the SOFs over a long period of
time to get a more accurate reading. The calculated host frequency is used to calculate the codec sampling clock.
2018 - 2020 Microchip Technology Inc.
DS00002875C-page 31
USB7206
8.0
FUNCTIONAL DESCRIPTIONS
This section details various USB7206 functions, including:
•
•
•
•
•
•
•
•
•
Downstream Battery Charging
Port Power Control
PortSplit
FlexConnect
USB to GPIO Bridging
USB to I2C Bridging
USB to SPI Bridging
Link Power Management (LPM)
Resets
8.1
Downstream Battery Charging
The device can be configured by an OEM to have any of the downstream ports support battery charging. The hub’s role
in battery charging is to provide acknowledgment to a device’s query as to whether the hub system supports USB battery
charging. The hub silicon does not provide any current or power FETs or any additional circuitry to actually charge the
device. Those components must be provided externally by the OEM.
FIGURE 8-1:
BATTERY CHARGING EXTERNAL POWER SUPPLY
INT
DC Power
SCL
Microchip
SOC
Hub
SDA
VBUS[n]
If the OEM provides an external supply capable of supplying current per the battery charging specification, the hub can
be configured to indicate the presence of such a supply from the device. This indication, via the PRT_CTLx pins, is on
a per port basis. For example, the OEM can configure two ports to support battery charging through high current power
FETs and leave the other two ports as standard USB ports.
The port control signals are assigned to programmable pins (PFx) and therefore the device must be programmed into
specific configurations to enable the signals. Refer to Section 3.3.4, PF[31:3] Configuration (CFG_STRAP[2:1]) for additional information.
For detailed information on utilizing the battery charging feature, refer to the application note “USB Battery Charging
with Microchip USB7202 and USB725x Hubs”, which can be found on the Microchip USB7206 product page www.microchip.com/USB7206.
DS00002875C-page 32
2018 - 2020 Microchip Technology Inc.
USB7206
8.2
Port Power Control
Port power and over-current sense share the same pin (PRT_CTLx) for each port. These functions can be controlled
directly from the USB hub, or via the processor.
Note:
8.2.1
The PRT_CTLx function is assigned to programmable function pins (PFx) via configuration straps. Refer
to Section 3.3.4, PF[31:3] Configuration (CFG_STRAP[2:1]) for additional information.
PORT POWER CONTROL USING USB POWER SWITCH
When operating in combined mode, the device will have one port power control and over-current sense pin for each
downstream port. When disabling port power, the driver will actively drive a '0'. To avoid unnecessary power dissipation,
the pull-up resistor will be disabled at that time. When port power is enabled, it will disable the output driver and enable
the pull-up resistor, making it an open drain output. If there is an over-current situation, the USB Power Switch will assert
the open drain OCS signal. The Schmidt trigger input will recognize that as a low. The open drain output does not interfere. The over-current sense filter handles the transient conditions such as low voltage while the device is powering up.
Note:
An external power switch is the required implementation for Type-C ports due to the requirement that VBUS
on Type-C ports must be discharged to 0V when no device is attached to the port.
FIGURE 8-2:
PORT POWER CONTROL WITH USB POWER SWITCH
Pull‐Up Enable
5V
50k
PRT_CTLx
OCS
USB Power
Switch
EN
PRTPWR
USB
Device
FILTER
OCS
8.2.2
PORT POWER CONTROL USING POLY FUSE
When using the device with a poly fuse, there is no need for an output power control. A single port power control and
over-current sense for each downstream port is still used from the Hub's perspective. When disabling port power, the
driver will actively drive a '0'. This will have no effect as the external diode will isolate pin from the load. When port power
is enabled, it will disable the output driver and enable the pull-up resistor. This means that the pull-up resistor is providing
3.3 volts to the anode of the diode. If there is an over-current situation, the poly fuse will open. This will cause the cathode of the diode to go to 0 volts. The anode of the diode will be at 0.7 volts, and the Schmidt trigger input will register
this as a low resulting in an over-current detection. The open drain output does not interfere.
Note:
Type-C ports may not utilize a Poly-Fuse port power implementation due to the requirements that VBUS
on Type-C ports must be discharged to 0V when no device is attached to the port.
2018 - 2020 Microchip Technology Inc.
DS00002875C-page 33
USB7206
FIGURE 8-3:
PORT POWER CONTROL USING A POLY FUSE
5V
Pull-Up Enable
Poly Fuse
50k
PRT_CTLx
USB
Device
PRTPWR
OCS
8.3
FILTER
PortSplit
The PortSplit feature allows the USB 2.0 and USB 3.2 PHYs associated with a downstream port to be operationally separated. The intention of this feature is to allow a system designer to connect an embedded USB 3.x device to the USB
3.2 PHY, while allowing the USB 2.0 PHY to be used as either a standard USB 2.0 port or with a separate embedded
USB 2.0 device. PortSplit can be configured via OTP/SMBus. By default, all ports are configured to non-split mode.
When PortSplit is disabled on a specific port, the corresponding PRT_CTLx pin controls both the USB 2.0 and USB 3.2
portions of the port (port power and overcurrent condition). When PortSplit is enabled on a specific port, the corresponding PRT_CTLx pin controls the USB 2.0 portion of the port, and the corresponding PRT_CTLx_U3 pin controls
the USB 3.2 portion of the port.
8.4
FlexConnect
The device allows the upstream port to be swapped with any downstream port, enabling any USB port to assume the
role of USB host at any time during hub operation. This host role exchange feature is called FlexConnect. Additionally,
the USB 2.0 ports can be flexed independently of the USB 3.2 ports.
This functionality can be used in two primary ways:
1.
2.
Host Swapping: This functionality can be achieved through a hub wherein a host and device can agree to swap
the host/device relationship; The host becomes a device, and the device becomes a host.
Host Sharing: A USB ecosystem can be shared between multiple hosts. Note that only 1 host may access to
the USB tree at a time.
FlexConnect can be enabled through any of the following three methods:
• I2C Control: The embedded I2C slave can be used to control the state of the FlexConnect feature through basic
write/read operations.
• USB Command: FlexConnect can be initiated via a special USB command directed to the hub’s internal Hub
Feature Controller device.
• Direct Pin Control: Any available GPIO pin on the hub can be assigned the role of a FlexConnect control pin.
Note:
Direct Pin Control is only available in certain configurations. Refer to Section 3.3.4, PF[31:3] Configuration
(CFG_STRAP[2:1]) for additional information.
DS00002875C-page 34
2018 - 2020 Microchip Technology Inc.
USB7206
For detailed information on utilizing the FlexConnect feature, refer to the application note “USB720x/USB725x FlexConnect Operation”, which can be found on the Microchip USB7206 product page at www.microchip.com/USB7206.
8.5
USB to GPIO Bridging
The USB to GPIO bridging feature provides system designers expanded system control and potential BOM reduction.
General Purpose Input/Outputs (GPIOs) may be used for any general 3.3V level digital control and input functions.
Commands may be sent from the USB Host to the internal Hub Feature Controller device in the Microchip hub to perform the following functions:
•
•
•
•
•
Set the direction of the GPIO (input or output)
Enable a pull-up resistor
Enable a pull-down resistor
Read the state
Set the state
For detailed information on utilizing the USB to GPIO bridging feature, refer to the application note “USB to GPIO Bridging with Microchip USB7202 and USB725x Hubs”, which can be found on the Microchip USB7206 product page at
www.microchip.com/USB7206.
8.6
USB to I2C Bridging
The USB to I2C bridging feature provides system designers expanded system control and potential BOM reduction. The
use of a separate USB to I2C device is no longer required and a downstream USB port is not lost, as occurs when a
standalone USB to I2C device is implemented.
Commands may be sent from the USB Host to the internal Hub Feature Controller device in the Microchip hub to perform the following functions:
• Configure I2C Pass-Through Interface
• I2C Write
• I2C Read
For detailed information on utilizing the USB to I2C bridging feature, refer to the application note “USB to I2C Bridging
with Microchip USB7202 and USB725x Hubs”, which can be found on the Microchip USB7206 product page at
www.microchip.com/USB7206.
8.7
USB to SPI Bridging
The USB to SPI bridging feature provides system designers expanded system control and potential BOM reduction. The
use of a separate USB to SPI device is no longer required and a downstream USB port is not lost, as occurs when a
standalone USB to SPI device is implemented.
Commands may be sent from the USB Host to the internal Hub Feature Controller device in the Microchip hub to perform the following functions:
• Enable SPI Pass-Through Interface
• SPI Write/Read
• Disable SPI Pass-Through Interface
For detailed information on utilizing the USB to SPI bridging feature, refer to the application note “USB to SPI Bridging
with Microchip USB7202 and USB725x Hubs”, which can be found on the Microchip USB7206 product page at
www.microchip.com/USB7206.
2018 - 2020 Microchip Technology Inc.
DS00002875C-page 35
USB7206
8.8
Link Power Management (LPM)
The device supports the L0 (On), L1 (Sleep), and L2 (Suspend) link power management states. These supported LPM
states offer low transitional latencies in the tens of microseconds versus the much longer latencies of the traditional USB
suspend/resume in the tens of milliseconds. The supported LPM states are detailed in Table 8-1.
TABLE 8-1:
LPM STATE DEFINITIONS
State
8.9
Description
Entry/Exit Time to L0
L2
Suspend
Entry: ~3 ms
Exit: ~2 ms (from start of RESUME)
L1
Sleep
Entry:
工商网监
湘ICP备2023018690号
