USB7252C
4-Port USB 3.2 Gen 2 Type-C® Controller Hub
Highlights
• 4-Port USB Smart Hub with:
- USB Gen 2 Type-B® on upstream port
- Native USB Gen 2 Type-C with Power Delivery PD
support on downstream ports 1 and 2®One Standard USB 3.2 Gen 2 downstream port
- One Standard USB 2.0 downstream port
- Internal Hub Feature Controller enables:
- USB to I2C/SPI/UART/I2S/GPIO bridge endpointsupport
- USB to internal hub register write and read
• USB Link Power Management (LPM) support
• Programming of firmware image to external SPI
memory device from USB host
• USB-IF Battery Charger revision 1.2 support on
downstream ports (DCP, CDP, SDP)
• Enhanced OEM configuration options available
through either OTP or external SPI memory
• Available in 100-pin (12mm x 12mm) VQFN
RoHS compliant package
• Commercial and industrial grade temperature
support
Target Applications
•
•
•
•
•
Standalone USB Hubs
Laptop Docks
PC Motherboards
PC Monitor Docks
Multi-function USB 3.2 Gen 2 Peripherals
Key Benefits
• USB 3.2 Gen 2 compliant 10 Gbps, 5 Gbps,
480 Mbps, 12 Mbps, and 1.5Mbps operation
- 5V tolerant USB 2.0 pins
- 1.21V tolerant USB 3.2 Gen 2 pins
- Integrated termination and pull-up/down resistors
• Native USB Type-C Support
- Type-C CC Pin with integrated Rp and Rd resistors
- Integrated multiplexer on USB Type-C enabled
ports. USB 3.2 Gen 2 PHYs are disabled until a
valid Type-C attach is detected, saving idle power.
Control for external VCONN supply
• Supports battery charging of most popular battery
powered devices on all ports
- USB-IF Battery Charging rev. 1.2 support
(DCP, CDP, SDP)
- Apple® portable product charger emulation
- Chinese YD/T 1591-2006/2009 charger emulation
- European Union universal mobile charger support
- Supports additional portable devices
• On-chip Microcontroller
- manages I/Os, VBUS, and other signals
• 96kB RAM, 256kB ROM
• 8kB One-Time-Programmable (OTP) ROM
- Includes on-chip charge pump
• Configuration programming via OTP Memory, SPI
external memory, or SMBus
• FlexConnect
- The roles of the upstream and all downstream
ports are reversible on command
• Multi-Host Endpoint Reflector
- Integrated host-controller endpoint reflector via
CDC/NCM device class for automotive applications
• USB Bridging
- USB to I2C, SPI, UART, I2S, and GPIO
• PortSwap
- Configurable USB 2.0 differential pair signal swap
• PHYBoost
- Programmable USB transceiver drive strength for
recovering signal integrity
• VariSense
- Programmable USB receive sensitivity
• PortSplit
- USB 2.0 and USB 3.2 Gen 2 port operation can be
split for custom applications using embedded USB
3.x devices in parallel with USB 2.0 devices
• Compatible with Microsoft Windows 10, 8, 7, XP,
Apple OS X 10.4+, and Linux hub drivers
• Optimized for low-power operation and low thermal dissipation
• 100-pin VQFN package (12mm x 12mm)
* USB Type-C® and USB-C® are registered trademarks of USB Implementers Forum
2021 Microchip Technology Inc.
DS00003852A-page 1
TO OUR VALUED CUSTOMERS
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DS00003852A-page 2
2021 Microchip Technology Inc.
1.0
PREFACE
1.1
General Terms
TABLE 1-1:
GENERAL TERMS
Term
Description
ADC
Analog-to-Digital Converter
Byte
8 bits
CDC
Communication Device Class
CSR
Control and Status Registers
DFP
Downstream Facing Port
DWORD
32 bits
EOP
End of Packet
EP
Endpoint
FIFO
First In First Out buffer
FS
Full-Speed
FSM
Finite State Machine
GPIO
General Purpose I/O
HS
Hi-Speed
HSOS
High Speed Over Sampling
Hub Feature Controller
The Hub Feature Controller, sometimes called a Hub Controller for short is the internal
processor used to enable the unique features of the USB Controller Hub. This is not to
be confused with the USB Hub Controller that is used to communicate the hub status
back to the Host during a USB session.
I2C
Inter-Integrated Circuit
LS
Low-Speed
lsb
Least Significant Bit
LSB
Least Significant Byte
msb
Most Significant Bit
MSB
Most Significant Byte
N/A
Not Applicable
NC
No Connect
OTP
One Time Programmable
PCB
Printed Circuit Board
PCS
Physical Coding Sublayer
PHY
Physical Layer
PLL
Phase Lock Loop
RESERVED
Refers to a reserved bit field or address. Unless otherwise noted, reserved bits must
always be zero for write operations. Unless otherwise noted, values are not guaranteed when reading reserved bits. Unless otherwise noted, do not read or write to
reserved addresses.
SDK
Software Development Kit
SMBus
System Management Bus
UFP
Upstream Facing Port
UUID
Universally Unique IDentifier
WORD
16 bits
2021 Microchip Technology Inc.
DS00003852A-page 3
1.2
Buffer Types
TABLE 1-2:
BUFFER TYPES
Buffer Type
Description
I
Input.
IS
Input with Schmitt trigger.
O12
Output buffer with 12 mA sink and 12 mA source.
OD12
Open-drain output with 12 mA sink
PU
50 μA (typical) internal pull-up. Unless otherwise noted in the pin description, internal pullups are always enabled.
Internal pull-up resistors prevent unconnected inputs from floating. Do not rely on internal
resistors to drive signals external to the device. When connected to a load that must be
pulled high, an external resistor must be added.
PD
50 μA (typical) internal pull-down. Unless otherwise noted in the pin description, internal
pull-downs are always enabled.
Internal pull-down resistors prevent unconnected inputs from floating. Do not rely on
internal resistors to drive signals external to the device. When connected to a load that
must be pulled low, an external resistor must be added.
ICLK
Crystal oscillator input pin
OCLK
Crystal oscillator output pin
I/O-U
Analog input/output defined in USB specification.
I-R
RBIAS.
A
Analog.
AIO
Analog bidirectional.
P
Power pin.
DS00003852A-page 4
2021 Microchip Technology Inc.
1.3
Pin Reset States
The pin reset state definitions are detailed in Table 1-3. Refer to Section 3.1, Pin Assignments for details on individual
pin reset states.
TABLE 1-3:
PIN RESET STATE LEGEND
Symbol
AI
Analog input
AIO
Analog input/output
AO
Analog output
PD
Hardware enables pull-down
PU
Hardware enables pull-up
Y
Hardware enables function
Z
Hardware disables output driver (high impedance)
PU
Hardware enables internal pull-up
PD
Hardware enables internal pull-down
1.4
1.
2.
3.
4.
5.
Description
Reference Documents
Universal Serial Bus Revision 3.2 Specification, http://www.usb.org
Battery Charging Specification, Revision 1.2, Dec. 07, 2010, http://www.usb.org
I2C-Bus Specification, Version 1.1, http://www.nxp.com/documents/user_manual/UM10204.pdf
I2S-Bus Specification, http://www.sparkfun.com/datasheets/BreakoutBoards/I2SBUS.pdf
System Management Bus Specification, Version 1.0, http://smbus.org/specs
Note:
Additional USB7252C resources can be found on the Microchip USB7252C product page at
www.microchip.com/USB7252C.
2021 Microchip Technology Inc.
DS00003852A-page 5
2.0
INTRODUCTION
2.1
General Description
The Microchip USB7252C hub is a low-power, OEM configurable, USB 3.2 Gen 2 hub controller with 4 downstream
ports and advanced features for embedded USB applications. The USB7252C is fully compliant with the Universal Serial
Bus Revision 3.2 Specification and USB 2.0 Link Power Management Addendum. The USB7252C supports 10 Gbps
SuperSpeed+ (SS+), 5 Gbps SuperSpeed (SS), 480 Mbps Hi-Speed (HS), 12 Mbps Full-Speed (FS), and 1.5 Mbps LowSpeed (LS) USB downstream devices on three standard USB 3.2 Gen 2 downstream ports and only legacy speeds (HS/
FS/LS) on one standard USB 2.0 downstream port.
The USB7252C is a standard USB 3.2 Gen 2 hub that supports native basic Type-C with integrated CC logic on two
downstream ports. The downstream Type-C ports include internal USB 3.2 Gen 2 multiplexers; no external multiplexer
is required for Type-C support.
The USB7252C supports the legacy USB speeds (HS/FS/LS) through a dedicated USB 2.0 hub controller that is the
culmination of seven generations of Microchip hub feature controller design and experience with proven reliability,
interoperability, and device compatibility. The SuperSpeed hub controller operates in parallel with the USB 2.0 controller,
decoupling the 10/5 Gbps SS+/SS data transfers from bottlenecks due to the slower USB 2.0 traffic.
The USB7252C enables OEMs to configure their system using “Configuration Straps.” These straps simplify the configuration process assigning default values to USB 3.2 Gen 2 ports and GPIOs. OEMs can disable ports, enable battery
charging and define GPIO functions as default assignments on power up removing the need for OTP or external SPI
ROM.
The USB7252C supports downstream battery charging. The USB7252C integrated battery charger detection circuitry
supports the USB-IF Battery Charging (BC1.2) detection method and most Apple devices. The USB7252C provides the
battery charging handshake and supports the following USB-IF BC1.2 charging profiles:
• DCP: Dedicated Charging Port (Power brick with no data)
• CDP: Charging Downstream Port (1.5A with data)
• SDP: Standard Downstream Port (0.5A[USB 2.0]/0.9A[USB 3.2] with data)
Additionally, the USB7252C includes many powerful and unique features such as:
The Hub Feature Controller, an internal USB device dedicated for use as a USB to I2C/UART/SPI/GPIO interface that
allows external circuits or devices to be monitored, controlled, or configured via the USB interface.
Multi-Host Endpoint Reflector, which provides unique USB functionality whereby USB data can be “mirrored” between
two USB hosts (Multi-Host) in order to perform a single USB transaction.This capability is fully covered by Microchip
intellectual property (U.S. Pat. Nos. 7,523,243 and 7,627,708) and is instrumental in enabling Apple CarPlay™, where
the Apple iPhone® becomes a USB Host.
FlexConnect, which provides flexible connectivity options. One of the USB7252C’s downstream ports can be reconfigured to become the upstream port, allowing master capable devices to control other devices on the hub.
PortSwap, which adds per-port programmability to USB differential-pair pin locations. PortSwap allows direct alignment
of USB signals (D+/D-) to connectors to avoid uneven trace length or crossing of the USB differential signals on the
PCB.
PHYBoost, which provides programmable levels of Hi-Speed USB signal drive strength
in the downstream port transceivers. PHYBoost attempts to restore USB signal integrity
in a compromised system environment. The graphic on the right shows an example of
Hi-Speed USB eye diagrams before and after PHYBoost signal integrity restoration. in
a compromised system environment.
VariSense, which controls the Hi-Speed USB receiver sensitivity enabling programmable levels of USB signal receive
sensitivity. This capability allows operation in a sub-optimal system environment, such as when a captive USB cable is
used.
Port Split, which allows for the USB 3.2 Gen 2 and USB 2.0 portions of downstream port 3 to operate independently
and enumerate two separate devices in parallel in special applications.
DS00003852A-page 6
2021 Microchip Technology Inc.
The USB7252C can be configured for operation through internal default settings. Custom OEM configurations are supported through external SPI ROM or OTP ROM. All port control signal pins are under firmware control in order to allow
for maximum operational flexibility and are available as GPIOs for customer specific use.
The USB7252C is available in commercial (0°C to +70°C) and industrial (-40°C to +85°C) temperature ranges. An internal block diagram of the USB7252C in an upstream Type-C application is shown in Figure 2-1.
FIGURE 2-1:
USB7252C INTERNAL BLOCK DIAGRAM - UPSTREAM TYPE-B APPLICATION
P0
B
2
I C from Master
+3.3 V
2
PHY0 PHY0
I C/SPI
VCORE
USB3 USB2
Hub Controller Logic
25 Mhz
PHY1 PHY2
A
B PHY1 CC
PHY3 PHY4
A
B PHY3 CC
PHY5 PHY5
HFC
PHY
PHY2
Hub Feature Controller OTP
GPIO SMB
SPI
I2S
UART
Mux
P1
C
Note:
P2
C
P3
A
P4
A
All port numbering in this document is LOGICAL port numbering with the device in the default configuration.
LOGICAL port numbering is the numbering as communicated to the USB host. It is the end result after any
port number remapping or port disabling. The PHYSICAL port number is the port number with respect to
the physical PHY on the chip. PHYSICAL port numbering is fixed and the settings are not impacted by
LOGICAL port renumbering/remapping. Certain port settings are made with respect to LOGICAL port numbering, and other port settings are made with respect to PHYSICAL port numbering. Refer to the “Configuration of USB7202/USB7206/USB725x” application note for details on the LOGICAL vs. PHYSICAL
mapping and additional configuration details.
2021 Microchip Technology Inc.
DS00003852A-page 7
3.0
PIN DESCRIPTIONS
3.1
Pin Assignments
RBIAS
VDD33
XTALI/CLK_IN
XTALO
ATEST
USB3UP_RXDM
USB3UP_RXDP
VCORE
USB3UP_TXDM
USB3UP_TXDP
USB2UP_DM
USB2UP_DP
VDD33
USB3DN_RXDM3
USB3DN_RXDP3
VCORE
USB3DN_TXDM3
USB3DN_TXDP3
USB2DN_DM3/PRT_DIS_M3
USB2DN_DP3/PRT_DIS_P3
VBUS_MON_UP
VDD33
VCORE
PF28
PF27
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
USB7252C 100-VQFN PIN ASSIGNMENTS
100
FIGURE 3-1:
RESET_N
1
75
PF26
PF30
2
74
PF29
PF31
3
73
SPI_D3/PF25
DP1_VBUS_MON
4
72
SPI_D2/PF24
USB2DN_DP1/PRT_DIS_P1
5
71
SPI_D1/PF23
USB2DN_DM1/PRT_DIS_M1
6
70
SPI_D0/CFG_BC_EN/PF22
USB3DN_TXDP1A
7
69
SPI_CE_N/CFG_NON_REM/PF20
USB3DN_TXDM1A
8
68
SPI_CLK/PF21
VCORE
9
67
VDD33
USB3DN_RXDP1A
10
66
PF19
USB3DN_RXDM1A
11
65
TEST3
DP1_CC1
12
64
TEST2
DP1_CC2
13
63
TEST1
USB2DN_DP4/PRT_DIS_P4
14
62
VDD33
USB2DN_DM4/PRT_DIS_M4
15
61
PF18
USB3DN_TXDP1B
16
60
PF17
USB3DN_TXDM1B
17
59
PF16
VCORE
18
58
PF15
USB3DN_RXDP1B
19
57
PF14
USB3DN_RXDM1B
20
56
PF13
CFG_STRAP1
21
55
VCORE
CFG_STRAP2
22
54
PF12
CFG_STRAP3
23
53
VDD33
TESTEN
24
52
PF11
VCORE
25
51
PF10
Note:
Microchip
USB7252C
(Top View 100-VQFN)
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
VDD33
DP2_CC1
DP2_CC2
USB2DN_DP2/PRT_DIS_P2
USB2DN_DM2/PRT_DIS_M2
USB3DN_TXDP2A
USB3DN_TXDM2A
VCO RE
USB3DN_RXDP2A
USB3DN_RXDM2A
DP2_VBUS_MON
USB3DN_TXDP2B
USB3DN_TXDM2B
VCO RE
USB3DN_RXDP2B
USB3DN_RXDM2B
VDD33
PF2
PF3
PF4
PF5
PF6
PF7
PF8
PF9
Thermal slug connects to VSS
Configuration straps are identified by an underlined symbol name. Signals that function as configuration
straps must be augmented with an external resistor when connected to a load.
DS00003852A-page 8
2021 Microchip Technology Inc.
Pin Num
Pin Name
Reset
Pin Num
Pin Name
Reset
1
RESET_N
Z
51
PF10
PD
2
PF30
Z
52
PF11
PD
3
PF31
Z
53
VDD33
Z
4
DP1_VBUS_MON
AI
54
PF12
PD
5
USB2DN_DP1/PRT_DIS_P1
AIO PD
55
VCORE
Z
6
USB2DN_DM1/PRT_DIS_M1
AIO PD
56
PF13
PD
7
USB3DN_TXDP1A
AO PD
57
PF14
PD
8
USB3DN_TXDM1A
AO PD
58
PF15
PD
9
VCORE
Z
59
PF16
PD
10
USB3DN_RXDP1A
AI PD
60
PF17
PD
11
USB3DN_RXDM1A
AI PD
61
PF18
Z
12
DP1_CC1
AI
62
VDD33
Z
13
DP1_CC2
AI
63
TEST1
Z
14
USB2DN_DP4/PRT_DIS_P4
AIO PD
64
TEST2
Z
15
USB2DN_DM4/PRT_DIS_M4
AIO PD
65
TEST3
Z
16
USB3DN_TXDP1B
AO PD
66
PF19
Z
17
USB3DN_TXDM1B
AO PD
67
VDD33
Z
18
VCORE
Z
68
SPI_CLK/PF21
Z
19
USB3DN_RXDP1B
AI PD
69
SPI_CE_N/CFG_NON_REM/PF20
PU
20
USB3DN_RXDM1B
AI PD
70
SPI_D0/CFG_BC_EN/PF22
Z
21
CFG_STRAP1
Z
71
SPI_D1/PF23
Z
22
CFG_STRAP2
Z
72
SPI_D2/PF24
Z
23
CFG_STRAP3
Z
73
SPI_D3/PF25
Z
24
TESTEN
Z
74
PF29
Z
25
VCORE
Z
75
PF26
Z
26
VDD33
Z
76
PF27
Z
27
DP2_CC1
AI
77
PF28
Z
28
DP2_CC2
AI
78
VCORE
Z
29
USB2DN_DP2/PRT_DIS_P2
AIO PD
79
VDD33
Z
30
USB2DN_DM2/PRT_DIS_M2
AIO PD
80
VBUS_MON_UP
AI
31
USB3DN_TXDP2A
AO PD
81
USB2DN_DP3/PRT_DIS_P3
AIO PD
32
USB3DN_TXDM2A
AO PD
82
USB2DN_DM3/PRT_DIS_M3
AIO PD
33
VCORE
Z
83
USB3DN_TXDP3
AO PD
34
USB3DN_RXDP2A
AI PD
84
USB3DN_TXDM3
AO PD
35
USB3DN_RXDM2A
AI PD
85
VCORE
Z
36
DP2_VBUS_MON
AI
86
USB3DN_RXDP3
AI PD
37
USB3DN_TXDP2B
AO PD
87
USB3DN_RXDM3
AI PD
38
USB3DN_TXDM2B
AO PD
88
VDD33
Z
39
VCORE
Z
89
USB2UP_DP
AIO Z
40
USB3DN_RXDP2B
AI PD
90
USB2UP_DM
AIO Z
41
USB3DN_RXDM2B
AI PD
91
USB3UP_TXDP
AO PD
42
VDD33
Z
92
USB3UP_TXDM
AO PD
43
PF2
Z
93
VCORE
Z
44
PF3
Z
94
USB3UP_RXDP
AI PD
45
PF4
Z
95
USB3UP_RXDM
AI PD
46
PF5
Z
96
ATEST
AO
47
PF6
Z
97
XTALO
AO
48
PF7
Z
98
XTALI/CLK_IN
AI
49
PF8
Z
99
VDD33
Z
50
PF9
Z
100
RBIAS
AI
Exposed Pad (VSS) must be connected to ground.
2021 Microchip Technology Inc.
DS00003852A-page 9
3.2
Pin Descriptions
This section contains descriptions of the various USB7252C pins. The “_N” symbol in the signal name indicates that the
active, or asserted, state occurs when the signal is at a low voltage level. For example, RESET_N indicates that the
reset signal is active low. When “_N” is not present after the signal name, the signal is asserted when at the high voltage
level.
The terms assertion and negation are used exclusively. This is done to avoid confusion when working with a mixture of
“active low” and “active high” signal. The term assert, or assertion, indicates that a signal is active, independent of
whether that level is represented by a high or low voltage. The term negate, or negation, indicates that a signal is inactive.
The “If Unused” column provides information on how to terminate pins if they are unused in a customer design.
Buffer type definitions are detailed in Section 1.2, Buffer Types.
TABLE 3-1:
PIN DESCRIPTIONS
Name
Symbol
Buffer
Type
Description
If Unused
USB 3.2 Gen 2 Interfaces
Upstream USB
3.2 Gen 2 TX D+
USB3UP_TXDP
I/O-U
Upstream USB 3.2 Gen 2 Transmit Data
Plus.
Float
Upstream USB
3.2 Gen 2 TX D-
USB3UP_TXDM
I/O-U
Upstream USB 3.2 Gen 2 Transmit Data
Minus.
Float
Upstream USB
3.2 Gen 2 RX D+
USB3UP_RXDP
I/O-U
Upstream USB 3.2 Gen 2 Receive Data
Plus.
Weak pulldown to
GND
Upstream USB
3.2 Gen 2 RX D-
USB3UP_RXDM
I/O-U
Upstream USB 3.2 Gen 2 Receive Data
Minus.
Weak pulldown to
GND
Downstream
Port 1 USB 3.2
Gen 2 TX D+
Orientation A
USB3DN_TXDP1A
I/O-U
Downstream USB Type-C® “Orientation A”
SuperSpeed+ Transmit Data Plus, port 1.
Float
Downstream
Port 1 USB 3.2
Gen 2 TX D- Orientation A
USB3DN_TXDM1A
I/O-U
Downstream USB Type-C “Orientation A”
SuperSpeed+ Transmit Data Minus, port 1.
Float
Downstream
Port 1 USB 3.2
Gen 2 RX D+
Orientation A
USB3DN_RXDP1A
I/O-U
Downstream USB Type-C “Orientation A”
SuperSpeed+ Receive Data Plus, port 1.
Weak pulldown to
GND
Downstream
Port 1 USB 3.2
Gen 2 RX DOrientation A
USB3DN_RXDM1A
I/O-U
Downstream USB Type-C “Orientation A”
SuperSpeed+ Receive Data Minus, port 1.
Weak pulldown to
GND
Downstream
Port 1 USB 3.2
Gen 2 TX D+
Orientation B
USB3DN_TXDP1B
I/O-U
Downstream USB Type-C “Orientation B”
SuperSpeed+ Transmit Data Plus, port 1.
Float
DS00003852A-page 10
2021 Microchip Technology Inc.
TABLE 3-1:
PIN DESCRIPTIONS (CONTINUED)
Name
Symbol
Buffer
Type
Downstream
Port 1 USB 3.2
Gen 2 TX DOrientation B
USB3DN_TXDM1B
I/O-U
Downstream USB Type-C “Orientation B”
SuperSpeed+ Transmit Data Minus, port 1.
Float
Downstream
Port 1 USB 3.2
Gen 2 RX D+
Orientation B
USB3DN_RXDP1B
I/O-U
Downstream USB Type-C “Orientation B”
SuperSpeed+ Receive Data Plus, port 1.
Weak pulldown to
GND
Downstream
Port 1 USB 3.2
Gen 2 RX DOrientation B
USB3DN_RXDM1B
I/O-U
Downstream USB Type-C “Orientation B”
SuperSpeed+ Receive Data Minus, port 1.
Weak pulldown to
GND
Downstream
Port 2 USB 3.2
Gen 2 TX D+
Orientation A
USB3DN_TXDP2A
I/O-U
Downstream USB Type-C “Orientation A”
SuperSpeed+ Transmit Data Plus, port 2.
Float
Downstream
Port 2 USB 3.2
Gen 2 TX DOrientation A
USB3DN_TXDM2A
I/O-U
Downstream USB Type-C “Orientation A”
SuperSpeed+ Transmit Data Minus, port 2.
Float
Downstream
Port 2 USB 3.2
Gen 2 RX D+
Orientation A
USB3DN_RXDP2A
I/O-U
Downstream USB Type-C “Orientation A”
SuperSpeed+ Receive Data Plus, port 2.
Weak pulldown to
GND
Downstream
Port 2 USB 3.2
Gen 2 RX DOrientation A
USB3DN_RXDM2A
I/O-U
Downstream USB Type-C “Orientation A”
SuperSpeed+ Receive Data Minus, port 2.
Weak pulldown to
GND
Downstream
Port 2 USB 3.2
Gen 2 TX D+
Orientation B
USB3DN_TXDP2B
I/O-U
Downstream USB Type-C “Orientation B”
SuperSpeed+ Transmit Data Plus, port 2.
Float
Downstream
Port 2 USB 3.2
Gen 2 TX DOrientation B
USB3DN_TXDM2B
I/O-U
Downstream USB Type-C “Orientation B”
SuperSpeed+ Transmit Data Minus, port 2.
Float
Downstream
Port 2 USB 3.2
Gen 2 RX D+
Orientation B
USB3DN_RXDP2B
I/O-U
Downstream USB Type-C “Orientation B”
SuperSpeed+ Receive Data Plus, port 2.
Weak pulldown to
GND
Downstream
Port 2 USB 3.2
Gen 2 RX DOrientation B
USB3DN_RXDM2B
I/O-U
Downstream USB Type-C “Orientation B”
SuperSpeed+ Receive Data Minus, port 2.
Weak pulldown to
GND
2021 Microchip Technology Inc.
Description
If Unused
DS00003852A-page 11
TABLE 3-1:
PIN DESCRIPTIONS (CONTINUED)
Name
Symbol
Buffer
Type
Downstream
Port 3 USB 3.2
Gen 2 TX D+
USB3DN_TXDP3
I/O-U
Downstream SuperSpeed+ Transmit Data
Plus, port 3.
Float
Downstream
Port 3 USB 3.2
Gen 2 TX D-
USB3DN_TXDM3
I/O-U
Downstream SuperSpeed+ Transmit Data
Minus, port 3.
Float
Downstream
Port 3 USB 3.2
Gen 2 RX D+
USB3DN_RXDP3
I/O-U
Downstream SuperSpeed+ Receive Data
Plus, port 3.
Weak pulldown to
GND
Downstream
Port 3 USB 3.2
Gen 2 RX D-
USB3DN_RXDM3
I/O-U
Downstream SuperSpeed+ Receive Data
Minus, port 3.
Weak pulldown to
GND
Description
If Unused
USB 2.0 Interfaces
Upstream USB
2.0 D+
USB2UP_DP
I/O-U
Upstream USB 2.0 Data Plus (D+).
Mandatory
Note 3-12
Upstream USB
2.0 D-
USB2UP_DM
I/O-U
Upstream USB 2.0 Data Minus (D-).
Mandatory
Note 3-12
Downstream
Ports 1-4 USB
2.0 D+
USB2DN_DP[1:4]
I/O-U
Downstream USB 2.0 Ports 1-4 Data Plus
(D+).
Connect
directly to
3.3V
Downstream
Ports 1-4 USB
2.0 D-
USB2DN_DM[1:4]
I/O-U
Downstream USB 2.0 Ports 1-4 Data Minus
(D-)
Connect
directly to
3.3V
SPI Interface
SPI Clock
SPI_CLK
I/O-U
SPI clock. If the SPI interface is enabled,
this pin must be driven low during reset.
Weak pulldown to
GND
SPI Data 3-0
SPI_D[3:0]
I/O-U
SPI Data 3-0. If the SPI interface is enabled,
these signals function as Data 3 through 0.
Note 3-1
Note 3-1
DS00003852A-page 12
SPI_D0 operates as the
CFG_BC_EN s tra p if
external SPI memory is not
used. It must be terminated
with the selected stra p
resistor to 3.3V or GND.
SPI_ D[1 :3] sh ou ld b e
connected to GND through
a weak pull-down.
2021 Microchip Technology Inc.
TABLE 3-1:
PIN DESCRIPTIONS (CONTINUED)
Name
Symbol
Buffer
Type
SPI Chip
Enable
SPI_CE_N
I/O12
Description
If Unused
Active low SPI chip enable input. If the SPI
interface is enabled, this pin must be driven
high in powerdown states.
Note 3-2
Note 3-2
Operates
as
the
CFG_NON_REM strap if
external SPI memory is not
used. It must be terminated
with the selected strap
resistor to 3.3V or GND.
USB Type-C Connector Control
Downstream
Port 1 Type-C
Voltage Monitor
DP1_VBUS_MON
AIO
Used to detect Type-C VBUS vSafe5V and
vSafe0V states on Port 1. A nominal voltage
of 2.7V (2.4V min -3.0V max) is required to
detect the presence of vSafe5V.
Externally, VBUS can be as high as 5.25 V,
which can be damaging to this pin. The
amplitude of VBUS must be reduced by a
voltage divider. The recommended voltage
divider is shown below. 1% tolerance resistors are recommended.
Note 3-3
VBUS_P1
DP1_VBUS_MON
49.9K
43K
For proper Type-C port operation, it is critical that this pin actually be connected to
VBUS of the port through the recommended
resistor divider. This pin should not be tied
permanently to a fixed voltage power rail.
Note 3-3
Downstream
Port 1 Type-C
CC1
DP1_CC1
I/O12
Used for Type-C attach and orientation
detection on Port 1. Includes configurable
Rp/Ra selection. Connect this pin directly to
the CC1 pin of the respective Type-C connector.
Note 3-4
2021 Microchip Technology Inc.
If unused: Weak pull-down
to GND. This pin may be
left unused if P ort 1 is
disabled or reconfigured to
operate in legacy Type-A
mode
through
hub
configuration.
Note 3-4
If unused: Weak pull-down
to GND. This pin may only
be left unused if Port 1 is
disabled or reconfigured to
operate in legacy Type-A
mode
through
hub
configuration.
DS00003852A-page 13
TABLE 3-1:
PIN DESCRIPTIONS (CONTINUED)
Name
Symbol
Buffer
Type
Downstream
Port 1 Type-C
CC2
DP1_CC2
I/O12
Description
Used for Type-C attach and orientation
detection on Port 1. Includes configurable
Rp/Ra selection. Connect this pin directly to
the CC2 pin of the respective Type-C connector.
Note 3-5
Downstream
Port 2 Type-C
Voltage Monitor
DP2_VBUS_MON
AIO
If Unused
Note 3-5
If unused: Weak pull-down
to GND. This pin may only
be left unused if Port 1 is
disabled or reconfigured to
operate in legacy Type-A
mode
through
hub
configuration.
Used for detect Type-C VBUS vSafe5V and
vSafe0V states on Port 2. A nominal voltage of 2.7V (2.4V min -3.0V max) is
required to detect the presence of vSafe5V.
Externally, VBUS can be as high as 5.25 V,
which can be damaging to this pin. The
amplitude of VBUS must be reduced by a
voltage divider. The recommended voltage
divider is shown below. 1% tolerance resistors are recommended.
Note 3-6
VBUS_P2
DP2_VBUS_MON
49.9K
43K
For proper Type-C port operation, it is critical that this pin actually be connected to
VBUS of the port through the recommended
resistor divider. This pin should not be tied
permanently to a fixed voltage power rail.
Note 3-6
Downstream
Port 2 Type-C
CC1
DP2_CC1
I/O12
Used for Type-C attach and orientation
detection on Port 2. Includes configurable
Rp/Ra selection. Connect this pin directly to
the CC1 pin of the respective Type-C connector.
Note 3-7
DS00003852A-page 14
If unused: Weak pull-down
to GND. This pin may be
left unused if P ort 2 is
disabled or reconfigured to
operate in legacy Type-A
mode
through
hub
configuration.
Note 3-7
If unused: Weak pull-down
to GND. This pin may only
be left unused if Port 2 is
disabled or reconfigured to
operate in legacy Type-A
mode
through
hub
configuration.
2021 Microchip Technology Inc.
TABLE 3-1:
PIN DESCRIPTIONS (CONTINUED)
Name
Symbol
Buffer
Type
Downstream
Port 2 Type-C
CC2
DP2_CC2
I/O12
Description
Used for Type-C attach and orientation
detection on Port 2. Includes configurable
Rp/Ra selection. Connect this pin directly to
the CC2 pin of the respective Type-C connector.
Note 3-8
Upstream
Voltage Monitor
VBUS_MON_UP
I/O12
If Unused
Note 3-8
If unused: Weak pull-down
to GND. This pin may only
be left unused if Port 2 is
disabled or reconfigured to
operate in legacy Type-A
mode
through
hub
configuration.
Used to detect VBUS on the upstream port.
Externally, VBUS can be as high as 5.25 V,
which can be damaging to this pin. A nominal voltage of 2.7V (2.4V min -3.0V max) is
required to detect the presence of vSafe5V.
The amplitude of VBUS must be reduced by
a voltage divider. The recommended voltage
divider is shown below. 1% tolerance resistors are recommended.
Mandatory
Note 3-12
VBUS_UP
Note:
VBUS_MON_UP
49.9K
43K
For embedded host applications,
this pin should be controlled by
an I/O on the host processor to a
2.68V logic level.
Miscellaneous
Programmable
Function Pins
PF[31:2]
2021 Microchip Technology Inc.
I/O12
Note 3-9
Programmable function pins.
Note 3-9
If unused: depends on the
configured pin function.
R efe r to S e ctio n 3.3 .4,
P F [3 1 : 2 ] C o n fi g ur a ti o n
(CFG_STRAP[2:1])
DS00003852A-page 15
TABLE 3-1:
PIN DESCRIPTIONS (CONTINUED)
Name
Symbol
Buffer
Type
Test 1
TEST1
A
Description
If Unused
Test 1 pin.
This signal is used for test purposes and
must always be pulled-up to 3.3V via a 10
k resistor.
Test 2
TEST2
A
Test 2 pin.
This signal is used for test purposes and
must always be pulled-up to 3.3V via a 10
k resistor.
Test 3
TEST3
A
Test 3 pin.
This signal is used for test purposes and
must always be pulled-up to 3.3V via a 10
k resistor.
Pull to 3.3V
through a
10 k
resistor
Pull to 3.3V
through a
10 k
resistor
Pull to 3.3V
through a
10 k
resistor
Reset Input
RESET_N
IS
This active low signal is used by the system
to reset the device.
Mandatory
Note 3-12
Bias Resistor
RBIAS
I-R
A 12.0 k 1.0% resistor is attached from
ground to this pin to set the transceiver’s
internal bias settings. Place the resistor as
close the device as possible with a dedicated, low impedance connection to the
ground plane.
Mandatory
Note 3-12
Test
TESTEN
I/O12
Test pin.
Connect to
GND
This signal is used for test purposes and
must always be connected to ground.
Analog Test
ATEST
A
Float
Analog test pin.
This signal is used for test purposes and
must always be left unconnected.
External 25 MHz
Crystal Input
XTALI
ICLK
External 25 MHz crystal input
Mandatory
Note 3-12
External 25 MHz
Reference Clock
Input
CLK_IN
ICLK
External reference clock input.
Mandatory
Note 3-12
DS00003852A-page 16
The device may alternatively be driven by a
single-ended clock oscillator. When this
method is used, XTALO should be left
unconnected.
2021 Microchip Technology Inc.
TABLE 3-1:
PIN DESCRIPTIONS (CONTINUED)
Name
Symbol
Buffer
Type
External 25 MHz
Crystal Output
XTALO
OCLK
Description
If Unused
External 25 MHz crystal output
Float
(only if single-ended
clock is
connected
to CLK_IN)
Configuration Straps
Port 4-1 D+
Disable
Configuration
Strap
PRT_DIS_P[4:1]
I
Port 4-1 D+ Disable Configuration Strap.
N/A
These configuration straps are used in conjunction with the corresponding
PRT_DIS_M[4:1] straps to disable the
related port (4-1). See Note 3-13.
Both USB data pins for the corresponding
port must be tied to 3.3V to disable the
associated downstream port.
Port 4-1 DDisable
Configuration
Strap
PRT_DIS_M[4:1]
I
Port 4-1 D- Disable Configuration Strap.
These configuration straps are used in conjunction with the corresponding
PRT_DIS_P[4:1] straps to disable the
related port (4-1). See Note 3-13.
Mandatory
Note 3-12
Both USB data pins for the corresponding
port must be tied to 3.3V to disable the
associated downstream port.
Non-Removable
Ports
Configuration
Strap
CFG_NON_REM
I
Non-Removable Ports Configuration Strap.
This configuration strap controls the number
of reported non-removable ports. See
Note 3-13 .
Note 3-10
2021 Microchip Technology Inc.
Note 3-10
Mandatory if external SPI
memory is not used for
firmware execution. If
external SPI m emory is
used
for
firmware
execution,
then
configuration strap resistor
should be omitted.
DS00003852A-page 17
TABLE 3-1:
PIN DESCRIPTIONS (CONTINUED)
Name
Symbol
Buffer
Type
Battery Charging
Configuration
Strap
CFG_BC_EN
I/O12
Description
Battery Charging Configuration Strap.
This configuration strap controls the number
of BC 1.2 enabled downstream ports. See
Note 3-13.
Note 3-11
Device Mode
Configuration
Straps 3-1
If Unused
CFG_STRAP[3:1]
I
Mandatory
Note 3-12
Mandatory if external SPI
memory is not used for
firmware execution. If
external SPI m emory is
used
for
firmware
execution,
then
configuration strap resistor
should be omitted.
Device Mode Configuration Straps 3-1.
These configuration straps are used to
select the device’s mode of operation. See
Note 3-13.
Mandatory
Note 3-12
Power/Ground
+3.3V I/O Power
Supply Input
VDD33
P
+3.3 V power and internal regulator input.
Mandatory
Note 3-12
Digital Core
Power Supply
Input
VCORE
P
Digital core power supply input.
Mandatory
Note 3-12
Ground
VSS
P
Common ground.
Mandatory
Note 3-12
This exposed pad must be connected to the
ground plane with a via array.
Note 3-12
Configuration strap values are latched on Power-On Reset (POR) and the rising edge of RESET_N
(external chip reset). Configuration straps are identified by an underlined symbol name. Signals that
function as configuration straps must be augmented with an external resistor when connected to a
load. For additional information, refer to Section 3.3, Configuration Straps and Programmable
Functions.
Note 3-13
Pin use is mandatory. Cannot be left unused.
DS00003852A-page 18
2021 Microchip Technology Inc.
3.3
Configuration Straps and Programmable Functions
Configuration straps are multi-function pins that are used during Power-On Reset (POR) or external chip reset
(RESET_N) to determine the default configuration of a particular feature. The state of the signal is latched following
deassertion of the reset. Configuration straps are identified by an underlined symbol name. This section details the various device configuration straps and associated programmable pin functions.
Note:
3.3.1
The system designer must guarantee that configuration straps meet the timing requirements specified in
Section 9.6.2, Power-On and Configuration Strap Timing and Section 9.6.3, Reset and Configuration Strap
Timing. If configuration straps are not at the correct voltage level prior to being latched, the device may
capture incorrect strap values.
PORT DISABLE CONFIGURATION (PRT_DIS_P[4:1] / PRT_DIS_M[4:1])
The PRT_DIS_P[4:1] / PRT_DIS_M[4:1] configuration straps are used in conjunction to disable the related port (4-1)
For PRT_DIS_Px (where x is the corresponding port 4-1):
0 = Port x D+ Enabled
1 = Port x D+ Disabled
For PRT_DIS_Mx (where x is the corresponding port 4-1):
0 = Port x D- Enabled
1 = Port x D- Disabled
Note:
3.3.2
Both PRT_DIS_Px and PRT_DIS_Mx (where x is the corresponding port) must be tied to 3.3 V to disable
the associated downstream port. Disabling the USB 2.0 port will also disable the corresponding USB 3.0
port.
NON-REMOVABLE PORT CONFIGURATION (CFG_NON_REM)
The CFG_NON_REM configuration strap is used to configure the non-removable port settings of the device to one of
five settings. These modes are selected by the configuration of an external resistor on the CFG_NON_REM pin. The
resistor options are a 200 kΩ pull-down, 200 kΩ pull-up, 10 kΩ pull-down, 10 kΩ pull-up, and 10 Ω pull-down, as shown
in Table 3-2.
2021 Microchip Technology Inc.
DS00003852A-page 19
3.3.3
BATTERY CHARGING CONFIGURATION (CFG_BC_EN)
TABLE 3-2:
CFG_NON_REM RESISTOR ENCODING
CFG_NON_REM Resistor Value
Setting
200 kΩ Pull-Down
All ports removable
200 kΩ Pull-Up
Port 1 non-removable
10 kΩ Pull-Down
Ports 1, 2 non-removable
10 kΩ Pull-Up
Ports 1, 2, 3 non-removable
10 Ω Pull-Down
Ports 1, 2, 3, 4 non-removable
The CFG_BC_EN configuration strap is used to configure the battery charging port settings of the device to one of five
settings. These modes are selected by the configuration of an external resistor on the CFG_BC_EN pin. The resistor
options are a 200 kΩ pull-down, 200 kΩ pull-up, 10 kΩ pull-down, 10 kΩ pull-up, and 10 Ω pull-down, as shown in
Table 3-3.
TABLE 3-3:
CFG_BC_EN RESISTOR ENCODING
CFG_BC_EN Resistor Value
Setting
200 kΩ Pull-Down
Battery charging not enable on any port
200 kΩ Pull-Up
BC1.2 DCP and CDP battery charging enabled on Port 1
10 kΩ Pull-Down
BC1.2 DCP and CDP battery charging enabled on Ports 1, 2
10 kΩ Pull-Up
BC1.2 DCP and CDP battery charging enabled on Ports 1, 2, 3
10 Ω Pull-Down
BC1.2 DCP and CDP battery charging enabled on Ports 1, 2, 3, 4
PF[31:2] CONFIGURATION (CFG_STRAP[2:1])
3.3.4
The USB7252C provides 30 programmable function pins (PF[31:2]). These pins can be configured to 4 predefined configurations via the CFG_STRAP[2:1] pins. These configurations are selected via external resistors on the
CFG_STRAP[2:1] pins, as detailed in Table 3-4. Resistor values and combinations not detailed in Table 3-4 are reserved
and should not be used.
Note:
CFG_STRAP3 is not used and must be pulled-down to ground via a 200 k resistor.
TABLE 3-4:
CFG_STRAP[2:1] RESISTOR ENCODING
CFG_STRAP2
Resistor Value
CFG_STRAP1
Resistor Value
Configuration 1
200 kΩ Pull-Down
200 kΩ Pull-Down
Configuration 2
200 kΩ Pull-Down
200 kΩ Pull-Up
Configuration 3
200 kΩ Pull-Down
10 kΩ Pull-Down
Configuration 4
200 kΩ Pull-Down
10 kΩ Pull-Up
Mode
A summary of the configuration pin assignments for each of the 4 configurations is provided in Table 3-5. For details on
behavior of each programmable function, refer to Table 3-6.
TABLE 3-5:
Pin
PF[31:2] FUNCTION ASSIGNMENT
Configuration 1
(SMBus/I2C)
Configuration 2
(I2S)
Configuration 3
(UART)
Configuration 4
(GPIO & FlexConnect)
DP1_VCONN1
DP1_VCONN1
DP1_VCONN1
DP1_VCONN1
PF2
PF3
DP1_VCONN2
DP1_VCONN2
DP1_VCONN2
DP1_VCONN2
PF4
DP2_DISCHARGE
DP2_DISCHARGE
DP2_DISCHARGE
DP2_DISCHARGE
PF5
DP1_DISCHARGE
DP1_DISCHARGE
DP1_DISCHARGE
DP1_DISCHARGE
DS00003852A-page 20
2021 Microchip Technology Inc.
TABLE 3-5:
Pin
PF[31:2] FUNCTION ASSIGNMENT (CONTINUED)
Configuration 1
(SMBus/I2C)
Configuration 2
(I2S)
Configuration 3
(UART)
Configuration 4
(GPIO & FlexConnect)
PF6
GPIO70
GPIO70
UART_RX
GPIO70
PF7
GPIO71
MIC_DET
UART_TX
GPIO71
PF8
(
)
(
)
(
)
(
PF9
(
)
(
)
(
)
(
Note 3-1
Note 3-1
Note 3-1
Note 3-1
Note 3-1
Note 3-1
Note 3-1)
Note 3-1)
PF10
DP2_VCONN1
DP2_VCONN1
DP2_VCONN1
DP2_VCONN1
PF11
DP2_VCONN2
DP2_VCONN2
DP2_VCONN2
DP2_VCONN2
PF12
PRT_CTL3_U3
PRT_CTL3_U3
PRT_CTL3_U3
PRT_CTL3_U3
PF13
PRT_CTL3
PRT_CTL3
PRT_CTL3
PRT_CTL3
PF14
GPIO78
I2S_SDI
UART_nCTS
GPIO78
PF15
PRT_CTL2
PRT_CTL2
PRT_CTL2
PRT_CTL2
PF16
PRT_CTL4
PRT_CTL4
PRT_CTL4
PRT_CTL4
PF17
PRT_CTL1
PRT_CTL1
PRT_CTL1
PRT_CTL1
PF18
(Note
3-1)
(Note
3-1)
(Note
3-1)
(Note
3-1)
PF19
SLV_I2C_DATA
I2S_SDO
UART_nRTS
GPIO83
PF20
SPI_CE_N
SPI_CE_N
SPI_CE_N
SPI_CE_N
PF21
SPI_CLK
SPI_CLK
SPI_CLK
SPI_CLK
PF22
SPI_D0
SPI_D0
SPI_D0
SPI_D0
PF23
SPI_D1
SPI_D1
SPI_D1
SPI_D1
PF24
SPI_D2
SPI_D2
SPI_D2
SPI_D2
PF25
SPI_D3
SPI_D3
SPI_D3
SPI_D3
PF26
SLV_I2C_CLK
I2S_SCK
UART_nDSR
GPIO90
PF27
GPIO91
I2S_MCLK
UART_nDTR
GPIO91
PF28
GPIO92
I2S_LRCK
UART_nDCD
GPIO92
PF29
(
Note 3-1)
(
Note 3-1)
(
Note 3-1)
(
Note 3-1)
PF30
MSTR_I2C_CLK
MSTR_I2C_CLK
MSTR_I2C_CLK
MSTR_I2C_CLK
PF31
MSTR_I2C_DATA
MSTR_I2C_DATA
MSTR_I2C_DATA
MSTR_I2C_DATA
Note 3-1
Note:
The default function is not used in the USB7252C.
The default PFx pin functions can be overridden with additional configuration by modification of the pin mux
registers. These changes can be made during the SMBus configuration stage, by programming to OTP
memory, or during runtime (after hub has attached and enumerated) by register writes via the SMBus slave
interface or USB commands to the internal Hub Feature Controller Device.
2021 Microchip Technology Inc.
DS00003852A-page 21
TABLE 3-6:
PROGRAMMABLE FUNCTIONS DESCRIPTIONS
Function
Buffer
Type
Description
If Unused
Master SMBus/I2C Interface
MSTR_I2C_CLK
I/O12
Bridging Master SMBus/I2C controller clock (SMBus/I2C controller
1). External 1k-10k pull-up resistors to 3.3V are required if the I2C
Master Interface is to be used.
Weak pulldown to
GND
MSTR_I2C_DATA
I/O12
Bridging Master SMBus/I2C controller data (SMBus/I2C controller
1). External 1k-10k pull-up resistors to 3.3V are required if the I2C
Master Interface is to be used.
Weak pulldown to
GND
Slave SMBus/I2C Interface
SLV_I2C_CLK
I/O12
Slave SMBus/I2C controller clock (SMBus/I2C controller 2). External 1k-10k pull-up resistors to 3.3V are required if the I2C Slave
Interface is to be used.
Weak pulldown to
GND
SLV_I2C_DATA
I/O12
Slave SMBus/I2C controller data (SMBus/I2C controller 2). External
1k-10k pull-up resistors to 3.3V are required if the I2C Slave Interface is to be used.
Weak pulldown to
GND
UART Interface
UART_TX
O12
UART Transmit
Weak pulldown to
GND
UART_RX
I
UART Receive
Weak pulldown to
GND
UART_nCTS
I
UART Clear To Send
Weak pulldown to
GND
UART_nRTS
O12
UART Request To Send
Weak pulldown to
GND
UART_nDCD
I
UART Data Carrier Detect
Weak pulldown to
GND
UART_nDSR
I
UART Data Set Ready
Weak pulldown to
GND
UART_nDTR
O12
UART Data Terminal Ready
Weak pulldown to
GND
I2S Interface
I2S_SDI
DS00003852A-page 22
I
I2S Serial Data In
Weak pulldown to
GND
2021 Microchip Technology Inc.
TABLE 3-6:
PROGRAMMABLE FUNCTIONS DESCRIPTIONS (CONTINUED)
Function
Buffer
Type
I2S_SDO
O12
I2S Serial Data Out
Weak pulldown to
GND
I2S_SCK
O12
I2S Continuous Serial Clock
Weak pulldown to
GND
I2S_LRCK
O12
I2S Word Select / Left-Right Clock
Weak pulldown to
GND
I2S_MCLK
O12
I2S Master Clock
Weak pulldown to
GND
MIC_DET
I
I2S Microphone Plug Detect
Weak pulldown to
GND
Description
If Unused
0 = No microphone plugged into the audio jack
1 = Microphone plugged into the audio jack
Miscellaneous
DP2_VCONN1
I/O12
Port 2 VCONN1 enable. Active high signal.
0 = VCONN is turned off.
1 = VCONN is turned on. If DP2_VCONN1 is asserted and >3.0V is
not sensed on the CC1 line, a VCONN fault condition is detected.
Note 3-1
DP2_VCONN2
I/O12
This pin can be left unused only if Port 2 is
disabled or reconfigured to operate as a legacy
Type-A port via OTP/SMBus/SPI configuration.
Port 2 VCONN2 enable. Active high signal.
0 = VCONN is turned off.
1 = VCONN is turned on. If DP2_VCONN2 is asserted and >3.0V is
not sensed on the CC2 line, a VCONN fault condition is detected.
Note 3-2
DP2_DISCHARGE
I/O12
0 = VBUS discharging is not active.
1 = VBUS is being discharged to GND. This pin only asserts for a
short duration when VBUS is being discharged from 5V (vSafe5V)
to 0V (vSafe0V).
2021 Microchip Technology Inc.
Weak pulldown to
GND
(Note 3-2)
This pin can be left unused only if Port 2 is
disabled or reconfigured to operate as a legacy
Type-A port via OTP/SMBus/SPI configuration.
Port 2 DISCHARGE enable. Active high signal.
Note 3-3
Weak pulldown to
GND
(Note 3-1)
Weak pulldown to
GND
(Note 3-3)
This pin can be left unused only if Port 2 is
disabled or reconfigured to operate as a legacy
Type-A port via OTP/SMBus/SPI configuration.
DS00003852A-page 23
TABLE 3-6:
PROGRAMMABLE FUNCTIONS DESCRIPTIONS (CONTINUED)
Function
Buffer
Type
DP1_VCONN1
I/O12
Description
If Unused
Port 1 VCONN1 enable. Active high signal.
0 = VCONN is turned off.
1 = VCONN is turned on. If DP1_VCONN1 is asserted and >3.0V is
not sensed on the CC1 line, a VCONN fault condition is detected.
Note 3-4
DP1_VCONN2
I/O12
This pin can be left unused only if Port 1 is
disabled or reconfigured to operate as a legacy
Type-A port via OTP/SMBus/SPI configuration.
Port 1 VCONN2 enable. Active high signal.
0 = VCONN is turned off.
1 = VCONN is turned on. If DP1_VCONN2 is asserted and >3.0V is
not sensed on the CC2 line, a VCONN fault condition is detected.
Note 3-5
DP1_DISCHARGE
I/O12
0 = VBUS discharging is not active.
1 = VBUS is being discharged to GND. This pin only asserts for a
short duration when VBUS is being discharged from 5V (vSafe5V)
to 0V (vSafe0V).
PRT_CTL4
I/O12
(PU)
Weak pulldown to
GND
(Note 3-5)
This pin can be left unused only if Port 1 is
disabled or reconfigured to operate as a legacy
Type-A port via OTP/SMBus/SPI configuration.
Port 1 DISCHARGE enable. Active high signal.
Note 3-6
Weak pulldown to
GND
(Note 3-4)
Weak pulldown to
GND
(Note 3-6)
This pin can be left unused only if Port 1 is
disabled or reconfigured to operate as a legacy
Type-A port via OTP/SMBus/SPI configuration.
Port 4 power enable / overcurrent sense
When the downstream port is enabled, this pin is set as an input
with an internal pull-up resistor applied. The internal pull-up
enables power to the downstream port while the pin monitors for an
active low overcurrent signal assertion from an external current
monitor on USB port 4.
Float
(Note 3-7)
This pin will change to an output and be driven low when the port is
disabled by configuration or by the host control.
Note:
Note 3-7
DS00003852A-page 24
This signal controls both the USB 2.0 and USB 3.2 portions of the port.
This pin can be left unused only if Port 4 is
disabled via strap/OTP/SMBus/SPI configuration.
2021 Microchip Technology Inc.
TABLE 3-6:
Function
PRT_CTL3
PROGRAMMABLE FUNCTIONS DESCRIPTIONS (CONTINUED)
Buffer
Type
I/O12
(PU)
Description
If Unused
Port 3 power enable / overcurrent sense
When the downstream port is enabled, this pin is set as an input
with an internal pull-up resistor applied. The internal pull-up
enables power to the downstream port while the pin monitors for an
active low overcurrent signal assertion from an external current
monitor on USB port 3.
Float
(Note 3-8)
This pin will change to an output and be driven low when the port is
disabled by configuration or by the host control.
Note:
When PortSplit is disabled, this signal controls both the
USB 2.0 and USB 3.2 portions of the port. When
PortSplit is enabled, this signal controls the USB 2.0
portion of the port only.
Note 3-8
PRT_CTL2
I/O12
(PU)
This pin can be left unused only if Port 3 is
disabled via strap/OTP/SMBus/SPI configuration.
Port 2 power enable / overcurrent sense
When the downstream port is enabled, this pin is set as an input
with an internal pull-up resistor applied. The internal pull-up
enables power to the downstream port while the pin monitors for an
active low overcurrent signal assertion from an external current
monitor on USB port 2.
Float
(Note 3-9)
This pin will change to an output and be driven low when the port is
disabled by configuration or by the host control.
Note:
This signal controls both the USB 2.0 and USB 3.2 portions of the port.
Note 3-9
PRT_CTL1
I/O12
(PU)
This pin can be left unused only if Port 2 is
disabled via strap/OTP/SMBus/SPI configuration.
Port 1 power enable / overcurrent sense
When the downstream port is enabled, this pin is set as an input
with an internal pull-up resistor applied. The internal pull-up
enables power to the downstream port while the pin monitors for an
active low overcurrent signal assertion from an external current
monitor on USB port 1.
Float
(Note 3-9)
This pin will change to an output and be driven low when the port is
disabled by configuration or by the host control.
Note:
This signal controls both the USB 2.0 and USB 3.2 portions of the port.
Note 3-10
2021 Microchip Technology Inc.
This pin can be left unused only if Port 1 is
disabled via strap/OTP/SMBus/SPI configuration.
DS00003852A-page 25
TABLE 3-6:
PROGRAMMABLE FUNCTIONS DESCRIPTIONS (CONTINUED)
Function
Buffer
Type
PRT_CTL3_U3
O12
Description
If Unused
Float
Port 3 USB 3.2 PortSplit power enable
This signal is an active high control signal used to enable to the
USB 3.2 portion of the downstream port 3 when PortSplit is
enabled. When PortSplit is disabled, this pin is not used.
Note:
GPIOx
3.4
I/O12
This signal should only be used to control an embedded
USB 3.2 device.
General Purpose Inputs/Outputs
(x = 70-71, 78, 83, 90-92)
Weak pulldown to
GND
Physical and Logical Port Mapping
The USB72xx family of devices are based upon a common architecture, but all have different modifications and/or pin
bond outs to achieve the various device configurations. The base chip is composed of a total of 6 USB3 PHYs and 7
USB2 PHYs. These PHYs are physically arranged on the chip in a certain way, which is referred to as the PHYSICAL
port mapping.
The actual port numbering is remapped by default in different ways on each device in the family. This changes the way
that the ports are numbered from the USB host’s perspective. This is referred to as LOGICAL mapping.
The various configuration options available for these devices may, at times, be with respect to PHYSICAL mapping or
LOGICAL mapping. Each individual configuration option which has a PHYSICAL or LOGICAL dependency is declared
as such within the register description.
The PHYSICAL vs. LOGICAL mapping is described for all port related pins in Table 3-7. A system design in schematics
and layout is generally performed using the pinout in Section 3.1, Pin Assignments, which is assigned by the default
LOGICAL mapping. Hence, it may be necessary to cross reference the PHYSICAL vs. LOGICAL look up tables when
determining the hub configuration.
Note:
The MPLAB Connect tool makes configuration simple; the settings can be selected by the user with respect
to the LOGICAL port numbering. The tool handles the necessary linking to the PHYSICAL port settings.
Refer to Section 6.0, Device Configuration for additional information.
DS00003852A-page 26
2021 Microchip Technology Inc.
TABLE 3-7:
Device
Pin
USB7252C PHYSICAL VS. LOGICAL PORT MAPPING
Pin Name (as in datasheet)
LOGICAL PORT NUMBER
0
1
2
3
4
PHYSICAL PORT NUMBER
0
1
5
USB2DN_DP1
X
X
6
USB2DN_DM1
X
X
7
USB3DN_TXDP1A
X
X
8
USB3DN_TXDM1A
X
X
10
USB3DN_RXDP1A
X
X
X
2
3
11
USB3DN_RXDM1A
14
USB2DN_DP4
15
USB2DN_DM4
16
USB3DN_TXDP1B
X
X
17
USB3DN_TXDM1B
X
X
19
USB3DN_RXDP1B
X
X
20
USB3DN_RXDM1B
X
29
USB2DN_DP2
X
X
30
USB2DN_DM2
X
X
31
USB3DN_TXDP2A
X
X
32
USB3DN_TXDM2A
X
X
34
USB3DN_RXDP2A
X
X
35
USB3DN_RXDM2A
X
X
37
USB3DN_TXDP2B
X
4
5
X
X
X
X
X
X
X
38
USB3DN_TXDM2B
X
X
40
USB3DN_RXDP2B
X
X
X
41
USB3DN_RXDM2B
81
USB2DN_DP3
X
X
82
USB2DN_DM3
X
X
83
USB3DN_TXDP3
X
X
84
USB3DN_TXDM3
X
X
86
USB3DN_RXDP3
X
X
87
USB3DN_RXDM3
89
USB2UP_DP
X
X
90
USB2UP_DM
X
X
91
USB3UP_TXDP
X
X
92
USB3UP_TXDM
X
X
94
USB3UP_RXDP
X
X
95
USB3UP_RXDM
X
X
2021 Microchip Technology Inc.
6
X
X
X
DS00003852A-page 27
4.0
DEVICE CONNECTIONS
4.1
Power Connections
Figure 4-1 illustrates the device power connections.
FIGURE 4-1:
POWER CONNECTIONS
+3.3V
Supply
VCORE
Supply
VDD33 (x8)
USB7252C
F
u
1
0
.0
0
+3.3V
+3.3V
F
u
1
.
0
F
u
7
.
4
VCORE (x9)
Digital Core
Internal Logic
3.3V Internal Logic
VSS (exposed pad)
F
u
1
0
.0
0
x8
4.2
VCORE
VCORE
F
u
1
.
0
F
u
7
.
4
x9
SPI Flash Connections
Figure 4-2 illustrates the Quad-SPI flash connections.
FIGURE 4-2:
QUAD-SPI FLASH CONNECTIONS
+3.3V
K
0
1
SPI_CE_N
CE#
SPI_CLK
CLK
SPI_D0
SIO0
SPI_D1
SIO1
SPI_D2
SIO2/WPn
SPI_D3
SIO3/HOLDn
USB7252C
DS00003852A-page 28
Quad-SPI Flash
2021 Microchip Technology Inc.
4.3
SMBus/I2C Connections
Figure 4-3 illustrates the SMBus/I2C connections.
FIGURE 4-3:
SMBUS/I2C CONNECTIONS
+3.3V
4.7K
Clock
x_I2C_CLK
USB7252C
SMBus/I2C
+3.3V
4.7K
Data
x_I2C_DAT
4.4
I2S Connections
Figure 4-4 illustrates the I2S connections.
FIGURE 4-4:
I2S CONNECTIONS
+3.3V
USB7252C
K
0
1
K
0
1
CODEC
I2S_MCLK
I2S_SCK
I2S
I2S_LRCK
I2S_SDO
I2S_SD
MSTR_I2C_CLK
I2C
MSTR_I2C_DAT
MIC_DET
2021 Microchip Technology Inc.
Audio Jack
DS00003852A-page 29
4.5
UART Connections
Figure 4-5 illustrates the UART connections.
FIGURE 4-5:
UART CONNECTIONS
USB7252C
UART
Transceiver
UART
Connector
UART_TX
UART_RX
UART_nRTS
UART_nCTS
UART_nDTR
UART_nDSR
UART_nDCD
DS00003852A-page 30
2021 Microchip Technology Inc.
5.0
MODES OF OPERATION
The device provides two main modes of operation: Standby Mode and Hub Mode. These modes are controlled via the
RESET_N pin, as shown in Table 5-1.
TABLE 5-1:
MODES OF OPERATION
RESET_N Input
Summary
0
Standby Mode: This is the lowest power mode of the device. No functions are active
other than monitoring the RESET_N input. All port interfaces are high impedance and
the PLL is halted. Refer to Section 8.12, Resets for additional information on
RESET_N.
1
Hub (Normal) Mode: The device operates as a configurable USB hub. This mode has
various sub-modes of operation, as detailed in Figure 5-1. Power consumption is based
on the number of active ports, their speed, and amount of data received.
The flowchart in Figure 5-1 details the modes of operation and details how the device traverses through the Hub Mode
stages (shown in bold). The remaining sub-sections provide more detail on each stage of operation.
FIGURE 5-1:
HUB MODE FLOWCHART
RESET_N deasserted
(SPI_INIT)
(CFG_ROM)
In SPI Mode
& Ext. SPI ROM
present?
NO
Load Config from
Internal ROM
YES
(CFG_STRAP)
Modify Config
Based on Config
Straps
Run From
External SPI ROM
YES
Perform SMBus/I2C
Initialization
YES
Configuration 1?
NO
SMBus Slave Pull-ups?
NO
(SMBUS_CHECK)
NO
SOC Done?
(CFG_SMBUS) YES
Combine OTP
Config Data
(CFG_OTP)
Hub Connect
(USB_ATTACH)
Normal Operation
(NORMAL_MODE)
2021 Microchip Technology Inc.
DS00003852A-page 31
5.1
5.1.1
Boot Sequence
STANDBY MODE
If the RESET_N pin is asserted, the hub will be in Standby Mode. This mode provides a very low power state for maximum power efficiency when no signaling is required. This is the lowest power state. In Standby Mode all downstream
ports are disabled, the USB data pins are held in a high-impedance state, all transactions immediately terminate (no
states saved), all internal registers return to their default state, the PLL is halted, and core logic is powered down in order
to minimize power consumption. Because core logic is powered off, no configuration settings are retained in this mode
and must be re-initialized after RESET_N is negated high.
5.1.2
SPI INITIALIZATION STAGE (SPI_INIT)
The first stage, the initialization stage, occurs on the deassertion of RESET_N. In this stage, the internal logic is reset,
the PLL locks if a valid clock is supplied, and the configuration registers are initialized to their default state. The internal
firmware then checks for an external SPI ROM. The firmware looks for an external SPI flash device that contains a valid
signature of “2DFU” (device firmware upgrade) beginning at address 0x3FFFA. If a valid signature is found, then the
external SPI ROM is enabled and the code execution begins at address 0x0000 in the external SPI device. If a valid
signature is not found, then execution continues from internal ROM (CFG_ROM stage).
The required SPI ROM must be a minimum of 1 Mbit, and 60 MHz or faster. Both 1, 2, and 4-bit SPI operation is supported. For optimum throughput, a 2-bit SPI ROM is recommended. Both mode 0 and mode 3 SPI ROMs are also supported.
If the system is not strapped for SPI Mode, code execution will continue from internal ROM (CFG_ROM stage).
5.1.3
CONFIGURATION FROM INTERNAL ROM STAGE (CFG_ROM)
In this stage, the internal firmware loads the default values from the internal ROM. Most of the hub configuration registers, USB descriptors, electrical settings, etc. will be initialized in this state.
5.1.4
CONFIGURATION STRAP READ STAGE (CFG_STRAP)
In this stage, the firmware reads the following configuration straps to override the default values:
•
•
•
•
•
CFG_STRAP[3:1]
PRT_DIS_P[4:1]
PRT_DIS_M[4:1]
CFG_NON_REM
CFG_BC_EN
If the CFG_STRAP[3:1] pins are set to Configuration 1, the device will move to the SMBUS_CHECK stage, otherwise
it will move to the CFG_OTP stage. Refer to Section 3.3, Configuration Straps and Programmable Functions for information on usage of the various device configuration straps.
5.1.5
SMBUS CHECK STAGE (SMBUS_CHECK)
Based on the PF[31:2] configuration selected (refer to Section 3.3.4, PF[31:2] Configuration (CFG_STRAP[2:1])), the
firmware will check for the presence of external pull up resistors on the SMBus slave programmable function pins. If 10K
pull-ups are detected on both pins, the device will be configured as an SMBus slave, and the next state will be CFG_SMBUS. If a pull-up is not detected in either of the pins, the next state is CFG_OTP.
5.1.6
SMBUS CONFIGURATION STAGE (CFG_SMBUS)
In this stage, the external SMBus master can modify any of the default configuration settings specified in the integrated
ROM, such as USB device descriptors, port electrical settings, and control features such as downstream battery
charging.
There is no time limit on this mode. In this stage the firmware will wait indefinitely for the SMBus/I2C configuration. The
external SMBus master writes to register 0xFF to end the configuration in legacy mode. In non-legacy mode, the SMBus
command USB_ATTACH (opcode 0xAA55) or USB_ATTACH_WITH_SMBUS (opcode 0xAA56) will finish the configuration.
DS00003852A-page 32
2021 Microchip Technology Inc.
5.1.7
OTP CONFIGURATION STAGE (CFG_OTP)
Once the SOC has indicated that it is done with configuration, all configuration data is combined in this stage. The
default data, the SOC configuration data, and the OTP data are all combined in the firmware and the device is programmed.
Note:
5.1.8
If the same register is modified in both CFG_SMBUS and CFG_OTP stages, the value from CFG_OTP will
overwrite any value written during CFG_SMBUS.
HUB CONNECT STAGE (USB_ATTACH)
Once the hub registers are updated through default values, SMBus master, and OTP, the device firmware will enable
attaching the USB host by setting the USB_ATTACH bit in the HUB_CMD_STAT register (for USB 2.0) and the
USB3_HUB_ENABLE bit (for USB 3.2). The device will remain in the Hub Connect stage indefinitely.
5.1.9
NORMAL MODE (NORMAL_MODE)
Lastly, the hub enters Normal Mode of operation. In this stage full USB operation is supported under control of the USB
Host on the upstream port. The device will remain in the normal mode until the operating mode is changed by the system.
If RESET_N is asserted low, then Standby Mode is entered. The device may then be placed into any of the designated
hub stages. Asserting a soft disconnect on the upstream port will cause the hub to return to the Hub Connect stage until
the soft disconnect is negated.
2021 Microchip Technology Inc.
DS00003852A-page 33
6.0
DEVICE CONFIGURATION
The device supports a large number of features (some mutually exclusive), and must be configured in order to correctly
function when attached to a USB host controller. Microchip provides a comprehensive software programming tool,
MPLAB Connect Configurator (formerly ProTouch2), for OTP configuration of various USB7252C functions and registers. All configuration is to be performed via the MPLAB Connect Configurator programming tool. For additional information on this tool, refer to the MPLAB Connect Configurator programming tool product page at http://
www.microchip.com/design-centers/usb/mplab-connect-configurator.
Additional information on configuring the USB7252C is also provided in the “Configuration of the USB720x/USB725x”
application note, which contains details on the hub operational mode, SOC configuration stage, OTP configuration, USB
configuration, and configuration register definitions. This application note, along with additional USB7252C resources,
can be found on the Microchip USB7252C product page at www.microchip.com/USB7252.
Note:
Device configuration straps and programmable pins are detailed in Section 3.3, Configuration Straps and
Programmable Functions.
Refer to Section 7.0, Device Interfaces for detailed information on each device interface.
DS00003852A-page 34
2021 Microchip Technology Inc.
7.0
DEVICE INTERFACES
The USB7252C provides multiple interfaces for configuration, external memory access, etc.. This section details the
various device interfaces:
•
•
•
•
SPI/SQI Master Interface
SMBus/I2C Master/Slave Interfaces
I2S Interface
UART Interface
Note:
For details on how to enable each interface, refer to Section 3.3, Configuration Straps and Programmable
Functions.
For information on device connections, refer to Section 4.0, Device Connections. For information on device
configuration, refer to Section 6.0, Device Configuration.
Microchip provides a comprehensive software programming tool, MPLAB Connect Configurator (formerly
ProTouch2), for configuring the USB7252C functions, registers and OTP memory. All configuration is to be
performed via the MPLAB Connect Configurator programming tool. For additional information on this tool,
refer to th MPLAB Connect Configurator programming tool product page at http://www.microchip.com/
design-centers/usb/mplab-connect-configurator.
7.1
SPI/SQI Master Interface
The SPI/SQI controller has two basic modes of operation: execution of an external hub firmware image, or the USB to
SPI bridge. On power up, the firmware looks for an external SPI flash device that contains a valid signature of 2DFU
(device firmware upgrade) beginning at address 0x3FFFA. If a valid signature is found, then the external ROM mode is
enabled and the code execution begins at address 0x0000 in the external SPI device. If a valid signature is not found,
then execution continues from internal ROM and the SPI interface can be used as a USB to SPI bridge.
The entire firmware image is then executed in place entirely from the SPI interface. The SPI interface will remain continuously active while the hub is in the runtime state. The hub configuration options are also loaded entirely out of the
SPI memory device. Both the internal ROM firmware image and internal OTP memory are completely ignored while executing the firmware and configuration from the external SPI memory.
The second mode of operation is the USB to SPI bridge operation. Additional details on this feature can be found in
Section 8.9, USB to SPI Bridging.
Table 7-1 details how the associated pins are mapped in SPI vs. SQI mode
TABLE 7-1:
Note:
SPI/SQI PIN USAGE
SPI Mode
SQI Mode
Description
SPI_CE_N
SQI_CE_N
SPI/SQI Chip Enable (Active Low)
SPI_CLK
SQI_CLK
SPI/SQI Clock
SPI_D0
SQI_D0
SPI Data Out; SQI Data I/O 0
SPI_D1
SQI_D1
SPI Data In; SQI Data I/O 1
-
SQI_D2
SQI Data I/O 2
-
SQI_D3
SQI Data I/O 3
For SPI/SQI master timing information, refer to Section 9.6.10, SPI/SQI Master Timing.
2021 Microchip Technology Inc.
DS00003852A-page 35
7.2
SMBus/I2C Master/Slave Interfaces
The device provides two independent SMBus/I2C controllers (Slave, and Master) which can be used to access internal
device run time registers or program the internal OTP memory. The device contains two 128 byte buffers to enable
simultaneous master/slave operation and to minimize firmware overhead in processed I2C packets. The I2C interfaces
support 100KHz Standard-mode (Sm) and 400KHz Fast Mode (Fm) operation.
The SMBus/I2C interfaces are assigned to programmable pins (PFx) and therefore the device must be programmed into
specific configurations to enable specific interfaces. Refer to Section 3.3.4, PF[31:2] Configuration (CFG_STRAP[2:1])
for additional information.
Note:
7.3
For SMBus/I2C timing information, refer to Section 9.6.7, SMBus Timing and Section 9.6.8, I2C Timing.
I2S Interface
The device provides an integrated I2S interface to facilitate the connection of digital audio devices. The I2S interface
conforms to the voltage, power, and timing characteristics/specifications as set forth in the I2S-Bus Specification, and
consists of the following signals:
•
•
•
•
•
•
I2S_SDI: Serial Data Input
I2S_SDO: Serial Data Output
I2S_SCK: Serial Clock
I2S_LRCK: Left/Right Clock (SS/FSYNC)
I2S_MCLK: Master Clock
MIC_DET: Microphone Plug Detect
Each audio connection is half-duplex, so I2S_SDO exists only on the transmit side and I2S_SDI exists only on the
receive side of the interface. Some codecs refer to the Serial Clock (I2S_SCK) as Baud/Bit Clock (BCLK). Also, the Left/
Right Clock is commonly referred to as LRC or LRCK. The I2S and other audio protocols refer to LRC as Word Select
(WS).
The following codec is supported by default:
• Analog Devices ADAU1961 (24-bit 96KHz)
The I2S interface is assigned to programmable pins (PFx) and therefore the device must be programmed into specific
configurations to enable the interface. Refer to Section 3.3.4, PF[31:2] Configuration (CFG_STRAP[2:1]) for additional
information.
Note:
7.3.1
For I2S timing information, refer to Section 9.6.9, I2S Timing. For detailed information on utilizing the I2S
interface, including support for other codecs, refer to the application note “USB720x/USB725x I2S Operation”, which can be found on the Microchip USB7252C product page at www.microchip.com/USB7252C.
MODES OF OPERATION
The USB audio class operates in three ways: Asynchronous, Synchronous and Adaptive. There are also multiple operating modes, such as hi-res, streaming, etc.. Typically for USB devices, inputs such as microphones are Asynchronous,
and output devices such as speakers are Adaptive. The hardware is set up to handle all three modes of operation. It is
recommended that the following configuration be used: Asynchronous IN; Adaptive OUT; 48Khz streaming mode; Two
channels: 16 bits per channel.
7.3.1.1
Asynchronous IN 48KHz Streaming
In this mode, the codec sampling clock is set to 48Khz based on the local oscillator. This clock is never changed. The
data from the codec is fed into the input FIFO. Since the sampling clock is asynchronous to the host clock, the amount
of data captured in every USB frame will vary. This issue is left for the host to handle. The input FIFO has two markers,
a low water mark (THRESHOLD_LOW_VAL), and a high water mark (THRESHOLD_HIGH_VAL). There are three registers to determine how much data to send back in each frame. If the amount of data in the FIFO exceeds the high water
mark, then HI_PKT_SIZE worth of data is sent. If the data is between the high and low water mark, the normal MID_PKT_SIZE amount of data is sent. If the data is below the low water mark, LO_PKT_SIZE worth of data is sent.
DS00003852A-page 36
2021 Microchip Technology Inc.
7.3.1.2
Adaptive OUT 48KHz Streaming
In this mode, the codec sampling clock is initially set to 48Khz based on the local oscillator. The host data is fed into the
OUT FIFO. The host will send the same amount of data on every frame, i.e. 48KHz of data based on the host clock. The
codec sampling clock is asynchronous to the host clock. This will cause the amount of data in the OUT FIFO to vary. If
the amount of data in the FIFO exceeds the high water mark, then the sampling clock is increased. If the data is between
the high and low water mark, the sampling clock does not change. If the data is below the low water mark, the sampling
clock is decreased.
7.3.1.3
Synchronous Operation
For synchronous operation, the internal clock must be synchronized with the host SOF. The Frame SOF is nominally
1mS. Since there is significant jitter in the SOFs, there is circuitry provided to measure the SOFs over a long period of
time to get a more accurate reading. The calculated host frequency is used to calculate the codec sampling clock.
7.4
UART Interface
The device incorporates a configurable universal asynchronous receiver/transmitter (UART) that is functionally compatible with the NS 16550AF, 16450, 16450 ACE registers and the 16C550A. The UART performs serial-to-parallel conversion on received characters and parallel-to-serial conversion on transmit characters. Two sets of baud rates are
provided: 24 Mhz and 16 MHz. When the 24 Mhz source clock is selected, standard baud rates from 50 to 115.2 K are
available. When the source clock is 16 MHz, baud rates from 125 K to 1,000 K are available. The character options are
programmable for the transmission of data in word lengths of from five to eight, 1 start bit; 1, 1.5 or 2 stop bits; even,
odd, sticky or no parity; and prioritized interrupts. The UART contains a programmable baud rate generator that is capable of dividing the input clock or crystal by a number from 1 to 65535. The UART is also capable of supporting the MIDI
data rate.
The UART interface is assigned to programmable pins (PFx) and therefore the device must be programmed into specific
configurations to enable the interface. Refer to Section 3.3.4, PF[31:2] Configuration (CFG_STRAP[2:1]) for additional
information.
7.4.1
TRANSMIT OPERATION
Transmission is initiated by writing the data to be sent to the TX Holding Register or TX FIFO (if enabled). The data is
then transferred to the TX Shift Register together with a start bit and parity and stop bits as determined by settings in
the Line Control Register. The bits to be transmitted are then shifted out of the TX Shift Register in the order Start bit,
Data bits (LSB first), Parity bit, Stop bit, using the output from the Baud Rate Generator (divided by 16) as the clock.
If enabled, a TX Holding Register Empty interrupt will be generated when the TX Holding Register or the TX FIFO (if
enabled) becomes empty.
When FIFOs are enabled (i.e. bit 0 of the FIFO Control Register is set), the UART can store up to 16 bytes of data for
transmission at a time. Transmission will continue until the TX FIFO is empty. The FIFO’s readiness to accept more data
is indicated by interrupt.
7.4.2
RECEIVE OPERATION
Data is sampled into the RX Shift Register using the Receive clock, divided by 16. The Receive clock is provided by the
Baud Rate Generator. A filter is used to remove spurious inputs that last for less than two periods of the Receive clock.
When the complete word has been clocked into the receiver, the data bits are transferred to the RX Buffer Register or
to the RX FIFO (if enabled) to be read by the CPU. (The first bit of the data to be received is placed in bit 0 of this register.) The receiver also checks that the parity bit and stop bits are as specified by the Line Control Register.
If enabled, an RX Data Received interrupt will be generated when the data has been transferred to the RX Buffer Register or, if FIFOs are enabled, when the RX Trigger Level has been reached. Interrupts can also be generated to signal
RX FIFO Character Timeout, incorrect parity, a missing stop bit (frame error) or other Line Status errors.
When FIFOs are enabled (i.e. bit 0 of the FIFO Control Register is set), the UART can store up to 16 bytes of received
data at a time. Depending on the selected RX Trigger Level, interrupt will go active to indicate that data is available when
the RX FIFO contains 1, 4, 8 or 14 bytes of data.
2021 Microchip Technology Inc.
DS00003852A-page 37
8.0
FUNCTIONAL DESCRIPTIONS
This section details various USB7252C functions, including:
•
•
•
•
•
•
•
•
•
•
•
•
Downstream Battery Charging
Port Power Control
CC Pin Orientation and Detection
PortSplit
FlexConnect
Multi-Host Endpoint Reflector
USB to GPIO Bridging
USB to I2C Bridging
USB to SPI Bridging
USB to UART Bridging
Link Power Management (LPM)
Resets
8.1
Downstream Battery Charging
The device can be configured by an OEM to have any of the downstream ports support battery charging. The hub’s role
in battery charging is to provide acknowledgment to a device’s query as to whether the hub system supports USB battery
charging. The hub silicon does not provide any current or power FETs or any additional circuitry to actually charge the
device. Those components must be provided externally by the OEM.
FIGURE 8-1:
BATTERY CHARGING EXTERNAL POWER SUPPLY
INT
DC Power
SCL
Microchip
SOC
Hub
SDA
VBUS[n]
If the OEM provides an external supply capable of supplying current per the battery charging specification, the hub can
be configured to indicate the presence of such a supply from the device. This indication, via the PRT_CTLx pins, is on
a per port basis. For example, the OEM can configure two ports to support battery charging through high current power
FETs and leave the other two ports as standard USB ports.
The port control signals are assigned to programmable pins (PFx) and therefore the device must be programmed into
specific configurations to enable the signals. Refer to Section 3.3.4, PF[31:2] Configuration (CFG_STRAP[2:1]) for additional information.
For detailed information on utilizing the battery charging feature, refer to the application note “USB Battery Charging
with Microchip USB720x and USB725x Hubs”, which can be found on the Microchip USB7252C product page
www.microchip.com/USB7252C.
DS00003852A-page 38
2021 Microchip Technology Inc.
8.2
Port Power Control
Port power and over-current sense share the same pin (PRT_CTLx) for each port. These functions can be controlled
directly from the USB hub, or via the processor.
Note:
The PRT_CTLx function is assigned to programmable function pins (PFx) via configuration straps. Refer
to Section 3.3.4, PF[31:2] Configuration (CFG_STRAP[2:1]) for additional information.
Note:
The port power control for the USB 2.0 and USB 3.2 portions of a specific port can also be individually controlled via the PortSplit function. Refer to Section 8.4, PortSplit for additional information.
8.2.1
PORT POWER CONTROL USING USB POWER SWITCH
When operating in combined mode, the device will have one port power control and over-current sense pin for each
downstream port. When disabling port power, the driver will actively drive a '0'. To avoid unnecessary power dissipation,
the pull-up resistor will be disabled at that time. When port power is enabled, it will disable the output driver and enable
the pull-up resistor, making it an open drain output. If there is an over-current situation, the USB Power Switch will assert
the open drain OCS signal. The Schmidt trigger input will recognize that as a low. The open drain output does not interfere. The over-current sense filter handles the transient conditions such as low voltage while the device is powering up.
Note:
An external power switch is the required implementation for Type-C ports due to the requirement that VBUS
on Type-C ports must be discharged to 0V when no device is attached to the port.
FIGURE 8-2:
PORT POWER CONTROL WITH USB POWER SWITCH
Pull‐Up Enable
5V
50k
PRT_CTLx
OCS
USB Power
Switch
EN
PRTPWR
USB
Device
FILTER
OCS
2021 Microchip Technology Inc.
DS00003852A-page 39
8.2.2
PORT POWER CONTROL USING POLY FUSE
When using the device with a poly fuse, there is no need for an output power control. A single port power control and
over-current sense for each downstream port is still used from the Hub's perspective. When disabling port power, the
driver will actively drive a '0'. This will have no effect as the external diode will isolate pin from the load. When port power
is enabled, it will disable the output driver and enable the pull-up resistor. This means that the pull-up resistor is providing
3.3 volts to the anode of the diode. If there is an over-current situation, the poly fuse will open. This will cause the cathode of the diode to go to 0 volts. The anode of the diode will be at 0.7 volts, and the Schmidt trigger input will register
this as a low resulting in an over-current detection. The open drain output does not interfere.
Note:
Type-C ports may not utilize a Poly-Fuse port power implementation due to the requirements that VBUS
on Type-C ports must be discharged to 0V when no device is attached to the port.
FIGURE 8-3:
PORT POWER CONTROL USING A POLY FUSE
5V
Pull-Up Enable
Poly Fuse
50k
PRT_CTLx
USB
Device
PRTPWR
OCS
8.3
FILTER
CC Pin Orientation and Detection
The device provides CC1 and CC2 pins on all Type-C ports for cable plug orientation and detection of a USB Type-C
receptacle. The device also integrates a comparator and DAC circuit to implement Type-C attach and detach functions,
which supports up to eight programmable thresholds for attach detection between a UFP and DFP. When operating as
a UFP, the device supports detecting changes in the DFP’s advertised thresholds.
When operating as a DFP, the device implements current sources to advertise current charging capabilities on both CC
pins. By default, the CC pins advertise a 3A VBUS sourcing capability when operating in DFP mode. This may be reconfigured to 1.5A or Default USB (500mA for USB2 DFP or 900mA for a USB3 DFP) via OTP, SMBus, or SPI configuration.
When a UFP connection is established, the current driven across the CC pins creates a voltage across the UFP’s Rd
pull-down that can be detected by the integrated CC comparator. When connected to an active cable, an alternative
pull-down, Ra, appears on the CC pin.
When operating as a UFP, the device applies an Rd pull-down on both CC lines and waits for a DFP connection from
the assertion of VBUS. The CC comparator is used to determine the advertised current charger capabilities supported
by the DFP.
VCONN is a 3V-5V supply used to power circuitry in the USB Type-C plug that is required to implement Electronically
Marked Cables and other VCONN Powered accessories. By default the DFP always sources VCONN when connected
to an active cable. The USB7252C requires the use of two external VCONN FETs. The device provides the enables for
these FETs, and can detect an over-current event (OCS) by monitoring the output voltage of the FET via the CC pins.
DS00003852A-page 40
2021 Microchip Technology Inc.
If the voltage on the VCONN line is sensed as
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