USBF1600T-I/SNVAO

USBF1600 USB Firmware Memory Features • Read and Write Operations - 2.7-3.6V • x1/x2/x4 Serial Peripheral Interface (SPI) Protocol • Firmware memory companion for the USB491X family of USB controllers • Targeted for USB 2.0 High-Speed infotainment applications including: - Integration with head unit systems - First, second and third row USB media hubs - Power delivery • Memory Size: - 2 MByte (16 Mbit) • High Speed Clock Frequency - 104 MHz max • Superior Reliability - Endurance: 100,000 Cycles (min) - Greater than 100 years Data Retention • Low Power Consumption: - Active Read current: 15 mA (typical @ 104 MHz) - Standby Current: 15 µA (typical) • Fast Erase Time - Sector/Block Erase: 18 ms (typ), 25 ms (max) - Chip Erase: 35 ms (typ), 50 ms (max) • Page-Program - 256 Bytes per page in x1 or x4 mode • End-of-Write Detection - Software polling the BUSY bit in status register • Flexible Erase Capability - Uniform 4 KByte sectors - Four 8 KByte top and bottom parameter overlay blocks - One 32 KByte top and bottom overlay blocks - Uniform 64 KByte overlay blocks • Write-Suspend - Suspend Program or Erase operation to access another block/sector • Software Reset (RST) mode • Software Write Protection - Individual-Block Write Protection with permanent lock-down capability - 64 KByte blocks, two 32 KByte blocks, and eight 8 KByte parameter blocks - Read Protection on top and bottom 8 KByte parameter blocks  2018 Microchip Technology Inc. • • • • - Security ID - One-Time Programmable (OTP) 2 KByte, Secure ID - 64 bit unique, factory pre-programmed identifier - User-programmable area Temperature Range - Industrial: -40°C to +85°C - Industrial +: -40°C to +105°C Packages Available - 8-contact WDFN (6mm x 5mm) - 8-lead SOIC (3.90 mm) All devices are RoHS compliant Automotive AECQ-100 Grade 2 and Grade 3 qualified Product Description USBF1600, a USB Firmware memory chip, is a companion to the Microchip Automotive USB Smart Hub devices: USB491X. Factory pre-programming is available for custom firmware and configurations. The USBF1600 memory function assures proper functionality, providing for decreased development time and engineering resources, and overall faster time to market. The USB Firmware memory features a six-wire, 4-bit I/O interface that allows for low-power, high-performance operation in a low pin count package. USBF1600 is manufactured with proprietary, highperformance CMOS SuperFlash technology. The splitgate cell design and thick-oxide tunneling injector attain better reliability and manufacturing compared with alternate approaches. USBF1600 is offered in 8-contact WDFN (6 mm x 5 mm), and 8-lead SOIC (3.90 mm). See Figures 1-1 through 1-2 for pin assignments. DS20005929A-page 1 USBF1600 TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced. If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via E-mail at docerrors@microchip.com. We welcome your feedback. Most Current Data Sheet To obtain the most up-to-date version of this data sheet, please register at our Worldwide Website at: http://www.microchip.com You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page. The last character of the literature number is the version number, (e.g., DS30000000A is version A of document DS30000000). Errata An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current devices. As device/documentation issues become known to us, we will publish an errata sheet. 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DS20005929A-page 2  2018 Microchip Technology Inc. USBF1600 1.0 PIN DESCRIPTIONS FIGURE 1-1: PIN DESCRIPTION FOR 8-CONTACT WDFN CE# 1 SO/SIO1 2 8 VDD 7 HOLD/SIO3 FIGURE 1-2: PIN DESCRIPTION FOR 8LEAD SOIC CE# 1 SO/SIO1 2 3 6 SCK VSS 4 5 SI/SIO0 7 HOLD/SIO3 WP#/SIO2 3 6 SCK VSS 4 5 SI/SIO0 20005262 08-wson QA P1.0 TABLE 1-1: VDD Top View Top View WP#/SIO2 8 20005262 08-soic SA P1.0 PIN DESCRIPTION Symbol Pin Name Functions SCK Serial Clock To provide the timing of the serial interface. Commands, addresses, or input data are latched on the rising edge of the clock input, while output data is shifted out on the falling edge of the clock input. SIO[3:0] Serial Data Input/Output To transfer commands, addresses, or data serially into the device or data out of the device. Inputs are latched on the rising edge of the serial clock. Data is shifted out on the falling edge of the serial clock. The Enable Quad I/O (EQIO) command instruction configures these pins for Quad I/O mode. SI Serial Data Input for SPI mode To transfer commands, addresses or data serially into the device. Inputs are latched on the rising edge of the serial clock. SI is the default state after a Power-on Reset. SO Serial Data Output for SPI mode To transfer data serially out of the device. Data is shifted out on the falling edge of the serial clock. SO is the default state after a power on reset. CE# Chip Enable The device is enabled by a high to low transition on CE#. CE# must remain low for the duration of any command sequence; or in the case of Write operations, for the command/data input sequence. WP# Write Protect The WP# is used in conjunction with the WPEN and IOC bits in the Configuration register to prohibit write operations to the Block-Protection register. This pin only works in SPI, single-bit and dual-bit Read mode. HOLD# Hold Temporarily stops serial communication with the SPI Flash memory while the device is selected. This pin only works in SPI, single-bit and dual-bit Read mode and must be tied high when not in use. VDD Power Supply To provide power supply voltage. VSS Ground  2018 Microchip Technology Inc. DS20005929A-page 3 USBF1600 2.0 MEMORY ORGANIZATION The USBF1600 SQI memory array is organized in uniform, 4 KByte erasable sectors with the following erasable blocks: eight 8 KByte parameter, two 32 KByte overlay, and thirty 64 KByte overlay blocks. See Figure 2-1. FIGURE 2-1: MEMORY MAP Top of Memory Block 8 KByte 8 KByte 8 KByte 8 KByte 32 KByte ... 64 KByte 2 Sectors for 8 KByte blocks 8 Sectors for 32 KByte blocks 16 Sectors for 64 KByte blocks 64 KByte ... 4 KByte 4 KByte 4 KByte 4 KByte 64 KByte 32 KByte 8 KByte 8 KByte 8 KByte 8 KByte Bottom of Memory Block 20005262 F41.0 DS20005929A-page 4  2018 Microchip Technology Inc. USBF1600 3.0 DEVICE OPERATION USBF1600 supports both Serial Peripheral Interface (SPI) bus protocol and a 4-bit multiplexed SQI bus protocol. To provide backward compatibility to traditional SPI Serial Flash devices, the device’s initial state after a power-on reset is SPI mode which supports multi-I/O (x1/x2/x4) Read/Write commands. A command instruction configures the device to SQI mode. The dataflow in the SQI mode is similar to the SPI mode, except it uses four multiplexed I/O signals for command, address, and data sequence. master is in stand-by mode and no data is being transferred. The SCK signal is low for Mode 0 and SCK signal is high for Mode 3. For both modes, the Serial Data I/O (SIO[3:0]) is sampled at the rising edge of the SCK clock signal for input, and driven after the falling edge of the SCK clock signal for output. The traditional SPI protocol uses separate input (SI) and output (SO) data signals as shown in Figure 3-1. The SQI protocol uses four multiplexed signals, SIO[3:0], for both data in and data out, as shown in Figure 3-2. This means the SQI protocol quadruples the traditional bus transfer speed at the same clock frequency, without the need for more pins on the package. The device supports both Mode 0 (0,0) and Mode 3 (1,1) bus operations. The difference between the two modes is the state of the SCK signal when the bus FIGURE 3-1: SPI PROTOCOL CE# SCK MODE 3 MODE 3 MODE 0 MODE 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SI MSB SO HIGH IMPEDANCE DON'T CARE Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 MSB FIGURE 3-2: 20005262 F03.0 SERIAL QUAD I/O PROTOCOL CE# MODE 3 MODE 3 CLK MODE 0 SIO(3:0) MODE 0 C1 C0 A5 A4 A3 A2 A1 A0 H0 L0 H1 L1 H2 L2 H3 L3 MSB 20005262 F04.0  2018 Microchip Technology Inc. DS20005929A-page 5 USBF1600 4.0 INSTRUCTIONS Instructions are used to read, write (erase and program), and configure the USBF1600. The complete list of the instructions is provided in Table 4-1. TABLE 4-1: DEVICE OPERATION INSTRUCTIONS FOR USBF1600 Mode Command Cycle1 SPI SQI Address Cycle(s)2, 3 Dummy Cycle(s)3 Data Cycle(s)3 No Operation 00H X X 0 0 0 RSTEN Reset Enable 66H X X 0 0 0 RST4 Reset Memory 99H X X 0 0 0 0 0 0 0 0 0 0 0 1 to  X 0 1 1 to  X 0 0 2 0 0 1 to  0 1 1 to  3 0 1 to  Instruction Description Max Freq Configuration NOP EQIO Enable Quad I/O 38H X RSTQIO5 Reset Quad I/O FFH X RDSR Read Status Register 05H X WRSR Write Status Register 01H X RDCR Read Configuration Register 35H X Read Read Memory 03H HighSpeed Read Read Memory at Higher Speed 0BH SQOR6 SPI Quad Output Read SQIOR7 SPI Quad I/O Read SDOR SPI Dual Output Read SDIOR9 X X 104 MHz Read X 3 3 1 to  X 3 1 1 to  6BH X 3 1 1 to  EBH X 3 3 1 to  3BH X 3 1 1 to  SPI Dual I/O Read BBH X 3 1 1 to  SB Set Burst Length C0H X X 0 0 1 RBSQI SQI Read Burst with Wrap 0CH X 3 3 n to  RBSPI7 SPI Read Burst with Wrap ECH X 3 3 n to  JEDEC-ID JEDEC-ID Read 9FH X Quad J-ID Quad I/O J-ID Read AFH SFDP Serial Flash Discoverable Parameters 5AH X 8 X 40 MHz 104 MHz Identification X 0 0 3 to  0 1 3 to  3 1 1 to  104 MHz Write WREN Write Enable 06H X X 0 0 0 WRDI Write Disable 04H X X 0 0 0 10 SE Erase 4 KBytes of Memory Array 20H X X 3 0 0 BE11 Erase 64, 32 or 8 KBytes of Memory Array D8H X X 3 0 0 CE Erase Full Array C7H X X 0 0 0 X PP Page Program 02H X SPI Quad PP6 SQI Quad Page Program 32H X DS20005929A-page 6 3 0 1 to 256 3 0 1 to 256 104 MHz  2018 Microchip Technology Inc. USBF1600 TABLE 4-1: DEVICE OPERATION INSTRUCTIONS FOR USBF1600 Instruction Description Mode Command Cycle1 SPI SQI Address Cycle(s)2, 3 Dummy Cycle(s)3 Data Cycle(s)3 WRSU Suspends Program/Erase B0H X X 0 0 0 WRRE Resumes Program/Erase 30H X X 0 0 0 RBPR Read Block-Protection Register 72H X 0 0 1 to6 X 0 1 1 to6 WBPR Write Block-Protection Register 42H X X 0 0 1 to 6 LBPR Lock Down Block-Protection Register 8DH X X 0 0 0 nVWLDR non-Volatile Write LockDown Register E8H X X 0 0 1 to 6 ULBPR Global Block Protection Unlock 98H X X 0 0 0 RSID Read Security ID 88H X 2 1 1 to 2048 X 2 3 1 to 2048 Max Freq 104 MHz Protection 104 MHz PSID Program User Security ID area A5H X X 2 0 1 to 256 LSID Lockout Security ID Programming 85H X X 0 0 0 Power Saving DPD Deep Power-down Mode B9H X X 0 0 0 RDPD Release from Deep Powerdown and Read ID ABH X X 3 0 1 to  1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 104 MHz Command cycle is two clock periods in SQI mode and eight clock periods in SPI mode. Address bits above the most significant bit of each density can be VIL or VIH. Address, Dummy/Mode bits, and Data cycles are two clock periods in SQI and eight clock periods in SPI mode. RST command only executed if RSTEN command is executed first. Any intervening command will disable Reset. Device accepts eight-clock command in SPI mode, or two-clock command in SQI mode. Data cycles are two clock periods. IOC bit must be set to ‘1’ before issuing the command. Address, Dummy/Mode bits, and data cycles are two clock periods. IOC bit must be set to ‘1’ before issuing the command. Data cycles are four clock periods. Address, Dummy/Mode bits, and Data cycles are four clock periods. Sector Addresses: Use AMS - A12, remaining address are don’t care, but must be set to VIL or VIH. Blocks are 64 KByte, 32 KByte, or 8KByte, depending on location. Block Erase Address: AMS - A16 for 64 KByte; AMS - A15 for 32 KByte; AMS - A13 for 8 KByte. Remaining addresses are don’t care, but must be set to VIL or VIH.  2018 Microchip Technology Inc. DS20005929A-page 7 USBF1600 5.0 ELECTRICAL SPECIFICATIONS Absolute Maximum Stress Ratings (Applied conditions greater than those listed under “Absolute Maximum Stress Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these conditions or conditions greater than those defined in the operational sections of this data sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.) Temperature Under Bias. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55°C to +125°C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to +150°C D. C. Voltage on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to VDD+0.5V Transient Voltage (