VME64

Optimized for VME64 Slave Controller Description The VMEbus was first standardized in 1981 and is still in wide use. With the advances in integration technologies, custom integrated VME controllers open the door for smaller and cheaper systems. Inicore offers a wide range of different VME slave controllers. Each one optimized for a certain application. The difference lies mainly in the address and data bus width and the supported data modes. The VME slave controller shields all the complexity of the asynchronous VMEbus and provides an easy-to-use, synchronous parallel user side interface towards custom logic. A built-in interrupter handles all local interrupt requests and acknowledgments. INTCmod TIM ERmod VM E Slave Cont roller on-c hip bus Features • ANSI/VITA 1-1994 compliant • VME slave controller • Data modes: D8, D16, D32 • Address modes: A16, A24, D32 • Supports read, write, readmodify-write, D32-BLT and MBLT cycles • Configurable D8, D16 or D32 interrupter • Fully synchronous user side interface • User selectable wait-states User Decode GPIOmod UARTmod Bus Bridge VMEb u s VMEchip • Synchronous design Figure 1: Sample application The figure above illustrates a typical application where several peripheral functions together with the VME slave core as well as a bus bridge are integrated into one FPGA. Applications • Industrial control • Military • Aerospace • Telecom • Medical Supported modes • • • • Data modes: D8, D16, D32 Address modes: A16, A24, A32 Access modes: Read, write, read-modify-write, D32-BLT, MBLT Interrupter: D8, D16, D32, RORA, ROAK Sample Utilization and Performance Table Optimized for Actel Devices Family ProASIC PLUS Axcelerator SXA RTSX Device - (speed grade) APA600 AX500-3 SX72A-3 RTSX72S-1 MIL 225 225 223 354 355 334 s-mod Utilization c-mod Tiles 729 RAM Total 3% 7% 10% 10% Performance [MHz] 43 101 74 47 INICORE INC. 5600 Mowry School Road Suite 180 Newark, CA 94560 Tel: 510 445 1529 Fax: 510 656 0995 www.inicore.com Page 1/2 v v v v v v v v v v v v v v v v v v v v v v v m m m m m m m m m m m m m m m m m m m m m m m e_ e_ e_ e_ e_ e_ e_ e_ e_ e_ e_ e_ e_ e_ e_ e_ e_ e_ e_ e_ e_ e_ e_ a d dr _ in [ 3 1 :1 ] a d dr _ o ut [ 3 1 :1 a d dr _ in t _ d r v _ addr_ drv _ n a d d r _ d ir a m [ 5 :0 ] da t a _ in [ 3 1 :0 ] da t a _ o ut [ 3 1 :0 da t a _ in t _ d r v _ da t a _ drv _ n d a t a _ d ir ds0 _ n ds1 _ n lw o r d _ i n _ n lw o r d _ o u t _ n a s_ n w r it e _ n dt ac k _ n be rr_ n ia c k _ n ia c k _ i n _ n ia c k _ o u t _ n ir q _ n [ 6 :0 ] About Inicore ] n U s e r S id e B u s ] n use r _ use r _ use r _ use r _ use r _ use r _ use r _ use r _ a d d r [ 3 1 :2 ] a m [ 5 :0 ] acc_ req acc_ rdy da t a _ r d [ 3 1 :0 ] da t a _ w r [ 3 1 :0 ] rwn b y t e _ v a li d [ 3 : 0 ]  FPGA and ASIC Design  Easy-to-use IP Cores  System-on-Chip Solutions  Consulting Services  ASIC to FPGA Migration  Obsolete ASIC Replacements VM E B u s In t e rru p t s use r _ use r _ use r _ use r _ ia c k ir e q il e v [ 2 : 0 ] iv e c [ 3 1 :0 ] Decode in t _ u s e r _ a m [ 5 :0 ] in t _ u s e r _ a d d r [ 3 1 : 1 ] use r _ a c c e ss_ e bl u s e r _ a c c e s s _ e b l _ m b lt V M E S la v e r e se t _ n c lk _ sy s Figure 2: Symbol Interfaces Pin Name Global Signals clk reset_n VME Bus vme_addr_in[31:1] vme_addr_out[31:1] vme_addr_int_drv_n vme_addr_drv_n vme_addr_dir vme_am[5:0] vme_data_in[31:0] vme_data_out [31:0] vme_data_int_drv_n vme_data_drv_n vme_data_dir vme_ds0_n vme_ds1_n vme_lword_in_n vme_lword_out_n vme_as_n vme_write_n vme_dtack_n vme_berr_n vme_iack_n in out out out out in in out out out out in in in out in in out in in Address bus input Address bus output Internal i/o driver enable External address bus driver enable External address bus driver direction Address modifier code Data bus input Data bus output Internal i/o driver enable External data bus driver enable External data bus driver direction Data strobe 0 Data strobe 1 Long word indicator, in Long word indicator, out Address strobe Read write not indicator Data acknowledge Bus error Interrupt acknowledge user_byte_valid [3:0] User Decode int_user_addr[31:1] int_user_am[5:0] user_access_ebl user_access_ebl_ mblt Interrupt user_iack user_ireq user_ivec[31:0] user_ilevel[2:0] out in in in Interrupt acknowledge Interrupt request Interrupt vector Interrupt request level out out in in Address bus Address modifier code Valid user access Valid user access mblt mode out in in System clock Asynchronous system reset, active low vme_iack_out_n vme_irq_n[6:0] User Side Bus user_addr[31:2] user_am[5:0] user_acc_req user_acc_rdy user_data_rd[31:0] user_data_wr[31:0] user_rwn out out out in in out out Address bus Address modifier code Data access request Data access request ready Data read bus Data write bus Data read or write access Data byte valid out out Type Description Pin Name vme_iack_in_n Type in Description Interrupt acknowledge chain in Interrupt acknowledge chain out Interrupt request Inicore is an experienced system design house providing FPGA / ASIC and SoC design services. The company's expertise in architecture, intellectual property, m ethodology and tool handling provides a complete design environment that helps customers shorten their design cycle and speed time to market. Our offering covers feasibility study, concept analysis, architecture definition, code generation and implementation. W hen ready, we deliver you a FPGA or take your design to an ASIC provider, whatever is m ore suitable for your unique solution. Deliverables The core is available as Actel optimized netlist or as RTL v ersion. Actel Optimized Netlist: • Netlist for target FPGA, EDIF, Verilog and VHDL format • User Guide RTL Source Code: • VHDL or Verilog source code • Funtional verification testbench • Synthesis script • Timing constraints • User guide © 2003, Inicore Inc, All rights reserved. All brands or product names mentioned are the property of their respective holders. 51415.71.02 Sept/2003 INICORE INC. 5600 Mowry School Road Suite 180 Newark, CA 94560 Tel: 510 445 1529 Fax: 510 656 0995 www.inicore.com Page 2/2