VSC7420XJG-02

VSC7420-02, VSC7421-02, and VSC7422-02 Datasheet Family of Gigabit Ethernet Switches Microsemi Headquarters One Enterprise, Aliso Viejo, CA 92656 USA Within the USA: +1 (800) 713-4113 Outside the USA: +1 (949) 380-6100 Sales: +1 (949) 380-6136 Fax: +1 (949) 215-4996 Email: sales.support@microsemi.com www.microsemi.com ©2018 Microsemi, a wholly owned subsidiary of Microchip Technology Inc. All rights reserved. Microsemi and the Microsemi logo are registered trademarks of Microsemi Corporation. All other trademarks and service marks are the property of their respective owners. Microsemi makes no warranty, representation, or guarantee regarding the information contained herein or the suitability of its products and services for any particular purpose, nor does Microsemi assume any liability whatsoever arising out of the application or use of any product or circuit. The products sold hereunder and any other products sold by Microsemi have been subject to limited testing and should not be used in conjunction with mission-critical equipment or applications. Any performance specifications are believed to be reliable but are not verified, and Buyer must conduct and complete all performance and other testing of the products, alone and together with, or installed in, any end-products. Buyer shall not rely on any data and performance specifications or parameters provided by Microsemi. It is the Buyer’s responsibility to independently determine suitability of any products and to test and verify the same. The information provided by Microsemi hereunder is provided “as is, where is” and with all faults, and the entire risk associated with such information is entirely with the Buyer. Microsemi does not grant, explicitly or implicitly, to any party any patent rights, licenses, or any other IP rights, whether with regard to such information itself or anything described by such information. Information provided in this document is proprietary to Microsemi, and Microsemi reserves the right to make any changes to the information in this document or to any products and services at any time without notice. About Microsemi Microsemi, a wholly owned subsidiary of Microchip Technology Inc. (Nasdaq: MCHP), offers a comprehensive portfolio of semiconductor and system solutions for aerospace & defense, communications, data center and industrial markets. Products include high-performance and radiation-hardened analog mixed-signal integrated circuits, FPGAs, SoCs and ASICs; power management products; timing and synchronization devices and precise time solutions, setting the world's standard for time; voice processing devices; RF solutions; discrete components; enterprise storage and communication solutions, security technologies and scalable anti-tamper products; Ethernet solutions; Power-over-Ethernet ICs and midspans; as well as custom design capabilities and services. Learn more at www.microsemi.com. VMDS-10392. 4.3 1/19 Contents 1 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.1 1.2 1.3 1.4 1.5 Revision 4.3 Revision 4.2 Revision 4.1 Revision 4.0 Revision 2.0 ....................................................................... ....................................................................... ....................................................................... ....................................................................... ....................................................................... 1 1 1 1 1 2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2.1 2.2 2.3 Register Notation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Standard References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Terms and Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 3 Product Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3.1 3.2 3.3 3.4 General Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3.1.1 Layer-2 Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3.1.2 Multicast . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3.1.3 Quality of Service . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3.1.4 Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3.1.5 Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Related Products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Functional Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3.4.1 Frame Arrival . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3.4.2 Frame Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3.4.3 Policing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3.4.4 Layer-2 Forwarding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3.4.5 Shared Queue System and Egress Scheduler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3.4.6 Rewriter and Frame Departure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3.4.7 CPU Port Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.4.8 CPU System and Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 4 Functional Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4.1 4.2 Port Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4.1.1 Port Module Numbering and Macro Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4.1.2 MAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4.1.2.1 Resets ..................................................................................................................................12 4.1.2.2 Port Mode Configuration ......................................................................................................13 4.1.2.3 Half-Duplex Mode .................................................................................................................13 4.1.2.4 Frame and Type/Length Check ............................................................................................13 4.1.2.5 Flow Control .........................................................................................................................14 4.1.2.6 Frame Aging .........................................................................................................................14 4.1.3 PCS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.1.3.1 Auto-Negotiation ...................................................................................................................15 4.1.3.2 Link Surveillance ..................................................................................................................16 4.1.3.3 Signal Detect ........................................................................................................................16 4.1.3.4 Tx Loopback .........................................................................................................................16 4.1.3.5 Test Patterns ........................................................................................................................16 4.1.3.6 Low Power Idle .....................................................................................................................17 4.1.3.7 100BASE-FX ........................................................................................................................18 SERDES6G . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.2.1 SERDES6G Basic Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 VMDS-10392 VSC7420-02, VSC7421-02, and VSC7422-02 Datasheet Revision 4.3 iii 4.3 4.4 4.5 4.6 4.2.1.1 SERDES6G Parallel Interface Configuration .......................................................................19 4.2.1.2 SERDES6G PLL Frequency Configuration ..........................................................................19 4.2.1.3 SERDES6G Frequency Configuration .................................................................................19 4.2.2 SERDES6G Loopback Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.2.3 SERDES6G Deserializer Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.2.4 SERDES6G Serializer Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4.2.5 SERDES6G Input Buffer Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4.2.6 SERDES6G Output Buffer Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 4.2.7 SERDES6G Clock and Data Recovery (CDR) in 100BASE-FX . . . . . . . . . . . . . . . . . . . . . . . 23 4.2.8 SERDES6G Energy Efficient Ethernet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 4.2.9 SERDES6G Data Inversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 4.2.10 SERDES6G Signal Detection Enhancements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 4.2.11 SERDES6G High-Speed I/O Configuration Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Copper Transceivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 4.3.1 Register Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 4.3.1.1 Broadcast Write ....................................................................................................................25 4.3.1.2 Register Reset ......................................................................................................................25 4.3.2 Cat5 Twisted Pair Media Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 4.3.2.1 Voltage-Mode Line Driver .....................................................................................................25 4.3.2.2 Cat5 Autonegotiation and Parallel Detection ........................................................................26 4.3.2.3 1000BASE-T Forced Mode Support .....................................................................................26 4.3.2.4 Automatic Crossover and Polarity Detection ........................................................................26 4.3.2.5 Manual MDI/MDI-X Setting ...................................................................................................27 4.3.2.6 Link Speed Downshift ...........................................................................................................27 4.3.2.7 Energy Efficient Ethernet ......................................................................................................27 4.3.3 LED Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 4.3.4 Ethernet Inline Powered Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 4.3.5 IEEE 802.3af PoE Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 4.3.6 ActiPHY™ Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 4.3.6.1 Low Power State ..................................................................................................................30 4.3.6.2 Link Partner Wake-up State .................................................................................................31 4.3.6.3 Normal Operating State ........................................................................................................31 4.3.7 Testing Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 4.3.7.1 Core Voltage and I/O Voltage Monitor ..................................................................................31 4.3.7.2 Ethernet Packet Generator (EPG) ........................................................................................31 4.3.7.3 CRC Counters ......................................................................................................................31 4.3.7.4 Far-End Loopback ................................................................................................................31 4.3.7.5 Near-End Loopback .............................................................................................................32 4.3.7.6 Connector Loopback ............................................................................................................32 4.3.8 VeriPHY™ Cable Diagnostics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Statistics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Classifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 4.5.1 General Data Extraction Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 4.5.2 Frame Acceptance Filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 4.5.3 QoS and DSCP Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 4.5.4 VLAN Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 4.5.5 Link Aggregation Code Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 4.5.6 CPU Forwarding Determination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Analyzer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 4.6.1 MAC Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 4.6.1.1 Hardware-Based Learning ...................................................................................................50 4.6.1.2 Age Scan ..............................................................................................................................50 4.6.1.3 CPU Commands ..................................................................................................................50 4.6.1.4 Known Multicasts .................................................................................................................51 4.6.1.5 IPv4 Multicast Entries ...........................................................................................................52 4.6.1.6 IPv6 Multicast Entries ...........................................................................................................52 4.6.1.7 Port and VLAN Filter ............................................................................................................53 4.6.1.8 Shared VLAN Learning ........................................................................................................53 VMDS-10392 VSC7420-02, VSC7421-02, and VSC7422-02 Datasheet Revision 4.3 iv 4.7 4.8 4.9 4.10 4.11 4.12 4.6.1.9 Learn Limit ............................................................................................................................54 4.6.2 VLAN Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 4.6.3 Forwarding Engine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 4.6.3.1 DMAC Analysis .....................................................................................................................56 4.6.3.2 VLAN Analysis ......................................................................................................................58 4.6.3.3 Aggregation ..........................................................................................................................59 4.6.3.4 SMAC Analysis .....................................................................................................................60 4.6.3.5 Storm Policers ......................................................................................................................61 4.6.3.6 sFlow Sampling ....................................................................................................................62 4.6.3.7 Mirroring ...............................................................................................................................63 4.6.4 Analyzer Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Policers and Ingress Shapers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 4.7.1 Policers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 4.7.2 Ingress Shapers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Shared Queue System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 4.8.1 Buffer Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 4.8.2 Frame Reference Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 4.8.3 Resource Depletion Condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 4.8.4 Configuration Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 4.8.5 Watermark Programming and Consumption Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 4.8.6 Advanced Resource Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 4.8.7 Ingress Pause Request Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 4.8.8 Tail Dropping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 4.8.9 Test Utilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 4.8.10 Energy Efficient Ethernet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Scheduler and Shaper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 4.9.1 Egress Shapers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 4.9.2 Deficit Weighted Round Robin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 4.9.3 Shaping and DWRR Scheduling Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 Rewriter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 4.10.1 VLAN Editing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 4.10.2 DSCP Remarking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 4.10.3 FCS Updating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 4.10.4 CPU Extraction Header Insertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 CPU Port Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 4.11.1 Frame Extraction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 4.11.2 Frame Injection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 4.11.3 Network Processor Interface (NPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 Clocking and Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 5 VCore-Ie System and CPU Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 5.1 5.2 5.3 5.4 5.5 VCore-Ie Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 Clocking and Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 5.2.1 Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 Shared Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 5.3.1 Shared Bus Arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 5.3.2 SI Memory Region . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 5.3.3 Switch Core Registers Memory Region . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 5.3.4 VCore-Ie Registers Memory Region . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 VCore-Ie CPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 5.4.1 Starting the VCore-Ie CPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 5.4.1.1 Loading On-chip Memory .....................................................................................................94 5.4.1.2 Mapping On-chip Memory ....................................................................................................95 5.4.2 Accessing the VCore-Ie Shared Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 5.4.3 Paged Access to VCore-Ie Shared Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 5.4.4 Software Debug and Development . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 Manual Frame Injection and Extraction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 VMDS-10392 VSC7420-02, VSC7421-02, and VSC7422-02 Datasheet Revision 4.3 v 5.6 5.7 5.5.1 Manual Frame Extraction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 5.5.2 Manual Frame Injection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 5.5.3 Frame Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 External CPU Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 5.6.1 Register Access and Multimaster Systems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 5.6.2 Serial Interface in Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 5.6.3 MIIM Interface in Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 5.6.4 Access to the VCore-Ie Shared Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 5.6.4.1 Optimized Reading .............................................................................................................106 5.6.5 Mailbox and Semaphores . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 VCore-Ie System Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 5.7.1 Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 5.7.2 UART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 5.7.2.1 UART Interrupt ...................................................................................................................109 5.7.3 Two-Wire Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 5.7.3.1 Two-Wire Serial Interface Addressing ................................................................................ 111 5.7.3.2 Two-Wire Serial Interface Interrupt ..................................................................................... 112 5.7.4 MII Management Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 5.7.4.1 Clock Configuration ............................................................................................................ 113 5.7.4.2 MII Management PHY Access ............................................................................................ 113 5.7.4.3 PHY Scanning .................................................................................................................... 114 5.7.4.4 MII Management Interrupt .................................................................................................. 114 5.7.5 GPIO Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 5.7.5.1 Overlaid Functions on the GPIOs .......................................................................................115 5.7.5.2 GPIO Interrupt .................................................................................................................... 115 5.7.6 Serial GPIO Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 5.7.6.1 Output Modes ..................................................................................................................... 118 5.7.6.2 SIO Interrupt ....................................................................................................................... 119 5.7.6.3 Loss of Signal Detection ..................................................................................................... 119 5.7.7 FAN Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 5.7.8 Interrupt Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 6 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 6.1 6.2 6.3 6.4 Port Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 6.1.1 VSC7420-02 Port Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 6.1.2 VSC7421-02 Port Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 6.1.3 VSC7422-02 Port Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 Switch Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 6.2.1 Switch Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 Port Module Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 6.3.1 MAC Configuration Port Mode Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 6.3.2 SerDes Configuration Port Mode Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 6.3.3 Port Reset Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 6.3.4 Port Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 6.3.4.1 RMON Statistics Group (RFC 2819) ..................................................................................128 6.3.4.2 IEEE 802.3-2005 Annex 30A Counters ..............................................................................129 6.3.4.3 SNMP Interfaces Group (RFC 2863) .................................................................................130 6.3.4.4 SNMP Ethernet-Like Group (RFC 3536) ............................................................................131 Layer-2 Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 6.4.1 Basic Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 6.4.1.1 Forwarding .........................................................................................................................131 6.4.1.2 Address Learning ...............................................................................................................132 6.4.1.3 MAC Table Address Aging ..................................................................................................133 6.4.2 Standard VLAN Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 6.4.2.1 Forwarding .........................................................................................................................135 6.4.2.2 Ingress Filtering ..................................................................................................................135 6.4.2.3 GARP VLAN Registration Protocol (GVRP) .......................................................................135 VMDS-10392 VSC7420-02, VSC7421-02, and VSC7422-02 Datasheet Revision 4.3 vi 6.5 6.6 6.7 6.8 6.4.2.4 Shared VLAN Learning ......................................................................................................135 6.4.2.5 Untagging ...........................................................................................................................136 6.4.3 Provider Bridges and Q-in-Q Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 6.4.4 Private VLANs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 6.4.5 Asymmetric VLANs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 6.4.6 Spanning Tree Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 6.4.6.1 Rapid Spanning Tree Protocol ...........................................................................................146 6.4.6.2 Multiple Spanning Tree Protocol ........................................................................................149 6.4.7 IEEE 802.1X: Network Access Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 6.4.7.1 Port-Based Network Access Control ..................................................................................151 6.4.7.2 MAC-Based Authentication with Secure CPU-Based Learning ..........................................152 6.4.7.3 MAC-Based Authentication with No Learning ....................................................................153 6.4.8 Link Aggregation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 6.4.8.1 Link Aggregation Configuration ..........................................................................................154 6.4.8.2 Link Aggregation Control Protocol (LACP) .........................................................................155 6.4.9 Simple Network Management Protocol (SNMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 6.4.10 Mirroring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 6.4.10.1 Mirroring Configuration .......................................................................................................157 IGMP and MLD Snooping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 6.5.1 IGMP and MLD Snooping Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 6.5.2 IP Multicast Forwarding Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 Quality of Service (QoS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 6.6.1 Basic QoS Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 6.6.2 IPv4 and IPv6 DSCP Remarking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 6.6.2.1 DSCP Remarking Configuration .........................................................................................161 CPU Extraction and Injection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 6.7.1 Forwarding to CPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 6.7.2 Frame Extraction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 6.7.3 Frame Injection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 6.7.4 Frame Extraction and Injection Using An External CPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 Energy Efficient Ethernet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 7 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 7.1 7.2 7.3 Targets and Base Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 DEVCPU_ORG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 7.2.1 DEVCPU_ORG:ORG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 7.2.1.1 DEVCPU_ORG:ORG:ERR_ACCESS_DROP ...................................................................168 7.2.1.2 DEVCPU_ORG:ORG:ERR_TGT .......................................................................................168 7.2.1.3 DEVCPU_ORG:ORG:ERR_CNTS .....................................................................................169 7.2.1.4 DEVCPU_ORG:ORG:CFG_STATUS .................................................................................169 SYS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 7.3.1 SYS:SYSTEM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 7.3.1.1 SYS:SYSTEM:RESET_CFG ..............................................................................................171 7.3.1.2 SYS:SYSTEM:VLAN_ETYPE_CFG ...................................................................................172 7.3.1.3 SYS:SYSTEM:PORT_MODE .............................................................................................172 7.3.1.4 SYS:SYSTEM:FRONT_PORT_MODE ..............................................................................173 7.3.1.5 SYS:SYSTEM:SWITCH_PORT_MODE ............................................................................173 7.3.1.6 SYS:SYSTEM:FRM_AGING ..............................................................................................173 7.3.1.7 SYS:SYSTEM:STAT_CFG .................................................................................................174 7.3.1.8 SYS:SYSTEM:EEE_CFG ...................................................................................................174 7.3.1.9 SYS:SYSTEM:EEE_THRES ..............................................................................................175 7.3.1.10 SYS:SYSTEM:IGR_NO_SHARING ...................................................................................176 7.3.1.11 SYS:SYSTEM:EGR_NO_SHARING ..................................................................................176 7.3.1.12 SYS:SYSTEM:SW_STATUS ..............................................................................................176 7.3.1.13 SYS:SYSTEM:EQ_TRUNCATE .........................................................................................177 7.3.1.14 SYS:SYSTEM:EQ_PREFER_SRC ....................................................................................177 7.3.1.15 SYS:SYSTEM:EXT_CPU_CFG .........................................................................................177 VMDS-10392 VSC7420-02, VSC7421-02, and VSC7422-02 Datasheet Revision 4.3 vii 7.4 7.3.2 SYS:SCH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 7.3.2.1 SYS:SCH:LB_DWRR_FRM_ADJ ......................................................................................178 7.3.2.2 SYS:SCH:LB_DWRR_CFG ...............................................................................................179 7.3.2.3 SYS:SCH:SCH_DWRR_CFG ............................................................................................179 7.3.2.4 SYS:SCH:SCH_SHAPING_CTRL ......................................................................................180 7.3.2.5 SYS:SCH:SCH_LB_CTRL .................................................................................................181 7.3.2.6 SYS:SCH:SCH_CPU .........................................................................................................181 7.3.3 SYS:SCH_LB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 7.3.3.1 SYS:SCH_LB:LB_THRES ..................................................................................................183 7.3.3.2 SYS:SCH_LB:LB_RATE ....................................................................................................183 7.3.4 SYS:RES_CTRL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 7.3.4.1 SYS:RES_CTRL:RES_CFG ..............................................................................................184 7.3.4.2 SYS:RES_CTRL:RES_STAT .............................................................................................185 7.3.5 SYS:PAUSE_CFG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 7.3.5.1 SYS:PAUSE_CFG:PAUSE_CFG .......................................................................................186 7.3.5.2 SYS:PAUSE_CFG:PAUSE_TOT_CFG ..............................................................................186 7.3.5.3 SYS:PAUSE_CFG:ATOP ...................................................................................................187 7.3.5.4 SYS:PAUSE_CFG:ATOP_TOT_CFG ................................................................................187 7.3.5.5 SYS:PAUSE_CFG:EGR_DROP_FORCE ..........................................................................187 7.3.6 SYS:MMGT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 7.3.6.1 SYS:MMGT:MMGT .............................................................................................................188 7.3.6.2 SYS:MMGT:EQ_CTRL .......................................................................................................188 7.3.7 SYS:MISC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 7.3.7.1 SYS:MISC:REPEATER ......................................................................................................188 7.3.8 SYS:STAT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 7.3.8.1 SYS:STAT:CNT ...................................................................................................................189 7.3.9 SYS:POL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 7.3.9.1 SYS:POL:POL_PIR_CFG ..................................................................................................190 7.3.9.2 SYS:POL:POL_MODE_CFG .............................................................................................191 7.3.9.3 SYS:POL:POL_PIR_STATE ...............................................................................................191 7.3.10 SYS:POL_MISC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 7.3.10.1 SYS:POL_MISC:POL_FLOWC ..........................................................................................192 7.3.10.2 SYS:POL_MISC:POL_HYST .............................................................................................192 7.3.11 SYS:ISHP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 7.3.11.1 SYS:ISHP:ISHP_CFG ........................................................................................................193 7.3.11.2 SYS:ISHP:ISHP_MODE_CFG ...........................................................................................193 7.3.11.3 SYS:ISHP:ISHP_STATE .................................................................................................... 194 ANA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 7.4.1 ANA:ANA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 7.4.1.1 ANA:ANA:ADVLEARN .......................................................................................................195 7.4.1.2 ANA:ANA:VLANMASK .......................................................................................................196 7.4.1.3 ANA:ANA:ANAGEFIL .........................................................................................................196 7.4.1.4 ANA:ANA:ANEVENTS .......................................................................................................196 7.4.1.5 ANA:ANA:STORMLIMIT_BURST ......................................................................................198 7.4.1.6 ANA:ANA:STORMLIMIT_CFG ...........................................................................................198 7.4.1.7 ANA:ANA:ISOLATED_PORTS ...........................................................................................199 7.4.1.8 ANA:ANA:COMMUNITY_PORTS ......................................................................................200 7.4.1.9 ANA:ANA:AUTOAGE .........................................................................................................200 7.4.1.10 ANA:ANA:MACTOPTIONS ................................................................................................200 7.4.1.11 ANA:ANA:LEARNDISC ......................................................................................................201 7.4.1.12 ANA:ANA:AGENCTRL .......................................................................................................201 7.4.1.13 ANA:ANA:MIRRORPORTS ................................................................................................202 7.4.1.14 ANA:ANA:EMIRRORPORTS .............................................................................................203 7.4.1.15 ANA:ANA:FLOODING ........................................................................................................203 7.4.1.16 ANA:ANA:FLOODING_IPMC .............................................................................................203 7.4.1.17 ANA:ANA:SFLOW_CFG ....................................................................................................204 7.4.2 ANA:ANA_TABLES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204 7.4.2.1 ANA:ANA_TABLES:ANMOVED .........................................................................................204 VMDS-10392 VSC7420-02, VSC7421-02, and VSC7422-02 Datasheet Revision 4.3 viii 7.5 7.6 7.4.2.2 ANA:ANA_TABLES:MACHDATA ........................................................................................205 7.4.2.3 ANA:ANA_TABLES:MACLDATA ........................................................................................205 7.4.2.4 ANA:ANA_TABLES:MACACCESS ....................................................................................205 7.4.2.5 ANA:ANA_TABLES:MACTINDX ........................................................................................207 7.4.2.6 ANA:ANA_TABLES:VLANACCESS ...................................................................................208 7.4.2.7 ANA:ANA_TABLES:VLANTIDX .........................................................................................209 7.4.2.8 ANA:ANA_TABLES:PGID ..................................................................................................209 7.4.2.9 ANA:ANA_TABLES:ENTRYLIM .........................................................................................210 7.4.3 ANA:PORT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 7.4.3.1 ANA:PORT:VLAN_CFG .....................................................................................................211 7.4.3.2 ANA:PORT:DROP_CFG ....................................................................................................212 7.4.3.3 ANA:PORT:QOS_CFG .......................................................................................................213 7.4.3.4 ANA:PORT:QOS_PCP_DEI_MAP_CFG ............................................................................213 7.4.3.5 ANA:PORT:CPU_FWD_CFG .............................................................................................214 7.4.3.6 ANA:PORT:CPU_FWD_BPDU_CFG .................................................................................214 7.4.3.7 ANA:PORT:CPU_FWD_GARP_CFG .................................................................................215 7.4.3.8 ANA:PORT:CPU_FWD_CCM_CFG ...................................................................................215 7.4.3.9 ANA:PORT:PORT_CFG .....................................................................................................215 7.4.3.10 ANA:PORT:POL_CFG ........................................................................................................217 7.4.4 ANA:COMMON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218 7.4.4.1 ANA:COMMON:AGGR_CFG .............................................................................................218 7.4.4.2 ANA:COMMON:CPUQ_CFG .............................................................................................219 7.4.4.3 ANA:COMMON:CPUQ_8021_CFG ...................................................................................220 7.4.4.4 ANA:COMMON:DSCP_CFG ..............................................................................................220 7.4.4.5 ANA:COMMON:DSCP_REWR_CFG .................................................................................221 REW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221 7.5.1 REW:PORT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221 7.5.1.1 REW:PORT:PORT_VLAN_CFG .........................................................................................222 7.5.1.2 REW:PORT:TAG_CFG .......................................................................................................222 7.5.1.3 REW:PORT:PORT_CFG ....................................................................................................223 7.5.1.4 REW:PORT:DSCP_CFG ....................................................................................................223 7.5.1.5 REW:PORT:PCP_DEI_QOS_MAP_CFG ...........................................................................224 7.5.2 REW:COMMON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224 7.5.2.1 REW:COMMON:DSCP_REMAP_CFG ..............................................................................224 DEVCPU_GCB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 7.6.1 DEVCPU_GCB:CHIP_REGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 7.6.1.1 DEVCPU_GCB:CHIP_REGS:GENERAL_PURPOSE .......................................................226 7.6.1.2 DEVCPU_GCB:CHIP_REGS:SI ........................................................................................226 7.6.1.3 DEVCPU_GCB:CHIP_REGS:CHIP_ID ..............................................................................227 7.6.2 DEVCPU_GCB:SW_REGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227 7.6.2.1 DEVCPU_GCB:SW_REGS:SEMA_INTR_ENA .................................................................227 7.6.2.2 DEVCPU_GCB:SW_REGS:SEMA_INTR_ENA_CLR .......................................................228 7.6.2.3 DEVCPU_GCB:SW_REGS:SEMA_INTR_ENA_SET ........................................................228 7.6.2.4 DEVCPU_GCB:SW_REGS:SEMA .....................................................................................229 7.6.2.5 DEVCPU_GCB:SW_REGS:SEMA_FREE......................................................................... 229 7.6.2.6 DEVCPU_GCB:SW_REGS:SW_INTR ..............................................................................229 7.6.2.7 DEVCPU_GCB:SW_REGS:MAILBOX ...............................................................................230 7.6.2.8 DEVCPU_GCB:SW_REGS:MAILBOX_CLR .....................................................................230 7.6.2.9 DEVCPU_GCB:SW_REGS:MAILBOX_SET ......................................................................230 7.6.3 DEVCPU_GCB:VCORE_ACCESS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231 7.6.3.1 DEVCPU_GCB:VCORE_ACCESS:VA_CTRL ...................................................................231 7.6.3.2 DEVCPU_GCB:VCORE_ACCESS:VA_ADDR ..................................................................232 7.6.3.3 DEVCPU_GCB:VCORE_ACCESS:VA_DATA ....................................................................233 7.6.3.4 DEVCPU_GCB:VCORE_ACCESS:VA_DATA_INCR .........................................................234 7.6.3.5 DEVCPU_GCB:VCORE_ACCESS:VA_DATA_INERT .......................................................234 7.6.4 DEVCPU_GCB:GPIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234 7.6.4.1 DEVCPU_GCB:GPIO:GPIO_OUT_SET ............................................................................235 7.6.4.2 DEVCPU_GCB:GPIO:GPIO_OUT_CLR ............................................................................235 VMDS-10392 VSC7420-02, VSC7421-02, and VSC7422-02 Datasheet Revision 4.3 ix 7.7 7.6.4.3 DEVCPU_GCB:GPIO:GPIO_OUT .....................................................................................235 7.6.4.4 DEVCPU_GCB:GPIO:GPIO_IN .........................................................................................236 7.6.4.5 DEVCPU_GCB:GPIO:GPIO_OE .......................................................................................236 7.6.4.6 DEVCPU_GCB:GPIO:GPIO_INTR ....................................................................................236 7.6.4.7 DEVCPU_GCB:GPIO:GPIO_INTR_ENA ...........................................................................237 7.6.4.8 DEVCPU_GCB:GPIO:GPIO_INTR_IDENT .......................................................................237 7.6.4.9 DEVCPU_GCB:GPIO:GPIO_ALT ......................................................................................237 7.6.5 DEVCPU_GCB:DEVCPU_RST_REGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237 7.6.5.1 DEVCPU_GCB:DEVCPU_RST_REGS:SOFT_CHIP_RST ...............................................238 7.6.5.2 DEVCPU_GCB:DEVCPU_RST_REGS:SOFT_DEVCPU_RST ........................................238 7.6.6 DEVCPU_GCB:MIIM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239 7.6.6.1 DEVCPU_GCB:MIIM:MII_STATUS ....................................................................................239 7.6.6.2 DEVCPU_GCB:MIIM:MII_CMD .........................................................................................240 7.6.6.3 DEVCPU_GCB:MIIM:MII_DATA .........................................................................................241 7.6.6.4 DEVCPU_GCB:MIIM:MII_CFG ..........................................................................................241 7.6.6.5 DEVCPU_GCB:MIIM:MII_SCAN_0 ....................................................................................242 7.6.6.6 DEVCPU_GCB:MIIM:MII_SCAN_1 ....................................................................................242 7.6.6.7 DEVCPU_GCB:MIIM:MII_SCAN_LAST_RSLTS ...............................................................242 7.6.6.8 DEVCPU_GCB:MIIM:MII_SCAN_LAST_RSLTS_VLD ......................................................243 7.6.7 DEVCPU_GCB:MIIM_READ_SCAN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243 7.6.7.1 DEVCPU_GCB:MIIM_READ_SCAN:MII_SCAN_RSLTS_STICKY ...................................243 7.6.8 DEVCPU_GCB:RAM_STAT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244 7.6.8.1 DEVCPU_GCB:RAM_STAT:RAM_INTEGRITY_ERR_STICKY .........................................244 7.6.9 DEVCPU_GCB:MISC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244 7.6.9.1 DEVCPU_GCB:MISC:MISC_CFG .....................................................................................245 7.6.9.2 DEVCPU_GCB:MISC:MISC_STAT ....................................................................................245 7.6.9.3 DEVCPU_GCB:MISC:PHY_SPEED_1000_STAT .............................................................246 7.6.9.4 DEVCPU_GCB:MISC:PHY_SPEED_100_STAT ...............................................................246 7.6.9.5 DEVCPU_GCB:MISC:PHY_SPEED_10_STAT .................................................................246 7.6.9.6 DEVCPU_GCB:MISC:DUPLEXC_PORT_STAT ................................................................246 7.6.10 DEVCPU_GCB:SIO_CTRL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247 7.6.10.1 DEVCPU_GCB:SIO_CTRL:SIO_INPUT_DATA .................................................................247 7.6.10.2 DEVCPU_GCB:SIO_CTRL:SIO_INT_POL ........................................................................248 7.6.10.3 DEVCPU_GCB:SIO_CTRL:SIO_PORT_INT_ENA ............................................................248 7.6.10.4 DEVCPU_GCB:SIO_CTRL:SIO_PORT_CONFIG .............................................................248 7.6.10.5 DEVCPU_GCB:SIO_CTRL:SIO_PORT_ENABLE .............................................................249 7.6.10.6 DEVCPU_GCB:SIO_CTRL:SIO_CONFIG .........................................................................249 7.6.10.7 DEVCPU_GCB:SIO_CTRL:SIO_CLOCK ..........................................................................251 7.6.10.8 DEVCPU_GCB:SIO_CTRL:SIO_INT_REG .......................................................................251 7.6.11 DEVCPU_GCB:FAN_CFG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252 7.6.11.1 DEVCPU_GCB:FAN_CFG:FAN_CFG ...............................................................................252 7.6.12 DEVCPU_GCB:FAN_STAT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253 7.6.12.1 DEVCPU_GCB:FAN_STAT:FAN_CNT ...............................................................................253 7.6.13 DEVCPU_GCB:MEMITGR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253 7.6.13.1 DEVCPU_GCB:MEMITGR:MEMITGR_CTRL ...................................................................254 7.6.13.2 DEVCPU_GCB:MEMITGR:MEMITGR_STAT ....................................................................255 7.6.13.3 DEVCPU_GCB:MEMITGR:MEMITGR_INFO ....................................................................255 7.6.13.4 DEVCPU_GCB:MEMITGR:MEMITGR_IDX .......................................................................256 DEVCPU_QS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257 7.7.1 DEVCPU_QS:XTR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257 7.7.1.1 DEVCPU_QS:XTR:XTR_FRM_PRUNING ........................................................................257 7.7.1.2 DEVCPU_QS:XTR:XTR_GRP_CFG .................................................................................258 7.7.1.3 DEVCPU_QS:XTR:XTR_MAP ...........................................................................................258 7.7.1.4 DEVCPU_QS:XTR:XTR_RD ..............................................................................................259 7.7.1.5 DEVCPU_QS:XTR:XTR_QU_FLUSH ................................................................................259 7.7.1.6 DEVCPU_QS:XTR:XTR_DATA_PRESENT .......................................................................260 7.7.2 DEVCPU_QS:INJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260 7.7.2.1 DEVCPU_QS:INJ:INJ_GRP_CFG .....................................................................................261 VMDS-10392 VSC7420-02, VSC7421-02, and VSC7422-02 Datasheet Revision 4.3 x 7.8 7.9 7.10 7.7.2.2 DEVCPU_QS:INJ:INJ_WR ................................................................................................261 7.7.2.3 DEVCPU_QS:INJ:INJ_CTRL .............................................................................................261 7.7.2.4 DEVCPU_QS:INJ:INJ_STATUS .........................................................................................262 7.7.2.5 DEVCPU_QS:INJ:INJ_ERR ...............................................................................................263 HSIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264 7.8.1 HSIO:PLL5G_STATUS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264 7.8.1.1 HSIO:PLL5G_STATUS:PLL5G_STATUS0 .........................................................................265 7.8.2 HSIO:RCOMP_STATUS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265 7.8.2.1 HSIO:RCOMP_STATUS:RCOMP_STATUS ......................................................................265 7.8.3 HSIO:SERDES6G_ANA_CFG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266 7.8.3.1 HSIO:SERDES6G_ANA_CFG:SERDES6G_DES_CFG ...................................................266 7.8.3.2 HSIO:SERDES6G_ANA_CFG:SERDES6G_IB_CFG .......................................................268 7.8.3.3 HSIO:SERDES6G_ANA_CFG:SERDES6G_IB_CFG1 .....................................................268 7.8.3.4 HSIO:SERDES6G_ANA_CFG:SERDES6G_OB_CFG ......................................................269 7.8.3.5 HSIO:SERDES6G_ANA_CFG:SERDES6G_OB_CFG1 ....................................................270 7.8.3.6 HSIO:SERDES6G_ANA_CFG:SERDES6G_SER_CFG ...................................................270 7.8.3.7 HSIO:SERDES6G_ANA_CFG:SERDES6G_COMMON_CFG ..........................................270 7.8.3.8 HSIO:SERDES6G_ANA_CFG:SERDES6G_PLL_CFG ....................................................271 7.8.4 HSIO:SERDES6G_DIG_CFG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272 7.8.4.1 HSIO:SERDES6G_DIG_CFG:SERDES6G_DIG_CFG .....................................................272 7.8.4.2 HSIO:SERDES6G_DIG_CFG:SERDES6G_MISC_CFG ...................................................272 7.8.5 HSIO:MCB_SERDES6G_CFG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273 7.8.5.1 HSIO:MCB_SERDES6G_CFG:MCB_SERDES6G_ADDR_CFG ......................................273 DEV_GMII . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274 7.9.1 DEV_GMII:PORT_MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274 7.9.1.1 DEV_GMII:PORT_MODE:CLOCK_CFG ...........................................................................274 7.9.1.2 DEV_GMII:PORT_MODE:PORT_MISC .............................................................................275 7.9.2 DEV_GMII:MAC_CFG_STATUS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275 7.9.2.1 DEV_GMII:MAC_CFG_STATUS:MAC_ENA_CFG ............................................................276 7.9.2.2 DEV_GMII:MAC_CFG_STATUS:MAC_MODE_CFG .........................................................276 7.9.2.3 DEV_GMII:MAC_CFG_STATUS:MAC_MAXLEN_CFG .....................................................277 7.9.2.4 DEV_GMII:MAC_CFG_STATUS:MAC_TAGS_CFG ..........................................................277 7.9.2.5 DEV_GMII:MAC_CFG_STATUS:MAC_ADV_CHK_CFG ..................................................278 7.9.2.6 DEV_GMII:MAC_CFG_STATUS:MAC_IFG_CFG .............................................................279 7.9.2.7 DEV_GMII:MAC_CFG_STATUS:MAC_HDX_CFG ............................................................279 7.9.2.8 DEV_GMII:MAC_CFG_STATUS:MAC_FC_CFG ...............................................................280 7.9.2.9 DEV_GMII:MAC_CFG_STATUS:MAC_FC_MAC_LOW_CFG ..........................................281 7.9.2.10 DEV_GMII:MAC_CFG_STATUS:MAC_FC_MAC_HIGH_CFG ..........................................281 7.9.2.11 DEV_GMII:MAC_CFG_STATUS:MAC_STICKY ................................................................282 DEV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283 7.10.1 DEV:PORT_MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284 7.10.1.1 DEV:PORT_MODE:CLOCK_CFG .....................................................................................284 7.10.1.2 DEV:PORT_MODE:PORT_MISC ......................................................................................285 7.10.2 DEV:MAC_CFG_STATUS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285 7.10.2.1 DEV:MAC_CFG_STATUS:MAC_ENA_CFG ......................................................................286 7.10.2.2 DEV:MAC_CFG_STATUS:MAC_MODE_CFG ..................................................................286 7.10.2.3 DEV:MAC_CFG_STATUS:MAC_MAXLEN_CFG ..............................................................286 7.10.2.4 DEV:MAC_CFG_STATUS:MAC_TAGS_CFG ....................................................................287 7.10.2.5 DEV:MAC_CFG_STATUS:MAC_ADV_CHK_CFG ............................................................288 7.10.2.6 DEV:MAC_CFG_STATUS:MAC_IFG_CFG .......................................................................288 7.10.2.7 DEV:MAC_CFG_STATUS:MAC_HDX_CFG ......................................................................289 7.10.2.8 DEV:MAC_CFG_STATUS:MAC_FC_CFG ........................................................................290 7.10.2.9 DEV:MAC_CFG_STATUS:MAC_FC_MAC_LOW_CFG ....................................................291 7.10.2.10DEV:MAC_CFG_STATUS:MAC_FC_MAC_HIGH_CFG ...................................................291 7.10.2.11 DEV:MAC_CFG_STATUS:MAC_STICKY ..........................................................................291 7.10.3 DEV:PCS1G_CFG_STATUS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293 7.10.3.1 DEV:PCS1G_CFG_STATUS:PCS1G_CFG .......................................................................294 7.10.3.2 DEV:PCS1G_CFG_STATUS:PCS1G_MODE_CFG ..........................................................294 VMDS-10392 VSC7420-02, VSC7421-02, and VSC7422-02 Datasheet Revision 4.3 xi 7.11 7.10.3.3 DEV:PCS1G_CFG_STATUS:PCS1G_SD_CFG ................................................................295 7.10.3.4 DEV:PCS1G_CFG_STATUS:PCS1G_ANEG_CFG ...........................................................295 7.10.3.5 DEV:PCS1G_CFG_STATUS:PCS1G_ANEG_NP_CFG ....................................................296 7.10.3.6 DEV:PCS1G_CFG_STATUS:PCS1G_LB_CFG ................................................................296 7.10.3.7 DEV:PCS1G_CFG_STATUS:PCS1G_ANEG_STATUS .....................................................297 7.10.3.8 DEV:PCS1G_CFG_STATUS:PCS1G_ANEG_NP_STATUS ..............................................297 7.10.3.9 DEV:PCS1G_CFG_STATUS:PCS1G_LINK_STATUS .......................................................298 7.10.3.10DEV:PCS1G_CFG_STATUS:PCS1G_LINK_DOWN_CNT ................................................298 7.10.3.11 DEV:PCS1G_CFG_STATUS:PCS1G_STICKY ..................................................................299 7.10.3.12DEV:PCS1G_CFG_STATUS:PCS1G_LPI_CFG ...............................................................299 7.10.3.13DEV:PCS1G_CFG_STATUS:PCS1G_LPI_WAKE_ERROR_CNT ....................................300 7.10.3.14DEV:PCS1G_CFG_STATUS:PCS1G_LPI_STATUS .........................................................300 7.10.4 DEV:PCS1G_TSTPAT_CFG_STATUS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301 7.10.4.1 DEV:PCS1G_TSTPAT_CFG_STATUS:PCS1G_TSTPAT_MODE_CFG ............................301 7.10.4.2 DEV:PCS1G_TSTPAT_CFG_STATUS:PCS1G_TSTPAT_STATUS ..................................302 7.10.5 DEV:PCS_FX100_CONFIGURATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302 7.10.5.1 DEV:PCS_FX100_CONFIGURATION:PCS_FX100_CFG .................................................303 7.10.6 DEV:PCS_FX100_STATUS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 304 7.10.6.1 DEV:PCS_FX100_STATUS:PCS_FX100_STATUS ...........................................................304 ICPU_CFG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305 7.11.1 ICPU_CFG:CPU_SYSTEM_CTRL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306 7.11.1.1 ICPU_CFG:CPU_SYSTEM_CTRL:GPR ............................................................................306 7.11.1.2 ICPU_CFG:CPU_SYSTEM_CTRL:RESET .......................................................................306 7.11.1.3 ICPU_CFG:CPU_SYSTEM_CTRL:GENERAL_STAT ........................................................307 7.11.2 ICPU_CFG:SPI_MST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308 7.11.2.1 ICPU_CFG:SPI_MST:SPI_MST_CFG ...............................................................................308 7.11.2.2 ICPU_CFG:SPI_MST:SW_MODE ......................................................................................308 7.11.3 ICPU_CFG:MPU8051 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 309 7.11.3.1 ICPU_CFG:MPU8051:MPU8051_STAT .............................................................................310 7.11.3.2 ICPU_CFG:MPU8051:MPU8051_MMAP ..........................................................................310 7.11.3.3 ICPU_CFG:MPU8051:MEMACC_CTRL ............................................................................ 311 7.11.3.4 ICPU_CFG:MPU8051:MEMACC .......................................................................................312 7.11.3.5 ICPU_CFG:MPU8051:MEMACC_SBA ..............................................................................312 7.11.4 ICPU_CFG:INTR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313 7.11.4.1 ICPU_CFG:INTR:INTR ......................................................................................................314 7.11.4.2 ICPU_CFG:INTR:INTR_ENA .............................................................................................317 7.11.4.3 ICPU_CFG:INTR:INTR_ENA_CLR ....................................................................................318 7.11.4.4 ICPU_CFG:INTR:INTR_ENA_SET ....................................................................................319 7.11.4.5 ICPU_CFG:INTR:INTR_RAW ............................................................................................320 7.11.4.6 ICPU_CFG:INTR:ICPU_IRQ0_ENA ...................................................................................321 7.11.4.7 ICPU_CFG:INTR:ICPU_IRQ0_IDENT ...............................................................................322 7.11.4.8 ICPU_CFG:INTR:ICPU_IRQ1_ENA ...................................................................................323 7.11.4.9 ICPU_CFG:INTR:ICPU_IRQ1_IDENT ...............................................................................323 7.11.4.10 ICPU_CFG:INTR:EXT_IRQ0_ENA ....................................................................................325 7.11.4.11 ICPU_CFG:INTR:EXT_IRQ0_IDENT .................................................................................325 7.11.4.12 ICPU_CFG:INTR:DEV_IDENT ...........................................................................................326 7.11.4.13 ICPU_CFG:INTR:EXT_IRQ0_INTR_CFG .........................................................................326 7.11.4.14 ICPU_CFG:INTR:SW0_INTR_CFG ...................................................................................328 7.11.4.15 ICPU_CFG:INTR:SW1_INTR_CFG ...................................................................................328 7.11.4.16 ICPU_CFG:INTR:MIIM1_INTR_CFG .................................................................................329 7.11.4.17 ICPU_CFG:INTR:MIIM0_INTR_CFG .................................................................................329 7.11.4.18 ICPU_CFG:INTR:UART_INTR_CFG .................................................................................330 7.11.4.19 ICPU_CFG:INTR:TIMER0_INTR_CFG ..............................................................................331 7.11.4.20 ICPU_CFG:INTR:TIMER1_INTR_CFG ..............................................................................331 7.11.4.21 ICPU_CFG:INTR:TIMER2_INTR_CFG ..............................................................................331 7.11.4.22 ICPU_CFG:INTR:TWI_INTR_CFG ....................................................................................332 7.11.4.23 ICPU_CFG:INTR:GPIO_INTR_CFG ..................................................................................332 7.11.4.24 ICPU_CFG:INTR:SGPIO_INTR_CFG ...............................................................................333 VMDS-10392 VSC7420-02, VSC7421-02, and VSC7422-02 Datasheet Revision 4.3 xii 7.12 7.13 7.11.4.25 ICPU_CFG:INTR:DEV_ALL_INTR_CFG ...........................................................................334 7.11.4.26 ICPU_CFG:INTR:BLK_ANA_INTR_CFG ...........................................................................334 7.11.4.27 ICPU_CFG:INTR:XTR_RDY0_INTR_CFG ........................................................................335 7.11.4.28 ICPU_CFG:INTR:XTR_RDY1_INTR_CFG ........................................................................336 7.11.4.29 ICPU_CFG:INTR:INJ_RDY0_INTR_CFG ..........................................................................336 7.11.4.30 ICPU_CFG:INTR:INJ_RDY1_INTR_CFG ..........................................................................337 7.11.4.31 ICPU_CFG:INTR:INTEGRITY_INTR_CFG ........................................................................338 7.11.4.32 ICPU_CFG:INTR:DEV_ENA ..............................................................................................338 7.11.5 ICPU_CFG:TIMERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 339 7.11.5.1 ICPU_CFG:TIMERS:WDT .................................................................................................339 7.11.5.2 ICPU_CFG:TIMERS:TIMER_TICK_DIV ............................................................................340 7.11.5.3 ICPU_CFG:TIMERS:TIMER_VALUE .................................................................................340 7.11.5.4 ICPU_CFG:TIMERS:TIMER_RELOAD_VALUE ................................................................341 7.11.5.5 ICPU_CFG:TIMERS:TIMER_CTRL ...................................................................................341 7.11.6 ICPU_CFG:TWI_DELAY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 342 7.11.6.1 ICPU_CFG:TWI_DELAY:TWI_CONFIG .............................................................................342 UART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 343 7.12.1 UART:UART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 343 7.12.1.1 UART:UART:RBR_THR ......................................................................................................344 7.12.1.2 UART:UART:IER .................................................................................................................345 7.12.1.3 UART:UART:IIR_FCR .........................................................................................................346 7.12.1.4 UART:UART:LCR ...............................................................................................................348 7.12.1.5 UART:UART:MCR ..............................................................................................................349 7.12.1.6 UART:UART:LSR ................................................................................................................350 7.12.1.7 UART:UART:MSR ...............................................................................................................353 7.12.1.8 UART:UART:SCR ...............................................................................................................354 7.12.1.9 UART:UART:USR ...............................................................................................................354 TWI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 355 7.13.1 TWI:TWI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 355 7.13.1.1 TWI:TWI:CFG .....................................................................................................................356 7.13.1.2 TWI:TWI:TAR .....................................................................................................................358 7.13.1.3 TWI:TWI:SAR .....................................................................................................................358 7.13.1.4 TWI:TWI:DATA_CMD .........................................................................................................359 7.13.1.5 TWI:TWI:SS_SCL_HCNT ..................................................................................................360 7.13.1.6 TWI:TWI:SS_SCL_LCNT ...................................................................................................361 7.13.1.7 TWI:TWI:FS_SCL_HCNT ...................................................................................................361 7.13.1.8 TWI:TWI:FS_SCL_LCNT ...................................................................................................362 7.13.1.9 TWI:TWI:INTR_STAT .........................................................................................................362 7.13.1.10TWI:TWI:INTR_MASK ........................................................................................................362 7.13.1.11 TWI:TWI:RAW_INTR_STAT ...............................................................................................363 7.13.1.12TWI:TWI:RX_TL .................................................................................................................367 7.13.1.13TWI:TWI:TX_TL .................................................................................................................368 7.13.1.14TWI:TWI:CLR_INTR ...........................................................................................................368 7.13.1.15TWI:TWI:CLR_RX_UNDER ...............................................................................................368 7.13.1.16TWI:TWI:CLR_RX_OVER ..................................................................................................369 7.13.1.17TWI:TWI:CLR_TX_OVER ..................................................................................................369 7.13.1.18TWI:TWI:CLR_RD_REQ ....................................................................................................369 7.13.1.19TWI:TWI:CLR_TX_ABRT ...................................................................................................369 7.13.1.20TWI:TWI:CLR_RX_DONE ..................................................................................................370 7.13.1.21TWI:TWI:CLR_ACTIVITY ...................................................................................................370 7.13.1.22TWI:TWI:CLR_STOP_DET ................................................................................................370 7.13.1.23TWI:TWI:CLR_START_DET ..............................................................................................371 7.13.1.24TWI:TWI:CLR_GEN_CALL ................................................................................................371 7.13.1.25TWI:TWI:CTRL ...................................................................................................................371 7.13.1.26TWI:TWI:STAT ....................................................................................................................372 7.13.1.27TWI:TWI:TXFLR .................................................................................................................373 7.13.1.28TWI:TWI:RXFLR ................................................................................................................374 7.13.1.29TWI:TWI:TX_ABRT_SOURCE ...........................................................................................374 VMDS-10392 VSC7420-02, VSC7421-02, and VSC7422-02 Datasheet Revision 4.3 xiii 7.14 7.13.1.30TWI:TWI:SDA_SETUP .......................................................................................................376 7.13.1.31TWI:TWI:ACK_GEN_CALL ................................................................................................376 7.13.1.32TWI:TWI:ENABLE_STATUS ..............................................................................................377 PHY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 378 7.14.1 PHY:PHY_STD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 378 7.14.1.1 PHY:PHY_STD:PHY_CTRL ...............................................................................................380 7.14.1.2 PHY:PHY_STD:PHY_STAT ................................................................................................381 7.14.1.3 PHY:PHY_STD:PHY_IDF1 ................................................................................................382 7.14.1.4 PHY:PHY_STD:PHY_IDF2 ................................................................................................382 7.14.1.5 PHY:PHY_STD:PHY_AUTONEG_ADVERTISMENT ........................................................382 7.14.1.6 PHY:PHY_STD:PHY_AUTONEG_LP_ABILITY .................................................................383 7.14.1.7 PHY:PHY_STD:PHY_AUTONEG_EXP .............................................................................384 7.14.1.8 PHY:PHY_STD:PHY_AUTONEG_NEXTPAGE_TX ...........................................................384 7.14.1.9 PHY:PHY_STD:PHY_AUTONEG_LP_NEXTPAGE_RX ....................................................385 7.14.1.10PHY:PHY_STD:PHY_CTRL_1000BT ................................................................................385 7.14.1.11 PHY:PHY_STD:PHY_STAT_1000BT .................................................................................386 7.14.1.12PHY:PHY_STD:MMD_ACCESS_CFG ...............................................................................387 7.14.1.13PHY:PHY_STD:MMD_ADDR_DATA ..................................................................................387 7.14.1.14PHY:PHY_STD:PHY_STAT_1000BT_EXT1 ......................................................................388 7.14.1.15PHY:PHY_STD:PHY_STAT_100BTX ................................................................................388 7.14.1.16PHY:PHY_STD:PHY_STAT_1000BT_EXT2 ......................................................................389 7.14.1.17PHY:PHY_STD:PHY_BYPASS_CTRL ...............................................................................390 7.14.1.18PHY:PHY_STD:PHY_ERROR_CNT1 ................................................................................391 7.14.1.19PHY:PHY_STD:PHY_ERROR_CNT2 ................................................................................392 7.14.1.20PHY:PHY_STD:PHY_ERROR_CNT3 ................................................................................392 7.14.1.21PHY:PHY_STD:PHY_CTRL_STAT_EXT ...........................................................................392 7.14.1.22PHY:PHY_STD:PHY_CTRL_EXT1 ....................................................................................395 7.14.1.23PHY:PHY_STD:PHY_CTRL_EXT2 ....................................................................................395 7.14.1.24PHY:PHY_STD:PHY_INT_MASK ......................................................................................397 7.14.1.25PHY:PHY_STD:PHY_INT_STAT ........................................................................................398 7.14.1.26PHY:PHY_STD:PHY_AUX_CTRL_STAT ...........................................................................400 7.14.1.27PHY:PHY_STD:PHY_MEMORY_PAGE_ACCESS ............................................................403 7.14.2 PHY:PHY_EXT1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 403 7.14.2.1 PHY:PHY_EXT1:PHY_CRC_GOOD_CNT ........................................................................404 7.14.2.2 PHY:PHY_EXT1:PHY_EXT_MODE_CTRL .......................................................................404 7.14.2.3 PHY:PHY_EXT1:PHY_CTRL_EXT3 ..................................................................................404 7.14.2.4 PHY:PHY_EXT1:PHY_CTRL_EXT4 ..................................................................................406 7.14.2.5 PHY:PHY_EXT1:PHY_1000BT_EPG1 ..............................................................................407 7.14.2.6 PHY:PHY_EXT1:PHY_1000BT_EPG2 ..............................................................................409 7.14.3 PHY:PHY_EXT2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 409 7.14.3.1 PHY:PHY_EXT2:PHY_PMD_TX_CTRL .............................................................................410 7.14.3.2 PHY:PHY_EXT2:PHY_EEE_CTRL ....................................................................................410 7.14.4 PHY:PHY_GP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 411 7.14.4.1 PHY:PHY_GP:PHY_COMA_MODE_CTRL .......................................................................412 7.14.4.2 PHY:PHY_GP:PHY_GLOBAL_INT_STAT .........................................................................412 7.14.5 PHY:PHY_EEE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 413 7.14.5.1 PHY:PHY_EEE:PHY_PCS_STATUS1 ...............................................................................414 7.14.5.2 PHY:PHY_EEE:PHY_EEE_CAPABILITIES .......................................................................414 7.14.5.3 PHY:PHY_EEE:PHY_EEE_WAKE_ERR_CNT ..................................................................415 7.14.5.4 PHY:PHY_EEE:PHY_EEE_ADVERTISEMENT .................................................................415 7.14.5.5 PHY:PHY_EEE:PHY_EEE_LP_ADVERTISEMENT ..........................................................416 8 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 417 8.1 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 417 8.1.1 Internal Pull-Up or Pull-Down Resistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 417 8.1.2 Reference Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 417 8.1.3 SGMII DC Definitions and Test Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 417 8.1.4 Enhanced SerDes Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 418 VMDS-10392 VSC7420-02, VSC7421-02, and VSC7422-02 Datasheet Revision 4.3 xiv 8.2 8.3 8.4 8.5 8.1.5 MIIM, GPIO, SI, JTAG, and Miscellaneous Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 420 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 421 8.2.1 Reference Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 421 8.2.2 Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 422 8.2.3 Enhanced SerDes Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 422 8.2.3.1 Enhanced SerDes Outputs .................................................................................................423 8.2.3.2 Enhanced SerDes Driver Jitter Characteristics ..................................................................424 8.2.3.3 Enhanced SerDes Inputs ...................................................................................................424 8.2.3.4 Enhanced SerDes Receiver Jitter Tolerance ......................................................................425 8.2.4 MII Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 426 8.2.5 Serial CPU Interface (SI) Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 427 8.2.6 Serial CPU Interface (SI) for Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 428 8.2.7 JTAG Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 429 8.2.8 Serial Inputs/Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 431 8.2.9 Two-Wire Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 432 Current and Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 433 8.3.1 Current Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 434 8.3.2 Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 434 8.3.3 Power Supply Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 435 Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 435 Stress Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 436 9 Pin Descriptions for VSC7420XJQ-02 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 437 9.1 9.2 9.3 9.4 Pin Diagram for VSC7420XJQ-02 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 437 Pins by Function for VSC7420XJQ-02 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 438 9.2.1 Analog Bias Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 438 9.2.2 Clock Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 439 9.2.3 General-Purpose Inputs and Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 439 9.2.4 JTAG Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 440 9.2.5 MII Management Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 440 9.2.6 Miscellaneous Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 440 9.2.7 Power Supplies and Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 441 9.2.8 Serial CPU Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 441 9.2.9 Enhanced SerDes Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 442 9.2.10 Twisted Pair Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 442 Pins by Number for VSC7420XJQ-02 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 445 Pins by Name for VSC7420XJQ-02 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 448 10 Pin Descriptions for VSC7420XJG-02 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 451 10.1 10.2 10.3 Pin Identifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 451 Pin Diagram for VSC7420XJG-02 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 452 Pins by Function for VSC7420XJG-02 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 454 11 Pin Descriptions for VSC7421XJQ-02 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 486 11.1 11.2 Pin Diagram for VSC7421XJQ-02 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 486 Pins by Function for VSC7421XJQ-02 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 487 11.2.1 Analog Bias Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 487 11.2.2 Clock Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 488 11.2.3 General-Purpose Inputs and Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 488 11.2.4 JTAG Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 489 11.2.5 MII Management Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 489 11.2.6 Miscellaneous Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 489 11.2.7 Power Supplies and Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 490 11.2.8 Serial CPU Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 490 11.2.9 Enhanced SerDes Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 491 11.2.10 Twisted Pair Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 491 VMDS-10392 VSC7420-02, VSC7421-02, and VSC7422-02 Datasheet Revision 4.3 xv 11.3 11.4 Pins by Number for VSC7421XJQ-02 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 494 Pins by Name for VSC7421XJQ-02 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 497 12 Pin Descriptions for VSC7421XJG-02 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500 12.1 12.2 12.3 Pin Identifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500 Pin Diagram for VSC7421XJG-02 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 501 Pins by Function for VSC7421XJG-02 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 503 13 Pin Descriptions for VSC7422XJQ-02 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 537 13.1 13.2 13.3 13.4 Pin Diagram for VSC7422XJQ-02 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 537 Pins by Function for VSC7422XJQ-02 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 538 13.2.1 Analog Bias Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 538 13.2.2 Clock Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 539 13.2.3 General-Purpose Inputs and Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 539 13.2.4 JTAG Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 540 13.2.5 MII Management Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 540 13.2.6 Miscellaneous Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 540 13.2.7 Power Supplies and Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 541 13.2.8 Serial CPU Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 541 13.2.9 Enhanced SerDes Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 542 13.2.10 Twisted Pair Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 542 Pins by Number for VSC7422XJQ-02 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 545 Pins by Name for VSC7422XJQ-02 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 548 14 Pin Descriptions for VSC7422XJG-02 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 551 14.1 14.2 14.3 Pin Identifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 551 Pin Diagram for VSC7422XJG-02 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 552 Pins by Function for VSC7422XJG-02 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 553 15 Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 585 15.1 15.2 15.3 Package Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 585 Thermal Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 587 Moisture Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 588 16 Design Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 589 16.1 16.2 16.3 16.4 Power Supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Supply Decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reference Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16.3.1 Single-Ended RefClk Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16.4.1 General Recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16.4.2 SGMII Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16.4.3 Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16.4.4 Enhanced SerDes Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16.4.5 Two-Wire Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 589 589 589 589 590 590 591 591 591 592 17 Design Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 593 17.1 17.2 17.3 17.4 17.5 17.6 17.7 10BASE-T mode unable to re-establish link . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Software script for link performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10BASE-T signal amplitude . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Clause 45 register 7.60 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Clause 45 register 3.22 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Clause 45 register 3.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Clause 45 register address post-increment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VMDS-10392 VSC7420-02, VSC7421-02, and VSC7422-02 Datasheet Revision 4.3 593 593 593 593 593 593 594 xvi 18 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 595 VMDS-10392 VSC7420-02, VSC7421-02, and VSC7422-02 Datasheet Revision 4.3 xvii Figures Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 Figure 8 Figure 9 Figure 10 Figure 11 Figure 12 Figure 13 Figure 14 Figure 15 Figure 16 Figure 17 Figure 18 Figure 19 Figure 20 Figure 21 Figure 22 Figure 23 Figure 24 Figure 25 Figure 26 Figure 27 Figure 28 Figure 29 Figure 30 Figure 31 Figure 32 Figure 33 Figure 34 Figure 35 Figure 36 Figure 37 Figure 38 Figure 39 Figure 40 Figure 41 Figure 42 Figure 43 Figure 44 Figure 45 Figure 46 Figure 47 Figure 48 Figure 49 Figure 50 Figure 51 Figure 52 Figure 53 Figure 54 VSC7422-02 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Frame Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Egress Scheduler and Shaper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 SERDES Loopback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Register Space Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Cat5 Media Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Energy Efficient Ethernet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Inline Powered Ethernet Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 ActiPHY State Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Far-End Loopback Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Near-End Loopback Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Connector Loopback Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Counter Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 VLAN Acceptance Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 QoS Classification Flow Chart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 DSCP Classification Flow Chart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Basic VLAN Classification Flow Chart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 MAC Table Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Analysis Steps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Frame Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Watermark Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Low Power Idle Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Egress Scheduler and Shapers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 CPU Injection And Extraction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 VCore-Ie System Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 Shared Bus Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 SI Read Timing in Normal Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 SI Read Timing in Fast Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 VCore-Ie Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 Write Sequence for SI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 Read Sequence for SI_Clk Slow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 Read Sequence for SI_Clk Pause . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 Read Sequence for One-Byte Padding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 MIIM Slave Write Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 MIIM Slave Read Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 UART Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 Two-Wire Serial Interface Timing for 7-bit Address Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 MII Management Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 SIO Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 SIO Timing with SGPIOs Disabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 SIO Output Order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 Link Activity Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 Logical Equivalent for Interrupt Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 Logical Equivalent for Interrupt Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 MAN Access Switch Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 ISP Example for Private VLAN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 DMZ Example for Private VLAN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 Asymmetric VLANs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 Spanning Tree Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 Multiple Spanning Tree Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 Link Aggregation Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 Port Mirroring Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 CPU Extraction and Injection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 SGMII DC Input Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 418 VMDS-10392 VSC7420-02, VSC7421-02, and VSC7422-02 Datasheet Revision 4.3 xviii Figure 55 Figure 56 Figure 57 Figure 58 Figure 59 Figure 60 Figure 61 Figure 62 Figure 63 Figure 64 Figure 65 Figure 66 Figure 67 Figure 68 Figure 69 Figure 70 Figure 71 Figure 72 Figure 73 Figure 74 Figure 75 Figure 76 Figure 77 Figure 78 Figure 79 Figure 80 Figure 81 Figure 82 SGMII DC Transmit Test Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SGMII DC Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SGMII DC Driver Output Impedance Test Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . nReset Signal Timing Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . QSGMII Transient Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MIIM Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SI Timing Diagram for Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SI Input Data Timing Diagram for Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SI Output Data Timing Diagram for Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SI_DO Disable Test Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . JTAG Interface Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Test Circuit for TDO Disable Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Serial I/O Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Two-Wire Serial Read Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Two-Wire Serial Write Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Diagram for VSC7420XJQ-02 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VSC7420XJG-02 Pin Diagram, Top Left . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VSC7420XJG-02 Pin Diagram, Top Right . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Diagram for VSC7421XJQ-02 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VSC7421XJG-02 Pin Diagram, Top Left . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VSC7421XJG-02 Pin Diagram, Top Right . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Diagram for VSC7422XJQ-02 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VSC7422XJG-02 Pin Diagram, Top Left . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VSC7422XJG-02 Pin Diagram, Top Right . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Package Drawing TQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Package Drawing BGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5 V CMOS Single-Ended RefClk Input Resistor Network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3 V CMOS Single-Ended RefClk Input Resistor Network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VMDS-10392 VSC7420-02, VSC7421-02, and VSC7422-02 Datasheet Revision 4.3 418 418 418 422 422 426 427 428 428 429 430 431 431 432 432 437 452 453 486 501 502 537 552 553 586 587 590 590 xix Tables Table 1 Table 2 Table 3 Table 4 Table 5 Table 6 Table 7 Table 8 Table 9 Table 10 Table 11 Table 12 Table 13 Table 14 Table 15 Table 16 Table 17 Table 18 Table 19 Table 20 Table 21 Table 22 Table 23 Table 24 Table 25 Table 26 Table 27 Table 28 Table 29 Table 30 Table 31 Table 32 Table 33 Table 34 Table 35 Table 36 Table 37 Table 38 Table 39 Table 40 Table 41 Table 42 Table 43 Table 44 Table 45 Table 46 Table 47 Table 48 Table 49 Table 50 Table 51 Table 52 Table 53 Table 54 Referenced Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Terms and Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Port Mapping from Switch Core Port Module to Interface Macros . . . . . . . . . . . . . . . . . . . . . . . . . 11 MAC Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Frame Aging Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 PCS Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Test Pattern Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Low Power Idle Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 100BASE-FX Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 SERDES6G Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 PLL Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 SERDES6 Frequency Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 SERDES6G Loop Bandwidth . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 De-Emphasis and Amplitude Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Supported MDI Pair Combinations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Counter Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Rx Counters in the Statistics Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 FIFO Drop Counters in the Statistics Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Tx Counters in the Statistics Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 General Data Extraction Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Frame Acceptance Filtering Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 QoS and DSCP Classification Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 VLAN Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Aggregation Code Generation Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 CPU Forwarding Determination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Frame Type Definitions for CPU Forwarding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 MAC Table Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 MAC Table Entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 MAC Table Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 IPv4 Multicast Destination Mask . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 IPv6 Multicast Destination Mask . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 VID/Port Filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 FID Definition Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Learn Limit Definition Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 VLAN Table Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Fields in the VLAN Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 VLAN Table Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 DMAC Analysis Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Forwarding Decisions Based on Flood Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 VLAN Analysis Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Analyzer Aggregation Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 SMAC Learning Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Storm Policer Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Storm Policers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 sFlow Sampling Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Mirroring Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Analyzer Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Policer Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Ingress Shaper Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Reservation Watermarks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Sharing Watermarks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Watermark Configuration Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Resource Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Energy Efficient Ethernet Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 VMDS-10392 VSC7420-02, VSC7421-02, and VSC7422-02 Datasheet Revision 4.3 xx Table 55 Table 56 Table 57 Table 58 Table 59 Table 60 Table 61 Table 62 Table 63 Table 64 Table 65 Table 66 Table 67 Table 68 Table 69 Table 70 Table 71 Table 72 Table 73 Table 74 Table 75 Table 76 Table 77 Table 78 Table 79 Table 80 Table 81 Table 82 Table 83 Table 84 Table 85 Table 86 Table 87 Table 88 Table 89 Table 90 Table 91 Table 92 Table 93 Table 94 Table 95 Table 96 Table 97 Table 98 Table 99 Table 100 Table 101 Table 102 Table 103 Table 104 Table 105 Table 106 Table 107 Table 108 Table 109 Table 110 Table 111 Table 112 Table 113 Scheduler and Egress Shaper Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Example of Mixing DWRR and Shaping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 Example of Strict and Work-Conserving Shaping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 VLAN Editing Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 Tagging Combinations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 DSCP Remarking Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 FCS Updating Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 CPU Extraction Header Insertion Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 Frame Extraction Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 CPU Extraction Header . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 Frame Injection Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 CPU Injection Header . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 Network Processor Interface Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 Clocking and Reset Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 VCore-Ie Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 Clocking and Reset Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 Shared Bus Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 SI Controller Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 Serial Interface Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 Special Function Registers (SFR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 VCore-Ie CPU Startup Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 Shared Bus Access (SBA) Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 Paged Access to VCore-Ie Shared Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 8051 Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 Manual Frame Extraction Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 Extraction Data Special Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 Frame Extraction Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 Manual Frame Injection Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 Frame Injection Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 SI Slave Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 SI Slave Mode Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 MIIM Slave Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 MIIM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 VCore-Ie Shared Bus Access Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 Mailbox and Semaphore Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 Timer Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 UART Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 UART Interface Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 Two-Wire Serial Interface Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 Two-Wire Serial Interface Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 Reserved Two-Wire Serial Interface Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 MIIM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 MIIM Management Controller Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 GPIO Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 GPIO Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 SIO Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 SIO Controller Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 Blink Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 Fan Controller Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 Fan Controller Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 Interrupt Controller Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 VSC7420-02: Mapping from Port Modules to Physical Interface Pins . . . . . . . . . . . . . . . . . . . . . 124 VSC7421-02 in Switch Mode 0: Mapping from Port Modules to Physical Interface Pins . . . . . . . 124 VSC7422-02: Mapping from Port Modules to Physical Interface Pins . . . . . . . . . . . . . . . . . . . . . 125 VSC7421-02 in Switch Mode 1: Mapping from Port Modules to Physical Interface Pins . . . . . . . 125 MAC Configuration of Port Modes for Ports with Internal PHYs . . . . . . . . . . . . . . . . . . . . . . . . . . 126 MAC Configuration of Port Modes for Ports with SerDes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 SERDES6G Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 Mapping of RMON Counters to Port Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 VMDS-10392 VSC7420-02, VSC7421-02, and VSC7422-02 Datasheet Revision 4.3 xxi Table 114 Table 115 Table 116 Table 117 Table 118 Table 119 Table 120 Table 121 Table 122 Table 123 Table 124 Table 125 Table 126 Table 127 Table 128 Table 129 Table 130 Table 131 Table 132 Table 133 Table 134 Table 135 Table 136 Table 137 Table 138 Table 139 Table 140 Table 141 Table 142 Table 143 Table 144 Table 145 Table 146 Table 147 Table 148 Table 149 Table 150 Table 151 Table 152 Table 153 Table 154 Table 155 Table 156 Table 157 Table 158 Table 159 Table 160 Table 161 Table 162 Table 163 Table 164 Table 165 Table 166 Table 167 Table 168 Table 169 Table 170 Table 171 Table 172 Mandatory Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 Optional Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 Recommended MAC Control Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 Pause MAC Control Recommended Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 Mapping of SNMP Interfaces Group Counters to Port Counters . . . . . . . . . . . . . . . . . . . . . . . . . 130 Mapping of SNMP Ethernet-Like Group Counters to Port Counters . . . . . . . . . . . . . . . . . . . . . . . 131 Port Group Identifier Table Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 Port Module Registers for Standard VLAN Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 Analyzer Registers for Standard VLAN Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 Rewriter Registers for Standard VLAN Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 Port Module Configurations for Provider Bridge VLAN Operation . . . . . . . . . . . . . . . . . . . . . . . . 137 System Configurations for Provider Bridge VLAN Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 Analyzer Configurations for Provider Bridge VLAN Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 Private VLAN Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 Analyzer Configurations for RSTP Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 RSTP Port State Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 RSTP Port State Configuration for Port p . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 Analyzer Configurations for MSTP Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 MSTP Port State Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 MSTP Port State Configuration for Port p and VLAN v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 Configurations for Port-Based Network Access Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 Configurations for MAC-Based Network Access Control with Secure CPU-Based Learning . . . . 152 Configurations for MAC-Based Network Access Control with No Learning . . . . . . . . . . . . . . . . . 153 Link Aggregation Group Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 Configuration Registers for LACP Frame Redirection to the CPU . . . . . . . . . . . . . . . . . . . . . . . . 156 System Registers for SNMP Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 Analyzer Registers for SNMP Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 Configuration Registers for Mirroring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 Configuration Registers for IGMP and MLD Frame Redirection to CPU . . . . . . . . . . . . . . . . . . . 158 IP Multicast Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 Basic QoS Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 Configuration Registers for DSCP Remarking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 Configurations for Redirecting or Copying Frames to the CPU . . . . . . . . . . . . . . . . . . . . . . . . . . 162 Configuration Registers When Using An External CPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 Configuration Registers When Using Energy Efficient Ethernet . . . . . . . . . . . . . . . . . . . . . . . . . . 165 List of Targets and Base Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 Register Groups in DEVCPU_ORG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 Registers in ORG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 Fields in ERR_ACCESS_DROP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 Fields in ERR_TGT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 Fields in ERR_CNTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 Fields in CFG_STATUS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 Register Groups in SYS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 Registers in SYSTEM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 Fields in RESET_CFG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 Fields in VLAN_ETYPE_CFG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 Fields in PORT_MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 Fields in FRONT_PORT_MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 Fields in SWITCH_PORT_MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 Fields in FRM_AGING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 Fields in STAT_CFG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 Fields in EEE_CFG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 Fields in EEE_THRES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 Fields in IGR_NO_SHARING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 Fields in EGR_NO_SHARING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 Fields in SW_STATUS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 Fields in EQ_TRUNCATE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 Fields in EQ_PREFER_SRC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 Fields in EXT_CPU_CFG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 VMDS-10392 VSC7420-02, VSC7421-02, and VSC7422-02 Datasheet Revision 4.3 xxii Table 173 Table 174 Table 175 Table 176 Table 177 Table 178 Table 179 Table 180 Table 181 Table 182 Table 183 Table 184 Table 185 Table 186 Table 187 Table 188 Table 189 Table 190 Table 191 Table 192 Table 193 Table 194 Table 195 Table 196 Table 197 Table 198 Table 199 Table 200 Table 201 Table 202 Table 203 Table 204 Table 205 Table 206 Table 207 Table 208 Table 209 Table 210 Table 211 Table 212 Table 213 Table 214 Table 215 Table 216 Table 217 Table 218 Table 219 Table 220 Table 221 Table 222 Table 223 Table 224 Table 225 Table 226 Table 227 Table 228 Table 229 Table 230 Table 231 Registers in SCH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Fields in LB_DWRR_FRM_ADJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Fields in LB_DWRR_CFG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Fields in SCH_DWRR_CFG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Fields in SCH_SHAPING_CTRL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Fields in SCH_LB_CTRL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Fields in SCH_CPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Registers in SCH_LB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Fields in LB_THRES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Fields in LB_RATE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Registers in RES_CTRL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Fields in RES_CFG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Fields in RES_STAT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Registers in PAUSE_CFG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Fields in PAUSE_CFG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Fields in PAUSE_TOT_CFG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Fields in ATOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Fields in ATOP_TOT_CFG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Fields in EGR_DROP_FORCE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Registers in MMGT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Fields in MMGT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Fields in EQ_CTRL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Registers in MISC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Fields in REPEATER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Registers in STAT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Fields in CNT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Registers in POL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Fields in POL_PIR_CFG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Fields in POL_MODE_CFG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Fields in POL_PIR_STATE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Registers in POL_MISC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Fields in POL_FLOWC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Fields in POL_HYST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Registers in ISHP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Fields in ISHP_CFG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Fields in ISHP_MODE_CFG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Fields in ISHP_STATE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Register Groups in ANA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Registers in ANA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Fields in ADVLEARN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Fields in VLANMASK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Fields in ANAGEFIL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Fields in ANEVENTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Fields in STORMLIMIT_BURST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Fields in STORMLIMIT_CFG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Fields in ISOLATED_PORTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Fields in COMMUNITY_PORTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Fields in AUTOAGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Fields in MACTOPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Fields in LEARNDISC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Fields in AGENCTRL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Fields in MIRRORPORTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Fields in EMIRRORPORTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Fields in FLOODING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Fields in FLOODING_IPMC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Fields in SFLOW_CFG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Registers in ANA_TABLES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Fields in ANMOVED . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Fields in MACHDATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VMDS-10392 VSC7420-02, VSC7421-02, and VSC7422-02 Datasheet Revision 4.3 178 179 179 179 180 181 182 182 183 183 184 185 185 185 186 186 187 187 187 188 188 188 188 189 189 190 190 190 191 191 192 192 192 193 193 193 194 194 195 195 196 196 197 198 199 199 200 200 200 201 201 202 203 203 203 204 204 205 205 xxiii Table 232 Table 233 Table 234 Table 235 Table 236 Table 237 Table 238 Table 239 Table 240 Table 241 Table 242 Table 243 Table 244 Table 245 Table 246 Table 247 Table 248 Table 249 Table 250 Table 251 Table 252 Table 253 Table 254 Table 255 Table 256 Table 257 Table 258 Table 259 Table 260 Table 261 Table 262 Table 263 Table 264 Table 265 Table 266 Table 267 Table 268 Table 269 Table 270 Table 271 Table 272 Table 273 Table 274 Table 275 Table 276 Table 277 Table 278 Table 279 Table 280 Table 281 Table 282 Table 283 Table 284 Table 285 Table 286 Table 287 Table 288 Table 289 Table 290 Fields in MACLDATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 Fields in MACACCESS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 Fields in MACTINDX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208 Fields in VLANACCESS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208 Fields in VLANTIDX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209 Fields in PGID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 Fields in ENTRYLIM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 Registers in PORT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 Fields in VLAN_CFG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 Fields in DROP_CFG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212 Fields in QOS_CFG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213 Fields in QOS_PCP_DEI_MAP_CFG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214 Fields in CPU_FWD_CFG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214 Fields in CPU_FWD_BPDU_CFG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 Fields in CPU_FWD_GARP_CFG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 Fields in CPU_FWD_CCM_CFG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 Fields in PORT_CFG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 Fields in POL_CFG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217 Registers in COMMON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218 Fields in AGGR_CFG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219 Fields in CPUQ_CFG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219 Fields in CPUQ_8021_CFG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 Fields in DSCP_CFG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 Fields in DSCP_REWR_CFG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221 Register Groups in REW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221 Registers in PORT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221 Fields in PORT_VLAN_CFG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222 Fields in TAG_CFG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222 Fields in PORT_CFG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223 Fields in DSCP_CFG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224 Fields in PCP_DEI_QOS_MAP_CFG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224 Registers in COMMON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224 Fields in DSCP_REMAP_CFG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 Register Groups in DEVCPU_GCB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 Registers in CHIP_REGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 Fields in GENERAL_PURPOSE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226 Fields in SI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226 Fields in CHIP_ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227 Registers in SW_REGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227 Fields in SEMA_INTR_ENA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228 Fields in SEMA_INTR_ENA_CLR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228 Fields in SEMA_INTR_ENA_SET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228 Fields in SEMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229 Fields in SEMA_FREE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229 Fields in SW_INTR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230 Fields in MAILBOX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230 Fields in MAILBOX_CLR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230 Fields in MAILBOX_SET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231 Registers in VCORE_ACCESS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231 Fields in VA_CTRL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231 Fields in VA_ADDR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232 Fields in VA_DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233 Fields in VA_DATA_INCR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234 Fields in VA_DATA_INERT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234 Registers in GPIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234 Fields in GPIO_OUT_SET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235 Fields in GPIO_OUT_CLR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235 Fields in GPIO_OUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236 Fields in GPIO_IN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236 VMDS-10392 VSC7420-02, VSC7421-02, and VSC7422-02 Datasheet Revision 4.3 xxiv Table 291 Table 292 Table 293 Table 294 Table 295 Table 296 Table 297 Table 298 Table 299 Table 300 Table 301 Table 302 Table 303 Table 304 Table 305 Table 306 Table 307 Table 308 Table 309 Table 310 Table 311 Table 312 Table 313 Table 314 Table 315 Table 316 Table 317 Table 318 Table 319 Table 320 Table 321 Table 322 Table 323 Table 324 Table 325 Table 326 Table 327 Table 328 Table 329 Table 330 Table 331 Table 332 Table 333 Table 334 Table 335 Table 336 Table 337 Table 338 Table 339 Table 340 Table 341 Table 342 Table 343 Table 344 Table 345 Table 346 Table 347 Table 348 Table 349 Fields in GPIO_OE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236 Fields in GPIO_INTR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236 Fields in GPIO_INTR_ENA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237 Fields in GPIO_INTR_IDENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237 Fields in GPIO_ALT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237 Registers in DEVCPU_RST_REGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238 Fields in SOFT_CHIP_RST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238 Fields in SOFT_DEVCPU_RST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238 Registers in MIIM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239 Fields in MII_STATUS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239 Fields in MII_CMD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240 Fields in MII_DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241 Fields in MII_CFG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242 Fields in MII_SCAN_0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242 Fields in MII_SCAN_1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242 Fields in MII_SCAN_LAST_RSLTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243 Fields in MII_SCAN_LAST_RSLTS_VLD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243 Registers in MIIM_READ_SCAN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243 Fields in MII_SCAN_RSLTS_STICKY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244 Registers in RAM_STAT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244 Fields in RAM_INTEGRITY_ERR_STICKY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244 Registers in MISC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245 Fields in MISC_CFG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245 Fields in MISC_STAT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246 Fields in PHY_SPEED_1000_STAT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246 Fields in PHY_SPEED_100_STAT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246 Fields in PHY_SPEED_10_STAT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246 Fields in DUPLEXC_PORT_STAT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247 Registers in SIO_CTRL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247 Fields in SIO_INPUT_DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247 Fields in SIO_INT_POL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248 Fields in SIO_PORT_INT_ENA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248 Fields in SIO_PORT_CONFIG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249 Fields in SIO_PORT_ENABLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249 Fields in SIO_CONFIG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250 Fields in SIO_CLOCK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251 Fields in SIO_INT_REG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252 Registers in FAN_CFG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252 Fields in FAN_CFG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252 Registers in FAN_STAT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253 Fields in FAN_CNT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253 Registers in MEMITGR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254 Fields in MEMITGR_CTRL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254 Fields in MEMITGR_STAT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255 Fields in MEMITGR_INFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255 Fields in MEMITGR_IDX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257 Register Groups in DEVCPU_QS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257 Registers in XTR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257 Fields in XTR_FRM_PRUNING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258 Fields in XTR_GRP_CFG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258 Fields in XTR_MAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259 Fields in XTR_RD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259 Fields in XTR_QU_FLUSH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260 Fields in XTR_DATA_PRESENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260 Registers in INJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261 Fields in INJ_GRP_CFG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261 Fields in INJ_WR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261 Fields in INJ_CTRL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262 Fields in INJ_STATUS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263 VMDS-10392 VSC7420-02, VSC7421-02, and VSC7422-02 Datasheet Revision 4.3 xxv Table 350 Table 351 Table 352 Table 353 Table 354 Table 355 Table 356 Table 357 Table 358 Table 359 Table 360 Table 361 Table 362 Table 363 Table 364 Table 365 Table 366 Table 367 Table 368 Table 369 Table 370 Table 371 Table 372 Table 373 Table 374 Table 375 Table 376 Table 377 Table 378 Table 379 Table 380 Table 381 Table 382 Table 383 Table 384 Table 385 Table 386 Table 387 Table 388 Table 389 Table 390 Table 391 Table 392 Table 393 Table 394 Table 395 Table 396 Table 397 Table 398 Table 399 Table 400 Table 401 Table 402 Table 403 Table 404 Table 405 Table 406 Table 407 Table 408 Fields in INJ_ERR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264 Register Groups in HSIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264 Registers in PLL5G_STATUS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265 Fields in PLL5G_STATUS0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265 Registers in RCOMP_STATUS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265 Fields in RCOMP_STATUS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266 Registers in SERDES6G_ANA_CFG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266 Fields in SERDES6G_DES_CFG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267 Fields in SERDES6G_IB_CFG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268 Fields in SERDES6G_IB_CFG1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268 Fields in SERDES6G_OB_CFG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269 Fields in SERDES6G_OB_CFG1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270 Fields in SERDES6G_SER_CFG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270 Fields in SERDES6G_COMMON_CFG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271 Fields in SERDES6G_PLL_CFG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271 Registers in SERDES6G_DIG_CFG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272 Fields in SERDES6G_DIG_CFG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272 Fields in SERDES6G_MISC_CFG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273 Registers in MCB_SERDES6G_CFG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273 Fields in MCB_SERDES6G_ADDR_CFG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274 Register Groups in DEV_GMII . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274 Registers in PORT_MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274 Fields in CLOCK_CFG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275 Fields in PORT_MISC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275 Registers in MAC_CFG_STATUS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275 Fields in MAC_ENA_CFG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276 Fields in MAC_MODE_CFG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276 Fields in MAC_MAXLEN_CFG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277 Fields in MAC_TAGS_CFG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278 Fields in MAC_ADV_CHK_CFG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279 Fields in MAC_IFG_CFG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279 Fields in MAC_HDX_CFG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280 Fields in MAC_FC_CFG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281 Fields in MAC_FC_MAC_LOW_CFG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281 Fields in MAC_FC_MAC_HIGH_CFG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282 Fields in MAC_STICKY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282 Register Groups in DEV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283 Registers in PORT_MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284 Fields in CLOCK_CFG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284 Fields in PORT_MISC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285 Registers in MAC_CFG_STATUS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285 Fields in MAC_ENA_CFG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286 Fields in MAC_MODE_CFG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286 Fields in MAC_MAXLEN_CFG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287 Fields in MAC_TAGS_CFG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287 Fields in MAC_ADV_CHK_CFG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288 Fields in MAC_IFG_CFG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288 Fields in MAC_HDX_CFG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289 Fields in MAC_FC_CFG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290 Fields in MAC_FC_MAC_LOW_CFG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291 Fields in MAC_FC_MAC_HIGH_CFG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291 Fields in MAC_STICKY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292 Registers in PCS1G_CFG_STATUS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293 Fields in PCS1G_CFG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294 Fields in PCS1G_MODE_CFG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295 Fields in PCS1G_SD_CFG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295 Fields in PCS1G_ANEG_CFG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296 Fields in PCS1G_ANEG_NP_CFG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296 Fields in PCS1G_LB_CFG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297 VMDS-10392 VSC7420-02, VSC7421-02, and VSC7422-02 Datasheet Revision 4.3 xxvi Table 409 Table 410 Table 411 Table 412 Table 413 Table 414 Table 415 Table 416 Table 417 Table 418 Table 419 Table 420 Table 421 Table 422 Table 423 Table 424 Table 425 Table 426 Table 427 Table 428 Table 429 Table 430 Table 431 Table 432 Table 433 Table 434 Table 435 Table 436 Table 437 Table 438 Table 439 Table 440 Table 441 Table 442 Table 443 Table 444 Table 445 Table 446 Table 447 Table 448 Table 449 Table 450 Table 451 Table 452 Table 453 Table 454 Table 455 Table 456 Table 457 Table 458 Table 459 Table 460 Table 461 Table 462 Table 463 Table 464 Table 465 Table 466 Table 467 Fields in PCS1G_ANEG_STATUS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297 Fields in PCS1G_ANEG_NP_STATUS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 298 Fields in PCS1G_LINK_STATUS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 298 Fields in PCS1G_LINK_DOWN_CNT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 298 Fields in PCS1G_STICKY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299 Fields in PCS1G_LPI_CFG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299 Fields in PCS1G_LPI_WAKE_ERROR_CNT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300 Fields in PCS1G_LPI_STATUS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300 Registers in PCS1G_TSTPAT_CFG_STATUS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301 Fields in PCS1G_TSTPAT_MODE_CFG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302 Fields in PCS1G_TSTPAT_STATUS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302 Registers in PCS_FX100_CONFIGURATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303 Fields in PCS_FX100_CFG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303 Registers in PCS_FX100_STATUS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 304 Fields in PCS_FX100_STATUS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 304 Register Groups in ICPU_CFG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305 Registers in CPU_SYSTEM_CTRL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306 Fields in GPR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306 Fields in RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306 Fields in GENERAL_STAT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 307 Registers in SPI_MST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308 Fields in SPI_MST_CFG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308 Fields in SW_MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 309 Registers in MPU8051 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 309 Fields in MPU8051_STAT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 310 Fields in MPU8051_MMAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 310 Fields in MEMACC_CTRL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 312 Fields in MEMACC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 312 Fields in MEMACC_SBA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313 Registers in INTR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313 Fields in INTR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 315 Fields in INTR_ENA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 317 Fields in INTR_ENA_CLR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 318 Fields in INTR_ENA_SET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 319 Fields in INTR_RAW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 320 Fields in ICPU_IRQ0_ENA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 322 Fields in ICPU_IRQ0_IDENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 322 Fields in ICPU_IRQ1_ENA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 323 Fields in ICPU_IRQ1_IDENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 324 Fields in EXT_IRQ0_ENA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 325 Fields in EXT_IRQ0_IDENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 325 Fields in DEV_IDENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 326 Fields in EXT_IRQ0_INTR_CFG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 327 Fields in SW0_INTR_CFG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 328 Fields in SW1_INTR_CFG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 328 Fields in MIIM1_INTR_CFG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 329 Fields in MIIM0_INTR_CFG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 330 Fields in UART_INTR_CFG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 330 Fields in TIMER0_INTR_CFG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 331 Fields in TIMER1_INTR_CFG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 331 Fields in TIMER2_INTR_CFG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 332 Fields in TWI_INTR_CFG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 332 Fields in GPIO_INTR_CFG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 333 Fields in SGPIO_INTR_CFG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 333 Fields in DEV_ALL_INTR_CFG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 334 Fields in BLK_ANA_INTR_CFG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 335 Fields in XTR_RDY0_INTR_CFG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 335 Fields in XTR_RDY1_INTR_CFG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 336 Fields in INJ_RDY0_INTR_CFG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 337 VMDS-10392 VSC7420-02, VSC7421-02, and VSC7422-02 Datasheet Revision 4.3 xxvii Table 468 Table 469 Table 470 Table 471 Table 472 Table 473 Table 474 Table 475 Table 476 Table 477 Table 478 Table 479 Table 480 Table 481 Table 482 Table 483 Table 484 Table 485 Table 486 Table 487 Table 488 Table 489 Table 490 Table 491 Table 492 Table 493 Table 494 Table 495 Table 496 Table 497 Table 498 Table 499 Table 500 Table 501 Table 502 Table 503 Table 504 Table 505 Table 506 Table 507 Table 508 Table 509 Table 510 Table 511 Table 512 Table 513 Table 514 Table 515 Table 516 Table 517 Table 518 Table 519 Table 520 Table 521 Table 522 Table 523 Table 524 Table 525 Table 526 Fields in INJ_RDY1_INTR_CFG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 337 Fields in INTEGRITY_INTR_CFG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 338 Fields in DEV_ENA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 338 Registers in TIMERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 339 Fields in WDT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 339 Fields in TIMER_TICK_DIV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 340 Fields in TIMER_VALUE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 341 Fields in TIMER_RELOAD_VALUE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 341 Fields in TIMER_CTRL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 341 Registers in TWI_DELAY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 342 Fields in TWI_CONFIG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 343 Register Groups in UART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 343 Registers in UART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 343 Fields in RBR_THR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 345 Fields in IER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 345 Fields in IIR_FCR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 347 Fields in LCR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 348 Fields in MCR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 349 Fields in LSR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 350 Fields in MSR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 353 Fields in SCR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 354 Fields in USR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 354 Register Groups in TWI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 355 Registers in TWI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 355 Fields in CFG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 356 Fields in TAR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 358 Fields in SAR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 359 Fields in DATA_CMD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 360 Fields in SS_SCL_HCNT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 361 Fields in SS_SCL_LCNT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 361 Fields in FS_SCL_HCNT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 361 Fields in FS_SCL_LCNT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 362 Fields in INTR_STAT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 362 Fields in INTR_MASK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 363 Fields in RAW_INTR_STAT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 363 Fields in RX_TL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 368 Fields in TX_TL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 368 Fields in CLR_INTR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 368 Fields in CLR_RX_UNDER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 369 Fields in CLR_RX_OVER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 369 Fields in CLR_TX_OVER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 369 Fields in CLR_RD_REQ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 369 Fields in CLR_TX_ABRT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 370 Fields in CLR_RX_DONE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 370 Fields in CLR_ACTIVITY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 370 Fields in CLR_STOP_DET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 371 Fields in CLR_START_DET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 371 Fields in CLR_GEN_CALL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 371 Fields in CTRL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 372 Fields in STAT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 372 Fields in TXFLR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 374 Fields in RXFLR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 374 Fields in TX_ABRT_SOURCE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 374 Fields in SDA_SETUP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 376 Fields in ACK_GEN_CALL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 377 Fields in ENABLE_STATUS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 377 Register Groups in PHY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 378 Registers in PHY_STD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 378 Fields in PHY_CTRL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 380 VMDS-10392 VSC7420-02, VSC7421-02, and VSC7422-02 Datasheet Revision 4.3 xxviii Table 527 Table 528 Table 529 Table 530 Table 531 Table 532 Table 533 Table 534 Table 535 Table 536 Table 537 Table 538 Table 539 Table 540 Table 541 Table 542 Table 543 Table 544 Table 545 Table 546 Table 547 Table 548 Table 549 Table 550 Table 551 Table 552 Table 553 Table 554 Table 555 Table 556 Table 557 Table 558 Table 559 Table 560 Table 561 Table 562 Table 563 Table 564 Table 565 Table 566 Table 567 Table 568 Table 569 Table 570 Table 571 Table 572 Table 573 Table 574 Table 575 Table 576 Table 577 Table 578 Table 579 Table 580 Table 581 Table 582 Table 583 Table 584 Table 585 Fields in PHY_STAT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 381 Fields in PHY_IDF1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 382 Fields in PHY_IDF2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 382 Fields in PHY_AUTONEG_ADVERTISMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 383 Fields in PHY_AUTONEG_LP_ABILITY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 383 Fields in PHY_AUTONEG_EXP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 384 Fields in PHY_AUTONEG_NEXTPAGE_TX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 384 Fields in PHY_AUTONEG_LP_NEXTPAGE_RX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 385 Fields in PHY_CTRL_1000BT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 386 Fields in PHY_STAT_1000BT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 386 Fields in MMD_ACCESS_CFG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 387 Fields in MMD_ADDR_DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 388 Fields in PHY_STAT_1000BT_EXT1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 388 Fields in PHY_STAT_100BTX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 388 Fields in PHY_STAT_1000BT_EXT2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 389 Fields in PHY_BYPASS_CTRL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 390 Fields in PHY_ERROR_CNT1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 392 Fields in PHY_ERROR_CNT2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 392 Fields in PHY_ERROR_CNT3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 392 Fields in PHY_CTRL_STAT_EXT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 393 Fields in PHY_CTRL_EXT1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 395 Fields in PHY_CTRL_EXT2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 395 Fields in PHY_INT_MASK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 397 Fields in PHY_INT_STAT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 398 Fields in PHY_AUX_CTRL_STAT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 401 Fields in PHY_MEMORY_PAGE_ACCESS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 403 Registers in PHY_EXT1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 403 Fields in PHY_CRC_GOOD_CNT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 404 Fields in PHY_EXT_MODE_CTRL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 404 Fields in PHY_CTRL_EXT3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 405 Fields in PHY_CTRL_EXT4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 406 Fields in PHY_1000BT_EPG1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 407 Fields in PHY_1000BT_EPG2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 409 Registers in PHY_EXT2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 410 Fields in PHY_PMD_TX_CTRL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 410 Fields in PHY_EEE_CTRL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 410 Registers in PHY_GP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 411 Fields in PHY_COMA_MODE_CTRL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 412 Fields in PHY_GLOBAL_INT_STAT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 412 Registers in PHY_EEE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 414 Fields in PHY_PCS_STATUS1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 414 Fields in PHY_EEE_CAPABILITIES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 415 Fields in PHY_EEE_WAKE_ERR_CNT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 415 Fields in PHY_EEE_ADVERTISEMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 415 Fields in PHY_EEE_LP_ADVERTISEMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 416 Internal Pull-Up or Pull-Down Resistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 417 Reference Clock Input DC Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 417 Enhanced SerDes Driver DC Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 419 Enhanced SerDes Receiver DC Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 419 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 420 MIIM, GPIO, SI, JTAG, and Miscellaneous Signals DC Specifications . . . . . . . . . . . . . . . . . . . . 420 Reference Clock AC Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 421 nReset Timing Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 422 Enhanced SerDes Output AC Specifications in SGMII Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 423 Enhanced SerDes Output AC Specifications in QSGMII Mode . . . . . . . . . . . . . . . . . . . . . . . . . . 423 Enhanced SerDes Output AC Specifications in 2.5G Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 423 Enhanced SerDes Driver Jitter Characteristics in SGMII Mode . . . . . . . . . . . . . . . . . . . . . . . . . . 424 Enhanced SerDes Driver Jitter Characteristics in QSGMII Mode . . . . . . . . . . . . . . . . . . . . . . . . . 424 Enhanced SerDes Input AC Specifications in SGMII Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 424 VMDS-10392 VSC7420-02, VSC7421-02, and VSC7422-02 Datasheet Revision 4.3 xxix Table 586 Table 587 Table 588 Table 589 Table 590 Table 591 Table 592 Table 593 Table 594 Table 595 Table 596 Table 597 Table 598 Table 599 Table 600 Table 601 Table 602 Table 603 Table 604 Table 605 Table 606 Table 607 Table 608 Table 609 Table 610 Table 611 Table 612 Table 613 Table 614 Table 615 Table 616 Table 617 Table 618 Table 619 Table 620 Table 621 Table 622 Table 623 Table 624 Table 625 Table 626 Table 627 Table 628 Table 629 Table 630 Table 631 Table 632 Table 633 Table 634 Table 635 Table 636 Table 637 Table 638 Table 639 Table 640 Table 641 Table 642 Enhanced SerDes Input AC Specifications in QSGMII Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 425 Enhanced SerDes Input AC Specifications in 2.5G Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 425 Enhanced SerDes Receiver Jitter Tolerance in SGMII Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 425 Enhanced SerDes Receiver Jitter Tolerance in QSGMII Mode . . . . . . . . . . . . . . . . . . . . . . . . . . 426 MIIM Timing Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 427 SI Timing Specifications for Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 427 SI Timing Specifications for Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 429 JTAG Interface AC Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 430 Serial I/O Timing Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 431 Two-Wire Serial Interface AC Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 432 Operating Current for VSC7420-02 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 434 Operating Current for VSC7421-02 and VSC7422-02 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 434 Power Consumption for VSC7420-02 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 434 Power Consumption for VSC7421-02 and VSC7422-02 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 435 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 435 Stress Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 436 Pin Type Symbol Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 438 Analog Bias Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 438 System Clock Interface Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 439 GPIO Pin Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 439 JTAG Interface Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 440 MII Management Interface Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 440 Miscellaneous Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 440 Power Supply and Ground Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 441 Serial CPU Interface Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 442 Enhanced SerDes Interface Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 442 Twisted Pair Interface Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 442 Pin Type Symbol Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 451 Pin Type Symbol Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 487 Analog Bias Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 487 System Clock Interface Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 488 GPIO Pin Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 488 JTAG Interface Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 489 MII Management Interface Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 489 Miscellaneous Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 489 Power Supply and Ground Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 490 Serial CPU Interface Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 491 Enhanced SerDes Interface Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 491 Twisted Pair Interface Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 491 Pin Type Symbol Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500 Pin Type Symbol Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 538 Analog Bias Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 538 System Clock Interface Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 539 GPIO Pin Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 539 JTAG Interface Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 540 MII Management Interface Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 540 Miscellaneous Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 540 Power Supply and Ground Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 541 Serial CPU Interface Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 542 Enhanced SerDes Interface Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 542 Twisted Pair Interface Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 542 Pin Type Symbol Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 551 Thermal Resistances TQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 588 Thermal Resistances BGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 588 Enhanced SerDes Interface Coupling Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 592 Ordering Information: TQFP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 595 Ordering Information: BGA Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 596 VMDS-10392 VSC7420-02, VSC7421-02, and VSC7422-02 Datasheet Revision 4.3 xxx Revision History 1 Revision History This section describes the changes that were implemented in this document. The changes are listed by revision, starting with the most current publication. 1.1 Revision 4.3 Revision 4.3 of this datasheet was published in January 2019. The following is a summary of the changes implemented in the datasheet: • • • • 1.2 Frame Arrival section was updated. For more information, see Frame Arrival, page 6. MIIM Interface in Slave Mode section was updated with a note. For more information, see MIIM Interface in Slave Mode, page 104. VeriPHY™ Cable Diagnostics section was updated. For more information, see VeriPHY™ Cable Diagnostics, page 32. VeriPHY control registers were deleted. For more information, see PHY:PHY_EXT1, page 403. Revision 4.2 Revision 4.2 of this datasheet was published in July 2018. In revision 4.2 of the document, a ball-grid array (BGA) package option of the device was added. The following is a summary of the additions to the datasheet. • • • • 1.3 Pin information for the BGA package device was added. For more information, see Pin Descriptions for VSC7420XJQ-02, page 437, Pin Descriptions for VSC7421XJQ-02, page 486, and Pin Descriptions for VSC7422XJQ-02, page 537. BGA package outline drawing was added. For more information, see Package Drawing, page 585. Thermal specifications for the BGA package was added. For more information, see Thermal Specifications, page 587. Ordering information was updated to reflect the availability of BGA devices. For more information, see Ordering Information, page 595. Revision 4.1 Revision 4.1 of this datasheet was published in July 2018. In revision 4.1 of the document, the VSC742004, VSC7421-04, and VSC7422-04 part numbers were added to reflect the availability of devices with extended operating temperature ranges of –40 °C ambient to 125 °C junction. For more information, see Ordering Information: BGA Package, page 596. 1.4 Revision 4.0 Revision 4.0 of this datasheet was published in December 2012. The following is a summary of the changes implemented in the datasheet: • • 1.5 Errata items, which were previously published in the VSC7420-02, VSC7421-02, and VSC7422-02 Errata revision 1.0 as open issues, are now reconciled in the datasheet. Now that the information is available in the datasheet, the previously published errata document no longer applies, and it has been removed from the Microsemi Web site. It was clarified that the VCore-Ie CPU frequency is 250 MHz, and the VCore-Ie system frequency is 125 MHz. Revision 2.0 Revision 2.0 of this datasheet was published in September 2012. This was the first publication of the document. VMDS-10392 VSC7420-02, VSC7421-02, and VSC7422-02 Datasheet Revision 4.3 1 Introduction 2 Introduction This document consists of descriptions and specifications for both functional and physical aspects of the VSC7420-02, VSC7421-02, and VSC7422-02 devices. It is intended for system designers and software developers. In addition to the datasheet, Microsemi maintains an extensive part-specific library of support and collateral materials that you may find useful in developing your own product. Depending upon the Microsemi device, this library may include: • • • • • • • Application notes that provide detailed descriptions of the use of the particular Microsemi product to solve real-world problems White papers published by industry experts that provide ancillary and background information useful in developing products that take full advantage of Microsemi product designs and capabilities User guides that describe specific techniques for interfacing to the particular Microsemi products Reference designs showing the Microsemi device built in to applications in ways intended to exploit its relative strengths Software Development Kits with sample commands and scripts Presentations highlighting the operational features and specifications of the devices to assist in developing your own product road map Input/Output Buffer Information specification (IBIS) models to help you create and support the interfaces available on the particular Microsemi product Visit and register as a user on the Microsemi Web site to keep abreast of the latest innovations from research and development teams and the most current product and application documentation. The address of the Microsemi Web site is www.Microsemi.com. 2.1 Register Notation This datasheet uses the following general register notation: ::. is not always present. In that case, the following notation is used: ::. When a register group does exist, it is always prepended with a target in the notation. In sections where only one register is discussed, or the target (and register group) is known from the context, the :: may be omitted for brevity, and uses the following notation: . Also, when a register contains only one field, the . is not included in the notation. 2.2 Standard References This document uses the following industry references. VMDS-10392 VSC7420-02, VSC7421-02, and VSC7422-02 Datasheet Revision 4.3 2 Introduction Referenced Documents Table 1 • Document Title Revision 802.1Q Amendment 4: Provider Bridges -2005 IEEE IEEE 802.1ad IEEE 802.1D Media Access Control (MAC) Bridges -2004 IEEE 802.1Q Virtual Bridged Local Area Networks -2005 IEEE 802.3 Local and metropolitan area networks — Specific requirements -2008 Carrier sense multiple access with collision detection (CSMA/CD) access method and physical layer specifications IEEE 802.3az Standard for Information Technology - Telecommunications and -2010 Information Exchange Between Systems - Local and Metropolitan Area Networks - Specific Requirements Part 3: Carrier Sense Multiple Access with Collision Detection (CSMA/CD) Access Method and Physical Layer Specifications Amendment: Media Access Control Parameters, Physical Layers and Management Parameters for Energy-Efficient Ethernet IETF RFC-2236 Internet Group Management Protocol, Version 2 (IGMPv2) November 1997 RFC-2710 Multicast Listener Discovery for IPv6 (MLDv1) October 1999 RFC-2819 Remote Network Monitoring (RMON) MIB May 2000 RFC-2863 The Interfaces Group MIB June 2000 RFC-3635 Definitions of Managed Objects for Ethernet-like Interface Types September 2003 Other ENG-46158 Cisco Serial GMII (SGMII) Specification EDCS-540123 Cisco QSGMII Specification 2.3 1.7 1.3 Terms and Abbreviations The following terms and abbreviations are used throughout this document. Terms and Abbreviations Table 2 • Term Explanation DEI IEEE Drop Eligible Indicator. PB IEEE 802.1AD Provider Bridging (also known as “Q-in-Q”). PCP IEEE Priority Code Point interpretation of Ethernet Priority (also known as 802.1p) bits. VID IEEE VLAN Identifier. Classified VLAN The final VLAN ID classification of a frame used in the forwarding process. VMDS-10392 VSC7420-02, VSC7421-02, and VSC7422-02 Datasheet Revision 4.3 3 Product Overview 3 Product Overview The SparX-III family of Gigabit Ethernet switches are pin-compatible devices with port counts ranging from 10 Gigabit Ethernet ports to 25 Gigabit Ethernet ports. The switches integrate up to 12 Gigabit copper PHYs and provide both SGMII and quad SGMII (QSGMII) interfaces. Up to two ports can run at 2.5 Gbps. These devices provide a rich set of Ethernet switching features such as Layer-2 forwarding with basic VLAN and QoS processing enabling delivery of differentiated services. Each product in the family contains an 8051 CPU enabling light management of the switch. Optionally, the switches can be managed from an external CPU using a serial interface or a MIIM interface. The SparX-III family contains the following three products: • • VSC7420-02 supports 8× 1G copper PHYs + 2× 2.5G SGMII VSC7421-02 supports two major port configurations: 12× 1G copper PHY + 2× 1G SGMII + 2× 2.5G SGMII • 3.1 General Features • • • • • • • • • • • 3.1.1 All 1G Ethernet ports are tri-speed 10/100/1000 Mbps ports All 2.5G Ethernet ports are quad-speed 10/100/1000/2500 Mbps ports Integrated copper transceivers are compliant with IEEE 802.3ab and support Microsemi ActiPHY™ link down power savings and PerfectReach™ smart cable reach algorithm SGMII ports support both 100-BASE-FX and 1000-BASE-X-SERDES Four megabits of integrated shared packet memory Fully nonblocking wire-speed switching performance for all frame sizes Eight priorities and eight queues per port Policing per queue and per port DWRR scheduler/shaper per queue and per port with a mix of strict and weighted queues Energy Efficient Ethernet (IEEE 802.3az) is supported by both the switch core and the internal copper PHYs VCore-Ie CPU system with integrated 8051 Layer-2 Switching • • • • • • • • • • 3.1.2 12× 1G copper PHY + 1× 2.5G SGMII + 1× QSGMII VSC7422-02 supports 12× 1G copper PHYs + 3× QSGMII + 1× 2.5G SGMII 8,192 MAC addresses 4,096 VLANs (IEEE 802.1Q) Push and pop of VLAN tags Link aggregation (IEEE 802.3ad) Link aggregation traffic distribution is programmable and based on Layer 2 through Layer 4 information Wire-speed hardware-based learning and CPU-based learning configurable per port Independent and shared VLAN learning Provider Bridging (VLAN Q-in-Q) support (IEEE 802.1ad) Rapid Spanning Tree Protocol support (IEEE 802.1w) Jumbo frame support up to 9.6 kilobytes with programmable MTU per port Multicast • • • • 8K L2 multicast group addresses with 64 port masks 8K IPv4/IPv6 multicast groups Internet Group Management Protocol version 2 (IGMPv2) support Multicast Listener Discovery (MLDv1) support VMDS-10392 VSC7420-02, VSC7421-02, and VSC7422-02 Datasheet Revision 4.3 4 Product Overview 3.1.3 Quality of Service • • • • • • 3.1.4 Security • • • • • • • 3.1.5 Generic storm controllers for flooded broadcast, flooded multicast, and flooded unicast traffic Selectable CPU queues for segregation of CPU redirected traffic, with 8 queues supported Per-port, per-address registration for snooping of reserved IEEE MAC addresses (BPDU, GARP) Port-based and MAC-based access control (IEEE 802.1X) Per-port CPU-based learning with option for secure CPU-based learning Per-port ingress and egress mirroring Mirroring per VLAN Management • • • • • • • 3.2 Eight QoS queues per port with strict or deficit weighted round-robin scheduling (DWRR) DSCP translation, both ingress and/or egress DSCP remarking based on QoS class PCP and DEI remarking based on QoS class Per-queue and per-port policing and shaping, programmable in steps of 100 kbps Full-duplex flow control (IEEE 802.3X) and half-duplex backpressure, symmetric and asymmetric 8051 CPU system with 64 kilobytes of internal RAM CPU frame extraction (eight queues) and injection (two queues), which enables efficient data transfer between Ethernet ports and CPU Fourteen pin-shared general-purpose I/Os Serial LED controller controlling up to 32 ports with four LEDs each Serial GPIO controller PHY management controller Per-port 32-bit counter set with support for the RMON statistics group (RFC 2819) and SNMP interfaces group (RFC 2863) Applications VSC7420-02, VSC7421-02, and VSC7422-02 target the unmanaged and web-managed Ethernet switch equipment in the SMB. 3.3 Related Products VSC7424-02 SparX-III managed Gigabit Ethernet switch: 10 ports with 8 integrated PHYs and 2 SGMIIs VSC7425-02 SparX-III managed Gigabit Ethernet switch: 18 ports with 12 integrated PHYs and 6 SGMIIs VSC7426-02 SparX-III managed Gigabit Ethernet switch: 24 ports with 12 integrated PHYs and 3 QSGMII VSC7427-02 SparX-III managed Gigabit Ethernet switch: 26 ports with 12 integrated PHYs, 3 QSGMII, and 2 SGMIIs The VSC7424-02, VSC7425-02, VSC7426-02, and VSC7427-02 family of fully managed Layer-2 Ethernet switches provides comprehensive support for QoS, VLAN, and security. They include advanced classification through the Microsemi Contents Aware Processor (VCAP), as well as a CPU system enabled with a 416 MHz MIPS 24KEc™ CPU. 3.4 Functional Overview This section provides an overview all major blocks and functions involved in the bridging operation in the same order as a frame traverses through the devices. It also outlines other major functionality of the device such as the CPU port module, the CPU system, and CPU interfaces. The following illustration shows the block diagram for the VSC7422-02. The other devices in the family have similar block diagrams. VMDS-10392 VSC7420-02, VSC7421-02, and VSC7422-02 Datasheet Revision 4.3 5 Product Overview Figure 1 • VSC7422-02 Block Diagram Switch Core CPU System – 8051 Shared Queue System Memory Controller Shared Memory Pool Ingress Processing CPU I/F 8051 On-chip RAM (64 KB) Target Access Scratch Pad (256 B) JTAG Shaper and Scheduler Egress Processing SI MIIM L2 Forwarding Ingress Statistics Rewriter Policer VLAN Tagging Push/Pop Tag Classification VLAN and QoS Egress Statistics GPIO JTAG_CLK JTAG_DI JTAG_DO JTAG_TMS JTAG_TRT SI_Clk SI_DI SI_DO SI_nEn MDC MDIO GPIO[13:0] LED SGPIO UART TACHO Two-Wire Serial IRQ CPU Port Module Port Module Interface Port Module #0 Port Module #1 Port Module #11 Port Module #12-15 Port Module #20-23 Port Module #24 MAC MAC MAC MAC MAC MAC SerDes6G #2 SerDes6G #1 SerDes6G #0 (QSGMII) (QSGMII) (QSGMII) (2.5G) SerDes_E1_TxP SerDes_E1_TxN SerDes_E1_RxP SerDes_E1_RxN SerDes_E0_TxP SerDes_E0_TxN SerDes_E0_RxP SerDes_E0_RxN 4x High Speed I/Os SerDes6G #3 SerDes_E2_TxP SerDes_E2_TxN SerDes_E2_RxP SerDes_E2_RxN P11_D[3:0]N P11_D[3:0]P P1_D[3:0]N P1_D[3:0]P P0_D[3:0]N P0_D[3:0]P 3.4.1 4x SerDes_E3_TxP SerDes_E3_TxN SerDes_E3_RxP SerDes_E3_RxN Copper PHYs 12 x CuPHY 4x nRESET RefClk_Sel[2:0] RefClkP RefClkN COMA_MODE Frame Arrival The Ethernet interfaces receive incoming frames and forward these to the port modules. Supported interfaces include copper transceivers, QSGMII, SGMII, and SerDes. The integrated low-power copper transceivers support full duplex operation at 10/100/1000 Mbps and half-duplex operation at 10/100 Mbps. The key PHY features are: • • Low power consumption in all modes through ActiPHY™ link down power savings, PerfectReach™ smart cable reach algorithm, and IEEE 802.3az Energy Efficient Ethernet idle power savings. VeriPHY® cable diagnostics suite provides extensive network cable operating conditions and status. The device features a serial LED controller interface for driving LED pins on both internal and external PHYs. The 1G SGMII and 2.5G SGMII ports support both 100BASE-X and 1000BASE-X-SERDES. Each port module contains a Media Access Controller (MAC) that performs a full suite of checks, such as VLAN Tag-aware frame size checking, frame check sequence (FCS) checking, and pause frame identification. VMDS-10392 VSC7420-02, VSC7421-02, and VSC7422-02 Datasheet Revision 4.3 6 Product Overview Each port module connecting to a SerDes macro contains a Physical Coding Sublayer (PCS) which perform 8 bits/10 bits encoding, auto-negotiation of link speed and duplex mode, and monitoring of the link status. Full-duplex is supported for all speeds, and half-duplex is supported for 10 Mbps and 100 Mbps. Symmetric and asymmetric pause flow control are both supported. All Ethernet ports support Energy Efficient Ethernet (EEE) according to IEEE 802.3az. The shared queue system is capable of controlling the operating states, active or low-power, of the PCS or the internal PHYs. Both the PCS and PHYs understand the line signaling as required for EEE. This includes signaling of active, sleep, quiet, refresh, and wake. Each QSGMII port can multiplex four port modules onto one I/O interface. Each of the underlying port modules has its own MAC and PCS and can negotiate link speed and duplex mode independently of the other port modules. 3.4.2 Frame Classification Each frame is sent to the ingress processing module for classification to a VLAN, classification to a Quality of Service (QoS) class, policing, collecting statistics, security enforcement, and Layer-2 forwarding. The classification engine can understand up to two VLAN tags and can look for Layer-3 and Layer-4 information behind two VLAN tags. If frames are triple tagged, the higher-layer protocol information is not extracted. The following illustration shows the frame classification. Figure 2 • Frame Classification Frame Data Basic Classification Frame Acceptance Frame Data Discard Untagged, S-tagged, C-tagged Special frames VLAN VLAN tag header VLAN pop count VLAN tag from frame Port VLAN QoS and DSCP QoS class DSCP value PCP from tag (inner or outer) DSCP from frame, trusted values only Remap/rewrite of DSCP Port default Aggregation Code Aggregation Code L2-L4 frame data The classification classifies each frame to a VLAN, a QoS class, DSCP value, and an aggregation code. The basic classification also performs a general frame acceptance check. Frame Acceptance The frame acceptance filter checks for valid combinations of VLAN tags against the ingress port’s VLAN acceptance filter where it is possible to configure rules for accepting untagged, priority-tagged, C-, and S-tagged frames. In addition, the filter also enables discarding of frames with illegal MAC addresses (for instance null MAC address or multicast source MAC address). VMDS-10392 VSC7420-02, VSC7421-02, and VSC7422-02 Datasheet Revision 4.3 7 Product Overview VLAN Every incoming frame is classified to a VLAN by the basic VLAN classification. This is based on the VLAN in the frame, or if the frame is untagged or the ingress port is VLAN unaware, it is based on the ingress port’s default VLAN. A VLAN classification includes the whole TCI (PCP, DEI, and VID) and also the TPID (C-tag or S-tag). For double-tagged frames, it is selectable whether the inner or the outer tag is used. The devices can recognize S-tagged frames with the standard TPID (0x88A8) or S-tagged frames using a custom programmable value. One custom value is supported by the devices. QoS and DSCP Each frame is classified to a Quality of Service (QoS) class. The QoS class is used throughout the devices for providing queuing, scheduling, and congestion control guarantees to the frame according to what is configured for that specific QoS class. The QoS class is assigned based on the class of service information in the frame’s VLAN tags (PCP and DEI) and/or the DSCP values from the IP header. Both IPv4 and IPv6 are supported. If the frame is nonIP or untagged, the port’s default QoS class is used. The DSCP values can be remapped before being used for QoS. This is done using a common table mapping the incoming DSCP to a new value. Remapping is enabled per port. In addition, for each DSCP value, it is possible to specify whether the value is trusted for QoS purposes. Each IP frame is also classified to an internal DSCP value. By default, this value is taken from the IP header but it may be remapped using the common DSCP mapping table or rewritten based on the assigned QoS class. The classified DSCP value may be written into the frame at egress – this is programmable in the rewriter. Aggregation Code Finally, the basic classification calculates an aggregation code, which is used to select between ports that are member of a link aggregation group. The aggregation code is based on selected Layer-2 through Layer-4 information, such as MAC addresses, IP addresses, IPv6 flow label, and TCP/UDP port numbers. The aggregation code ensures that frames belonging to the same conversation are using the same physical ports in a link aggregation group. 3.4.3 Policing Each frame is subject to a number of different policing operations. The devices feature per queue and per port programmable policers. It is programmable per port whether to use the port policer and the queue policers. It is also programmable whether the policers are working in serial or in parallel. Each frame is counted in associated statistics reflecting the ingress port and the QoS class. The statistics can count bytes or frames. Finally, the analyzer contains a group of storm control policers that are capable of policing various kinds of flooding traffic as well as CPU directed learn traffic. These policers are global policers working on all frames received by the switch. All policers can measure frame rates or bit rates. 3.4.4 Layer-2 Forwarding After the policers, the Layer-2 forwarding block (the analyzer) handles all fundamental bridging operations and maintains the associated MAC table, the VLAN table, and the aggregation table. The devices implement an 8K MAC table and a 4K VLAN table. The main task of the analyzer is to determine the destination port set of each frame. This forwarding decision is based on various information such as the frame’s ingress port, source MAC address, destination MAC address, and the VLAN identifier, as well as mirroring, and the destination port’s link aggregation configuration. The switch performs Layer-2 forwarding of frames. For unicast and Layer-2 multicast frames, this means forwarding based on the destination MAC address and the VLAN. For IPv4 multicast frames, the switch performs Layer-2 forwarding, but based on Layer-3 information. The following describes some of the contributions to the Layer-2 forwarding: VMDS-10392 VSC7420-02, VSC7421-02, and VSC7422-02 Datasheet Revision 4.3 8 Product Overview • • • • • 3.4.5 VLAN classification VLAN-based forward filtering include source port filtering, destination port filtering, VLAN mirroring, asymmetric VLANs, and so on. MAC addresses Destination and source MAC address lookups in the MAC table determine if a frame is a learn frame, a flood frame, a multicast frame, or a unicast frame. Learning By default, the devices perform wire-speed learning on all ports. However, certain ports could be configured with secure learning enabled, where an incoming frame with unknown source MAC address is classified as a “learn frame” and is redirected to the CPU. The CPU performs the learning decision and also decides whether the frame is forwarded. Learning can also be disabled. In that case, it does not matter if the source MAC address is in the MAC table. Link aggregation A frame targeted at a link aggregate is further processed to determine which of the link aggregate group ports the frame must be forwarded to. Mirroring Mirror probes may be set up in different places in the forwarding path for monitoring purposes. As part of a mirror a copy of the frame is sent either to the CPU or to another port. Shared Queue System and Egress Scheduler The analyzer provides the destination port set of a frame to the shared queue system. It is the queue system's task to control the frame forwarding to all destination ports. The shared queue system embeds 4Mbits of memory that can be shared between all queues and ports. The queue system implements egress queues per priority per ingress port. The sharing of resources between queues and ports is controlled by an extensive set of thresholds. The overall frame latency through the switch is low due to the shared queue system only storing the frame once. Each egress port implements a scheduler and shapers as shown in the following illustration. Per egress port, the scheduler sees the outcome of aggregating the egress queues (one per ingress port per Qos class) into eight queues, one queue per QoS class. The aggregation is done in a round-robin fashion per QoS class serving all ingress ports equally. Figure 3 • Egress Scheduler and Shaper Shapers Queue Q7 S Q6 S Q5 Q0 Wt_5 Wt_0 S S Port High Med D W R R Low S T R I C T S Queue Schedulers When transmitting frames from the shared queue system out on an egress port, frames are scheduled within the port using one of two methods: • • Strict priority – frames with the highest priority are always transmitted before frames with lower priority. Deficit Weighted Round Robin (DWRR) – queues 6 and 7 are always strict, and queues 0 through 5 are weighted. Each queue sets a weight ranging from 0 to 31. In addition, each egress port implements shapers, one per egress queue and one per port. 3.4.6 Rewriter and Frame Departure Before transmitting the frame on the egress line, the rewriter can modify selected fields in the frame, such as VLAN tags, DSCP value, and FCS. The rewriter controls the final VLAN tagging of frames based on the classified VLAN, the VLAN pop count, and egress-determined VLAN actions. The egress VLAN actions are by default given by the VMDS-10392 VSC7420-02, VSC7421-02, and VSC7422-02 Datasheet Revision 4.3 9 Product Overview egress port settings. These include normal VLAN operations such as pushing a VLAN tag, untagging for specific VLANs, and simple translations of DEI and PCP. The PCP and DEI bits in the VLAN tag are subject to remarking based on translating the classified tag header or by using the classified QoS value from ingress. In addition, the DSCP value in IP frames can be updated using the classified DSCP value from ingress. The DSCP value can be remapped at egress before writing it into the frame. Finally, the rewriter updates the FCS if the frame was modified before the frame is transmitted. The egress port module controls the flow control exchange of pause frames with a neighboring device when the interconnection link operates in full-duplex flow control mode. When the connected device triggers flow control through transmission of a pause frame, the MAC stops the egress scheduler’s forwarding of frames out of the port. Traffic then builds up in the queue system but sufficient queuing is available to ensure wire speed lossless operation. In half-duplex operation, the port module’s egress path responds to back pressure generation from a connected device by collision detection and frame retransmission. 3.4.7 CPU Port Module The CPU port module contains eight CPU extraction queues and two CPU injection queues. These queues provide an interface for exchanging frames between the internal CPU system and the switch core. An external CPU using the serial interface can also inject and extract frames to and from the switch core by using the CPU port module. Additionally, any Ethernet interface on the devices can be used for extracting and injecting frames. The switch core can intercept a variety of different frame types and copy or redirect these to the CPU extraction queues. The classifier can identify a set of well-known frames such as IEEE reserved destination MAC addresses (BPDUs, GARPs), as well as IP-specific frames (IGMP, MLD). In addition, frames can be intercepted based on the MAC table, the VLAN table, or the learning process. Whenever a frame is copied or redirected to the CPU, a CPU extraction queue number is associated with the frame and used by the CPU port module when enqueuing the frame into the 8 CPU extraction queues. The CPU extraction queue number is programmable for every interception option in the switch core. 3.4.8 CPU System and Interfaces The devices feature a VCore-Ie CPU system containing a 208 MHz 8051 CPU. It is suitable for basic switch tasks such as simple runtime protocols and port state monitoring. VCore-Ie includes 64 kilobytes of internal storage, which can be used for code and data. In addition to the integrated processor, the CPU system permits the attachment of an external CPU. For configuration of switch register, an external CPU can use a serial interface. For frame transfers, the external CPU has the option of using the serial interface or an SGMII port. The devices include a GPIO interface with 14 individually configurable pins. Through the GPIOs, various interfaces are supported by the devices: • • • • • Two-wire serial interface (two GPIO pins) UART (two GPIO pins) External interrupt (one interrupt pin) Serial GPIO (SGPIO) and LED interface (four GPIO pins) Fan controller with speed input and pulse-width-modulated output (two GPIO pins) The Serial GPIO and LED interface can specifically be used for driving external LEDs for the internal and external copper PHYs or for serializing external interrupts, for instance link down events from external PHYs, before being input to the devices. Finally, each of the devices has two MII management controllers; one for the internal PHYs and one connected to the MIIM interface for controlling external PHYs. VMDS-10392 VSC7420-02, VSC7421-02, and VSC7422-02 Datasheet Revision 4.3 10 Functional Descriptions 4 Functional Descriptions This section provides detailed information about the functional aspects of the VSC7420-02, VSC7421-02, and VSC7422-02 Gigabit Ethernet switch devices, available configurations, operational features, and testing functionality. 4.1 Port Modules The port modules contain the following functional blocks: • • MAC PCS (ports connecting to a high-speed I/O SerDes macro) Ports connecting to one of the integrated copper transceivers do not have a PCS. 4.1.1 Port Module Numbering and Macro Connections The port modules connect to the interface macros. The interface macros can be of two types: • • Internal copper PHY SERDES6G macro The interface macros connect to the external interface pins. For more information about the SerDes macros and integrated copper transceivers, see SERDES6G, page 18 and Copper Transceivers, page 24. Which switch core port modules are connected to which interface macros depends on part number and for some parts on internal configuration. VSC7421-02 can be used in two different port configurations: switch mode 0 or switch mode 1. The VSC7420-02 and VSC7422-02 devices run in switch mode 0. The switch mode is controlled through DEVCPU_GCB::MISC_CFG.SW_MODE. The following table lists the mapping from the switch core port modules to the interface macros. Empty cells in the table imply that the port module number is not in use for the specific part number. When programming registers depending on port numbers, the switch core port module number must always be used. Examples of this are when accessing port module registers (PORT::) or using port masks in system or analyzer registers (SYS::, ANA::). The number next to the interface macro type (for example, “3” in cell SERDES6G, 3) indicates either the macro number or the internal PHY number that must be used when addressing the macros and PHYs for programming. Table 3 • Port Mapping from Switch Core Port Module to Interface Macros VSC7421-02 VSC7421-02 Switch Mode 0 Switch Mode 1 CuPHY, 0-7 CuPHY, 0-7 CuPHY, 0-7 8-11 CuPHY, 8-11 CuPHY, 8-11 CuPHY, 8-11 12-15 SERDES6G, 3 Switch Core Port Module 0-7 VSC7420-02 CuPHY, 0-7 16 VSC7422-02 SERDES6G, 3 SERDES6G, 3 SERDES6G, 2 17 SERDES6G, 2 18 SERDES6G, 2 19 SERDES6G, 2 20-23 SERDES6G, 2 SERDES6G, 1 24 SERDES6G, 1 25 SERDES6G, 0 SERDES6G, 1 SERDES6G, 0 SERDES6G, 0 SERDES6G, 0 VMDS-10392 VSC7420-02, VSC7421-02, and VSC7422-02 Datasheet Revision 4.3 11 Functional Descriptions Table 3 • Port Mapping from Switch Core Port Module to Interface Macros (continued) Switch Core Port Module 26 4.1.2 VSC7420-02 CPU port VSC7421-02 VSC7421-02 Switch Mode 0 Switch Mode 1 CPU port CPU port VSC7422-02 CPU port MAC This section provides information about the high-level functionality and the configuration options of the Media Access Controller (MAC) that is used in each of the port modules. The MAC supports the following speeds and duplex modes: • • PHY ports support 10/100/1000 Mbps in full-duplex mode and 10/100 Mbps in half-duplex mode. SERDES6G ports support 10/100/1000 Mbps in full-duplex mode and 10/100 Mbps in half-duplex mode. The MACs also support 2500 Mbps in full-duplex mode as follows: VSC7420-02: Port modules 24 and 25. VSC7421-02: Port modules 24 and 25 in switch mode 1. In switch mode 0, port module 25. VSC7422-02: Port module 25. The following table lists the registers associated with configuring the MAC. Table 4 • 4.1.2.1 MAC Configuration Registers Register Description Replication CLOCK_CFG Reset and speed configuration Per port MAC_ENA_CFG Enabling of Rx and Tx data paths Per port MAC_MODE_CFG Port mode configuration Per port MAC_MAXLEN_CFG Maximum length configuration Per port MAC_TAGS_CFG VLAN tag length configuration Per port MAC_ADV_CHK_CFG Type length configuration Per port MAC_IFG_CFG Interframe gap configuration Per port MAC_HDX_CFG Half-duplex configuration Per port MAC_FC_CFG Flow control configuration Per port MAC_FC_MAC_LOW_CFG LSB of SMAC used in pause frames Per port MAC_FC_MAC_HIGH_CF G MSB of SMAC used in pause frames Per port MAC_STICKY Sticky bit recordings Per port Resets There are a number of resets in the port module. All of the resets can be set and cleared simultaneously. By default, all blocks are in the reset state. With reference to register CLOCK_CFG, the resets are: • • • • • • MAC_RX_RST — Reset of the MAC receiver MAC_TX_RST — Reset of the MAC transmitter PORT_RST — Reset of the ingress and egress queues PHY_RST — Reset of the integrated PHY (only present for port modules connecting to a PHY) PCS_RX_RST — Reset of the PCS decoder (only present for port modules connecting to a SerDes macro) PCS_TX_RST — Reset of the PCS encoder (only present for port modules connecting to a SerDes macro) VMDS-10392 VSC7420-02, VSC7421-02, and VSC7422-02 Datasheet Revision 4.3 12 Functional Descriptions When changing the MAC configuration, the port must go through a reset cycle. This is done by writing register CLOCK_CFG twice. On the first write, the reset bits are set. On the second write, the reset bits are cleared. Bits that are not reset bits in CLOCK_CFG must keep their new value for both writes. For more information about resetting a port, see Port Reset Procedure, page 127. 4.1.2.2 Port Mode Configuration The MAC provides a number of handles for configuring the port mode. With reference to the MAC_MODE_CFG, MAC_IFG_CFG, and MAC_ENA_CFG registers, the handles are: • • • • Duplex mode (FDX_ENA). Half or full duplex. Data sampling (GIGA_MODE_ENA). Must be 1 in 1 Gbps and 2.5 Gbps and 0 in 10 Mbps and 100 Mbps. Enabling transmission and reception of frames (TX_ENA/RX_ENA). Clearing RX_ENA stops the reception of frames and further frames are discarded. An ongoing frame reception is interrupted. Clearing TX_ENA stops the dequeuing of frames from the egress queues, which means that frames are held back in the egress queues. An ongoing frame transmission is completed. Tx to Tx inter-frame gap (TX_IFG). For ports connecting to an internal PHY, the link speed is determined by the PHY. For other ports, the link speed is configured using CLOCK_CFG.LINK_SPEED with the following options: • Link speed (CLOCK_CFG.LINK_SPEED) 1 Gbps (125 MHz clock) Ports 24 and 25: 1 Gbps or 2.5 Gbps (125 MHz or 312.5 MHz clock). The actual clock frequency depends on the SerDes configuration. 100 Mbps (25 MHz clock) 10 Mbps (2.5 MHz clock) 4.1.2.3 Half-Duplex Mode A number of special configuration options are available for half-duplex (HDX) mode: • • • • • Seed for back-off randomizer Field MAC_HDX_CFG.SEED seeds the randomizer used by the backoff algorithm. Use MAC_HDX_CFG.SEED_LOAD to load a new seed value. Backoff after excessive collision Field MAC_HDX_CFG.WEXC_DIS determines whether the MAC backs off after an excessive collision has occurred. If set, backoff is disabled after excessive collisions. Retransmission of frame after excessive collision Field MAC_HDX_CFG.RETRY_AFTER_EXC_COL_ENA determines if the MAC retransmits frames after an excessive collision has occurred. If set, a frame is not dropped after excessive collisions, but the backoff sequence is restarted. Although this is a violation of IEEE 802.3, it is useful in non-dropping half-duplex flow control operation. Late collision timing Field MAC_HDX_CFG.LATE_COL_POS adjusts the border between a collision and a late collision in steps of 1 byte. According to IEEE 802.3, section 21.3, this border is permitted to be on data byte 56 (counting frame data from 1); that is, a frame experiencing a collision on data byte 55 is always retransmitted, but it is never retransmitted when the collision is on byte 57. For each higher LATE_COL_POS value, the border is moved 1 byte higher. Rx-to-Tx inter-frame gap The sum of MAC_IFG_CFG.RX_IFG1 and MAC_IFG_CFG.RX_IFG2 establishes the time for the Rx-to-Tx inter-frame gap. RX_IFG1 is the first part of half-duplex Rx-toTx inter-frame gap. Within RX_IFG1, this timing is restarted if carrier sense (CRS) has multiple highlow transitions (due to noise). RX_IFG2 is the second part of half-duplex Rx-to-Tx inter-frame gap. Within RX_IFG2, transitions on CRS are ignored. When enabling a port for half-duplex mode, the switch core must also be enabled (SYS::FRONT_PORT_MODE.HDX_MODE). 4.1.2.4 Frame and Type/Length Check The MAC supports frame lengths of up to 16 kilobytes. The maximum length accepted by the MAC is configurable in MAC_MACLEN_CFG.MAX_LEN. VMDS-10392 VSC7420-02, VSC7421-02, and VSC7422-02 Datasheet Revision 4.3 13 Functional Descriptions The MAC allows tagged frames to be 4 bytes longer and double-tagged frames to be 8 bytes longer than the specified maximum length (MAC_TAGS_CFG.VLAN_LEN_AWR_ENA). The MAC must be configured to look for VLAN tags. By default, EtherType 0x8100 identifies a VLAN tag. In addition, a custom EtherType can be configured in MAC_TAGS_CFG.TAG_ID. The MAC can be configured to look for none, one, or two tags (MAC_TAG_CFG.VLAN_AWR_ENA, MAC_TAG_CFG.VLAN_DBL_AWR_ENA). The type/length check (MAC_ADV_CHK_CFG.LEN_DROP_ENA) causes the MAC to discard frames with type/length errors (in-range and out-of-range errors). 4.1.2.5 Flow Control In full-duplex mode, the MAC provides independent support for transmission of pause frames and reaction to incoming pause frames. This allows for asymmetric flow control configurations. The MAC obeys received pause frames (MAC_FC_CFG.RX_FC_ENA) by pausing the egress traffic according to the timer values specified in the pause frames. The transmission of pause frames is triggered by assertion of a flow control condition in the ingress queues caused by a queue filling exceeding a watermark. For more information, see Shared Queue System, page 66. The MAC handles the formatting and transmission of the pause frame. The following configuration options are available: • • • • Transmission of pause frames (MAC_CFG_CFG.TX_FC_ENA). Pause timer value used in transmitted pause frames (MAC_FC_CFG.PAUSE_VAL_CFG). Flow control cancellation when the ingress queues de-assert the flow control condition by transmission of a pause frame with timer value 0 (MAC_FC_CFG.ZERO_PAUSE_ENA). Source MAC address used in transmitted pause frames (MAC_FC_MAC_HIGH_CFG, MAC_FC_MAC_LOW_CFG). The MAC has the option to discard incoming frames when the remote link partner is not obeying the pause frames transmitted by the MAC. The MAC discards an incoming frame if a Start-of-Frame is seen after the pause frame was transmitted. It is configurable how long reaction time is given to the link partner (MAC_FC_CFG.FC_LATENCY_CFG). The benefit of this approach is that the queue system is not risking being overloaded with frames due to a non-complying link partner. In half-duplex mode, the MAC does not react to received pause frames. If the flow control condition is asserted by the ingress queues, the industry-standard backpressure mechanism is used. Together with the ability to retransmit frames after excessive collisions (MAC_HDX_CFG.RETRY_AFTER_EXC_COL_ENA), this enables non-dropping half-duplex flow control. 4.1.2.6 Frame Aging The following table lists the registers associated with frame aging. Table 5 • Frame Aging Configuration Registers Register Description Replication SYS::FRM_AGING Frame aging time None REW::PORT_CFG.AGE_DIS Disable frame aging Per port The MAC supports frame aging where frames are discarded if a maximum transit delay through the switch is exceeded. All frames, including CPU-injected frames, are subject to aging. The transit delay is time from when a frame is fully received until that frame is scheduled for transmission through the egress MAC. The maximum allowed transit delay is configured in SYS::FRM_AGING. Frame aging can be disabled per port (REW::PORT_CFG.AGE_DIS). Discarded frames due to frame aging are counted in the c_tx_aged counter. VMDS-10392 VSC7420-02, VSC7421-02, and VSC7422-02 Datasheet Revision 4.3 14 Functional Descriptions 4.1.3 PCS This section provides information about the Physical Coding Sublayer (PCS) block, where the auto-negotiation process establishes mode of operation for a link. The PCS supports both SGMII mode and two SerDes modes, 1000BASE-X and 100BASE-FX. The PCS block is only available in port modules 12 through 25. The following table lists the registers associated with PCS. Table 6 • PCS Configuration Registers Registers Description Replication PCS1G_CFG PCS configuration Per PCS PCS1G_MODE_CFG PCS mode configuration Per PCS PCS1G_SD_CFG Signal detect configuration Per PCS PCS1G_ANEG_CFG Configuration of the PCS autonegotiation process Per PCS PCS1G_ANEG_NP_CFG Auto-negotiation next page configuration Per PCS PCS1G_LB_CFG Loop-back configuration Per PCS PCS1G_ANEG_STATUS Status signaling of the PCS auto-negotiation process Per PCS PCS1G_ANEG_NP_STATUS Status signaling of the PCS auto-negotiation next page process Per PCS PCS1G_LINK_STATUS Link status Per PCS PCS1G_LINK_DOWN_CNT Link down counter Per PCS PCS1G_STICKY Sticky bit register Per PCS The PCS is enabled in PCS1G_CFG.PCS_ENA and supports both SGMII and 1000BASE-X SERDES mode (PCS_MODE_CFG.SGMII_MODE_ENA), as well as 100-BASE-FX. For information about enabling 100BASE-FX, see 100BASE-FX, page 18. The PCS also supports the IEEE 802.3, Clause 66 unidrectional mode, where the transmission of data is independent of the state of the receive link (PCS_MODE_CFG.UNIDIR_MODE_ENA). 4.1.3.1 Auto-Negotiation Auto-negotiation is enabled in PCS1G_ANEG_CFG.ANEG_ENA. To restart the auto-negotiation process, PCS1G_ANEG_CFG.ANEG_RESTART_ONE_SHOT must be set. In SGMII mode (PCS_MODE_CFG.SGMII_MODE_ENA=1), matching the duplex mode with the link partner must be ignored (PCS1G_ANEG_CFG.SW_RESOLVE_ENA). Otherwise, the link is kept down when the auto-negotiation process fails. The advertised word for the auto-negotiation process (base page) is configured in PCS1G_ANEG_CFG.ADV_ABILITY. The next page information is configured in PCS1G_ANEG_NP_CFG.NP_TX. When the auto-negotiation state machine has exchanged base page abilities, the PCS1G_ANEG_STATUS.PAGE_RX_STICKY is asserted indicating that the link partner’s abilities were received (PCS1G_ANEG_STATUS.LP_ADV_ABILITY). If next page information is exchanged, PAGE_RX_STICKY must be cleared, next page abilities must be written to PCS1G_ANEG_NP_CFG.NP_TX, and PCS1G_ANEG_NP_CFG.NP_LOADED_ONE_SHOT must be set. When the auto-negotiation state machine has exchanged the next page abilities, the PCS1G_ANEG_STATUS.PAGE_RX_STICKY is asserted again, indicating that the link partner’s next VMDS-10392 VSC7420-02, VSC7421-02, and VSC7422-02 Datasheet Revision 4.3 15 Functional Descriptions page abilities were received (PCS1G_ANEG_STATUS.LP_NP_RX). Additional exchanges of next page information are possible using the same procedure. After the last next page is received, the auto-negotiation state machine enters the IDLE_DETECT state and the PCS1G_ANEG_STATUS.PR bit is set indicating that ability information exchange (base page and possible next pages) is finished and software can now resolve priority. Appropriate actions, such as Rx or Tx reset, or auto-negotiation restart, can then be taken, based on the negotiated abilities. The LINK_OK state is reached one link timer period later. When the auto-negotiation process reaches the LINK_OK state, PCS1G_ANEG_STATUS.ANEG_COMPLETE is asserted. 4.1.3.2 Link Surveillance The current link status can be observed through PCS1G_LINK_STATUS.LINK_STATUS. The LINK_STATUS is defined as either the PCS synchronization state or as bit 15 of PCS1G_ANEG_STATUS.LP_ADV_ABILTY, which carries information about the link status of the attached PHY in SGMII mode. Link down is defined as the auto-negotiation state machine being in neither the AN_DISABLE_LINK_OK state nor the LINK_OK state for one link timer period. If a link down event occurs, PCS1G_STICKY.LINK_DOWN_STICKY is set, and PCS1G_LINK_DOWN_CNT is incremented. In SGMII mode, the link timer period is 1.6 ms; in SerDes mode, the link timer period is 10 ms. The PCS synchronization state can be observed through PCS1G_LINK_STATUS.SYNC_STATUS. Synchronization is lost when the PCS is not able to recover and decode data received from the attached serial link. 4.1.3.3 Signal Detect The PCS can be enabled to react to loss of signal through signal detect (PCS1G_SD_CFG.SD_ENA). At loss of signal, the PCS Rx state machine is restarted, and frame reception stops. If signal detect is disabled, no action is taken upon loss of signal. The polarity of signal detect is configurable in PCS1G_SD_CFG.SD_POL. The source of signal detect is selected in PCS1G_SD_CFG.SD_SEL to either the SerDes PMA or the PMD receiver. If the SerDes PMA is used as source, the SerDes macro provides the signal detect. If the PMD receiver is used as source, signal detect is sampled externally through one of the GPIO pins on the devices. For more information about the configuration of the GPIOs and signal detect, see GPIO Controller, page 114. PCS1G_LINK_STATUS.SIGNAL_DETECT contains the current value of the signal detect input. 4.1.3.4 Tx Loopback For debug purposes, the Tx data path in the PCS can be looped back into the Rx data path. This feature is enabled through PCS1G_LB_CFG.TBI_HOST_LB_ENA. 4.1.3.5 Test Patterns The following table lists the registers associated with configuring test patterns. Table 7 • Test Pattern Registers Registers Description Replication PCS1G_TSTPAT_MODE_CFG Test pattern configuration Per PSC PCS1G_TSTPAT_MODE_STATU Test pattern status S Per PCS PCS1G_TSTPAT_MODE_CFG.JTP_SEL overwrites normal operation of the PCS and enables generation of jitter test patterns for debugging. The jitter test patterns are defined in IEEE 802.3, Annex 36A, and the following patterns are supported: • • High frequency test pattern Low frequency test pattern VMDS-10392 VSC7420-02, VSC7421-02, and VSC7422-02 Datasheet Revision 4.3 16 Functional Descriptions • • • Mixed frequency test pattern Continuous random test pattern with long frames Continuous random test pattern with short frames PCS1G_TSTPAT_MODE_STATUS register holds information about error and lock conditions while running the jitter test patterns. 4.1.3.6 Low Power Idle The following table lists the registers associated with low power idle (LPI). Table 8 • Low Power Idle Registers Registers Description Replication PCS1G_LPI_CFG Configuration of the PCS Low Power Idle process Per PSC PCS1G_LPI_WAKE_ERROR_CNT Error counter Per PCS PCS1G_LPI_STATUS Low Power Idle status Per PCS The PCS supports Energy Efficient Ethernet (EEE) as defined by IEEE 802.3az. The PCS converts Low Power Idle (LPI) encoding between the MAC and the serial interface transparently. In addition, the PCS provides control signals allowing to stop data transmission in the SerDes macro. During low power idles the serial transmitter in the SerDes macro can be powered down, only interrupted periodically while transmitting refresh information, which allows the receiver to notice that the link is still up but in power down mode. When a SERDES6G macro operating in QSGMII mode is enabled for powering down of the serial transmitter during low power idles, one of the four PCSs connected to the macro must be selected master (PCS1G_LPI_CFG.QSGMII_MS_SEL). The master PCS sends refresh information to the attached receivers periodically. Note that the serial transmitter can only power down when all four attached ports are in low power idle. For more information about powering down the serial transmitter in the SerDes macros, see SERDES6G, page 18. It is not necessary to enable the PCS for EEE, because it is controlled indirectly by the shared queue system. It is possible, however, to manually force the PCS into the low power idle mode through PCS1G_LPI_CFG.TX_ASSERT_LPIDLE. During LPI mode, the PCS constantly encodes low power idle with periodical refreshes. For more information about EEE, see Energy Efficient Ethernet, page 73. The current low power idle state can be observed through PCS1G_LPI_STATUS for both receiver and transmitter: • • RX_LPI_MODE: Set if the receiver is in low power idle mode. RX_QUIET: Set if the receiver is in the Quiet state of the low power idle mode. If cleared while RX_LPI_MODE is set, the receiver is in the refresh state of the low power idle mode. The same is observable for the transmitter through TX_LPI_MODE and TX_QUIET. If an LPI symbol is received, the RX_LPI_EVENT_STICKY bit is set, and if an LPI symbol is transmitted, the TX_LPI_EVENT_STICKY bit is set. These events are sticky. The PCS1G_LPI_WAKE_ERROR_CNT wake-up error counter increments when the receiver detects a signal and the PCS is not synchronized. This can happen when the transmitter fails to observe the wakeup time or if the receiver is not able to synchronize in time. VMDS-10392 VSC7420-02, VSC7421-02, and VSC7422-02 Datasheet Revision 4.3 17 Functional Descriptions 4.1.3.7 100BASE-FX The following table lists the registers associated with 100BASE-FX configuration. Table 9 • 100BASE-FX Registers Registers Description Replication PCS_FX100_CFG Configuration of the PCS 100BASE-FX mode Per PSC PCS_FX100_STATUS Status of the PCS 100BASE-FX mode Per PCS The PCS supports a 100BASE-FX mode in addition to the SGMII and 1000BASE-X SerDes modes. The 100BASE-FX mode uses 4-bit/5-bit coding as specified in IEEE 802.3 Clause 24 for fiber connections. The 100BASE-FX mode is enabled through PCS_FX100_CFG.PCS_ENA, which masks out all PCS1G related registers. The following options are available: Far-End Fault facility In 100BASE-FX, the PCS supports the optional Far-End Fault facility. Both FarEnd Fault generation (PCS_FX100_CFG.FEF_GEN_ENA) and Far-End Fault Detection (PCS_FX100_CFG.FEF_CHK_ENA) are supported. An Far-End Fault incident is recorded in PCS_FX100_STATUS.FEF_FOUND. Signal Detect 100BASE-FX has a similar signal detect scheme to the SGMII and SerDes modes. For 100BASE-FX, PCS_FX100_CFG.SD_ENA enables signal detect, PCS_FX100_CFG.SD_POL controls the polarity, and PCS_FX100_CFG.SD_SEL selects the input source. The current status of the signal detect input can be observed through PCS_FX100_STATUS.SIGNAL_DETECT. For more information about signal detect, see Signal Detect, page 16. Link Surveillance The PCS synchronization status can be observed through PCS_FX100_STATUS.SYNC_STATUS. When synchronization is lost, the link breaks and PCS_FX100_STATUS.SYNC_LOST_STICKY is set. The PCS continuously tries to recover the link. Unidirectional mode 100BASE-FX has a similar unidirectional mode as SGMII and SerDes modes. PCS_FX100_CFG.UNIDIR_MODE_ENA enables unidirectional mode. 4.2 SERDES6G The SERDES6G is a high-speed SerDes interface that operates at 100 Mbps (100BASE-FX), 1 Gbps (SGMII/SerDes), 2.5 Gbps (SGMII), and 4 Gbps (QSGMII). The 100BASE-FX mode is supported by oversampling. The following table lists the registers associated with SERDES6G. Table 10 • SERDES6G Registers Registers Description Replication SERDES6G_COMMON_CFG Common configuration Per SerDes SERDES6G_DES_CFG Deserializer configuration Per SerDes SERDES6G_IB_CFG Input buffer configuration Per SerDes SERDES6G_IB_CFG1 Input buffer configuration Per SerDes SERDES6G_SER_CFG Serializer configuration Per SerDes SERDES6G_OB_CFG Output buffer configuration Per SerDes SERDES6G_OB_CFG1 Output buffer configuration Per SerDes SERDES6G_PLL_CFG PLL configuration Per SerDes SERDES6G_MISC_CFG Miscellaneous configuration Per SerDes VMDS-10392 VSC7420-02, VSC7421-02, and VSC7422-02 Datasheet Revision 4.3 18 Functional Descriptions For increased performance in specific application environments, SERDES6G supports the following: • • • • • • 4.2.1 Baud rate support, configurable from 1 Gbps to 4 G, for quarter, half, and full rate modes Programmable loop bandwidth and phase regulation for the deserializer Configurable input buffer features such as signal detect/loss of signal (LOS) options Configurable output buffer features, such as programmable de-emphasis, amplitude drive levels, and slew rate control Synchronous Ethernet support Loopbacks for system test SERDES6G Basic Configuration The SERDES6G is enabled in SERDES6G_COMMON_CFG.ENA_LANE. By default, the SERDES6G is held in reset and must be released before the interface is active. This is done through SERDES6G_COMMON_CFG.SYS_RST and SERDES6G_MISC_CFG.LANE_RST. 4.2.1.1 SERDES6G Parallel Interface Configuration The SERDES6 block includes a parallel data interface, which can operate in two different modes. It must be set according to the mode of operation (SERDES6G_COMMON_CFG.IF_MODE). For 100 Mbps, 1 Gbps, and 2.5 Gbps operation, the 10-bit mode is used, and for 4 Gbps operation (QSGMII), the 20-bit mode is used. 4.2.1.2 SERDES6G PLL Frequency Configuration To operate the SERDES6G block at the correct frequency, configure the internal macro as follows. The PLL calibration is enabled through SERDES6G_PLL_CFG.PLL_FSM_ENA. 1. 2. 3. Configure SERDES6G_PLL_CFG.PLL_FSM_CTRL_DATA in accordance with data rates listed in the following two tables. Set SYS_RST = 0 (active) and PLL_FSM_ENA = 0 (inactive). Set SYS_RST = 1 (deactive) and PLL_FSM_ENA = 1 (active). Table 11 • 4.2.1.3 PLL Configuration Mode SERDES6G_PLL_CFG.PLL_FSM_CTRL_DATA SGMII/SerDes, 1 Gbps data 60 SGMII, 2.5 Gbps data 48 QSGMII, 4 Gbps data 120 SERDES6G Frequency Configuration The following table lists the range of data rates that are supported by SERDES6G. Table 12 • 4.2.2 SERDES6 Frequency Configuration Registers Configuration SGMII/SerDes 1 Gbps SGMII 2.5 Gbps QSGMII 4 Gbps SERDES6G_PLL_CFG.PLL_ROT_FRQ 0 1 0 SERDES6G_PLL_CFG.PLL_ROT_DIR 1 0 0 SERDES6G_PLL_CFG.PLL_ENA_ROT 0 1 0 SERDES6G_COMMON_CFG.QRATE 1 0 0 SERDES6G_COMMON_CFG.HRATE 0 1 0 SERDES6G Loopback Modes The SERDES6G interface supports two different loopback modes for testing and debugging data paths: equipment loopback and facility loopback. VMDS-10392 VSC7420-02, VSC7421-02, and VSC7422-02 Datasheet Revision 4.3 19 Functional Descriptions Equipment loopback (SERDES6G_COMMON_CFG.ENA_ELOOP) Data is looped back from serializer output to the deserializer input, and the receive clock is recovered. The equipment loopback includes all transmit and receive functions, except for the input and output buffers. The Tx data can still be observed on the output. Facility loopback (SERDES6G_COMMON_CFG.ENA_FLOOP) The clock and parallel data output from deserializer are looped back to the serializer interface. Incoming serial data passes through the input buffer, the CDR, the deserializer, back to the serializer, and finally out through the output buffer. Only one of the loopbacks can be enabled at the same time. The following illustration shows the loopback paths for the SERDESG6. Figure 4 • SERDES Loopback Rx Path Rx (P/N) 20 ESD Input Buffer Deserializer Equipment Loop Facility Loop Equipment Loop ESD Output Buffer Equipment Loop Tx (P/N) 20 Serializer Tx Path 4.2.3 SERDES6G Deserializer Configuration The SERDES6G block includes digital control logic that interacts with the analog modules within the block and compensates for the frequency offset between the received data and the internal high-speed reference clock. To gain high jitter performance, the phase regulation is a PI-type regulator, whose proportional (P) and integrative (I) characteristics can be independently configured. The integrative part of the phase regulation loop is configured in SERDES6G_DES_CFG.DES_PHS_CTRL. The limits of the integrator are programmable, allowing different settings for the integrative regulation while guaranteeing that the proportional part still is stronger than the integrative part. Integrative regulation compensates frequency modulation from DC up to cut-off frequency. Frequencies above the cut-off frequency are compensated by the proportional part. The DES_BW_HYST register field controls the time constant of the integrator independently of the proportional regulator. The range of DES_BW_HYST is programmable as follows: • • • Full rate mode = 3 to 7 Half-rate mode = 2 to 7 Quarter-rate mode = 1 to 7 The lower the configuration setting, the smaller the time-constant of the integrative regulation. For normal operation, configure DES_BW_HYST to 5. The cut-off-frequency is calculated to: VMDS-10392 VSC7420-02, VSC7421-02, and VSC7422-02 Datasheet Revision 4.3 20 Functional Descriptions fco = 1/(2 × PI × 128 × PLL period × 32 × 2^(DES_BW_HYST + 1 – DES_BW_ANA)) PLL period = 1/(n × data rate) where, n = 1 (full rate mode), 2 (half-mode) or 4 (quarter-rate mode) The integrative regulator can compensate a static frequency offset within the programmed limits down to a remaining frequency error of below 4 ppm. In steady state, the integrator toggles between two values around the exact value, and the proportional part of the phase regulation takes care of the remaining phase error. After a device reset, the phase regulation may be 180° out of phase compared to the incoming data, resulting in a deadlock condition at the sampling stage of the deserializer. To prevent this situation, the SERDES6G provides a 180° deadlock protection mechanism (SERDES6G_DES_CFG.DES_MBTR_CTRL). If the deadlock protection mechanism is enabled, a small frequency offset is applied to the phase regulation loop. The offset is sufficient to move the sampling point out of the 180° deadlock region, while at the same time, small enough to allow the regulation loop to compensate when the sample point is within the data eye. The loop bandwidth for the proportional part of the phase regulation loop is controlled by configuring SERDES6G_DES_CFG.DES_BW_ANA. The fastest loop bandwidth setting (lowest configuration value) results in a loop bandwidth that is equal to the maximum frequency offset compensation capability. For improved jitter performance, use a setting with sufficient margin to track the expected frequency offset rather than using the maximum frequency offset. For example, if a 100 ppm offset is expected, use a setting that is four times higher than the offset. For more information about possible bandwidth selections, see Table 357, page 267. The following table provides the limits for the frequency offset compensation. The values are theoretical limits for input signals without jitter, because the actual frequency offset compensation capability is dependent on the toggle rate of the input data and the input jitter. Note that only applicable configuration values are listed. HRATE and QRATE are the configuration settings of SERDES6G_COMMON_CFG.HRATE and SERDES6G_COMMON_CFG.QRATE. Table 13 • SERDES6G Loop Bandwidth DES_BW_ANA Limits when HRATE = 0 QRATE = 0 Limits when HRATE = 1 QRATE = 0 2 1953 ppm 3 4.2.4 Limits when HRATE = 0 QRATE = 1 1953 ppm 977 ppm 4 1953 ppm 977 ppm 488 ppm 5 977 ppm 488 ppm 244 ppm 6 488 ppm 244 ppm 122 ppm 7 244 ppm 122 ppm 61 ppm SERDES6G Serializer Configuration The serializer provides the ability to align the phase of the internal clock and data to a selected source (SERDES6G_SER_CFG.SER_ENALI). The phase align logic is used when SERDES6G operates in the facility loopback mode. 4.2.5 SERDES6G Input Buffer Configuration The SERDES6G input buffer supports configuration options for: • • Automatic input voltage offset compensation Loss of signal detection The input buffer is normally AC-coupled and therefore the common-mode termination is switched off (SERDES6G_IB_CFG1.IB_CTERM_ENA). In order to support type-2 loads (DC-coupling at 1.0 V VMDS-10392 VSC7420-02, VSC7421-02, and VSC7422-02 Datasheet Revision 4.3 21 Functional Descriptions termination voltage) according to the OIF CEI specifications, common-mode termination must be enabled. The sensitivity of the level detect circuit can be adapted to the input signal’s characteristics (amplitude and noise). The threshold value for the level detect circuit is set in SERDES6G_IB_CFG.IB_VBCOM. The default value is suitable for normal operation. When the SerDes interface operates in 100BASE-FX mode, the input buffer of the SERDES6G macro must also be configured for 100BASE-FX (SERDES6G_IB_CFG.IB_FX100_ENA). During test or reception of low data rate signals (for example, 100BASE-FX), the DC-offset compensation must be disabled. For all other modes, the DC-offset compensation must be enabled for optimized performance. DC-offset compensation is controlled by SERDES6G_IB_CFG1.IB_ENA_OFFSAC and SERDES6G_IB_CFG1.IB_ENA_OFFSDC. 4.2.6 SERDES6G Output Buffer Configuration The SERDEDS6G output buffer supports the following configuration options: • • • • • Amplitude control De-emphasis and output polarity inversion Slew rate control Skew adjustment Idle mode The maximum output amplitude of the output buffer depends on the output buffer’s supply voltage. For interface standards requiring higher output amplitudes (backplane application or interface to optical modules, for example), the output buffer can be supplied from a 1.2 V instead of a 1.0 V supply. By default, the output buffer is configured for 1.2 V mode, because enabling the 1.0 V mode when supplied from 1.2 V must be avoided. The supply mode is configured by SERDES6G_OB_CFG.OB_ENA1V_MODE. The output buffer supports a four-tap pre-emphasis realized by one pre-cursor, the center tap, and two post cursors. The pre-cursor coefficient, C0, is configured by SERDES6G_SER_CFG.OB_PREC. C0 is a 5-bit value, with the most significant bit defining the polarity. The lower 4-bit value is hereby defined as B0. The first post-cursor coefficient, C2, is configured by SERDES6G_OB_CFG.OB_POST0. C2 is a 6bit value, with the most significant bit defining the polarity. The lower 5-bit value is hereby defined as B2. The second post-cursor coefficient, C3, is configured by SERDES6G_SER_CFG.OB_POST1. C3 is 5-bit value, with the most significant bit defining the polarity. The lower 4-bit value is hereby defined as B3. The center-tap coefficient, C1, is a 6-bit value. Its polarity can be programmed by SERDES6G_OB_CFG.OB_POL, which is defined as p1. For normal operation SERDES6G_OB_CFG.OB_POL must be set to 1. The value of the 6 bits forming C1 is calculated by the following equation. Equation 1: C1: (64 – (B0 + B2 + B3)) × p1 The output amplitude is programmed by SERDES6G_OB_CFG1.OB_LEV, which is a 6-bit value. This value is internally increased by 64 and defines the amplitude coefficient K. The range of K is therefore 64 to 127. The differential peak-peak output swing is given by 8.75 mV × K. The maximum peak-peak output swing depends on the data stream and can be calculated to: Equation 2: H(Z) = 4.375 mVpp × K × (C0 × z1 + C1 × z0 + C2 × z–1 + C3 × z–2)/64 with zn denoting the current bits of the data pattern defining the amplitude of Z. The output amplitude also depends on the output buffer’s supply voltage. For more information about the dependencies between the maximum achievable output amplitude and the output buffer’s supply voltage, see Table 574, page 419. VMDS-10392 VSC7420-02, VSC7421-02, and VSC7422-02 Datasheet Revision 4.3 22 Functional Descriptions The configuration bits are summarized in the following table. Table 14 • De-Emphasis and Amplitude Configuration Configuration Value Description OB_PREC Signed 5-bit value Pre-cursor setting C0 Range is –15 to 15 OB_POST0 Signed 6-bit value First post-cursor setting C2 Range is –31 to 31 OB_POST1 Signed 5-bit value Second post-cursor setting C3 Range is –15 to 15 OB_LEV Unsigned 6-bit value Amplitude coefficient, K = OB_LEV + 64 Range is 0 to 63 OB_POL 0 1 Non-inverting mode Inverting mode The output buffer provides additional options to configure its behavior. These options are: • • • 4.2.7 Idle mode: Enabling idle mode (SERDES6G_OB_CFG.OB_IDLE) results in a remaining voltage of less than 30 mV at the buffers differential outputs. Slew Rate: Slew rate can be controlled by two configuration settings. SERDES6G_OB_CFG.OB_SR_H provides coarse adjustments whereas SERDES6G_OB_CFG.OB_SR provides fine adjustments. Skew control: In 1 Gbps SGMII mode, skew adjustment is controlled by SERDES6G_OB_CFG1.OB_ENA_CAS. Skew control is not applicable to other modes. SERDES6G Clock and Data Recovery (CDR) in 100BASE-FX To enable clock and data recovery when operating SERDES6G in 100BASE-FX mode, set the following register fields: • • • 4.2.8 SERDES6G_MISC_CFG.DES_100FX_CPMD_ENA = 1 SERDES6G_IB_CFG.IB_FX100_ENA = 1 SERDES6G_DES_CFG.DES_CPMD_SEL = 2 SERDES6G Energy Efficient Ethernet The SERDES6G block supports Energy Efficient Ethernet as defined in IEEE 802.3az. To enable the low power modes, set SERDES6G_MISC_CFG.TX_LPI_MODE_ENA and SERDES6G_MISC_CFG.RX_LPI_MODE_ENA. At this point, the attached PCS takes full control over the high-speed output and input buffer activity. 4.2.9 SERDES6G Data Inversion The data streams in the transmit and the receive direction can be inverted using SERDES6G_MISC_CFG.TX_DATA_INV_ENA and SERDES6G_MISC_CFG.RX_DATA_INV_ENA. This effectively allows for swapping the P and N lines of the high-speed serial link. 4.2.10 SERDES6G Signal Detection Enhancements Signal detect information from the SERDES6G macro is normally directly passed to the attached PCS. It is possible to enable a hysteresis such that the signal detect condition must be active or inactive for a certain time before it is signaled to the attached PCS. The signal detect assertion time (the time signal detect must be active before the information is passed to a PCS) is programmable in SERDES6G_DIG_CFG.SIGDET_AST. The signal detect de-assertion time (the time signal detect must be inactive before the information is passed to a PCS) is programmable in SERDES6G_DIG_CFG.SIGDET_DST. VMDS-10392 VSC7420-02, VSC7421-02, and VSC7422-02 Datasheet Revision 4.3 23 Functional Descriptions 4.2.11 SERDES6G High-Speed I/O Configuration Bus The high-speed SerDes macros are configured using the high-speed I/O configuration bus (MCB), which is a serial bus connecting the configuration register set with all the SerDes macros. The HSIO::MCB_SERDES6G_ADDR_CFG register is used for SERDES6G macros. The configuration busses are used for both writing to and reading from the macros. The SERDES6G macros are programmed as follows: • • • • Program the configuration registers for the SERDES6G macro. For more information about configuration options, see SERDES6G, page 18. Transfer the configuration from the configuration registers to one or more SerDes macros by writing the address of the macro (MCB_SERDES6G_ADDR_CFG.SERDES6G_ADDR) and initiating the write access (MCB_SERDES6G_ADDR_CFG.SERDES6G_WR_ONE_SHOT). The SerDes macro address is a mask with one bit per macro so that one or more macros can be programmed at the same time. The MCB_SERDES6G_ADDR_CFG.SERDES6G_WR_ONE_SHOT are automatically cleared when the writing is done. The configuration and status information in the SERDES6G macros can be read as follows: • • • 4.3 Transfer the configuration and status from one or more SerDes macros to the configuration registers by writing the address of the macro (MCB_SERDES6G_ADDR_CFG.SERDES6G_ADDR) and initiating the read access (MCB_SERDES6G_ADDR_CFG.SERDES6G_RD_ONE_SHOT). The SerDes macro address is a mask with one bit per macro so that configuration and status information from one or more macros can be read at the same time. When reading from more than one macro, the results from each macro are OR’ed together. The MCB_SERDES6G_ADDR_CFG.SERDES6G_RD_ONE_SHOT are automatically cleared when the reading is done. Copper Transceivers The VSC7420-02, VSC7421-02, and VSC7422-02 devices include low-power Gigabit Ethernet transceivers. The devices include the following number of transceivers: • • VSC7420-02 includes 8 transceivers, numbered 0 through 7 VSC7421-02 and VSC7422-02 include 12 transceivers, numbered 0 through 11 This section describes the high-level functionality and operation of the built-in transceivers. The integration is kept as close to multi-chip PHY and switch designs as possible. This allows a fast path for software already running in a similar distributed design while still benefiting from the cost savings provided by the integration. 4.3.1 Register Access The registers of the integrated transceivers are not placed in the memory map of the switch, but are attached instead to the built-in MII management controller 0 of the devices. As a result, PHY registers are accessed indirectly through the switch registers. For more information, see MII Management Controller, page 112. In addition to providing the IEEE 802.3 specified 16 MII Standard Set registers, the PHYs contain an extended set of registers that provide additional functionality. The devices support the following types of registers: • • • • IEEE Clause 22 device registers with addresses from 0 to 31 Two pages of extended registers with addresses from 16E1 through 30E1 and 16E2 through 30E2 General-purpose registers with addresses from 0G to 30G IEEE Clause 45 devices registers accessible through the Clause 22 registers 13 and 14 to support IEEE 802.3az Energy Efficient Ethernet registers The memory mapping is controlled through PHY_MEMORY_PAGE_ACCESS::PAGE_ACCESS_CFG. The following illustration shows the relationship between the device registers and their address spaces. VMDS-10392 VSC7420-02, VSC7421-02, and VSC7422-02 Datasheet Revision 4.3 24 Functional Descriptions Register Space Layout Figure 5 • 0 1 2 3 . . . 13 14 15 16 17 18 19 . . . 4.3.1.1 Clause 45 Registers IEEE 802.3 Standard Registers 15G Main Registers 16E1 17E1 18E1 19E1 . . . Extended Registers 1 30E1 30 31 0G 1G 2G 3G . . . 0x0000 16E2 17E2 18E2 19E2 . . . Extended Registers 2 30E2 0x0001 16G 17G 18G 19G . . . General-Purpose Registers 30G 0x0002 0x0010 Broadcast Write The PHYs can be configured to accept MII PHY register write operations regardless of the destination address of these writes. This is enabled in PHY_CTRL_STAT_EXT::BROADCAST_WRITE_ENA. This enabling allows similar configurations to be sent quickly to multiple PHYs without having to do repeated MII PHY write operations. This feature applies only to writes; MII PHY register read operations are still interpreted with “correct” address. 4.3.1.2 Register Reset The PHY can be reset through software. This is enabled in PHY_CTRL::SOFTWARE_RESET_ENA. Enabling this field initiates a software reset of the PHY. Fields that are not described as sticky are returned to their default values. Fields that are described as sticky are only returned to defaults if stickyreset is disabled through PHY_CTRL_STAT_EXT::STICKY_RESET_ENA. Otherwise, they retain their values from prior to the software reset. A hardware reset always brings all PHY registers back to their default values. 4.3.2 Cat5 Twisted Pair Media Interface The twisted pair interfaces are compliant with IEEE 802.3-2008 and IEEE 802.3az for Energy Efficient Ethernet. 4.3.2.1 Voltage-Mode Line Driver Unlike many other gigabit PHYs, this PHY uses a patented voltage-mode line driver that allows it to fully integrate the series termination resistors (required to connect the PHY’s Cat5 interface to an external 1:1 transformer). Also, the interface does not require placement of an external voltage on the center tap of the magnetic. The following illustration shows the connections. VMDS-10392 VSC7420-02, VSC7421-02, and VSC7422-02 Datasheet Revision 4.3 25 Functional Descriptions Figure 6 • Cat5 Media Interface PHY Port_n RJ-45 Transformer TXVPA_n 1 A+ TXVNA_n 2 A– TXVPB_n 3 B+ 6 B– 4 C+ 5 C– 7 D+ 8 D– 0.1 µF 0.1 µF TXVNB_n TXVPC_n 0.1 µF TXVNC_n TXVPD_n 0.1 µF TXVND_n 75 Ω 75 Ω 1000 pF, 2 kV 75 Ω 75 Ω 4.3.2.2 Cat5 Autonegotiation and Parallel Detection The integrated transceivers support twisted pair autonegotiation as defined by clause 28 of the IEEE 802.3-2008. The autonegotiation process evaluates the advertised capabilities of the local PHY and its link partner to determine the best possible operating mode. In particular, auto-negotiation can determine speed, duplex configuration, and master or slave operating modes for 1000BASE-TX. Autonegotiation also allow the devices to communicate with the link partner (through the optional “next pages”) to set attributes that may not otherwise be defined by the IEEE standard. If the Cat5 link partner does not support auto negotiation, the devices automatically use parallel detection to select the appropriate link speed. Auto-negotiation can be disabled by clearing PHY_CTRL.AUTONEG_ENA. If auto-negotiation is disabled, the state of the SPEED_SEL_MSB_CFG, SPEED_SEL_LSB_CFG, and DUPLEX_MODE_CFG fields in the PHY_CTRL register determine the device operating speed and duplex mode. Note that while 10BASE-T and 100BASE-T do not require auto-negotiation, clause 40 defines that 1000BASE-T require auto-negotiation. 4.3.2.3 1000BASE-T Forced Mode Support The integrated transceivers provides support for a 1000BASE-T forced test mode. In this mode, the PHY can be forced into 1000BASE-T mode and does not require manual setting of master/slave at the two ends of the link. This mode is only for test purposes. Do not use in normal operation. To configure a PHY in this mode, set PHY_EEE_CTRL.FORCE_1000BT_ENA = 1, with PHY_CTRL.SPEED_SEL_LSB_CFG = 1 and PHY_CTRL.SPEED_SEL_LSB_CFG = 0. 4.3.2.4 Automatic Crossover and Polarity Detection For trouble-free configuration and management of Ethernet links, the integrated transceivers include a robust automatic crossover detection feature for all three speeds on the twisted-pair interface (10BASE- VMDS-10392 VSC7420-02, VSC7421-02, and VSC7422-02 Datasheet Revision 4.3 26 Functional Descriptions T, 100BASE-T, and 1000BASE T). Known as HP Auto-MDIX, the function is fully compliant with clause 40 of the IEEE 802.3-2002. Additionally, the devices detect and correct polarity errors on all MDI pairs—a useful capability that exceeds the requirements of the standard. Both HP Auto-MDIX detection and polarity correction are enabled in the device by default. You can change the default settings using fields POL_INV_DIS and PAIR_SWAP_DIS in the PHY_BYPASS_CTRL register. Status bits for each of these functions are located in register PHY_AUX_CTRL_STAT. The integrated transceivers can be configured to perform HP Auto-MDIX, even when auto-negotiation is disabled (PHY_CTRL.AUTONEG_ENA = 0) and the link is forced into 10/100 speeds. To enable the HP Auto-MDIX feature, set PHY_BYPASS_CTRL.FORCED_SPEED_AUTO_MDIX_DIS to 0. The HP Auto-MDIX algorithm successfully detects, corrects, and operates with any of the MDI wiring pair combinations listed in the following table. Table 15 • Supported MDI Pair Combinations RJ-45 Pin Pairings 4.3.2.5 1, 2 3, 6 4, 5 7, 8 Mode A B C D Normal MDI B A D C Normal MDI-X A B D C Normal MDI with pair swap on C and D pair B A C D Normal MDI-X with pair swap on C and D pair Manual MDI/MDI-X Setting As an alternative to HP Auto-MDIX detection, the PHY can be forced to be MDI or MDI-X using PHY_EXT_MODE_CTRL.FORCE_MDI_CROSSOVER_ENA. Setting this field to 10 forces MDI, and setting 11 forces MDI-X. Leaving the bits 00 enables the MDI/MDI-X setting to be based on FORCED_SPEED_AUTO_MDIX_DIS and PAIR_SWAP_DIS in the register PHY_BYPASS_CTRL. 4.3.2.6 Link Speed Downshift For operation in cabling environments that are incompatible with 1000BASE-T, the devices provide an automatic link speed “downshift” option. When enabled, the devices automatically change their 1000BASE-T auto-negotiation advertisement to the next slower speed after a set number of failed attempts at 1000BASE-T. No reset is required to exit this state if a subsequent link partner with 1000BASE-T support is connected. This is useful in setting up in networks using older cable installations that may include only pairs A and B and not pairs C and D. Link speed downshifting is configured and monitored using SPEED_DOWNSHIFT_STAT, SPEED_DOWNSHIFT_CFG, and SPEED_DOWNSHIFT_ENA in the register PHY_CTRL_EXT3. 4.3.2.7 Energy Efficient Ethernet The integrated transceivers support IEEE 802.3az Energy Efficient Ethernet (EEE) currently in development. This new standard provides a method for reducing power consumption on an Ethernet link during times of low use. It uses Low Power Idles (LPI) to achieve this objective. VMDS-10392 VSC7420-02, VSC7421-02, and VSC7422-02 Datasheet Revision 4.3 27 Functional Descriptions Figure 7 • Energy Efficient Ethernet Using LPI, the usage model for the link is to transmit data as fast as possible and then return to a low power idle state. Energy is saved on the link by cycling between active and low power idle states. Power is reduced during LPI by turning off unused circuits and, using this method, energy use scales with bandwidth utilization. The transceivers use LPI to optimize power dissipation in 100BASE-TX and 1000BASE-T operation. In addition, IEEE 802.3az defines a 10BASE-Te mode that reduces transmit signal amplitude from 5 V to approximately 3.3 V, peak-to-peak. This mode reduces power consumption in 10 Mbps link speed and can fully interoperate with legacy 10BASE-T compliant PHYs over 100 m Cat5 cable or better. To configure the transceivers in 10BASE-Te mode, set PHY_EEE_CTRL.EEE_LPI_RX_100BTX_DIS to 1 for each port. Additional Energy Efficient Ethernet features are controlled through Clause 45 registers as defined in Clause 45 registers to Support Energy Efficient Ethernet. 4.3.3 LED Interface The devices also have a LED controller interface by means of the serial GPIO pins, GPIO_[3:0]. For more information, see Serial GPIO Controller, page 115. 4.3.4 Ethernet Inline Powered Devices The integrated transceivers can detect legacy inline powered devices in Ethernet network applications. The inline powered detection capability can be part of a system that allows for IP-phone and other devices, such as wireless access points, to receive power directly from their Ethernet cable, similar to office digital phones receiving power from a Private Branch Exchange (PBX) office switch over the telephone cabling. This can eliminate the need of an external power supply for an IP-phone. It also enables the inline powered device to remain active during a power outage (assuming the Ethernet switch is connected to an uninterrupted power supply, battery, back-up power generator, or some other uninterruptable power source). The following illustration shows an example of this type of application. VMDS-10392 VSC7420-02, VSC7421-02, and VSC7422-02 Datasheet Revision 4.3 28 Functional Descriptions Figure 8 • Inline Powered Ethernet Switch Control Gigabit Switch / PHY PHY_port0 PHY_port1 PHY_portn Transformer Transformer Transformer RJ-45 I/F RJ-45 I/F RJ-45 I/F Link Partner Link Partner Inline, Power-Over-Ethernet (PoE) Power Supply Cat5 Link Partner The following procedure describes the process that an Ethernet switch must perform to process inline power requests made by a link partner (LP); that is, in turn, capable of receiving inline power. 1. Enable the inline powered device detection mode on each transceiver using its serial management interface. Set PHY_CTRL_EXT4.INLINE_POW_DET_ENA to 1. 2. Ensure that the Auto-Negotiation Enable bit (register 0.12) is also set to 1. In the application, the devices send a special Fast Link Pulse (FLP) signal to the LP. Reading PHY_CTRL_EXT4.INLINE_POW_DET_STAT returns 00 during the search for devices that require Power-over-Ethernet (PoE). 3. The transceiver monitors its inputs for the FLP signal looped back by the LP. An LP capable of receiving PoE loops back the FLP pulses when the LP is in a powered-down state. This is reported when PHY_CTRL_EXT4.INLINE_POW_DET_STAT reads back 01. If an LP device does not loop back the FLP after a specific time, PHY_CTRL_EXT4.INLINE_POW_DET_STAT automatically resets to 10. 4. If the transceiver reports that the LP needs PoE, the Ethernet switch must enable inline power on this port, externally of the PHY. 5. The PHY automatically disables inline powered device detection if PHY_CTRL_EXT4.INLINE_POW_DET_STAT automatically resets to 10, and then automatically changes to its normal auto-negotiation process. A link is then auto-negotiated and established when the link status bit is set (PHY_STAT.LINK_STAT is set to 1). 6. In the event of a link failure (indicated when PHY_STAT.LINK_STAT reads 0), the inline power must be disabled to the inline powered device external to the PHY. The transceiver disables its normal auto-negotiation process and re-enables its inline powered device detection mode. 4.3.5 IEEE 802.3af PoE Support The integrated transceivers are also compatible with switch designs intended for use in systems that supply power to Data Terminal Equipment (DTE) by means of the MDI or twisted pair cable, as described in clause 33 of the IEEE 802.3af. 4.3.6 ActiPHY™ Power Management In addition to the IEEE-specified power-down control bit (PHY_CTRL.POWER_DOWN_ENA), the devices also include an ActiPHY power management mode for each PHY. The ActiPHY mode enables VMDS-10392 VSC7420-02, VSC7421-02, and VSC7422-02 Datasheet Revision 4.3 29 Functional Descriptions support for power-sensitive applications. It uses a signal detect function that monitors the media interface for the presence of a link to determine when to automatically power-down the PHY. The PHY “wakes up” at a programmable interval and attempts to wake-up the link partner PHY by sending a burst of FLP over copper media. The ActiPHY power management mode in the integrated transceivers is enabled on a per-port basis during normal operation at any time by setting PHY_AUX_CTRL_STAT.ACTIPHY_ENA to 1. Three operating states are possible when ActiPHY mode is enabled: • • • Low power state LP wake-up state Normal operating state (link up state) The PHY switches between the low power state and the LP wake-up state at a programmable rate (the default is two seconds) until signal energy is detected on the media interface pins. When signal energy is detected, the PHY enters the normal operating state. If the PHY is in its normal operating state and the link fails, the PHY returns to the low power state after the expiration of the link status time-out timer. After reset, the PHY enters the low power state. When auto-negotiation is enabled in the PHY, the ActiPHY state machine operates as described. If autonegotiation is disabled and the link is forced to use 10BT or 100BTX modes while the PHY is in its low power state, the PHY continues to transition between the low power and LP wake-up states until signal energy is detected on the media pins. At that time, the PHY transitions to the normal operating state and stays in that state even when the link is dropped. If auto-negotiation is disabled while the PHY is in the normal operation state, the PHY stays in that state when the link is dropped and does not transition back to the low power state. The following illustration shows the relationship between ActiPHY states and timers. Figure 9 • ActiPHY State Diagram Low Power State Signal energy detected on media FLP Burst or Clause 37 restart signal sent Sleep timer expires Timeout timer expires and auto-negotiation enabled LP Wake-up State 4.3.6.1 Normal Operation Low Power State All major digital blocks are powered down in the lower power state. In this state, the PHY monitors the media interface pins for signal energy. The PHY comes out of low power state and transitions to the normal operating state when signal energy is detected on the media. This happens when the PHY is connected to one of the following: • • Auto-negotiation capable link partner Another PHY in enhanced ActiPHY LP wake-up state In the absence of signal energy on the media pins, the PHY transitions from the low power state to the LP wake-up state periodically based on the programmable sleep timer VMDS-10392 VSC7420-02, VSC7421-02, and VSC7422-02 Datasheet Revision 4.3 30 Functional Descriptions (PHY_CTRL_EXT3.ACTIPHY_SLEEP_TIMER). The actual sleep time duration is random, from –80 ms to +60 ms, to avoid two linked PHYs in ActiPHY mode entering a lock-up state during operation. After sending signal energy on the relevant media, the PHY returns to the low power state. 4.3.6.2 Link Partner Wake-up State In the link partner wake-up state, the PHY attempts to wake up the link partner. Up to three complete FLP bursts are sent on alternating pairs A and B of the Cat5 media for a duration based on the wake-up timer, which is set using register bits 20E1.12:11. After sending signal energy on the relevant media, the PHY returns to the low power state. 4.3.6.3 Normal Operating State In normal operation, the PHY establishes a link with a link partner. When the media is unplugged or the link partner is powered down, the PHY waits for the duration of the programmable link status time-out timer, which is set using ACTIPHY_LINK_TIMER_MSB_CFG and ACTIPHY_LINK_TIMER_LSB_CFG in the PHY_AUX_CTRL_STAT register. It then enters the low power state. 4.3.7 Testing Features The integrated transceivers include several testing features designed to facilitate performing systemlevel debugging. 4.3.7.1 Core Voltage and I/O Voltage Monitor The VSC7420-02, VSC7421-02, and VSC7422-02 device contains a monitoring circuit that provides a readout of the I/O and core supply voltages. The voltage value that is read out is accurate to within ±25 mV for the core and low voltage I/O supplies (0.9 V to 1.4 V) and ±50 mV for the high voltage I/O supplies (2.25 V to 2.75 V). 4.3.7.2 Ethernet Packet Generator (EPG) The Ethernet Packet Generator (EPG) can be used at each of the 10/100/1000BASE-T speed settings for Copper Cat5 media to isolate problems between the MAC and the PHY, or between a local PHY and its remote link partner. Enabling the EPG feature effectively disables all MAC interface transmit pins and selects the EPG as the source for all data transmitted onto the twisted pair interface. Important The EPG is intended for use with laboratory or in-system testing equipment only. Do not use the EPG testing feature when the PHY is connected to a live network. To use the EPG feature, set PHY_1000BT_EPG2.EPG_ENA to 1. When PHY_1000BT_EPG2.EPG_RUN_ENA is set to 1, the PHY begins transmitting Ethernet packets based on the settings in the PHY_1000BT_EPG1 and PHY_1000BT_EPG2 registers. These registers set: • • • • • • Source and destination addresses for each packet Packet size Inter-packet gap FCS state Transmit duration Payload pattern If PHY_1000BT_EPG1.TRANSMIT_DURATION_CFG is set to 0, PHY_1000BT_EPG1.EPG_RUN_ENA is cleared automatically after 30,000,000 packets are transmitted. 4.3.7.3 CRC Counters Two separate CRC counters are available in the PHY: a 14-bit good CRC counter available through PHY_CRC_GOOD_CNT.CRC_GOOD_PKT_CNT and a separate 8-bit bad CRC counter in PHY_CTRL_EXT4.CRC_1000BT_CNT. 4.3.7.4 Far-End Loopback The far-end loopback testing feature is enabled by setting PHY_CTRL_EXT1.FAR_END_LOOPBACK_ENA to 1. When enabled, it forces incoming data from a link VMDS-10392 VSC7420-02, VSC7421-02, and VSC7422-02 Datasheet Revision 4.3 31 Functional Descriptions partner on the current media interface, into the MAC interface of the PHY, to be re-transmitted back to the link partner on the media interface as shown in the following illustration. The incoming data also appears on the receive data pins of the MAC interface. Data present on the transmit data pins of the MAC interface is ignored when using this testing feature. Figure 10 • Far-End Loopback Diagram Link Partner Rx Cat5 4.3.7.5 PHY Switch Tx Near-End Loopback When the near-end loopback testing feature is enabled (by setting PHY_CTRL.LOOPBACK_ENA to 1), data on the transmit data pins (TXD) is looped back in the PCS block, onto the device receive data pins (RXD), as shown in the following illustration. When using this testing feature, no data is transmitted over the network. Figure 11 • Near-End Loopback Diagram Link Partner Rx Cat5 4.3.7.6 PHY Switch Tx Connector Loopback The connector loopback testing feature allows the twisted pair interface to be looped back externally. When using the connector loopback feature, the PHY must be connected to a loopback connector or a loopback cable. Pair A must be connected to pair B, and pair C to pair D, as shown in the following illustration. The connector loopback feature functions at all available interface speeds. Figure 12 • Connector Loopback Diagram PHY Switch A Cat5 B C D When using the connector loopback testing feature, the device auto-negotiation, speed, and duplex configuration is set using device registers 0, 4, and 9. For 1000BASE-T connector loopback, the following additional writes are required, executed in the following steps: 1. 2. 4.3.8 Enable the 1000BASE-T connector loopback. Set PHY_CTRL_EXT2.CON_LOOPBACK_1000BT_ENA to 1. Disable pair swap correction. Set PHY_CTRL_EXT2.CON_LOOPBACK_1000BT_ENA to 1. VeriPHY™ Cable Diagnostics The VSC7420-02, VSC7421-02, and VSC7422-02 devices include a comprehensive suite of cable diagnostic functions that are available through the onboard processor. These functions enable cable operating conditions and status to be accessed and checked. VMDS-10392 VSC7420-02, VSC7421-02, and VSC7422-02 Datasheet Revision 4.3 32 Functional Descriptions The VeriPHY suite has the ability to identify the cable length and operating conditions and to isolate common faults that can occur on the Cat5 twisted pair cabling. For the functional details of the VeriPHY suite and operating instructions, see ENT-AN0125, PHY, Integrated PHY-Switch VeriPHY - Cable Diagnostics Feature Application Note. Statistics 4.4 The following table lists the registers for the statistics module. Table 16 • Counter Registers Register Description Replication SYS::STAT:CNT Data register for reading Per counter port counters per port SYS::STAT_CFG.STAT_CLEAR_SHOT Clears port counters SYS::STAT_CFG.STAT_CLEAR_PORT Selects which port’s counters to clear SYS::STAT_CFG.TX_GREEN_CNT_MODE Controls whether to counts bytes or frames for Tx priority counters SYS::STAT_CFG.DROP_GREEN_CNT_MOD Controls whether to E counts bytes or frames for drop priority counters ANA::AGENCTRL.GREEN_COUNT_MODE ANA::AGENCTRL.RED_COUNT_MODE Controls whether to counts bytes or frames for Rx priority counters All counters for all ports are sharing a common statistics block with directly addressable counters. Each counter is 32 bits wide, which is large enough to ensure a wrap-around time longer than 13 seconds. Each switch core port has 43 Rx counters, 18 FIFO drop counters, and 31 Tx counters. The following table defines the per-port available Rx counters and lists the counter’s base address in the common statistics block. Table 17 • Rx Counters in the Statistics Block Type Short Name Base Address Description Rx c_rx_oct 0x000 Received octets in good and bad frames. Rx c_rx_uc 0x001 Number of good unicasts. Rx c_rx_mc 0x002 Number of good multicasts. Rx c_rx_bc 0x003 Number of good broadcasts. Rx c_rx_short 0x004 Number of short frames with valid CRC ( 0)? Y DROP_C_TAGGED_ENA [port]? Y N Discard Priority S-tagged Frame (VID=0)? Y DROP_PRIO_S_TAGGED_ENA [port]? Y N Discard Priority C-tagged Frame (VID=0)? Y DROP_PRIO_C_TAGGED_ENA [port]? Y N Discard DROP_UNTAGGED_ENA[port] and not reserved address (BPDU, GARP, CCM)? Y Discard Frame is Accepted If the frame is accepted by the VLAN acceptance filter, it can still be discarded in other places of the switch, such as: • • • 4.5.3 Policers, due to traffic exceeding a peak information rate. Analyzer, due to forwarding decisions such as VLAN ingress filtering. Queue system, due to lack of resources, frame aging, or excessive collisions. QoS and DSCP Classification This section provides information about the functions in the QoS and DSCP classification. The two tasks are described one, because the tasks have a significant amount of functionality in common. The following table lists the registers associated with QoS and DSCP classification. Table 22 • QoS and DSCP Classification Registers Register Description Replication ANA.PORT.QOS_CFG Configuration of the overall classification flow for QoS and DSCP. Per port ANA:PORT:QOS_PCP_DEI_MAP Mapping from (DEI, PCP) to _CFG (QoS). Per port per DEI per PCP VMDS-10392 VSC7420-02, VSC7421-02, and VSC7422-02 Datasheet Revision 4.3 40 Functional Descriptions Table 22 • QoS and DSCP Classification Registers (continued) Register Description Replication ANA::DSCP_CFG DSCP configuration per DSCP value. Per DSCP ANA::DSCP_REWR_CFG DSCP rewrite values per QoS class. Per QoS The classification provides the user with control of the QoS and DSCP classification algorithm. The result of the basic classification are the following frame properties, which follow the frame through the switch: • • The frame’s QoS class. This class is encoded in a 3-bit field, where 7 is the highest priority QoS class and 0 is the lowest priority QoS class. The QoS class is used by the queue system when enqueuing frames and when evaluating resource consumptions, for policing, statistics, and rewriter actions. The frame’s DSCP. This value is encoded in a 6-bit fields. The DSCP value is forwarded with the frame to the rewriter where it is translated and rewritten into the frame. The DSCP value is only applicable to IPv4 and IPv6 frames. The classifier looks for the following fields in the incoming frame to determine the QoS and DSCP classification: • • • • Port default QoS class. The default DSCP value is the frame’s DSCP value. For non-IP frames, the DSCP is 0 and it not used elsewhere in the switch. Priority Code Point (PCP) when the frame is VLAN tagged or priority tagged. There is an option to use the inner tag for double tagged frames (VLAN_CFG.VLAN_INNER_TAG_ENA). Both S-tagged and C-tagged frames are considered. Drop Eligible Indicator (DEI) when the frame is VLAN tagged or priority tagged. There is an option to use the inner tag for double tagged frames (VLAN_CFG.VLAN_INNER_TAG_ENA). Both S-tagged and C-tagged frames are considered. DSCP (all 6 bits, both for IPv4 and IPv6 packets). The classifier can look for the DSCP value behind up to two VLAN tags. The following illustration shows the flow chart of QoS classification. VMDS-10392 VSC7420-02, VSC7421-02, and VSC7422-02 Datasheet Revision 4.3 41 Functional Descriptions Figure 15 • QoS Classification Flow Chart QOS = QOS_DEFAULT_VAL[port] DSCP = 0 ”Frame is IPv4 or IPv6" Y DSCP = Frame.DSCP Y DSCP_TRANSLATE_ENA[port] Y DSCP = DSCP_TRANSLATE_VAL[DSCP] QOS_DSCP_ENA[port] Y DSCP_TRUST_ENA[DSCP] Y ”Frame has inner tag” and QOS_PCP_ENA[port] and VLAN_INNER_TAG_ENA[port]=1 QOS = QOS_DSCP_VAL[DSCP] Y QOS = QOS_PCP_DEI_VAL[port][Frame.InnerDEI][Frame.InnerPCP] ”Frame has outer tag” and QOS_PCP_ENA[port] Y QOS = QOS_PCP_DEI_VAL[port][Frame.OuterDEI][Frame.OuterPCP] Classified QoS The following illustration shows the flow chart for DSCP classification. VMDS-10392 VSC7420-02, VSC7421-02, and VSC7422-02 Datasheet Revision 4.3 42 Functional Descriptions Figure 16 • DSCP Classification Flow Chart DSCP = 0 ”Frame is IPv4 or IPv6" Y DSCP = Frame.DSCP Y DSCP_TRANSLATE_ENA[port] Y DSCP = DSCP_TRANSLATE_VAL[DSCP] DSCP_REWR_CFG[port] == ”Rewrite all” or DSCP_REWR_CFG[port] == Rewrite DSCP=0" and DSCP == 0 or DSCP_REWR_CFG[port] == ”Rewrite select” and DSCP_REWR_ENA[DSCP] == 1 Y DSCP = DSCP_QOS_REWR_VAL[QOS] Classified DSCP The translation part of the DSCP classification is common for both QoS and DSCP classification. VMDS-10392 VSC7420-02, VSC7421-02, and VSC7422-02 Datasheet Revision 4.3 43 Functional Descriptions 4.5.4 VLAN Classification The following table lists the registers associated with VLAN classification. Table 23 • VLAN Configuration Registers Register Description Replication ANA:PORT:VLAN_CFG Configures the port’s processing of Per port VLAN information in VLAN-tagged and priority-tagged frames. Configures the port-based VLAN. The VLAN classification determines a tag header for all frames. The tag header includes the following information: • • • • Priority Code Point (PCP) Drop Eligible Indicator (DEI) VLAN Identifier (VID) Tag Protocol Identifier (TPID) type (TAG_TYPE). This field informs whether tag used for classification was a C-tag or an S-tag. The tag header determined by the classifier is carried with the frame through the switch and is used in various places such as the analyzer for forwarding and the rewriter for egress tagging operations. The devices recognize three kinds of tags based on the TPID, which is the EtherType in front of the tag: • • • Customer tags (C-TAGs), which use TPID 0x8100. Service tags (S-TAGs), which use TPID 0x88A8 (IEEE 802.1ad). Service tags (S-TAGs), which use a custom TPID programmed in SYS::VLAN_ETYPE_CFG. For customer tags and service tags, both VLAN tags (tags with nonzero VID) and priority tags (tags with VID = 0) are processed. The tag header is either retrieved from a tag in the incoming frame or from a default port-based tag header. The port-based tag header is configured in ANA:PORT:VLAN_CFG. For double tagged frames, there is an option to use the inner tag instead of the outer tag (VLAN_CFG.VLAN_INNNER_TAG_ENA). In addition to the tag header, the ingress port decides the number of VLAN tags to pop at egress (VLAN_POP_CNT). If the configured number of tags to pop is greater than the actual number of tags in the frame, the number is reduced to the number of actual tags in the frame. The following illustration shows the flow chart for basic VLAN classification. VMDS-10392 VSC7420-02, VSC7421-02, and VSC7422-02 Datasheet Revision 4.3 44 Functional Descriptions Figure 17 • Basic VLAN Classification Flow Chart TAG_TYPE = VLAN_CFG.VLAN_TAG_TYPE PCP = VLAN_CFG.VLAN_PCP DEI = VLAN_CFG.VLAN_DEI VID = VLAN_CFG.VLAN_VID VLAN_POP_CNT = VLAN_CFG.VLAN_POP_CNT VLAN_AWARE_ENA[port] and ”Frame has outer tag” Y VLAN_INNER_TAG_ENA[port] and ”Frame has inner tag” Y TAG_TYPE = (Frame.InnerTPID 0x8100) PCP = Frame.InnerPCP DEI = Frame.InnerDEI VID = Frame.InnerVID TAG_TYPE = (Frame.OuterTPID 0x8100) PCP = Frame.OuterPCP DEI = Frame.OuterDEI VID = Frame.OuterVID VID == 0? Y VID = VLAN_CFG.VLAN_VID Basic Classified Tag Header (TAG_TYPE, PCP, DEI, VID) 4.5.5 Link Aggregation Code Generation This section provides information about the functions in link aggregation code generation. VMDS-10392 VSC7420-02, VSC7421-02, and VSC7422-02 Datasheet Revision 4.3 45 Functional Descriptions The following table lists the registers associated with aggregation code generation. Table 24 • Aggregation Code Generation Registers Register Description Replication ANA::AGGR_CFG Configures use of Layer-2 through Common Layer-4 flow information for link aggregation code generation. The classifier generates a link aggregation code, which is used in the analyzer when selecting to which port in a link aggregation group a frame is forwarded. The following contributions to the link aggregation code is configured in the AGGR_CFG register: • • • • • • Destination MAC address—use the lower 12 bits of the DMAC. Source MAC address—use the lower 12 bits of the SMAC. IPv6 flow label—use the 20 bits of the flow label. IPv4 source and destination IP addresses—use the lower 8 bits of the SIP and DIP. TCP/UDP source and destination port for IPv4 and IPv6 frames—use the lower 8 bits of the SPORT and DPORT. Random aggregation code—use a pseudo-random number instead of the frame information. Each of the enabled contributions are XOR’ed together, yielding a 4-bit aggregation code ranging from 0 to 15. For more information about how the aggregation code is used, see Link Aggregation, page 153. 4.5.6 CPU Forwarding Determination The following table lists the registers associated with CPU forwarding. Table 25 • CPU Forwarding Determination Register Description Replication CPU_FWD_CFG Enables CPU forwarding for various frame types Per port CPU_FWD_BPDU_CFG Enables CPU forwarding per BPDU address Per port CPU_FWD_GARP_CFG Enables CPU forwarding per GARP address Per port CPU_FWD_CCM_CFG Enables CPU forwarding per CCM/Link trace address Per port CPUQ_CFG CPU extraction queues for various None frame types CPUQ_8021_CFG CPU extraction queues for BPDU, None GARP, and CCM addresses. The classifier has support for determining whether certain frames must be forwarded to the CPU extraction queues. Other parts of the device can also determine CPU forwarding, for example, the analyzer, based on MAC table entries. All events leading to CPU forwarding are OR’ed together, and the final CPU extraction queue mask, which is available to the user, contains the sum of all events leading to CPU extraction. For more information, see CPU Extraction and Injection, page 162. Upon CPU forwarding by the classifier, the frame type determines whether the frame is redirected or copied to the CPU. Any frame type or event causing a redirection to the CPU cause all front ports to be removed from the forwarding decision - only the CPU receives the frame. When copying a frame to the CPU, the normal forwarding of the frame is unaffected. VMDS-10392 VSC7420-02, VSC7421-02, and VSC7422-02 Datasheet Revision 4.3 46 Functional Descriptions The following table lists the frame types, with respect to CPU forwarding, that are recognized by the classifier. Table 26 • Frame Type Definitions for CPU Forwarding Frame Condition Copy/Redirect BPDU frames. Reserved Addresses (IEEE 802.1D 7.12.6) DMAC = 0x0180C2000000 to 0x0180C20000F (BPDUs and various Slow protocols supporting spanning tree, link aggregation, port authentication) Redirect Reserved ALLBRIDGE address DMAC = 0x0180C2000010 Redirect GARP Application DMAC = 0x0180C2000020 to 0x0180C200002F Addresses (IEEE 802.1D 12.5) Redirect CCM/Link Trace Addresses (IEEE P802.1ag) DMAC = 0x0180C2000030 to 0x0180C200003F Redirect IGMP DMAC = 0x01005E000000 to 0x01005E7FFFFF EtherType = IPv4 IP Protocol = IGMP Redirect MLD DMAC = 0x333300000000 to 0x3333FFFFFFFFF EtherType = IPv6 IPv6 Next Header = 0 Hop-by-hop options header with the first option being a Router Alert option with the MLD message (Option Type = 5, Opt Data Len = 2, Option Data = 0). Redirect IPv4 Multicast Ctrl DMAC = 0x01005E000000 to 0x01005E7FFFFF EtherType = IPv4 IP protocol is not IGMP IPv4 DIP inside 224.0.0.x Copy Source port All frames received on enabled ingress port Copy All other frames 4.6 Analyzer The analyzer module is responsible for a number of tasks: • • • Determining the set of destination ports, also known as the forwarding decision, for frames received by port modules. This includes Layer-2 forwarding, CPU-forwarding, mirroring, and SFlow sampling. Keeping track of network stations and their MAC addresses through MAC address learning and aging. Holding VLAN membership information (configured by CPU) and applying this to the forwarding decision. The analyzer consists of three main blocks: • • • MAC table VLAN table Forwarding Engine The MAC and VLAN tables are the main databases used by the forwarding engine. The forwarding engine determines the forwarding decision and initiates learning in the MAC table when appropriate. VMDS-10392 VSC7420-02, VSC7421-02, and VSC7422-02 Datasheet Revision 4.3 47 Functional Descriptions The analyzer operates on analyzer requests initiated by the port modules. For each received frame, the port module requests the analyzer to determine the forwarding decision.The analyzer request contains the following frame information: • • • • Destination and source MAC addresses. Physical port number where the frame was received (referred to as PPORT). Logical port number where the frame was received (referred to as LPORT). By default, LPORT and PPORT are the same. However, when using link aggregation, multiple physical ports map to the same logical port. The LPORT value for each physical port is configured in ANA:PORT:PORT_CFG.PORTID_VAL in the analyzer. Frame properties derived by the classifier: Classified VID Link aggregation code Basic CPU forwarding CPU forwarding for special frame types determined by the classifier Based on this information, the analyzer determines an analyzer reply, which is returned to the ingress port modules. The analyzer reply contains: • • The forwarding decision (referred to as DEST). This mask contains 27 bits, 1 bit for each front port and the CPU port. The final CPU extraction queue mask (referred to as CPUQ). This mask contains 8 bits, 1 bit for each CPU extraction queue. The terms PPORT, LPORT, DEST and CPUQ, as previously defined, are used throughout the remainder of this section. 4.6.1 MAC Table This section provides information about the MAC table block in the analyzer. The following table lists the registers associated with MAC table access. Table 27 • MAC Table Access Register Description Replication MACHDATA MAC address and VID when accessing the MAC table. None MACLDATA MAC address when accessing the MAC table. None MACTINDX Direct address into the MAC table for direct read and write. None MACACCESS Flags and command when accessing the MAC None table. MACTOPTIONS Flags when accessing the MAC table None AUTOAGE Age scan period. None AGENCTRL Controls the default values for new entries in MAC table. None ENTRYLIM Controls limits on number of learned entries per Per port port LEARNDISC Counts the number of MAC table entries not learned due lack of storage in the MAC table None The analyzer contains a MAC table with 8192 entries containing information about stations learned by the devices. The table is organized as a hash table with four buckets and 2048 rows. Each row is indexed by an 11-bit hash value, which is calculated based on the station’s (MAC, VID) pair, as shown in the following illustration. VMDS-10392 VSC7420-02, VSC7421-02, and VSC7422-02 Datasheet Revision 4.3 48 Functional Descriptions Figure 18 • MAC Table Organization MAC/VID Hash Key Value Index 0 bucket 0 bucket 1 bucket 2 bucket 3 Index 1 bucket 0 bucket 1 bucket 2 bucket 3 Index XXX bucket 0 bucket 1 bucket 2 bucket 3 Index 2047 bucket 0 bucket 1 bucket 2 bucket 3 The following table lists the fields for each entry in the MAC table. Table 28 • MAC Table Entry Field Bits Description VALID 1 Entry is valid. MAC 48 The MAC address of the station (primary key). VID 12 VLAN identifier that the station is learned with (primary key). DEST_IDX 6 Destination mask index pointing to a destination mask in the destination mask table (PGID entries 0 through 63). IP6_MASK 3 Partial IPv6 multicast destination port mask. See IPv6 Multicast Entries, page 52. ENTRY_TYPE 2 Entry type: 0: Normal entry subject to aging. 1: Normal entry not subject to aging (locked). 2: IPv4 multicast entry not subject to aging. Full port set is encoded in MAC table entry. 3: IPv6 multicast entry not subject to aging. Full port set is encoded in MAC table entry. AGED_FLAG 1 Entry is aged once by an age scan. See Age Scan, page 50. MAC_CPU_COP 1 Y Copy frames from or to this station to the CPU. SRC_KILL 1 Do not forward frames from this station. Note This flag is not used for destination lookups. IGNORE_VLAN 1 Do not use the VLAN_PORT_MASK from the VLAN table when forwarding frames to this station. Entries in the MAC table can be added, deleted, or updated in three ways: VMDS-10392 VSC7420-02, VSC7421-02, and VSC7422-02 Datasheet Revision 4.3 49 Functional Descriptions • Hardware-based learning of source MAC addresses (that is, inserting new (MAC, VID) pairs in the MAC table). Age scans (setting AGED_FLAG and deleting entries.) CPU commands (for example, for CPU-based learning.) • • 4.6.1.1 Hardware-Based Learning The analyzer adds an entry to the MAC table when learning is enabled, and the MAC table does not contain an entry for a received frame’s (SMAC, VID). The new entry is formatted as follows: • • • • • • • • • VALID is set MAC is set to the frame’s SMAC VID set to the frame’s VID ENTRY_TYPE is set to 0 (normal entry subject to aging) DEST_IDX is set to the frame’s LPORT MAC_CPU_COPY is set to AGENCTRL.LEARN_CPU_COPY SRC_KILL is set to AGENCTRL.LEARN_SRC_KILL IGNORE_VLAN is set to AGENCTRL.LEARN_IGNORE_VLAN All other fields are cleared When a frame is received from a known station, that is, the MAC table already contains an entry for the received frame's (SMAC, VID), the analyzer can update the entry as follows. For entries of entry type 0 (unlocked entries): • The AGED_FLAG is cleared. This implies the station is active, avoiding the deletion of the entry due to aging. If the existing entry’s DEST_IDX differs from the frame’s LPORT, then the entry’s DEST_IDX is set to the frame's LPORT. This implies the station has moved to a new port. • For entries of entry type 1 (locked entries): • The AGED_FLAG is cleared. This implies the station is active. Entries of entry types 2 and 3 are never updated, because their multicast MAC addresses are never used as source MAC addresses. For more information about learning, see SMAC Analysis, page 60. 4.6.1.2 Age Scan The analyzer scans the MAC table for inactive entries. An age scan is initiated by either a CPU command or automatically performed by the device with a configurable age scan period (AUTOAGE). The age scan checks the flag AGED_FLAG for all entries in the MAC table. If an entry’s AGED_FLAG is already set and the entry is of entry type 0, the entry is removed. If the AGED_FLAG is not set, it is set to 1. The flag is cleared when receiving frames from the station identified by the MAC table entry. For more information, see Hardware-Based Learning, page 50. 4.6.1.3 CPU Commands The following table lists the set of commands that a CPU can use to access the MAC table. The MAC table command is written to MACACCESS.MAC_TABLE_CMD. Some commands require the registers MACLDATA, MACHDATA, and MACTINDX to be preloaded before the command is issued. Some commands return information in MACACCESS, MACLDATA, and MACHDATA. Table 29 • MAC Table Commands Command Purpose Use LEARN Insert/learn new entry in MAC table. Position given by (MAC, VID) Configure MAC and VID of the new entry in MACHDATA and MACLDATA. Configure remaining entry fields in MACACCESS. The location in the MAC table is calculated based on (MAC, VID). FORGET Delete/unlearn entry given by (MAC, VID) Configure MAC and VID in MACHDATA and MACLDATA. VMDS-10392 VSC7420-02, VSC7421-02, and VSC7422-02 Datasheet Revision 4.3 50 Functional Descriptions Table 29 • 4.6.1.4 MAC Table Commands (continued) Command Purpose Use AGE Start age scan No preload required. Issue command. READ Read entry pointed Configure row (0-2047) and column (0-3) of the entry to read to by (row, column) in: MACTINDX.INDEX (row) MACTINDX.BUCKET (column) MACACCESS.VALID must be 0. When MAC_TABLE_CMD changes to IDLE, MACHDATA, MACLDATA, and MACACCESS contain the information read. LOOKUP Lookup entry pointed to by (MAC, VID) WRITE Configure MAC and VID of the new entry in MACHDATA and Write entry, MAC table position given MACLDATA. Configure remaining entry fields in MACACCESS. The location in the MAC table is given by row by (row, column) and column in MACTINDX. INIT Initialize the table No preload required. Issue command. GET_NEXT Get the smallest entry in the MAC table numerically larger than the specified (MAC, VID). The VID and MAC are evaluated as a 60-bit number with the VID being most significant. Configure MAC and VID of the starting point for the search in MACHDATA and MACLDATA. When MAC_TABLE_CMD changes to IDLE, success of the search is indicated by MACACESS.VALID. If successful, MACHDATA, MACLDATA, and MACACCESS contain the information read. IDLE Indicate that MAC table is ready for new command Configure MAC and VID of station to look up in MACHDATA and MACLDATA. MACACCESS.VALID must be 1. Issue a READ command. When MAC_TABLE_CMD changes to IDLE, success of the lookup is indicated by MACACESS.VALID. If successful, MACACCESS contains the entry information. Known Multicasts From a CPU, entries can be added to the MAC table with any content. This makes it possible to add a known multicast address with multiple destination ports: • • • • • Set the MAC and VID in MACHDATA and MACLDATA Set MACACCESS.ENTRY_TYPE = 1 because this is not an entry subject to aging. Set MACACCESS.AGED_FLAG to 0. Set MACACCESS.DEST_IDX to an unused value. Set the destination mask in the destination mask table pointed to by DEST_IDX to the desired ports. Example All frames in VLAN 12 with MAC address 0x010000112233 are to be forwarded to ports 8, 9, and 12. This is done by inserting the following entry in the MAC table: VID = 12 MAC = 0x010000112233 ENTRY_TYPE = 1 VALID = 1 VMDS-10392 VSC7420-02, VSC7421-02, and VSC7422-02 Datasheet Revision 4.3 51 Functional Descriptions AGED_FLAG = 0 DEST_IDX = 40 and configuring the destination mask table: PGID[40 = 0x1300. IPv4 and IPv6 multicast entries can be programmed differently without using the destination mask table. This is described in the following subsection. 4.6.1.5 IPv4 Multicast Entries MAC table entries with the ENTRY_TYPE = 2 settings are interpreted as IPv4 multicast entries. IPv4 multicasts entries match IPv4 frames, which are classified to the specified VID, and which have DMAC = 0x01005Exxxxxx, where xxxxxx is the lower 24 bits of the MAC address in the entry. Instead of a lookup in the destination mask table (PGID), the destination set is set to the lower 2 bits of the DEST_IDX value concatenated with the upper 24 bits of the entry MAC address. This is shown in the following table. Table 30 • IPv4 Multicast Destination Mask Destination Ports Record Bit Field Ports 23-0 MAC[47-24] Ports 25-24 DEST_IDX[1-0] Example All IPv4 multicast frames in VLAN 12 with MAC 01005E112233 are to be forwarded to ports 8, 9, and 12. This is done by inserting the following entry in the MAC table entry: VALID = 1 VID = 12 MAC = 0x001300112233 ENTRY_TYPE = 2 DEST_IDX = 0 4.6.1.6 IPv6 Multicast Entries MAC table entries with the ENTRY_TYPE = 3 settings are interpreted as IPv6 multicast entries: IPv6 multicasts entries match IPv6 frames, which are classified to the specified VID, and which have DMAC=0x3333xxxxxxxx, where xxxxxxxx is the lower 32 bits of the MAC address in the entry. Instead of a lookup in the destination mask table (PGID), the destination set is set to AGED_FLAG field concatenated with the IP6_MASK field, the DEST_IDX field and the upper 16 bits the MAC field. This is shown in the following table. Table 31 • IPv6 Multicast Destination Mask Destination Ports Record Bit Field Port 25 AGED_FLAG Ports 24-22 IP6_MASK Ports 21-16 DEST_IDX Ports 15-0 MAC [47-32] Example All IPv6 multicast frames in VLAN 12 with MAC 333300112233 are to be forwarded to ports 8, 9, and 12. This is done by inserting the following entry in the MAC table entry: VID = 12 MAC = 0x130000112233 VMDS-10392 VSC7420-02, VSC7421-02, and VSC7422-02 Datasheet Revision 4.3 52 Functional Descriptions ENTRY_TYPE = 3 VALID = 1 AGED_FLAG = 0 IP6_MASK = 0 DEST_IDX = 0 4.6.1.7 Port and VLAN Filter The following table lists the registers associated with the port and VLAN filter. Table 32 • VID/Port Filters Register Description Replication ANAGEFIL Port and VLAN filter for limiting the target for aging and search operations on MAC table. None The ANAGEFIL register can be used to only hit specific VLANs or ports when doing certain operations. If the filter is enabled, it affects: • • 4.6.1.8 Manual age scan command (MACACCESS.MAC_TABLE_CMD = AGE) The LOOKUP and GET_NEXT MAC table commands. For more information, see CPU Commands, page 50. Shared VLAN Learning The following table lists the location of the Filter Identifier (FID) used for shared VLAN learning. Table 33 • Register FID Definition Registers Description AGENCTRL.FID_MAS Combines multiple VIDs in the MAC table. K Replication None In the default configuration, the device is set up to do Independent VLAN Learning (IVL), that is, MAC addresses are learned separately on each VLAN. The device also supports Shared VLAN Learning (SVL), where a MAC table entry is shared among a group of VLANs. For shared VLAN learning, a MAC address and a Filter Identifier (FID) define each MAC table entry. A set of VIDs then map to the FID. The AGENCTRL.FID_MASK controls the mapping between FID and VIDs. The 12-bit FID_MASK masks out the corresponding bits in the VID. The FID used for learning and lookup is therefore calculated as FID = VID AND (NOT FID_MASK). All VIDs mapping to the same FID share the same MAC table entries. If the FID_MASK is cleared, Independent VLAN Learning is used. This is the default. Example Configure all MAC table entries to be shared among all VLANs. This is done by setting FID_MASK to 111111111111. Example Split the MAC table into two separate databases: one for even VIDs and one for odd VIDs. This is done by setting FID_MASK to 111111111110. VMDS-10392 VSC7420-02, VSC7421-02, and VSC7422-02 Datasheet Revision 4.3 53 Functional Descriptions 4.6.1.9 Learn Limit The following table lists the registers associated with controlling the number of MAC table entries per port. Table 34 • Learn Limit Definition Registers Register Description Replication ENTRYLIM Configures maximum number of unlocked entries in the MAC table per ingress port. Per port PORT_CFG. LIMIT_CPU If set, learn frames exceeding the limit are copied to the CPU. Per port PORT_CFG. LIMIT_DROP If set, learn frames exceeding the limit are discarded. Per port LEARNDISC The number of MAC table entries that could None not be learned due to a lack of storage space. The ENTRYLIM.ENTRYLIM register specifies the maximum number of unlocked entries in the MAC table that a port is allowed to use. Locked and IPMC entries are not taken into account. After the limit is reached, both auto-learning and CPU-based learning on unlocked entries are denied. A learn frame causing the limit to be exceeded can be copied to the CPU (PORT_CFG.LIMIT_DROP) and the forwarding to other front ports can be denied (PORT_CFG.LIMIT_DROP). The ENTRYLIM.ENTRYSTAT register holds the current number of entries in the MAC table. MAC table aging and manual removing of entries through the CPU cause the current number to be reduced. If a MAC table entry moves from one port to another port, this is also reduces the current number. If the move causes the new port’s limit to be exceeded, the entry is denied and removed from the MAC table. The LEARNDISC counts all events where a MAC table entry is not created or updated due to a learn limit. 4.6.2 VLAN Table The following table lists the registers associated with the VLAN Table. Table 35 • VLAN Table Access Register Description Replication VLANTIDX VID to access, and VLAN flags. None VLANACCESS VLAN port mask for VID and command None for access The analyzer has a VLAN table that contains information about the members of each of the 4096 VLANs. The following table lists fields for each entry in the VLAN table. Table 36 • Fields in the VLAN Table Field Bits Description VLAN_PORT_MASK 26 One bit for each port. Set if port is member of VLAN. The CPU port is always a member of all VLANs. VLAN_MIRROR 1 Mirror frames received in the VLAN. See Mirroring, page 63. VLAN_SRC_CHK 1 VLAN ingress filtering. If set, frames classified to this VLAN are dropped if PPORT is not member of the VLAN. VLAN_LEARN_DISABLE 1 D Disable learning in the VLAN. VMDS-10392 VSC7420-02, VSC7421-02, and VSC7422-02 Datasheet Revision 4.3 54 Functional Descriptions Table 36 • Fields in the VLAN Table (continued) Field Bits Description VLAN_PRIV_VLAN 1 Set VLAN to private. By default, all ports are members of all VLANs. This default can be changed through a CPU command. The following table lists the set of commands that a CPU can issue to access the VLAN table. The VLAN table command is written to VLANACCESS.VLAN_TBL_CMD. Table 37 • 4.6.3 VLAN Table Commands Command Purpose Use INIT Initialize the table Issue command. When VLAN_TBL_CMD changes to IDLE, initialization has completed and all ports are member of all VLANs. All flags are cleared. READ Read VLAN table entry for specific VID. Configure the VLAN to read from in VLANTIDX.INDEX. When VLAN_TBL_CMD changes to IDLE, VLANACCESS and VLANTIDX contain the information read. WRITE Write VLAN table entry for specific VID. Configure the VLAN to write to in VLANTIDX.INDEX. Configure the content of the VLAN record in VLANACCESS.VLANACCESS VLANTIDX.VLAN_MIRROR VLANTIDX.VLAN_SRC_CHK VLANTIDX.VLAN_LEARN_DISABLED VLANTIDX.VLAN_PRIV_VLAN IDLE Indicate that VLAN table is ready for new command Forwarding Engine The analyzer determines the set of ports to which each frame is forwarded, in several configurable steps. The resulting destination port set can include any number of ports, as well as the CPU port. The analyzer request from the port modules is passed through all the processing steps of the forwarding engine. As each step is carried out, the destination port set (DEST) and CPU extraction queue mask (CPUQ) are built up. In addition to the forwarding decision, the analyzer determines which frames are subject to learning (also known as learn frames). Learn frames trigger insertion of a new entry in the MAC table or update of an existing entry. Learning is presented as part of the forwarding, because in some cases, learning changes the normal forwarding of a frame, such as secure learning. During the processing, the analyzer determines a local frame property. The learning-disabled flag, LRN_DIS is used in the SMAC Learning step: • • If the learning-disabled flag is set, learning based on (SMAC, VID) is disabled. If the learning-disabled flag is cleared, learning is conducted according to the configuration in the SMAC learning step. The following illustration shows the configuration steps in the analyzer. VMDS-10392 VSC7420-02, VSC7421-02, and VSC7422-02 Datasheet Revision 4.3 55 Functional Descriptions Figure 19 • Analysis Steps Analyzer Request DMAC Analysis Forward to known destinations or flood MAC table CPUQ DEST VLAN Analysis Check VLAN membership LRN_DIS VLAN table CPUQ DEST Aggregation Select one port per aggregation group LRN_DIS CPUQ DEST SMAC Analysis Perform learning MAC table CPUQ DEST Storm Policers Limit rate of specific frame types CPUQ DEST sFlow Sampling Perform statistical sampling CPUQ DEST Mirroring Add mirrorports for frames being mirrored Analyzer Reply 4.6.3.1 DMAC Analysis During the DMAC analysis step, the (DMAC, VID) pair is looked up in the MAC table to get the first input to the calculation of the destination port set. For more information about the MAC table, see MAC Table, page 48. VMDS-10392 VSC7420-02, VSC7421-02, and VSC7422-02 Datasheet Revision 4.3 56 Functional Descriptions The following table lists the registers associated with the DMAC analysis step. Table 38 • DMAC Analysis Registers Register Description Replication FLOODING.FLD_UNICAST Index into the PGID table used for None flooding of unicast frames. FLOODING.FLD_BROADCAST Index into the PGID table used for None flooding of broadcast frames. FLOODING.FLD_MULTICAST Index into the PGID table used for None flooding of multicast frames, not flooded by the IPMC flood masks. FLOODING_IPMC.FLD_MC4_CT RL Index into the PGID table used for None flooding of IPv4 multicast control frames. FLOODING_IPMC.FLD_MC4_DA Index into the PGID table used for None TA flooding of IPv4 multicast data frames. FLOODING_IPMC.FLD_MC6_CT RL Index into the PGID table used for None flooding of IPv6 multicast control frames. FLOODING_IPMC.FLD_MC6_DA Index into the PGID table used for None TA flooding of IPv6 multicast data frames. PGID[63:0] Destination and flooding masks table 64 AGENCTRL. IGNORE_DMAC_FLAGS None Controls the use of MAC table flags from (DMAC, VID) entry and flooding flags CPUQ_CFG Configuration of CPU extraction queues None The (DMAC, VID) pair is looked up in the MAC table. If a match is found, the entry is returned and DEST is determined based on the MAC table entry. For more information, see MAC Table, page 48. If an entry is found in the MAC table entry of ENTRY_TYPE 0 or 1 and the CPU port is set in the PGID pointed to by the MAC table entry, CPU extraction queue PGID.DST_PGID is added to the CPUQ. If an entry is not found for the (DMAC, VID) in the MAC table, the frame is flooded. The forwarding decision is set to one of the seven flooding masks defined in ANA::FLOODING or ANA::FLOODING_IPMC, based on one of the flood type definitions listed in the following table. Table 39 • Forwarding Decisions Based on Flood Type Frame Type Condition IPv4 multicast data DMAC = 0x01005E000000 to 0x01005E7FFFFF EtherType = IPv4 IP protocol is not IGMP IPv4 DIP outside 224.0.0.x IPv6 multicast data DMAC = 0x333300000000 to 0x3333FFFFFFFFF EtherType = IPv6 IPv6 DIP outside 0xFF02::/16 VMDS-10392 VSC7420-02, VSC7421-02, and VSC7422-02 Datasheet Revision 4.3 57 Functional Descriptions Table 39 • Forwarding Decisions Based on Flood Type (continued) Frame Type Condition IPv4 multicast control DMAC = 0x01005E000000 to 0x01005E7FFFFF EtherType = IPv4 IP protocol is not IGMP IPv4 DIP inside 224.0.0.x IPv6 multicast control DMAC = 0x333300000000 to 0x3333FFFFFFFFF EtherType = IPv6 IPv6 DIP inside 0xFF02::/16 Broadcast DMAC = 0xFFFFFFFFFFFFFF non-IPv4-multicast-data non-IPv6-multicast-data non-IPv4-multicast-control non-IPv6-multicast-control Multicast Bit 40 in DMAC = 1 non-broadcast non-IPv4-multicast-data non-IPv6-multicast-data non-IPv4-multicast-control non-IPv6-multicast-control Unicast Bit 40 in DMAC = 0 Additionally, the MAC table flag MAC_CPU_COPY is processed if MAC_CPU_COPY is set, if the CPU port is added to DEST, and if CPUQ_CFG.CPUQ_MAC is added to CPUQ. The processing of this flag can be disabled through AGENCTRL.IGNORE_DMAC_FLAGS. Finally, classifier-based CPU-forwarding is processed if: • • The classifier decided to redirect the frame to the CPU, DEST is set to the CPU port only. The corresponding CPU extraction queue is added to CPUQ. The classifier decided to copy the frame to the CPU, the CPU port is added to DEST. The corresponding CPU extraction queue is added to CPUQ. For more information about frame type definitions for CPU forwarding, see Table 26, page 47. 4.6.3.2 VLAN Analysis During the VLAN analysis step, VLAN configuration is taken into account. As a result, ports can be removed from the forwarding decision. For more information about VLAN configuration, see VLAN Table, page 54. The following table lists the registers associated with VLAN analysis. Table 40 • VLAN Analysis Registers Register Description VLANMASK If PPORT is set in this mask, and PPORT is None not member of the VLAN to which the frame is classified, DEST is cleared. This is also called VLAN ingress filtering. Replication PORT_CFG.RECV_EN If this bit is cleared for PPORT, forwarding Per port A from this port to other front ports is disabled, and DEST is cleared. VMDS-10392 VSC7420-02, VSC7421-02, and VSC7422-02 Datasheet Revision 4.3 58 Functional Descriptions Table 40 • VLAN Analysis Registers (continued) Register Description PGID[106:80] Source port mask. Port mask per port, which Per port specifies allowed destination ports for frames received on PPORT. By default, a port can forward to all other ports except itself. ISOLATED_PORTS Private VLAN mask. Isolated ports are cleared in this mask. None COMMUNITY_PORTS Private VLAN mask. Community ports are cleared in this mask. None ADVLEARN.VLAN_CHK If set and VLAN ingress filtering clears DEST, then SMAC learning is disabled. Replication None The frame’s VID is used as an address for lookup in the VLAN table and the returned VLAN information is processed as follows: • • • • All ports that are not members of the VLAN (VLAN_PORT_MASK) are removed from DEST, except if the (DMAC, VID) match in the MAC table has VLAN_IGNORE set, or if there is no match in the MAC table and AGENCTRL.FLOOD_IGNORE_VLAN is set. Note These two exceptions are skipped if AGENCTRL.IGNORE_DMAC_FLAGS is set. If the VLAN_PRIV_VLAN flag in the VLAN table is set, the VLAN is private, and isolated and community ports must be treated differently. An isolated port is identified as an ingress port for which PPORT is cleared in the ISOLATED_PORTS register. An community port is identified as an ingress port for which PPORT is cleared in the COMMUNITY_PORTS register. For frames received on an isolated port, all isolated and community ports are removed from the forwarding decision. For frames received on a community port, all isolated ports are removed from the forwarding decision. If VLAN ingress filtering is enabled, it is checked whether PPORT is member of the VLAN (VLAN_PORT_MASK). If this is not the case, DEST is cleared. VLAN ingress filtering is enabled per port in the VLANMASK register or per VLAN in the VLAN_SRC_CHK flag in the VLAN table. If either is set, VLAN ingress filtering is performed. Next, it is checked whether the ingress port is enabled to forward frames to other front ports and the source mask (PGID[80+PPORT]) is processed as follows: • • If PORT_CFG.RECV_ENA for PPORT is 0, DEST is cleared except for the CPU port. Any ports, which are cleared in PGID[80+PPORT], are removed from DEST. Finally, SMAC learning is disabled by setting the LRN_DIS flag when either of the following two conditions is fulfilled as follows: • • 4.6.3.3 VLAN_LEARN_DISABLED is set in the VLAN table for the VLAN. A frame is subject to VLAN ingress filtering (frame dropped due to PPORT not being member of VLAN), and ADVLEARN.VLAN_CHK is set. Aggregation During the aggregation step, link aggregation is handled. The following table lists the registers associated with aggregation. Table 41 • Analyzer Aggregation Registers Register Description Replication PGID[79:64] Aggregation mask table. 16 The purpose of the aggregation step is to ensure that when a frame is destined for an aggregation group, it is forwarded to exactly one of the group's member ports. VMDS-10392 VSC7420-02, VSC7421-02, and VSC7422-02 Datasheet Revision 4.3 59 Functional Descriptions For non-aggregated ports, there is a one-to-one correspondence between logical port (LPORT) and physical port (PPORT). The aggregation step does not change the forwarding decision. For aggregated ports, all physical ports in the aggregation group map to the same logical port, and the entry in the destination mask table for the logical port includes all physical ports, which are members of the aggregation group. As a result, all but one member port must be removed from the destination port set. The lni aggregation code generated in the classifier is used to look up an aggregation mask in the aggregation masks table. Finally, ports that are cleared in the selected aggregation mask are removed from DEST. For more information about link aggregation, see Link Aggregation, page 153. 4.6.3.4 SMAC Analysis During the SMAC analysis step, the MAC table is searched for a match against the (SMAC, VID), and the MAC table is updated due to learning. The learning part is skipped if the LRN_DIS flag was set by any of the previous steps. The following table lists the registers associated with SMAC learning. Table 42 • SMAC Learning Registers Register Description Replication PORT_CFG.LEARN_ENA If set for PPORT, learning is skipped (that Per port is, LEARNAUTO, LEARNCPU, LEARNDROP, LIMIT_CPU, LIMIT_DROP, LOCKED_PORTMOVE_CPU, and LOCKED_PORTMOVE_DROP are ignored). PORT_CFG.LEARNAUTO If set for PPORT, hardware-based learning Per port is performed. PORT_CFG.LEARNCPU If set for PPORT, learn frames are copied to the CPU. Per port PORT_CFG.LEARNDROP If set for PPORT, the CPU drops or forwards learn frames. Per port PORT_CFG.LIMIT_CPU If set for PPORT, learn frames for which Per port PPORT exceeds the port’s limit are copied to the CPU. PORT_CFG.LIMIT_DROP If set for PPORT, learn frames for which PPORT exceeds the port’s limit are discarded. Per port PORT_CFG. If set for PPORT, frames triggering a port LOCKED_PORTMOVE_CPU move of a locked entry are copied to the CPU. Per port PORT_CFG. LOCKED_PORTMOVE_DR OP If set for PPORT, frames triggering a port move of a locked entry are discarded. Per port AGENCTRL.IGNORE_SMA C_FLAGS Controls the use of the MAC table flags from (SMAC, VID) entry. None Three different type of learn frames are identified: • Normal learn frames Frames for which an entry for the (SMAC, VID) is not found in the MAC table or the (SMAC, VID) entry in the MAC table is unlocked and has a DEST_IDX different from LPORT. In addition, the learn limit for the LPORT must not be exceeded (ENTRYLIM). VMDS-10392 VSC7420-02, VSC7421-02, and VSC7422-02 Datasheet Revision 4.3 60 Functional Descriptions • • Learn frames exceeding the learn limit Same condition as for normal learn frames except that the learn limit for the LPORT is exceeded (ENTRYLIM) Learn frames triggering a port move of a locked MAC table entry Frames for which the (SMAC, VID) entry in the MAC table is locked and has a DEST_IDX different from LPORT. For all learn frames, the following must apply before learning related processing is applied: • • Learning is enabled by PORT_CFG.LEARN_ENA. The LRN_DIS flag from previous processing steps must be cleared, which implies that: – Learning is not disabled due to VLAN ingress filtering – Learning is enabled for the VLAN (VLAN_LEARN_DISABLED is cleared in the VLAN table) In addition, learning must not be disabled due to the ingress policer having policed the frame. For more information, see Policers, page 64. If learning is enabled, learn frames are processed according to the setting of the following configuration parameters. Normal learn frames: • • • Automatic learning. If PORT_CFG.LEARNAUTO is set for PPORT, the (SMAC, VID) entry is automatically added to the MAC table Drop learn frames. If PORT_CFG.LEARNDROP is set for PPORT, DEST is cleared for learn frames. Therefore, learn frames are not forwarded on any ports. This is used for secure learning, where the CPU must verify a station before forwarding is allowed. Copy learn frames to the CPU. If PORT_CFG.LEARNCPU is set for PPORT, the CPU port is added to DEST for learn frames and CPUQ_CFG.CPUQ_LRN is set in CPUQ. This is used for CPU based learning. Learn frames exceeding the learn limit: • • Drop learn frames. If PORT_CFG.LIMIT_DROP is set for PPORT, DEST is cleared for learn frames. As a result, learn frames are not forwarded on any ports. Copy learn frames to the CPU – If PORT_CFG.LIMIT_CPU is set for PPORT, the CPU port is added to DEST and CPUQ_CFG.CPUQ_LRN is set in CPUQ for learn frames. Learn frames triggering a port move of a locked MAC table entry: • • Drop learn frames. If PORT_CFG.LOCKED_PORTMOVE_DROP is set for PPORT, DEST is cleared for learn frames. Therefore, learn frames are not forwarded on any ports. Copy learn frames to the CPU. If PORT_CFG.LOCKED_PORTMOVE_CPU is set for PPORT, the CPU port is added to DEST and CPUQ_CFG.CPUQ_LOCKED_PORTMOVE is added to CPUQ. Finally, if a match is found in the MAC table for the (SMAC, VID), adjustments can be made to the forwarding decision. • • If the (SMAC, VID) match in the MAC table has SRC_KILL set, DEST is cleared except the CPU port. If the (SMAC, VID) match in the MAC table has MAC_CPU_COPY set, the CPU port is added to DEST and CPUQ_CFG.CPUQ_MAC_COPY is added to CPUQ. The processing of the MAC table flags from the (SMAC, VID) match can be disabled through AGENCTRL.IGNORE_SMAC_FLAGS. 4.6.3.5 Storm Policers The storm policers are activated during the storm policers step. The following table lists the registers associated with storm policers. Table 43 • Storm Policer Registers Register Description Replication STORMLIMIT_CFG Enable policing of various frame types. 4 STORMLIMIT_BURS Configure maximum allowed rates of the T different frame types. None VMDS-10392 VSC7420-02, VSC7421-02, and VSC7422-02 Datasheet Revision 4.3 61 Functional Descriptions The analyzer contains four storm policers that can limit the maximum allowed forwarding frame rate for various frame types. The storm policers are common to all ports and, as a result, measure the sum of traffic forwarded by the switch. A frame can activate several storm policers, and the frame is discarded if any of the activated storm policers exceed a configured rate. The storm policers work independently of other policers in the system (for example, port policers). As a result, frames policed by other policers are still measured by the storm policers. Each storm policer can be configured to a frame rate ranging from 1 frame per second to 1 million frames per second. The following table lists the available storm policers. Table 44 • Storm Policers Storm Policer Description Broadcast Flooded frames with DMAC = 0xFFFFFFFFFFFF. Multicast Flooded frames with DMAC bit 40 set, except broadcasts. Unicast Flooded frames with DMAC bit 40 cleared. Learn Learn frames copied or redirected to the CPU due to learning (LOCKED_PORTMOVE_CPU, LIMIT_CPU, LEARNCPU). For each of the storm policers, a maximum rate is configured in STORMLIMIT_CFG and STORMLIMIT_BURST: • • • • STORM_UNIT chooses between a base unit of 1 frame per second or 1 kiloframes per second. STORM_RATE sets the rate to 1, 2, 4, 8, …, 1024 times the base unit (STORM_UNIT). STORM_BURST configures the maximum number of frames in a burst. STORM_MODE specifies how the policer affects the forwarding decision. The options are: When policing, clear the CPU port in DEST. When policing, clear DEST except for the CPU port. When policing, clear DEST Note that frames where the DMAC lookup returned a PGID with the CPU port set are always forwarded to the CPU even when the frame is policed by the storm policers. For more information, see DMAC Analysis, page 56. 4.6.3.6 sFlow Sampling This process step handles sFlow sampling. The following table lists the registers associated with sFlow sampling. Table 45 • sFlow Sampling Registers Register Description Replication SFLOW_CFG Configures sFlow samplers (type and rates). Per port CPUQ_CFG.CPUQ_SFLOW CPU extraction queue for sFLow sampled frames. None sFlow is a standard for monitoring high-speed switch networks through statistical sampling of incoming and outgoing frames. Each port in the devices can be setup as an sFlow agent monitoring the particular link and generating sFlow data. If a frame is sFlow sampled, it is copied to the sFlow CPU extraction queue (CPUQ_SFLOW). An sFlow agent is configured through SFLOW_CFG with the following options: • • SF_RATE specifies the probability that the sampler copies a frame to the CPU. Each frame being candidate for the sampler has the same probability of being sampled. The rate is set in steps of 1/4096. SF_SAMPLE_RX enables incoming frames on the port as candidates for the sampler. VMDS-10392 VSC7420-02, VSC7421-02, and VSC7422-02 Datasheet Revision 4.3 62 Functional Descriptions • SF_SAMPLE_TX enables outgoing frames on the port as candidates for the sampler. The Rx and Tx can be enabled independently. If both are enabled, all incoming and outgoing traffic on the port is subject to the statistical sampling given by the rate in SF_RATE. 4.6.3.7 Mirroring This processing step handles mirroring. The following table lists the registers associated with mirroring. Table 46 • Mirroring Registers Register Description Replication ADVLEARN.LEARN_MIRROR For learn frames, ports in this mask (mirror ports) are added to DEST. None AGENCTRL.MIRROR_CPU Mirror all frames forwarded to the CPU port module None PORT_CFG.SRC_MIRROR_ENA Mirror all frames received on an ingress port (ingress port mirroring). Per port EMIRRORPORTS Mirror frames that are to be None transmitted on any ports set in this mask (egress port mirroring) VLANTIDX.VLAN_MIRROR Mirror all frames classified to a specific VID. Per VLAN MIRRORPORTS When mirroring a frame, ports in this mask are added to DEST. None AGENCTRL.CPU_CPU_KILL_EN Clear the CPU port if source port is None A the CPU port and the CPU port is set in DEST. Frames subject to mirroring are identified based on the following mirror probes: • • • • • Learn mirroring if ADVLEARN.LEARN_MIRROR is set and frame is a learn frame. CPU mirroring if AGENCTRL.MIRROR_CPU is set and the CPU port is set in DEST. Ingress mirroring if PORT_CFG.SRC_MIRROR_ENA is set. Egress mirroring if any port set in EMIRRORPORTS is also set in DEST. VLAN mirroring if VLAN_MIRROR set in the VLAN table entry. The following adjustment is made to the forwarding decision for frames subject to mirroring: • Ports set in MIRRORPORTS are added to DEST. If the CPU port is set in the MIRRORPORTS, CPU extraction queue CPUQ_CFG.CPUQ_MIRROR is added to the CPUQ. For learn frames with learning enabled, all ports in ADVLEARN.LEARN_MIRROR are added to DEST. For more information, see SMAC Analysis, page 60. For more information about mirroring, see Mirroring, page 156. Finally, if AGENCTRL.CPU_CPU_KILL_ENA is set, the CPU port is removed if the ingress port is the CPU port itself. This is similar to source port filtering done for front ports and prevents the CPU from sending frames back to itself. VMDS-10392 VSC7420-02, VSC7421-02, and VSC7422-02 Datasheet Revision 4.3 63 Functional Descriptions 4.6.4 Analyzer Monitoring Miscellaneous events in the analyzer can be monitored, which can provide an understanding of the events during the processing steps. The following table lists the registers associated with analyzer monitoring. Analyzer Monitoring Table 47 • Register Description Replication ANMOVED ANMOVED[n] is set when a known station has moved None to port n. ANEVENTS Sticky bit register for various events. LEARNDISC The number of learn events that failed due to a lack of None storage space in the MAC table. None Port moves, defined as a known station moving to a new port, are registered in the ANMOVED register. A port move occurs when an existing MAC table entry for (MAC, VID) is updated with new port information (DEST_IDX). Such an event is registered in ANMOVED by setting the bit corresponding to the new port. Continuously occurring port moves may indicate a loop in the network or a faulty link aggregation configuration. A list of 27 events, such as frame flooding or policer drop, can be monitored in ANEVENTS. The LEARNDISC counter registers every time an entry in the MAC table cannot be made or if an entry is removed due to lack of storage. 4.7 Policers and Ingress Shapers The devices support a policer per ingress ports and per ingress queues. Each ingress port also has an ingress shaper. Both the policers and the shapers can limit the bandwidth of received frames. When configured bandwidth is exceeded, the policers discard frames, while the ingress shaper holds back the traffic in the queue system. Each frame can hit up to two policers and one ingress shaper. In addition to the policers and ingress shapers described, the devices also support a number of storm policers and an egress scheduler with per-port and per-egress queue shapers. For more information, see Storm Policers, page 61 and Scheduler and Shaper, page 74. 4.7.1 Policers This section explains the functions of the policers. The following table lists the registers associated with policer control. Table 48 • Policer Control Registers Register Description Replication ANA:PORT:POL_CFG Enables use of port and queue policers. Per port SYS:POL:POL_PIR_CFG Configures the policer’s peak information 256 rate. SYS:POL:POL_MODE_CF Configures the policer’s mode of G operation. 256 SYS:POL:POL_PIR_STAT E Current state of the peak information rate 256 bucket. SYS:PORT:POL_FLOWC Flow control settings Per port SYS::POL_HYST Hysteresis settings. None The policers can be assigned to the following two blocks: VMDS-10392 VSC7420-02, VSC7421-02, and VSC7422-02 Datasheet Revision 4.3 64 Functional Descriptions • • Ingress ports. Port ‘p’ use policer ‘p’. Ingress queues. Ingress queue ‘q’ on port ‘p’ use policer 32 + 8x ‘p’ + ‘q’. Each of the eight per-port ingress queues can be assigned to its own policer. Port and queue policers are enabled through ANA:PORT:POL_CFG.PORT_POL_ENA and ANA:PORT:POL_CFG.QUEUE_POL_ENA. Each frame can hit a policer from each block; one port policer, one queue policer. The policers are selected as follows: • • The ingress port where the frame was received points to the port policer. The QoS class classified to by the classifier points to the queue policer. Any frame received by the MAC and forwarded to the classifier is applicable to policing. Frames with errors, pause frames, or MAC control frames are not forwarded by the MAC and, as a result, they are not accounted for in the policers. That is, they are not policed and are not adding to the rate measured by the policers. In addition, the following special frame types can bypass the policers: • • If ANA:PORT:POL_CFG.POL_CPU_REDIR_8021 is set, frames being redirected to the CPU due to the classifier detecting the frames as being BPDU, ALLBRIDGE, GARP, or CCM/Link trace frames are not policed. If ANA:PORT:POL_CFG.POL_CPU_REDIR_IP is set, frames being redirected to the CPU due to the classifier detecting the frames as being IGMP or MLD frames are not policed. These frames are still considered part of the rates being measured so the frames add to the relevant policer buckets but they are never discarded due to policing. The order in which the policers are executed is controlled through ANA:PORT:POL_CFG.POL_ORDER. The order can take the following main modes: • • • Serial The policers are checked one after another. If a policer is closed, the frame is discarded and the subsequent policer buckets are not updated with the frame. The serial order is programmable. Parallel with independent bucket updates The two policers are working in parallel independently of each other. Each frame is added to a policer bucket if the policer is open, otherwise the frame is discarded. A frame may be added to one policer although another policer is closed. Parallel with dependent bucket updates The two policers are working in parallel but dependent on each other with respect to bucket updates. A frame is only added to the policer buckets if all two policers are open. Each of the policers contain a leaky bucket with the following configurations: • • Peak Information Rate (PIR) – Specified in POL_PIR_CFG.PIR_RATE in steps of 100 kbps. Maximum is 3.277 Gbps. Peak Burst Size (PBS) – Specified in POL_PIR_CFG.PIR_BURST in steps of 4 kilobytes. Maximum is 252 kilobytes. Additionally, the following parameters can be configured per policer: • • • The leaky bucket calculation can be configured to include or exclude preamble and inter-frame gap through configuration of POL_MODE_CFG.IPG_SIZE. Each policer can be configured to measure frame rates instead of bit rates (POL_MODE_CFG.FRM_MODE). The rate unit can be configured to 100 frames per second or 1 frame per second. POL_MODE_CFG.OVERSHOOT_ENA controls whether a bucket is allowed to use more than the actual number of tokens in the bucket when accepting a frame (overshooting). If POL_MODE_CFG.OVERSHOOT_ENA is cleared, the number of tokens in the bucket must be larger than the number of tokens required to accept the frame. By default, a policer discards frames while the policer is closed. A discarded frame is neither forwarded to any ports (including the CPU) nor is it learned. However, each port policer has the option to run in flow control where the policer instructs the MAC to issue flow control pause frames instead of discarding frames. This is enabled in SYS:PORT:POL_FLOWC. Common for all port policers, POL_HYST.POL_FC_HYST specifies a hysteresis, which controls when the policer can re-open after having closed. VMDS-10392 VSC7420-02, VSC7421-02, and VSC7422-02 Datasheet Revision 4.3 65 Functional Descriptions To improve fairness between small and large frames being policed by the same policer, POL_HYST.POL_DROP_HYST specifies a hysteresis, which controls when the policer can re-open after being closed. By setting it to a value larger than the maximum transmission unit, it guarantees that when the policer opens again, all frames have the same chance of being accepted. This setting only applies to policers working in drop mode. The current fill level of the leaky buckets can be read in POL_PIR_STATE. The unit is 0.5 bits. 4.7.2 Ingress Shapers The following table lists the registers associated with ingress shaper control. Table 49 • Ingress Shaper Control Registers Register Description Replication SYS:PORT:ISHP_CFG Configures rate and burst. Per port SYS:PORT:ISHP_MODE_CFG Configures mode of operation. Per port SYS:PORT:ISHP_STATE Current level of leaky bucket. Per port In addition to the policers, each port has an ingress shaper that controls the rate at which ingress ports are allowed to transfer data to egress ports. An ingress shaper does not discard any frames when its rate is exceeded, but simply holds back the frames in the ingress queues until the rate is below the configured value again. To ensure proper operation of the ingress shapers, all frames on all ports must be assigned the same QoS class when the ingress shapers are enabled. The ingress shaper is enabled in ISHP_CFG.ISHP_ENA. Each of the ingress shapers contains a leaky bucket with the following configurations: • • Maximum transfer rate is specified in ISHP_CFG.ISHP_RATE in steps of 100 kbps. Maximum is 3.277 Gbps. Maximum burst size is specified in ISHP_CFG.ISHP_BURST in steps of 4 kilobytes. Maximum is 252 kilobytes. Additionally, the following parameters can be configured per ingress shaper: • • The leaky bucket calculation can be configured to include or exclude preamble and inter-frame gap through configuration of ISHP_MODE_CFG.ISHP_IPG_SIZE. Each ingress shaper can be configured to measure frame rates instead of bit rates (ISHP_MODE_CFG.ISHP_FRM_MODE). The rate unit can be configured to 100 frames per second or 1 frame per second. The current fill level of the leaky bucket can be read in ISHP_STATE. The unit is 0.5 bits. 4.8 Shared Queue System The devices include a shared queue system with one ingress queue and eight egress queues per port. The queue system has 512 kilobytes of buffer. Frames are stored in the ingress queue after frame analysis. Each egress port module selected by the frame analysis receives a copy of the frame and stores the frame in the appropriate egress queue given by the frame’s QoS class. The transfer from ingress to egress is extremely efficient with a transfer time of 8 ns per frame copy (equivalent to a transfer rate of 64 Gbps for 64-byte frames and 1.5 Tbps for 1518byte frames. Each egress port module has a scheduler, which selects between the egress queues when transmitting frames. The following illustration shows the shared queue system. VMDS-10392 VSC7420-02, VSC7421-02, and VSC7422-02 Datasheet Revision 4.3 66 Functional Descriptions Rx MAC Rx RxMAC MAC Frame Analysis (Find QoS class and set of destination ports) Ingress Queues (1/port) Egress Queues (1/QoS class/port) Ingr. Queue 0 One or multiple copies or discard Port 0, priority 1 Port 26, priority 7 Ingr. Queue 26 Egress Transmitter Egress Port Module (1/port) Scheduler Ingr. Queue 1 Port 0, priority 0 MAC Tx Resource depletion can prevent one or more of the frame copies from the ingress queue to the egress queues. If a frame copy cannot be made due to lack of resources, the ingress port’s flow control mode determines the behavior as follows: • • Ingress port is in drop mode: The frame copy is discarded. Ingress port is in flow control mode: The frame is held back in the ingress queue and the frame copy is made when the congestion clears. For more information about special configurations of the shared queue system with respect to flow control, see Ingress Pause Request Generation, page 72. 4.8.1 Buffer Management A number of watermarks control how much data can be pending in the egress queues before the resources are depleted. There are no watermarks for the ingress queues, except for flow control, because the ingress queues are empty most of the time due to the fast transfer rates from ingress to egress. For more information, see Ingress Pause Request Generation, page 72. When the watermarks are configured properly, congested traffic does not influence the forwarding of non-congested traffic. F The memory is split into two main areas: • • A reserved memory area. The reserved memory area is subdivided into areas per port per QoS class per direction (ingress/egress). A shared memory area, which is shared by all traffic. For setting up the reserved areas, egress queue watermarks exist per port and per QoS class for both ingress and egress. The following table lists the reservation watermarks. Table 50 • Reservation Watermarks Register Description Replication BUF_Q_RSRV_E Configures the reserved amount of egress buffer per egress queue. Per egress queue VMDS-10392 VSC7420-02, VSC7421-02, and VSC7422-02 Datasheet Revision 4.3 67 Functional Descriptions Table 50 • Reservation Watermarks (continued) Register Description Replication BUF_P_RSRV_E Configures the reserved amount of egress Per egress buffer shared among the eight egress queues. port BUF_Q_RSRV_I Configures the reserved amount of egress buffer per ingress port per QoS class across all egress ports. BUF_P_RSRV_I Per ingress Configures the reserved amount of egress buffer per ingress port shared among the eight port QoS classes. Per ingress port per QoS class All the watermarks, including the ingress watermarks, are compared against the memory consumptions in the egress queues. For example, the ingress watermarks in BUF_Q_RSRV_I compare against the total consumption of frames across all egress queues received on the specific ingress port and classified to the specific QoS class. The ingress watermarks in BUF_P_RSRV_I compare against the total consumption of all frames across all egress queues received on the specific ingress port. The reserved areas are guaranteed minimum areas. A frame cannot be discarded or held back in the ingress queues if the frame’s reserved areas are not yet used. The shared memory area is the area left when all the reservations are taken out. The shared memory area is shared between all ports, however, it is possible to configure a set of watermarks per QoS class and per drop precedence level (green/yellow) to stop some traffic flows before others. The following table lists the sharing watermarks. Table 51 • Sharing Watermarks Register Description Replication BUF_PRIO_SHR_E Configures how much of the shared memory area that egress frames with the given QoS class are allowed to use. Per QoS class BUF_COL_SHR_E Configures how much of the shared memory area that egress frames with the given drop precedence level are allowed to use. Per drop precedence level BUF_PRIO_SHR_I Configures how much of the shared memory area that ingress frames with the given QoS class are allowed to use. Per QoS class BUF_COL_SHR_I Configures how much of the shared memory area that ingress frames with the given drop precedence level are allowed to use. Per drop precedence level The sharing watermarks are maximum areas in the shared memory that a given traffic flow can use. They do not guarantee anything. When a frame is enqueued into the egress queue system, the frame first consumes from the queue’s reserved memory area, then from the port’s reserved memory area. When all the frame’s reserved memory areas are full, it consumes from the shared memory area. The following provides some simple examples on how to configure the watermarks and how that influences the resource management: • • Setting BUF_Q_RSRV_E(egress port = 17, QoS class = 4) to 2 kilobytes guarantees that traffic destined for port 17 classified to QoS class 4 have room for 2 kilobytes of frame data before frames can get discarded. Setting BUF_Q_RSRV_I(ingress port = 17, QoS class = 4) to 2 kilobytes guarantees that traffic received on port 17 classified to QoS class 4 have room for 2 kilobytes of frame data before frames can get discarded. VMDS-10392 VSC7420-02, VSC7421-02, and VSC7422-02 Datasheet Revision 4.3 68 Functional Descriptions • • Setting BUF_P_RSRV_I(ingress port 17) to 10 kilobytes guarantees that traffic received on port 17 have room for 10 kilobytes of data before frames can get discarded. The three above reservations reserve in total 14 kilobytes of memory (2 + 2+ 10 kilobytes) for port 17. If the same reservations are made for all ports, there are 512 – 27 × 14 = 134 kilobytes left for sharing. If the sharing watermarks are all set to 134 kilobytes, all traffic groups can consume memory from the shared memory area without restrictions. If, instead, setting BUF_PRIO_SHR_E(QoS class = 7) to 100 kilobytes and the other watermarks BUF_PRIO_SHR_E(QoS class = 0:6) to 70 kilobytes guarantees that traffic classified to QoS class 7 has 30 kilobytes extra buffer. The buffer is shared between all ports. 4.8.2 Frame Reference Management Each frame in an egress queue consumes a frame reference, which is a pointer element that points to the frame’s data in the memory and to the pointer element belonging to the next frame in the queue. The following illustrations shows how the frame references are used for creating the queue structure. Figure 20 • Frame Reference Frame Reference Pointer Memory Pointer Buffer Memory Egress queue, port 17, QoS class 4 Head Tail Frame References The shared queue system holds a table of 5500 frame references. The consumption of frame references is controlled through a set of watermarks. The set of watermarks is the exact same as for the buffer control. The frame reference watermarks are prefixed REF_. Instead of controlling the amount of consumed memory, they control the number of frame references. Both reservation and sharing watermarks are available. For more information, see Table 50, page 67 and Table 51, page 68. When a frame is enqueued into the shared queue system, the frame consumes first from the queue’s reserved frame reference area, then from the port’s reserved frame reference area. When all the frame’s reserved frame reference areas are full, it consumes from the shared frame reference area. 4.8.3 Resource Depletion Condition A frame copy is made from an ingress port to an egress port when both a memory check and a frame reference check succeed. The memory check succeeds when at least one of the following conditions is met: • • • Ingress memory is available: BUF_Q_RSRV_I or BUF_P_RSRV_I are not exceeded. Egress memory is available: BUF_Q_RSRV_E or BUF_P_RSRV_E are not exceeded. Shared memory is available: None of BUF_PRIO_SHR_E or BUF_PRIO_SHR_I are exceeded. The frame reference check succeeds when at least one of the following conditions is met: • • • Ingress frame references are available: REF_Q_RSRV_I or REF_P_RSRV_I are not exceeded. Egress frame references are available: REF_Q_RSRV_E or REF_P_RSRV_E are not exceeded. Shared frame references are available: None of REF_PRIO_SHR_E or REF_PRIO_SHR_I are exceeded. VMDS-10392 VSC7420-02, VSC7421-02, and VSC7422-02 Datasheet Revision 4.3 69 Functional Descriptions 4.8.4 Configuration Example This section provides an example of how the watermarks can be configured for a QoS-aware switch with no color handling and the effects of the settings. Table 52 • Watermark Configuration Example Watermark Value Comment BUF_Q_RSRV_I 500 bytes Guarantees that a port is capable of receiving at least one frame in all QoS classes. Note It is not necessary to assign a full MTU, because the watermarks are checked before the frame is added to the memory consumption. BUF_P_RSRV_I 0 No additional guarantees for the ingress port. BUF_Q_RSRV_E 200 bytes Guarantees that all QoS classes are capable of sending a non-congested stream of traffic through the switch. BUF_P_RSRV_E 10 kilobytes Guarantees that all egress ports have 10 kilobytes of buffer, independently of other traffic in the switch. This is the most demanding reservation in this setup, reserving 270 kilobytes of the total 512 kilobytes. BUF_COL_SHR_E BUF_COL_SHR_I Maximum Effectively disables frame coloring as watermark is never reached. BUF_PRIO_SHR_E 82 kilobytes to BUF_PRIO_SHR_I 103 kilobytes The different QoS classes are cut-off with 3 kilobytes distance (82, 85, 88, 91, 94, 97, 100, and 103 kilobytes). This gives frames with higher QoS classes a larger part of the shared buffer area. Effectively, this means that the burst capacity is 92 kilobytes for frames belonging to QoS class 0 and up to 113 kilobytes for frame belonging to QoS class 7. REF_Q_RSRV_E REF_Q_RSRV_I 4 For both ingress and egress, this guarantees that four frames can be pending from and to each port. REF_P_RSRV_E REF_P_RSRV_I 20 For both ingress and egress, this guarantees that an extra 20 frames can be pending, shared between all QoS classes within the port. REF_COL_SHR_E REF_COL_SHR_I Maximum Effectively disables frame coloring as watermark is never reached. REF_PRIO_SHR_E 2350 - 2700 REF_PRIO_SHR_I 4.8.5 The different QoS classes are cut-off with a distance of 50 frame references (2350, 2400, 2450, 2500, 2550, 2600, 2650, and 2700). This gives frames with higher QoS classes a larger part of the shared reference area. Watermark Programming and Consumption Monitoring The watermarks previously described are all found in the SYS::RES_CFG register. The register is replicated 1024 times. The following illustration the organization. VMDS-10392 VSC7420-02, VSC7421-02, and VSC7422-02 Datasheet Revision 4.3 70 Functional Descriptions Figure 21 • Watermark Layout 0 Port 0 Port 1 Port 2 8 ... 0 Port and QoS class reservation watermarks (xxx = Q_RSRV) 0 BUF_xxx_I 216 512 BUF_xxx_E 768 224 REF_xxx_E 253 QoS class sharing watermarks (xxx = PRIO_SHR) 0 1 2 3 4 5 6 7 Port 25 Port 26 208 256 REF_xxx_I QoS class QoS class QoS class QoS class QoS class QoS class QoS class QoS class QoS class QoS class QoS class QoS class QoS class QoS class QoS class QoS class Port reservation watermarks (xxx = P_RSRV) 0 1 2 3 4 5 6 7 Port 0 Port 1 Port 2 ... Port 25 Port 26 The illustration shows the watermarks available for the BUF_xxx_I group of watermarks. For the other groups of watermarks (BUF_xxx_I, REF_xxx_I, BUF_xxx_E, and REF_xxx_E), the exact same set of watermarks is available. For monitoring purposes, SYS::RES_STAT provides information about the resource consumption currently in use as well as the maximum consumption for corresponding watermarks. The information is available for each of the watermarks listed, and the layout of the RES_STAT register follows the layout of the watermarks. SYS::MMGT.FREECNT holds the amount of free memory in the shared queue system and SYS::EQ_CTRL.FP_FREE_CNT holds the number of free frame references in the shared queue system. 4.8.6 Advanced Resource Management A number of additional handles into the resource management system are available for special use of the device. They are described in the following table. Table 53 • Resource Management Resource Management Description Forced drop of egress frames SYS:PORT:EGR_DROP_FORCE. If an ingress port is in configured in flow control mode, frames received on the port are by default held back if one or more destination ports do not allow more data. However, if forced drop of egress frames is enabled for the egress port, frames are discarded. This could be enabled for the CPU port and for a mirror target port in order not to cause head-of-line blocking of non-congested traffic. Prevent ingress port from using of the shared resources. SYS:IGR_NO_SHARING. For frames received on ports set in this mask, the shared watermarks are considered exceeded. This prevents the port from using more resources than allowed by the reservation watermarks. VMDS-10392 VSC7420-02, VSC7421-02, and VSC7422-02 Datasheet Revision 4.3 71 Functional Descriptions Table 53 • 4.8.7 Resource Management (continued) Resource Management Description Prevent egress port from using of the shared resources. SYS:EGR_NO_SHARING. For frames switched to ports set in this mask the shared watermarks are considered exceeded. This prevents the port from using more resources than allowed by the reservation watermarks. Preferred sources SYS::EQ_PREFER_SRC. By default, ingress ports that have frames for transmission of equal QoS class are serviced in round robin. However, ingress ports marked in this mask are preferred over ingress ports not marked. Truncating SYS:PORT:EQ_TRUNCATE. Each egress queue can be configured to truncate frames to 92 bytes. Frames shorter than 92 bytes are not changed. This could be the enabled for a specific CPU extraction queue used for learning or a mirror target port where the first segment of the frames is sufficient for further frame processing. Prevent dequeuing SYS:PORT:PORT_MODE.DEQUEUE_DIS. Each egress port can disable dequeuing of frames from the egress queues. Ingress Pause Request Generation During resource depletion, the shared queue system either discards frames when the ingress port operates in drop mode, or holds back frames when the ingress port operates in flow control mode. The following describes special configuration for the flow control mode. The shared queue system is enabled for holding back frames during resource depletion in SYS:PORT:PAUSE_CFG.PAUSE_ENA. In addition, this enables the generation of pause requests to the port module based on memory consumptions. The MAC uses the pause request to generate pause frames or create back pressure collisions to halt the link partner. This is done according to the MAC configuration. For more information about MAC configuration, see MAC, page 12. The shared queue system generates the pause request based on the ingress port’s memory consumption and also based on the total memory consumption in the shared queue system. This enables a larger burst capacity for a port operating in flow control while not jeopardizing the non-dropping flow control. Generating the pause request partially depends on a memory consumption flag, TOT_PAUSE, which is set and cleared under the following conditions: • • The TOT_PAUSE flag is set when the total consumed memory in the shared queue system exceeds the SYS:PORT:PAUSE_TOT_CFG.PAUSE_TOT_START watermark. The TOT_PAUSE flag is cleared when the total consumed memory in the shared queue system is below the SYS:PORT:PAUSE_TOT_CFG.PAUSE_TOT_STOP watermark. The pause request is asserted when both of the following conditions are met: • • The TOT_PAUSE flag is set. The ingress port memory consumption exceeds the SYS:PORT:PAUSE_CFG.PAUSE_START watermark. The pause request is deasserted the following condition is met: • 4.8.8 The ingress port’s consumption is below the SYS:PORT:PAUSE_CFG.PAUSE_STOP watermark. Tail Dropping The shared queue system implements a tail dropping mechanism where incoming frames are discarded if the port’s memory consumption and the total memory consumption exceed certain watermarks. Tail VMDS-10392 VSC7420-02, VSC7421-02, and VSC7422-02 Datasheet Revision 4.3 72 Functional Descriptions dropping implies that the frame is discarded unconditionally. All ports in the device are subject to tail dropping. It is independent of whether the port is in flow control mode or drop mode. Tail dropping can be effective under special conditions. For example, tail dropping can prevent an ingress port from consuming all the shared memory when pause frames are lost or the link partner is not responding to pause frames. The shared queue system initiates tail dropping by discarding the incoming frame if the following two conditions are met at any point while writing the frame data to the memory: • • 4.8.9 The ingress port memory consumption exceeds the SYS:PORT:ATOP_CFG.ATOP watermark. The total consumed memory in the shared queue system exceeds the SYS:PORT:ATOP_TOT_CFG.ATOP_TOT watermark. Test Utilities This section describes some of test utilities that are built into the shared queue system. Each egress port can enable a frame repeater (SYS::REPEATER), which means that the head-of-line frames in the egress queues are transmitted but not dequeued after transmission. As a result, the scheduler sees the same frames again and again while the repeater function is active. The SYS:PORT:PORT_MODE.DEQUEUE_DIS disables both transmission and dequeuing from the egress queues when set. 4.8.10 Energy Efficient Ethernet This section provides information about the functions of Energy Efficient Ethernet in the shared queue system. The following tables lists the registers associated with Energy Efficient Ethernet. Table 54 • Energy Efficient Ethernet Control Registers Register Description Replication SYS:PORT:EEE_CFG Enabling and configuration of Energy Efficient Ethernet Per port SYS:EEE_THRES Configuration of thresholds (bytes None and frames) SYS::SW_STATUS.PORT_LPI Status bit indicating that egress port is in LPI state Per port The shared queue system supports Energy Efficient Ethernet (EEE) as defined by IEEE 802.3az by initiating the Low Power Idle (LPI) mode during periods of low link use. EEE is controlled per port by an egress queue state machine that monitors the queue fillings and ensures correct wake-up and sleep timing. The egress queue state machine is responsible for informing the connected PCS or internal PHY of changes in EEE states (active, sleep, low power idle, and wake up). Figure 22 • Low Power Idle Operation Active Low-Power Idle Active Tq Quiet Wake Ts Refresh Refresh Sleep Active Quiet Active Quiet Tr Energy Efficient Ethernet is enabled per port through SYS:PORT:EEE_CFG.EEE_ENA. VMDS-10392 VSC7420-02, VSC7421-02, and VSC7422-02 Datasheet Revision 4.3 73 Functional Descriptions By default, the egress port is transmitting enqueued data. This is the active state. If none of the port’s egress queues have enqueued data for the time specified in SYS:PORT:EEE_CFG.EEE_TIMER_HOLDOFF, the egress port instructs the PCS or internal PHY to enter the EEE sleep state. When data is enqueued in any of the port’s egress queues, a timer (SYS:PORT:EEE_CFG.EEE_TIMER_AGE) is started. When one of the following conditions is met, the port enters the wake up state: • • • • A queue specified as high priority (SYS:PORT:EEE_CFG.EEE_FAST_QUEUES) has any data to transmit. The total number of frames in the port’s egress queues exceeds SYS::EEE_THRESS.EEE_HIGH_FRAMES. The total number of bytes in the port’s egress queues exceeds SYS::EEE_THRESS.EEE_HIGH_FRAMES. The time specified in SYS:PORT:EEE_CFG.EEE_TIMER_AGE has passed. PCS and or the internal PHY is instructed to wake up. To ensure that PCS, PHY, and link partner are resynchronized; the egress port holds back transmission of data until the time specified in SYS:PORT:EEE_CFG.EEE_TIMER_WAKEUP has passed. After this time interval, the port resumes transmission of data. The status bit SYS::SW_STATUS.PORT_LPI is set while the egress port holds back data due to LPI (from the sleep state to the wake up state, both included). 4.9 Scheduler and Shaper The following table lists the registers associated with the scheduler and egress shaper control. Table 55 • Scheduler and Egress Shaper Control Registers Register Description Replication SYS::LB_DWRR_FRM_ADJ Configuration of gap value Common SYS::LB_DWRR_CFG Enabling of gap value adjustment for use in scheduler and shapers Per port SYS::SCH_DWRR_CFG Enabling of DWRR scheduler and configurations of costs Per port SYS::SCH_SHAPING_CTRL Enabling of shaping Per port SYS::SCH_LB_CTRL.LB_INIT Initialization of scheduler and shapers Common SYS::LB_THRES Configuration of shaper threshold Per shaper SYS::LB_RATE Configuration of shaper rate Per shaper Each egress port contains a scheduler and a set of egress shapers that control the read out from the egress queuing system to the associated port module. By default, the scheduler operates in strict priority. The egress queues are searched in the following prioritized order: Queue for QoS class 7 has highest priority followed by 6, 5, 4, 3, 2, 1, and 0. In addition, the scheduler can operate in a mixed mode, where queue 7 and queue 6 are strictly served and queues 5 through 0 operate in a deficit weighted round robin (DWRR) mode. In DWRR mode, QoS class queues 5 through 0 are given a weight and the scheduler selects frames from these queues according to the weights. Both the egress port and each of the egress queues have an associated leaky-bucket shaper. The egress port shaper is positioned towards the MAC and limits the overall transmission bandwidth on the port. Frames are only scheduled if the port shaper is open. The egress queue shapers control the input to the scheduler for each egress queue. Generally, the scheduler only searches an egress queue if the egress queue’s shaper is open. VMDS-10392 VSC7420-02, VSC7421-02, and VSC7422-02 Datasheet Revision 4.3 74 Functional Descriptions DWRR is used to guarantee queues a minimum share of the available bandwidth, and shaping is used to configure a maximum rate that cannot be exceeded. The following illustration shows the egress shapers and scheduler. Figure 23 • Egress Scheduler and Shapers Shapers Queue Q7 S Q6 S Q5 Q0 Wt_5 Wt_0 S S Port High Med D W R R Low S T R I C T S Queue Schedulers The overall scheduling algorithm is as follows: 1. 2. 3. If the port shaper is closed, no frames are scheduled. Frames are held back until the port shaper opens. If the port shaper is open, queues with an open queue shaper are candidates for scheduling. Queue 7 has highest priority followed by 6. Queues 5 through 0 may operate in strict mode or in the DWRR mode where each queue is weighted relatively to the other queues. Frames in a queue with a closed queue shaper are held back until the queue shaper opens. If no frames are scheduled during step 2, a second round of scheduling is performed. Queues programmed as work conserving and having a closed queue shaper become candidates for the second round of scheduling. The following are the configuration options for the shapers and scheduler. Each port is configured independently of other ports. Within a port, the following functionality can be enabled independently: • • • 4.9.1 DWRR mode (SCH_DWRR_CFG.DWRR_MODE): If set, queues 5 through 0 are scheduled according to the associated weights. Port shaping (SCH_SHAPING_CTRL.PORT_SHAPING_ENA): If set, the egress bandwidth is controlled by the port shaper settings. Per-queue shaping (SCH_SHAPING_CTRL.PRIO_SHAPING_ENA): If set for a queue, the queue shaper settings control the rate into the scheduler. Egress Shapers Each of the egress shapers (port and queues) contains a leaky bucket with the following configurations: • • Maximum rate – Specified in LB_RATE.LB_RATE in steps of 100160 bps. Maximum is 3.282 Gbps. Maximum burst size – Specified in LB_THRES.LB_THRES in steps of 4 kilobytes. Maximum is 252 kilobytes. The frame adjustment value LB_DWRR_FRM_ADJ.FRM_ADJ can be used to program the fixed number of extra bytes to add to each frame transmitted (irrespective of QoS class) in the shaper and DWRR calculations. A value of 20 bytes corresponds to line-rate calculation and accommodates for 12 bytes of inter-frame gap and 8 bytes of preamble. Data-rate based shaping and DWRR calculations are achieved by programming 0 bytes. Each port can enable the use of the frame adjustment value LB_DWRR_FRM_ADJ.FRM_ADJ through LB_DWRR_CFG.FRM_ADJ_ENA. If enabled on a port, both shapers and scheduler are affected. By default, while a queue shaper is closed, frames in the queue are not scheduled, even if none of the other queues have frames to transmit. Each queue can enable a work-conserving mode (SCH_SHAPING_CTRL.PRIO_LB_EXS_ENA) in which a second scheduling round is possible. If none of the queues with an open shaper have frames for transmission, work-conserving queues with closed shapers may get a share of the excess bandwidth. The sharing of the excess bandwidth obeys the same configured scheduling rules as for the first round of scheduling. VMDS-10392 VSC7420-02, VSC7421-02, and VSC7422-02 Datasheet Revision 4.3 75 Functional Descriptions The queue shapers implement two burst modes. By default, a leaky bucket is continuously assigned new credit according to the configured shaper rate (LB_RATE). This implies that during idle periods, credit is building up, which allows for a burst of data when the queue again has data to transmit. This is not convenient in an Audio/Video Bridging (AVB) environment where this behavior enforces a requirement for larger buffers in end-equipment. To circumvent this, each queue shaper can enable an AVB mode (SCH_SHAPING_CTRLPRIO_LB_AVB_ENA) in which credit is only assigned during periods where the queue shaper has data to transmit and is waiting for another queue to finish a transmission. This AVB mode prevents the accumulation of large amount of credits. The shapers must be initialized through SCH_LB_CTRL.LB_INIT before use. 4.9.2 Deficit Weighted Round Robin The DWRR uses a cost-based algorithm compared to a weight-based algorithm. A high cost implies a small share of the bandwidth. When the DWRR is enabled, each of queues 5 through 0 are programmed with a cost (SCH_DWRR_CFG.COST_CFG). A cost is a number between 1 and 32. The programmable DWRR costs determine the behavior of the DWRR algorithm. The costs result in weights for each queue. The weights are relative to one another, and the resulting share of the egress bandwidth for a particular QoS class is equal to the queue’s weight divided by the sum of all the queues’ weights. Costs are easily converted to weights and vice versa given the following two algorithms: Weights to Costs Given a desired set of weights (W0, W1, W2, W3, W4, W5), the costs can be calculated using the following algorithm: 1. 2. Set the cost of the queue with the smallest weight (Wsmallest) to cost 32. For any other queue Qn with weight Wn, set the corresponding cost Cn to: Cn = 32 × Wsmallest/Wn Costs to Weights Given a set of costs for all queues (C0, C1, C2, C3, C4, C5), the resulting weights can be calculated using the following algorithm: 1. 2. Set the weight of the queue with the highest cost (Chighest) to 1. For any other queue Qn with cost Cn, set the corresponding weight Wn to Wn = Chighest/Cn Cost and Weight Conversion Examples The following bandwidth distribution must be implemented: • • • • • • Queue 0: 5% (W0 = 5) Queue 1: 10% (W1 = 10) Queue 2: 15% (W2 = 15) Queue 3: 20% (W3 = 20) Queue 4: 20% (W4 = 20) Queue 5: 30% (W5 = 30) Given the algorithm to get from weights to costs, the following costs are calculated: • • • • • • C0 = 32 (Smallest weight) C1 = 32∗5/10 = 16 C2 = 32*5/15 = 10.67 (rounded up to 11) C3 = 32*5/20 = 8 C4 = 32*5/20 = 8 C5 = 32*5/30 = 5.33 (rounded down to 5) Due to the rounding off, these costs result in the following bandwidth distribution, which is slightly off compared to the desired distribution: • • • • • • Queue 0: 4.92% Queue 1: 9.85% Queue 2: 14.32% Queue 3: 19.70% Queue 4: 19.70% Queue 5: 31.51% VMDS-10392 VSC7420-02, VSC7421-02, and VSC7422-02 Datasheet Revision 4.3 76 Functional Descriptions 4.9.3 Shaping and DWRR Scheduling Examples This section provides examples and additional information about the use of the egress shapers and scheduler. Mixing DWRR and Shaping Example • • • • • • Port is shaped down to 500 Mbps. Queues 7 and 6 are strict while queue 5 through 0 are weighted. Queue 7 is shaped to 100 Mbps. Queue 6 is shaped to 50 Mbps. The following traffic distribution is desired for queue 5 through 0: Q0: 5%, Q1: 10%, Q2: 15%, Q3: 20%, Q4: 20%, Q5: 30% Each queue receives 125 Mbps of incoming traffic. The following table lists the DWRR configuration and the resulting egress bandwidth for the various queues. Table 56 • Example of Mixing DWRR and Shaping Queue Distribution of Weighted Traffic Configuration Costs/Weights (Cn/Wn) Result: Egress Bandwidth Q0 5% 32/1 1/(1+2+2.9+4+4+6.4) × (500 – Mbps – 150 Mbps) = 17.2 Mbps Q1 10% 16/2 2/(1+2+2.9+4+4+6.4) × (500 – Mbps – 150 Mbps) = 34.5 Mbps Q2 15% 11/2.9 2.9/(1+2+2.9+4+4+6.4) × (500 – Mbps – 50 Mbps) = 50.1 Mbps Q3 20% 8/4 4/(1+2+2.9+4+4+6.4) × (500 – Mbps – 150 Mbps) = 68.9 Mbps Q4 20% 8/4 4/(1+2+2.9+4+4+6.4) × (500 – Mbps – 150 Mbps) = 68.9 Mbps Q5 30% 5/6.4 6.4/(1+2+2.9+4+4+6.4) × (500 – Mbps – 150 Mbps) = 110.3 Mbps Q6 50 = Mbps Q7 100 = Mbps Sum: 100% 500 = Mbps Strict and Work-Conserving Shaping Example • • • • • Port is shaped down to 500 Mbps. All queues are strict. All queues are shaped to 50 Mbps. Queues 6 and 7 are work-conserving (allowed to use excess bandwidth). All queues receive 125 Mbps of traffic each. The following table lists the resulting egress bandwidth for the various queues. Table 57 • Example of Strict and Work-Conserving Shaping Queue Result: Egress Bandwidth Q0 50 Mbps Q1 50 Mbps Q2 50 Mbps Q3 50 Mbps Q4 50 Mbps Q5 50 Mbps Q6 75 Mbps (Gets the last 25 Mbps of the 100 Mbps in excess not used by queue 7) Q7 125 Mbps (Gets 75 Mbps of the 100 Mbps in excess limited only by the received rate) VMDS-10392 VSC7420-02, VSC7421-02, and VSC7422-02 Datasheet Revision 4.3 77 Functional Descriptions Table 57 • 4.10 Example of Strict and Work-Conserving Shaping (continued) Queue Result: Egress Bandwidth Sum: 500 Mbps Rewriter The switch core includes a rewriter common for all ports that determines how the egress frame is edited before transmitted. The rewriter performs the following editing: • • VLAN editing; tagging of frames and remapping of PCP and DEI. DSCP remarking; rewriting the DSCP value in IPv4 and IPv6 frames based on classified DSCP value. FCS updating. CPU extraction header insertion. • • Each port module including the CPU port module has its own set of configuration in the rewriter. Each frame is handled by the rewriter one time per destination port. 4.10.1 VLAN Editing The following table lists the registers associated with VLAN editing. Table 58 • VLAN Editing Registers Register Description Replication PORT_VLAN_CFG Port VLAN for egress port. Used for untagged set. Per port TAG_CFG Tagging rules for port tag Per port PCP_DEI_QOS_MAP_CFG Mapping table. Maps QoS class to Per port per new PCP and DEI values. QoS The rewriter initially pops the number of VLAN tags specified by the VLAN_POP_CNT parameter received with the frame from the classifier. One VLAN tag can be popped. The rewriter itself does not influence the number of VLAN tags being popped. After popping the VLAN tags, the rewriter decides whether to push zero or one new VLAN tag to the outgoing frame according to the port’s tagging configuration in register TAG_CFG The following table lists the possible tagging combinations: Table 59 • Tagging Combinations TAG_CFG.TAG_CFG Tagging action 0 No tagging. 1 Tag all frames according to the port’s tagging configuration. Do not tag if VID=0 or VID=PORT_VLAN.PORT_VID. 2 Tag all frames according to the port’s tagging configuration. Do not tag if VID=0. 3 Tag all frames according to the port’s tagging configuration. When adding a VLAN tag, the contents of the tag header, including the TPID, is highly programmable. The starting point is the classified tag header coming from the analyzer containing a PCP, DEI, VID and tag type. For each of the fields in the resulting tag, it is programmable how the value is determined. For the port tag, the following options are available: Port tag: PCP and DEI VMDS-10392 VSC7420-02, VSC7421-02, and VSC7422-02 Datasheet Revision 4.3 78 Functional Descriptions • • • • Use the classified values. Use the egress port’s port VLAN (PORT_VLAN.PORT_PCP, PORT_VLAN.PORT_DEI). Map the QoS class to a new set of PCP and DEI using the per-port table PCP_DEI_QOS_MAP_CFG. Set the DEI to the DP level, independently of the preceding PCP and DEI configurations. Port Tag: VID • Use the classified VID. Port Tag: TPID • • • • 4.10.2 Use Ethernet type 0x8100 (C-tag) Use Ethernet type 0x88A8 (S-tag) Use custom Ethernet type programmed in PORT_VLAN.PORT_TPID. Use custom Ethernet type programmed in PORT_VLAN.PORT_TPID unless the incoming tag was a C-tag. DSCP Remarking The following table lists the registers associated with DSCP remarking. Table 60 • DSCP Remarking Registers Register Description Replication DSCP_CFG Selects how the DSCP remarking Per port is done DSCP_REMAP_CFG Mapping table from DSCP to DSCP. None The rewriter can remark the DSCP value in IPv4 and IPv6 frames, that is, write a new DSCP value to the DSCP field in the frame. If a port is enabled for DSCP remarking (DSCP_CFG.DSCP_REWR_CFG), the new DSCP value is derived by using the classified DSCP value from the classifier in the ingress port. This DSCP value can be mapped before replacing the existing value in the frame. The following options are available: • • • No DSCP remarking - Leave the DSCP value in the frame untouched. Update the DSCP value in the frame with the value received from the analyzer Update the DSCP value in the frame with the value received from the analyzer remapped through DSCP_REMAP_CFG. Additionally, the IP checksum is updated for IPv4 frames. Note that the IPv6 header does not contain a checksum. As a result, checksum updating does not apply for IPv6 frames. 4.10.3 FCS Updating The following table lists the registers associated with FCS updating. Table 61 • FCS Updating Registers Register Description Replication PORT_CFG.FCS_UPDATE_NONC FCS update configuration for PU_CFG non-CPU injected frames. Per port PORT_CFG.FCS_UPDATE_CPU_E FCS update configuration for NA CPU injected frames. Per port The rewriter updates a frame’s FCS when required or instructed to do so. Different handling is available for frames injected by the CPU and for all other frames. For non-CPU injected frames, the following update options are available: • Never update the FCS. VMDS-10392 VSC7420-02, VSC7421-02, and VSC7422-02 Datasheet Revision 4.3 79 Functional Descriptions • • Conditional update - Update the FCS if the frame was modified due to VLAN tagging or DSCP remarking. Always update the FCS. Additionally, the rewriter can update the FCS for all frames injected from the CPU through the CPU injection queues in the CPU port module: • • 4.10.4 Never update the FCS. Always update the FCS. CPU Extraction Header Insertion The following table lists the registers associated with CPU extraction header insertion. Table 62 • CPU Extraction Header Insertion Registers Register Description Replication PORT_CFG.IFH_INSERT_ENA Enables insertion of the CPU extraction header. Per port PORT_CFG.IFH_INSERT_MODE Configures the position of the CPU Per port extraction header. Any port in the switch core can request the rewriter to insert a CPU extraction header in the frame before transmission. For more information about the contents of the CPU extraction header, see CPU Extraction and Injection, page 162. The CPU extraction header can be placed before the DMAC or right after the SMAC. When inserting the header, the frame is extended with eight bytes. Note that the FCS is only updated when the header is inserted after the SMAC. The insertion of the CPU extraction header is the last editing in the rewriter. This implies that any VLAN tags in the frame will appear after the extraction header. 4.11 CPU Port Module The CPU port module connects the switch core to the CPU system so that frames can be injected from or extracted to the CPU. It is also possible to use a regular front port as a CPU port. This is known as a Network Processor Interface (NPI). The following illustration shows how the switch core interfaces to the CPU system through the CPU port module for injection and extraction of frames. VMDS-10392 VSC7420-02, VSC7421-02, and VSC7422-02 Datasheet Revision 4.3 80 Functional Descriptions Figure 24 • CPU Injection And Extraction Extraction Register access Injection Group 0 Injection Group 1 CPU Port 26 CPU Port 27 Injection header included? (SYS:PORT:PORT_MODE.INCL_I NJ_HDR) Switch Core Switch Core FDMA Switch port 26 CPU extraction queues CPU Port Module CPU Port Module Device CPU Injection Queue to port mapping (SYS::SCH_CPU.SCH_CPU_MAP) Strict/Round robin (SYS::SCH_CPU.SCH_CPU_RR) CPU Port 26 CPU Port 27 Rewriter Rewriter Extraction header included? (REW:PORT:PORT_CFG.IFH_INSERT_ENA ) CPU Queue 0 Switch port 26 CPU Queue 1 Switch port 26, QoS class 0-7 Device CPU Switch Core Analyzer Queue to group mapping (DEVCPU_QS::XTR_MAP.GRP) Extraction Group 0 Extraction Group 1 Fixed per channel FDMA 4.11.1 Register access Frame Extraction The following table lists the registers associated with frame extraction. Table 63 • Register Frame Extraction Registers Description Replication SYS::SCH_CPU.SCH_CPU_MA Configuration of mapping of Per CPU port P extraction queues to CPU ports (ports 26 and 27) SYS::SCH_CPU.SCH_CPU_RR Configuration of CPU scheduler Per CPU port (ports 26 and 27) REW:PORT:PORT_CFG.IFG_IN Enables insertion of extraction SERT_ENA header Per CPU port (port 26 and 27) In the switch core, extracted frames are forwarded to one of the eight CPU extraction queues. Each of these queues is mapped to one of two CPU ports (port 26 and port 27) through SYS::SCH_CPU.SCH_CPU_MAP. For each CPU port, there is a scheduler working either in strict mode VMDS-10392 VSC7420-02, VSC7421-02, and VSC7422-02 Datasheet Revision 4.3 81 Functional Descriptions or round robin, which selects between the CPU extraction queues mapped to the same CPU port (SYS::SCH_CPU.SCH_CPU_RR). In strict mode, higher queue numbers are preferred over smaller queue numbers. In round robin, all queue are serviced one after another. The two CPU ports contain the same rewriter as regular front ports. The rewriter modifies the frames before sending them to the CPU. In particular, the rewriter inserts an extraction header (REW::PORT:PORT_CFG.IFH_INSERT_ENA), which contains relevant side band information about the frame such as the frame’s classification result (VLAN tag information, DSCP, QoS class) and the reason for sending the frame to the CPU. For more information about the rewriter, see Rewriter, page 78. The device CPU contains the functionality for reading out the frames. This can be done through the frame DMA or regular register access. The following table lists the contents of the CPU extraction header. Table 64 • CPU Extraction Header Field Bit Width Description SIGNATURE 56 8 Must be 0xFF. SRC_PORT 51 5 The port number where the frame was received (0-26). DSCP 45 6 The frame’s classified DSCP value. RESERVED 38 8 Unused. SFLOW_ID 32 5 sFlow sampling ID. 0-26: Frame was SFlow sampled by a Tx sampler on port given by SFLOW_ID. 27: Frame was SFlow sampled by an RX sampler on port given by SRC_PORT. 28-30: Reserved. 31: Frame was not SFlow sampled. RESERVED 30 2 Unused. LRN_FLAGS 28 2 The source MAC address learning action triggered by the frame. 0: No learning. 1: Learning of a new entry. 2: Updating of an already learned unlocked entry. 3: Updating of an already learned locked entry. CPU_QUEUE 20 8 CPU extraction queue mask (one bit per CPU extraction queue). Each bit set implies the frame was subjected to CPU forwarding to the specific queue. QOS_CLASS 17 3 The frame’s classified QoS class. TAG_TYPE 16 1 The tag information’s associated Tag Protocol Identifier (TPID). The definitions are: 0: C-tag: EtherType = 0x8100. 1: S-tag: EtherType = 0x88A8 or custom value. PCP 13 3 The frame’s classified PCP. DEI 12 1 The frame’s classified DEI. VID 0 12 The frame’s classified VID. VMDS-10392 VSC7420-02, VSC7421-02, and VSC7422-02 Datasheet Revision 4.3 82 Functional Descriptions 4.11.2 Frame Injection The following table lists the registers associated with frame injection. Table 65 • Frame Injection Registers Register Description Replication SYS:PORT:PORT_MODE.INCL_I NJ_HDR Enable parsing of injection header Per CPU port (ports 26 and 27) SYS:PORT:EQ_PREFER_SRC Enable preferred arbitration of the CPU port (port 26) over front ports CPU port (port 26 only) The CPU injects frames through the two CPU injection groups independent of each other. The injection groups connect to the two CPU ports (port 26 and port 27) in the CPU port module. In CPU port module, each of the two CPU ports have dedicated access to the switch core. Inside the switch core, all CPU injected frames are seen as coming from CPU port (port 26). This implies that both CPU injection groups consume memory resources from the shared queue system for port 26 and that analyzer configuration for port 26 are applied to all frames. In the switch core, the CPU port can be preferred over other ingress ports when transferring frames to egress queues by enabling precedence of the CPU port (SYS::EQ_PREFER_SRC). The first eight bytes of a frame written to a CPU injection group is an injection header containing relevant side band information about how the frame must be processed by the switch core. The CPU ports must be enabled to expect the CPU injection header (SYS:PORT:INCL_INJ_HDR). On a per-frame basis, the CPU controls whether frames injected through the CPU port module are processed by the analyzer. If the frame is processed by the analyzer, it is sent through the processing steps to calculate the destination ports for the frame. If analyzer processing is not selected, the CPU can specify the destination port set and related information to fully control the forwarding of the frame. For more information about the analyzer’s processing steps, see Forwarding Engine, page 55. The contents of the CPU injection header is listed in the following table. Table 66 • CPU Injection Header Field Bit Width Description BYPASS 63 1 When this bit is set, the analyzer processing is skipped for this frame. The destination set is specified in DEST and CPU_QUEUE. Forwarding uses the QOS_CLASS, and the rewriter uses the tag information (POP_CNT, TAG_TYPE, PCP, DEI, VID) for rewriting actions. When this bit is cleared, the analyzer determines the destination set, QoS class, and VLAN classification for the frame through normal frame processing including lookups in the MAC table and VLAN table. RESERVED 59 4 Unused. DEST 32 27 This is the destination set for the frame. DEST[26] is the CPU. Used when BYPASS = 1. RESERVED 30 2 Unused. VMDS-10392 VSC7420-02, VSC7421-02, and VSC7422-02 Datasheet Revision 4.3 83 Functional Descriptions Table 66 • 4.11.3 CPU Injection Header (continued) Field Bit Width Description POP_CNT 28 2 Number of VLAN tags that must be popped in the rewriter before adding new tags. Used when BYPASS = 1. 0: No tags must be popped. 1: One tag must be popped. 2: Two tags must be popped. 3: Disable rewriting of VLAN tags and DSCP value. The FCS is still updated. CPU_QUEUE 20 8 CPU extraction queue mask (one bit per CPU extraction queue). Each bit set implies the frame must be forwarded by the CPU to the specific queue. Used when BYPASS = 1 and DEST[26] = 1. QOS_CLASS 17 3 The frame’s classified QoS class. Used when BYPASS = 1. TAG_TYPE 16 1 The tag information’s associated Tag Protocol Identifier (TPID). Used when BYPASS = 1. 0: C-tag: EtherType = 0x8100. 1: S-tag: EtherType = 0x88A8 or custom value. PCP 13 3 The frame’s classified PCP. Used when BYPASS = 1. DEI 12 1 The frame’s classified DEI. Used when BYPASS = 1. VID 0 12 The frame’s classified VID. Used when BYPASS = 1. Network Processor Interface (NPI) The following table lists the registers associated with the network processor interface. Table 67 • Network Processor Interface Registers Register Description Replication SYS::EXT_CPU_CFG None Configuration of the NPI port number and configuration of which CPU extraction queues are redirected to the NPI. REW:PORT:PORT_CFG.IFG_INS Enables insertion of extraction ERT_ENA header Per port SYS:PORT:PORT_MODE.INCL_I NJ_HDR Per port Configuration of NPI ingress mode. Any front port can be configured as a network processor interface through which frames can be injected from and extracted to an external CPU. Only one port can be an NPI at the same time. SYS::EXT_CPU_CFG.EXT_CPU_PORT holds the port number of the NPI. A dual CPU system is possible where both the internal and the external CPU are active at the same time. Through SYS::EXT_CPU_CFG.EXT_CPUQ_MSK, it is configurable to which of the eight CPU extraction queues are directed to the internal CPU and which are directed to external CPU. A frame can be extracted to both the internal CPU and the external CPU if the frame is extracted for multiple reasons. A frames being extracted to the external CPU can have the CPU extraction header inserted in front of the frame (REW:PORT:PORT_CFG.IFG_INSERT_ENA), and a frame being injected to the switch core can have the CPU injection header inserted in front of the frame (SYS:PORT:PORT_MODE.INCL_INJ_HDR). VMDS-10392 VSC7420-02, VSC7421-02, and VSC7422-02 Datasheet Revision 4.3 84 Functional Descriptions Through the BYPASS field in the CPU injection header, the external CPU can control forwarding of injected frames by either letting the frame analyze and forward accordingly or directly specifying the destination set 4.12 Clocking and Reset The following table lists the registers associated with clocking and reset. Table 68 • Clocking and Reset Registers Target:Register_group:Register.field Description Replication HSIO::PLL5G_STATUS0 LCPLL status None DEVCPU_GCB:: SOFT_CHIP_RST Reset of the internal copper PHYs or the entire device None DEVCPU_GCB::SOFT_DEVCPU_RST Reset of the extraction and injection modules None CFG::RESET None CPU reset configuration The LCPLL provides the clocks used by the SerDes, the central part of the switch core, and the VCore-Ie CPU system. The reference clock for the LCPLL (REFCLK_P and REFCLK_N pins) is either differential or singleended. The frequency can be 25 MHz, 125 MHz, or 156.25 MHz. For more information about the reference clock frequency selections, see the Pins by Function section for the appropriate device. For more information about reference clock options, see Reference Clock, page 589. A global software reset is performed with DEVCPU_GCB::SOFT_CHIP_RST. For more information about the configuration of the CPU frequency and software reset options when using the V-Core-III, see Clocking and Reset, page 88. For more information about the clock and reset configuration for the Ethernet interfaces in the port modules, see MAC, page 12, and SERDES6G, page 18. The MAC clock domains are not included in the global reset. VMDS-10392 VSC7420-02, VSC7421-02, and VSC7422-02 Datasheet Revision 4.3 85 VCore-Ie System and CPU Interface 5 VCore-Ie System and CPU Interface This section provides information about the functional aspects of blocks and the interfaces related to the VCore-Ie on-chip microprocessor system. The VSC7420-02, VSC7421-02, and VSC7422-02 devices contain a fast VCore-Ie CPU system that is based on an embedded 8051-compatible microprocessor. The VCore-Ie system can control the device independently or it can support an external CPU, relieving the external CPU of the otherwise timeconsuming tasks of transferring frames, maintaining the switch core, and handling networking protocols. When the VCore-Ie CPU is enabled, it either boots up independently from Flash or a code-image can be manually loaded and started from an external CPU. An external CPU can be connected to the VSC7420-02, VSC7421-02, and VSC7422-02 devices through the serial interface (SI) or dedicated MIIM slave interface. When the VCore-Ie CPU is enabled and boots up from Flash, the SI is reserved as boot interface and cannot be used by an external CPU. The VCore-Ie CPU and the external CPUs can access internal chip registers for configuration, monitoring, and collecting statistics. The VCore-Ie system includes a number of functional blocks and registers that are tightly coupled to the VCore-Ie CPU. The external CPU can access these blocks and register through an indirect addressing scheme. The registers are available when the VCore-Ie CPU is enabled or disabled. The following illustration shows how the serial controller operates in either master or slave mode. When the VCore-Ie CPU is enabled, it forces the boot interface to master mode. An interface in slave mode allows an external CPU access to register targets inside the device. VMDS-10392 VSC7420-02, VSC7421-02, and VSC7422-02 Datasheet Revision 4.3 86 VCore-Ie System and CPU Interface 8051 SFR 64 KB Code/Data CPU Registers Arbiter Slave Flash Master Debug - or External CPU Figure 25 • VCore-Ie System Block Diagram Various I/Os Fan control MIIM master GPIO, SGPIO UART Serial (SPI) Controller Shared Bus (32-Bit Address Space) Target Access VCore-Ie System tgt:z registers tgt:b registers Fast Registers for Manual Extraction/Injection Switch Core Register Targets tgt:a registers Arbiter Switch Core QS Interface 5.1 VCore-Ie Configurations The following table summarizes the possible VCore-Ie configurations. Table 69 • VCore-Ie Configurations Level of Strapping Pins VCORE_CFG[2] VCORE_CFG[1] VCORE_CFG[0] Behavior Don’t care 0 0 The 8051 is enabled and boots from SI. VMDS-10392 VSC7420-02, VSC7421-02, and VSC7422-02 Datasheet Revision 4.3 87 VCore-Ie System and CPU Interface Table 69 • VCore-Ie Configurations (continued) Level of Strapping Pins VCORE_CFG[2] VCORE_CFG[1] VCORE_CFG[0] Behavior Don’t care 0 1 Automatic boot is disabled by forcing the 8051 into reset. SI slave mode is enabled. The 8051 can be manually started from the on-chip RAM. Don’t care 1 1 Automatic boot is disabled by forcing the 8051 into reset. MIIM and SI slave modes are enabled. The 8051 can be manually started from the on-chip RAM. The VCore-Ie CPU can boot up automatically and then hand over ownership of the SI to an external CPU (after it boots up from SI Flash). 5.2 Clocking and Reset The following table lists the registers associated with clocking and reset. Table 70 • Clocking and Reset Configuration Registers Register Description RESET VCore-Ie reset configuration and release of specific blocks from reset SOFT_CHIP_RST Resets configuration WDT Watchdog timer configuration and status The frequency of the VCore-Ie CPU is 250 MHz, and the frequency of the VCore-Ie system is 125 MHz. The VCore-Ie CPU (including the VCore-Ie system) can be soft-reset by setting RESET.CORE_RST_FORCE. By default, this resets both the VCore-Ie CPU and the VCore-Ie system. The VCore-Ie system can be excluded from a soft reset by setting RESET.CORE_RST_CPU_ONLY;softreset using CORE_RST_FORCE only then resets the VCore-Ie CPU. The VSC7420-02, VSC7421-02, and VSC7422-02 devices can be soft-reset by using SOFT_CHIP_RST.SOFT_CHIP_RST, which by default, resets the entire device. The VCore-Ie system and CPU can be protected from a chip-level soft reset by configuring RESET.CORE_RST_PROTECT. In this case, a chip-level soft reset is applied to all other blocks except the VCore-Ie system and CPU. The GPIO alternate modes are reset to the default values when performing chip-level soft reset. This must be taken into account when the VCore-Ie system is protected from chip-level soft reset (by means of RESET.CORE_RST_PROTECT). When automatic booting of the VCore-Ie CPU is disabled using the VCORE_CFG pins, the VCore-Ie CPU can be manually released through RESET.CPU_RELEASE. 5.2.1 Watchdog Timer The VCore-Ie system has a built-in watchdog timer (WDT) with a time-out cycle of two seconds. The watchdog timer is enabled, disabled, or reset through the WDT register. The watchdog timer is disabled by default. After the watchdog timer is enabled, it must be regularly reset by software. Otherwise, it times out and causes a VCore-Ie soft reset equivalent to setting RESET.CORE_RST_FORCE. Improper use of the WDT.WDT_LOCK causes an immediate timeout-reset as if the watchdog timer had run out. The VMDS-10392 VSC7420-02, VSC7421-02, and VSC7422-02 Datasheet Revision 4.3 88 VCore-Ie System and CPU Interface WDT.WDT_STATUS field shows if the last VCore-Ie CPU reset was caused by WDT timeout (or improper locking sequence). The WDT.WDT_STATUS field is updated only during VCore-Ie CPU reset. To enable or to reset the watchdog timer, write the locking sequence, as described in WDT.WDT_LOCK, at the same time as setting the WDT.WDT_ENABLE field. Because watchdog timeout is equivalent to setting RESET.CORE_RST_FORCE, the RESET.CORE_RST_CPU_ONLY field also applies to watchdog initiated soft reset. 5.3 Shared Bus The following table lists the registers associated with the shared bus. Table 71 • Shared Bus Configuration Registers Register Description PL1, PL2, PL3 Master priorities The shared bus is a 32-bit address and 32-bit data bus with dedicated master and slave interfaces that interconnect all blocks in the VCore-Ie system. The VCore-Ie CPU and external CPU are masters on the shared bus and only they can start access on the bus. The shared bus uses byte addresses, and transfers of 8, 16, or 32 bits can be made. For 16-bit and 32bit access, the addresses must be aligned to 16-bit and 32-bit addresses, respectively. To increase performance, bursting of multiple 32-bit words on the shared bus can be performed. All slaves are mapped into the VCore-Ie system’s 32-bit address space and can be accessed directly by masters on the shared bus. The address space of the shared bus is considerably wider than what the 8051 can access directly. However, by using custom special function registers, which is part of the Microsemi 8051 implementation, reads and writes can be done in the complete VCore-Ie shared bus region. For more information, see VCore-Ie CPU, page 91. The following illustration shows the mapping of the shared bus memory. Figure 26 • Shared Bus Memory Map 0x00000000 0x10000000 Memory Map 256 MB SI Controller 1.25 GB Reserved 0x60000000 256 MB Switch Core Registers 0x70000000 256 MB 0x80000000 VCore-I Registers 2 GB Reserved 0xFFFFFFFF 5.3.1 Shared Bus Arbitration The VCore-Ie shared bus arbitrates between masters that want to access the bus; the default is to use a strict prioritized arbitration scheme where the VCore-Ie CPU has highest priority. Priorities can be changed using registers PL1 though PL3. VMDS-10392 VSC7420-02, VSC7421-02, and VSC7422-02 Datasheet Revision 4.3 89 VCore-Ie System and CPU Interface 5.3.2 SI Memory Region This section provides information about the functional aspects of the serial interface (SI) in master mode. For information about using an external CPU to access register targets using the serial interface, see Serial Interface in Slave Mode, page 101. The following table lists the registers associated with the SI controller. Table 72 • SI Controller Configuration Registers Register Description SPI_MST_CFG Serial interface speed SW_MODE Manual control of the serial interface pins When the VCore-Ie system controls the SI, reading from the SI controller’s memory region is automatically converted to read access on the SI. The SI supports one 24-address bit Flash device. The VCore-Ie CPU can execute code directly from Flash by executing from the SI controller's memory region. The SI controller accepts 8-bit, 16-bit, and 32-bit read access with or without bursting, byte address n in the SI controller’s memory region maps directly to byte address n inside the SPI Flash. Writing to the SI requires manual control of the SI pins using software. Setting SW_MODE.SW_PIN_CTRL_MODE places all SI pins under software control. Output enable and the value of SI_Clk, SI_DO, SI_nEn are controlled using the SW_MODE register. The value of the SI_DI pin is available through SW_MODE.SW_SPI_SDI. Note The VCore-Ie CPU cannot execute code directly from the SI controller’s memory region while simultaneously writing to the serial interface. The following table lists the serial interface pins. Table 73 • Serial Interface Pins Pin Name I/O Description SI_nEN O Active low chip select. SI_Clk O Clock output. SI_DO O Data output (MOSI). SI_DI I Data output (MISO). The SI controller does speculative perfecting of data. After reading address n, the SI controller automatically continues reading address n + 1, so that the next value is ready if or when requested by the VCore-Ie CPU. This greatly optimizes reading from sequential addresses in the Flash, such as when copying data from Flash into program memory. Figure 27 • SI Read Timing in Normal Mode SI_nEn SI_Clk 2 2 2 2 1 1 1 1 1 1 1 1 1 1 9 8 7 6 5 4 3 2 1 0 3 2 1 0 9 8 7 6 5 4 3 2 1 0 SI_DO READ SI_DI 24-Bit Address 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 Data Byte #0 Data Byte #1 Data Byte #2 VMDS-10392 VSC7420-02, VSC7421-02, and VSC7422-02 Datasheet Revision 4.3 Data Byte #3 90 VCore-Ie System and CPU Interface Figure 28 • SI Read Timing in Fast Mode SI_nEn SI_Clk 2 2 2 2 1 1 1 1 1 1 1 1 1 1 9 8 7 6 5 4 3 2 1 0 3 2 1 0 9 8 7 6 5 4 3 2 1 0 SI_DO FAST_READ 24-Bit Address SI_DI Dummy Byte 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 Data Byte #0 Data Byte #1 Data Byte #2 Data Byte #3 The default timing of the SI controller operates with most serial interface Flash devices. Use the following process to calculate the optimized SI parameters for a specific SI device: 1. 2. 3. Calculate an appropriate frequency divider value as described in SPI_MST_CFG.CLK_DIV. The SI operates at no more than 25 MHz, and the maximum frequency of the SPI device must not be exceeded. For information about the VCore-Ie system frequency, see Clocking and Reset, page 88. The SPI device may require a FAST_READ command rather than normal READ when the SI frequency is increased. Setting SPI_MST_CFG.FAST_READ_ENA makes the SI controller use FAST_READ commands. Calculate SPI_MST_CFG.CS_DESELECT_TIME so that it matches how long the SPI device requires chip-select to be deasserted between accesses. This value depends on the SI clock period that results from the SPI_MST_CFG.CLK_DIV setting. These parameters must be written to SPI_MST_CFG. The CLK_DIV field must either be written last or at the same time as the other parameters. The SPI_MST_CFG register can be configured while also booting up from the SI. When the VCore CPU boots from the SI interface, the default values of the SPI_MST_CFG register are used until the SI_MST_CFG is reconfigured with optimized parameters. This implies that SI_Clk is operating at approximately 4 MHz, with normal read instructions, and maximum gap between chip select operations to the Flash. 5.3.3 Switch Core Registers Memory Region Register targets in the Switch Core are memory-mapped into the Switch Core registers region of the shared bus memory map. All registers are 32-bit wide and must only be accessed using 32-bit reads and writes. Bursts are supported. Writes to this region are buffered (there is a one-word write buffer). Multiple back-to-back write access pauses the shared bus until the write buffer is freed up (until the previous writes are done). Reads from this region pause the shared bus until read data is available. Registers in the 0x60000000 though 0x6FFFFFFF region in the 0x6 targets are physically located in other areas of the device rather than the VCore-Ie system; reading from these targets may take up to 1.1 µs in a single master system. For more information, see Register Access and Multimaster Systems, page 101. 5.3.4 VCore-Ie Registers Memory Region Registers inside the VCore-Ie domain are memory mapped into the VCore-Ie registers region of the shared bus memory map. All registers are 32-bit wide and must only be accessed using 32-bit reads and writes, bursts are supported. The registers in the 0x70000000 though 0x7FFFFFFF region are all placed inside the VCore-Ie, read and write access to these registers is fast (done in a few clock cycles). 5.4 VCore-Ie CPU The VCore-Ie CPU system is based on a fast, embedded 8051-compatible microprocessor. When automatic boot is enabled using the VCORE_CFG strapping pins, the VCore-Ie CPU automatically starts to execute code in the Flash at byte address 0 in the SI controller region. VMDS-10392 VSC7420-02, VSC7421-02, and VSC7422-02 Datasheet Revision 4.3 91 VCore-Ie System and CPU Interface A typical automatic boot sequence is as follows: 1. 2. 3. 4. Configure the appropriate VCore-Ie CPU frequency the same as for clocking and reset. For more information about supported clock frequencies, see Clocking and Reset, page 88. The maximum frequency for the VCore-Ie CPU is 208.33 MHz. Speed up the boot interface. For more information, see Shared Bus, page 89. Copy code-image from the Flash to on-chip memory. For more information, see Loading On-chip Memory, page 94. Map on-chip memory. For more information, see Mapping On-chip Memory, page 95. When automatic boot is disabled, an external CPU can start the VCore-Ie CPU through the registers. A typical manual boot-up sequence is as follows: 1. 2. 3. Load on-chip memory with code-image. For more information, see Loading On-chip Memory, page 94. Map on-chip memory. For more information, see Mapping On-chip Memory, page 95. Configure appropriate VCore-Ie CPU frequency and release reset to the VCore-Ie CPU. For more information, see Clocking and Reset, page 88. Note When manually booting up, the size of the code image is limited by the size of the on-chip memory. However, when automatically booting up from Flash, the VCore-Ie CPU can use paging to access code and data for a total of up to 16 megabytes. For more information, see Paged Access to VCore-Ie Shared Bus, page 96. Figure 29 • VCore-Ie Block Diagram int0_n VCore-Ie CPU interrupts SP IF On-chip Scratchpad Memory 256 Bytes SFR int1_n SFR IF 64 KB clk DATA IF On-chip RAM Code/Data 8051 Clock Gating CODE IF VCore-Ie CPU clock MMU Shared Bus Master MMAP SBA Access VCore-Ie registers Shared Bus The preceding illustration shows the basic blocks of the VCore-Ie 8051 implementation. The illustration highlights features such as: • • • • • • VCore-Ie CPU frequency of 250 MHz. Advanced clock gating control that automatically pauses the 8051 during shared bus access. Two independent interrupts from dedicated VCore-Ie interrupt controller allows interrupts from all major VCore-Ie blocks, including timers, UART, and hardware based semaphores (for communication with external CPU). On-chip 256-byte scratchpad. The lower 128 bytes are directly and indirectly addressable. The upper 128 bytes are indirectly addressable. Simple Memory Management Unit maps 8051’s code and data access to either on-chip memory or shared bus (with support for paging). Custom SFR registers allows access to the full 32-bit address space of the shared bus, direct control of the MMU, and other features. VMDS-10392 VSC7420-02, VSC7421-02, and VSC7422-02 Datasheet Revision 4.3 92 VCore-Ie System and CPU Interface • Easy debugging and development of software using an external CPU through dedicated status registers in the VCore-Ie system domain. For more information, Software Debug and Development, page 97. The UART and three timers have been moved out of the 8051 and into the general VCore-Ie register domain so that they are unaffected by the clock gating of the VCore-Ie CPU. The SFR registers related to timers and UART have been removed from the list of SFR registers. For more information on how to use the VCore-Ie system UART and timers, see UART, page 108 and Timers, page 108. The following table lists the available VCore-Ie CPU SFR registers and associated register fields. A “-” means that the register field is available for general read and write access, and a 0 or 1 means that the register field is reserved. When writing reserved register fields, these must be set to 0 or 1, as indicated in the table. Table 74 • Special Function Registers (SFR) Register Addr Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 GPR(1) 0x80 - - - - - - - - SP 0x81 - - - - - - - - DPL 0x82 - - - - - - - - DPH 0x83 - - - - - - - - PCON 0x87 - - 1 1 GF1 GF0 STOP IDLE TCON 0x88 0 0 0 0 IE1 IT1 IE0 IT0 MPAGE(1) 0x92 - - - - - - - - PG(1) 0xB0 IFP3 IFP2 IFP1 IFP0 OP3 OP2 OP1 OP0 EPG(1) 0xC0 EIFP3 EIFP2 EIFP1 EIFP0 EOP3 EOP2 EOP1 EOP0 PSW 0xD0 CY AC F0 RS1 RS0 0V F1 P ACC 0xE0 - - - - - - - - B 0xF0 - - - - - - - - MMAP(1) 0xF2 ACH ACL ADH ADL MCH MCL MDH MDL RA_AD0_RD(1) 0xF6 - - - - - - 0 0 RA_AD0_WR(1) 0xF7 - - - - - - 0 0 RA_AD1(1) 0xF9 - - - - - - - - RA_AD2(1) 0xFA - - - - - - - - RA_AD3(1) 0xFB - - - - - - - - RA_DA0(1) 0xFC - - - - - - - - RA_DA1(1) 0xFD - - - - - - - - RA_DA2(1) 0xFE - - - - - - - - RA_DA3(1) 0xFF - - - - - - - - 1. This register is not part of the standard 8051 implementation. The SFR::GPR register is an 8-bit general-purpose register. The value of this register is available to external CPU through ICPU_CFG::MPU8051_STAT.MPU8051_GPR. The contents of the SFR::MPAGE register are used for the upper eight address bits during “MOVX A, @Ri” and “MOVX @Ri, A” instructions. For legacy 8051 designs, the MPAGE register replaces the Port2-Latch. To enable memory access instructions (“MOVX A, @Ri"“ and “MOVX @Ri, A”), SFR register 0x8E must be written to 0 (“MOV 0x8E, #0x00”). For more information about the SFR::MMAP register, see Mapping On-chip Memory, page 95. VMDS-10392 VSC7420-02, VSC7421-02, and VSC7422-02 Datasheet Revision 4.3 93 VCore-Ie System and CPU Interface For more information about the SFR::RA_* registers, see Accessing the VCore-Ie Shared Bus, page 95. 5.4.1 Starting the VCore-Ie CPU This section provides information about the startup procedures for the VCore-Ie CPU. The procedures apply to both manual and automatic booting. The following table lists the registers associated with starting up the VCore-Ie CPU. Table 75 • VCore-Ie CPU Startup Registers Register Description RESET Manual release of VCore-Ie CPU reset MPU8051_MMAP Mapping of on-chip memory MEMACC_CTRL Starting copy of memory regions MEMACC Configuration of on-chip memory address range MEMACC_SBA Configuration of SBA start address GPR Set of eight general-purpose 32-bit registers The VCORE_CFG strapping pins determine if the VCore-Ie CPU boots up automatically or if it is kept in reset after startup. For more information, see VCore-Ie Configurations, page 87. 5.4.1.1 Loading On-chip Memory The basic principle of loading the on-chip memory is the same whether the VCore-Ie CPU is copying from Flash during automatic booting or if an external CPU is manually loading a code-image. The initial step of loading on-chip memory is to set up a source address in the shared bus domain by writing to MEMACC_SBA.MEMACC_SBA_START. For automatic booting, this is typically address 0x00000000 (the first address in the Flash). When manually loading on-chip memory from an external CPU, a good choice for transferring data is the eight 32-bit general-purpose registers (GPR), starting at address 0x70000000. The second step is to configure destination-range in the on-chip memory by using MEMACC.MEMACC_START and MEMACC.MEMACC_STOP. A transfer is started by writing to MEMACC_CTRL.MEMACC_DO. This field is cleared when all (32-bit) words in the range MEMACC_START through MEMACC_STOP are copied. When MEMACC_START is equal to MEMACC_STOP, only one word is copied. Word addresses are incremented for each word that is copied (the registers are not physically changed). This means that the n’th word in a given transfer is copied between addresses MEMACC_AHB_START.MEM_ACC_START+n and MEMACC.MEMACC_START+n. When loading from Flash, the entire on-chip memory can be filled using one long transfer. When loading from an external CPU using the GPR registers, the external CPU repeat transferring blocks of code until the entire code-image is copied to on-chip memory. The clock of the VCore-Ie CPU is gated during loading of the on-chip memory, which means that loading of the on-chip memory is instantaneous (from the point of view of the software running on the VCore-Ie CPU). By setting MEMACC_CTRL.MEMACC_EXAMINE, the direction of the transfer can be changed, which allows an external CPU to examine the contents of the on-chip memory instead of loading it. Loading of the on-chip memory is not limited to copying code during booting. Whenever code or data must be copied from Flash to on-chip memory, the hardware for loading the on-chip memory can be used. The on-chip memory area can be loaded while the VCore-Ie CPU is operating. Example: Manually Loading 58 Bytes of Code to On-Chip Memory. This example uses all eight GPR registers for transferring data to on-chip memory. Configure the MEMACC_AHB register to 0x70000000 (the address of the first GPR register). Write the first 32 bytes of code to GRP[0] though GPR[7]. Set the destination range to the first 8 words of on-chip memory by writing 0x001C0000 to the MEMACC register. VMDS-10392 VSC7420-02, VSC7421-02, and VSC7422-02 Datasheet Revision 4.3 94 VCore-Ie System and CPU Interface Write to MEMACC_CTRL.MEMACC_DO to start the access, make sure that MEMACC_CTRL.MEMACC_EXAMINE is cleared. The MEMACC_DO field is automatically cleared when the transfer is done, when this happens the next 26 bytes can be written to GRP[0] though GPR[6] (only byte addresses 0 and 1 of GPR[6] is used). Update the destination range in on-chip memory by writing 0x00380020 to the MEMACC register. Start the second transfer by writing to MEMACC_CTRL.MEMACC_DO. After this field is cleared, the code is copied. The on-chip memory can then be mapped, and the VCore-Ie CPU can be released from reset. 5.4.1.2 Mapping On-chip Memory By default, the on-chip memory is transparent to the VCore-Ie CPU. Using the MPU8051_MMAP or the SFR::MMAP registers, the on-chip memory can be mapped into code and data space of the VCore-Ie CPU. There are two MMAP registers: one that is part of the VCore-Ie registers (MPU8051_MMAP) and one that is a part of the 8051’s SFR registers (SFR::MMAP). The mapping of on-chip memory is the result of a bit-wise OR between these two registers. Only one of these registers must be used. When manually loading a code-image from an external CPU, the MPU8051_MMAP register must be used. When automatically booting up from Flash, use the SFR::MMAP register. The encoding of these two registers are the same, and both registers are commonly referred to as MMAP. The MPU8051_MMAP register in the VCore-Ie registers can be protected from VCore-Ie soft-reset. When the MPU8051_MMAP register is used, and the VCore-Ie system is protected from reset, the mapping remains active after soft-reset of the VCore-Ie CPU. The code interface of the 8051 maps to the shared bus by default. Setting MMAP.MAP_CODE_LOW maps access in the low 32 kilobyte region of the code interface to the on-chip memory. Setting MMAP.MAP_CODE_HIGH maps access in the high 32 kilobyte region of the code interface to the onchip memory. MMAP.MSADDR_CODE_LOW controls if either the lower or higher half of the on-chip memory is accessed when the low 32 kilobyte region of the code interface maps an access to on-chip memory. MMAP.MSADDR_CODE_HIGH controls if either lower or higher half of the on-chip memory is accessed when the high 32 kilobyte region of the code interface maps an access to the on-chip memory. The data interface of the 8051 maps to the shared bus by default. Setting MMAP.MAP_DATA_LOW maps access in the low 32 kilobyte region of the data interface to the on-chip memory. Setting MMAP.MAP_DATA_HIGH maps access in the high 32 kilobyte region of the data interface to the on-chip memory. MMAP.MSADDR_DATA_LOW controls if either the lower or higher half of the on-chip memory is accessed when the low 32 kilobyte region of the data interface maps an access to the on-chip memory. MMAP.MSADDR_DATA_HIGH controls if either the lower or higher half of the on-chip memory is accessed when the high 32 kilobyte region of the data interface maps an access to the on-chip memory. Example: Map the Complete On-Chip Memory to Both Code and Data. Some 8051 compilers support using the same physical memory for both code and data. To map the complete 64 kilobyte on-chip memory to both code and data interfaces, set MMAP to 0xAF. Then a code access on address n and a data access on address n both maps to an access on address n inside the on-chip memory. Example: Split On-Chip Memory between Code and Data. In some cases, it may be desirable to use nonoverlapping memory for code and data. Setting MMAP to 0x15 maps the lower half of the on-chip memory to the code interface and the higher half to the data interface. Code address n then maps to address n inside the on-chip memory, and data address n maps to address n+0x8000 inside the on-chip memory. 5.4.2 Accessing the VCore-Ie Shared Bus Access to the VCore-Ie shared bus is done through registers in the Special Function Registers (SFR) domain of the VCore-Ie CPU. VMDS-10392 VSC7420-02, VSC7421-02, and VSC7422-02 Datasheet Revision 4.3 95 VCore-Ie System and CPU Interface The following table lists the registers associated with the VCore-Ie shared bus. Table 76 • Shared Bus Access (SBA) Registers Register Description SFR::RA_AD0_RD SBA address[7:0], and read access initiation SFR::RA_AD0_WR SBA address[7:0], and write access initiation SFR::RA_AD1 SBA address[15:8] SFR::RA_AD2 SBA address[23:16] SFR::RA_AD3 SBA address[31:24] SFR::RA_DA0 SBA data[7:0] SFR::RA_DA1 SBA data[15:8] SFR::RA_DA2 SBA data[23:16] SFR::RA_DA3 SBA data[31:24] During access to the VCore-Ie shared bus, the clock of the VCore-Ie CPU is gated. This means that from the point of view of the software, access to the shared bus is instantaneous. Although the shared bus is byte-addressable, the VCore-Ie always does word access (reading or writing 32 bits of data). As a result, the shared bus address must be a word-aligned address, meaning that the two least significant bits of the address must always be 0. Reading from the VCore-Ie shared bus requires configuration of read-address by writing to RA_AD3, RA_AD2, RA_AD1, followed by write to RA_AD0_RD. The last write initiates the read access. The registers RA_DA3, RA_DA2, RA_DA1, and RA_DA0 are overwritten with the result of the read access. Note Because shared bus accesses are instantaneous, from software perspective, the data is available to the instruction immediately following the write to RA_AD0_RD. Writing to the VCore-Ie shared bus requires setting up write-data in RA_DA3, RA_DA2, RA_DA1, and RA_DA0, configuration of write-address by writing to RA_AD3, RA_AD2, RA_AD1, followed by write to RA_AD0_WR. The last write initiates the write access. The only registers that can be modified by hardware are the RA_DA* registers and these are only changed during read operations. Example: Copy ICPU_CFG::GPR[1] to ICPU_CFG::GPR[2] with change to 4'th byte. Perform read by setting RA_AD3=0x70, RA_AD2=0x00, RA_AD1=0x00, and RA_AD0_RD=0x04. The RA_DA3, RA_DA2, RA_DA1, and RA_DA0 registers have now been updated with the value of ICPU_CFG::GPR[1]. Modify RA_DA3 (the 4'th byte), and set RA_AD0_WR=0x08 to save to ICPU_CFG::GPR[2]. 5.4.3 Paged Access to VCore-Ie Shared Bus The VCore-Ie CPU supports paged access to the shared bus. Paging extends the address space of the VCore-Ie CPU by 8 bits, thereby increasing the addressable region from 64 kilobytes to 16 megabytes. The following table lists the registers associated with paged access to the VCore-Ie shared bus. Table 77 • Paged Access to VCore-Ie Shared Bus Register Description SFR::PG Paging Control SFR::EPG Extended Paging Control The paging mechanism of the VCore-Ie CPU only applies to access to the shared bus; the paging registers (PG and EPG) does not effect code or data access that are mapped to on-chip memory. VMDS-10392 VSC7420-02, VSC7421-02, and VSC7422-02 Datasheet Revision 4.3 96 VCore-Ie System and CPU Interface The PG register contains two groups: IFP[3:0] and OP[3:0]. The IFP group holds four page bits used for instruction fetches and program memory reads (MOVC instructions). The OP group holds four page bits used for all other types of external memory accesses. The layout of the EPG register is similar to the PG register: EIFP[3:0] and EOP[3:0] hold the four most significant page bits, so that the concatenation of EIFP and IFP provides the eight instruction page bits, and the concatenation of EOP and OP provides the eight other access page bits. Note The IFP/EIFP and OP/EOP fields are independent, which means that the VCore-Ie CPU can execute code and read data from different pages of the Flash. The paging function is useful for accessing small seldom used functions or data directly in Flash. However, it is sometimes more sensible to copy code or data from Flash to on-chip memory, by use of the dedicated loader hardware, before accessing it. For more information, seeLoading On-chip Memory, page 94. 5.4.4 Software Debug and Development This section provides information about methods that use combinations of software and hardware to allow debugging code within VCore-Ie CPU. The following table lists the registers associated with 8051 status. Table 78 • 8051 Status Registers Register Description MPU8051_STAT Status from the 8051 GENERAL_STAT Sleep status from the 8051 GPR Set of 8 general purpose 32-bit registers The MPU8051_STAT.MPU8051_GPR field is a read-only copy of the 8-bit SFR::GPR register.The MPU8051_STAT.MPU8051_STOP field is set when the 8051 enters stop mode (by setting SFR::PCON.STOP). By using these fields, the 8051 can report up to 256 exit conditions from the 8051 software to the external CPU. The only way for the VCore-Ie CPU to exit the stop mode is by resetting the VCore-Ie CPU. In a real-life application, the VCore-Ie CPU must not use the stop mode unless it has also enabled the watchdog timer, which would bring the system back online after the unlikely event of an error. The GENERAL_STAT.CPU_SLEEP field is set when the 8051 enters idle mode after setting SFR::PCON.IDLE. As a result, an external CPU can determine if the 8051 is in IDLE mode by examining the CPU_SLEEP field. The VCore-Ie registers includes eight 32-bit, general-purpose registers (GPR) that can be used for exchanging information between the 8051 and an external CPU. This can be combined with the software interrupt and semaphore implementation. For more information, see Mailbox and Semaphores, page 107. The same mechanism that is used for loading code into the on-chip memory can also be used for examining on-chip memory. By setting ICPU_CFG::MEMACC_CTRL.MEMACC_EXAMINE, a portion of the on-chip memory can be extracted and placed in SBA domain for access by an external CPU. 5.5 Manual Frame Injection and Extraction This section provides information about the manual frame injection and extraction to and from the CPU system. The devices have two injection groups and two extraction groups available. 5.5.1 Manual Frame Extraction This section provides information about manual frame extraction. VMDS-10392 VSC7420-02, VSC7421-02, and VSC7422-02 Datasheet Revision 4.3 97 VCore-Ie System and CPU Interface The following table lists the registers associated with manual frame extraction. Table 79 • Manual Frame Extraction Registers Register Description Replication XTR_FRM_PRUNING Frame pruning Per xtr queue XTR_GRP_CFG Extraction group configuration Per xtr group XTR_MAP Map extraction queue to group Per xtr queue XTR_RD Extraction read data Per xtr group XTR_QU_SEL Software controlled queue selection Per xtr group XTR_QU_FLUSH Extraction queue flush None XTR_DATA_PRESENT Extraction status None The devices have two extraction queues to which data can be redirected. Before data can be extracted each extraction queue must be enabled and mapped to an extraction group. The devices have two extraction groups available, and the mapping between queues and groups can be set arbitrary. A queue is enabled by setting the corresponding XTR_MAP.MAP_ENA field and the mapping to an extraction group is set in XTR_MAP.GRP. The XTR_DATA_PRESENT register shows if data is present in the extraction queues. It has two fields: • • XTR_DATA_PRESENT.DATA_PRESENT shows the data present status per extraction queue XTR_DATA_PRESENT.DATA_PRESENT_GRP shows the data present status per extraction group. When frame data is available in an extraction group, it can be read from the associated XTR_RD register, which is replicated per extraction group. The XTR_RD register returns the next 4 bytes of the frame data. When the read operation is completed, the register is automatically updated with the next 4 bytes of the frame data. End-of-frame (EOF) and other status indications are indicated by special data words in the data stream (when reading XTR_RD). The following table lists the possible special data words. Table 80 • Extraction Data Special Values Data Value Description 0x80000000-0x80000003 EOF. The two LSBs indicate the number of unused bytes. 0x80000004 EOF. Frame was pruned. 0x80000005 EOF. The frame was aborted and is invalid. 0x80000006 Escape. Next data is frame data and not a status word. 0x80000007 Data not ready. Each read operation on the XTR_RD register must check for the special values listed above and act accordingly. The escape data word (0x80000006) is inserted into the data stream when the frame data matches one of the special data words. When the escape data word is read it means that the next data word to be read is actual frame data and not a status word. The position of the EOF data word in the data stream can be configured in XTR_GRP_CFG.STATUS_WORD_POS. The possibilities are to have the EOF status word after the last frame data word or to have EOF status word just before the last frame data word. The default is to have the EOF status word after the last frame data word. The byte order of the XTR_RD register can be configured in XTR_GRP_CFG.BYTE_SWAP. The default is to have the byte order in little-endian. By clearing XTR_GRP_CFG.BYTE_SWAP, the byte order is changed to big-endian (network order). The byte order of the status words listed in Table 80, page 98 is not affected by the value of XTR_GRP_CFG.BYTE_SWAP. It is possible to configure a prune size for all extracted frames from an extraction queue using XTR_FRM_PRUNING. When pruning is enabled, all frames that are larger than the specified prune size VMDS-10392 VSC7420-02, VSC7421-02, and VSC7422-02 Datasheet Revision 4.3 98 VCore-Ie System and CPU Interface is pruned to the prune size. When a frame is pruned, the EOF status word is set to 0x80000004. The maximum prune size is 1024 bytes, and the prune size is defined in whole 32-bit words only. Frames in individual extraction queues can be flushed by setting the corresponding bit in XTR_QU_FLUSH.FLUSH. Flushing is disabled by clearing XTR_QU_FLUSH.FLUSH. Note Flushing does not affect the queues in the OQS so it may be needed to make the OQS stop sending data to the CPU extraction queues before flushing. When a frame is extracted, it can be prefixed with an 8-byte CPU extraction header (EH). The option to prefix an EH to the frame data is set in the rewriter. For more information about the extraction header format, see CPU Extraction Header, page 82. The extraction queue from which the frame originates is available through the CPU_QUEUE field in the CPU extraction header. The following table shows an example of reading a 65-byte frame, followed by a 64-byte frame. In the example, it is assumed that each frame is prefixed with an EH. Data is read big endian, and the EOF status word is configured to come just before the last frame data word. Undefined bytes cannot be assumed to be zero. Table 81 • Frame Extraction Example Read Number INJ_WR Bits 31:24 INJ_WR Bits 23:16 INJ_WR Bits 15:8 INJ_WR Bits 7:0 1 EH bit 63:56 EH bit 55:48 EH bit 47:40 EH bit 39:32 2 EH bit 31:24 EH bit 23:16 EH bit 15:8 EH bit 7:0 3 Frame byte 1 (DMAC) Frame byte 2 (DMAC) Frame byte 3 (DMAC) Frame byte 4 (DMAC) 4 Frame byte 5 (DMAC) Frame byte 6 (DMAC) Frame byte 7 (SMAC) Frame byte 8 (SMAC) 19 0x80 (EOF) 0x00 (EOF) 0x00 (EOF) 0x03 (EOF) 20 Frame byte 65 (FCS) Undefined Undefined Undefined 21 EH bit 63:56 EH bit 55:48 EH bit 47:40 EH bit 39:32 38 0x80 (EOF) 0x00 (EOF) 0x00 (EOF) 0x00 (EOF) 39 Frame byte 61 Frame byte 62 Frame byte 63 Frame byte 64 … … 5.5.2 Manual Frame Injection This section provides information about manual frame injection on the devices. The following table lists the register associated with manual frame injection. Table 82 • Manual Frame Injection Registers Register Description Replication INJ_GRP_CFG Injection group configuration Per injection group INJ_WR Injection write data Per injection group INJ_CTRL Injection control Per injection group INJ_STATUS Injection status None INJ_ERR Injection errors Per injection group VMDS-10392 VSC7420-02, VSC7421-02, and VSC7422-02 Datasheet Revision 4.3 99 VCore-Ie System and CPU Interface The devices have two injection groups available. Frames can be injected from the CPU injection groups using register writes. There are two ways of injecting frames: • • Directly forwarding to a specific port, bypassing the analyzer. Normal forwarding of a frame through the analyzer. To control the injection mode, an 8-byte injection header (IH) must be prefixed to the frame data. For more information about the injection modes and the injection header, see Frame Injection, page 83. Frame data is injected by doing consecutive writes of 4 bytes to the INJ_WR register, which is replicated per injection group. Endianess of the INJ_WR register is configured in INJ_GRP_CFG.BYTE_SWAP. Start-of-frame (SOF) and end-of-frame (EOF) indications are set in INJ_CTRL. INJ_CTRL must be written prior to INJ_WR. SOF and EOF is indicated in INJ_CTRL.SOF and INJ_CTRL.EOF respectively. In INJ_CTRL.VLD_BYTES the number of valid bytes of the last write to INJ_WR is indicated and VLD_BYTES must be set together with the EOF indication. The frame data must include the 4-byte FCS, but it does not have to be correct, because it is recalculated by the egress port module. While a frame is being injected it can be aborted by setting INJ_CTRL.ABORT. The SOF, EOF, and ABORT fields of INJ_CTRL are automatically cleared by hardware. Dummy bytes can be injected in front of a frame before the actual frame data (including injection header). The dummy bytes are discarded before the frame data is transmitted by the CPU system. The number of bytes to discard from the frame data is set in INJ_CTRL.GAP_SIZE. The GAP_SIZE field must be set together with SOF. Before each write to INJ_WR, the status fields INJ_STATUS.WMARK_REACHED and INJ_STATUS.FIFO_RDY must be checked to ensure successful injection. The INJ_ERR register shows if an error occurred during frame injection. The following table shows an example of injecting a 65-byte frame followed by a 64-byte frame. Both frames are prefixed by a CPU injection header and big-endian mode is used for the INJ_WR register. The “don’t care” bytes can be any value. Table 83 • Frame Injection Example Register Access INJ_WR Bits 31:24 INJ_WR Bits 23:16 INJ_WR Bits 15:8 INJ_WR Bits 7:0 INJ_CTRL #1 GAP_SIZE = 0, ABORT = 0, EOF = 0, SOF = 1, VLD_BYTES = 0 INJ_WR #1 IH bit 63:56 IH bit 55:48 IH bit 47:40 IH bit 39:32 INJ_WR #2 IH bit 31:24 IH bit 23:16 IH bit 15:8 IH bit 7:0 INJ_WR #3 Frame byte 1 (DMAC) Frame byte 2 (DMAC) Frame byte 3 (DMAC) Frame byte 4 (DMAC) INJ_WR #4 Frame byte 5 (DMAC) Frame byte 6 (DMAC) Frame byte 7 (SMAC) Frame byte 8 (SMAC) … INJ_CTRL #2 GAP_SIZE = 0, ABORT = 0, EOF = 1, SOF = 0, VLD_BYTES = 1 INJ_WR #19 Frame byte 65 (FCS) INJ_CTRL #3 GAP_SIZE = 0, ABORT = 0, EOF = 0, SOF = 1, VLD_BYTES = 0 INJ_WR #20 IH bit 63:56 Don’t care IH bit 55:48 Don’t care IH bit 47:40 Don’t care IH bit 39:32 … INJ_CTRL #4 GAP_SIZE = 0, ABORT = 0, EOF = 1, SOF = 0, VLD_BYTES = 0 INJ_WR #37 Frame byte 61 Frame byte 62 Frame byte 63 Frame byte 64 VMDS-10392 VSC7420-02, VSC7421-02, and VSC7422-02 Datasheet Revision 4.3 100 VCore-Ie System and CPU Interface 5.5.3 Frame Interrupts Software can be interrupted when frame data is available for extraction or when there is room for frames to be injected. The value of DEVCPU_QS::XTR_DATA_PRESENT.DATA_PRESENT_GRP is provided directly as interrupt inputs to the VCore-Ie system’s interrupt controller (the XTR_RDY interrupts), so that software can be interrupted when frame data is available for extraction. Using the interrupt controller, these interrupts can be mapped independently to the VCore-Ie CPU interrupt inputs. The negated value of DEVCPU_QS::INJ_STATUS.WMARK_REACHED is provided as interrupt inputs to the VCore-Ie system’s interrupt controller (the INJ_RDY interrupts), so that software can be interrupted when there is room in the IQS. Using the interrupt controller, these can be mapped independently to the VCore-Ie CPU interrupt inputs. 5.6 External CPU Support This section describes the handles of the device, which is dedicated to supporting external CPU systems. In addition to the dedicated logic, an external CPU can interact with most of the VCore-Ie system. An external CPU attaches to the device through the SI or MIIM and has access to register targets in the switch core domain. Through these register targets, indirect access into the VCore-Ie system on the VCore-Ie SBA is possible. For more information, Access to the VCore-Ie Shared Bus, page 106. The external CPU can coexist with the internal VCore-Ie CPU and hardware-semaphores and interrupts are implemented for inter-CPU communication. For more information, see Mailbox and Semaphores, page 107. 5.6.1 Register Access and Multimaster Systems The access time is the time it takes for a CPU interface to read or write a register inside a register target. The access time depends on the target and the number of CPU interfaces that are attempting to access the target. There are two types of targets: • • Fast Register Targets have dedicated logic for each CPU interface, and the interfaces have guaranteed access to the fast targets; the access time is no more than 35 ns. Normal Register Targets are accessible by all CPU interfaces. When different interfaces access the same target, each interface competes for access. When a target is accessed by only one CPU interface, the maximum access time is 1.1 µs. When a target is accessed by more than one CPU interface, the access time is increased to no more than 2.2 µs. Fast Targets are DEVCPU_QS, DEVCPU_ORG, and the VCore-Ie registers (ICPU_CFG, UART, and so on). All other register targets in the device are considered Normal Targets. The VCore-Ie registers are placed on the VCore-Ie shared bus and are indirectly accessible to an external CPU through the DEVCPU_GCB register target. 5.6.2 Serial Interface in Slave Mode This section provides information about the function of the serial interface (SI) in slave mode. The following table lists the registers associated with SI slave mode. Table 84 • SI Slave Mode Register Register Description SI Configuration of endianess, bit order, and padding The serial interface implements a SPI-compatible protocol that allows an external CPU to perform read and write accesses to register targets inside the device. Endianess and bit order is configurable, and several options for high frequencies are supported. The serial interface is available to an external CPU when the VCore-Ie CPU does not own the SI. For more information, VCore-Ie System and CPU Interface, page 86. VMDS-10392 VSC7420-02, VSC7421-02, and VSC7422-02 Datasheet Revision 4.3 101 VCore-Ie System and CPU Interface The following table lists the pins of the SI interface. Table 85 • SI Slave Mode Pins Pin Name Direction Description SI_nEn I Active low chip select SI_Clk I Clock input SI_DI I Data input (MOSI) SI_DO O Data output (MISO) SI_DI is sampled on rising edge of SI_Clk. SI_DO is changed on falling edge of SI_Clk. There are no requirements on the logical values of the SI_Clk and SI_DI inputs when SI_nEn is asserted or deasserted, they can be either 0 or 1. SI_DO is only driven during reading when read-data is shifted out of the device. The external CPU initiates access by asserting chip select and then transmitting one bit read/write indication, one don’t care bit, and 22 address bits. For write access, an additional 32 data bits are transmitted. For read access, the external CPU continues to clock the interface while reading out the result. With the register address of a specific register (REG_ADDR), the SI address (SI_ADDR) is calculated: SI_ADDR = (REG_ADDR) – 0×60000000)>>2 Data word endianess is configured through SI.SI_ENDIAN. The order of the data bits is configured using SI.SI_LSB. Setting SI.SI_LSB affects both the first 24 bits of the SI command and the 32 bits of data. The following illustration shows various configurations for write access. The data format during writing, as depicted, is also used when the device is transmitting data during read operations. Figure 30 • Write Sequence for SI SI_nEn SI_Clk Big endian mode (SI.SI_ENDIAN=1), Most significant bit first (SI.SI_LSB=0) SI_DI 2 2 1 1 1 1 1 1 1 1 1 1 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 1 0 9 8 7 6 5 4 3 2 1 0 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 Serial Address (SI_ADDR) Serial Data SI_DO Big endian mode (SI.SI_ENDIAN=1), Least significant bit first (SI.SI_LSB=1) SI_DI 1 1 1 1 2 2 6 7 8 9 0 1 8 9 1 1 1 1 1 1 2 2 2 2 2 2 3 3 1 1 1 1 2 2 2 2 1 1 1 1 1 1 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 0 1 2 3 4 5 4 5 6 7 8 9 0 1 6 7 8 9 0 1 2 3 0 1 2 3 4 5 Serial Address (SI_ADDR) + Write Indication Serial Data Little endian mode (SI.SI_ENDIAN=0), Most significant bit first (SI.SI_LSB=0) SI_DI 2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 2 2 1 1 1 1 3 3 2 2 2 2 2 2 9 8 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 9 8 1 0 9 8 7 6 5 4 3 2 1 0 5 4 3 2 1 0 3 2 1 0 9 8 7 6 1 0 9 8 7 6 5 4 Serial Address (SI_ADDR) Serial Data Little endian mode (SI.SI_ENDIAN=0), Least significant bit first (SI.SI_LSB=1) SI_DI 1 1 1 1 2 2 6 7 8 9 0 1 8 9 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 3 3 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 Serial Address (SI_ADDR) + Write Indication Serial Data When reading registers using the SI interface, the device needs to prepare read data after receiving the last address bit. The access time of the register that is read must be satisfied before shifting out the first bit of read data. For information about access time, see Register Access and Multimaster Systems, page 101. The external CPU must apply one of the following solutions to satisfy access time: VMDS-10392 VSC7420-02, VSC7421-02, and VSC7422-02 Datasheet Revision 4.3 102 VCore-Ie System and CPU Interface • • • Use SI_Clk with a period that is a minimum of twice the access time for the register target. For example, for Normal Targets (single master): 1/(2 × 1.1 µs) = 450 kHz. Pause the SI_Clk between shifting of serial address bit 0 and the first data bit with enough time to satisfy the access time for the register target. Configure the device to send out enough padding (dummy) bytes before transmitting the read data to satisfy the access time for the register target. Inserting padding (dummy) bytes is configured in SI.SI_WAIT_STATES. The required number of padding bytes depends on the SI frequency. The SI_DO output is not driven while shifting though padding bytes. Note When using padding bytes, it is usually cumbersome to change the padding configuration on the fly. Then it makes sense to use enough padding to support the worst case access time. Example: The required number of padding bytes for 20 MHz SI. The clock period at 20 MHz is 50 ns; it will take 50 ns × 8 = 400 ns to shift through one padding byte. For a single master system, the worstcase access time to any register target is 1.1 µs. To satisfy this delay, SI.SI_WAIT_STATES must be configured to at least three. This means that the external CPU must shift a total of 56 bits when reading from the device (the last 32 bits are the read data). The following illustrations show the options for serial read access. The illustrations show only one mapping of read data, little endian with most significant bit first. Any of the mappings can be configured and apply to read data in the same way as for write data. Figure 31 • Read Sequence for SI_Clk Slow SI_nEn SI_Clk Big endian mode (SI.SI_ENDIAN=1), Most significant bit first (SI.SI_LSB=0), no padding (SI.SI_WAIT_STATES=0) SI_DI 2 2 1 1 1 1 1 1 1 1 1 1 9 8 7 6 5 4 3 2 1 0 1 0 9 8 7 6 5 4 3 2 1 0 Serial Address (SI_ADDR) 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 9 8 7 6 5 4 3 2 1 0 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 SI_DO Serial Data Figure 32 • Read Sequence for SI_Clk Pause SI_nEn pause SI_Clk Big endian mode (SI.SI_ENDIAN=1), Most significant bit first (SI.SI_LSB=0), no padding (SI.SI_WAIT_STATES=0) SI_DI 2 2 1 1 1 1 1 1 1 1 1 1 9 8 7 6 5 4 3 2 1 0 1 0 9 8 7 6 5 4 3 2 1 0 Serial Address (SI_ADDR) 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 9 8 7 6 5 4 3 2 1 0 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 SI_DO Serial Data Figure 33 • Read Sequence for One-Byte Padding SI_nEn SI_Clk Big endian mode (SI.SI_ENDIAN=1), Most significant bit first (SI.SI_LSB=0), 1 byte of padding (SI.SI_WAIT_STATES=1) SI_DI 2 2 1 1 1 1 1 1 1 1 1 1 9 8 7 6 5 4 3 2 1 0 1 0 9 8 7 6 5 4 3 2 1 0 Serial Address (SI_ADDR) 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 9 8 7 6 5 4 3 2 1 0 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 SI_DO padding (1 byte) Serial Data VMDS-10392 VSC7420-02, VSC7421-02, and VSC7422-02 Datasheet Revision 4.3 103 VCore-Ie System and CPU Interface When using SI, the external CPU must first configure the SI register after power-up, reset, or chip-level soft reset. To configure the device into a known state 1. 2. 5.6.3 Write 0 to the SI register. Write the desired configuration using data formatted as little endian with most significant bit first. MIIM Interface in Slave Mode This section provides the functional aspects of the MIIM slave interface. Note: The MIIM slave I/F, due to its low bandwidth, is not aimed at supporting or recommended for managed switch applications. The MIIM slave interface allows an external CPU to perform read and write access to the register targets inside the device. Register access is done indirectly, because the address and data fields of the MIIM protocol is less than those used by the register targets. Transfers on the MIIM interface are using the Management Frame Format protocol specified in IEEE 802.3, Clause 22. The MIIM slave pins on the device are overlaid functions on the GPIO interface. MIIM slave mode is enabled by configuring the appropriate VCORE_CFG strapping pins. For more information, see VCore-Ie System and CPU Interface, page 86. When MIIM slave mode is enabled, the appropriate GPIO pins are automatically overtaken. For more information, see Overlaid Functions on the GPIOs, page 115. The following table lists the pins of the MIIM slave interface. Table 86 • MIIM Slave Pins Pin Name I/O Description MDC_SLV, GPIO I MIIM slave clock input MDIO_SLV, GPIO I/O MIIM slave data input/output MDIO_SLV is sampled or changed on the rising edge of MDC_SLV by the MIIM slave interface. The MIIM slave mode uses PHY address 31. The MIIM slave has seven 16-bit MIIM registers defined as listed in the following table. Table 87 • MIIM Registers Register Address Register Name Description 0 ADDR_REG0 Bit 15:0 of the address to read or write. The address field must be formatted as a word address. 1 ADDR_REG1 Bit 31:16 of the address to read or write. 2 DATA_REG0 Bit 15:0 of the data to read or write. Returns 0x0000 if a register read error occurred. 3 DATA_REG1 Bit 31:16 of the data to read or write. The read or write operation is initiated after this register is read or written. Returns 0x8000 if read while busy or a register read error occurred. 4 DATA_REG1_INCR Bit 31:16 of data to read or write. The read or write operation is initiated after this register is read or written. When the operation is complete, the address register is incremented by one. Returns 0x8000 if read while busy or if a register read error occurred. VMDS-10392 VSC7420-02, VSC7421-02, and VSC7422-02 Datasheet Revision 4.3 104 VCore-Ie System and CPU Interface Table 87 • MIIM Registers (continued) Register Address Register Name Description 5 DATA_REG1_INERT Bit 31:16 of data to read or write. Reading or writing to this register will not cause a register access to be initiated. Returns 0x8000 if a register read error occurred. 6 STAT_REG The status register gives the status of any ongoing operations. Bit 0: Busy - Is set while a register read/write operation is in progress. Bit 1: Busy_rd - the busy status during the last read or write operation. Bit 2: Err - Is set if a register access error occurred. Others: Reserved. A 32-bit register read or write transaction over the MIIM interface is done indirectly due to the limited data width of the MIIM frame. First, the address of the register inside the device must be set in the two 16-bit address registers of the MIIM slave using two MIIM write transactions. Afterwards the two 16-bit data registers can be read/written to access the data value of the register inside the device. Thus, it requires up to four MIIM transactions to perform a single read or write operation on a register target. The address of the register to read/write is set in registers ADDR_REG0 and ADDR_REG1. The data to write to the register pointed to by the address in ADDR_REG0 and addr_reg1 is first written to DATA_REG0 and then to DATA_REG1. When the write transaction to DATA_REG1 is completed, the MIIM slave initiates the register transaction. With the register address of a specific register (REG_ADDR), the MIIM address (MIIM_ADDR) is calculated as: MIIM_ADDR = (REG_ADDR - 0x60000000)>>2 The following illustration shows a single MIIM write transaction on the MIIM interface. Figure 34 • MIIM Slave Write Sequence / / MDC MDIO / / / / 1 0 PREAMBLE 32-bit 1 0 ST 2-bit 1 OP 2-bit / / / / / / / / / / / / PHYAD 5-bit / / 1 REGAD 5-bit / / / / 0 TA 2-bit DATA 16-bit A reading transaction is done in a similar way. First, read the DATA_REG0 and then read the DATA_REG1. As with a write operation. The register transaction is not initiated before the DATA_REG1 register is read. In other words, the returned read value is from the previous read transaction. The following illustration shows a single MIIM read transaction on the MIIM interface. Figure 35 • MIIM Slave Read Sequence MDC MDIO 1 / / / / / / / / / / / / / / / / / / PREAMBLE 32-bit 0 ST 2-bit 1 1 OP 2-bit 0 PHYAD 5-bit REGAD 5-bit Z 0 TA 2-bit / / / / / DATA 16-bit VMDS-10392 VSC7420-02, VSC7421-02, and VSC7422-02 Datasheet Revision 4.3 105 VCore-Ie System and CPU Interface 5.6.4 Access to the VCore-Ie Shared Bus This section provides information about how to access the VCore-Ie shared bus (SBA) from an external CPU. The following table lists the registers associated with the VCore-Ie shared bus access. Table 88 • VCore-Ie Shared Bus Access Registers Register Description VA_CTRL Status for ongoing accesses VA_ADDR Configuration of shared bus address VA_DATA Data register VA_DATA_INCR Data register, access increments VA_ADDR VA_DATA_INERT Data register, access does not start new accesses An external CPU perform 32-bit reads and writes to the SBA through the VCore Access (VA) registers. In the VCore-Ie system, there is a dedicated master on the shared bus that handles VA accesses. For information about arbitration between masters on the shared bus, see Shared Bus Arbitration, page 89. The SBA address is configured in VA_ADDR. Accessing the VA_DATA register starts an SBA access. Writing to VA_DATA starts a write with the 32-bit value that was written to VA_DATA. Reading from VA_DATA returns the current value of the register and starts a read access, when the read-access completes the result will automatically be stored in the VA_DATA register. The VA_DATA_INCR register behaves like VA_DATA, except that after starting an access the VA_ADDR register is incremented by 4 (so that it points to the next word address in the SBA domain). Reading from the VA_DATA_INCR register returns the value of VA_DATA, writing to VA_DATA_INCR overwrites the value of VA_DATA. Note By using VA_DATA_INCR, sequential addresses can be accessed without having to manually increment the VA_ADDR register between each access. The VA_DATA_INERT register provides direct access to the VA_DATA value without starting accesses on the SBA. Reading from the VA_DATA_INERT register returns the value of VA_DATA, writing to VA_DATA_INERT overwrites the value of VA_DATA. The VCore-Ie shared bus is capable of returning error-indication when illegal register regions are accessed. If a VA access result in an error-indication from the SBA, the VA_CTRL.VA_ERR field is set, and the VA_DATA is set to 0x80000000. Note SBA error indications only occur when non-existing memory regions or illegal registers are accessed. It does not occur during normal operation, so the VA_CTRL.VA_ERR indication is useful during debugging only. Example: Reading from ICPU_CFG::GRP[1] through the VA registers. The ICPU_GPR register is the second register in the SBA VCore-Ie Registers region. Set VA_ADDR to 0x70000004, read once from VA_DATA (and discard the read-value). Wait until VA_CTRL.VA_BUSY is cleared, then VA_DATA contains the value of the ICPU_CFG::GRP[1] register. Using VA_DATA_INERT (instead of VA_DATA) to read the data is appropriate because this does not start a new SBA access. 5.6.4.1 Optimized Reading SBA access is typically much faster than the CPU interface, which is used to access the VA registers. The VA_DATA register (VA_DATA_INCR and VA_DATA_INERT) return 0x80000000 while VA_CTRL.VA_BUSY is set. This means that it is possible to skip checking for busy between read access to SBA. For example, after initiating a read access from SBA, software can proceed directly to reading from VA_DATA, VA_DATA_INCR, or VA_DATA_INERT. • If the second read is different from 0x80000000; then the second read returned valid read data (the SBA access was done before the second read was performed). VMDS-10392 VSC7420-02, VSC7421-02, and VSC7422-02 Datasheet Revision 4.3 106 VCore-Ie System and CPU Interface • If the second read is equal to 0x80000000; VA_CTRL must be read. If VA_CTRL.VA_BUSY_RD is cleared (and VA_CTRL.VA_ERR_RD is also cleared), then 0x80000000 is the actual read data If VA_CTRL.VA_BUSY_RD is set, the SBA access was not yet done at the time of the second read. Start over again by repeating the read from VA_DATA. Optimized reading can be used for single-read access (reading VA_DATA and then VA_DATA_INERT). For sequential reads (reading VA_DATA_INCR several times), the VA_ADDR is only incremented on successful (non-busy) reads. 5.6.5 Mailbox and Semaphores This section provides information about the semaphores and mailbox features for CPU to CPU communication. The following table lists the registers associated with mailbox and semaphore. Table 89 • Mailbox and Semaphore Registers Register Description SEMA Taking of semaphores, replicated per semaphore. SEMA_FREE Current status for all semaphores. SEMA_INTR_ENA Enable software interrupt on free semaphores. SEMA_INTR_ENA_CLR Atomic clear of the SEMA_INTR_ENA register. SEMA_INTR_ENA_SET Atomic set of the SEMA_INTR_ENA register. SW_INTR Asserting of software interrupts. MAILBOX Mailbox. MAILBOX_CLR Atomic clear of bits in the mailbox register. MAILBOX_SET Atomic set of bits in the mailbox register. The devices implements eight independent semaphores. The semaphores are controlled through the SEMA register. The SEMA register is replicated once per semaphore; SEMA[0] corresponds to the first semaphore, SEMA[1] the second semaphore, and so on. Any CPU can attempt to take a semaphore n by reading SEMA[n].SEMA. If the result is 1, the semaphore was successfully taken and is now owned by the CPU. If the result is 0, the semaphore was not free. After a CPU successfully takes a semaphore, all additional reads from the corresponding SEMA register will return 0. To release semaphore n, a CPU must write 1 to SEMA[n].SEMA. Note Any CPU can release semaphores; it does not have to the one that has taken the semaphore, this allows implementation of handshaking protocols. The current status for all semaphores is available in SEMA_FREE.SEMA_FREE. A software interrupt can be generated when one or more semaphores are free. Interrupt is enabled in SEMA_INTR_ENA.SEMA_INTR_ENA, atomic set and clear are possible through SEMA_INTR_ENA_CLR and SEMA_INTR_ENA_SET. Semaphores [3:0] can trigger SW0 interrupt when enabled and semaphores [7:4] can trigger SW1 interrupt. The currently interrupting semaphores are available through SEMA_INTR_ENA.SEMA_INTR_IDENT; this field is the result of a logical AND between SEMA_INTR_ENA.SEMA_INTR_ENA and SEMA_FREE.SEMA_FREE. In addition to interrupting on free semaphores, a software interrupt can be manually set by writing to SW_INTR.SW0_INTR or SW_INTR.SW1_INTR, these fields are self-clearing. The mailbox is a 32-bit register that can be set and cleared atomically using any CPU interface (including the VCore-Ie CPU). The MAILBOX register allows reading (and writing) of the current mailbox value. VMDS-10392 VSC7420-02, VSC7421-02, and VSC7422-02 Datasheet Revision 4.3 107 VCore-Ie System and CPU Interface Atomic clear of specific bits in the mailbox register is done by writing a mask to MAILBOX_CLR. Atomic setting of specific bits in the mailbox register is done by writing a mask to MAILBOX_SET. 5.7 VCore-Ie System Peripherals This section describes the subblocks of the VCore-Ie system. They are primarily intended to be used by the VCore-Ie CPU. However, an external CPU can access and control these through the shared bus. 5.7.1 Timers This section provides information about the timers. The following table lists the registers associated with timers. Table 90 • Timer Registers Register Description Replication TIMER_CTRL Enable/disable timer Per timer TIMER_VALUE Current timer value Per timer TIMER_RELOAD_VALUE Value to load when wrapping Per timer TIMER_TICK_DIV None Common timer-tick divider There are three decrementing 32-bit timers in the VCore-Ie system that run from a common divider. The common divider is driven by a fixed 250 MHz clock and can generate timer ticks in the range of 0.1 µs (10 MHz) to 1 ms (1 kHz), configurable through TIMER_TICK_DIV. The default timer tick is 100 µs (10 kHz). Note The timers are independent of the VCore-Ie CPU frequency, because the common divider uses a fixed clock. Software can access each timer value through the TIMER_VALUE registers. These can be read or written at any time, even when the timers are active. When a timer is enabled through TIMER_CTRL.TIMER_ENA, it decrements from the current value until it reaches zero. An attempt to decrement a TIMER_VALUE of zero generates interrupt and assigns TIMER_VALUE to the contents of TIMER_RELOAD_VALUE. Interrupts generated by the timers are send to the VCore-Ie interrupt controller. From here, interrupts can be forwarded to the VCore-Ie CPU or to an external CPU. For more information, see Interrupt Controller, page 121. By setting TIMER_CTRL.ONE_SHOT_ENA the timer disables itself after generating one interrupt. When this field is cleared, timers will decrement, interrupt, and reload indefinitely (or until disabled by software, that is, by clearing of TIMER_CTRL.TIMER_ENA). A timer can be reloaded from TIMER_RELOAD_VALUE at the same time as it is enabled by setting both TIMER_CTRL.FORCE_RELOAD and TIMER_CTRL.TIMER_ENA. Example: Configure Timer0 So That It Interrupts Every 1 ms. With the default timer tick of 100 µs ten timer ticks are needed for a timer that wraps every 1 ms. Configure TIMER_RELOAD_VALUE[0] to 0x9. Then enable the timer and force a reload by setting TIMER_CTRL[0].TIMER_ENA and TIMER_CTRL[0].FORCE_RELOAD at the same time. 5.7.2 UART This section provides information about the UART (Universal Asynchronous Receiver/Transmitter) controller. The following table lists the registers associated with the UART. Table 91 • UART Registers Register Description RBR_THR Receive buffer/transmit buffer/Divisor (low) VMDS-10392 VSC7420-02, VSC7421-02, and VSC7422-02 Datasheet Revision 4.3 108 VCore-Ie System and CPU Interface Table 91 • UART Registers (continued) Register Description IER Interrupt enable/Divisor (high) IIR_FCR Interrupt identification/FIFO control LCR Line control MCR Modem control LSR Line status MSR Modem status SCR Scratchpad USR UART status The VCore-Ie system UART is functionally based on the industry-standard 16550 UART (RS232 protocol). This implementation features a 16-byte receive and a 16-byte transmit FIFO. Figure 36 • UART Timing One Character 1 start bit 5 to 8 data bits (LSB first) + optional parity 1, 1.5, or 2 stop bits The number of data-bits, parity, parity-polarity, and stop-bit length are all programmable using LCR. The UART pins on the devices are overlaid functions on the GPIO interface. Before enabling the UART, the VCore-Ie CPU must enable overlaid modes for the appropriate GPIO pins. For more information, see For more information about enabling the overlaid functionality of the GPIOs, see Overlaid Functions on the GPIOs, page 115. The following table lists the pins of the UART interface. Table 92 • UART Interface Pins Pin Name I/O Description UART_RX/ GPIO_31 I UART receive data UART_TX/GPIO_30 O UART transmit data The baud rate of the UART is derived from the VCore-Ie system frequency. The divider value is indirectly set through the RBR_THR and IER registers. The baud rate is equal to the VCore-Ie system clock frequency divided by sixteen multiplied by the value of the baud rate divisor. A divider of zero disables the baud rate generator and no serial communications occur. The default value for the divisor register is zero. Example: Configure a baud rate of 9600 in a 125 MHz system. To generate a baud rate of 9600, the divisor register must be set to 0x32E (125 MHz/(16 × 9600 Hz)). Set LCR.DLAB and write 0x2E to RBR_THR and 0x03 to IER (this assumes that the UART is not in use). Finally, clear LCR.DLAB to change the RBR_THR and IER registers back to the normal mode. By default, the FIFO mode of the UART is disabled. Enabling the 16-byte receive and 16-byte transmit FIFOs (through IIR_FCR) is recommended. Note Although the UART itself supports RTS and CTS, these signals are not available on the pins of the device. 5.7.2.1 UART Interrupt The UART can generate interrupt whenever any of the following prioritized events are enabled (through IER): VMDS-10392 VSC7420-02, VSC7421-02, and VSC7422-02 Datasheet Revision 4.3 109 VCore-Ie System and CPU Interface • • • • Receiver error Receiver data available Character timeout (in FIFO mode only) Transmit FIFO empty or at or below threshold (in programmable THRE interrupt mode) When an interrupt occurs, the IIR_FCR register can be accessed to determine the source of the interrupt. Note that the IIR_FCR register has different purposes when reading or writing. When reading, the interrupt status is available in bits 0 through 3. For more information about interrupts and how to handle them, see the IIR_FCR register description. Example: Enable Interrupt When Transmit FIFO is Below One-Quarter Full. To get this type of interrupt, the THRE interrupt must be used. First, configure TX FIFO interrupt level to one-quarter full by setting IIR_FCR.TET to 10; at the same time, ensure that the IIR_FCR.FIFOE field is also set. Set IER.PTIME to enable the THRE interrupt in the UART. In addition, the VCore-Ie interrupt controller must be configured for the CPU to be interrupted. For more information, see Interrupt Controller, page 121. 5.7.3 Two-Wire Serial Interface This section provides information about the functions of the two-wire serial interface controller. The following table lists the registers associated with the two-wire serial interface. Table 93 • Two-Wire Serial Interface Registers Register Description CFG General configuration TAR Target address SAR Slave address DATA_CMD Receive/transmit buffer and command SS_SCL_HCNT Standard speed high time clock divider SS_SCL_LCNT Standard speed low time clock divider FS_SCL_HCNT Fast speed high time clock divider FS_SCL_LCNT Fast speed low time clock divider INTR_STAT Masked interrupt status INTR_MASK Interrupt mask register RAW_INTR_STAT Unmasked interrupt status RX_TL Receive FIFO threshold for RX_FULL interrupt TX_TL Transmit FIFO threshold for TX_EMPTY interrupt CLR_* Individual CLR_* registers are used for clearing specific interrupts. See register descriptions for corresponding interrupt. CTRL Control register STAT Status register TXFLR Current transmit FIFO level RXFLR Current receive FIFO level TX_ABRT_SOURCE Arbitration sources SDA_SETUP Data delay clock divider ACK_GEN_CALL Acknowledge of general call ENABLE_STATUS General two-wire serial controller status TWI_CONFIG Configuration of SDA hold-delay VMDS-10392 VSC7420-02, VSC7421-02, and VSC7422-02 Datasheet Revision 4.3 110 VCore-Ie System and CPU Interface The two-wire serial interface controller is compatible with the industry standard two-wire serial interface protocol. The controller supports standard speed up to 100 kbps and fast speed up to 400 kbps. Multiple bus masters, as well as both 7-bit and 10-bit addressing are also supported. By default, the two-wire serial interface controller operates as master only (CFG.MASTER_ENA), however, slave mode can be enabled (CFG.SLAVE_DIS). In slave mode, the controller generates an interrupt when addressed by an external master. For read requests, the controller then halts the two-wire serial bus until the VCore-Ie CPU has processed the request and provided a response (reply-data) to the controller. The slave addresses (SAR) of the two-wire serial interface controller must be unique on the two-wire serial interface bus. This must be configured before enabling slave mode. For information about addresses that have a special meaning on the bus, see Two-Wire Serial Interface Addressing, page 111. The two-wire serial interface pins on the devices are overlaid functions on the GPIO interface. Before enabling the two-wire serial interface, the VCore-Ie CPU must enable overlaid functions for the appropriate GPIO pins. For more information, see Overlaid Functions on the GPIOs, page 115. The following table lists the pins of the two-wire serial interface. Table 94 • Two-Wire Serial Interface Pins Pin Name I/O Description TWI_SCL, GPIO O Two-wire serial interface clock, open-collector output. TWI_SDA, GPIO I/O Two-wire serial interface data, open-collector output. Setting CTRL.ENABLE enables the controller. The controller can be disabled by clearing the CTRL.ENABLE field, there is a chance that disabling is not allowed (at the time when it is attempted); the ENABLE_STATUS register shows if the controller was successful disabled. Before enabling the controller, the user must decide on either standard or fast mode (CFG.SPEED) and configure clock dividers for generating the correct timing (SS_SCL_HCNT, SS_SCL_LCNT, FS_SCL_HCNT, FS_SCL_LCNT, and SDA_SETUP). The configuration of the divider registers depends on the VCore-Ie system clock frequency. The register descriptions explain how to calculate the required values. Some two-wire serial devices requires a hold time on SDA after SCK when transmitting from the two-wire serial interface controller. The device supports a configurable hold delay through the TWI_CONFIG register. The two-wire serial interface controller has an 8-byte combined receive and transmit FIFO. Figure 37 • Two-Wire Serial Interface Timing for 7-bit Address Access SCL 1 7 8 9 1 7 8 9 SDA A6 A0 R/W ACK D7 D1 D0 ACK START Address / Command Data STOP During normal operation of the two-wire serial interface controller, the STATUS register shows the activity and FIFO states. 5.7.3.1 Two-Wire Serial Interface Addressing Use CFG.MASTER_10BITADDR and CFG.SLAVE_10BITADDR to configure either 7 or 10 bit addressing for master and slave modes respectively. There are a number of reserved two-wire serial interface addresses. The two-wire serial interface controller does not restrict the use of these. However, if they are used out of context, there may be VMDS-10392 VSC7420-02, VSC7421-02, and VSC7422-02 Datasheet Revision 4.3 111 VCore-Ie System and CPU Interface compatibility issues with other two-wire serial devices. The following table lists the two-wire serial interface reserved addresses. Table 95 • Reserved Two-Wire Serial Interface Addresses Register Address Description 0000 000 General Call address/START Byte If the slave is enabled the two-wire serial interface controller places the data in the receive buffer and issues a general call interrupt. The acknowledge response is configurable (through ACK_GEN_CALL). 0000 001 CBUS address. The two-wire serial interface controller ignores this address. 0000 01X Reserved, do not use. 0000 1XX Reserved, do not use. 1111 1XX Reserved, do not use. 1111 0XX 10-bit addressing indication, 7-bit address devices must not use this. The two-wire serial interface controller can general both General Call and START Byte. Initiate this through TAR.GC_OR_START_ENA or TAR.GC_OR_START. When operating as master, the target/slave address is configured using the TAR register. 5.7.3.2 Two-Wire Serial Interface Interrupt The two-wire serial interface controller can generate a multitude of interrupts. All of these are described in the RAW_INTR_STAT register. The RAW_INTR_STAT register contains interrupt fields that are always set when their “trigger” conditions occur. The INTR_MASK register is used for masking interrupts and allowing interrupts to propagate to the INTR_STAT register. When set in the INTR_STAT register, the two-wire serial interface controller asserts interrupt toward the VCore-Ie interrupt controller. The RAW_INTR_STAT register also specifies what is required to clear the specific interrupts. When the source of the interrupt is removed, reading the appropriate CLR_* register (for example, CLR_RX_OVER) clears the interrupt. 5.7.4 MII Management Controller This section provides information about the MII Management controllers. The following table lists the registers associated with the MII Management controllers. Table 96 • MIIM Registers Register Description MII_STATUS General configuration MII_CMD Target address MII_DATA Slave address MII_CFG Receive/transmit buffer and command MII_SCAN_0 Standard speed high time clock divider MII_SCAN_1 Standard speed low time clock divider MII_SCAN_LAST_RSLTS Fast speed high time clock divider MII_SCAN_LAST_RSLTS_VLD Fast speed low time clock divider The devices contain two MIIM controllers with equal functionality. Controller 0 is connected to the internal PHY, and controller 1 is used to manage external PHYs. Only the interface of controller 1 is available as pins on the device. Data is transferred on the MIIM interface using the Management Frame Format protocol specified in IEEE 802.3, Clause 22 or the MDIO Manageable Device protocol defined in VMDS-10392 VSC7420-02, VSC7421-02, and VSC7422-02 Datasheet Revision 4.3 112 VCore-Ie System and CPU Interface IEEE 802.3, Clause 45. The clause 45 protocol differs from the clause 22 protocol by using indirect register accesses to increase the address range. The controller supports both Clause 22 and 45. The following table lists the pins of the MIIM interface for controller 1. Table 97 • MIIM Management Controller Pins Pin Name I/O Description MDC O MIIM clock MDIO I/O MIIM data input/output The MDIO signal is changed or sampled on the falling edge of the MDC clock by the controller. When the controller does not drive the MDIO pin it is tri-stated. Figure 38 • MII Management Timing MDC MDIO // // // // // // // // // // // // preamble 32-bit 5.7.4.1 ST 2-bit OP 2-bit PHYAD 5-bit REGAD 5-bit TA 2-bit Address/data 16-bit Clock Configuration The frequency of the management interface clock generated by the MIIM controller is derived from the VCore-Ie system frequency. The MIIM clock frequency is configurable and is selected with MII_CFG.MIIM_CFG_PRESCALE. The calculation of the resulting frequency is explained in the register description for MII_CFG.MIIM_CFG_PRESCALE. The maximum frequency of the MIIM clock is 25 MHz. 5.7.4.2 MII Management PHY Access Reads and writes across the MII management interface are performed through the MII_CMD register. Details of the operation, such as the PHY address, the register address of the PHY to be accessed, the operation to perform on the register (for example, read or write), and write data (for write operations) are set in the MII_CMD register. When the appropriate fields of MII_CMD are set, the operation is initiated by writing 0x1 to MII_CMD.MIIM_CMD_VLD. The register is automatically cleared when the MIIM command is initiated. When initiating single MIIM commands, MII_CMD.MIIM_CMD_SCAN must be set to 0x0. When an operation is initiated, the current status of the operation can be read in MII_STATUS. The fields MII_STATUS.MIIM_STAT_PENDING_RD and MII_STATUS.MIIM_STAT_PENDING_WR can be used to poll for completion of the operation. For a read operation, the read data is available in MII_DATA.MIIM_DATA_RDDATA after completion of the operation. The value of MII_DATA.MIIM_DATA_RDDATA is only valid if MII_DATA.MIIM_DATA_SUCCESS indicates no read errors. The MIIM controller contains a small command FIFO. Additional MIIM commands can be queued as long as MII_STATUS.MIIM_STAT_OPR_PEND is cleared. Care must be taken with read operations, because multiple queued read operations will overwrite MII_DATA.MIIM_DATA_RDDATA. Note A typical software implementation will never queue read operations, because the software needs read data before progressing the state of the software. In this case MIIM_STATUS.MIIM_STAT_OPR_PEND is checked before issuing MIIM read or write commands, for read-operations MII_STATUS.MIIM_STAT_BUSY is checked before returning read result. By default, the MIIM controller operates in clause 22 mode. To access clause 45 compatible PHYs, MII_CFG.MIIM_ST_CFG_FIELD and MII_CMD.MIIM_CMD_OPR_FIELD must be set according to clause 45 mode of operation. VMDS-10392 VSC7420-02, VSC7421-02, and VSC7422-02 Datasheet Revision 4.3 113 VCore-Ie System and CPU Interface 5.7.4.3 PHY Scanning The MIIM controller can be configured to continuously read certain PHY registers and detect if the read value is different from an expected value. If a difference is detected, a special sticky bit register is set or a CPU interrupt is generated, or both. For example, the controller can be programmed to read the status registers of one or more PHYs and detect whether the Link Status changed since the sticky register was last read. The reading of the PHYs is performed sequentially with the low and high PHY numbers specified in MII_SCAN_0 as range bounds. The accessed address within each of the PHYs is specified in MII_CMD.MIIM_CMD_REGAD. The scanning begins when a 0x1 is written to MII_CMD.MIIM_CMD_SCAN and a read operation is specified in MII_CMD.MIIM_CMD_OPR_FIELD. Setting MII_CMD.MIIM_CMD_SINGLE_SCAN stops the scanning after all PHYs have been scanned one time. The remaining fields of MII_CMD register is not used when scanning is enabled. In MII_SCAN_1.MIIM_SCAN_EXPECT the expected value for the PHY register is set. The expected value is compared to the read value after applying the mask set in MII_SCAN_1.MIIM_SCAN_MASK. To “don’t care” a bit-position, write a 0 to the mask. If the expected value for a bit position differs from the read value during scanning, and the mask register has a 1 for the corresponding bit, a mismatch for the PHY is registered. The scan results from the most recent scan can be read in MII_SCAN_LAST_RSLTS. The register contains one bit for each of the possible 32 PHYs. A mismatch during scanning is indicated by a 0. MII_SCAN_LAST_RSLTS_VLD will indicate for each PHY if the read operation performed during the scan was successful. The sticky-bit register MII_SCAN_RSLTS_STICKY has the mismatch bit set for all PHYs that had a mismatch during scanning since the last read of the sticky-bit register. When the register is read, its value is reset to all-ones (no mismatches). 5.7.4.4 MII Management Interrupt The MII management controllers can generate interrupts during PHY scanning. Each MII management controller has a separate interrupt signal to the interrupt controller. Interrupt is asserted when one or more PHYs have a mismatch during scan. The interrupt is cleared by reading the MII_SCAN_RSLTS_STICKY register, which resets all MII_SCAN_RSLTS_STICKY indications. 5.7.5 GPIO Controller This section provides information about the use of GPIO pins. The following table lists the registers associated with GPIO. Table 98 • GPIO Registers Register Description GPIO_OUT Value to drive on GPIO outputs GPIO_OUT_SET Atomic set of bits in GPIO_OUT GPIO_OUT_CLR Atomic clear of bits in GPIO_OUT GPIO_IN Current value on the GPIO pins GPIO_OE Enable of GPIO output mode (drive GPIOs) GPIO_ALT Enable of overlaid GPIO functions GPIO_INTR Interrupt on changed GPIO value GPIO_INTR_ENA Enable interrupt on changed GPIO value GPIO_INTR_IDENT Currently interrupting sources The GPIO pins are individually programmable. By default, GPIOs are inputs, however, they can be individually changed to outputs through GPIO_OE. For GPIOs that are in input mode, the value of the GPIO pin is reflected in the GPIO_IN register. GPIOs that are in output mode are driven to the value specified in GPIO_OUT. VMDS-10392 VSC7420-02, VSC7421-02, and VSC7422-02 Datasheet Revision 4.3 114 VCore-Ie System and CPU Interface In a system where multiple different CPU threads (or different CPUs) may work on the GPIOs at the same time, the GPIO_OUT_SET and GPIO_OUT_CLR registers provide a way for each thread to safely control the output value of GPIOs that are under their control, without having to implement locked regions and semaphores. 5.7.5.1 Overlaid Functions on the GPIOs Most of the GPIO pins have overlaid (alternative) functions that can be enabled through the replicated GPIO_ALT register. For a particular GPIO n: Enable overlaid mode 1 by setting GPIO_ALT[0][n] and clearing GPIO_ALT[1][n]. Overlaid mode 2 is enabled by clearing GPIO_ALT[0][n] and setting GPIO_ALT[1][n]. For normal GPIO mode, clear both GPIO_ALT[0][n] and GPIO_ALT[1][n]. The GPIOs that are not included in the following table do not have overlaid functions; the GPIO_ALT bits corresponding to these GPIOs must not be set. Table 99 • GPIO Mapping GPIO Pin Overlaid Function 1 Description GPIO_0 GPIO_1 GPIO_2 GPIO_3 SIO_CLK SIO_LD SIO_DO SIO_DI Serial GPIO controller connections. See Serial GPIO Controller, page 115. GPIO_4 TACHO Fan controller TACHO input. See FAN Controller, page 120. GPIO_5 GPIO_6 GPIO_7 TWI_SCK TWI_SDA None Two-wire serial interface connections. See Two-Wire Serial Interface, page 110. GPIO_8 EXT_IRQ0 External interrupt. See Interrupt Controller, page 121. GPIO_15 GPIO_16 None MIIM slave interface connections. GPIO_15 is MDC_SLV, and GPIO_16 is MDIO_SLV. See MIIM Interface in Slave Mode, page 104. GPIO_29 PWM Fan controller PWM output. See FAN Controller, page 120. GPIO_30 GPIO_31 UART_TX UART_RX UART connections. See UART, page 108. For example, to enable the UART_RX and UART_TX overlaid functions, set bits 30 (enable UART_TX) and 31 (enable UART_RX) in the GPIO_ALT[0] register. The UART now has control of the GPIO pins. 5.7.5.2 GPIO Interrupt The GPIO controller continually monitors all inputs and set bits in the GPIO_INTR register whenever a GPIO changes its input value. By enabling specific GPIO pins in the GPIO_INTR_ENA register, a change indication from GPIO_INTR is allowed to propagate (as GPIO interrupt) from the GPIO controller to the VCore-Ie Interrupt Controller. The currently interrupting sources can be read from GPIO_INTR_IDENT, this register is the result of a binary AND between the GPIO_INTR and GPIO_INTR_ENA registers. Note When the GPIO_INTR_IDENT register is different from zero, the GPIO controller is indicating an interrupt. 5.7.6 Serial GPIO Controller The VSC7420-02, VSC7421-02, and VSC7422-02 devices feature a serial GPIO controller (SIO). By using a serial interface, the SIO controller significantly extends the number of available GPIOs with a minimum number of additional pins on the device. The main purpose of the SIO controller is to connect control signals from SFP modules; however, it can also act as an LED controller. VMDS-10392 VSC7420-02, VSC7421-02, and VSC7422-02 Datasheet Revision 4.3 115 VCore-Ie System and CPU Interface The SIO controller supports up to 128 serial GPIOs (SGPIOs) organized into 32 ports, with four SGPIOs per port. The following table lists the registers associated with the serial GPIO. Table 100 • SIO Registers Register Description Replication SIO_INPUT_DATA Input data SGPIOs per port (4) SIO_INT_POL Interrupt polarity SGPIOs per port (4) SIO_PORT_INT_ENA Interrupt enable None SIO_PORT_CONFIG Output port configuration Per port (32) SIO_PORT_ENABLE Port enable None SIO_CONFIG General configuration None SIO_CLOCK Clock configuration None SIO_INT_REG Interrupt register SGPIOs per port (4) The following table lists the pins of the SIO controller. The pins of the SIO controller are overlaid on GPIOs. For more information about enabling the overlaid functionality of the GPIOs, see Overlaid Functions on the GPIOs, page 115. Table 101 • SIO Controller Pins Pin Name I/O Description SIO_CLK/GPIO_0 O SIO clock output, frequency is configurable using SIO_CLOCK.SIO_CLK_FREQ. SIO_LD/GPIO_1 O SIO load data, polarity is configurable using SIO_CONFIG.SIO_LD_POLARITY. SIO_DO/GPIO_2 O SIO data output. SIO_DI/GPIO_3 I SIO data input. The SIO controller works by shifting SGPIO values out on SIO_DO though a chain of shift registers on the PCB. After shifting a configurable number of SGPIO bits, the SIO controller asserts SIO_LD, which causes the shift registers to apply the values of the shifted bits to outputs. The SIO controller is also capable of reading inputs, at the same time as shifting out SGPIO values on SIO_DO, it also samples the SIO_DI input. The values sampled on SIO_DI are made available to software. If the SIO controller is only used for outputs, the use of the load signal is optional. If the load signal is omitted, simpler shift registers (without load) can be used, however, the outputs of these registers will toggle during shifting. When driving LED outputs, it is acceptable that the outputs will toggle when SGPIO values are updated (shifted through the chain). When the shift frequency is fast, the human eye is not able to see the shifting though the LEDs. The number of shift registers in the chain is configurable. The SIO controller allows enabling of individual ports through SIO_PORT_ENABLE; only enabled ports are shifted out on SI_DO. Ports that are not enabled are skipped during shifting of GPIO values. Note SIO_PORT_ENABLE allows skipping of ports in the SGPIO output stream that are not in use. The number of GPIOs per (enabled) port is configurable as well, through SIO_CONFIG.SIO_PORT_WIDTH this can be set to 1,2,3, or 4 bits. The number of bits per port is common for all enabled ports, so the number of shift registers on the PCB must be equal to the number of enabled ports times the number of SGPIOs per port. Enabling of ports and configuration of SGPIOs per port applies to both output mode and input mode. Unlike a regular GPIO port, a single SGPIO position can be used both as output and input. That is, VMDS-10392 VSC7420-02, VSC7421-02, and VSC7422-02 Datasheet Revision 4.3 116 VCore-Ie System and CPU Interface software can control the output of the shift register AND read the input value at the same time. Using SGPIOs as inputs requires load-capable shift registers. Regular shift registers and load-capable shift-registers can be mixed, which is useful when driving LED indications for integrated PHYs at the same time as supporting reading of link status from SFP modules, for example. Figure 39 • SIO Timing Parallel to serial shift registers load data on logical 0 Serial to parallel shift registers output data on rising edge SIO_LD 28 ns SIO_CLK pN b3 SIO_DO SIO_DI p0 b0 pN b2 p0 b1 pN b1 p0 b2 pN b0 p0 b3 pN-1 pN-1 b2 b3 p1 b0 p1 b2 p1 b1 p0 b3 pN b0 p0 b2 pN b1 p0 b1 pN b2 pN b3 p0 b0 pN b3 p0 b0 pN b2 p0 b1 Burst gap The SGPIO values are output in bursts followed by assertion of the SIO_LD signal. Values can be output as a single burst, or as continuous bursts separated by a configurable burst gap. The maximum length of a burst is 32 × 4 data cycles. The burst gap is configurable in steps of approximately 1 ms between 0 ms and 33 ms through SIO_CONFIG.SIO_BURST_GAP_DIS and SIO_CONFIG.SIO_BURST_GAP. A single burst is issued by setting SIO_CONFIG.SIO_SINGLE_SHOT. The field is automatically cleared by hardware when the burst is finished. To issue continuous bursts, set SIO_CONFIG.SIO_AUTO_REPEAT. The SIO controller continues to issue bursts until SIO_CONFIG.SIO_AUTO_REPEAT is cleared. SGPIO output values are configured in SIO_PORT_CONFIG.BIT_SOURCE. The input value is available in SIO_INPUT_DATA.S_IN. The following illustration shows what happens when the number of SGPIOs per port is configured to 2 (through SIO_CONFIG.SIO_PORT_WIDTH). Disabling of ports (through SIO_PORT_ENABLE) is handled in the same way as disabling the SGPIO ports. Figure 40 • SIO Timing with SGPIOs Disabled SIO_LD SIO_CLK SIO_DO pN b3 pN b2 Disabled pN b1 pN b0 pN-1 pN-1 pN-1 pN-1 pN-2 pN-2 pN-2 b1 b2 b1 b3 b0 b3 b2 Disabled Disabled p0 b3 p0 b2 p0 b1 p0 b0 Disabled Burst VMDS-10392 VSC7420-02, VSC7421-02, and VSC7422-02 Datasheet Revision 4.3 117 VCore-Ie System and CPU Interface The frequency of the SIO_CLK clock output is configured through SIO_CLOCK.SIO_CLK_FREQ. The SIO_LD output is asserted after each burst, this output is asserted for 28 ns. The polarity of SIO_LD is configurable through SIO_CONFIG.SIO_LD_POLARITY. The SIO_LD output can be used to ensure that outputs are stable when serial data is being shifted through the registers. This can be done by using the SIO_LD output to shift the output values into serialto-parallel registers after the burst is completed. If serial-to-parallel registers are not used, the outputs will toggle while the burst is being shifted through the chain of shift registers. A universal serial-to-parallel shift register outputs the data on a positive-edge load signal, and a universal parallel-to-serial shift register shifts data when the load pin is high, so one common load signal can be used for both input and output serial parallel conversion. The assertion of SIO_LD happens after the burst to ensure that after power up, the single burst will result in well-defined output registers. Consequently, to sample input values one time, two consecutive bursts must be issued. The first burst results in the input values being sampled by the serial-to-parallel registers, and the second burst shifts the input values into the SIO controller. The required port order in the serial bitstream depends on the physical layout of the shift register chain. Often the input and output port orders must be opposite in the serial streams. The port order of the input and output bitstream is independently configurable in SIO_CONFIG.SIO_REVERSE_INPUT and SIO_CONFIG.SIO_REVERSE_OUTPUT. The following illustration shows the port order. Figure 41 • SIO Output Order SIO_CLK Default order pN b3 SIO_DO SIO_DI p0 b0 pN b2 p0 b1 pN b1 pN b0 p0 b3 p0 b2 pN-1 pN-1 pN-1 pN-1 pN-2 b2 b1 b0 b3 b3 p1 b0 p1 b1 p1 b2 p1 b2 p0 b3 pN b0 p2 b0 p1 b3 p0 b2 pN b1 p0 b1 pN b2 p0 b0 pN b3 Reverse order p0 b0 SIO_DO SIO_DI 5.7.6.1 pN b3 p0 b1 pN b2 p0 b3 p0 b2 pN b1 pN b0 p1 b0 p1 b1 p1 b2 p1 b2 p1 b3 pN-1 pN-1 pN-1 pN-1 pN-2 b3 b2 b1 b0 b3 pN b0 p2 b0 p0 b3 pN b1 p0 b2 pN b2 p0 b1 pN b3 p0 b0 Output Modes The output mode of each SGPIO can be individually configured in SIO_PORT_CONFIG.BIT_SOURCE. The SIO controller features three output modes: • • • Static Blink Link activity Static Mode The static mode is used to assign a fixed value to the SGPIO, for example, fixed 0 or fixed 1. Blink Mode The blink mode makes the SGPIO blink at a fixed rate. The SIO controller features two blink modes that can be set independently. A SGPIO can then be configured to use either blink mode 0 or blink mode 1. The blink outputs are configured in SIO_CONFIG.SIO_BMODE_0 and SIO_CONFIG.SIO_BMODE_1. To synchronize the blink modes between different devices, reset the blink VMDS-10392 VSC7420-02, VSC7421-02, and VSC7422-02 Datasheet Revision 4.3 118 VCore-Ie System and CPU Interface counter using SIO_CONFIG.SIO_BLINK_RESET. The “burst toggle” mode of blink mode 1 toggles the output with every burst. Table 102 • Blink Modes Mode Description Blink mode 0 0: 20 Hz blink frequency 1: 10 Hz blink frequency 2: 5 Hz blink frequency 3: 2.5 Hz blink frequency Blink mode 1 0: 20 Hz blink frequency 1: 10 Hz blink frequency 2: 5 Hz blink frequency 3: Burst toggle Link Activity Mode The link activity mode makes the output blink when there is activity on the port module (Rx or Tx). The mapping between SIO port number port module number is 1:1, For example, port 0 is connected to port module 0, port 1 is connected to port module 1, and so on. The link activity mode uses an envelope signal to gate the selected blinking pattern (blink mode 0 or blink mode 1). When the envelope signal is asserted, the output blinks, and when the envelope pattern is deasserted, the output is turned off. To ensure that even a single packet makes a visual blink, an activity pulse from the port module is extended to minimum 100 ms. If another packet is sent while the envelope signal is asserted, the activity pulse is extended by another 100 ms. The polarity of the link activity modes can be set in SIO_PORT_CONFIG.BIT_SOURCE. The following illustration shows the link activity timing. Figure 42 • Link Activity Timing 100 ms pulse MAC Pulse Envelope Blink Mode Output 5.7.6.2 SIO Interrupt The SIO controller can generate interrupts based on the value of the input value of the SGPIOs. All interrupts are level sensitive. Interrupts are enabled using the two registers. Interrupts can be individually enabled for each port in SIO_PORT_INT_ENA.INT_ENA (32 bits) and in SIO_CONFIG.SIO_INT_ENA (4 bits) interrupts are enabled for the four inputs per port. In other words, SIO_CONFIG.SIO_INT_ENA is common for all 32 ports. The polarity of interrupts is configured for each SGPIO in SIO_INT_POL. The SIO controller has one interrupt output connected to the main interrupt controller, which is asserted when one or more interrupts are active. To determine which SGPIO is causing the interrupt, the CPU must read the sticky bit interrupt register SIO_INT_REG. The register has one bit per SGPIO and can only be cleared by software. A bit is cleared by writing a 1 to the bit position. The interrupt output remains high until all interrupts in SIO_INT_REG are cleared. 5.7.6.3 Loss of Signal Detection The SIO controller can propagate loss of signal detection inputs directly to the signal detection input of the port modules. This is useful when, for example, SFP modules are connected to the device. The mapping between SIO ports and port modules is the same as for the link activity inputs; port 0 is connected to port module 0, port1 is connected to port module 1, and so on. VMDS-10392 VSC7420-02, VSC7421-02, and VSC7422-02 Datasheet Revision 4.3 119 VCore-Ie System and CPU Interface The value of SGPIO bit 0 of each SIO port is forwarded directly to the loss of signal input on the corresponding device. The device must enable the loss of signal input locally in the device. The polarity of the loss of signal input is configured using SIO_INT_POL, meaning the same polarity must be used for loss of signal detect and interrupt. 5.7.7 FAN Controller The VSC7420-02, VSC7421-02, and VSC7422-02 devices include a fan controller that can be used to control and monitor a system fan. The fan speed is regulated using a pulse-width-modulation (PWM) output. The fan speed is monitored using a TACHO input. This is especially powerful when combined with the internal temperature sensor (in the PHY). The following table lists the registers associated with the fan controller. Table 103 • Fan Controller Registers Register Description FAN_CFG General configuration FAN_CNT Fan revolutions counter The following table lists the pins of the fan controller. The pins of the fan controller are overlaid on GPIOs. For more information about enabling the overlaid functionality of GPIOs, see Overlaid Functions on the GPIOs, page 115. Table 104 • Fan Controller Pins Pin Name I/O Description TACHO/GPIO_4 I TACHO input for counting revolutions. PWM/GPIO_29 O PWM fan output. The PWM output can be configured to any of the following frequencies in FAN_CFG.PWM_FREQ: • • • • • • • • 10 Hz 20 Hz 40 Hz 60 Hz 80 Hz 100 Hz 120 Hz 25 kHz The low frequencies can be used for driving three-wire fans using a FET/transistor. The 25 kHz frequency can be used for four-wire fans that use the PWM input internally to control the fan. The duty cycle of the PWM output is programmable from 0% to 100%, with 8-bit accuracy. The polarity of the output can be controlled by FAN_CFG.INV_POL, so a duty-cycle of 100%, for example, can be either always low or always high. The PWM output pin can be configured to act as a normal output or as an open-collector output, where the output value of the pin is kept low, but the output enable is toggled. The open-collector output mode is enabled by setting FAN_CFG.PWM_OPEN_COL_ENA. Note By using open-collector mode, it is possible to do external pull-up to higher voltage than the maximum GPIO I/O supply. The GPIOs are 5V-tolerable. The speed of the fan can be measured using a 16-bit wrapping counter that counts the rising edges on the TACHO-input. A fan usually gives 1-4 pulses per revolution depending on the fan type. Optionally, the TACHO-input can be gated by the polarity-corrected PWM output by setting FAN_CFG.GATE_ENA, so that only TACHO pulses received while the polarity corrected PWM output is high are counted. Glitches on the TACHO-input can occur right after the PWM output goes high, therefore the gate signal is delayed VMDS-10392 VSC7420-02, VSC7421-02, and VSC7422-02 Datasheet Revision 4.3 120 VCore-Ie System and CPU Interface by 10 µs when PWM goes high. There is no delay when PWM goes low, and the length of the delay is not configurable. Software reads the counter value in FAN_CNT and calculates the RPM of the fan. The following is an example of how to calculate the RPM of the fan: If the fan controller is configured to 100 Hz and a 20% duty cycle, each PWM pulse is high in 2 ms and low in 8 ms. If gating is enabled the gating of the TACHO-input is “open” in 1.99 ms and “closed” in 8.01 ms. If the fan is turning with 100 RPM and gives two TACHO pulses per revolution, it will ideally give 200 pulses per minute. TACHO pulses are only counted in 19.99% of the time, so it will give 200× 0.1999 = 39.98 pulses per minute. If the additional 10 µs gating time is ignored, the counter value is multiplied by 5/2 to get the RPM value, because there is a 20% duty cycle with two TACHO pulses per revolution. By multiplying with 5/2, the RPM value is calculated to 99.95, which is 0.05% off the correct value (due to the 10 µs gating time). 5.7.8 Interrupt Controller This section provides information about the VCore-Ie interrupt controller. The following table lists the registers associated with the interrupt controller. Table 105 • Interrupt Controller Registers Register Description Configuration and status for interrupts ICPU_IRQ0_ENA Global enable of ICPU_IRQ0 interrupt ICPU_IRQ0_IDENT Currently interrupting ICPU_IRQ0 sources ICPU_IRQ1_ENA Global enable of ICPU_IRQ1 interrupt ICPU_IRQ1_IDENT Currently interrupting ICPU_IRQ1 sources EXT_IRQ0_ENA Global enable of EXT_IRQ0 interrupt EXT_IRQ0_IDENT Currently interrupting EXT_IRQ0 sources Configuration of individual interrupt sources EXT_IRQ0_INTR_CFG EXT_IRQ0 source configuration SW0_INTR_CFG SW0 source configuration SW1_INTR_CFG SW1 source configuration UART_INTR_CFG UART source configuration TIMER0_INTR_CFG TIMER0 source configuration TIMER1_INTR_CFG TIMER1 source configuration TIMER2_INTR_CFG TIMER2 source configuration TWI_INTR_CFG TWI source configuration GPIO_INTR_CFG GPIO source configuration SGPIO_INTR_CFG SGPIO source configuration DEV_ALL_INTR_CFG DEV_ALL source configuration XTR_RDY0_INTR_CFG XTR_RDY0 source configuration XTR_RDY1_INTR_CFG XTR_RDY1 source configuration INJ_RDY0_INTR_CFG INJ_RDY0 source configuration INJ_RDY1_INTR_CFG INJ_RDY1 source configuration MIIM0_INTR_CFG MIIM0 source configuration MIIM1_INTR_CFG MIIM1 source configuration General enable/disable and status for all interrupt sources INTR Interrupt sticky bits VMDS-10392 VSC7420-02, VSC7421-02, and VSC7422-02 Datasheet Revision 4.3 121 VCore-Ie System and CPU Interface Table 105 • Interrupt Controller Registers (continued) Register Description INTR_ENA Interrupt enable INTR_ENA_SET Atomic set of bits in INTR_ENA INTR_ENA_CLR Atomic clear of bits in INTR_ENA INTR_RAW Raw value of interrupt from sources DEV_IDENT Currently interrupting DEV_ALL sources Possible sources of the DEV_ALL interrupt are: • • • • • Fast link status from the PHYs for port 0 through 11 (DEV_IDENT[11:0]) PCS link status from the PCS for port 12 through 25 (DEV_IDENT[25:12]) PCS link status from the PCS for port 10 (DEV_IDENT[26]) PCS link status from the PCS for port 11 (DEV_IDENT[27]) Global PHY interrupt (DEV_IDENT[28]) Each of the interrupt sources in the VCore-Ie system can be individually assigned to one of three possible interrupt outputs: Two ICPU_IRQ interrupt outputs go directly to the VCore-Ie CPU, and one EXT_IRQ interrupt allows interrupting external devices. Each interrupt output has a global enable register, ICPU_IRQ0_ENA, ICPU_IRQ1_ENA, and EXT_IRQ0_ENA. This register must be set in order for the interrupt outputs to propagate interrupts. When there is an active interrupt on any interrupt output, the ICPU_IRQ0_IDENT, ICPU_IRQ1_IDENT, and EXT_IRQ0_IDENT registers show the active interrupt sources for each individual interrupt. The EXT_IRQ0 pin is special, because it is an overlaid function on the GPIO interface. The active level of the EXT_IRQ0 pin is configured individually through the INTR_POL field of EXT_IRQ0_INTR_CFG. Additionally, the EXT_IRQ0 pin operates as an either interrupt output or as an interrupt source. This is individually configured through the INTR_DIR field of EXT_IRQ0_INTR_CFG. When operating as an output, the EXT_IRQ0 pin can be tri-stated when there is no interrupt. This is configured through the field INTR_DRV in EXT_IRQ0_INTR_CFG field. For more information about the location on the GPIOs and how to enable the overlaid function, see GPIO Controller, page 114. When an interrupt output is configured to drive only during interrupt, interrupt outputs from multiple devices can be connected in parallel with a pull-resistor to make wired-or/and interrupts. EXT_IRQ0_INTR_CFG must be configured before enabling the overlaid GPIO function. The following illustration depicts ICPU_IRQ0 and EXT_IRQ0. Figure 43 • Logical Equivalent for Interrupt Outputs ICPU_IRQ0_ENA Active interrupt sources with ICPU_IRQ0 as destination all sources OR ICPU_IRQ0 AND ICPU_IRQ0_IDENT EXT_IRQ0_DIR EXT_IRQ0_DRV EXT_IRQ0_ENA Active interrupt sources with EXT_IRQ0 as destination all sources OR AND XOR EXT_IRQ0_IDENT Source: EXT_IRQ0 when not configured as output AND OR EXT_IRQ0 EXT_IRQ0_POL XOR Note Internally in the device, all interrupt sources are active high. VMDS-10392 VSC7420-02, VSC7421-02, and VSC7422-02 Datasheet Revision 4.3 122 VCore-Ie System and CPU Interface Each interrupt source has its own configuration register (*_INTR_CFG). The sticky functionality can be bypassed by means of the INTR_BYPASS field. For software development, an interrupt event can be emulated by setting the one-shot INTR_FORCE field. The destination interrupt output is configured through the INTR_SEL field. Interrupt outputs can have many sources, but each source can only have one destination. The bypass feature can be useful when only a single, or just a few, interrupt source is enabled for a specific interrupt output. When stickiness in the interrupt controller is bypassed, clearing the interrupt indication at its source also clears the associated interrupt. If an interrupt source indicates an interrupt, the associated field in the INTR register is set, this is a sticky indication. The current interrupt inputs from the sources are available through INTR_RAW. For an interrupt to propagate to its destination, it must be enabled by setting the associated INTR_ENA field. In a system where multiple different CPU threads (or different CPUs) may work on the interrupts at the same time, the INTR_ENA_SET and INTR_ENA_CLR registers provide a method for each thread to safely control enabling and disabling of the interrupts that are under their control, without having to implement locked regions and semaphores. The following illustration shows an example of the UART interrupt; however, it is representative to any other interrupt by substituting UART for the interrupt name. The timer interrupt sources are only asserted for a single clock cycle (when the timer wraps). As a result, the trigger and bypass functions (as depicted) are not needed (nor implemented) for the timer interrupt sources. Figure 44 • Logical Equivalent for Interrupt Sources Interrupt source; UART_INTR INTR_RAW.UART_RAW UART_INTR_CFG.UART_INTR_BYPASS 1 0 OR AND Interrupt indication from UART INTR.INTR_UART is sticky UART_INTR_CFG.UART_INTR_FORCE INTR_ENA.UART_INTR_ENA VMDS-10392 VSC7420-02, VSC7421-02, and VSC7422-02 Datasheet Revision 4.3 123 Features 6 Features This section provides information about specific features supported by individual blocks in the VSC7420-02, VSC7421-02, and VSC7422-02 devices and describes how these features are administrated by configurations across the entire device. Examples of various standard features are described such as the support for different spanning tree versions and VLAN operations, and more advanced features, such as QoS. 6.1 Port Mapping This section provides information about the mapping from switch core port modules to SerDes type to physical interface pins on the VSC7420-02, VSC7421-02, and VSC7422-02 devices. When accessing port module registers (PORT::), port masks in the analyzer, or in general, whenever a switch core register refers to a port, the internal switch port module number must be used. 6.1.1 VSC7420-02 Port Mapping The internal port modules in the switch core maps to external pins on the VSC7420-02 device according to the following table. Table 106 • VSC7420-02: Mapping from Port Modules to Physical Interface Pins Port Number Switch Port Module Interface Type 0–7 0–7 Internal PHY 8 24 2.5G SGMII SERDES6G SerDes_E1_TxP, SerDes_E1_TxN, SerDes_E1_RxP, SerDes_E1_RxN 9 25 2.5G SGMII SERDES6G SerDes_E0_TxP, SerDes_E0_TxN, SerDes_E0_RxP, SerDes_E0_RxN 26 CPU port 6.1.2 SerDes Type Interface Pins Px_D[3:0]N, Px_D[3:0]P, where x is 0 through 7 VSC7421-02 Port Mapping The VSC7421-02 device has the option to run in one of two switch modes controlling the type and number of external Ethernet interfaces: • • Switch mode 0 enables 12× CuPHY + 1× QSGMI + 1× 2.5G SGMII Switch mode 1 enables 12× CuPHY + 2× 1G SGMII + 2× 2.5G SGMII The switch mode is controlled through DEVCPU_GCB::MISC_CFG.SW_MODE. The internal port modules in the switch core maps to the external pins on the VSC7421-02 device as shown in the following tables. Table 107 • VSC7421-02 in Switch Mode 0: Mapping from Port Modules to Physical Interface Pins Port Number Switch Port Module Interface Type SerDes Type 0 – 11 0 – 11 Internal PHY 12 – 15 12 – 15 QSGMII SERDES6G SerDes_E3_TxP, SerDes_E3_TxN, SerDes_E3_RxP, SerDes_E3_RxN 16 25 2.5G SGMII SERDES6G SerDes_E0_TxP, SerDes_E0_TxN, SerDes_E0_RxP, SerDes_E0_RxN Interface Pins Px_D[3:0]N, Px_D[3:0]P, where x is 0 through 11 VMDS-10392 VSC7420-02, VSC7421-02, and VSC7422-02 Datasheet Revision 4.3 124 Features Table 107 • VSC7421-02 in Switch Mode 0: Mapping from Port Modules to Physical Interface Pins Port Number Switch Port Module Interface Type 26 CPU port SerDes Type Interface Pins Table 108 • VSC7421-02 in Switch Mode 1: Mapping from Port Modules to Physical Interface Pins Port Number Switch Port Module Interface Type 0 – 11 0 – 11 Internal PHY 12 16 1G SGMII SERDES6G SerDes_E3_TxP, SerDes_E3_TxN, SerDes_E3_RxP, SerDes_E3_RxN 13 19 1G SGMII SERDES6G SerDes_E2_TxP, SerDes_E1_TxN, SerDes_E2_RxP, SerDes_E1_RxN 14 24 2.5G SGMII SERDES6G SerDes_E1_TxP, SerDes_E1_TxN, SerDes_E1_RxP, SerDes_E1_RxN 15 25 2.5G SGMII SERDES6G SerDes_E0_TxP, SerDes_E0_TxN, SerDes_E0_RxP, SerDes_E0_RxN 26 CPU port 6.1.3 SerDes Type Interface Pins Px_D[3:0]N, Px_D[3:0]P, where x is 0 through 11 VSC7422-02 Port Mapping The internal port modules in the switch core maps to external pins on the VSC7422-02 device as shown in the following table. Table 109 • VSC7422-02: Mapping from Port Modules to Physical Interface Pins 6.2 Switch Port Port Number Module Interface Type SerDes Type 0 – 11 0 – 11 Internal PHY 12 – 15 12 – 15 QSGMII SERDES6G SerDes_E3_TxP, SerDes_E3_TxN, SerDes_E3_RxP, SerDes_E3_RxN 16 – 19 16 – 19 QSGMII SERDES6G SerDes_E2_TxP, SerDes_E2_TxN, SerDes_E2_RxP, SerDes_E2_RxN 20-23 20-23 QSGMII SERDES6G SerDes_E1_TxP, SerDes_E1_TxN, SerDes_E1_RxP, SerDes_E1_RxN 24 25 2.5G SGMII SERDES6G SerDes_E0_TxP, SerDes_E0_TxN, SerDes_E0_RxP, SerDes_E0_RxN 26 CPU port Interface Pins Px_D[3:0]N, Px_D[3:0]P, where x is 0 through 11 Switch Control This section provides information about the minimum requirements for switch operation. 6.2.1 Switch Initialization The following initialization sequence is required to ensure proper operation of the switch: VMDS-10392 VSC7420-02, VSC7421-02, and VSC7422-02 Datasheet Revision 4.3 125 Features 1. 2. 3. 4. 5. 6. 6.3 Configure the desired switch mode in DEVCPU_GCB::MISC_CFG.SW_MODE. Initialize memories: SYS.RESET_CFG.MEM_ENA = 1. SYS.RESET_CFG.MEM_INIT = 1. Wait 100 µs for memories to initialize (SYS.RESET_CFG.MEM_INIT cleared). Enable the switch core: SYS.RESET_CFG.CORE_ENA = 1. Release reset of the internal PHYs: DEVCPU_GCB.SOFT_CHIP_RST.SOFT_PHY_RST = 0. Enable each port module through SYS.PORT.SWITCH_PORT_MODE.PORT_ENA = 1. Port Module Control This section provides information about the features and configurations for port control, port reset procedures, and port counters. 6.3.1 MAC Configuration Port Mode Control All port modules can be configured independently to the speed and duplex modes listed in the following tables. Table 110 • MAC Configuration of Port Modes for Ports with Internal PHYs 10 Mbps, 10 Mbps, 100 Mbps, 100 Mbps, 1 Gbps, Full Half Duplex Full Duplex Half Duplex Full Duplex Duplex Configuration PORT::CLOCK_CFG.LINK_SPEED PORT::MAC_MODE_CFG.FDX_ENA 0 1 0 1 1 PORT::MAC_MODE_CFG.GIGA_MODE_ENA 0 0 0 0 1 SYS:PORT:FRONT_PORT_MODE.HDX_MOD 1 E 0 1 0 0 PORT::MAC_IFG_CFG.TX_IFG 17 17 17 17 5 PORT::MAC_IFG_CFG.RX_IFG1 11 11 PORT::MAC_IFG_CFG.RX_IFG2 9 9 PORT::MAC_HDX_CFG.LATE_COL_POS 64 64 0 0 SYS:PORT:FRONT_PORT_MODE.HDX_MOD 1 E 0 1 Table 111 • MAC Configuration of Port Modes for Ports with SerDes Configuration 10 Mbps, Half Duplex 10 Mbps, Full Duplex 1 Gbps, 100 Mbps, 100 Mbps, Full Half Duplex Full Duplex Duplex 2.5 Gbps, Full Duplex PORT::CLOCK_CFG.LINK_SPEED 3 3 2 2 1 1 PORT::MAC_MODE_CFG.FDX_ENA 0 1 0 1 1 1 PORT::MAC_MODE_CFG.GIGA_MODE 0 _ENA 0 0 0 1 1 SYS:FRONT_PORT_MODE.HDX_MOD 1 E 0 1 0 0 0 PORT::MAC_IFG_CFG.TX_IFG 15 15 15 15 5 5 PORT::MAC_IFG_CFG.RX_IFG1 11 7 VMDS-10392 VSC7420-02, VSC7421-02, and VSC7422-02 Datasheet Revision 4.3 126 Features Table 111 • MAC Configuration of Port Modes for Ports with SerDes (continued) Configuration 10 Mbps, Half Duplex PORT::MAC_IFG_CFG.RX_IFG2 9 10 Mbps, Full Duplex 6.3.2 2.5 Gbps, Full Duplex 9 PORT::MAC_HDX_CFG.LATE_COL_PO 67 S SYS::FRONT_PORT_MODE.HDX_MO DE 1 Gbps, 100 Mbps, 100 Mbps, Full Half Duplex Full Duplex Duplex 67 1 0 1 0 0 0 SerDes Configuration Port Mode Control The SerDes ports are configured according to the following table. Table 112 • SERDES6G Configuration Configuration 6.3.3 SGMII Mode 2.5G Mode QSGMII Mode hsio::serdes6g_pll_cfg.pll_rot_frq 0 1 0 hsio::serdes6g_pll_cfg.pll_rot_dir 1 0 0 hsio::serdes6g_pll_cfg.pll_ena_rot 0 1 0 hsio::serdes6g_common_cfg.ena_lane 1 1 1 hsio::serdes6g_common_cfg.if_mode 1 1 3 hsio::serdes6g_common_cfg.qrate 1 0 0 hsio::serdes6g_common_cfg.hrate 0 1 0 hsio::serdes6g_ib_cfg1.ib_reserved 1 1 1 Port Reset Procedure When changing a switch port’s mode of operation or restarting a switch port, the following port reset procedure must be followed: 1. 2. 3. 4. 5. 6. 7. Disable the MAC frame reception in the switch port: PORT::MAC_ENA_CFG.RX_ENA = 0. Disable traffic being sent to or from the switch port: SYS:PORT:SWITCH_PORT_MODE_ENA = 0 SYS:PORT:FRONT_PORT_MODE_HDX_MODE = 0. Disable shaping to speed up flushing of frames SYS:SCH_SHAPING_CTRL.PORT_SHAPING_ENA = 0, SYS:SCH_SHAPING_CTRL.PRIO_SHAPING_ENA = 0. Flush the queues associated with the port: REW:PORT:PORT_CFG.FLUSH_ENA = 1. Wait at least the time it takes to receive a frame of maximum length on the port Worst-case delays for 10 kilobyte jumbo frames are: 8 ms on a 10M port 800 µs on a 100M port 80 µs on a 1G port, 32 µs on a 2.5G port. Reset the switch port by setting the following reset bits in CLOCK_CFG: PORT::CLOCK_CFG.MAC_TX_RST = 1, PORT::CLOCK_CFG.MAC_RX_RST = 1, PORT::CLOCK_CFG.PORT_RST = 1, PORT::CLOCK_CFG.PHY_RST = 1 (if port is connected to an internal PHY). Wait until flushing is complete: SYS:PORT:SW_STATUS.EQ_AVAIL must return 0. VMDS-10392 VSC7420-02, VSC7421-02, and VSC7422-02 Datasheet Revision 4.3 127 Features 8. Clear flushing again: REW:PORT:PORT_CFG.FLUSH_ENA = 0. 9. Re-enable traffic being sent to or from the switch port: SYS:PORT:SWITCH_PORT_MODE.PORT_ENA = 1. 10. Set up the switch port to the new mode of operation. Keep the reset bits in CLOCK_CFG set. For more information about port mode configurations, see Table 110, page 126 or Table 111, page 126. 11. Release the switch port from reset by clearing the reset bits in CLOCK_CFG. It is not necessary to reset the SerDes macros. 6.3.4 Port Counters The statistics collected in each port module provide monitoring of various events. This section describes how industry-standard Management Information Bases (MIBs) can be implemented using the counter set in this device. The following MIBs are considered: • • • • 6.3.4.1 RMON statistics group (RFC 2819) IEEE 802.3-2005 Annex 30A counters SNMP interfaces group (RFC 2863) SNMP Ethernet-like group (RFC 3536) RMON Statistics Group (RFC 2819) The following table provides the mapping of RMON counters to port counters. Table 113 • Mapping of RMON Counters to Port Counters RMON Counter Rx/Tx Switch Core Implementation EtherStatsDropEvents Rx C_RX_CAT_DROP + C_DR_TAIL + sum of C_DR_GREEN_PRIO_x, where x is 0 through 7. EtherStatsOctets Rx C_RX_OCT EtherStatsPkts Rx C_RX_SHORT + C_RX_FRAG + C_RX_JABBER + C_RX_LONG + C_RX_SZ_64 + C_RX_SZ_65_127 + C_RX_SZ_128_255 + C_RX_SZ_256_511 + C_RX_SZ_512_1023 + C_RX_SZ_1024_1526 + C_RX_SZ_JUMBO EtherStatsBroadcastPkts Rx C_RX_BC EtherStatsMulticastPkts Rx C_RX_MC EtherStatsCRCAlignErrors Rx C_RX_CRC EtherStatsUndersizePkts Rx C_RX_SHORT EtherStatsOversizePkts Rx C_RX_LONG EtherStatsFragments Rx C_RX_FRAG EtherStatsJabbers Rx C_RX_JABBER EtherStatsPkts64Octets Rx C_RX_SZ_64 EtherStatsPkts65to127Octets Rx C_RX_SZ_65_127 EtherStatsPkts128to255Octets Rx C_RX_SZ_128_255 EtherStatsPkts256to511Octets Rx C_RX_SZ_256_511 EtherStatsPkts512to1023Octets Rx C_RX_SZ_512_1023 EtherStatsPkts1024to1518Octets Rx C_RX_SZ_1024_1526 EtherStatsDropEvents Tx C_TX_DROP + C_TX_AGE EtherStatsOctets Tx C_TX_OCT VMDS-10392 VSC7420-02, VSC7421-02, and VSC7422-02 Datasheet Revision 4.3 128 Features Table 113 • Mapping of RMON Counters to Port Counters (continued) 6.3.4.2 RMON Counter Rx/Tx Switch Core Implementation EtherStatsPkts Tx C_TX_SZ_64 + C_TX_SZ_65_127 + C_TX_SZ_128_255 + C_TX_SZ_256_511 + C_TX_SZ_512_1023 + C_TX_SZ_1024_1526 + C_TX_SZ_JUMBO EtherStatsBroadcastPkts Tx C_TX_BC EtherStatsMulticastPkts Tx C_TX_MC EtherStatsCollisions Tx C_TX_COL EtherStatsPkts64Octets Tx C_TX_SZ_64 EtherStatsPkts65to127Octets Tx C_TX_SZ_65_127 EtherStatsPkts128to255Octets Tx C_TX_SZ_128_255 EtherStatsPkts256to511Octets Tx C_TX_SZ_256_511 EtherStatsPkts512to1023Octets Tx C_TX_SZ_512_1023 EtherStatsPkts1024to1518Octets Tx C_TX_SZ_1024_1526 IEEE 802.3-2005 Annex 30A Counters This section provides the mapping of IEEE 802.3-2005 Annex 30A counters to port counters. Only counter groups with supported counters are listed. Table 114 • Mandatory Counters Counter Rx/Tx Switch Core Implementation aFramesTransmittedOK Tx C_TX_SZ_64 + C_TX_SZ_65_127 + C_TX_SZ_128_255 + C_TX_SZ_256_511 + C_TX_SZ_512_1023 + C_TX_SZ_1024_1526 + C_TX_SZ_JUMBO aSingleCollisionFrames Tx Does not apply aMultipleCollisionFrames Tx Does not apply aFramesReceivedOK Rx Sum of C_RX_GREEN_PRIO_x, where x is 0 through 7. aFrameCheckSequenceErrors Rx Not available. C_RX_CRC is the sum of FCS and alignment errors. aAlignmentErrors Rx Not available. C_RX_CRC is the sum of FCS and alignment errors. Table 115 • Optional Counters Counter Rx/Tx Switch Core Implementation aMulticastFramesXmittedOK Tx C_TX_MC aBroadcastFramesXmittedOK Tx C_TX_BC aMulticastFramesReceivedOK Rx C_RX_MC aBroadcastFramesReceivedOK Rx C_RX_BC aInRangeLengthErrors Rx Not available aOutOfRangeLengthField Rx Not available VMDS-10392 VSC7420-02, VSC7421-02, and VSC7422-02 Datasheet Revision 4.3 129 Features Table 115 • Optional Counters (continued) Counter Rx/Tx Switch Core Implementation aFrameTooLongErrors Rx C_RX_LONG Table 116 • Recommended MAC Control Counters Counter Rx/Tx Switch Core Implementation aMACControlFramesTransmitted Tx Not available aMACControlFramesReceived Rx C_RX_CONTROL aUnsupportedOpcodesReceived Rx Not available Table 117 • Pause MAC Control Recommended Counters Counter 6.3.4.3 Rx/Tx Switch Core Implementation aPauseMACControlFramesTransmitted Tx C_TX_PAUSE. Transmitted pause frames in 10/100 Mbps full-duplex are not counted. aPauseMACControlFramesReceived C_RX_PAUSE Rx SNMP Interfaces Group (RFC 2863) The following table provides the mapping of SNMP interfaces group counters to port counters. Table 118 • Mapping of SNMP Interfaces Group Counters to Port Counters Counter Rx/Tx Switch Core Implementation IfInOctets Rx C_RX_OCT IfInUcastPkts Rx C_RX_UC IfInNUcastPkts Rx C_RX_BC + C_RX_MC IfInBroadcast (RFC 1573) Rx C_RX_BC IfInMulticast (RFC 1573) Rx C_RX_MC IfInDiscards Rx C_DR_TAIL + C_RX_CAT_DROP IfInErrors Rx C_RX_CRC + C_RX_SHORT + C_RX_FRAG + C_RX_JABBER + C_RX_LONG IfInUnknownProtos Rx Always zero. IfOutOctets Tx C_TX_OCT IfOutUcastPkts Tx C_TX_UC IfOutNUcastPkts Tx C_TX_BC + C_TX_MC ifOutMulticast (RFC 1573) Tx C_TX_MC ifOutBroadcast (RFC 1573) Tx C_TX_BC IfOutDiscards Tx Always zero. IfOutErrors Tx C_TX_DROP + C_TX_AGE VMDS-10392 VSC7420-02, VSC7421-02, and VSC7422-02 Datasheet Revision 4.3 130 Features 6.3.4.4 SNMP Ethernet-Like Group (RFC 3536) The following table provides the mapping of SNMP Ethernet-like group counters to port counters. Table 119 • Mapping of SNMP Ethernet-Like Group Counters to Port Counters 6.4 Counter Rx/Tx Switch Core Implementation dot3StatsAlignmentErrors Rx Not available. C_RX_CRC is the sum of FCS and alignment errors. dot3StatsFCSErrors Rx Not available. C_RX_CRC is the sum of FCS and alignment errors. dot3StatsSingleCollisionFrames Tx Not available. dot3StatsMultipleCollisionFrames Tx Not available. dot3StatsSQETestErrors Rx Not applicable. dot3StatsDeferredTransmissions Tx Not available. dot3StatsLateCollisions Tx Not available. C_TX_DROP is the sum of Late collisions and Excessive collisions. dot3StatsExcessiveCollisions Tx Not available. C_TX_DROP is the sum of Late collisions and Excessive collisions. dot3StatsInternalMacTransmitErrors Tx Not applicable. Always 0. dot3StatsCarrierSenseErrors Tx Not available. dot3StatsFrameTooLongs Rx C_RX_LONG. dot3StatsInternalMacReceiveErrors Rx Not applicable. Always 0. dot3InPauseFrames Rx C_RX_PAUSE. dot3OutPauseFrames Tx C_TX_PAUSE. Transmitted pause frames in 10/100 Mbps full-duplex are not counted. Layer-2 Switch This section describes the Layer-2 switch features: • • • • • • • 6.4.1 Switching VLAN and GVRP Rapid Spanning Tree Link aggregation Port-based access control Mirroring SNMP support Basic Switching Basic switching covers forwarding, address learning, and address aging. 6.4.1.1 Forwarding The devices contain a Layer-2 switch and frames are forwarded using Layer-2 information only. The switch is designed to comply with the IEEE Bridging standard in IEEE 802.1D and the IEEE VLAN standard in IEEE 802.1Q: • • • Unicast frames are forwarded to a single destination port that corresponds to the DMAC. Multicast frames are forwarded to multiple ports determined by the DMAC multicast group. The CPU configures multicast groups in the MAC table and the port group identifier (PGID) table. A multicast group can span across any set of ports. Broadcast frames (DMAC = FF-FF-FF-FF-FF-FF) are, by default, flooded to all ports except the ingress port. Also, in compliance with the standard, a unicast or multicast frame with unknown VMDS-10392 VSC7420-02, VSC7421-02, and VSC7422-02 Datasheet Revision 4.3 131 Features DMAC is flooded to all ports except the ingress port. It is possible to configure flood masks to restrict the flooding of frames. There are separate flood masks for the following frame types: Unicast (ANA::FLOODING.FLD_UNICAST) Layer 2 multicast (ANA::FLOODING.FLD_MULTICAST) Layer 2 broadcast (ANA::FLOODING.FLD_BROADCAST) IPv4 multicast data (ANA::FLOODING_IPMC.FLD_MC4_DATA) IPv4 multicast control (ANA::FLOODING_IPMC.FLD_MC4_CTRL) IPv6 multicast data (ANA::FLOODING_IPMC.FLD_MC6_DATA) IPv6 multicast control (ANA::FLOODING_IPMC.FLD_MC6_CTRL) For frames with a known destination MAC address, the destination mask comes from an entry in the port group identifier table (ANA::PGID). The PGID table contains 107 entries (entry 0 through 106), where entry 0 through 63 are used for destination masks. The remaining PGID entries are used for other parts of the forwarding and are described below. The following table shows the PGID table organization. Table 120 • Port Group Identifier Table Organization Entry Type Number Unicast entries 0 – 26 (including CPU) Multicast entries 27 – 63 Aggregation Masks 64 – 79 Source Masks 80 – 106 The unicast entries contains only the port number corresponding to the entry number. Destination masks for multicast groups must be manually entered through the CPU into the destination masks table. IPv4 and IPv6 multicast entries can also be entered using direct encoding in the MAC table, where the destination masks table is not used. For information about forwarding and configuring destination masks, see MAC Table, page 48. The aggregation masks ensures that a frame is forwarded to exactly one member of an aggregation group. For all forwarding decisions, a source mask prevents frames from being sent back to the ingress port. The source mask removes the ingress port from the destination mask. All ports are enabled for receiving frames by default. This can be disabled by clearing ANA:PORT:PORT_CFG.RECV_ENA. 6.4.1.2 Address Learning The learning process minimizes the flooding of frames. A frame’s source MAC address is learned together with its VID. Each entry in the MAC table is uniquely identified by a (MAC,VID) pair. In the forwarding process, a frame’s (DMAC,VID) pair is used as the key for the MAC table lookup. The learning of unknown SMAC addresses can be either hardware-based or CPU-based. The following list shows the available learn schemes, which can be configured per port: • • Hardware-based learning autonomously adds entries to the MAC table without interaction from the CPU. Use the following configuration: ANA:PORT:PORT_CFG.LEARN_ENA = 1 ANA:PORT:PORT_CFG.LEARNCPU = 0 ANA:PORT:PORT_CFG.LEARNDROP = 0 ANA:PORT:PORT_CFG.LEARNAUTO = 1 CPU-based learning copies frames with unknown SMACs, or when the SMAC appears on a different port, to the CPU. These frames are forwarded as usual. Use the following configuration. ANA:PORT:PORT_CFG.LEARN_ENA = 1 ANA:PORT:PORT_CFG.LEARNCPU = 1 VMDS-10392 VSC7420-02, VSC7421-02, and VSC7422-02 Datasheet Revision 4.3 132 Features • • ANA:PORT:PORT_CFG.LEARNDROP = 0 ANA:PORT:PORT_CFG.LEARNAUTO = 0 Secure CPU-based learning is similar to CPU-based learning, except that it allows the CPU to verify the SMAC addresses before both learning and forwarding. Secure CPU-based learning redirects frames with unknown SMACs, or when the SMAC appears on a different port, to the CPU. These frames are not forwarded by hardware. Use the following configuration. ANA::PORT_CFG.LEARN_ENA = 1 ANA::PORT_CFG.LEARNCPU = 1 ANA::PORT_CFG.LEARNDROP = 1 ANA::PORT_CFG.LEARNAUTO = 0 No learning where all learn frames are discarded. Frames with known SMAC in the MAC table are forwarded by hardware. Use the following configuration. ANA:PORT:PORT_CFG.LEARN_ENA = 1 ANA:PORT:PORT_CFG.LEARNCPU = 0 ANA:PORT:PORT_CFG.LEARNDROP = 1 ANA:PORT:PORT_CFG.LEARNAUTO = 0 Frames forwarded to the CPU for learning can be extracted from the CPU extraction queue configured in ANA:PORT:CPUQ_CFG.CPUQ_LRN. During CPU-based learning, the rate of frames subject to learning being copied or redirected to the CPU can be controlled with the learn storm policer (ANA::STORMLIMIT_CFG[3]). This policer puts a limit on the number of frames per second that are subject to learning being copied or redirected to the CPU. The learn frames storm policer can help prevent a CPU from being overloaded when performing CPU based learning. 6.4.1.3 MAC Table Address Aging To keep the MAC table updated, an aging scan is conducted to remove entries that were not recently accessed. This ensures that stations that have moved to a new location are not permanently prevented from receiving frames in their new location. It also frees up MAC table entries occupied by obsolete stations to give room for new stations. In IEEE 802.1D, the recommended period for aging-out entries in the MAC address table is 300 seconds per entry. The device aging implementation checks for the aging-out of all the entries in the table. The first age scan sets the age bit for every entry in the table. The second age scan removes entries where the age bit has not been cleared since the first age scan. An entry’s age bit is cleared when a received frame’s (SMAC, VID) matches an entry’s (MAC, VID); that is, the station is active and transmits frames. To ensure that 300 seconds is the longest an entry can reside not accessed (and unchanged) in the table, the maximum time between age scans is 150 seconds. The device can conduct age scans in two ways: • • Automatic age scans CPU initiated age scans When using automatic aging, the time between age scans is set in the ANA::AUTOAGE register in steps of 1 second, in the range from 1 second to 12 days. When using CPU-initiated aging, the CPU implements the timing between age scans. A scan is initiated by sending an aging command to the MAC address table (ANA::MACACCESS. MAC_TABLE_CMD). The CPU-controlled age scan process can conveniently be used to flush the entire MAC table by conducting two age scans, one immediately after the other. Flushing selective MAC table entries is also possible. Incidents that require MAC table flushing are: • • Reconfiguration of Spanning Tree protocol port states, which may cause station moves to occur. If there is a link failure notification (identified by a PHY layer device), flush the MAC table on the specific port where the link failed. To deal with these incidents, the age scan process is configurable to run only for entries learned on a specified port or for a specified VLAN (ANA:: ANAGEFIL.VID_VAL). The filters can also be combined to do aging on entries that match both the specific port and the specific VLAN. VMDS-10392 VSC7420-02, VSC7421-02, and VSC7422-02 Datasheet Revision 4.3 133 Features Single entries can be flushed from the MAC table by sending the FORGET command to the MAC address table. 6.4.2 Standard VLAN Operation This section provides information about configuring and operating the devices as a standard VLANaware switch. For more information about using the switch as a Q-in-Q enabled provider bridge, see Provider Bridges and Q-in-Q Operation, page 137. For information about the use of private VLANs and asymmetric VLANs, see Private VLANs, page 141 and Asymmetric VLANs, page 145. The following table lists the port module registers for standard VLAN operation. Table 121 • Port Module Registers for Standard VLAN Operation Register/Register Field Description Replication MAC_TAGS_CFG Allows tagged frames to be 4 bytes longer than the length configured in MAC_MAXLEN_CFG. Per port The following table lists the analyzer configurations and status bits for standard VLAN operation. Table 122 • Analyzer Registers for Standard VLAN Operation Register/Register Field Description Replication DROP_CFG.DROP_UNTAGGED_ENA Discard untagged frames. Per port DROP_CFG.DROP_C_TAGGED_ENA Discard VLAN tagged frames. Per port DROP_CFG.DROP_PRIO_C_TAGGED_ENA Discard priority tagged frames. Per port VLAN_CFG.VLAN_AWARE_ENA Use incoming VLAN tags in VLAN classification. Per port VLAN_CFG.VLAN_POP_CNT Remove VLAN tags from frames in the rewriter. Per port VLAN_CFG.VLAN_DEI VLAN_CFG.VLAN_PCP VLAN_CFG.VLAN_VID Ingress port VLAN configuration. Per port VLANMASK Per-port VLAN ingress filtering enable. None ANEVENTS.VLAN_DISCARD A sticky bit indicating that a frame was None dropped due to lack of VLAN membership of source port. ADVLEARN.VLAN_CHK Disable learning for frames discarded due to None source port VLAN membership check. VLANACCESS VLAN table command. For indirect access to None configuration of the 4096 VLANs. VLANTIDX VLAN table index. For indirect access to configuration of the 4096 VLANs. None AGENCTRL.FID_MASK Enable shared VLAN learning. None CPU_FWD_GARP_CFG Per port Enable capture of frames with reserved GARP DMAC addresses, including GVRP for VLAN registration. Per-address configuration. CPUQ_8021_CFG.CPUQ_GARP_VAL CPU queue for captured GARP frames. Per GARP address VMDS-10392 VSC7420-02, VSC7421-02, and VSC7422-02 Datasheet Revision 4.3 134 Features The following table lists the rewriter registers for standard VLAN operation. Table 123 • Rewriter Registers for Standard VLAN Operation Register/Register Field Description Replication TAG_CFG Egress VLAN tagging configuration Per port PORT_VLAN_CFG Egress port VLAN configuration Per port In a VLAN-aware switch, each port is a member of one or more virtual LANs. Each incoming frame must be assigned a VLAN membership and forwarded according to the assigned VID. The following information draws on the definitions and principles of operations in IEEE 802.1Q. Note that the switch supports more features than mentioned in the following section, which only describes the basic requirements for a VLAN aware switch. Standard VLAN operation is configured individually per switch port using the following configuration: • • MAC_TAGS_CFG.VLAN_AWR_ENA = 1 MAC_TAGS_CFG.VLAN_LEN_AWR_ENA = 1 VLAN_CFG.VLAN_AWARE_ENA = 1, VLAN_CFG.VLAN_POP_CNT = 1. Each switch port has an Acceptable Frame Type parameter, which is set to Admit Only VLAN tagged frames or Admit All Frames: • • Admit Only VLAN-tagged frames: DROP_CFG.DROP_UNTAGGED_ENA = 1, DROP_CFG.DROP_PRIO_C_TAGGED_ENA = 1, DROP_CFG.DROP_C_TAGGED = 0. Admit All Frames: DROP_CFG.DROP_UNTAGGED_ENA = 0, DROP_CFG.DROP_PRIO_C_TAGGED_ENA = 0, DROP_CFG.DROP_C_TAGGED = 0. Frames that are not discarded are subject to the VLAN classification. Untagged and priority-tagged frames are classified to a Port VLAN Identifier (PVID). The PVID is configured per port in VLAN_CFG.VLAN_VID. Tagged frames are classified to the VID given in the frame’s tag. For more information about VLAN classification, see VLAN Classification, page 44. 6.4.2.1 Forwarding Forwarding is always based on the combination of the classified VID and the destination MAC address. By default, all switch ports are members of all VLANs. This can be changed in VLANACCESS and VLANTIDX where port masks per VLAN are set up. 6.4.2.2 Ingress Filtering VLAN ingress filtering can be enabled per switch port with the register VLANMASK and per router port with MACx_CFG.INGRESS_CHK. The filter checks for all incoming frames to determine if the ingress port is a member of the VLAN to which the frame is classified. If the port is not a member, the frame is discarded. Whenever a frame is discarded due to lack of VLAN membership, the ANEVENTS.VLAN_DISCARD sticky bit is set. To ensure that VLAN ingress filtered frames are not learned, ADVLEARN.VLAN_CHK must be set. 6.4.2.3 GARP VLAN Registration Protocol (GVRP) GARP VLAN Registration Protocol (GVRP) is used to propagate VLAN configurations between bridges. On a GVRP-enabled switch, all GVRP frames must be redirected to the CPU for further processing. The GVRP frames use a reserved GARP MAC address (01-80-C2-00-00-21) and can be redirected to the CPU by setting bit 1 in the analyzer register CPU_FWD_GARP_CFG. 6.4.2.4 Shared VLAN Learning The devices can be configured for either Independent VLAN learning or Shared VLAN learning. Independent VLAN learning is the default. VMDS-10392 VSC7420-02, VSC7421-02, and VSC7422-02 Datasheet Revision 4.3 135 Features Shared VLAN learning, where multiple VLANs map to the same filtering database, is enabled through Filter Identifiers (FIDs). Basically, this means that learning is unique for a (MAC, FID) set and that a learned MAC address is learned for all VIDs that map to the FID. Shared VLAN learning is enabled in AGENCTRL.FID_MASK. The 12-bit FID mask sets which bits in the VID are indifferent to the learning. For example, if the least significant two bits are set in the FID mask, the following VID sets are sharing learning, where X and Y are any hexadecimal digits: • • • • 6.4.2.5 VID set 1: 0xXY0, 0xXY1, 0xXY2, 0xXY3 VID set 2: 0xXY4, 0xXY5, 0xXY6, 0xXY7 VID set 3: 0xXY8, 0xXY9, 0xXYA, 0xXYB VID set 4: 0xXYC, 0xXYD, 0xXYE, 0xXYF Untagging An untagged set can be configured for each egress port, which defines the VIDs for which frames are transmitted untagged. The untagged set can consist of zero, one, or all VIDs. For all VIDs not in the untagged set, frames are transmitted tagged. The available configurations are: • • • The untagged set is empty: TAG_CFG.TAG_CFG = 3. The untagged set consists of all VIDs: TAG_CFG.TAG_CFG = 0. The untagged set consists of one VID : TAG_CFG.TAG_CFG = 1. PORT_VLAN_CFG.PORT_VID = . Optionally, frames received as priority-tagged frames (VID = 0) can also be transmitted as untagged (TAG_CFG.TAG_CFG=2). 6.4.2.5.1 Port-Based VLAN Example Situation: Ports 0 and 1 are isolated from ports 2 and 3 using port-based VLANs. Ports 0 and 1 are assigned port VID 1 and ports 2 and 3 port VID 2. All frames in the network are untagged. Resolution: # Port module configuration of ports 0 – 1. # Configure the ports to always use the port VID. VLAN_CFG.VLAN_AWARE_ENA = 0 # Allow only untagged frames. DROP_CFG.DROP_UNTAGGED_ENA = 0 DROP_CFG.DROP_PRIO_C_TAGGED = 1 DROP_CFG.DROP_C_TAGGED = 1 # Configure the port VID to 1. VLAN_CFG.VLAN_VID = 1 # Port module configuration of ports 2 – 3. # Same as for ports 0-1, except that the port VID is set to 2. VLAN_CFG.VLAN_VID = 2 # Analyzer configuration. # Configure VLAN 1 to contain ports 0-1. VLANTIDX.INDEX = 1 VLANTIDX.VLAN_PRIV_VLAN = 0 VLANTIDX.VLAN_MIRROR = 0 (don’t care, for this example) VLANTIDX.VLAN_LEARN_DISABLE = 0 VLANTIDX.VLAN_SRC_CHK = 1 VLANACCESS.VLAN_PORT_MASK = 0x03 VLANACCESS.VLAN_TBL_CMD = 2 # Configure VLAN 2 to contain ports 2-3. VLANTIDX.INDEX = 2 VMDS-10392 VSC7420-02, VSC7421-02, and VSC7422-02 Datasheet Revision 4.3 136 Features VLANTIDX.VLAN_PRIV_VLAN = 0 VLANTIDX.VLAN_MIRROR = 0 (don’t care, for this example) VLANTIDX.VLAN_LEARN_DISABLE = 0 VLANTIDX.VLAN_SRC_CHK = 1 VLANACCESS.VLAN_PORT_MASK = 0x0C VLANACCESS.VLAN_TBL_CMD = 2 6.4.3 Provider Bridges and Q-in-Q Operation The following table lists the port module configurations for provider bridge VLAN operation. Table 124 • Port Module Configurations for Provider Bridge VLAN Operation Register/Register Field Description Replication MAC_TAGS_CFG Allow single tagged frames to be 4 bytes longer and double-tagged frames to be 8 bytes longer than the length configured in MAC_MAXLEN_CFG. Per port The following table lists the port module configurations for provider bridge VLAN operation. Table 125 • System Configurations for Provider Bridge VLAN Operation Register/Register Field Description Replication VLAN_ETYPE_CFG.VLAN_S_T TPID for S-tagged frames. EtherType Per port AG_ETYPE_VAL 0x88A8 and the configurable value VLAN_ETYPE_CFG.VLAN_S_TAG_E TYPE_VAL are identified as the S-tag identifier. The following table lists the analyzer configurations for provider bridge VLAN operation. Table 126 • Analyzer Configurations for Provider Bridge VLAN Operation Register/Register Field Description Replication DROP_CFG.DROP_UNTAGGE Discard untagged frames. D_ENA Per port DROP_CFG.DROP_S_TAGGED Discard VLAN S-tagged frames. _ENA Per port DROP_CFG.DROP_PRIO_S_TA Discard priority S-tagged frames. GGED_ENA Per port VLAN_CFG.VLAN_AWARE_EN Use incoming VLAN tags in VLAN A classification. Per port VLAN_CFG.VLAN_POP_CNT Remove VLAN tags from frames in the Per port rewriter. VLAN_CFG.VLAN_TAG_TYPE Tag type for untagged frames (Customer tag or service tag). Per port VLAN_CFG.VLAN_INNER_TAG Use inner tag for VLAN classification _ENA instead of outer tag. Per port VLAN_CFG.VLAN_DEI VLAN_CFG.VLAN_PCP VLAN_CFG.VLAN_VID Per port Ingress port VLAN configuration. VMDS-10392 VSC7420-02, VSC7421-02, and VSC7422-02 Datasheet Revision 4.3 137 Features Table 126 • Analyzer Configurations for Provider Bridge VLAN Operation (continued) Register/Register Field Description Replication VLANACCESS VLAN table command. For indirect access to configuration of the 4096 VLANs. None VLANTIDX VLAN table index. For indirect access None to configuration of the 4096 VLANs. The devices support the standard provider bridge features in IEEE 802.1ad (Provider Bridges). The features related to provider bridges are: • • • • Support for multiple tag headers (EtherTypes 0x8100, 0x88A8, and a programmable value are recognized as tag header EtherTypes) Pushing and popping of one VLAN tag Selective VLAN classification using either inner or outer VLAN tag Enabling or disabling learning per VLAN The following section discusses briefly how to configure these different features in the switch. The devices support multiple VLAN tags. They can be used in MAN applications as a provider bridge, aggregating traffic from numerous independent customer LANs into the MAN space. One of the purposes of the provider bridge is to recognize and use VLAN tags so that the VLANs in the MAN space can be used independent of the customers’ VLANs. This is accomplished by adding a VLAN tag with a MAN-related VID for frames entering the MAN. When leaving the MAN, the tag is stripped, and the original VLAN tag with the customer-related VID is again available. This provides a tunneling mechanism to connect remote customer VLANs through a common MAN space without interfering with the VLAN tags. All tags use EtherType 0x8100 for customer tags and EtherType 0x88A8, or a programmable value, for service provider tags. If a given service VLAN only has two member ports on the switch, the learning can be disabled for the particular VLAN (VLANTIDX.VLAN_LEARN_DISABLE) and can rely on flooding as the forwarding mechanism between the two ports. This way, the MAC table requirements are reduced. 6.4.3.0.1 MAN Access Switch Example Situation: The following is an example of setting up the device as a MAN access switch with these requirements: • • • Customer ports are aggregated into a network port for tunneling through the MAN to access remote VLANs. Local switching between ports of the different customers must be eliminated. Frames must be label-switched from network port to correct customer port without need for MAC address learning. VMDS-10392 VSC7420-02, VSC7421-02, and VSC7422-02 Datasheet Revision 4.3 138 Features Figure 45 • MAN Access Switch Setup Frames in This Segment Service Provider Tag (Outer Tag) Customer Tag (Inner Tag) EtherType VID EtherType 0x88A8 1 0x8100 1 0x88A8 1 0x8100 118 0x88A8 1 0x8100 0 Priority-tagged frames to/from customer 1 0x88A8 2 0x8100 1 Frames to/from customer 2's VLAN 1 0x88A8 2 0x8100 4 Frames to/from customer 2's VLAN 4 0x88A8 2 N/A N/A Untagged frames to/from customer 2 VID Description Frames to/from customer 1's VLAN 1 Frames to/from customer 1's VLAN 118 MAN Service-Provider Domain 16 8 9 MAN Port / Network Port Customer Ports Customer 1's LAN Frames in This Segment Customer Tag EtherType Customer 2's LAN Frames in This Segment Customer Tag VID 0x8100 1 0x8100 118 0x8100 0 Description Frames in Customer 1's VLAN 1 Frames in Customer 1's VLAN 118 Customer 1's Priority-Tagged Frames EtherType VID Description 0x8100 1 Frames in Customer 2's VLAN 1 0x8100 4 Frames in Customer 2's VLAN 4 N/A N/A Customer 2's Untagged Frames This example is typically accomplished by letting each customer port have a unique port VID (PVID), which is used in the outer VLAN tag (the service provider tag). In the MAN, the VID directly indicates the customer port from which the frame is received or the customer port to which the frame is going. A customer port is VLAN-unaware and classifies to a port-based VLAN. In the egress direction of the customer port, frames are transmitted untagged, which facilitates the stripping of the outer tag. That is, the provider tag is stripped, but the customer tag is kept. The port must allow frames with a maximum size of 1522 bytes. VMDS-10392 VSC7420-02, VSC7421-02, and VSC7422-02 Datasheet Revision 4.3 139 Features Resolution: # Configuration of customer 1’s port (port 8). # Allow for a single VLAN tag in the length check and set the maximum length without VLAN # tag to 1518 bytes. MAC_TAGS_CFG.VLAN_LEN_AWR_ENA = 1 MAC_TAGS_CFG.VLAN_AWAR_ENA = 1 MAC_MAXLEN_CFG.MAX_LEN = 1518 # Configure the port to leave any incoming tags in the frame and to ignore any # incoming VLAN tags in the VLAN classification. The port VID is always used in the # VLAN classification. VLAN_CFG.VLAN_POP_CNT = 0 VLAN_CFG.VLAN_AWARE_ENA = 0 # Allow both C-tagged and untagged frames coming in to the device to also support customer traffic not using VLANs to be carried across the MAN. DROP_CFG.DROP_UNTAGGED_ENA = 0 DROP_CFG.DROP_C_TAGGED = 0 DROP_CFG.DROP_PRIO_C_TAGGED = 0 DROP_CFG.DROP_S_TAGGED = 1 DROP_CFG.DROP_PRIO_S_TAGGED = 1 # Use service provider tagging when frames from this port exit the switch. # (EtherType 0x88A8). VLAN_CFG.VLANTAG_TYPE = 1 # Configure the port VID to 1. VLAN_CFG.VLAN_VID = 1 # Configure the egress side of the port to not insert tags. # (The service provider tags are stripped in the ingress side of the MAN port). TAG_CFG.TAG_CFG = 0 # Configuration of customer 2's port (port 9). # Same as for customer 1’s port (port 8), except that the port VID is set to 2. VLAN_CFG.VLAN_VID = 2 # Configuration of the network port (port 16). # MAN traffic in transit between network ports is supported by configuring all network # ports as follows: # Allow for two VLAN tags in the length check and set the max length without # VLAN tags to 1518 bytes. MAC_TAGS_CFG.VLAN_LEN_AWR_ENA = 1 MAC_TAGS_CFG.VLAN_AWAR_ENA = 1 MAC_TAGS_CFG.PB_ENA =1 MAC_MAXLEN_CFG.MAX_LEN = 1518 # Configure the port to use incoming VLAN tags in the VLAN classification, # and to remove the first (outer) VLAN tag (the service tag) from incoming frames. VLAN_CFG.VLAN_POP_CNT = 1 VLAN_CFG.VLAN_AWARE_ENA = 1 # Allow only S-tagged frames. DROP_CFG.DROP_UNTAGGED_ENA = 1 DROP_CFG.DROP_C_TAGGED = 1 DROP_CFG.DROP_PRIO_C_TAGGED = 1 DROP_CFG.DROP_S_TAGGED = 0 DROP_CFG.DROP_PRIO_S_TAGGED = 0 # The tag type is unused on the network port VLAN_CFG.VLANTAG_TYPE = 0 # Configure the egress side of the port to insert tags. TAG_CFG.TAG_CFG = 1 # Common configuration in the analyzer. VMDS-10392 VSC7420-02, VSC7421-02, and VSC7422-02 Datasheet Revision 4.3 140 Features # Configure VLAN 1 to contain customer 1’s port (port 8) and the network # (port 16). Disable learning in VLAN 1. Ingress filtering is don’t care port # based VLANs. VLANTIDX.INDEX = 1 VLANTIDX.VLAN_PRIV_VLAN = 0 (don’t care, for this example) VLANTIDX.VLAN_MIRROR = 0 (don’t care, for this example) VLANTIDX.VLAN_LEARN_DISABLE = 1 VLANTIDX.VLAN_SRC_CHK = 0 (don’t care, for this example) VLANACCESS.VLAN_PORT_MASK = 0x00010100 VLANACCESS.VLAN_TBL_CMD = 2 # Configure VLAN 2 to contain customer 2's port (port 9) and the network # (port 16). Disable learning in VLAN 2. Ingress filtering is don’t-care port # based VLANs. VLANTIDX.INDEX = 2 VLANTIDX.VLAN_PRIV_VLAN = 0 (don’t care, for this example) VLANTIDX.VLAN_MIRROR = 0 (don’t care, for this example) VLANTIDX.VLAN_LEARN_DISABLE = 1 VLANTIDX.VLAN_SRC_CHK = 0 (don’t care, for this example) VLANACCESS.VLAN_PORT_MASK = 0x00010200 VLANACCESS.VLAN_TBL_CMD = 2 6.4.4 port for port for Private VLANs The following table lists the analyzer configuration registers for private VLAN support. Table 127 • Private VLAN Configuration Registers Register Description Replication VLANACCESS VLAN table command. For indirect access to configuration of the 4096 VLANs. None VLANTIDX VLAN table index. For indirect access to configuration of the 4096 VLANs. None ISOLATED_PORTS VLAN port mask indicating isolated ports in private VLANs. None COMMUNITY_PORTS VLAN port mask indicating community ports in None private VLANs. When a VLAN is configured to be a private VLAN, communication between ports within that VLAN can be prevented. Two application examples are: • • Customers connected to an ISP can be members of the same VLAN, but they are not allowed to communicate with each other within that VLAN. Servers in a farm of web servers in a Demilitarized Zone (DMZ) are allowed to communicate with the outside world and with database servers on the inside segment, but are not allowed to communicate with each other For private VLANs to be applied, the switch must first be configured for standard VLAN operation. For more information, see Standard VLAN Operation, page 134. When this is in place, one or more of the configured VLANs can be configured as private VLANs. Ports in a private VLAN fall into one of three groups: • • Promiscuous ports Ports from which traffic can be forwarded to all ports in the private VLAN Ports that can receive traffic from all ports in the private VLAN Community Ports Ports from which traffic can only be forwarded to community and promiscuous ports in the private VMDS-10392 VSC7420-02, VSC7421-02, and VSC7422-02 Datasheet Revision 4.3 141 Features VLAN • Ports that can receive traffic from only community and promiscuous ports in the private VLAN Isolated ports Ports from which traffic can only be forwarded to promiscuous ports in the private VLAN Ports that can receive traffic from only promiscuous ports in the private VLAN The configuration of promiscuous, community, and isolated ports applies to all private VLANs. The forwarding of frames classified to a private VLAN happens: • • • 6.4.4.0.1 When traffic comes in on a promiscuous port in a private VLAN, the VLAN mask from the VLAN table is applied. When traffic comes in on a community port, the ISOLATED_PORT mask is applied in addition to the VLAN mask from the VLAN table. When traffic comes in on an isolated port, the ISOLATED_PORT mask and the COMMUNITY_PORT mask are applied in addition to the VLAN mask from the VLAN table. ISP Example Situation: Customers A, B, and C are connected to the same switch at the ISP. Customers A and B are allowed to communicate with each other, as well as the ISP. Customer C can only communicate with the ISP. VLAN 1 is the private VLAN that isolates Customers A, B from C. Traffic on VLAN 1 coming in from the ISP (port 8) uses the VLAN mask in the VLAN table. Traffic on VLAN 1 from customer A or B has the ISOLATED_PORTS mask applied in addition to the mask from the VLAN table, with the result that traffic from customer A and B is not forwarded to customers C. Traffic on VLAN 1 from customer C has the ISOLATED_PORTS mask and the COMMUNITY_PORTS mask applied in addition to the mask from the VLAN table, with the result that traffic from customer C is not forwarded to customers A and B. The following illustration shows the desired setup. VMDS-10392 VSC7420-02, VSC7421-02, and VSC7422-02 Datasheet Revision 4.3 142 Features Figure 46 • ISP Example for Private VLAN ISP VLAN 1 8 0 Promiscuous Port 2 1 Isolated Port Community Ports VLAN 1 RouterA PC_A VLAN Table VID Ports in Mask Private .. .. .. . . . 1 0, 1, 2, 8 1 .. .. .. . . . VLAN 1 VLAN 1 RouterB PC_B RouterC PC_C1 ISOLATED_PORTS (Isolated ports set to 0) Bit Value PC_C2 COMMUNITY_PORTS (Community ports set to 0) Bit 0 Value 0 1 1 1 1 0 2 .. . 8 .. . 0 .. . 1 .. . 2 .. . 8 .. . 1 .. . 1 .. . 0 Resolution: # It is assumed that Port VID and tag handling for VLAN 1 is already # configured according to the description in Standard VLAN Operation. # Configure VLAN 1 as a private VLAN in the VLAN table by performing these steps: # - Point to VLAN 1. # - Set it as private. # - Disable mirroring of the VLAN (not important for the example). # - Enable learning within the VLAN (not important for the example). # - Disable source check within the VLAN (not important for the example). # - Include ports 0, 1, 2, and 8 in the VLAN mask. # Insert the entry into the VLAN table. VLANTIDX.INDEX = 1 VLANTIDX.VLAN_PRIV_VLAN = 1 VLANTIDX.VLAN_MIRROR = 0 (don’t care, for this example) VLANTIDX.VLAN_LEARN_DISABLE = 0 (don’t care, for this example) VLANTIDX.VLAN_SRC_CHK = 0 (don't care, for this example) VLANACCESS.VLAN_PORT_MASK = 0x00000107 VLANACCESS.VLAN_TBL_CMD = 2 VMDS-10392 VSC7420-02, VSC7421-02, and VSC7422-02 Datasheet Revision 4.3 143 Features # Configure the private VLAN mask so that port 8 is a promiscuous # port, ports 0 and 1 are community ports, and port 2 is an isolated port. ISOLATED_PORTS.ISOL_PORTS = 0x00000103 COMMUNITY_PORTS.COMM_PORTS = 0x00000104 6.4.4.0.2 DMZ Example Situation: VLAN 17 is a private VLAN that isolates Server1 and Server2. Traffic on VLAN 17 coming from the internal or the external router (ports 8 and 9) uses the VLAN mask in the VLAN table. Traffic on VLAN 17 from Server1 and Server2 (ports 14 and 15) has the ISOLATED_PORTS applied in addition to the mask from the VLAN table, with the result that traffic from Server1 is not forwarded to Server2 and visa versa. The following illustration shows the desired setup. Figure 47 • DMZ Example for Private VLAN Promiscuous Ports VLAN 17 LAN Internal Router VLAN 17 9 15 8 14 VLAN 17 VLAN 17 WAN External Router Isolated Ports ServerDB Server1 ISOLATED_PORTS (Promiscuous Ports Set to 1) VLAN Table VID .. . 17 .. . Ports in Mask .. . 8, 9, 14, 15 .. . Server2 Private .. . 1 .. . Bit .. . Value .. . 8 1 9 .. . 14 1 .. . 0 15 .. . 0 .. . Resolution: # It is assumed that Port VID and tag handling for VLAN 17 is already # configured according to the description in Standard VLAN Operation. # Configure VLAN 17 as a private VLAN in the VLAN table by performing these steps: # - Point to VLAN 17. # - Set it as private. # - Disable mirroring of the VLAN (not important for the example). # - Enable learning within the VLAN (not important for the example). # - Disable source check within the VLAN (not important for the example). # - Include ports 8, 9, 14, and 15 in the VLAN mask. # - Insert the entry into the VLAN table. VLANTIDX.INDEX = 17 VLANTIDX.VLAN_PRIV_VLAN = 1 VMDS-10392 VSC7420-02, VSC7421-02, and VSC7422-02 Datasheet Revision 4.3 144 Features VLANTIDX.VLAN_MIRROR = 0 (don’t care, for this example) VLANTIDX.VLAN_LEARN_DISABLE = 0 (don’t care, for this example) VLANTIDX.VLAN_SRC_CHK = 0 (don’t care, for this example) VLANACCESS.VLAN_PORT_MASK = 0x0000C300 VLANACCESS.VLAN_TBL_CMD = 2 # Configure the private VLAN mask so that ports 8 and 9 are promiscuous # ports. ISOLATED_PORTS.ISOL_PORTS = 0x00000300 6.4.5 Asymmetric VLANs Asymmetric VLANs use the same configuration registers as for standard VLAN operation. For more information about standard VLAN operation, see Standard VLAN Operation, page 134. Asymmetric VLANs can be used to prevent communication between hosts in a network. This behavior is similar to what can be obtained by using private VLANs. For more information, seePrivate VLANs, page 141. Situation: A server and two hosts are connected to a switch. Communication between the hosts and the server should be allowed, but the hosts are not allowed to communicate directly. All traffic between the server and the hosts is untagged. Host 1 is connected to port 9, host 2 to port 10, and the server to port 8. The host-1 port gets port VID 1 and the host-2 port gets port VID 2. The server port is a member of both VLANs 1 and 2. The server port gets port VID 3, and the two host ports are members of VLAN 3, as shown in the following illustration. Figure 48 • Asymmetric VLANs Server 8 PVID=3 VLAN Table VID .. . 1 Ports in Mask .. . 8 2 8 3 .. . 9, 10 .. . PVID=1 9 Host 1 10 PVID=2 Host 2 Resolution: # Analyzer configurations common for ports 8, 9, and 10. # Allow only untagged frames. DROP_CFG.DROP_UNTAGGED_ENA = 0 DROP_CFG.DROP_C_TAGGED_ENA = 1 DROP_CFG.DROP_PRIO_C_TAGGED_ENA = 1 # As tagged frames are dropped all frames are classified to the port VID. VLAN_CFG.VLAN_AWARE_ENA = 0 (don’t care, for this example) # Configure the egress side of the port to not insert tags. TAG_CFG.TAG_CFG = 0 VMDS-10392 VSC7420-02, VSC7421-02, and VSC7422-02 Datasheet Revision 4.3 145 Features # Analyzer configuration specific for port 8. Set the port VID to 3. VLAN_CFG.VLAN_VID = 3 VLAN_CFG.VLAN_DEI = 0 (don’t care, for this example) # Analyzer configuration specific for port 9. Set the port VID to 1. VLAN_CFG.VLAN_VID = 1 VLAN_CFG.VLAN_DEI = 0 (don’t care, for this example) # Analyzer configuration specific for port 10. Set the port VID to 2. VLAN_CFG.VLAN_VID = 2 VLAN_CFG.VLAN_DEI = 0 (don’t care, for this example) # Analyzer configuration common to all ports. # Configure VLAN 1 to contain port 8. VLANTIDX.INDEX = 1 VLANTIDX.VLAN_PRIV_VLAN = 0 VLANTIDX.VLAN_MIRROR = 0 (don’t care, for this example) VLANTIDX.VLAN_LEARN_DISABLE = 0 VLANTIDX.VLAN_SRC_CHK = 0 VLANACCESS.VLAN_PORT_MASK = 0x00000100 VLANACCESS.VLAN_TBL_CMD = 2 # Configure VLAN 2 to contain port 8. VLANTIDX.INDEX = 2 VLANTIDX.VLAN_PRIV_VLAN = 0 VLANTIDX.VLAN_MIRROR = 0 (don’t care, for this example) VLANTIDX.VLAN_LEARN_DISABLE = 0 VLANTIDX.VLAN_SRC_CHK = 0 VLANACCESS.VLAN_PORT_MASK = 0x00000100 VLANACCESS.VLAN_TBL_CMD = 2 # Configure VLAN 3 to contain ports 9 and 10. VLANTIDX.INDEX = 3 VLANTIDX.VLAN_PRIV_VLAN = 0 VLANTIDX.VLAN_MIRROR = 0 (don’t care, for this example) VLANTIDX.VLAN_LEARN_DISABLE = 0 VLANTIDX.VLAN_SRC_CHK = 0 VLANACCESS.VLAN_PORT_MASK = 0x00000600 VLANACCESS.VLAN_TBL_CMD = 2 6.4.6 Spanning Tree Protocol This section provides information about Rapid Spanning Tree Protocol (RSTP) support. The devices also support legacy Spanning Tree Protocol (STP). STP was obsoleted by RSTP in IEEE 802.1D and is not described in this document. It is assumed that only LAN ports connected to the switch core participate in the spanning tree protocol. This implies that BPDUs are terminated by the switch core. 6.4.6.1 Rapid Spanning Tree Protocol The following table lists the analyzer configuration registers for Rapid Spanning Tree Protocol (RSTP) operation. Table 128 • Analyzer Configurations for RSTP Support Register/Register Field Description Replication PGID[80-106] Source masks used for ingress filtering Per port PGID[64-79] Aggregation masks that can be used for egress filtering for RSTP 16 PORT_CFG.LEARN_ENA Enable learning per port Per port VMDS-10392 VSC7420-02, VSC7421-02, and VSC7422-02 Datasheet Revision 4.3 146 Features Table 128 • Analyzer Configurations for RSTP Support (continued) Register/Register Field Description Replication CPU_FWD_BPDU_CFG Enable redirection of frames with reserved Per port per BPDU DMAC addresses address CPUQ_8021_CFG.CPUQ_B CPU extraction queue for redirected PDU_VAL BPDU frames Per address To eliminate potential loops in a network, the Rapid Spanning Tree Protocol in IEEE 802.1D creates a single path between any two bridges in a network, adding stability and predictability to the network. The protocol is implemented by assigning states to all ports. Each state controls a port’s functionality, limiting its ability to receive and transmit frames and learn addresses. Establishing a spanning tree is done through the exchange of BPDUs between bridge entities. BPDUs are frequently exchanged between neighboring bridges. These frames are identified by the Bridge protocol address range (DMAC = 01-80-C2-00-00-0x). When there is a change in the network topology, the protocol reconfigures the port states. Figure 49 • Spanning Tree Example Spanning Tree Path Spanning Tree Path Cable Ports in Discarding State The following table lists the Rapid Spanning Tree port state properties. Table 129 • RSTP Port State Properties State BPDU Reception BPDU Generation Frame Forwarding SMAC Learning Discarding Yes Yes No No Learning Yes Yes No Yes Forwarding Yes Yes Yes Yes The legacy STP states disabled, blocking, and listening correspond to the discarding state of RSTP. All frames with a Bridge protocol address must be redirected to the CPU. This is configured in CPU_FWD_BPDU_CFG. BPDUs are forwarded to the CPU irrespective of the port’s RSTP state. CPUQ_8021_CFG.CPUQ_BPDU_VAL can be used to configure in which CPU extraction queue the BPDUs are placed. BPDU generation is done through frame injection from the CPU. VMDS-10392 VSC7420-02, VSC7421-02, and VSC7422-02 Datasheet Revision 4.3 147 Features Frame forwarding is controlled through ingress filtering and egress filtering. Ingress filtering can be done by using the source masks (PGID[80-106]), and egress filtering can be done by using the aggregation masks (PGID[64-79]). Forwarding can be disabled for ports not in the Forwarding state by clearing their source masks and excluding them from all aggregation masks. The use of the aggregation masks for egress filtering does not preclude the combination of link aggregation and RSTP support. All ports in a link aggregation group that are not in the Forwarding state must be disabled in all aggregation masks. For link aggregated ports in the Forwarding state, the aggregation masks must be configured for link aggregation (such as when RSTP is not supported.) Learning can be enabled per port with the PORT_CFG.LEARN_ENA. The following table provides an overview of the port state configurations for port p. Table 130 • RSTP Port State Configuration for Port p State CPU_FWD_BPDU _CFG[p].BPDU_R EDIR_ENA[0] PGID[80+p] PGID[64-79], All 16 Masks, Bit p PORT_CFG[p].LE ARN_ENA Discarding 1 0 0 0 Learning 1 0 0 1 Forwarding 1 1 except for bit p 1 1 6.4.6.1.1 RSTP Example Situation: Port 0 is in the RSTP Discarding state. Port 2 is in the RSTP Learning state. Port 3 is in the RSTP Forwarding state. All other ports on the switch are unused. Resolution: # Get Spanning Tree Protocol BDPUs to CPU extraction queue 0 for port 0, 2, and 3. CPU_FWD_BPDU_CFG[0].BPDU_REDIR_ENA[0] = 1 CPU_FWD_BPDU_CFG[2].BPDU_REDIR_ENA[0] = 1 CPU_FWD_BPDU_CFG[3].BPDU_REDIR_ENA[0] = 1 CPUQ_8021_CFG.CPUQ_BPDU_VAL[0] = 0 # Configure the source mask for port 0 (Discarding state). PGID[80] = 0x00 # Configure the source mask for port 2 (Learning state). PGID[82] = 0x00 # Configure the source mask for port 3 (Forwarding state). PGID[83] = 0x77 # Configure the aggregation masks to only allow forwarding to port 3 # (Forwarding state). PGID[64-79] = 0x08 # Configure the learn mask to only allow learning on ports # 2 (Learning state) and 3 (Forwarding state). PORT_CFG[0].LEARN_ENA = 0 PORT_CFG[2].LEARN_ENA = 1 PORT_CFG[3].LEARN_ENA = 1 VMDS-10392 VSC7420-02, VSC7421-02, and VSC7422-02 Datasheet Revision 4.3 148 Features 6.4.6.2 Multiple Spanning Tree Protocol The following table lists the analyzer configuration registers for Multiple Spanning Tree Protocol (MSTP) operation. Table 131 • Analyzer Configurations for MSTP Support Register/Register Field Description Replication VLANACCESS.VLAN_SRC_CHK None Per-VLAN ingress filtering enable. Part of VLAN table command for indirect access to configuration of the 4095 VLANs VLANMASK Per-port VLAN ingress filtering enable None ADVLEARN.VLAN_CHK Disable learning for frames discarded None due to VLAN membership source port filtering PORT_CFG.LEARN_ENA Enable learning per port Per port CPU_FWD_BPDU_CFG Enable redirection of frames with reserved BPDU DMAC addresses Per port per address CPUQ_8021_CFG.CPUQ_BPDU_VAL CPU extraction queue for redirected BPDU frames Per address The Multiple Spanning Tree Protocol (MSTP) in IEEE 802.1Q increases network use, relative to RSTP, by creating multiple spanning trees that VLANs can map to independently, rather than having only one path between bridges common for all VLANs. The multiple spanning trees are created by assigning different bridge identifiers for each spanning tree. Mapping the VLANs to spanning trees is done arbitrarily. Figure 50 • Multiple Spanning Tree Example MSTP 1 MSTP 1 MSTP 2 Cable MSTP 2 Ports in Discarding State for MSTP 1 Ports in Discarding State for MSTP 2 VMDS-10392 VSC7420-02, VSC7421-02, and VSC7422-02 Datasheet Revision 4.3 149 Features The Learning state is not supported for MSTP. However, this has limited impact, because when the port is taken to the Forwarding state, learning is done at wire-speed, and, as a result, the SMAC learn delay is less important. MSTP is supported for all VLANs. The following table lists the multiple spanning tree port state properties. Table 132 • MSTP Port State Properties State per VLAN BPDU Reception BPDU Generation Frame Forwarding SMAC Learning Discarding Yes Yes No No Learning (not supported) Yes Yes No Yes Forwarding Yes Yes Yes Yes To enable the MSTP port states: • • • Ensure that the switch is VLAN-aware. For more information, see Standard VLAN Operation, page 134. Set the ADVLEARN.VLAN_CHK bit to prevent learning of frames discarded due to VLAN ingress filtering. Configure all ports as defined for the forwarding state of the RSTP port. For more information, see Table 130, page 148. Port states per VLAN are hereafter solely configured through the VLAN masks as listed in the following table for port p and VLAN v. Table 133 • MSTP Port State Configuration for Port p and VLAN v State VLAN_ACCESS. VLAN_SRC_CHKVLAN v VLAN_ACCESS. VLAN_PORT_MASK Bit p, VLAN v Discarding 1 0 Learning Not supported Not supported Forwarding 1 1 As an alternative to setting the VLANACCESS.VLAN_SRC_CHK bit in all VLAN entries in the VLAN table, VLAN ingress filtering can be enabled globally for all VLANs on a per port basis through VLANMASK. For all multiple spanning tree instances, BPDUs are forwarded to the CPU irrespective of the port states. 6.4.6.2.1 MSTP Example Situation: Ports 10 and 11 are both members of VLANs 20 and 21. Two spanning trees are used: • • Spanning tree for VLAN 20, where both ports 10 and 11 are in the Forwarding state Spanning tree for VLAN 21, where port 10 is in the Discarding state and port 11 is in the Forwarding state All other ports on the switch are unused. Resolution: # Get all BDPUs to CPU queue 0. CPU_FWD_BPDU_CFG[*].BPDU_REDIR_ENA[0] = 1 CPUQ_8021_CFG.CPUQ_BPDU_VAL[0] = 0 # Enable learning on all ports. The VLAN table controls forwarding and learning. PORT::PORT_CFG.LEARN_ENA = 1 # Disable learning of VLAN membership source port filtered frames. ADVLEARN.VLAN_CHK = 1 VMDS-10392 VSC7420-02, VSC7421-02, and VSC7422-02 Datasheet Revision 4.3 150 Features # Configure VLAN 20 for ports 10 and 11 in Forwarding state. VLANTIDX.INDEX = 20 VLANTIDX.VLAN_PRIV_VLAN = 0 VLANTIDX.VLAN_MIRROR = 0 (don’t care, for this example) VLANTIDX.VLAN_LEARN_DISABLE = 0 VLANTIDX.VLAN_SRC_CHK = 1 VLANACCESS.VLAN_PORT_MASK = 0x00000C00 VLANACCESS.VLAN_TBL_CMD = 2 # Configure VLAN 21 for port 10 in Discarding state and port 11 in Forwarding state. VLANTIDX.INDEX = 21 VLANTIDX.VLAN_PRIV_VLAN = 0 VLANTIDX.VLAN_MIRROR = 0 (don’t care, for this example) VLANTIDX.VLAN_LEARN_DISABLE = 0 VLANTIDX.VLAN_SRC_CHK = 1 VLANACCESS.VLAN_PORT_MASK = 0x00000800 VLANACCESS.VLAN_TBL_CMD = 2 6.4.7 IEEE 802.1X: Network Access Control IEEE 802.1X Port-Based Network Access Control provides a standard for authenticating and authorizing devices attached to a LAN port. Generally, IEEE 802.1X is port-based; however, the devices also support MAC-based network access control. This section provides information about the configuration settings for port-based and MAC-based network access control. 6.4.7.1 Port-Based Network Access Control The following table lists the configuration settings that are required for port-based network access control. Table 134 • Configurations for Port-Based Network Access Control Register/Register Field Description/Value Replication ANA::CPU_FWD_BPDU_CF Must be set to 1 to redirect frames with G.BPDU_REDIR_ENA[3] destination MAC addresses 01-80-C2-00-00-03 to the CPU Port Module. IEEE 802.1X uses MAC address 01-80-C2-00-00-03. Per port ANA::CPUQ_8021_CFG.CP Queue to which authentication BPDUs UQ_BPDU_VAL[3] are redirected. None ANA::PGID[64-79] When a port is not yet authenticated, any 16 forwarding of frames to the port can be disabled by clearing the port’s bit in all 16 aggregation masks. After authenticated, these bits must be set. VMDS-10392 VSC7420-02, VSC7421-02, and VSC7422-02 Datasheet Revision 4.3 151 Features Table 134 • Configurations for Port-Based Network Access Control (continued) Register/Register Field Description/Value Replication ANA::PGID[80-106] Per port Source masks. When a port is not yet authenticated, any forwarding of frames received on the port must be disabled. This can be done by setting the ANA::PGID[80+port] to allzeros. After authenticated, the port’s source mask must be set back to its normal value. The configuration settings required for port-based network access control enable the following functionality: • • • 6.4.7.2 Redirects frames with DMAC 01-80-C2-00-00-03 to CPU, even if the port is not yet authenticated. Stops forwarding of frames to ports that are not yet authenticated. This is configured in ANA::PGID[64-79]. Stops forwarding of frames received on ports that are not yet authenticated. This is configured in ANA::PGID[80-106]. MAC-Based Authentication with Secure CPU-Based Learning The following table lists the configuration settings required for MAC-based network access control with secure CPU-based learning. Table 135 • Configurations for MAC-Based Network Access Control with Secure CPU-Based Learning Register/Register Field Description/Value ANA:PORT:CPU_FWD_BPDU_CF G.BPDU_REDIR_ENA[3] Must be set to 1 to redirect frames Per port with destination MAC addresses 0180-C2-00-00-03 to the CPU Port Module. IEEE 802.1X uses MAC address 0180-C2-00-00-03. ANA::CPUQ_8021_CFG.CPUQ_BP Queue to which authentication DU_VAL[3] BPDUs are redirected. ANA:PORT:PORT_CFG.LEARN_E NA ANA:PORT:PORT_CFG.LEARNCP U ANA:PORT:PORT_CFG.LEARNDR OP ANA:PORT:PORT_CFG.LEARNAU TO Must be set to support secure CPU-based learning. See Address Learning, page 132. PORT_CFG.LEARN_ENA = 1 PORT_CFG.LEARNCPU = 1 PORT_CFG.LEARNDROP = 1 PORT_CFG.LEARNAUTO = 0 Replication None Per port The MAC-based network access control with secure CPU-based learning enables the following functionality: • • • Redirects frames with DMAC 01-80-C2-00-00-03 to CPU. Only frames from known, authenticated MAC addresses are forwarded to other ports. Frames from unknown MAC addresses are redirected to CPU for authentication. After the address is authenticated, the CPU must insert an entry in the MAC table. The authentication process may be initiated from the CPU when receiving learn frames. VMDS-10392 VSC7420-02, VSC7421-02, and VSC7422-02 Datasheet Revision 4.3 152 Features 6.4.7.3 MAC-Based Authentication with No Learning The following table lists the configuration settings required for MAC-based network access control with no learning. Table 136 • Configurations for MAC-Based Network Access Control with No Learning Register/Register Field Description/Value Replication ANA:PORT:CPU_FWD_BPDU_CFG Must be set to 1 to redirect frames Per port .BPDU_REDIR_ENA[3] with destination MAC addresses 01-80-C2-00-00-03 to the CPU Port Module. IEEE 802.1X uses MAC address 01-80-C2-00-00-03. ANA::CPUQ_8021_CFG.CPUQ_BP Queue to which authentication DU_VAL[3] BPDUs are redirected. ANA:PORT:PORT_CFG.LEARN_EN A ANA:PORT:PORT_CFG.LEARNCP U ANA:PORT:PORT_CFG.LEARNDR OP ANA:PORT:PORT_CFG.LEARNAUT O None Must be set to support no learning. None See Address Learning, page 132. PORT_CFG.LEARN_ENA = 1 PORT_CFG.LEARNCPU = 1 PORT_CFG.LEARNDROP = 1 PORT_CFG.LEARNAUTO = 0 The MAC-based network access control with no learning enables the following functionality: • • • 6.4.8 Frames with DMAC 01-80-C2-00-00-03 are redirected to CPU. Unauthenticated and unauthorized devices must initiate an 802.1X session by sending 802.1X BPDUs (MAC address: 01-80-C2-00-0003). After the address is authenticated, the CPU must insert an entry in the MAC table. Only frames from known, authenticated MAC addresses are forwarded to other ports. Frames from unknown MAC addresses are discarded and the CPU can therefore not initiate the authentication process. Link Aggregation Link aggregation bundles multiple ports (member ports) together into a single logical link. It is primarily used to increase available bandwidth without introducing loops in the network and to improve resilience against faults. A link aggregation group (LAG) can be established with individual links being dynamically added or removed. This enables bandwidth to be incrementally scaled based on changing requirements. A link aggregation group can be quickly reconfigured if faults are identified. Frames destined for a LAG are sent on only one of the LAG’s member ports. The member port on which a frame is forwarded is determined by a 4-bit aggregation code (AC) that is calculated for the frame. The aggregation code ensures that frames belonging to the same frame flow (for example, a TCP connection) are always forwarded on the same LAG member port. For that reason, reordering of frames within a flow is not possible. The aggregation code is based on the following information: • • • • • • SMAC DMAC Source and destination IPv4 address. Source and destination TCP/UDP ports for IPv4 packets Source and destination TCP/UDP ports for IPv6 packets IPv6 Flow Label For best traffic distribution among the LAG member ports, enable all six contributions to the aggregation code. VMDS-10392 VSC7420-02, VSC7421-02, and VSC7422-02 Datasheet Revision 4.3 153 Features Each LAG can consist of up to 16 member ports. Any quantity of LAGs may be configured for the device (only limited by the quantity of ports on the device.) To configure a proper traffic distribution, the ports within a LAG must use the same link speed. A port cannot be a member of multiple LAGs. 6.4.8.1 Link Aggregation Configuration The following table lists the registers associated with link aggregation groups. Table 137 • Link Aggregation Group Configuration Registers Register/Register Field Description/Value Replication ANA::PGID[0 – 63] Destination mask 64 ANA::PGID[80 – 106] Source mask. Per port ANA::PGID[64 – 79] Aggregation mask. 16 ANA::PORT_CFG.PORTID_VA Logical port number. Must be set to Per port L the same value for all ports that are part of a given LAG; for example, the lowest port number that is a member of the LAG. ANA::AGGR_CFG. AC_IP6_FLOW_LBL_ENA Use IPv6 flow label when calculating None AC. Configure identically for all ports. Recommended value is 1. ANA::AGGR_CFG. AC_SIPDIP_ENA Use IPv4 source and destination IP None address when calculating aggregation code. Configure identically for all ports. Recommended value is 1. ANA::AGGR_CFG. AC_TCPUDP_PORT_ENA Use IPv4 TCP/UDP port when calculating aggregation code. Configure identically for all ports. Recommended value is 1. ANA:: AGGR_CFG. AC_DMAC_ENA Use destination MAC address when None calculating aggregation code. Configure identically for all ports. Recommended value is 1. ANA:: AGGR_CFG. AC_SMAC_ENA Use source MAC address when calculating aggregation code. Configure identically for all ports. Recommended value is 1. None ANA:: AGGR_CFG. AC_RND_ENA Use random aggregation code. Recommended value is 0. None None To set up a link aggregation group, the following destination masks, source masks, and aggregation masks must be configured: • • Destination Masks: ANA::PGID[0-63] — For each of the member ports, the corresponding destination mask must be configured to include all member ports of the LAG. Source Masks: ANA::PGID[80-106] — The source masks must be configured to avoid flooding frames that are received at one member port back to another member port of the LAG. As a result, the source masks for each of the member ports must be configured to exclude all of the LAG’s member ports. VMDS-10392 VSC7420-02, VSC7421-02, and VSC7422-02 Datasheet Revision 4.3 154 Features • Aggregation Masks: ANA::PGID[64-79] — The aggregation masks must be configured to ensure that when a frame is destined for the LAG, it gets forwarded to exactly one of the LAG’s member ports. Also, the distribution of traffic between member ports is determined by this configuration. The following illustration shows an example of a LAG configuration. Figure 51 • Link Aggregation Example Configuration, Switch A Aggregation Masks AC Port mask 0x0: 0b11..111001101 0x1: 0b11..111001110 0x2: 0b11..111011100 0x3: 0b11..111101100 0x4: 0b11..111001101 0x5: 0b11..111001110 0x6: 0b11..111011100 0x7: 0b11..111101100 0x8: 0b11..111001101 0x9: 0b11..111001110 0xA: 0b11..111011100 0xB: 0b11..111101100 0xC: 0b11..111001101 0xD: 0b11..111001110 0xE: 0b11..111011100 0xF: 0b11..111101100 Destination Masks DEST INDX Port mask 0: 0b00..000110011 1: 0b00..000110011 4: 0b00..000110011 5: 0b00..000110011 Port 0: 1: 4: 5: Source Masks Port mask 0b11..111001100 0b11..111001100 0b11..111001100 0b11..111001100 PORT_CFG[0].PORTID_VAL = 0 PORT_CFG[1].PORTID_VAL = 0 PORT_CFG[4].PORTID_VAL = 0 PORT_CFG[5].PORTID_VAL = 0 Switch A 0 1 4 5 LAG Configuration, Switch B Aggregation Masks AC Port mask 0x0: 0b11..100011111 0x1: 0b11..100101111 0x2: 0b11..101001111 0x3: 0b11..110001111 0x4: 0b11..100011111 0x5: 0b11..100101111 0x6: 0b11..101001111 0x7: 0b11..110001111 0x8: 0b11..100011111 0x9: 0b11..100101111 0xA: 0b11..101001111 0xB: 0b11..110001111 0xC: 0b11..100011111 0xD: 0b11..100101111 0xE: 0b11..101001111 0xF: 0b11..110001111 Destination Masks DEST INDX Port mask 4: 0b00..011110000 5: 0b00..011110000 6: 0b00..011110000 7: 0b00..011110000 Port 4: 5: 6: 7: 4 5 6 7 Switch B Source Masks Port mask 0b11..100001111 0b11..100001111 0b11..100001111 0b11..100001111 PORT_CFG[4].PORTID_VAL = 4 PORT_CFG[5].PORTID_VAL = 4 PORT_CFG[6].PORTID_VAL = 4 PORT_CFG[7].PORTID_VAL = 4 In this example, ports 0, 1, 4, and 5 of switch A are configured as a LAG. These ports are connected to 4 ports (4, 5, 6, 7) of switch B, providing an aggregated bandwidth of 4 Gbps between the two switches. The aggregation masks for switch A are configured such that frames (destined for the LAG) are distributed on the member ports as follows: • • • • 6.4.8.2 Port 0 if frame’s aggregation code (AC) is 0x0, 0x4, 0x8, 0xC Port 1 if frame’s aggregation code (AC) is 0x1, 0x5, 0x9, 0xD Port 4 if frame’s aggregation code (AC) is 0x2, 0x6, 0xA, 0xE Port 5 if frame’s aggregation code (AC) is 0x3, 0x7, 0xB, 0xF Link Aggregation Control Protocol (LACP) LACP allows switches connected to each other to automatically discover if any ports are member of the same LAG. VMDS-10392 VSC7420-02, VSC7421-02, and VSC7422-02 Datasheet Revision 4.3 155 Features To implement LACP, any LACP frames must be redirected to the CPU. Such frames are identified by the DMAC being equal to 01-80-C2-00-00-02 (Slow Protocols Multicast address). The following table lists the registers associated with configuring the redirection of LACP frames to the CPU. Table 138 • Configuration Registers for LACP Frame Redirection to the CPU Register/Register Field Description/Value ANA::CPU_FWD_BPDU_CFG. Must be set to 1. BPDU_REDIR_ENA[2] 6.4.9 Replication Per port Simple Network Management Protocol (SNMP) This section provides information about the port module registers and the analyzer registers for SNMP operation. The following table lists the system registers for SNMP operation. Table 139 • System Registers for SNMP Support Register Description Replication CNT The value of the counter. For more information about how to read counters, see Statistics, page 33. None The following table lists the analyzer registers for SNMP support. Table 140 • Analyzer Registers for SNMP Support Register Description Replication MACACCESS Command register for indirect MAC table access. Supports GET_NEXT command None MACHDATA High part of data word when accessing MAC table. None MACLDATA Low part of data word when accessing MAC table. None MACTINDX Index for direct-mode access to MAC table. None For SNMP support according to IETF RFC 1157, use the following features: • • RMON counters MAC table GET_NEXT function For more information about the supported RMON counters, see Port Counters, page 128. For more information about the MAC table GET_NEXT function, see Table 29, page 50. 6.4.10 Mirroring To debug network problems, selected traffic can be copied, or mirrored, to a mirror port where a frame analyzer can be attached to analyze the frame flow. The traffic to be copied to the mirror port can be selected as follows: • • • • • All frames received on a given port (also known as ingress mirroring) All frames transmitted on a given port (also known as egress mirroring All frames classified to specific VIDs All frames sent to the CPU (may be useful for software debugging) Frames where the source MAC address is to be learned (also known as learn frame), which may be useful for software debugging The mirror port may be any port on the device, including the CPU. VMDS-10392 VSC7420-02, VSC7421-02, and VSC7422-02 Datasheet Revision 4.3 156 Features 6.4.10.1 Mirroring Configuration The following table lists configuration registers associated with mirroring. Table 141 • Configuration Registers for Mirroring Register/Register Field Description/Value Replication ANA::PORT_CFG.SRC_MIRROR_E If set, all frames received on this Per port NA port are mirrored to the port set configured in MIRRORPORTS, that is, ingress mirroring. ANA:: EMIRRORPORTS Frames forwarded to ports in Per port this mask are mirrored to the port set configured in MIRRORPORTS, that is, egress mirroring. ANA::VLANTIDX.VLAN_MIRROR If set, all frames classified to this VLAN are mirrored to the port set configured in MIRRORPORTS. ANA::AGENCTRL.MIRROR_CPU None Frames destined for the CPU extraction queues are also forwarded to the port set configured in MIRRORPORTS. ANA::MIRRORPORTS None The mirror ports. Usually only one mirror port is configured, that is, only one bit is set in this mask. ANA::CPUQ_CFG.CPUQ_MIRROR CPU extraction queue used, if CPU is included in MIRRORPORTS. ANA::ADVLEARN.LEARN_MIRROR Learn frames are also forwarded to ports marked in MIRRORPORTS. One per VID None None The following illustration shows a port mirroring example. Figure 52 • Port Mirroring Example Mirror Port Switch 2 Network Analyzer 3 Probe Port Server All traffic to and from the server on port 3 (the probe port) is mirrored to port 2 (the mirror port). Note that the mirror port may become congested, because both the Rx frames and Tx frames on the probe port become Tx frames on the mirror port. The following mirror configuration is required: ANA::PORT_CFG[3].SRC_MIRROR_ENA = 1 ANA::EMIRRORPORTS[3] = 1 ANA::MIRRORPORTS = 0x0000004 In addition to the mirror configuration settings, the egress configuration of the mirror port (port 2) must be configured identically to the egress configuration of the probe port (port 3). This is to ensure that VLAN VMDS-10392 VSC7420-02, VSC7421-02, and VSC7422-02 Datasheet Revision 4.3 157 Features tagging and DSCP remarking at the mirror port is performed consistently with that of the probe port, such that the frame copies at the mirror port are identical to the original frames on the probe port. Multiple mirror conditions, such as mirror multiple probe ports, VLANs, and so on, can be enabled concurrently to the same mirror port. However, in such configurations, it may not be possible to configure the egress part of the mirror port to perform tagging and DSCP remarking consistent with that of the original frame. 6.5 IGMP and MLD Snooping This section provides information about the features and configurations related to Internet Group Management Protocol (IGMP) and Multicast Listener Discovery (MLD) snooping. By default, Layer-3 multicast data traffic is flooded in a Layer-2 network in the broadcast domain spanned by the VLAN. This causes unnecessary traffic in the network and extra processing of unsolicited frames in hosts not listening to the multicast traffic. IGMP and MLD snooping enables a Layer-2 switch to listen to IGMP and MLD conversations between host and routers. The switch can then prune multicast traffic from ports that do not have a multicast listener, and as a result, do not need a copy of the multicast frame. This is done by managing the multicast group addresses and the associated port masks. IGMP is used to manage IPv4 multicast memberships, and MLD is used to manage IPv6 multicast memberships. The devices support IGMPv2 and MLDv1. IGPMv2 and MLDv1 use any-source multicasting (ASM), where the multicast listener joins a group and can receive the multicast traffic from any source. The support in the devices is two-fold: • • 6.5.1 Control plane: IGMP and MLD frames are redirected to the CPU. This enables the CPU to listen to the queries and reports. Data plane: By monitoring the multicast group registrations and de-registrations signaled through the IGMP and MLD frames, the CPU can setup multicast group addresses and associated ports. IGMP and MLD Snooping Configuration To implement IGMP and MLD snooping, any IGMP or MLD frames must be redirected to the CPU. For information about by the conditions by which such frames are identified, see CPU Forwarding Determination, page 46. IGMP and MLD frames can be independently snooped and assigned individual CPU extraction queues. The following table lists the registers associated with configuring the redirection of IGMP and MLD frames to the CPU. Table 142 • Configuration Registers for IGMP and MLD Frame Redirection to CPU Register/Register Field Description/Value Replication ANA::CPU_FWD_CFG.IGMP_REDIR Must be set to 1 to redirect IGMP Per port _ENA frames to the CPU ANA::CPU_FWD_CFG.MLD_REDIR Must be set to 1 to redirect MLD Per port _ENA frames to the CPU ANA::CPUQ_CFG.CPUQ_IGMP CPU extraction queue for IGMP frames None ANA::CPUQ_CFG.CPUQ_MLD CPU extraction queue for MLD frames None VMDS-10392 VSC7420-02, VSC7421-02, and VSC7422-02 Datasheet Revision 4.3 158 Features 6.5.2 IP Multicast Forwarding Configuration The following table lists the registers associated with configuring the multicast group addresses and the associated ports. Table 143 • IP Multicast Configuration Registers Register/Register Field Description/Value Replication MACHDATA MAC address and VID when accessing None the MAC table. MACLDATA MAC address when accessing the MAC None table. MACTINDX Direct address into the MAC table for direct read and write. None MACACCESS Flags and command when accessing the MAC table. None MACTOPTIONS Flags when accessing the MAC table None FLOODING_IPMC None Index into the PGID table used for flooding of IPv4/6 multicast control and data frames. PGID[63:0] Destination and flooding masks table 64 IPv4 and IPv6 multicast group addresses are programmed in the MAC table as IPv4 and IPv6 multicast entries. For more information, see MAC Table, page 48. The entry in the MAC table also holds the set of egress ports associated with the group address. By default, programming an IPv4 or IPv6 multicast entry in the MAC table makes it an any-source multicast, because the actual source IP address is insignificant with respect to forwarding. The switch provides full control of flooding of unknown IP multicast frames. For more information, see Table 39, page 57. Generally, an IGMP and MLD snooping switch disables flooding of unknown multicast frames, except to ports connecting to multicast routers. Note that unknown IPv4 multicast control frames should be flooded to all ports, because IPv4 is not as strict as IPv6 in terms of registration for IP multicast groups. 6.6 Quality of Service (QoS) This section discusses features and configurations related to QoS. The devices include a number of features related to providing low-latency guaranteed services to critical network traffic such as voice and video in contrast to best-effort traffic such as web traffic and file transfers. All incoming frames are classified to a QoS class, which is used in the queue system when assigning resources, in the arbitration from ingress to egress queues and in the egress scheduler when selecting the next frame for transmission. The QoS classification enables predefined schemes for handling Priority Code Points (PCP), Drop Eligible Indicator (DEI), and Differentiated Service Code Points (DSCP): • • • • • QoS classification based on PCP and DEI for tagged frames. The mapping table from PCP and DEI to QoS class is programmable per port. QoS classification based on DSCP values. Can optionally use only trusted DSCP values. The mapping table from DSCP value to QoS class is common between all ports. The devices have the option to work as a DS boundary node connecting two DS domains together by translating incoming/outgoing DSCP values for selected ports. The DSCP values can optionally be remarked based on the frame’s classified QoS class. For untagged or non-IP frames, a default per-port QoS class is programmable. VMDS-10392 VSC7420-02, VSC7421-02, and VSC7422-02 Datasheet Revision 4.3 159 Features 6.6.1 Basic QoS Configuration The following table lists the registers associated with configuring basic QoS. Table 144 • Basic QoS Configuration Registers Register Description Replication ANA:PORT:QOS_CFG QoS and DSCP configuration Per port ANA:PORT:QOS_PCP_DE Mapping of DEI and PCP to QoS class and Per port I_MAP_CFG: drop precedence level ANA::DSCP_CFG DSCP configuration Per DSCP Situation: Assume a configuration with the following requirements: • • • • • • All frames with DSCP=7 must get QoS class 7. All frames with DSCP=8 must get QoS class 5. DSCP=9 is untrusted and all frames with DSCP=9 should be treated as a non-IP frame. VLAN-tagged frames with PCP=7 must get QoS class 7 All other IP frames must get QoS class 1. All other non-IP frames must get QoS class 0. Solution: # Program overall QoS configuration QOS_CFG.QOS_DSCP_ENA = 1 QOS_CFG.QOS_PCP_ENA = 1 # Program DSCP trust configuration (“*” = 0 through 63) DSCP_CFG[*].DSCP_TRUST_ENA = 1 DSCP_CFG[9].DSCP_TRUST_ENA = 0 # Program DSCP QoS configuration (“*” = 0 through 63) DSCP_CFG[*].QOS_DSCP_VAL = 1 DSCP_CFG[7].QOS_DSCP_VAL = 7 DSCP_CFG[8].QOS_DSCP_VAL = 5 # Program PCP QoS configuration (“*” = 0 through 15) # Note: both 7 and 15 are programmed in order to don’t care DEI QOS_PCP_DEI_MAP_CFG[*] = 0 QOS_PCP_DEI_MAP_CFG[7] = 7 QOS_PCP_DEI_MAP_CFG[15] = 7 # Program default QoS class for non-IP, non-tagged frames. QOS_CFG.QOS_DEFAULT_VAL = 0 6.6.2 IPv4 and IPv6 DSCP Remarking IPv4 and IPv6 packets include a 6-bit Differentiated Services Code Point (DSCP), which switches and routers can use to determine the QoS class of a frame. With a proper value in the DSCP field, packets can be prioritized consistently throughout the network. Compared to QoS classification based on user priority, classification based on DSCP provides two main advantages • • DSCP field is already present in all packets (assuming all traffic is IPv4/IPv6). DSCP value is preserved during routing and is therefore better suited for end-to-end QoS signaling. Some hosts may be able to send packets with an appropriate value in the DSCP field, whereas other hosts may not provide an appropriate value in the DSCP field. VMDS-10392 VSC7420-02, VSC7421-02, and VSC7422-02 Datasheet Revision 4.3 160 Features For packets without an appropriate value in the DSCP field, the devices can be configured to write a new DSCP value into the frame, based on the QoS class of the frame. For example, the devices may have determined the QoS class based on the VLAN tag priority information (PCP and DEI). After the packet is transmitted by the egress port, the DSCP field can be rewritten with a value based on the QoS class of the frame. Any subsequent routers or switches can then be easily prioritize the frame, based on the rewritten DSCP value. The DSCP rewriting functionality available in the devices provide flexible, per-ingress port and perDSCP-value configuration of whether frames should be subject to DSCP rewrite. If it is determined at the ingress port that the DSCP value should be rewritten and to which value, this is then signaled to the egress ports, where the actual change of the DSCP field is done. 6.6.2.1 DSCP Remarking Configuration The following table lists the configuration registers associated with DSCP remarking. Table 145 • Configuration Registers for DSCP Remarking Register/Register Field Description/Value Replication ANA:PORT:DSCP_REWR_CFG Two-bit DSCP rewrite mode per ingress port: 0x0: No DSCP rewrite. 0x1: Rewrite only if the frame’s current DSCP value is zero. 0x2: Rewrite only if the frame’s current DSCP value is enabled for remarking in ANA::DSCP_CFG.DSCP_REWR_ENA. 0x3: Rewrite DSCP of all frames, regardless of current DSCP value. Per ingress port ANA::DSCP_CFG.DSCP_REWR_ Enables specific DSCP values for rewrite for ports with ENA DSCP rewrite mode set to 0x2. Per DSCP ANA::DSCP_REWR_CFG.DSCP_ Maps the frame’s QoS class to a DSCP value. QOS_REWR_VAL Per QoS class REW::DSCP_CFG.DSCP_REWR Enables DSCP rewrite for egress port. _CFG Per egress port REW::DSCP_REMAP_CFG None Remap table of DSCP values. The configuration related to the ingress port controls whether a frame is to be remarked. For each ingress port, a DSCP rewrite mode is configured in ANA:PORT:DSCP_REWR_CFG. This register defines the four different modes as follows: • • • • 0x0: No DSCP rewrite, that is, never change the received DSCP value. 0x1: Rewrite if DSCP is zero. This may be useful if a DSCP value of zero indicates that the host has not written any value to the DSCP field. 0x2: Rewrite selected DSCP values. In ANA::DSCP_CFG.DSCP_REWR_ENA specific DSCP values can be selected for rewrite, for example, if only certain DSCP values are allowed in the network. 0x3: Rewrite all DSCP values. After a frame is selected for DSCP rewrite, based on the configuration for the ingress port, the new DSCP value is determined by mapping the QoS class to a new DSCP value (ANA::DSCP_REWR_CFG.DSCP_QOS_REWR_VAL). The resulting DSCP value is forwarded to the Rewriter at the egress port, which determines whether to actually write the new DSCP value into the frame (REW::DSCP_CFG.DSCP_REWR_CFG). Optionally, the DSCP value may be translated before written into the frame (REW::DSCP_REMAP_CFG) for applications where the switch acts as an DS boundary node. When an IPv4 DSCP is rewritten, the IP header checksum is updated accordingly. VMDS-10392 VSC7420-02, VSC7421-02, and VSC7422-02 Datasheet Revision 4.3 161 Features 6.7 CPU Extraction and Injection This section provides information about how the CPU extracts and injects frames to and from the switch core. The following illustration shows the CPU Port Module used for injection and extraction. Figure 53 • CPU Extraction and Injection CPU Port Module Extraction Strict / RR Q6 Q5 Switch Core Q0 Strict / RR Queue to Port Map Q7 Extraction Group 0 Extraction Group 1 Selector Scheduler Injection Strict / RR Queue Injection Group 0 Injection Group 1 Scheduler The switch core forwards CPU extracted frames to eight CPU extraction queues. Each of these queue is then mapped to one of two CPU Extraction Groups. For each extraction group there is a scheduler (strict or round robin) which selects between the CPU extraction queues mapped to the same group. When injecting frames, there are two CPU Injection Groups available where for instance one can be used for the Frame DMA and one can be used for manually injected frames. A scheduler (Strict or round robin) selects between the two injection groups meaning the switch core only sees one stream of frames being injected. 6.7.1 Forwarding to CPU Several mechanisms can be used to trigger redirection or copying of frames to the CPU. They are listed in the following table. Table 146 • Configurations for Redirecting or Copying Frames to the CPU Frame Type Configuration (Including Selection of Extraction Redirect Queue) or Copy IEEE 802.1D Reserved Range DMAC = 01-80-C2-00-00-0x ANA:PORT:CPU_FWD_BPDU_CFG ANA::CPUQ_8021_CFG.CPUQ_BPDU_VAL IEEE 802.1D Allbridge DMAC = 01-80-C2-00-00-10 ANA:PORT: Redirect CPU_FWD_CFG.CPU_ALLBRIDGE_REDIR_ENA ANA::CPUQ_CFG.CPUQ_ALLBRIDGE IEEE 802.1D GARP Range DMAC = 01-80-C2-00-00-2x ANA:PORT:CPU_FWD_GARP_CFG ANA::CPUQ_8021_CFG.CPUQ_GARP_VAL Redirect IEEE 802.1D CCM/Link Trace Range DMAC = 01-80-C2-00-00-3x ANA:PORT:CPU_FWD_CCM_CFG ANA::CPUQ_8021_CFG.CPUQ_CCM_VAL Redirect IGMP (IPv4) ANA:PORT:CPU_IGMP_REDIR_ENA ANA::CPUQ_CFG.CPUQ_IGMP Redirect IP Multicast Control (IPv4) ANA:PORT:CPU_IPMC_CTRL_COPY_ENA ANA::CPUQ_CFG.CPUQ_IPMC_CTRL Copy Redirect VMDS-10392 VSC7420-02, VSC7421-02, and VSC7422-02 Datasheet Revision 4.3 162 Features Table 146 • Configurations for Redirecting or Copying Frames to the CPU (continued) Frame Type Configuration (Including Selection of Extraction Redirect Queue) or Copy MLD (IPv6) ANA:PORT:CPU_MLD_REDIR_ENA ANA::CPUQ_CFG.CPUQ_MLD Redirect CPU-based learning ANA:PORT:PORT_CFG.LEARNCPU ANA::CPUQ_CFG.CPUQ_LRN Copy CPU-based learning of locked MAC ANA:PORT: table entries seen on a new port PORT_CFG.LOCKED_PORTMOVE_CPU ANA::CPUQ_CFG.CPUQ_LOCKED_PORTMOVE 6.7.2 CPU-based learning of frames exceeding learn limit in MAC table ANA:PORT:PORT_CFG.LIMIT_CPU ANA::CPUQ_CFG.CPUQ_LRN MAC table match using MAC table ANA::MACACCESS.MAC_CPU_COPY ANA::CPUQ_CFG.CPUQ_MAC_COPY Copy MAC table match using PGID table ANA::MACACCESS.DEST_IDX ANA::PGID.PGID (bit 26) ANA::PGID.CPUQ_DST_PGID Redirect or copy Flooded frames ANA::MACACCESS.DEST_IDX ANA::PGID.PGID (bit 26) ANA::PGID.CPUQ_DST_PGID Redirect or copy Any frame received on selected ports ANA:PORT:CPU_SRC_COPY_ENA ANA:CPUQ_CFG.CPUQ_SRC_COPY Copy Mirroring Copy ANA::MIRRORPORTS (bit 26) ANA::CPUQ_CFG:CPUQ_MIRROR For more information about mirroring, see Mirroring, page 156. SFlow ANA::CPUQ_CFG.CPUQ_SFLOW For more information about SFlow, see sFlow Sampling, page 62. Copy Frame Extraction The CPU receives frames through the eight CPU extraction queues in the CPU port module. The eight queues are using resources (memory and frame descriptor pointers) from the shared queue system and are subject to the thresholds and congestion rules programmed for the CPU port (port 26) and the shared queue system in general. Through register access, the CPU can extract frames from the CPU extraction queues. For more information, see Frame Extraction, page 81. The switch core may place the eight-byte long CPU extraction header before the DMAC or after the SMAC (REW::PORT_CFG.IFH_INSERT_MODE). The CPU extraction header contains relevant side band information about the frame such as the frame’s classification result (VLAN tag information, DSCP, or QoS class) and the reason for sending the frame to the CPU. For more information about the contents of the CPU extraction header, see CPU Extraction Header, page 82. 6.7.3 Frame Injection The CPU can inject frames through the two CPU injection groups. The two groups merge into one injection queue through the injection scheduler (DEVCPU_QS::INJ_GRP_CFG). The injection queue uses resources (memory and frame descriptor pointers) from the shared queue system and is subject to the thresholds and congestion rules programmed for the CPU port (port 26) and the shared queue system in general. VMDS-10392 VSC7420-02, VSC7421-02, and VSC7422-02 Datasheet Revision 4.3 163 Features Through register access, the CPU can inject frames to the CPU injection groups. For more information, see Frame Injection, page 83. The first eight bytes of a frame written into a CPU group is an injection header containing relevant side band information about how the frame must be processed by the switch core. For more information, see Table 66, page 83. 6.7.4 Frame Extraction and Injection Using An External CPU The following table lists the configuration registers associated with using an external CPU. Table 147 • Configuration Registers When Using An External CPU Register/Register Field Description/Value SYS::EXT_CPU_CFG.EXT_CPU_PO Port number where external RT CPU is connected. Replication None SYS::EXT_CPU_CFG.EXT_CPUQ_M Configures which CPU None SK Extraction Queues are sent to the external CPU. REW::PORT_CFG.IFH_INSERT_ENA Enables the insertion of the CPU extraction header in egress frames. Per port REW::PORT_CFG.IFH_INSERT_MOD Controls the position of the E CPU extraction header. Per port SYS::PORT_MODE.INCL_INJ_HDR Enables ingress port to look for Per port CPU injection header in incoming frames. An external CPU can connect up to any front port module and use the Ethernet interface for extracting and injecting frames into the switch core. Note If an external CPU is connected by means of the serial interface, the frame extraction and injection is performed. For more information, see Frame Extraction, page 163 and Frame Injection, page 163. When extracting frames, the CPU extraction header can be placed before the DMAC (in the preamble) or after the SMAC (REW::PORT_CFG.IFH_INSERT_MODE). For more information about the contents of the eight-byte long extraction header, see Frame Extraction, page 163. When injecting frames, the CPU injection header controls whether a frame is processed by the analyzer or forwarded directly to the destination set specified in the injection header. The injection header must be placed before destination MAC address in the frame. For more information about the contents of the eight-byte long injection header, see Frame Injection, page 163. An internal and external CPU may coexist in a dual CPU system where the two CPUs handles different run-time protocols. When extracting CPU frames, it is selectable which CPU extraction queues are connected to the external CPU and which remain connected to the internal CPU (SYS::EXT_CPU_CFG.EXT_CPUQ_MSK). If a frame is forwarded to the CPU for more than one reason (for example, a BPDU which is also a learn frame), the frame can be forwarded to both the internal CPU extraction queues and to the external CPU. 6.8 Energy Efficient Ethernet Defined by IEEE 802.3az, Energy Efficient Ethernet (EEE) provides a mechanism for reducing the energy consumption on Ethernet links during times of low utilization. Basically, when the transmission queues on a link are empty, the connecting macros and PHYs can be put into a sleep mode using LowPower Idles (LPI), where the energy consumption is reduced by turning off unused circuits. When data is ready again for transmission, the macros and PHYs are waked up and data can flow again. The reaction time for bringing the link alive again is in the range of microseconds, so no data is lost due to low-power idles, however, data will experience increased latency. VMDS-10392 VSC7420-02, VSC7421-02, and VSC7422-02 Datasheet Revision 4.3 164 Features Both internal PHYs and internal SerDes macros support EEE in both the Rx and Tx direction. The following table lists configuration registers related to using Energy Efficient Ethernet. Table 148 • Configuration Registers When Using Energy Efficient Ethernet Register/Register Field Description/Value Replication SYS:PORT:EEE_CFG Queue system configuration of EEE. Per port SYS::EEE_THRESH EEE thresholds used by queue system. None PORT::PCS1G_LPI_CFG Low power idle configuration for the PCS. Per SerDes port PORT::PCS1G_LPI_WAKE_ERRO Wake error counter. R_CNT Per SerDes port PORT::PCS1G_LPI_STATUS Low power idle status. Per SerDes port HSIO::SERDES6G_MISC_CFG Enable LPI in 6G SerDes. Per SerDes port IEEE Clause 45 PHY registers EEE configuration for the internal Per Copper PHYs. PHY port Ports with internal copper PHYs support LPI for 100BASE-TX and 1000BASE-T and can also reduce the transmit signal amplitude in a 10BASE-Te mode. For ports with SerDes, the PCS supports LPI for all modes. When the PCS is in LPI, the connecting SerDes macro is also in LPI. To enable Energy Efficient Ethernet, configure the following functions: • Enable the ports for EEE and configure the timers and thresholds in the queue system to determine when the system will attempt to enter the LPI state and how fast it can wake up again. Enable LPI for the relevant ports in PCS, SerDes macros, and internal PHYs. For more information, see PCS, page 15, SERDES6G, page 18, and Cat5 Twisted Pair Media Interface, page 25. VMDS-10392 VSC7420-02, VSC7421-02, and VSC7422-02 Datasheet Revision 4.3 165 Registers 7 Registers This section provides information about the programming interface, register maps, register descriptions, and register tables of the VSC7420-02, VSC7421-02, and VSC7422-02 devices. In writing to registers with reserved bits, use a read-modify-write technique, where the entire register is read, but only the user bits to be changed are modified. Do not change the values of registers and bits marked as reserved. Their read state should not be considered static or unchanging. Unspecified registers and bits must be written to 0 and can be ignored when read. 7.1 Targets and Base Addresses The following table lists all register targets and associated base addresses for the VSC7420-02, VSC7421-02, and VSC7422-02 devices. The next level lists registers groups and offsets within targets, and the deepest level lists registers within the register groups. Both register groups and registers may be replicated (repeated) a number of times. The repeat-count and the distance between two repetitions is listed in the “Instances and Address Spacing” column of the tables. If there is only one instance, the spacing is omitted. The “Offset within Target”/”Offset within Register Group” columns hold the offset of the first instance of the register group/register. To calculate the absolute address of a given register, multiply the register group’s replication number by the register group's address spacing and add it to the register group’s offset within the target. Then multiply the register’s replication number with the register’s address spacing and add it to the register’s offset within the register group. Finally, add these two numbers to the absolute address of the target in question. Table 149 • List of Targets and Base Addresses Target Name Base Address Description Details DEVCPU_ORG 0x60000000 CPU Device Origin Page 167 SYS 0x60010000 Switching Engine Configuration Page 170 ANA 0x60020000 Analyzer Configuration Page 194 REW 0x60030000 Rewriter Configuration Page 221 DEVCPU_GCB 0x60070000 CPU Device General Configuration Page 225 DEVCPU_QS 0x60080000 CPU Device Queue System Page 257 HSIO 0x600A0000 High Speed I/O SerDes Configuration Page 264 DEV[0] 0x601E0000 Port Configuration (GMII) Page 274 DEV[1] 0x601F0000 Port Configuration (GMII) Page 274 DEV[2] 0x60200000 Port Configuration (GMII) Page 274 DEV[3] 0x60210000 Port Configuration (GMII) Page 274 DEV[4] 0x60220000 Port Configuration (GMII) Page 274 DEV[5] 0x60230000 Port Configuration (GMII) Page 274 DEV[6] 0x60240000 Port Configuration (GMII) Page 274 DEV[7] 0x60250000 Port Configuration (GMII) Page 274 DEV[8] 0x60260000 Port Configuration (GMII) Page 274 DEV[9] 0x60270000 Port Configuration (GMII) Page 274 DEV[10] 0x60280000 Port Configuration (GMII/SERDES) Page 283 DEV[11] 0x60290000 Port Configuration (GMII/SERDES) Page 283 VMDS-10392 VSC7420-02, VSC7421-02, and VSC7422-02 Datasheet Revision 4.3 166 Registers Table 149 • List of Targets and Base Addresses (continued) 7.2 Target Name Base Address Description Details DEV[12] 0x602A0000 Port Configuration (SERDES) Page 283 DEV[13] 0x602B0000 Port Configuration (SERDES) Page 283 DEV[14] 0x602C0000 Port Configuration (SERDES) Page 283 DEV[15] 0x602D0000 Port Configuration (SERDES) Page 283 DEV[16] 0x602E0000 Port Configuration (SERDES) Page 283 DEV[17] 0x602F0000 Port Configuration (SERDES) Page 283 DEV[18] 0x60300000 Port Configuration (SERDES) Page 283 DEV[19] 0x60310000 Port Configuration (SERDES) Page 283 DEV[20] 0x60320000 Port Configuration (SERDES) Page 283 DEV[21] 0x60330000 Port Configuration (SERDES) Page 283 DEV[22] 0x60340000 Port Configuration (SERDES) Page 283 DEV[23] 0x60350000 Port Configuration (SERDES) Page 283 DEV[24] 0x60360000 Port Configuration (SERDES) Page 283 DEV[25] 0x60370000 Port Configuration (SERDES) Page 283 ICPU_CFG 0x70000000 VCore Configuration Page 305 UART 0x70100000 VCore UART Configuration Page 343 TWI 0x70100400 VCore Two-Wire Interface Configuration Page 355 PHY MIIM PHY Configuration Page 378 DEVCPU_ORG Table 150 • Register Groups in DEVCPU_ORG 7.2.1 Offset within Register Group Name Target Instances and Address Spacing Description Details ORG 1 Page 167 0x00000000 Origin registers DEVCPU_ORG:ORG Parent: DEVCPU_ORG Instances: 1 Table 151 • Registers in ORG Register Name Offset within Register Group Instances and Address Spacing Description Details ERR_ACCESS_DROP 0x00000000 1 Target Module ID is Unknown Page 168 ERR_TGT 0x00000008 1 Target Module is Busy Page 168 ERR_CNTS 0x0000000C 1 Error Counters Page 169 VMDS-10392 VSC7420-02, VSC7421-02, and VSC7422-02 Datasheet Revision 4.3 167 Registers Table 151 • Registers in ORG (continued) 7.2.1.1 Register Name Offset within Register Group Instances and Address Spacing Description Details CFG_STATUS 0x0000001C 1 Page 169 Configuration and Status Register DEVCPU_ORG:ORG:ERR_ACCESS_DROP Parent: DEVCPU_ORG:ORG Instances: 1 Table 152 • Fields in ERR_ACCESS_DROP Field Name Bit Access Description NO_ACTION_STICKY 24 Sticky Sticky bit that - when set - indicates 0x0 that at least one request was received by a target, but the target did not do anything with it (Eg. access to a non existing register) '0': No errors occurred. '1': At least one request was received with no action. TGT_MODULE_NO_ACTI 23:16 ON_STICKY R/O Target Module ID. When the sticky_no_action bit is set, this field holds the ID of the last target that received a request that didn't resolve in an action. 0x01 : Module id 1 0xFF : module id 255 UTM_STICKY Sticky Sticky bit that - when set - indicates 0x0 that at least one request for an unknown target module has been done. '0': No errors occurred. '1': At least one request to an unknown target has been done. R/O 0x00 Target Module ID. When the sticky_utm bit is set, this field holds the ID of the last target that was unknown. 0x01 : Module id 1 0xFF : module id 255 8 TGT_MODULE_UTM_STI 7:0 CKY 7.2.1.2 Default 0x00 DEVCPU_ORG:ORG:ERR_TGT Parent: DEVCPU_ORG:ORG Instances: 1 Write all ones to this register to clear it. VMDS-10392 VSC7420-02, VSC7421-02, and VSC7422-02 Datasheet Revision 4.3 168 Registers Table 153 • Fields in ERR_TGT 7.2.1.3 Field Name Bit Access Description Default BSY_STICKY 8 Sticky Sticky bit that - when set - indicates 0x0 that at least one request was not processed because the target was busy. '0': No error has occurred '1': A least one request was dropped due to that the target was busy. TGT_MODULE_BSY 7:0 R/O 0x00 Target Module ID. When the sticky_bsy bit is set, this field holds the ID of the last target that was unable to process a request. 0x01 : Module id 1 0xFF : Module id 255 DEVCPU_ORG:ORG:ERR_CNTS Parent: DEVCPU_ORG:ORG Instances: 1 Table 154 • Fields in ERR_CNTS 7.2.1.4 Field Name Bit Access Description Default NO_ACTION_CNT 31:24 R/W 0x00 No action Counter. Counts the number of requests that were not processed by the Target Module, because the target did not know what to do ( e.g. access to a non-existing register ). This counter saturates at max. UTM_CNT 23:16 R/W 0x00 Unknown Target Counter. Counts the number of requests that were not processed by the Target Module, because the target was no found. This counter saturates at max. BUSY_CNT 15:8 R/W Busy Counter. Counts the number of requests that were not processed by the Target Module, because it was busy. This may be because the Target Module was waiting for access to/from its host. This counter saturates at max. 0x00 DEVCPU_ORG:ORG:CFG_STATUS Parent: DEVCPU_ORG:ORG Instances: 1 VMDS-10392 VSC7420-02, VSC7421-02, and VSC7422-02 Datasheet Revision 4.3 169 Registers Table 155 • Fields in CFG_STATUS Field Name Bit Access Description RD_ERR_STICKY 1 Sticky If a new read access is initialized 0x0 before the previous read access has completed this sticky bit is set. Both the 1st and 2nd read access will be handled, but the 2nd access will overwrite data from the 1st access. '0': A read access that has been initialized before the previous read access had completed has never occurred. '1': At least one time a read access has been initialized before the previous read access had completed. R/O When set a access is in progress. 0x0 '0': No access is in progress. '1': A access is in progress. ACCESS_IN_PROGRESS 0 7.3 Default SYS Table 156 • Register Groups in SYS Offset within Register Group Name Target Instances and Address Spacing Description Details SYSTEM 0x000081B0 1 Switch Configuration Page 171 SCH 0x0000845C 1 Scheduler registers Page 178 SCH_LB 0x00003800 1 Scheduler leaky bucket registers Page 182 RES_CTRL 0x00004000 1024 0x00000008 Watermarks and status for egress queue system Page 183 PAUSE_CFG 0x000085A4 1 Watermarks for egress queue system Page 185 MMGT 0x000037A0 1 Memory manager status Page 187 MISC 0x000037AC 1 Miscellaneous Page 188 STAT 0x00000000 3558 0x00000004 Frame statistics Page 189 POL 0x00006000 256 0x00000020 General policer configuration Page 190 POL_MISC 0x00008704 1 Flow control configuration Page 192 ISHP 0x00008000 27 0x00000010 Ingress shaper configuration Page 193 VMDS-10392 VSC7420-02, VSC7421-02, and VSC7422-02 Datasheet Revision 4.3 170 Registers 7.3.1 SYS:SYSTEM Parent: SYS Instances: 1 Table 157 • Registers in SYSTEM 7.3.1.1 Register Name Offset within Register Group Instances and Address Spacing Description Details RESET_CFG 0x00000000 1 Core reset control Page 171 VLAN_ETYPE_CFG 0x00000008 1 S-tag Ethernet Type Page 172 PORT_MODE 0x0000000C 28 0x00000004 Per device port configuration Page 172 FRONT_PORT_MODE 0x0000007C 26 0x00000004 Various Ethernet port configurations Page 173 SWITCH_PORT_MODE 0x000000E4 27 0x00000004 Various switch port mode settings Page 173 FRM_AGING 0x00000150 1 Configure Frame Aging Page 173 STAT_CFG 0x00000154 1 Statistics configuration Page 174 EEE_CFG 0x00000158 26 0x00000004 Page 174 Control Energy Efficient Ethernet operation per front port. EEE_THRES 0x000001C0 1 Thresholds for delayed EEE queues Page 175 IGR_NO_SHARING 0x000001C4 1 Control shared memory users Page 176 EGR_NO_SHARING 0x000001C8 1 Control shared memory users Page 176 SW_STATUS 0x000001CC 27 0x00000004 Various status info per switch port Page 176 EQ_TRUNCATE 0x00000238 27 0x00000004 Truncate frames in queue Page 177 EQ_PREFER_SRC 0x000002A4 1 Precedence for source ports Page 177 EXT_CPU_CFG 0x000002A8 1 External CPU port configuration Page 177 SYS:SYSTEM:RESET_CFG Parent: SYS:SYSTEM Instances: 1 Controls reset and initialization of the switching core. Proper startup sequence is: - Enable memories - Initialize memories - Enable core VMDS-10392 VSC7420-02, VSC7421-02, and VSC7422-02 Datasheet Revision 4.3 171 Registers Table 158 • Fields in RESET_CFG 7.3.1.2 Field Name Bit Access Description Default CORE_ENA 2 R/W Switch core is enabled when this field is set. 0x0 MEM_ENA 1 R/W Core memory controllers are enabled when this field is set. 0x0 MEM_INIT 0 One-shot 0x0 Initialize core memories. Field is automatically cleared when operation is complete ( approx. 40 us). SYS:SYSTEM:VLAN_ETYPE_CFG Parent: SYS:SYSTEM Instances: 1 Table 159 • Fields in VLAN_ETYPE_CFG Field Name Bit VLAN_S_TAG_ETYPE_V 15:0 AL 7.3.1.3 Access Description Default R/W Custom Ethernet Type for S-tags. Tags with TPID = 0x88A8 are always recognized as S-tags. 0x88A8 SYS:SYSTEM:PORT_MODE Parent: SYS:SYSTEM Instances: 28 These configurations exists per frontport and for each of the two CPU ports (26+27). Table 160 • Fields in PORT_MODE Field Name Bit Access Description Default RESERVED 4:3 R/W Must be set to its default. 0x2 L3_PARSE_CFG 2 R/W Enable frame analysis on Layer-3 0x1 and Layer-4 protocol information. If cleared, all frames are seen as non-IP and are handled accordingly. This affects all blocks using IP information such as classification, IP flooding, IP forwarding, and DSCP rewriting. DEQUEUE_DIS 1 R/W Disable dequeuing from the egress 0x0 queues. Frames are not discarded, but may become aged when dequeuing is re-enabled. INCL_INJ_HDR 0 R/W Enable parsing of 64-bit injection 0x0 header, which must be prepended all frames received on this port. VMDS-10392 VSC7420-02, VSC7421-02, and VSC7422-02 Datasheet Revision 4.3 172 Registers 7.3.1.4 SYS:SYSTEM:FRONT_PORT_MODE Parent: SYS:SYSTEM Instances: 26 Table 161 • Fields in FRONT_PORT_MODE 7.3.1.5 Field Name Bit Access Description Default HDX_MODE 0 R/W Enables the queue system to support the half duplex mode. Must be set for a port when enabled for half-duplex mode (MAC_MODE_ENA.FDX_ENA cleared). 0x0 SYS:SYSTEM:SWITCH_PORT_MODE Parent: SYS:SYSTEM Instances: 27 Table 162 • Fields in SWITCH_PORT_MODE 7.3.1.6 Field Name Bit Access Description Default PORT_ENA 3 R/W Enable port for any frame transfer. 0x0 Frames to or from a port with PORT_ENA cleared are discarded. RESERVED 2 R/W Must be set to its default. 0x1 RESERVED 1 R/W Must be set to its default. 0x1 SYS:SYSTEM:FRM_AGING Parent: SYS:SYSTEM Instances: 1 VMDS-10392 VSC7420-02, VSC7421-02, and VSC7422-02 Datasheet Revision 4.3 173 Registers Table 163 • Fields in FRM_AGING Field Name Bit Access Description Default MAX_AGE 31:0 R/W 0x00000000 Frames are aged and removed from the queue system when the frame's age timer becomes two. The frame age timer is increased for all frames whenever the configured time, MAX_AGE, has passed. The unit is 4 ns. Effectively, this means that a frame is aged when the frame has waited in the queue system between one or two times the period specified by MAX_AGE. A value of zero disables the aging. A value less than 6000 (24 us) is illegal. 7.3.1.7 SYS:SYSTEM:STAT_CFG Parent: SYS:SYSTEM Instances: 1 Table 164 • Fields in STAT_CFG 7.3.1.8 Field Name Bit Access Description Default RESERVED 10 R/W Must be set to its default. 0x1 RESERVED 9 R/W Must be set to its default. 0x1 RESERVED 8 R/W Must be set to its default. 0x1 RESERVED 7 R/W Must be set to its default. 0x1 STAT_CLEAR_PORT 5:1 R/W Select which port to clear counters 0x00 for. STAT_CLEAR_SHOT 0 One-shot Set STAT_CLEAR_SHOT to clear 0x0 all counters for the port selected by STAT_CLEAR_PORT port. Auto-cleared when complete (1us). SYS:SYSTEM:EEE_CFG Parent: SYS:SYSTEM Instances: 26 VMDS-10392 VSC7420-02, VSC7421-02, and VSC7422-02 Datasheet Revision 4.3 174 Registers Table 165 • Fields in EEE_CFG Field Name Bit Access Description Default EEE_ENA 29 R/W Enable EEE operation on the port. 0x0 A port enters the low power mode when no egress queues have data ready. The port is activated when one of the following conditions is true: - A queue has been non-empty for EEE_TIMER_AGE. - A queue has more than EEE_HIGH_FRAMES frames pending. - A queue has more than EEE_HIGH_BYTES bytes pending. - A queue is marked as a fast queue, and has data pending. EEE_FAST_QUEUES 28:21 R/W 0x00 Queues set in this mask activate the egress port immediately when any of the queues have data available. EEE_TIMER_AGE 20:14 R/W 0x23 Maximum time frames in any queue must wait before the port is activated. The default value corresponds to 48 us. Time = 4**(EEE_TIMER_AGE/16) * (EEE_TIMER_AGE mod 16) microseconds 7.3.1.9 0x14 EEE_TIMER_WAKEUP 13:7 R/W Time from the egress port is activated until frame transmission is restarted. Default value corresponds to 16 us. Time = 4**(EEE_TIMER_WAKEUP/16) * (EEE_TIMER_WAKEUP mod 16) microseconds EEE_TIMER_HOLDOFF 6:0 R/W 0x05 When all queues are empty, the port is kept active until this time has passed. Default value corresponds to 5 us. Time = 4**(EEE_TIMER_HOLDOFF/16) * (EEE_TIMER_HOLDOFF mod 16) microseconds SYS:SYSTEM:EEE_THRES Parent: SYS:SYSTEM VMDS-10392 VSC7420-02, VSC7421-02, and VSC7422-02 Datasheet Revision 4.3 175 Registers Instances: 1 Table 166 • Fields in EEE_THRES Field Name Bit Access Description Default EEE_HIGH_BYTES 15:8 R/W Maximum number of bytes in a queue before egress port is activated. Unit is 48 bytes. 0x00 EEE_HIGH_FRAMES 7:0 R/W Maximum number of frames in a queue before the egress port is activated. Unit is 1 frame. 0x00 7.3.1.10 SYS:SYSTEM:IGR_NO_SHARING Parent: SYS:SYSTEM Instances: 1 Table 167 • Fields in IGR_NO_SHARING Field Name Bit Access Description IGR_NO_SHARING 26:0 R/W Control whether frames received 0x0000000 on the port may use shared resources. If ingress port or queue has reserved memory left to use, frame enqueuing is always allowed. 0: Use shared memory as well 1: Do not use shared memory 7.3.1.11 Default SYS:SYSTEM:EGR_NO_SHARING Parent: SYS:SYSTEM Instances: 1 Table 168 • Fields in EGR_NO_SHARING Field Name Bit Access Description EGR_NO_SHARING 26:0 R/W Control whether frames forwarded 0x0000000 to the port may use shared resources. If egress port or queue has reserved memory left to use, frame enqueuing is always allowed. 0: Use shared memory as well 1: Do not use shared memory 7.3.1.12 Default SYS:SYSTEM:SW_STATUS Parent: SYS:SYSTEM Instances: 27 VMDS-10392 VSC7420-02, VSC7421-02, and VSC7422-02 Datasheet Revision 4.3 176 Registers Table 169 • Fields in SW_STATUS Field Name Bit Access Description EQ_AVAIL 9:2 R/O Status bit per egress queue 0x00 indicating whether data is ready for transmission. PORT_LPI 1 R/O Status bit indicating whether port is 0x0 in low-power-idle due to the LPI algorithm (EEE_CFG). If set, transmissions are held back. PORT_RX_PAUSED 0 R/O 0x0 Status bit indicating whether the switch core is instructing the MAC to pause the ingress port. 7.3.1.13 Default SYS:SYSTEM:EQ_TRUNCATE Parent: SYS:SYSTEM Instances: 27 Table 170 • Fields in EQ_TRUNCATE Field Name Bit Access Description EQ_TRUNCATE 7:0 R/W If a bit is set, frames transmitted 0x00 from corresponding egress queue are truncated to 92 bytes. 7.3.1.14 Default SYS:SYSTEM:EQ_PREFER_SRC Parent: SYS:SYSTEM Instances: 1 Table 171 • Fields in EQ_PREFER_SRC Field Name Bit Access Description EQ_PREFER_SRC 26:0 R/W When multiple sources have data 0x4000000 in the same priority, ingress ports set in this mask are preferred over ingress ports not set when arbitrating frames from ingress to egress. When multiple ports are set, the arbitration between these ports are round-robin. 7.3.1.15 Default SYS:SYSTEM:EXT_CPU_CFG Parent: SYS:SYSTEM Instances: 1 VMDS-10392 VSC7420-02, VSC7421-02, and VSC7422-02 Datasheet Revision 4.3 177 Registers Table 172 • Fields in EXT_CPU_CFG 7.3.2 Field Name Bit Access Description Default EXT_CPU_PORT 12:8 R/W Select the port to use as the external CPU port. 0x1B EXT_CPUQ_MSK 7:0 R/W Frames destined for a CPU extraction queue set in this mask are sent to the external CPU defined by EXT_CPU_PORT instead of the internal CPU. 0x00 SYS:SCH Parent: SYS Instances: 1 Table 173 • Registers in SCH 7.3.2.1 Register Name Offset within Register Group Instances and Address Spacing Description Details LB_DWRR_FRM_ADJ 0x00000000 1 Leaky bucket frame adjustment Page 178 LB_DWRR_CFG 0x00000004 26 0x00000004 Leaky bucked frame adjustment Page 179 SCH_DWRR_CFG 0x0000006C 26 0x00000004 Deficit weighted round robin Page 179 control register SCH_SHAPING_CTRL 0x000000D8 26 0x00000004 Scheduler shaping control register Page 180 SCH_LB_CTRL 0x00000140 1 Leaky bucket control Page 181 SCH_CPU 0x00000144 1 Map CPU queues to CPU ports Page 181 SYS:SCH:LB_DWRR_FRM_ADJ Parent: SYS:SCH Instances: 1 VMDS-10392 VSC7420-02, VSC7421-02, and VSC7422-02 Datasheet Revision 4.3 178 Registers Table 174 • Fields in LB_DWRR_FRM_ADJ Field Name Bit Access Description Default FRM_ADJ 4:0 R/W Value added to leaky buckets and 0x00 DWRR each time a frame is scheduled. If set to 20, this corresponds to inclusion of minimum Ethernet IFG and preamble. 0-31: Number of bytes added at start of frame 7.3.2.2 SYS:SCH:LB_DWRR_CFG Parent: SYS:SCH Instances: 26 Table 175 • Fields in LB_DWRR_CFG Field Name Bit Access Description Default FRM_ADJ_ENA 0 R/W If enabled, the value configured in 0x0 SCH_LB_DWRR_FRM_ADJ.FRM _ADJ is added to the frame length for each frame. The modified frame length is used by both the leaky bucket and DWRR algorithm. 0:Disable frame length adjustment. 1:Enable frame length adjustment. 7.3.2.3 SYS:SCH:SCH_DWRR_CFG Parent: SYS:SCH Instances: 26 Table 176 • Fields in SCH_DWRR_CFG Field Name Bit Access Description Default DWRR_MODE 30 R/W 0x0 Configure DWRR scheduling for port. Weighted- and strict prioritization can be configured. 0: All priorities are scheduled strict 1: The two highest priorities (6, 7) are strict. The rest is DWRR VMDS-10392 VSC7420-02, VSC7421-02, and VSC7422-02 Datasheet Revision 4.3 179 Registers Table 176 • Fields in SCH_DWRR_CFG (continued) 7.3.2.4 Field Name Bit Access Description Default COST_CFG 29:0 R/W 0x00000000 Queue cost configuration. Bit vector used to configure the cost of each priority. Bits 4:0: Cost for queue 0. Bits 9:5: Cost for queue 1. Bits 14:10: Cost for queue 2. Bits 19:15: Cost for queue 3. Bits 24:20: Cost for queue 4. Bits 29:25: Cost for queue 5. Within each cost field, the following encoding is used: 0: Cost 1 1: Cost 2 ... 31: Cost 32 SYS:SCH:SCH_SHAPING_CTRL Parent: SYS:SCH Instances: 26 Table 177 • Fields in SCH_SHAPING_CTRL Field Name Bit Access Description Default PRIO_SHAPING_ENA 7:0 R/W Enable priority shaping. If enabled 0x00 the BW of a priority is limited to SCH_LB::LB_RATE. xxxxxxx1: Enable shaping for Prio 0 xxxxxx1x: Enable shaping for Prio 1 ... 1xxxxxxx: Enable shaping for Prio N PORT_SHAPING_ENA 8 R/W Enable port shaping. If enabled the 0x0 total BW of a port is limited to SCH_LB::LB_RATE. 0: Disable port shaping 1: Enable port shaping VMDS-10392 VSC7420-02, VSC7421-02, and VSC7422-02 Datasheet Revision 4.3 180 Registers Table 177 • Fields in SCH_SHAPING_CTRL (continued) Field Name Bit Access Description Default PRIO_LB_EXS_ENA 23:16 R/W 0x00 Allow this queue to use excess bandwidth. If none of the priorities are allowed (by their priority LB) to transmit. The resulting BW of a queue is a function of the port- and queue LBs, the DWRR and the excess enable bit: 1) Port LB closed. Hold back frames. 2) Port LB open -> Use strict- or DWRR scheduling to distribute traffic between open Queue LBs 3) All Queue LBs closed -> Hold back frames except for Queues which have PRIO_LB_EXS_ENA set. The excess BW is distributed using strict- or DWRR scheduling. xxxxxxx1: Enable excess BW for Prio 0 xxxxxx1x: Enable excess BW for Prio 1 ... 1xxxxxxx: Enable excess BW for Prio N 7.3.2.5 SYS:SCH:SCH_LB_CTRL Parent: SYS:SCH Instances: 1 Table 178 • Fields in SCH_LB_CTRL Field Name Bit Access Description Default LB_INIT 0 One-shot 0x0 Set to 1 to force a complete initialization of state and configuration of leaky buckets. Must be done before the scheduler is used. Field is automatically cleared whether initialization is complete. 0: No Action 1: Force initialization. 7.3.2.6 SYS:SCH:SCH_CPU Parent: SYS:SCH Instances: 1 VMDS-10392 VSC7420-02, VSC7421-02, and VSC7422-02 Datasheet Revision 4.3 181 Registers Table 179 • Fields in SCH_CPU 7.3.3 Field Name Bit Access Description Default SCH_CPU_MAP 9:2 R/W Maps the 8 CPU queues to CPU port 26 or 27. Bit set directs CPU queue to CPU port 26/27. 0x00 SCH_CPU_RR 1:0 R/W Set the scheduler for CPU port 0x0 to run round robin between queues instead of strict. SYS:SCH_LB Parent: SYS Instances: 1 Ethernet leaky bucket configuration per port and per priority. The address of the configuration is based on the following layout: (Assume the priority count is 8) 0: Leaky bucket for priority 0 of port 0 1: Leaky bucket for priority 1 of port 0 2: Leaky bucket for priority 2 of port 0 3: Leaky bucket for priority 3 of port 0 4: Leaky bucket for priority 4 of port 0 5: Leaky bucket for priority 5 of port 0 6: Leaky bucket for priority 6 of port 0 7: Leaky bucket for priority 7 of port 0 8: Leaky bucket port 0 9: Leaky bucket for priority 0 of port 1 10: Leaky bucket for priority 1 of port 1 . . The configuration for each leaky bucket includes rate and threshold configuration. Table 180 • Registers in SCH_LB Register Name Offset within Register Group Instances and Address Spacing Description LB_THRES 0x00000000 234 0x00000004 Leaky bucket threshold Page 183 LB_RATE 0x00000400 234 0x00000004 Leaky bucket rate Page 183 Details VMDS-10392 VSC7420-02, VSC7421-02, and VSC7422-02 Datasheet Revision 4.3 182 Registers 7.3.3.1 SYS:SCH_LB:LB_THRES Parent: SYS:SCH_LB Instances: 234 Table 181 • Fields in LB_THRES Field Name Bit Access Description Default LB_THRES 5:0 R/W Burst capacity of leaky buckets 0x00 The unit is 4KB (1KB = 1024Bytes). The largest supported threshold is 252KB when the register value is set to all "1"s. Queue shaper Q on port P uses shaper 9*P+Q. Port shaper on port P uses shaper 9*P+8. 0: Always closed 1: Burst capacity = 4096 bytes ... n: Burst capacity = n x 4096 bytes 7.3.3.2 SYS:SCH_LB:LB_RATE Parent: SYS:SCH_LB Instances: 234 Table 182 • Fields in LB_RATE Field Name Bit Access Description Default LB_RATE 14:0 R/W Leaky bucket rate in unit of 100160 0x0000 bps. Queue shaper Q on port P uses shaper 9*P+Q. Port shaper on port P uses shaper 9*P+8. 0: Open until burst capacity is used, then closed. 1: Rate = 100160 bps n: Rate = n x 100160 bps 7.3.4 SYS:RES_CTRL Parent: SYS Instances: 1024 VMDS-10392 VSC7420-02, VSC7421-02, and VSC7422-02 Datasheet Revision 4.3 183 Registers Table 183 • Registers in RES_CTRL 7.3.4.1 Register Name Offset within Register Group Instances and Address Spacing Description Details RES_CFG 0x00000000 1 Watermark configuration Page 184 RES_STAT 0x00000004 1 Resource status Page 185 SYS:RES_CTRL:RES_CFG Parent: SYS:RES_CTRL Instances: 1 The queue system tracks four resource consumptions: Resource 0: Memory tracked per source Resource 1: Frame references tracked per source Resource 2: Memory tracked per destination Resource 3: Frame references tracked per destination Before a frame is added to the queue system, some conditions must be met: - Reserved memory for the specific (SRC, PRIO) or for the specific SRC is available OR - Reserved memory for the specific (DST,PRIO) or for the specific DST is available OR - Shared memory is available The frame reference resources are checked for availability like the memory resources. Enqueuing of a frame is allowed if both the memory resource check and the frame reference resource check succeed. The extra resources consumed when enqueuing a frame are first taken from the reserved (SRC,PRIO), next from the reserved SRC, and last from the shared memory area. The same is done for DST. Both memory consumptions and frame reference consumptions are updated. The register is layed out the following way: Index 0-215: Reserved amount for (x,PRIO) at index 8*x+PRIO, x=SRC or DST Index 224-250: Reserved amount for (x) Resource 0 is accessed at index 0-255, 1 at index 256-511 etc. The amount of shared memory is located at index 255. An extra watermark at 254 is used for limiting amount of shared memory used before yellow traffic is discarded. The amount of shared references is located at index 511. An extra watermark at 510 is used for limiting amount of shared references for yellow traffic. VMDS-10392 VSC7420-02, VSC7421-02, and VSC7422-02 Datasheet Revision 4.3 184 Registers At index 216-223 there is a watermarks per priority used for limiting how much of the shared buffer must be used per priority. Likewise at offset 472 there are priority watermarks for references. The allocation size for memory tracking is 48 bytes, and all frames is added a 4 byte header internally. Table 184 • Fields in RES_CFG 7.3.4.2 Field Name Bit Access Description Default WM_HIGH 10:0 R/W 0x000 Watermark for resource. Note, the default value depends on the index. Refer to the congestion scheme documentation for details. Bit 10: Unit; 0:1, 1:16 Bits 9-0: Value to be multiplied with unit SYS:RES_CTRL:RES_STAT Parent: SYS:RES_CTRL Instances: 1 Table 185 • Fields in RES_STAT 7.3.5 Field Name Bit Access Description Default INUSE 27:14 R/W Current consumption for corresponding watermark in RES_CFG. 0x0000 MAXUSE 13:0 R/W Maximum consumption for corresponding watermark in RES_CFG. 0x0000 SYS:PAUSE_CFG Parent: SYS Instances: 1 Table 186 • Registers in PAUSE_CFG Register Name Offset within Register Group Instances and Address Spacing Description PAUSE_CFG 0x00000000 27 0x00000004 Watermarks for flow control Page 186 condition per switch port. PAUSE_TOT_CFG 0x0000006C 1 Configure total memory pause condition Page 186 ATOP 0x00000070 27 0x00000004 Tail dropping level Page 187 Details VMDS-10392 VSC7420-02, VSC7421-02, and VSC7422-02 Datasheet Revision 4.3 185 Registers Table 186 • Registers in PAUSE_CFG (continued) 7.3.5.1 Register Name Offset within Register Group Instances and Address Spacing Description Details ATOP_TOT_CFG 0x000000DC 1 Total raw memory use before tail dropping is activated Page 187 EGR_DROP_FORCE 0x000000E0 1 Configures egress ports for Page 187 flowcontrol SYS:PAUSE_CFG:PAUSE_CFG Parent: SYS:PAUSE_CFG Instances: 27 Table 187 • Fields in PAUSE_CFG 7.3.5.2 Field Name Bit Access Description Default PAUSE_START 22:12 R/W Start pausing ingress stream when 0x7FF the amount of memory consumed by the port exceeds this watermark. The TOTPAUSE condition must also be met. See RES_CFG PAUSE_STOP 11:1 R/W Stop pausing ingress stream when 0x7FF the amount of memory consumed by the port is below this watermark. See RES_CFG. PAUSE_ENA 0 R/W 0x0 Enable pause feedback to the MAC, allowing transmission of pause frames or HDX collisions to limit ingress data rate. SYS:PAUSE_CFG:PAUSE_TOT_CFG Parent: SYS:PAUSE_CFG Instances: 1 Table 188 • Fields in PAUSE_TOT_CFG Field Name Bit Access Description Default PAUSE_TOT_START 21:11 R/W Assert TOTPAUSE condition when 0x000 total memory allocation is above this watermark. See RES_CFG PAUSE_TOT_STOP 10:0 R/W Deassert TOTPAUSE condition when total memory allocation is below this watermark. See RES_CFG 0x000 VMDS-10392 VSC7420-02, VSC7421-02, and VSC7422-02 Datasheet Revision 4.3 186 Registers 7.3.5.3 SYS:PAUSE_CFG:ATOP Parent: SYS:PAUSE_CFG Instances: 27 Table 189 • Fields in ATOP 7.3.5.4 Field Name Bit Access Description Default ATOP 10:0 R/W When a source port consumes more than this level in the packet memory, frames are tail dropped, unconditionally of destination. See RES_CFG 0x7FF SYS:PAUSE_CFG:ATOP_TOT_CFG Parent: SYS:PAUSE_CFG Instances: 1 Table 190 • Fields in ATOP_TOT_CFG 7.3.5.5 Field Name Bit Access Description Default ATOP_TOT 10:0 R/W Tail dropping is activate on a port when the port use has exceeded the ATOP watermark for the port, and the total memory use has exceeded this watermark. See RES_CFG 0x7FF SYS:PAUSE_CFG:EGR_DROP_FORCE Parent: SYS:PAUSE_CFG Instances: 1 Table 191 • Fields in EGR_DROP_FORCE Field Name Bit EGRESS_DROP_FORCE 26:0 7.3.6 Access Description Default R/W When enabled for a port, frames to 0x0000000 the port are discarded, even when the ingress port is enabled for flow control. Applicable to egress ports that should not create head-of-line blocking in ingress ports operating in flow control mode. An example is the CPU port. SYS:MMGT Parent: SYS Instances: 1 VMDS-10392 VSC7420-02, VSC7421-02, and VSC7422-02 Datasheet Revision 4.3 187 Registers Table 192 • Registers in MMGT 7.3.6.1 Register Name Offset within Register Group Instances and Address Spacing Description Details MMGT 0x00000000 1 Packet Memory Status Page 188 EQ_CTRL 0x00000008 1 Egress queue status Page 188 SYS:MMGT:MMGT Parent: SYS:MMGT Instances: 1 Table 193 • Fields in MMGT 7.3.6.2 Field Name Bit Access Description Default FREECNT 19:8 R/O Number of 192-byte free memory words. 0x000 SYS:MMGT:EQ_CTRL Parent: SYS:MMGT Instances: 1 Table 194 • Fields in EQ_CTRL 7.3.7 Field Name Bit Access Description Default FP_FREE_CNT 12:0 R/O Number of free frame references. 0x0000 SYS:MISC Parent: SYS Instances: 1 Table 195 • Registers in MISC 7.3.7.1 Register Name Offset within Register Group Instances and Address Spacing Description Details REPEATER 0x00000018 1 Page 188 Frame repeating setup SYS:MISC:REPEATER Parent: SYS:MISC Instances: 1 VMDS-10392 VSC7420-02, VSC7421-02, and VSC7422-02 Datasheet Revision 4.3 188 Registers Table 196 • Fields in REPEATER 7.3.8 Field Name Bit Access Description Default REPEATER 26:0 R/W A bit set in this mask makes the corresponding port skip dequeing from the queue selected by the scheduler. This can be used for simple frame generation and scheduler experiments. 0x0000000 SYS:STAT Parent: SYS Instances: 3558 These registers are used for accessing all frame statistics. Table 197 • Registers in STAT 7.3.8.1 Register Name Offset within Register Group Instances and Address Spacing Description Details CNT 0x00000000 1 Page 189 Counter values SYS:STAT:CNT Parent: SYS:STAT Instances: 1 VMDS-10392 VSC7420-02, VSC7421-02, and VSC7422-02 Datasheet Revision 4.3 189 Registers Table 198 • Fields in CNT 7.3.9 Field Name Bit Access Description Default CNT 31:0 R/W 0x00000000 Counter values. The counters are layed in three main blocks where each port has a share within the block: Rx counters: 0x000 - 0x488 - port0: 0x000 - 0x02A - port1: 0x02B - 0x055 - port26 (CPU): 0x45E - 0x488 Tx counters: 0x800 - 0xB44 - port0: 0x800 - 0x81E - port1: 0x81F - 0x83D - port26 (CPU): 0xB26 - 0xB44 Drop counters: 0xC00 - 0xDE5 - port0: 0xC00 - 0xC11 - port1: 0xC12 - 0xC23 - port26 (CPU): 0xDD4 - 0xDE5 SYS:POL Parent: SYS Instances: 256 Port and QoS policers Table 199 • Registers in POL 7.3.9.1 Register Name Offset within Register Group Instances and Address Spacing Description POL_PIR_CFG 0x00000000 1 Peak Information Rate Page 190 configuration for this policer POL_MODE_CFG 0x00000008 1 Common configuration for this policer Page 191 POL_PIR_STATE 0x0000000C 1 State of this policer Page 191 Details SYS:POL:POL_PIR_CFG Parent: SYS:POL Instances: 1 Table 200 • Fields in POL_PIR_CFG Field Name Bit Access Description Default PIR_RATE 20:6 R/W Accepted rate for this policer. Unit 0x0000 is 100 kbps. VMDS-10392 VSC7420-02, VSC7421-02, and VSC7422-02 Datasheet Revision 4.3 190 Registers Table 200 • Fields in POL_PIR_CFG (continued) 7.3.9.2 Field Name Bit Access Description Default PIR_BURST 5:0 R/W Burst capacity of this policer. Unit is 4 kilobytes. 0x00 Default SYS:POL:POL_MODE_CFG Parent: SYS:POL Instances: 1 Table 201 • Fields in POL_MODE_CFG 7.3.9.3 Field Name Bit Access Description IPG_SIZE 9:5 R/W Size of IPG to add to each frame if 0x14 line rate policing is chosen in FRM_MODE. FRM_MODE 4:3 R/W 0x0 Accounting mode of this policer. 0: Line rate. Police bytes including IPG_SIZE. 1: Data rate. Police bytes excluding IPG. 2. Frame rate. Police frames with rate unit = 100 fps and burst unit = 32.8 frames. 3: Frame rate. Police frame with rate unit = 1 fps and burst unit = 0.3 frames. OVERSHOOT_ENA 0 R/W 0x1 If set, overshoot is allowed. This implies that a frame of any length is accepted if the policer is open even if the frame causes the bucket to use more than the remaining capacity. If cleared, overshoot is not allowed. This implies that it is checked that the frame will not use more than the remaining capacity in the bucket before accepting the frame. SYS:POL:POL_PIR_STATE Parent: SYS:POL Instances: 1 Table 202 • Fields in POL_PIR_STATE Field Name Bit Access Description Default PIR_LVL 21:0 R/W Current fill level of this policer. Unit 0x000000 is 0.5 bits. VMDS-10392 VSC7420-02, VSC7421-02, and VSC7422-02 Datasheet Revision 4.3 191 Registers 7.3.10 SYS:POL_MISC Parent: SYS Instances: 1 Table 203 • Registers in POL_MISC Register Name Offset within Register Group Instances and Address Spacing Description POL_FLOWC 0x00000000 27 0x00000004 Flow control configuration per policer Page 192 POL_HYST 0x0000006C 1 Set delay between flow control clearings Page 192 7.3.10.1 Details SYS:POL_MISC:POL_FLOWC Parent: SYS:POL_MISC Instances: 27 Table 204 • Fields in POL_FLOWC Field Name Bit Access Description POL_FLOWC 0 R/W Use MAC flow control for lowering 0x0 ingress rate 0: Standard policing. Frames are discarded when the rate is exceeded. 1: Flow control policing. Policer instructs the MAC to issue pause frames when the rate is exceeded. 7.3.10.2 Default SYS:POL_MISC:POL_HYST Parent: SYS:POL_MISC Instances: 1 Table 205 • Fields in POL_HYST Field Name Bit Access Description Default POL_FC_HYST 9:4 R/W Set hysteresis for when to re-open 0x02 a bucket after the burst capacity has been used. Unit is 1 kilobytes. This applies to policer in flow control mode (POL_FLOWC=1). POL_DROP_HYST 3:0 R/W Set hysteresis for when to re-open 0x0 a bucket after the burst capacity has been used. Unit is 2 kilobytes. This applies to policer in drop mode (POL_FLOWC=0). VMDS-10392 VSC7420-02, VSC7421-02, and VSC7422-02 Datasheet Revision 4.3 192 Registers 7.3.11 SYS:ISHP Parent: SYS Instances: 27 Table 206 • Registers in ISHP Register Name Offset within Register Group Instances and Address Spacing Description Details ISHP_CFG 0x00000000 1 Rate and burst configuration Page 193 ISHP_MODE_CFG 0x00000004 1 Mode of operation Page 193 ISHP_STATE 0x00000008 1 State of this shaper Page 194 7.3.11.1 SYS:ISHP:ISHP_CFG Parent: SYS:ISHP Instances: 1 Table 207 • Fields in ISHP_CFG Field Name Bit Access Description ISHP_RATE 21:7 R/W Accepted rate for this shaper. Unit 0x0000 is 100 kbps. ISHP_BURST 6:1 R/W Burst capacity of this shaper. Unit is 4kB 0x00 ISHP_ENA 0 R/W Enable ingress shaping for this port. 0x0 7.3.11.2 Default SYS:ISHP:ISHP_MODE_CFG Parent: SYS:ISHP Instances: 1 Table 208 • Fields in ISHP_MODE_CFG Field Name Bit Access Description Default ISHP_IPG_SIZE 6:2 R/W Size of IPG to add each frame if line rate shaping is chosen in ISHP_MODE. 0x14 VMDS-10392 VSC7420-02, VSC7421-02, and VSC7422-02 Datasheet Revision 4.3 193 Registers Table 208 • Fields in ISHP_MODE_CFG (continued) Field Name Bit Access Description ISHP_MODE 1:0 R/W 0x0 Accounting mode of this shaper. 0: Line rate. Shape bytes including IPG_size 1: Data rate. Shape bytes excluding IPG 2. Frame rate. Shape frames with rate unit = 100 fps and burst unit = 32.8 frames. 3: Frame rate. Shape frame with rate unit = 1 fps and burst unit = 0.3 frames. 7.3.11.3 Default SYS:ISHP:ISHP_STATE Parent: SYS:ISHP Instances: 1 Table 209 • Fields in ISHP_STATE 7.4 Field Name Bit Access Description Default ISHP_LVL 21:0 R/W Current fill level of this shaper. Unit 0x000000 is 0.5 bits. ANA Table 210 • Register Groups in ANA 7.4.1 Offset within Register Group Name Target Instances and Address Spacing Description Details ANA 0x00000D80 1 General analyzer configuration Page 194 ANA_TABLES 0x00001000 1 MAC, VLAN, and PGID table configuration Page 204 PORT 0x00000000 27 0x00000080 Per port configurations for Classifier Page 211 COMMON 0x00000E38 1 Common configurations for Page 218 Classifier ANA:ANA Parent: ANA Instances: 1 VMDS-10392 VSC7420-02, VSC7421-02, and VSC7422-02 Datasheet Revision 4.3 194 Registers Table 211 • Registers in ANA 7.4.1.1 Register Name Offset within Register Group Instances and Address Spacing Description Details ADVLEARN 0x00000000 1 Advanced Learning Setup Page 195 VLANMASK 0x00000004 1 VLAN Source Port Mask Page 196 ANAGEFIL 0x00000008 1 Aging Filter Page 196 ANEVENTS 0x0000000C 1 Event Sticky Bits Page 196 STORMLIMIT_BURST 0x00000010 1 Storm policer burst Page 198 STORMLIMIT_CFG 0x00000014 4 0x00000004 Storm Policer configuration Page 198 ISOLATED_PORTS 0x00000024 1 Private VLAN Mask for isolated ports Page 199 COMMUNITY_PORTS 0x00000028 1 Private VLAN Mask for community ports Page 200 AUTOAGE 0x0000002C 1 Auto Age Timer Page 200 MACTOPTIONS 0x00000030 1 MAC Table Options Page 200 LEARNDISC 0x00000034 1 Learn Discard Counter Page 201 AGENCTRL 0x00000038 1 Analyzer Configuration Page 201 MIRRORPORTS 0x0000003C 1 Mirror Target Ports Page 202 EMIRRORPORTS 0x00000040 1 Egress Mirror Mask Page 203 FLOODING 0x00000044 1 Standard flooding configuration Page 203 FLOODING_IPMC 0x00000048 1 Flooding configuration for IP multicasts Page 203 SFLOW_CFG 0x0000004C 27 0x00000004 SFlow sampling configuration per port Page 204 ANA:ANA:ADVLEARN Parent: ANA:ANA Instances: 1 Table 212 • Fields in ADVLEARN Field Name Bit Access Description Default VLAN_CHK 26 R/W If this bit is set, a frame discarded 0x0 because of VLAN ingress filtering is not subject to learning. VLAN ingress filtering is controlled by the VLAN_SRC_CHK flag in the VLAN table (see VLANACCESS register) or the VLANMASK register. LEARN_MIRROR 25:0 R/W Learn frames are also forwarded to 0x0000000 ports marked in this mask. VMDS-10392 VSC7420-02, VSC7421-02, and VSC7422-02 Datasheet Revision 4.3 195 Registers 7.4.1.2 ANA:ANA:VLANMASK Parent: ANA:ANA Instances: 1 Table 213 • Fields in VLANMASK 7.4.1.3 Field Name Bit Access Description VLANMASK 26:0 R/W 0x0000000 Mask for requiring VLAN ingress filtering. If the bit for the frame's physical ingress port is set in this mask, then the port must be member of ingress frame's VLAN (VLANACCESS.VLAN_PORT_MA SK), otherwise the frame is discarded. Default ANA:ANA:ANAGEFIL Parent: ANA:ANA Instances: 1 This register sets up which entries are touched by an aging operation (manual as well as automatic aging). In this way, it is possible to have different aging periods in each VLAN and to have quick removal of entries on specific ports. The register also affects the GET_NEXT MAC table command. When using the register to control the behavior of GET_NEXT, it is recommended to disable automatic aging while executing the GET_NEXT command. Table 214 • Fields in ANAGEFIL 7.4.1.4 Field Name Bit Access Description Default AGE_LOCKED 19 R/W Select entries to age. If cleared, unlocked entries will be aged and potentially removed. If set, locked entries will be aged but not removed. 0x0 PID_EN 18 R/W If set, only MAC table entries with a 0x0 destination index matching PID_VAL are aged. PID_VAL 17:13 R/W Destination index used in selective 0x00 aging. VID_EN 12 R/W If set, only MAC table entries with a 0x0 VID matching VID_VAL are aged. VID_VAL 11:0 R/W VID used in selective aging. 0x000 ANA:ANA:ANEVENTS Parent: ANA:ANA VMDS-10392 VSC7420-02, VSC7421-02, and VSC7422-02 Datasheet Revision 4.3 196 Registers Instances: 1 Table 215 • Fields in ANEVENTS Field Name Bit Access Description Default AUTOAGE 24 Sticky An AUTOAGE run was performed. 0x0 STORM_DROP 22 Sticky A frame was discarded, because it 0x0 exceeded the flooding storm limitations configured in STORMLIMIT. LEARN_DROP 21 Sticky A frame was discarded, because it 0x0 was subject to learning, and the DropMode flag was set in ADVLEARN. AGED_ENTRY 20 Sticky 0x0 An entry was removed at CPU Learn, or CPU requested an aging process. CPU_LEARN_FAILED 19 Sticky A learn operation failed due to hash table depletion. CPU-based learning only. AUTO_LEARN_FAILED 18 Sticky 0x0 A learn operation of incoming source MAC address failed due to hash table depletion. Hardware-based learning only. LEARN_REMOVE 17 Sticky An entry was removed when learning a new source MAC address. 0x0 AUTO_LEARNED 16 Sticky An entry was learned from an incoming frame. Hardware-based learning only. 0x0 AUTO_MOVED 15 Sticky A station was moved to another port. 0x0 CLASSIFIED_DROP 13 Sticky A frame was not forwarded due to 0x0 classification (such as BPDUs). CLASSIFIED_COPY 12 Sticky A frame was copied to the CPU due to classification. VLAN_DISCARD 11 Sticky A frame was discarded due to lack 0x0 of VLAN membership on source port. FWD_DISCARD 10 Sticky A frame was discarded due to 0x0 missing forwarding state on source port. MULTICAST_FLOOD 9 Sticky A frame was flooded with multicast 0x0 flooding mask. UNICAST_FLOOD 8 Sticky A frame was flooded with unicast flooding mask. DEST_KNOWN 7 Sticky A frame was forwarded with known 0x0 destination MAC address. 0x0 0x0 0x0 VMDS-10392 VSC7420-02, VSC7421-02, and VSC7422-02 Datasheet Revision 4.3 197 Registers Table 215 • Fields in ANEVENTS (continued) 7.4.1.5 Field Name Bit Access Description Default BUCKET3_MATCH 6 Sticky A destination was found in hash table bucket 3. 0x0 BUCKET2_MATCH 5 Sticky A destination was found in hash table bucket 2. 0x0 BUCKET1_MATCH 4 Sticky A destination was found in hash table bucket 1. 0x0 BUCKET0_MATCH 3 Sticky A destination was found in hash table bucket 0. 0x0 CPU_OPERATION 2 Sticky A CPU-initiated operation on the MAC or VLAN table was processed. Default is 1 due to auto-initialization of the MAC and VLAN table. 0x1 DMAC_LOOKUP 1 Sticky A destination address was looked up in the MAC table. 0x0 SMAC_LOOKUP 0 Sticky A source address was looked up in 0x0 the MAC table. ANA:ANA:STORMLIMIT_BURST Parent: ANA:ANA Instances: 1 Table 216 • Fields in STORMLIMIT_BURST 7.4.1.6 Field Name Bit Access Description Default STORM_BURST 3:0 R/W 0x0 Allowed number of frames in a burst is 2**STORM_BURST. The maximum allowed burst is 4096 frames, which corresponds to STORM_BURST = 12. The STORM_BURST is common for all storm policers. ANA:ANA:STORMLIMIT_CFG Parent: ANA:ANA Instances: 4 0: UC storm policer 1: BC storm policer 2: MC policer 3: Learn policer VMDS-10392 VSC7420-02, VSC7421-02, and VSC7422-02 Datasheet Revision 4.3 198 Registers Table 217 • Fields in STORMLIMIT_CFG 7.4.1.7 Field Name Bit Access Description Default STORM_RATE 6:3 R/W 0x0 Allowed rate of storm policer is 2**STORM_UNIT frames per second or kiloframes per second. See STORM_UNIT. The maximum allowed rate is 1024 kiloframes per second, which corresponds to STORM_RATE = 10 with STORM_UNIT set to 0. STORM_UNIT 2 R/W If set, the base unit for the storm policer is 0x0 one frame per second. If cleared, the base unit is one kiloframe per second. STORM_MODE 1:0 R/W Mode of operation for storm policer. 0: Disabled. 1: Police CPU destination only. 2: Police front port destinations only. 3: Police both CPU and front port destinations. 0x0 ANA:ANA:ISOLATED_PORTS Parent: ANA:ANA Instances: 1 Table 218 • Fields in ISOLATED_PORTS Field Name Bit Access Description Default ISOL_PORTS 26:0 R/W 0x7FFFFFF This mask is used in private VLANs applications. Promiscuous and community ports must be set and isolated ports must be cleared. For frames classified to a private VLAN (see the VLAN_PRIV_VLAN field in VLAN table), the resulting VLAN mask is calculated as follows: - Frames received on a promiscuous port use the VLAN mask directly. - Frames received on a community port use the VLAN mask AND'ed with the ISOL_PORTS. - Frames received on a isolated port use the VLAN mask AND'ed with the COMM_PORTS AND'ed with the ISOL_PORTS. For frames classified to a non-private VLAN, this mask is not used. VMDS-10392 VSC7420-02, VSC7421-02, and VSC7422-02 Datasheet Revision 4.3 199 Registers 7.4.1.8 ANA:ANA:COMMUNITY_PORTS Parent: ANA:ANA Instances: 1 Table 219 • Fields in COMMUNITY_PORTS Field Name Bit Access Description COMM_PORTS 26:0 R/W 0x7FFFFFF This mask is used in private VLANs applications. Promiscuous and isolated ports must be set and community ports must be cleared. Default See ISOLATED_PORTS.ISOL_PORTS for details. 7.4.1.9 ANA:ANA:AUTOAGE Parent: ANA:ANA Instances: 1 Table 220 • Fields in AUTOAGE Field Name Bit Access Description AGE_FAST 21 R/W Sets the unit of PERIOD to 8.2 us. 0x0 PERIOD must be a minimum of 3 when using the FAST option. AGE_PERIOD 20:1 R/W 0x00000 Time in seconds between automatic aging of a MAC table entry. Setting AGE_PERIOD to zero effectively disables automatic aging. An inactive unlocked MAC table entry is aged after 2*AGE_PERIOD. AUTOAGE_LOCKED 0 R/W Also set the AGED_FLAG bit on locked entries. They will not be removed. 0x0 7.4.1.10 Default ANA:ANA:MACTOPTIONS Parent: ANA:ANA Instances: 1 Table 221 • Fields in MACTOPTIONS Field Name Bit Access Description Default REDUCED_TABLE 1 R/W When set, the MAC table will be reduced 256 entries (64 hash-chains of 4) 0x0 VMDS-10392 VSC7420-02, VSC7421-02, and VSC7422-02 Datasheet Revision 4.3 200 Registers Table 221 • Fields in MACTOPTIONS (continued) Field Name Bit Access Description SHADOW 0 R/W 0x0 Enable MAC table shadow registers. The SHADOW bit affects the behavior of the READ command in MACACCESS.MAC_TABLE_CMD : With the shadow bit set, reading bucket 0 causes the remaining 3 buckets in the row to be stored in "shadow registers". Following read accesses to bucket 1-3 return the content of the shadow registers. This is useful when reading a MAC table, which can change while being read. 7.4.1.11 Default ANA:ANA:LEARNDISC Parent: ANA:ANA Instances: 1 The total number of MAC table entries that have been or would have been learned, but have been discarded due to a lack of storage space. Table 222 • Fields in LEARNDISC Field Name Bit Access Description Default LEARNDISC 31:0 R/W Number of discarded learn requests due to MAC table overflow (collisions or MAC table entry limits). 0x00000000 Default 7.4.1.12 ANA:ANA:AGENCTRL Parent: ANA:ANA Instances: 1 Table 223 • Fields in AGENCTRL Field Name Bit Access Description FID_MASK 23:12 R/W 0x000 Mask used to enable shared learning among multiple VLANs. The FID value used in learning and MAC table lookup is calculated as: FID = VID and (not FID_MASK) By default, FID_MASK is set to all-zeros, corresponding to independent VLAN learning. In this case FID becomes identical to VID. VMDS-10392 VSC7420-02, VSC7421-02, and VSC7422-02 Datasheet Revision 4.3 201 Registers Table 223 • Fields in AGENCTRL (continued) Field Name Bit Access Description Default IGNORE_DMAC_FLAGS 11 R/W Do not react to flags found in the DMAC entry or the corresponding flags for flooded frames (FLOOD_IGNORE_VLAN). 0x0 IGNORE_SMAC_FLAGS 10 R/W Do not react to flags found in the SMAC entry. Note, the IGNORE_VLAN flag is not checked for SMAC entries. 0x0 FLOOD_SPECIAL 9 R/W Flood frames using the lowest 27 bits of DMAC as destination port mask. This is only added for testing purposes. 0x0 FLOOD_IGNORE_VLAN 8 R/W VLAN mask is not applied to flooded frames. 0x0 MIRROR_CPU 7 R/W Frames destined for the CPU extraction queues are also forwarded to the port set configured in MIRRORPORTS. 0x0 LEARN_CPU_COPY 6 R/W If set, auto-learned stations get the 0x0 CPU_COPY flag set in the MAC table entry. LEARN_SRC_KILL 5 R/W If set, auto-learned stations get the 0x0 SRC_KILL flag set in the MAC table entry. LEARN_IGNORE_VLAN 4 R/W If set, auto-learned stations get the 0x0 IGNORE_VLAN flag set in the MAC table entry. CPU_CPU_KILL_ENA 3 R/W If set, CPU injected frames are never sent back to the CPU. 0x1 RESERVED 2 R/W Must be set to its default. 0x1 RESERVED 1 R/W Must be set to its default. 0x1 RESERVED 0 R/W Must be set to its default. 0x1 Default 7.4.1.13 ANA:ANA:MIRRORPORTS Parent: ANA:ANA Instances: 1 Table 224 • Fields in MIRRORPORTS Field Name Bit Access Description MIRRORPORTS 26:0 R/W 0x0000000 Ports set in this mask receive a mirror copy. If CPU is included in mask (bit 26 set), then the frame is copied to CPU extraction queue CPUQ_CFG.CPUQ_MIRROR. VMDS-10392 VSC7420-02, VSC7421-02, and VSC7422-02 Datasheet Revision 4.3 202 Registers 7.4.1.14 ANA:ANA:EMIRRORPORTS Parent: ANA:ANA Instances: 1 Table 225 • Fields in EMIRRORPORTS Field Name Bit Access Description EMIRRORPORTS 26:0 R/W Frames forwarded to ports in this 0x0000000 mask are mirrored to the port set configured in MIRRORPORTS (i.e. egress port mirroring). 7.4.1.15 Default ANA:ANA:FLOODING Parent: ANA:ANA Instances: 1 Table 226 • Fields in FLOODING Field Name Bit Access Description Default FLD_UNICAST 17:12 R/W Set the PGID mask to use when flooding unknown unicast frames. 0x3F FLD_BROADCAST 11:6 R/W Set the PGID mask to use when flooding unknown broadcast frames. 0x3F FLD_MULTICAST 5:0 R/W Set the PGID mask to use when 0x3F flooding unknown multicast frames (except IP multicasts). 7.4.1.16 ANA:ANA:FLOODING_IPMC Parent: ANA:ANA Instances: 1 Table 227 • Fields in FLOODING_IPMC Field Name Bit Access Description Default FLD_MC4_CTRL 23:18 R/W Set the PGID mask to use when flooding unknown IPv4 Multicast Control frames. 0x3F FLD_MC4_DATA 17:12 R/W Set the PGID mask to use when flooding unknown IPv4 Multicast Data frames. 0x3F FLD_MC6_CTRL 11:6 R/W Set the PGID mask to use when flooding unknown IPv6 Multicast Control frames. 0x3F FLD_MC6_DATA 5:0 R/W Set the PGID mask to use when flooding unknown IPv6 Multicast Data frames. 0x3F VMDS-10392 VSC7420-02, VSC7421-02, and VSC7422-02 Datasheet Revision 4.3 203 Registers 7.4.1.17 ANA:ANA:SFLOW_CFG Parent: ANA:ANA Instances: 27 Table 228 • Fields in SFLOW_CFG 7.4.2 Field Name Bit Access Description SF_RATE 13:2 R/W 0x000 Probability of a frame being SFLOW sampled. Unit is 1/4096. A value of 0 makes 1/4096 of the candidates being forwarded to the SFLOW CPU extraction queue. A values of 4095 makes all candidates being forwarded. Default SF_SAMPLE_RX 1 R/W Enable SFLOW sampling of frames received on this port. 0x0 SF_SAMPLE_TX 0 R/W Enable SFLOW sampling of frames transmitted on this port. 0x0 ANA:ANA_TABLES Parent: ANA Instances: 1 Table 229 • Registers in ANA_TABLES 7.4.2.1 Register Name Offset within Register Group Instances and Address Spacing Description Details ANMOVED 0x000001AC 1 Station Move Logger Page 204 MACHDATA 0x000001B0 1 MAC Address High Page 205 MACLDATA 0x000001B4 1 MAC Address Low Page 205 MACACCESS 0x000001B8 1 MAC Table Command Page 205 MACTINDX 0x000001BC 1 MAC Table Index Page 207 VLANACCESS 0x000001C0 1 VLAN Table Command Page 208 VLANTIDX 0x000001C4 1 VLAN Table Index Page 209 PGID 0x00000000 107 0x00000004 Port Group Identifiers Page 209 ENTRYLIM 0x00000200 27 0x00000004 MAC Table Entry Limits Page 210 ANA:ANA_TABLES:ANMOVED Parent: ANA:ANA_TABLES Instances: 1 VMDS-10392 VSC7420-02, VSC7421-02, and VSC7422-02 Datasheet Revision 4.3 204 Registers Table 230 • Fields in ANMOVED Field Name Bit Access Description ANMOVED 26:0 R/W 0x0000000 Sticky bit set when a station has been learned on a port while already learned on another port (i.e. port move). The register is cleared by writing 1 to the bits to be cleared. This mask can be used to detect topology problems in the network, where stations are learned on multiple ports repeatedly. If some bits in this register get asserted repeatedly, the ports can be shut down, or management warnings can be issued. 7.4.2.2 Default ANA:ANA_TABLES:MACHDATA Parent: ANA:ANA_TABLES Instances: 1 Table 231 • Fields in MACHDATA 7.4.2.3 Field Name Bit Access Description Default VID 27:16 R/W VID used in MAC table operations 0x000 through MACACCESS. For read operations, the VID value is returned in this field. MACHDATA 15:0 R/W Most significant 16 MAC address 0x0000 bits used in MAC table operations through MACACCESS. ANA:ANA_TABLES:MACLDATA Parent: ANA:ANA_TABLES Instances: 1 Table 232 • Fields in MACLDATA 7.4.2.4 Field Name Bit Access Description Default MACLDATA 31:0 R/W Lower 32 MAC address bits used in MAC table operations through MACACCESS. 0x00000000 ANA:ANA_TABLES:MACACCESS Parent: ANA:ANA_TABLES Instances: 1 This register is used for updating or reading the MAC table from the CPU. VMDS-10392 VSC7420-02, VSC7421-02, and VSC7422-02 Datasheet Revision 4.3 205 Registers The command (MAC_TABLE_CMD) selects between different operations and uses the following encoding: 000 - IDLE: The previous operation has completed. 001 - LEARN: Insert/learn new entry in MAC table. Position given by (MAC, VID) in MACHDATA and MACLDATA. 010 - FORGET: Delete/unlearn entry given by (MAC, VID) in MACHDATA and MACLDATA. Both locked and unlocked entries are deleted. 011 - AGE: Start an age scan on the MAC table. 100 - GET_NEXT: Get the smallest entry in the MAC table numerically larger than the (MAC, VID) specified in MACHDATA and MACLDATA. The VID and MAC are evaluated as a 60-bit number with the VID being most significant. 101 - INIT: Table is initialized (completely cleared). 110 - READ: The READ command is divided into two modes: Direct mode and indirect mode. Direct mode (read): With MACACCESS.VALID cleared, the entry pointed to by MACTINDX.INDEX (row) and MACTINDX.BUCKET (column) is read. Indirect mode (lookup): With MACACCESS.VALID set, the entry pointed to by (MAC, VID) in the MACHDATA and MACLDATA is read. 111 - WRITE Write entry. Address of the entry is specified in MACTINDX.INDEX (row) and MACTINDX.BUCKET (column). An existing entry (locked or unlocked) is overwritten. The MAC_TABLE_CMD must be IDLE before a new command can be issued. The AGE and CLEAR commands run for approximately 50 us. The other commands execute immediately. VMDS-10392 VSC7420-02, VSC7421-02, and VSC7422-02 Datasheet Revision 4.3 206 Registers The flags IGNORE_VLAN and MAC_CPU_COPY are ignored for DMAC lookup if AGENCTRL.IGNORE_DMAC_FLAGS is set. The flags SRC_KILL and MAC_CPU_COPY are ignored for SMAC lookup if AGENCTRL.IGNORE_SMAC_FLAGS is set. Table 233 • Fields in MACACCESS 7.4.2.5 Field Name Bit Access Description Default IP6_MASK 18:16 R/W Bits 24:22 in the destination port mask for IPv6 entries. 0x0 MAC_CPU_COPY 15 R/W 0x0 Frames matching this entry are copied to the CPU extraction queue CPUQ_CFG.CPUQ_MAC. Applies to both SMAC and DMAC lookup. SRC_KILL 14 R/W 0x0 Frames matching this entry are discarded. Applies only to the SMAC lookup. For discarding frames based on the DMAC lookup a NULL PGID mask can be used. IGNORE_VLAN 13 R/W The VLAN mask is ignored for this 0x0 destination. Applies only to DMAC lookup. AGED_FLAG 12 R/W This flag is set on every aging run. 0x0 Entry is removed if flag is already set. The flag is cleared when the entry is target for a SMAC lookup. Locked entries will not be removed. Bit is for IPv6 Multicast used for port 25. VALID 11 R/W Entry is valid. ENTRY_TYPE 10:9 R/W 0x0 Type of entry: 0: Normal entry eligible for aging 1: Locked entry. Entry will not be removed by aging 2: IPv4 Multicast entry. Full portset in mac record 3: IPv6 Multicast entry. Full portset in mac record DEST_IDX 8:3 R/W 0x00 Index for the destination masks table (PGID). For unicasts, this is a number from 0-EXB_PORT_CNT_MINUS_ONE . MAC_TABLE_CMD 2:0 R/W MAC Table Command. See below. 0x0 0x0 ANA:ANA_TABLES:MACTINDX Parent: ANA:ANA_TABLES Instances: 1 VMDS-10392 VSC7420-02, VSC7421-02, and VSC7422-02 Datasheet Revision 4.3 207 Registers Table 234 • Fields in MACTINDX 7.4.2.6 Field Name Bit Access Description Default BUCKET 12:11 R/W Selects one of the four MAC table 0x0 entries in a row. The row is addressed with the INDEX field. M_INDEX 10:0 R/W The index selects one of the 2048 0x000 MAC table rows. Within a row the entry is addressed by the BUCKET field ANA:ANA_TABLES:VLANACCESS Parent: ANA:ANA_TABLES Instances: 1 The VLAN_TBL_CMD field of this register is used for updating and reading the VLAN table. The command (VLAN_TBL_CMD) selects between different operations and uses the following encoding: 00 - IDLE: The previous operation has completed. 01 - READ: The VLAN table entry set in VLANTIDX.INDEX is returned in VLANACCESS.VLAN_PORT_MASK and the VLAN flags in VLANTIDX. 10 - WRITE: The VLAN table entry pointed to by VLANTIDX.INDEX is updated with VLANACCESS.VLAN_PORT_MASK and the VLAN flags in VLANTIDX. 11 - INIT: The VLAN table is initialized to default values (all ports are members of all VLANs). The VLAN_TBL_CMD must be IDLE before a new command can be issued. The INIT command run for approximately 50 us whereas the other commands execute immediately. When an operation has completed, VLAN_TBL_CMD changes to IDLE. Table 235 • Fields in VLANACCESS Field Name Bit Access Description Default VLAN_PORT_MASK 28:2 R/W Frames classified to this VLAN can 0x3FFFFFF only be sent to ports in this mask. Note that the CPU port module is always member of all VLANs and its VLAN membership can therefore not be configured through this mask. VMDS-10392 VSC7420-02, VSC7421-02, and VSC7422-02 Datasheet Revision 4.3 208 Registers Table 235 • Fields in VLANACCESS (continued) 7.4.2.7 Field Name Bit Access Description Default VLAN_TBL_CMD 1:0 R/W VLAN Table Command. 0x0 ANA:ANA_TABLES:VLANTIDX Parent: ANA:ANA_TABLES Instances: 1 Table 236 • Fields in VLANTIDX 7.4.2.8 Field Name Bit Access Description Default VLAN_PRIV_VLAN 15 R/W If set, a VLAN is a private VLAN. See PRIV_VLAN_MASK for details. 0x0 VLAN_LEARN_DISABLE D 14 R/W Disable learning for this VLAN. 0x0 VLAN_MIRROR 13 R/W If set, all frames classified to this VLAN are mirrored to the port set configured in MIRRORPORTS. 0x0 VLAN_SRC_CHK 12 R/W If set, VLAN ingress filtering is enabled for this VLAN. If set, a frame's ingress port must be member of the frame's VLAN, otherwise the frame is discarded. 0x0 V_INDEX 11:0 R/W 0x000 Index used to select VLAN table entry for read/write operations (see VLANACCESS). This value equals the VID. ANA:ANA_TABLES:PGID Parent: ANA:ANA_TABLES Instances: 107 Three port masks are applied to all frames, allowing transmission to a port if the corresponding bit is set in all masks. 0-63: A mask is applied based on destination analysis 64-79: A mask is applied based on aggregation analysis 80-106: A mask is applied based on source port analysis Destination analysis: There are 64 destination masks in total. By default, the first 26 port masks only have the bit corresponding to their port number set. These masks should not be changed, except for aggregation. The remaining destination masks are set to 0 by default and are available for use for Layer-2 multicasts and flooding (See FLOODING and FLOODING_IPMC). VMDS-10392 VSC7420-02, VSC7421-02, and VSC7422-02 Datasheet Revision 4.3 209 Registers Aggregation analysis: The aggregation port masks are used to select only one port within each aggregation group. These 16 masks must be setup to select only one port in each aggregated port group. For ports, which are not part of any aggregation group, the corresponding bits in all 16 masks must be set. I.e. if no aggregation is configured, all masks must be set to all-ones. The aggregation mask used for the forwarding of a given frame is selected by the frame's aggregation code (see AGGRCTRL). Source port analysis: The source port masks are used to prevent frames from being looped back to the ports on which they were received, and must be updated according to the aggregation configuration. A frame that is received on port n, uses mask 80+n as a mask to filter out destination ports to avoid loopback, or to facilitate port grouping (port-based VLANs). The default values are that all bits are set except for the index number. Table 237 • Fields in PGID 7.4.2.9 Field Name Bit Access Description Default PGID 26:0 R/W When a mask is chosen, bit N must be set for the frame to be transmitted on port N. 0x7FFFFFF CPUQ_DST_PGID 29:27 R/W CPU extraction queue used when 0x0 CPU port is enabled in PGID. Only applicable for the destination analysis. ANA:ANA_TABLES:ENTRYLIM Parent: ANA:ANA_TABLES Instances: 27 Table 238 • Fields in ENTRYLIM Field Name Bit Access Description Default ENTRYLIM 17:14 R/W Maximum number of unlocked entries in the MAC table learned on this port. Locked entries and IPMC entries do not obey this limit. Both auto-learned and unlocked CPU-learned entries obey this limit. 0: 1 entry 1: 2 entries n: 2**n entries >12: 8192 entries 0xD VMDS-10392 VSC7420-02, VSC7421-02, and VSC7422-02 Datasheet Revision 4.3 210 Registers Table 238 • Fields in ENTRYLIM (continued) 7.4.3 Field Name Bit Access Description Default ENTRYSTAT 13:0 R/W Current number of unlocked MAC table entries learned on this port. 0x0000 ANA:PORT Parent: ANA Instances: 27 Table 239 • Registers in PORT 7.4.3.1 Register Name Offset within Register Group Instances and Address Spacing Description Details VLAN_CFG 0x00000000 1 Port VLAN configuration Page 211 DROP_CFG 0x00000004 1 VLAN acceptance filtering Page 212 QOS_CFG 0x00000008 1 QoS and DSCP configuration Page 213 QOS_PCP_DEI_MAP_ 0x00000010 CFG 16 0x00000004 Mapping of DEI and PCP to Page 213 QoS class CPU_FWD_CFG 0x00000050 1 CPU forwarding of special protocols Page 214 CPU_FWD_BPDU_CF G 0x00000054 1 CPU forwarding of BPDU frames Page 214 CPU_FWD_GARP_CF G 0x00000058 1 CPU forwarding of GARP frames Page 215 CPU_FWD_CCM_CFG 0x0000005C 1 CPU forwarding of CCM/Link trace frames Page 215 PORT_CFG 0x00000060 1 Special port configuration Page 215 POL_CFG 0x00000064 1 Policer selection Page 217 ANA:PORT:VLAN_CFG Parent: ANA:PORT Instances: 1 Table 240 • Fields in VLAN_CFG Field Name Bit Access Description Default VLAN_AWARE_ENA 20 R/W Enable VLAN awareness. If set, Q-tag headers are processed during the basic VLAN classification. If cleared, Q-tag headers are ignored during the basic VLAN classification. 0x0 VMDS-10392 VSC7420-02, VSC7421-02, and VSC7422-02 Datasheet Revision 4.3 211 Registers Table 240 • Fields in VLAN_CFG (continued) 7.4.3.2 Field Name Bit Access Description Default VLAN_POP_CNT 19:18 R/W Number of tag headers to remove 0x0 from ingress frame. 0: Keep all tags. 1: Pop up to 1 tag (outer tag if available). 2: Pop up to 2 tags (outer and inner tag if available). 3: Reserved. VLAN_INNER_TAG_ENA 17 R/W Set if the inner Q-tag must be used 0x0 instead of the outer Q-tag. If the received frame is single tagged, the outer tag is used. This bit influences the VLAN acceptance filter (DROP_CFG), the basic VLAN classification (VLAN_CFG), and the basic QoS classification (QOS_CFG). VLAN_TAG_TYPE 16 R/W Tag Protocol Identifier type for port-based VLAN. 0: C-tag (EtherType = 0x8100) 1: S-tag (EtherType = 0x88A8 or configurable value (VLAN_ETYPE_CFG)) 0x0 VLAN_DEI 15 R/W DEI value for port-based VLAN. 0x0 VLAN_PCP 14:12 R/W PCP value for port-based VLAN. 0x0 VLAN_VID 11:0 R/W VID value for port-based VLAN. 0x000 Access Description Default DROP_UNTAGGED_ENA 6 R/W Drop untagged frames. 0x0 DROP_S_TAGGED_ENA 5 R/W Drop S-tagged frames (VID different from 0 and EtherType = 0x88A8 or configurable value (VLAN_ETYPE_CFG)). 0x0 DROP_C_TAGGED_ENA 4 R/W Drop C-tagged frames (VID different from 0 and EtherType = 0x8100). 0x0 DROP_PRIO_S_TAGGED 3 _ENA R/W Drop S-tagged frames (VID=0 and 0x0 EtherType = 0x88A8 or configurable value (VLAN_ETYPE_CFG)). ANA:PORT:DROP_CFG Parent: ANA:PORT Instances: 1 Table 241 • Fields in DROP_CFG Field Name Bit VMDS-10392 VSC7420-02, VSC7421-02, and VSC7422-02 Datasheet Revision 4.3 212 Registers Table 241 • Fields in DROP_CFG (continued) Field Name 7.4.3.3 Bit Access Description Default DROP_PRIO_C_TAGGED 2 _ENA R/W Drop priority C-tagged frames 0x0 (VID=0 and EtherType = 0x8100). DROP_NULL_MAC_ENA 1 R/W 0x0 Drop frames with source or destination MAC address equal to 0x000000000000. DROP_MC_SMAC_ENA 0 R/W Drop frames with multicast source 0x0 MAC address. ANA:PORT:QOS_CFG Parent: ANA:PORT Instances: 1 Table 242 • Fields in QOS_CFG 7.4.3.4 Field Name Bit Access Description Default QOS_DEFAULT_VAL 7:5 R/W Default QoS class. 0x0 QOS_DSCP_ENA 4 R/W If set, the QoS class can be based 0x0 on DSCP values. QOS_PCP_ENA 3 R/W If set, the QoS class can be based 0x0 on PCP and DEI values for tagged frames. DSCP_TRANSLATE_ENA 2 R/W 0x0 Set if the DSCP value must be translated before using the DSCP value. If set, the translated DSCP value is given from DSCP_CFG[DSCP].DSCP_TRAN SLATE_VAL. DSCP_REWR_CFG R/W Configure which DSCP values to 0x0 rewrite based on QoS class. If the DSCP value is to be rewritten, then the new DSCP = DSCP_REWR_CFG[QoS class].DSCP_QOS_REWR_VAL. 0: Rewrite none. 1: Rewrite if DSCP=0 2: Rewrite for selected values configured in DSCP_CFG[DSCP].DSCP_REWR _ENA. 3: Rewrite all. 1:0 ANA:PORT:QOS_PCP_DEI_MAP_CFG Parent: ANA:PORT Instances: 16 VMDS-10392 VSC7420-02, VSC7421-02, and VSC7422-02 Datasheet Revision 4.3 213 Registers Table 243 • Fields in QOS_PCP_DEI_MAP_CFG 7.4.3.5 Field Name Bit Access Description Default QOS_PCP_DEI_VAL 2:0 R/W 0x0 Map the frame's PCP and DEI values to a QoS class. QoS class = QOS_PCP_DEI_MAP_CFG[index] .QOS_PCP_DEI_VAL, where index = 8*DEI + PCP. Only applicable to tagged frames. The use of Inner or outer tag can be selected using VLAN_CFG.VLAN_INNER_TAG_ ENA. ANA:PORT:CPU_FWD_CFG Parent: ANA:PORT Instances: 1 Table 244 • Fields in CPU_FWD_CFG 7.4.3.6 Field Name Bit Access Description Default CPU_MLD_REDIR_ENA 4 R/W If set, MLD frames are redirected to the CPU. 0x0 CPU_IGMP_REDIR_ENA 3 R/W If set, IGMP frames are redirected 0x0 to the CPU. CPU_IPMC_CTRL_COPY 2 _ENA R/W If set, IPv4 multicast control frames 0x0 (destination IP address in the range 224.0.0.x) are copied to the CPU. CPU_SRC_COPY_ENA 1 R/W 0x0 If set, all frames received on this port are copied to the CPU extraction queue given by CPUQ_CFG.CPUQ_SRC_COPY. CPU_ALLBRIDGE_REDIR 0 _ENA R/W 0x0 If set, All LANs bridge management group frames (DMAC = 01-80-C2-00-00-10) are redirected to the CPU. ANA:PORT:CPU_FWD_BPDU_CFG Parent: ANA:PORT Instances: 1 VMDS-10392 VSC7420-02, VSC7421-02, and VSC7422-02 Datasheet Revision 4.3 214 Registers Table 245 • Fields in CPU_FWD_BPDU_CFG 7.4.3.7 Field Name Bit Access Description Default BPDU_REDIR_ENA 15:0 R/W If bit x is set, BPDU frame (DMAC 0x0000 = 01-80-C2-00-00-0x) is redirected to the CPU. ANA:PORT:CPU_FWD_GARP_CFG Parent: ANA:PORT Instances: 1 Table 246 • Fields in CPU_FWD_GARP_CFG 7.4.3.8 Field Name Bit Access Description Default GARP_REDIR_ENA 15:0 R/W If bit x is set, GARP frame (DMAC 0x0000 = 01-80-C2-00-00-2x) is redirected to the CPU. ANA:PORT:CPU_FWD_CCM_CFG Parent: ANA:PORT Instances: 1 Table 247 • Fields in CPU_FWD_CCM_CFG 7.4.3.9 Field Name Bit Access Description Default CCM_REDIR_ENA 15:0 R/W If bit x is set, CCM/Link trace frame 0x0000 (DMAC = 01-80-C2-00-00-3x) is redirected to the CPU. ANA:PORT:PORT_CFG Parent: ANA:PORT Instances: 1 Table 248 • Fields in PORT_CFG Field Name Bit Access Description Default SRC_MIRROR_ENA 14 R/W 0x0 If set, all frames received on this port are mirrored to the port set configured in MIRRORPORTS (ie. ingress mirroring). For egress mirroring, see EMIRRORPORTS. VMDS-10392 VSC7420-02, VSC7421-02, and VSC7422-02 Datasheet Revision 4.3 215 Registers Table 248 • Fields in PORT_CFG (continued) Field Name Bit Access Description Default LIMIT_DROP 13 R/W If set, learn frames on an ingress 0x0 port, which has exceeded the maximum number of MAC table entries are discarded. Forwarding to CPU is still allowed. Note that if LEARN_ENA is cleared, then the LIMIT_DROP is ignored. LIMIT_CPU 12 R/W If set, learn frames on an ingress port, which has exceeded the maximum number of MAC table entries are copied to the CPU extraction queue specified in CPUQ_CFG.CPUQ_LRN. Note that if LEARN_ENA is cleared, then the LIMIT_CPU is ignored. LOCKED_PORTMOVE_D 11 ROP R/W If set, incoming frames triggering a 0x0 port move for a locked entry in the MAC table received on this port are discarded. Forwarding to CPU is still allowed. Note that if LEARN_ENA is cleared, then the LOCKED_PORTMOVE_DROP is ignored. LOCKED_PORTMOVE_C 10 PU R/W If set, incoming frames triggering a 0x0 port move for a locked MAC table entry received on this port are copied to the CPU extraction queue specified in CPUQ_CFG.CPUQ_LOCKED_PO RTMOVE. Note that if LEARN_ENA is cleared, then the LOCKED_PORTMOVE_CPU is ignored. LEARNDROP 9 R/W If set, incoming learn frames received on this port are discarded. Forwarding to CPU is still allowed. Note that if LEARN_ENA is cleared, then the LEARNDROP is ignored. LEARNCPU 8 R/W 0x0 If set, incoming learn frames received on this port are copied to the CPU extraction queue specified in AGENCTRL.CPUQ_LRN. Note that if LEARN_ENA is cleared, then the LEARNCPU is ignored. LEARNAUTO 7 R/W If set, incoming learn frames 0x1 received on this port are auto learned. Note that if LEARN_ENA is cleared, then the LEARNAUTO is ignored. 0x0 0x0 VMDS-10392 VSC7420-02, VSC7421-02, and VSC7422-02 Datasheet Revision 4.3 216 Registers Table 248 • Fields in PORT_CFG (continued) Field Name Bit Access Description Default LEARN_ENA 6 R/W Enable learning for frames received on this port. If cleared, learning is skipped and any configuration settings in LEARNAUTO, LEARNCPU, LEARNDROP is ignored. 0x1 RECV_ENA 5 R/W Enable reception of frames. If cleared, all incoming frames on this port are discarded by the analyzer. 0x1 PORTID_VAL 4:0 R/W Logical port number for front port. 0x00 If port is not a member of a LLAG, then PORTID must be set to the physical port number. If port is a member of a LLAG, then PORTID must be set to the common PORTID_VAL used for all member ports of the LLAG. 7.4.3.10 ANA:PORT:POL_CFG Parent: ANA:PORT Instances: 1 Table 249 • Fields in POL_CFG Field Name Bit Access Description Default POL_CPU_REDIR_8021 19 R/W If set, frames with a DMAC = IEEE 0x0 reserved addresses (BPDU, GARP, CCM, ALLBRIGDE), which are redirected to the CPU are not policed by any policers. The frames are still counted in the policer buckets. POL_CPU_REDIR_IP 18 R/W 0x0 If set, IGMP and MLD frames, which are redirected to the CPU are not policed by any policers. The frames are still counted in the policers buckets. PORT_POL_ENA 17 R/W Enable port policing. Port policing on port P uses policer P. 0x0 QUEUE_POL_ENA 16:9 R/W Bitmask, where bit enables policing of frames classified to QoS class n on this port. Queue policing of QoS class Q on port P uses policer 32+P*8+Q. 0x00 VMDS-10392 VSC7420-02, VSC7421-02, and VSC7422-02 Datasheet Revision 4.3 217 Registers Table 249 • Fields in POL_CFG (continued) Field Name Bit Access Description Default POL_ORDER 8:0 R/W Each frame is checked against two 0x1FF policers: PORT(0) and QOS(1). In this register, a bit set will make updating of a policer be dependant on the result from another policer. Bit set means: Policer state is checked before policer is updated. Bit0: Port policer must be open in order to update port policer with frame Bit1: QoS policer must be open in order to update port policer with frame Bit2: Reserved Bit3: Port policer must be open in order to update QoS policer with frame Bit4: QoS policer must be open in order to update QoS policer with frame Bit5-8: Reserved 7.4.4 ANA:COMMON Parent: ANA Instances: 1 Table 250 • Registers in COMMON 7.4.4.1 Register Name Offset within Register Group Instances and Address Spacing Description Details AGGR_CFG 0x00000000 1 Aggregation code generation Page 218 CPUQ_CFG 0x00000004 1 CPU extraction queue configuration Page 219 CPUQ_8021_CFG 0x00000008 16 0x00000004 CPU extraction queue per address of BPDU, GARP, and CCM frames. Page 220 DSCP_CFG 0x00000048 64 0x00000004 DSCP configuration per DSCP value. Page 220 DSCP_REWR_CFG 0x00000148 8 0x00000004 DSCP rewrite values per QoS class Page 221 ANA:COMMON:AGGR_CFG Parent: ANA:COMMON Instances: 1 VMDS-10392 VSC7420-02, VSC7421-02, and VSC7422-02 Datasheet Revision 4.3 218 Registers Table 251 • Fields in AGGR_CFG 7.4.4.2 Field Name Bit Access Description Default AC_RND_ENA 6 R/W Use pseudo random number for aggregation code. Overrule other contributions. 0x0 AC_DMAC_ENA 5 R/W Use the lower 12 bits of the destination MAC address for aggregation code. 0x0 AC_SMAC_ENA 4 R/W Use the lower 12 bits of the source 0x0 MAC address for aggregation code. AC_IP6_FLOW_LBL_ENA 3 R/W Use the 20-bit IPv6 flow label for aggregation code. AC_IP6_TCPUDP_ENA 2 R/W Use least significant 8 bits of both 0x0 source port and destination port of IPv6 frames for aggregation code. AC_IP4_SIPDIP_ENA 1 R/W Use least significant 8 bits of both 0x0 source IP address and destination IP address of IPv4 frames for aggregation code. AC_IP4_TCPUDP_ENA 0 R/W Use least significant 8 bits of both 0x0 source port and destination port of IPv4 frames for aggregation code. 0x0 ANA:COMMON:CPUQ_CFG Parent: ANA:COMMON Instances: 1 Table 252 • Fields in CPUQ_CFG Field Name Bit Access Description Default CPUQ_MLD 29:27 R/W CPU extraction queue used for MLD frames. 0x0 CPUQ_IGMP 26:24 R/W CPU extraction queue used for IGMP frames. 0x0 CPUQ_IPMC_CTRL 23:21 R/W CPU extraction queue used for IPv4 multicast control frames. 0x0 CPUQ_ALLBRIDGE 20:18 R/W CPU extraction queue used for allbridge frames (DMAC = 01-80-C2-00-00-10). 0x0 CPUQ_LOCKED_PORTM 17:15 OVE R/W CPU extraction queue for frames 0x0 triggering a port move for a locked MAC table entry. CPUQ_SRC_COPY R/W CPU extraction queue for frames copied due to CPU_SRC_COPY_ENA 14:12 0x0 VMDS-10392 VSC7420-02, VSC7421-02, and VSC7422-02 Datasheet Revision 4.3 219 Registers Table 252 • Fields in CPUQ_CFG (continued) 7.4.4.3 Field Name Bit Access Description Default CPUQ_MAC_COPY 11:9 R/W CPU extraction queue for frames copied due to CPU_COPY return by MAC table lookup 0x0 CPUQ_LRN 8:6 R/W CPU extraction queue for frames copied due to learned or moved stations. 0x0 CPUQ_MIRROR 5:3 R/W CPU extraction queue for frames copied due to mirroring to the CPU. 0x0 CPUQ_SFLOW 2:0 R/W CPU extraction queue for frames copied due to SFLOW sampling. 0x0 ANA:COMMON:CPUQ_8021_CFG Parent: ANA:COMMON Instances: 16 Table 253 • Fields in CPUQ_8021_CFG 7.4.4.4 Field Name Bit Access Description Default CPUQ_BPDU_VAL 8:6 R/W CPU extraction queue used for BPDU frames. 0x0 CPUQ_GARP_VAL 5:3 R/W CPU extraction queue used for GARP frames. 0x0 CPUQ_CCM_VAL 2:0 R/W CPU extraction queue used for CCM/Link trace frames. 0x0 Default ANA:COMMON:DSCP_CFG Parent: ANA:COMMON Instances: 64 Table 254 • Fields in DSCP_CFG Field Name Bit Access Description QOS_DSCP_VAL 10:8 R/W Maps the frame's DSCP value to a 0x0 QoS class. This is enabled in QOS_CFG.QOS_DSCP_ENA. DSCP_TRANSLATE_VAL 7:2 R/W Translated DSCP value triggered if 0x00 DSCP translation is set for port (QOS_CFG[port].DSCP_TRANSL ATE_ENA) DSCP_TRUST_ENA R/W Must be set for a DSCP value if the 0x0 DSCP value is to be used for QoS classification. 1 VMDS-10392 VSC7420-02, VSC7421-02, and VSC7422-02 Datasheet Revision 4.3 220 Registers Table 254 • Fields in DSCP_CFG (continued) 7.4.4.5 Field Name Bit Access Description Default DSCP_REWR_ENA 0 R/W Set if the DSCP value is selected 0x0 to be rewritten. This is controlled in QOS_CFG.DSCP_REWR_CFG. ANA:COMMON:DSCP_REWR_CFG Parent: ANA:COMMON Instances: 8 Table 255 • Fields in DSCP_REWR_CFG Field Name Bit DSCP_QOS_REWR_VAL 5:0 7.5 Access Description Default R/W 0x00 Map the frame's QoS class to a DSCP value. DSCP = DSCP_REWR_CFG[QoS class].DSCP_QOS_REWR_VAL. This is controlled in QOS_CFG.DSCP_REWR_CFG and DSCP_CFG.DSCP_REWR_ENA. REW Table 256 • Register Groups in REW Offset within Register Group Name Target 7.5.1 Instances and Address Spacing Description Details PORT 0x00000000 28 0x00000080 Per port configurations for Rewriter Page 221 COMMON 0x00000E00 1 Common configurations for Page 224 Rewriter REW:PORT Parent: REW Instances: 28 Table 257 • Registers in PORT Register Name Offset within Register Group Instances and Address Spacing Description Details PORT_VLAN_CFG 0x00000000 1 Port VLAN configuration Page 222 TAG_CFG 0x00000004 1 Tagging configuration Page 222 PORT_CFG 0x00000008 1 Special port configuration Page 223 VMDS-10392 VSC7420-02, VSC7421-02, and VSC7422-02 Datasheet Revision 4.3 221 Registers Table 257 • Registers in PORT (continued) Register Name Offset within Register Group Instances and Address Spacing Description Details DSCP_CFG 0x0000000C 1 DSCP updates Page 223 8 0x00000004 Mapping of QoS class to PCP and DEI values. Page 224 PCP_DEI_QOS_MAP_ 0x00000010 CFG 7.5.1.1 REW:PORT:PORT_VLAN_CFG Parent: REW:PORT Instances: 1 Table 258 • Fields in PORT_VLAN_CFG 7.5.1.2 Field Name Bit Access Description Default PORT_TPID 31:16 R/W Tag Protocol Identifier for port. 0x0000 PORT_DEI 15 R/W DEI value for port. 0x0 PORT_PCP 14:12 R/W PCP value for port. 0x0 PORT_VID 11:0 R/W VID value for port. 0x001 Default REW:PORT:TAG_CFG Parent: REW:PORT Instances: 1 Table 259 • Fields in TAG_CFG Field Name Bit Access Description TAG_CFG 6:5 R/W 0x0 Enable VLAN port tagging. 0: Port tagging disabled. 1: Tag all frames, except when VID=PORT_VLAN_CFG.PORT_VI D or VID=0. 2: Tag all frames, except when VID=0. 3: Tag all frames. TAG_TPID_CFG 4:3 R/W Select TPID EtherType in port tag. 0x0 0: Use 0x8100. 1: Use 0x88A8. 2: Use custom value from PORT_VLAN_CFG.PORT_TPID. 3: Use PORT_VLAN_CFG.PORT_TPID, unless ingress tag was a C-tag (EtherType = 0x8100) VMDS-10392 VSC7420-02, VSC7421-02, and VSC7422-02 Datasheet Revision 4.3 222 Registers Table 259 • Fields in TAG_CFG (continued) 7.5.1.3 Field Name Bit Access Description Default TAG_QOS_CFG 1:0 R/W Select PCP/DEI fields in port tag. 0x0 0: Use classified PCP/DEI values. 1: Reserved. 2: Use PCP/DEI values from port VLAN tag in PORT_VLAN_CFG. 3: Use QoS class mapped to PCP/DEI values (PCP_DEI_QOS_MAP_CFG). REW:PORT:PORT_CFG Parent: REW:PORT Instances: 1 Table 260 • Fields in PORT_CFG 7.5.1.4 Field Name Bit Access Description Default IFH_INSERT_ENA 7 R/W Insert IFH into frame (mainly for CPU ports) 0x0 IFH_INSERT_MODE 6 R/W Select the position of IFH in the generated frames when IFH_INSERT_ENA is set 0: IFH written before DMAC. 1: IFH written after SMAC. 0x0 FCS_UPDATE_NONCPU_ 5:4 CFG R/W FCS update mode for frames not received on the CPU port. 0: Update FCS if frame data has changed 1: Never update FCS 2: Always update FCS 0x0 FCS_UPDATE_CPU_ENA 3 R/W If set, update FCS for all frames injected by the CPU. If cleared, never update the FCS. 0x1 FLUSH_ENA 2 R/W If set, all frames destined for the egress port are discarded. Note Flushing must be disabled on ports operating in half-duplex mode. 0x0 AGE_DIS 1 R/W Disable frame ageing for this egress port. Note Frame ageing must be disabled on ports operating in half-duplex mode. 0x0 REW:PORT:DSCP_CFG Parent: REW:PORT Instances: 1 VMDS-10392 VSC7420-02, VSC7421-02, and VSC7422-02 Datasheet Revision 4.3 223 Registers Table 261 • Fields in DSCP_CFG Field Name Bit Access Description Default DSCP_REWR_CFG 1:0 R/W Egress DSCP rewrite. 0x0 0: No update of DSCP value in frame. 1: Update with DSCP value from analyzer. 2: Update with DSCP value from analyzer remapped through DSCP_REMAP_CFG. 7.5.1.5 REW:PORT:PCP_DEI_QOS_MAP_CFG Parent: REW:PORT Instances: 8 Table 262 • Fields in PCP_DEI_QOS_MAP_CFG 7.5.2 Field Name Bit Access Description Default DEI_QOS_VAL 3 R/W Map the frame's QoS class to a DEI value. DEI = PCP_DEI_QOS_MAP_CFG[QoS class].DEI_QOS_VAL. This must be enabled in VLAN_CFG.QOS_CFG. 0x0 PCP_QOS_VAL 2:0 R/W Map the frame's QoS class to a PCP value. PCP = PCP_DEI_QOS_MAP_CFG[QoS class].PCP_QOS_VAL. This must be enabled in VLAN_CFG.QOS_CFG. 0x0 REW:COMMON Parent: REW Instances: 1 Table 263 • Registers in COMMON 7.5.2.1 Register Name Offset within Register Group Instances and Address Spacing Description DSCP_REMAP_CFG 0x00000100 64 0x00000004 Remap table of DSCP values. Details Page 224 REW:COMMON:DSCP_REMAP_CFG Parent: REW:COMMON Instances: 64 VMDS-10392 VSC7420-02, VSC7421-02, and VSC7422-02 Datasheet Revision 4.3 224 Registers Table 264 • Fields in DSCP_REMAP_CFG 7.6 Field Name Bit Access Description Default DSCP_REMAP_VAL 5:0 R/W One to one DSCP remapping table 0x00 common for all ports. This table is used when DSCP_CFG.DSCP_REWR_ENA= 2. DEVCPU_GCB Table 265 • Register Groups in DEVCPU_GCB 7.6.1 Offset within Register Group Name Target Instances and Address Spacing Description Details CHIP_REGS 0x00000000 1 Page 225 SW_REGS 0x00000014 1 VCORE_ACCESS 0x00000054 1 Page 231 GPIO 0x00000068 1 Page 234 DEVCPU_RST_REGS 0x00000090 1 Page 237 MIIM 0x000000A0 2 0x00000024 Page 239 MIIM_READ_SCAN 0x000000E8 1 Page 243 RAM_STAT 0x00000114 1 Page 244 MISC 0x00000118 1 Miscellaneous Registers Page 244 SIO_CTRL 0x00000130 1 Serial IO control configuration Page 247 FAN_CFG 0x000001F0 1 Configuration register for the fan controller Page 252 FAN_STAT 0x000001F4 1 Fan controller statistics Page 253 MEMITGR 0x00000234 1 Memory integrity monitor Page 253 Registers for software/software interaction Page 227 DEVCPU_GCB:CHIP_REGS Parent: DEVCPU_GCB Instances: 1 Table 266 • Registers in CHIP_REGS Register Name Offset within Register Group Instances and Address Spacing Description Details GENERAL_PURPOSE 0x00000000 1 Page 226 general purpose register VMDS-10392 VSC7420-02, VSC7421-02, and VSC7422-02 Datasheet Revision 4.3 225 Registers Table 266 • Registers in CHIP_REGS (continued) 7.6.1.1 Register Name Offset within Register Group Instances and Address Spacing Description Details SI 0x00000004 1 SI registers Page 226 CHIP_ID 0x00000008 1 Chip Id Page 227 DEVCPU_GCB:CHIP_REGS:GENERAL_PURPOSE Parent: DEVCPU_GCB:CHIP_REGS Instances: 1 Table 267 • Fields in GENERAL_PURPOSE Field Name Bit GENERAL_PURPOSE_R 31:0 EG 7.6.1.2 Access Description Default R/W This is a general-purpose register that can be used for testing. The value in this register has no functionality other than general purpose storage. 0x00000000 DEVCPU_GCB:CHIP_REGS:SI Parent: DEVCPU_GCB:CHIP_REGS Instances: 1 Configuration of serial interface data format. This register modifies how the SI receives and transmits data, when configuring this register first write 0 (to get to a known state), then configure the desired values. Table 268 • Fields in SI Field Name Bit Access Description Default SI_LSB 5 R/W Setup SI to use MSB or LSB first. See datasheet for more information. 0: SI expect/transmit MSB first 1: SI expect/transmit LSB first 0x0 SI_ENDIAN 4 R/W Setup SI to use either big or little 0x1 endian data format. See datasheet for more information. 0: SI uses little endian notation 1: SI uses big endian notation SI_WAIT_STATES 3:0 R/W Configure the number of padding 0x0 bytes that the SI must insert before transmitting read-data during reading from the device. 0 : don't insert any padding 1 : Insert 1 byte of padding ... 15: Insert 15 bytes of padding VMDS-10392 VSC7420-02, VSC7421-02, and VSC7422-02 Datasheet Revision 4.3 226 Registers 7.6.1.3 DEVCPU_GCB:CHIP_REGS:CHIP_ID Parent: DEVCPU_GCB:CHIP_REGS Instances: 1 Table 269 • Fields in CHIP_ID 7.6.2 Field Name Bit Access Description Default REV_ID 31:28 R/O Revision ID. 0x3 PART_ID 27:12 R/O Part ID. VSC7420-02 VSC7421-02 VSC7422-02 0x7420 0x7421 0x7422 MFG_ID 11:1 R/O Manufacturer's ID. 0x074 ONE 0 R/O Returns '1' 0x1 DEVCPU_GCB:SW_REGS Parent: DEVCPU_GCB Instances: 1 Table 270 • Registers in SW_REGS 7.6.2.1 Register Name Offset within Register Group Instances and Address Spacing Description Details SEMA_INTR_ENA 0x00000000 1 Semaphore SW interrupt enable Page 227 SEMA_INTR_ENA_CL R 0x00000004 1 Clear of semaphore SW interrupt enables Page 228 SEMA_INTR_ENA_SE T 0x00000008 1 Masking of semaphore Page 228 SEMA 0x0000000C 8 0x00000004 Semaphore register Page 229 SEMA_FREE 0x0000002C 1 Semaphore status Page 229 SW_INTR 0x00000030 1 Manually assert software interrupt Page 229 MAILBOX 0x00000034 1 Mailbox register Page 230 MAILBOX_CLR 0x00000038 1 Mailbox register atomic clear Page 230 MAILBOX_SET 0x0000003C 1 Mailbox register atomic set Page 230 DEVCPU_GCB:SW_REGS:SEMA_INTR_ENA Parent: DEVCPU_GCB:SW_REGS Instances: 1 VMDS-10392 VSC7420-02, VSC7421-02, and VSC7422-02 Datasheet Revision 4.3 227 Registers Table 271 • Fields in SEMA_INTR_ENA 7.6.2.2 Field Name Bit Access Description Default SEMA_INTR_IDENT 15:8 R/O This is a bitwise AND of SEMA_FREE and SEMA_INTR_ENA providing an fast access to the cause of an interrupt, given the current mask. 0x00 SEMA_INTR_ENA 7:0 R/W 0x00 Set bits in this register to enable interrupt when the corresponding semaphore is free. In a multi-threaded environment, or with more than one active processor the CPU_SEMA_ENA_SET and CPU_SEMA_ENA_CLR registers can be used for atomic modifications of this register. If interrupt is enabled for a particular semaphore, then software interrupt will be asserted for as long as the semaphore is free (and interrupt is enabled for that semaphore). The lower half of the available semaphores are connected to software Interrupt 0 (SW0), the upper half is connected to software interrupt 1 (SW1). DEVCPU_GCB:SW_REGS:SEMA_INTR_ENA_CLR Parent: DEVCPU_GCB:SW_REGS Instances: 1 Table 272 • Fields in SEMA_INTR_ENA_CLR 7.6.2.3 Field Name Bit Access Description Default SEMA_INTR_ENA_CLR 7:0 One-shot Set to clear corresponding interrupt enable in SEMA_INTR_ENA. 0x00 DEVCPU_GCB:SW_REGS:SEMA_INTR_ENA_SET Parent: DEVCPU_GCB:SW_REGS Instances: 1 Table 273 • Fields in SEMA_INTR_ENA_SET Field Name Bit Access Description Default SEMA_INTR_ENA_SET 7:0 One-shot Set to set corresponding interrupt enable in SEMA_INTR_ENA. 0x00 VMDS-10392 VSC7420-02, VSC7421-02, and VSC7422-02 Datasheet Revision 4.3 228 Registers 7.6.2.4 DEVCPU_GCB:SW_REGS:SEMA Parent: DEVCPU_GCB:SW_REGS Instances: 8 Table 274 • Fields in SEMA Field Name Bit Access Description SEMA 0 R/W General Semaphore.The process 0x1 to read this field will read a '1' and thus be granted the semaphore. The semaphore is released by the interface by writing a '1' to this field. Read : '0': Semaphore was not granted. '1': Semaphore was granted. Default Write : '0': No action. '1': Release semaphore. 7.6.2.5 DEVCPU_GCB:SW_REGS:SEMA_FREE Parent: DEVCPU_GCB:SW_REGS Instances: 1 Table 275 • Fields in SEMA_FREE 7.6.2.6 Field Name Bit Access Description Default SEMA_FREE 7:0 R/O Show which semaphores that are currently free. '0' : Corresponding semaphore is taken. '1' : Corresponding semaphore is free. 0xFF DEVCPU_GCB:SW_REGS:SW_INTR Parent: DEVCPU_GCB:SW_REGS Instances: 1 This register provides a simple interface for interrupting on either software interrupt 0 or 1, without implementing semaphore support. Note: setting this field causes a short pulse on the corresponding interrupt connection, this kind of interrupt cannot be used in combination with the SW1_INTR_CONFIG.SW1_INTR_BYPASS feature. VMDS-10392 VSC7420-02, VSC7421-02, and VSC7422-02 Datasheet Revision 4.3 229 Registers Table 276 • Fields in SW_INTR 7.6.2.7 Field Name Bit Access Description Default SW1_INTR 1 One-shot Set this field to inject software interrupt 1. This field is automatically cleared after interrupt has been generated. 0x0 SW0_INTR 0 One-shot Set this field to assert software interrupt 0. This field is automatically cleared after interrupt has been generated. 0x0 DEVCPU_GCB:SW_REGS:MAILBOX Parent: DEVCPU_GCB:SW_REGS Instances: 1 Table 277 • Fields in MAILBOX 7.6.2.8 Field Name Bit Access Description Default MAILBOX 31:0 R/W 0x00000000 Read/write register. Atomic modifications can be performed by using the MAILBOX_CLR and MAILBOX_SET registers. DEVCPU_GCB:SW_REGS:MAILBOX_CLR Parent: DEVCPU_GCB:SW_REGS Instances: 1 Table 278 • Fields in MAILBOX_CLR 7.6.2.9 Field Name Bit Access Description Default MAILBOX_CLR 31:0 One-shot 0x00000000 Set bits in this register to atomically clear corresponding bits in the MAILBOX register. This register returns 0 on read. DEVCPU_GCB:SW_REGS:MAILBOX_SET Parent: DEVCPU_GCB:SW_REGS Instances: 1 VMDS-10392 VSC7420-02, VSC7421-02, and VSC7422-02 Datasheet Revision 4.3 230 Registers Table 279 • Fields in MAILBOX_SET 7.6.3 Field Name Bit Access Description Default MAILBOX_SET 31:0 One-shot 0x00000000 Set bits in this register to atomically set corresponding bits in the MAILBOX register. This register returns 0 on read. DEVCPU_GCB:VCORE_ACCESS Parent: DEVCPU_GCB Instances: 1 Table 280 • Registers in VCORE_ACCESS 7.6.3.1 Register Name Offset within Register Group Instances and Address Spacing Description Details VA_CTRL 0x00000000 1 Control register for VCore accesses Page 231 VA_ADDR 0x00000004 1 Address register for VCore Page 232 accesses VA_DATA 0x00000008 1 Data register for VCore accesses Page 233 VA_DATA_INCR 0x0000000C 1 Data register for VCore accesses (w. auto increment of address) Page 234 VA_DATA_INERT 0x00000010 1 Data register for VCore accesses (will not initiate access) Page 234 DEVCPU_GCB:VCORE_ACCESS:VA_CTRL Parent: DEVCPU_GCB:VCORE_ACCESS Instances: 1 Table 281 • Fields in VA_CTRL Field Name Bit Access Description Default VA_ERR_RD 3 R/O 0x0 This field is set to the value of VA_CTRL:VA_ERR whenever one of the data registers ACC_DATA, ACC_DATA_INCR, or ACC_DATA_RO is read. By reading this field it is possible to determine if the last read-value from one of these registers was erred. VMDS-10392 VSC7420-02, VSC7421-02, and VSC7422-02 Datasheet Revision 4.3 231 Registers Table 281 • Fields in VA_CTRL (continued) 7.6.3.2 Field Name Bit Access Description Default VA_ERR 2 R/O This field is set if the access inside 0x0 the VCore domain was terminated by an error. This situation can occur when accessing an unmapped part of the VCore memory-map or when accessing a target that reports error (e.g. accessing uninitialized DDR2 memory). If an error occurs during reading, the read-data will be 0x80000000. So as an optimization, software only has to check for error if 0x80000000 is returned (and in that case VA_ERR_RD should be checked). When writing you should always check if successful. VA_BUSY_RD 1 R/O 0x0 This field is set to the value of VA_CTRL:VA_BUSY whenever one of the data registers ACC_DATA, ACC_DATA_INCR, or ACC_DATA_RO is read. By reading this field it is possible to determine if the last read-value from one of these registers was valid. VA_BUSY 0 R/O This field is set by hardware when 0x0 an access into VCore domain is started, and cleared when the access is done. DEVCPU_GCB:VCORE_ACCESS:VA_ADDR Parent: DEVCPU_GCB:VCORE_ACCESS Instances: 1 Table 282 • Fields in VA_ADDR Field Name Bit Access Description Default VA_ADDR 31:0 R/W 0x00000000 The address to access in the VCore domain, all addresses must be 32-bit aligned (i.e. the two least significant bit must always be 0). When accesses are initiated using the ACC_DATA_INCR register, then this field is automatically incremented by 4 at the end of the transfer. The memory region of the VCore that maps to switch-core registers may not be accessed by using these registers. VMDS-10392 VSC7420-02, VSC7421-02, and VSC7422-02 Datasheet Revision 4.3 232 Registers 7.6.3.3 DEVCPU_GCB:VCORE_ACCESS:VA_DATA Parent: DEVCPU_GCB:VCORE_ACCESS Instances: 1 The VA_DATA, VA_DATA_INCR, and VA_DATA_INERT registers are used for indirect access into the VCore domain. The functionality of the VA_DATA_INCR and VA_DATA_INERT registers are similar to this register - but with minor exceptions. These exceptions are fleshed out in the description of the respective registers. Table 283 • Fields in VA_DATA Field Name Bit Access Description Default VA_DATA 31:0 R/W Reading or writing from/to this field 0x00000000 initiates accesses into the VCore domain. While an access is ongoing (VA_CTRL:VA_BUSY is set) this field may not be written. It is possible to read this field while an access is ongoing, but the data returned will be 0x80000000. When writing to this field; a write into the VCore domain is initiated to the address specified in the VA_ADDR register, with the data that was written to this field. Only 32-bit writes are supported. This field may not be written to until the VA_CTRL:VA_BUSY indicates that no accesses is ongoing. When reading from this field; a read from the VCore domain is initiated from the address specified in the VA_ADDR register. Important: The data that is returned from reading this field (and stating an access) is not the result of the newly initiated read, instead the data from the last access is returned. The result of the newly initiated read access will be ready once the VA_CTRL:VA_BUSY field shows that the access is done. Note: When the result of a read-access is read from this field (the second read), a new access will automatically be initiated. This is desirable when reading a series of addresses from VCore domain. If a new access is not desirable, then the result should be read from the VA_DATA_INERT register instead of this field! VMDS-10392 VSC7420-02, VSC7421-02, and VSC7422-02 Datasheet Revision 4.3 233 Registers 7.6.3.4 DEVCPU_GCB:VCORE_ACCESS:VA_DATA_INCR Parent: DEVCPU_GCB:VCORE_ACCESS Instances: 1 Table 284 • Fields in VA_DATA_INCR 7.6.3.5 Field Name Bit Access Description VA_DATA_INCR 31:0 R/W This field behaves in the same way 0x00000000 as ACC_DATA:ACC_DATA. Except when an access is initiated by using this field (either read or write); the address register (ACC_ADDR) is automatically incremented by 4 at the end of the access, i.e. when VA_CTRL:VA_BUSY is deasserted. Default DEVCPU_GCB:VCORE_ACCESS:VA_DATA_INERT Parent: DEVCPU_GCB:VCORE_ACCESS Instances: 1 Table 285 • Fields in VA_DATA_INERT 7.6.4 Field Name Bit Access Description Default VA_DATA_INERT 31:0 R/W This field behaves in the same way 0x00000000 as ACC_DATA:ACC_DATA. Except accesses (read or write) does not initiate VCore accesses. Writing to this register just overwrites the value currently held by all of the data registers (ACC_DATA, ACC_DATA_INCR, and ACC_DATA_INERT). DEVCPU_GCB:GPIO Parent: DEVCPU_GCB Instances: 1 General Purpose I/O Control configuration and status registers. Each register in this group contains one field with one bit per GPIO pin. Bit 0 in each field corresponds to GPIO0, bit 1 to GPIO1, and so on. Table 286 • Registers in GPIO Register Name Offset within Register Group Instances and Address Spacing Description Details GPIO_OUT_SET 0x00000000 1 Page 235 GPIO output set VMDS-10392 VSC7420-02, VSC7421-02, and VSC7422-02 Datasheet Revision 4.3 234 Registers Table 286 • Registers in GPIO (continued) 7.6.4.1 Register Name Offset within Register Group Instances and Address Spacing Description Details GPIO_OUT_CLR 0x00000004 1 GPIO output clear Page 235 GPIO_OUT 0x00000008 1 GPIO output Page 235 GPIO_IN 0x0000000C 1 GPIO input Page 236 GPIO_OE 0x00000010 1 GPIO pin direction Page 236 GPIO_INTR 0x00000014 1 GPIO interrupt Page 236 GPIO_INTR_ENA 0x00000018 1 GPIO interrupt enable Page 237 GPIO_INTR_IDENT 0x0000001C 1 GPIO interrupt identity Page 237 GPIO_ALT 0x00000020 1 GPIO alternate functions Page 237 DEVCPU_GCB:GPIO:GPIO_OUT_SET Parent: DEVCPU_GCB:GPIO Instances: 1 Table 287 • Fields in GPIO_OUT_SET 7.6.4.2 Field Name Bit Access Description Default G_OUT_SET 31:0 One-shot 0x00000000 Setting a bit in this field will immediately set the corresponding bit in GPIO_O::G_OUT. Reading this register always return 0. '0': No change '1': Corresponding bit in GPIO_O::OUT is set. DEVCPU_GCB:GPIO:GPIO_OUT_CLR Parent: DEVCPU_GCB:GPIO Instances: 1 Table 288 • Fields in GPIO_OUT_CLR 7.6.4.3 Field Name Bit Access Description Default G_OUT_CLR 31:0 One-shot Setting a bit in this field will immediately clear the corresponding bit in GPIO_O::G_OUT. Reading this register always return 0. '0': No change '1': Corresponding bit in GPIO_O::OUT is cleared. 0x00000000 DEVCPU_GCB:GPIO:GPIO_OUT Parent: DEVCPU_GCB:GPIO Instances: 1 VMDS-10392 VSC7420-02, VSC7421-02, and VSC7422-02 Datasheet Revision 4.3 235 Registers In a multi-threaded software environment using the registers GPIO_OUT_SET and GPIO_OUT_CLR for modifying GPIO values removes the need for software-locked access. Table 289 • Fields in GPIO_OUT 7.6.4.4 Field Name Bit Access Description Default G_OUT 31:0 R/W 0x00000000 Controls the value on the GPIO pins enabled for output (via the GPIO_OE register). This field can be modified directly or by using the GPIO_O_SET and GPIO_O_CLR registers. DEVCPU_GCB:GPIO:GPIO_IN Parent: DEVCPU_GCB:GPIO Instances: 1 Table 290 • Fields in GPIO_IN 7.6.4.5 Field Name Bit Access Description Default G_IN 31:0 R/O GPIO input register. Reflects the 0x00000000 current state of the corresponding GPIO pins. DEVCPU_GCB:GPIO:GPIO_OE Parent: DEVCPU_GCB:GPIO Instances: 1 Table 291 • Fields in GPIO_OE 7.6.4.6 Field Name Bit Access Description Default G_OE 31:0 R/W Configures the direction of the GPIO pins. '0': Input '1': Output 0x00000000 DEVCPU_GCB:GPIO:GPIO_INTR Parent: DEVCPU_GCB:GPIO Instances: 1 Table 292 • Fields in GPIO_INTR Field Name Bit Access Description Default G_INTR 31:0 Sticky Indicates whether a GPIO input has changed since last clear. '0': No change '1': GPIO has changed 0x00000000 VMDS-10392 VSC7420-02, VSC7421-02, and VSC7422-02 Datasheet Revision 4.3 236 Registers 7.6.4.7 DEVCPU_GCB:GPIO:GPIO_INTR_ENA Parent: DEVCPU_GCB:GPIO Instances: 1 Table 293 • Fields in GPIO_INTR_ENA 7.6.4.8 Field Name Bit Access Description Default G_INTR_ENA 31:0 R/W Enables individual GPIO pins for interrupt. 0x00000000 DEVCPU_GCB:GPIO:GPIO_INTR_IDENT Parent: DEVCPU_GCB:GPIO Instances: 1 Table 294 • Fields in GPIO_INTR_IDENT 7.6.4.9 Field Name Bit Access Description G_INTR_IDENT 31:0 R/O Shows which GPIO sources that 0x00000000 are currently interrupting. This field is the result of an AND-operation between the GPIO_INTR and the GPIO_INTR_ENA registers. Default DEVCPU_GCB:GPIO:GPIO_ALT Parent: DEVCPU_GCB:GPIO Instances: 1 Table 295 • Fields in GPIO_ALT 7.6.5 Field Name Bit Access Description Default G_ALT 31:0 R/W Configures alternate functions for individual GPIO bits. 0: GPIO mode 1: Alternate mode 0x00000000 DEVCPU_GCB:DEVCPU_RST_REGS Parent: DEVCPU_GCB Instances: 1 Resets the chip VMDS-10392 VSC7420-02, VSC7421-02, and VSC7422-02 Datasheet Revision 4.3 237 Registers Table 296 • Registers in DEVCPU_RST_REGS 7.6.5.1 Register Name Offset within Register Group Instances and Address Spacing Description SOFT_CHIP_RST 0x00000000 1 Reset part or the whole chip Page 238 SOFT_DEVCPU_RST 0x00000004 1 Soft reset of devcpu. Details Page 238 DEVCPU_GCB:DEVCPU_RST_REGS:SOFT_CHIP_RST Parent: DEVCPU_GCB:DEVCPU_RST_REGS Instances: 1 Table 297 • Fields in SOFT_CHIP_RST 7.6.5.2 Field Name Bit Access Description SOFT_PHY_RST 1 R/W Clear this field to release reset in 0x1 the Cu-PHY. This field is automatically set during hard-reset and soft-reset of the chip. After reset is released the PHY will indicate when it is ready to be accessed via DEVCPU_GCB::MISC_STAT.PHY _READY. Default SOFT_CHIP_RST 0 R/W 0x0 Set this field to reset the whole chip. This field is automatically cleared by the reset. Note: It is possible for the VCore to protect itself from soft-reset of the chip, for more info see RESET.CORE_RST_PROTECT inside the VCore register space. DEVCPU_GCB:DEVCPU_RST_REGS:SOFT_DEVCPU_RST Parent: DEVCPU_GCB:DEVCPU_RST_REGS Instances: 1 Table 298 • Fields in SOFT_DEVCPU_RST Field Name Bit Access Description Default SOFT_XTR_RST 1 R/W Set this field to reset the extraction 0x0 logic. The reset remains asserted until this field is cleared. Note: Extraction logic is also reset while SOFT_CHIP_RST.SOFT_NON_C FG_RST is set. VMDS-10392 VSC7420-02, VSC7421-02, and VSC7422-02 Datasheet Revision 4.3 238 Registers Table 298 • Fields in SOFT_DEVCPU_RST (continued) 7.6.6 Field Name Bit Access Description Default SOFT_INJ_RST 0 R/W Set this field to reset the injection 0x0 logic. The reset remains asserted until this field is cleared. Note: Injection logic is also reset while SOFT_CHIP_RST.SOFT_NON_C FG_RST is set. DEVCPU_GCB:MIIM Parent: DEVCPU_GCB Instances: 2 Table 299 • Registers in MIIM 7.6.6.1 Register Name Offset within Register Group Instances and Address Spacing Description Details MII_STATUS 0x00000000 1 MIIM Status Page 239 MII_CMD 0x00000008 1 MIIM Command Page 240 MII_DATA 0x0000000C 1 MIIM Reply Data Page 241 MII_CFG 0x00000010 1 MIIM Configuration Page 241 MII_SCAN_0 0x00000014 1 MIIM Scan 0 Page 242 MII_SCAN_1 0x00000018 1 MIIM Scan 1 Page 242 MII_SCAN_LAST_RSLT 0x0000001C S 1 MIIM Results Page 242 MII_SCAN_LAST_RSLT 0x00000020 S_VLD 1 MIIM Results Page 243 DEVCPU_GCB:MIIM:MII_STATUS Parent: DEVCPU_GCB:MIIM Instances: 1 Table 300 • Fields in MII_STATUS Field Name Bit Access Description Default MIIM_STAT_BUSY 3 R/O 0x0 Indicates the current state of the MIIM controller. When read operations are done (no longer busy), then read data is available via the DEVCPU_GCB::MII_DATA register. 0: MIIM controller is in idle state 1: MIIM controller is busy performing MIIM cmd (Either read or read cmd). VMDS-10392 VSC7420-02, VSC7421-02, and VSC7422-02 Datasheet Revision 4.3 239 Registers Table 300 • Fields in MII_STATUS (continued) 7.6.6.2 Field Name Bit Access Description Default MIIM_STAT_OPR_PEND 2 R/O The MIIM controller has a CMD fifo 0x0 of depth one. When this field is 0, then it is safe to write another MIIM command to the MIIM controller. 0 : Read or write not pending 1 : Read or write pending. MIIM_STAT_PENDING_R 1 D R/O Indicates whether a read operation 0x0 via the MIIM interface is in progress or not. 0 : Read not in progress 1 : Read in progress. MIIM_STAT_PENDING_W 0 R R/O Indicates whether a write operation 0x0 via the MIIM interface is in progress or not. 0 : Write not in progress 1 : Write in progress. MIIM_SCAN_COMPLETE 4 R/O 0x0 Signals if all PHYs have been scanned ( with auto scan ) at least once. 0 : Auto scan has not scanned all PHYs. 1 : Auto scan has scanned all PHY at least once. DEVCPU_GCB:MIIM:MII_CMD Parent: DEVCPU_GCB:MIIM Instances: 1 Table 301 • Fields in MII_CMD Field Name Bit Access Description Default MIIM_CMD_VLD 31 One-shot Must be set for starting a new PHY 0x0 access. This bit is automatically cleared. 0 : Write to this register is ignored. 1 : Write to this register is processed. MIIM_CMD_PHYAD 29:25 R/W Indicates the addressed PHY number. 0x00 MIIM_CMD_REGAD 24:20 R/W Indicates the addressed of the register within the PHY that shall be accessed. 0x00 MIIM_CMD_WRDATA 19:4 R/W Data to be written in the PHY register. 0x0000 VMDS-10392 VSC7420-02, VSC7421-02, and VSC7422-02 Datasheet Revision 4.3 240 Registers Table 301 • Fields in MII_CMD (continued) Field Name Bit Access Description MIIM_CMD_SINGLE_SCA 3 N R/W Select if scanning of the PHY shall 0x0 be done once, or scanning should be done continuously. 0 : Do continuously PHY scanning 1 : Stop once all PHY have been scanned. MIIM_CMD_OPR_FIELD R/W Indicates type of operation. Clause 22: 2:1 Default 0x0 01 : Write 10 : Read Clause 45: 00 : Address 01 : Write 10 : Read inc. 11 : Read. MIIM_CMD_SCAN 7.6.6.3 0 R/W 0x0 Indicates whether automatic scanning of PHY registers is enabled. When enabled, the PHY-number for each automatic read is continuously round-robined from PHY_ADDR_LOW through PHY_ADDR_HIGH. This function is started upon a read operation (ACCESS_TYPE). Scan MUST be disabled when doing any configuration of the MIIM controller. 0 : Disabled 1 : Enabled. DEVCPU_GCB:MIIM:MII_DATA Parent: DEVCPU_GCB:MIIM Instances: 1 Table 302 • Fields in MII_DATA 7.6.6.4 Field Name Bit Access Description Default MIIM_DATA_SUCCESS 17:16 R/O Indicates whether a read operation 0x0 failed or succeeded. 00 : OK 11 : Error MIIM_DATA_RDDATA 15:0 R/O Data read from PHY register. 0x0000 DEVCPU_GCB:MIIM:MII_CFG Parent: DEVCPU_GCB:MIIM Instances: 1 VMDS-10392 VSC7420-02, VSC7421-02, and VSC7422-02 Datasheet Revision 4.3 241 Registers Table 303 • Fields in MII_CFG 7.6.6.5 Field Name Bit Access Description Default MIIM_CFG_PRESCALE 7:0 R/W 0x32 Configures the MIIM clock frequency. This is computed as system_clk/(2*(1+X)), where X is the value written to this register. Note : Setting X to 0 is invalid and will result in the same frequency as setting X to 1. MIIM_ST_CFG_FIELD 10:9 R/W The ST (start-of-frame) field of the 0x1 MIIM frame format adopts the value of this field. This must be configured for either clause 22 or 45 MIIM operation. "01": Clause 22 "00": Clause 45 Other values are reserved. DEVCPU_GCB:MIIM:MII_SCAN_0 Parent: DEVCPU_GCB:MIIM Instances: 1 Table 304 • Fields in MII_SCAN_0 7.6.6.6 Field Name Bit Access Description Default MIIM_SCAN_PHYADHI 9:5 R/W Indicates the high PHY number to 0x00 scan during automatic scanning. MIIM_SCAN_PHYADLO 4:0 R/W Indicates the low PHY number to scan during automatic scanning. 0x00 DEVCPU_GCB:MIIM:MII_SCAN_1 Parent: DEVCPU_GCB:MIIM Instances: 1 Table 305 • Fields in MII_SCAN_1 7.6.6.7 Field Name Bit Access Description Default MIIM_SCAN_MASK 31:16 R/W Indicates the mask for comparing 0x0000 the PHY registers during automatic scan. MIIM_SCAN_EXPECT 15:0 R/W Indicates the expected value for comparing the PHY registers during automatic scan. 0x0000 DEVCPU_GCB:MIIM:MII_SCAN_LAST_RSLTS Parent: DEVCPU_GCB:MIIM Instances: 1 VMDS-10392 VSC7420-02, VSC7421-02, and VSC7422-02 Datasheet Revision 4.3 242 Registers Table 306 • Fields in MII_SCAN_LAST_RSLTS 7.6.6.8 Field Name Bit Access Description Default MIIM_LAST_RSLT 31:0 R/O 0x00000000 Indicates for each PHY if a PHY register has matched the expected value (with mask). This register reflects the value of the last reading of the phy register. 0 : Mismatch. 1 : Match. DEVCPU_GCB:MIIM:MII_SCAN_LAST_RSLTS_VLD Parent: DEVCPU_GCB:MIIM Instances: 1 Table 307 • Fields in MII_SCAN_LAST_RSLTS_VLD 7.6.7 Field Name Bit Access Description Default MIIM_LAST_RSLT_VLD 31:0 R/O Indicates for each PHY if a PHY register matched are valid or not. 0 : Scan result not valid. 1 : Scan result valid. 0x00000000 DEVCPU_GCB:MIIM_READ_SCAN Parent: DEVCPU_GCB Instances: 1 Table 308 • Registers in MIIM_READ_SCAN Register Name Offset within Register Group MII_SCAN_RSLTS_STI 0x00000000 CKY 7.6.7.1 Instances and Address Spacing Description 2 0x00000004 MIIM Results Details Page 243 DEVCPU_GCB:MIIM_READ_SCAN:MII_SCAN_RSLTS_STICKY Parent: DEVCPU_GCB:MIIM_READ_SCAN Instances: 2 VMDS-10392 VSC7420-02, VSC7421-02, and VSC7422-02 Datasheet Revision 4.3 243 Registers Table 309 • Fields in MII_SCAN_RSLTS_STICKY Field Name Bit Access Description Default MIIM_SCAN_RSLTS_STI CKY 31:0 R/O 0x00000000 Indicates for each PHY if a PHY register has had a mismatch of the expected value (with mask) since last reading of MIIM_SCAN_RSLTS_STICKY. Result is sticky, and result will indicate if there has been a mismatch since the last reading of this register. Upon reading this register, all bits are reset to '1'. 0 : Mismatch 1 : Match. 7.6.8 DEVCPU_GCB:RAM_STAT Parent: DEVCPU_GCB Instances: 1 Table 310 • Registers in RAM_STAT Register Name Offset within Register Group RAM_INTEGRITY_ERR 0x00000000 _STICKY 7.6.8.1 Instances and Address Spacing Description Details 1 Page 244 QS RAM status DEVCPU_GCB:RAM_STAT:RAM_INTEGRITY_ERR_STICKY Parent: DEVCPU_GCB:RAM_STAT Instances: 1 Table 311 • Fields in RAM_INTEGRITY_ERR_STICKY Field Name Bit QS_XTR_RAM_INTGR_E 0 RR_STICKY 7.6.9 Access Description Default Sticky 0x0 Integrity error for QS_XTR RAM '0': No RAM integrity check error occurred '1': A RAM integrity check error occurred Bit is cleared by writing a '1' to this position. DEVCPU_GCB:MISC Parent: DEVCPU_GCB VMDS-10392 VSC7420-02, VSC7421-02, and VSC7422-02 Datasheet Revision 4.3 244 Registers Instances: 1 Table 312 • Registers in MISC 7.6.9.1 Register Name Offset within Register Group Instances and Address Spacing Description Details MISC_CFG 0x00000000 1 Page 245 MISC_STAT 0x00000004 1 Page 245 PHY_SPEED_1000_ST 0x00000008 AT 1 Page 246 PHY_SPEED_100_STA 0x0000000C T 1 Page 246 PHY_SPEED_10_STAT 0x00000010 1 Page 246 DUPLEXC_PORT_STA 0x00000014 T 1 Page 246 Miscellaneous Configuration Register DEVCPU_GCB:MISC:MISC_CFG Parent: DEVCPU_GCB:MISC Instances: 1 Register to control various muxing in the IO-ring. Table 313 • Fields in MISC_CFG 7.6.9.2 Field Name Bit Access Description Default SW_MODE 7:6 R/W Set the sw_mode for HSIO. 0: Use for VSC7421-02 (12x CuPHY + 1x QSGMII + 1x 2.5G SGMII) and VSC7422-02. 1: Use for VSC7420-02 and VSC7421-02 (12x CuPHY + 2x 1G SGMII + 2x 2.5G SGMII). 2: Reserved. 3: Reserved. 0x0 QSGMII_FLIP_LANE1 5 R/W Flip or swap lanes in QSGMII#1. 0x0 QSGMII_FLIP_LANE2 4 R/W Flip or swap lanes in QSGMII#2. 0x0 QSGMII_FLIP_LANE3 3 R/W Flip or swap lanes in QSGMII#3. 0x0 QSGMII_SHYST_DIS 2 R/W Disable hysteresis of synchronization state machine. 0x0 QSGMII_E_DET_ENA 1 R/W Enable 8b10b error propagation (8b10b error code-groups are replaced by K70.7 error symbols. 0x0 QSGMII_USE_I1_ENA 0 R/W Use I1 during idle sequencing only. 0x0 DEVCPU_GCB:MISC:MISC_STAT Parent: DEVCPU_GCB:MISC Instances: 1 VMDS-10392 VSC7420-02, VSC7421-02, and VSC7422-02 Datasheet Revision 4.3 245 Registers Table 314 • Fields in MISC_STAT 7.6.9.3 Field Name Bit Access Description Default PHY_READY 3 R/O This field is set high when the PHY 0x0 is ready for access after release of PHY reset via DEVCPU_GCB::SOFT_CHIP_RS T.SOFT_PHY_RST. DEVCPU_GCB:MISC:PHY_SPEED_1000_STAT Parent: DEVCPU_GCB:MISC Instances: 1 Table 315 • Fields in PHY_SPEED_1000_STAT 7.6.9.4 Field Name Bit Access Description Default SPEED_1000 11:0 R/O p2m_speed1000c status from PHY 0x000 DEVCPU_GCB:MISC:PHY_SPEED_100_STAT Parent: DEVCPU_GCB:MISC Instances: 1 Table 316 • Fields in PHY_SPEED_100_STAT 7.6.9.5 Field Name Bit Access Description Default SPEED_100 11:0 R/O p2m_speed100 status from PHY 0x000 DEVCPU_GCB:MISC:PHY_SPEED_10_STAT Parent: DEVCPU_GCB:MISC Instances: 1 Table 317 • Fields in PHY_SPEED_10_STAT 7.6.9.6 Field Name Bit Access Description Default SPEED_10 11:0 R/O p2m_speed10 status from PHY 0x000 DEVCPU_GCB:MISC:DUPLEXC_PORT_STAT Parent: DEVCPU_GCB:MISC Instances: 1 VMDS-10392 VSC7420-02, VSC7421-02, and VSC7422-02 Datasheet Revision 4.3 246 Registers Table 318 • Fields in DUPLEXC_PORT_STAT Field Name Bit Access Description Default DUPLEXC 11:0 R/O p2m_duplexc_port status from PHY 0x000 7.6.10 DEVCPU_GCB:SIO_CTRL Parent: DEVCPU_GCB Instances: 1 Table 319 • Registers in SIO_CTRL Register Name Offset within Register Group Instances and Address Spacing Description SIO_INPUT_DATA 0x00000000 4 0x00000004 Input data registers Page 247 SIO_INT_POL 0x00000010 4 0x00000004 Interrupt polarity for each GPIO Page 248 SIO_PORT_INT_ENA 0x00000020 1 Interrupt enable register for Page 248 each port. SIO_PORT_CONFIG 0x00000024 32 0x00000004 Configuration of output data Page 248 values SIO_PORT_ENABLE 0x000000A4 1 Port enable register Page 249 SIO_CONFIG 0x000000A8 1 General configuration register Page 249 SIO_CLOCK 0x000000AC 1 Configuration of the serial IO clock frequency Page 251 SIO_INT_REG 0x000000B0 4 0x00000004 Interrupt register Page 251 7.6.10.1 Details DEVCPU_GCB:SIO_CTRL:SIO_INPUT_DATA Parent: DEVCPU_GCB:SIO_CTRL Instances: 4 Table 320 • Fields in SIO_INPUT_DATA Field Name Bit Access Description Default S_IN 31:0 R/O 0x00000000 Serial input data. The first replication holds bit 0 from all ports, the 2nd replication holds bit 1 from all ports, etc. Values of disabled gpios are undefined. bit order: (port-31 bit-n down to port-0 bit-n) VMDS-10392 VSC7420-02, VSC7421-02, and VSC7422-02 Datasheet Revision 4.3 247 Registers 7.6.10.2 DEVCPU_GCB:SIO_CTRL:SIO_INT_POL Parent: DEVCPU_GCB:SIO_CTRL Instances: 4 Table 321 • Fields in SIO_INT_POL Field Name Bit Access Description INT_POL 31:0 R/W 0x00000000 Interrupt polarity. Bit n from all ports. This register defines at which logic value an interrupt is generated. For bit 0, this register is also used to define the polarity of the "loss of signal" output. 0 : interrupt at logic value '1' 1 : interrupt at logic value '0' For "loss of signal": 0 : "loss of signal" is active high 1: "loss of signal" is active low 7.6.10.3 Default DEVCPU_GCB:SIO_CTRL:SIO_PORT_INT_ENA Parent: DEVCPU_GCB:SIO_CTRL Instances: 1 Table 322 • Fields in SIO_PORT_INT_ENA Field Name Bit Access Description Default INT_ENA 31:0 R/W Interrupt enable vector with one enable bit for each port. 0x00000000 0 : Interrupt is disabled for the port. 1 : Interrupt is enabled for the port. port order: (portN down to port0) 7.6.10.4 DEVCPU_GCB:SIO_CTRL:SIO_PORT_CONFIG Parent: DEVCPU_GCB:SIO_CTRL Instances: 32 VMDS-10392 VSC7420-02, VSC7421-02, and VSC7422-02 Datasheet Revision 4.3 248 Registers Table 323 • Fields in SIO_PORT_CONFIG Field Name Bit Access Description BIT_SOURCE 11:0 R/W 0x000 Output source select for the four outputs from each port. The source select is encoded using three bits for each output bit. The placement of the source select bits for each output bit in the register: Output bit 0: (2 down to 0) Output bit 1: (5 down to 3) Output bit 2: (8 down to 6) Output bit 3: (11 down to 9) Source select encoding for each output bit: 0 : Forced '0' 1 : Forced '1' 2 : Blink mode 0 3 : Blink mode 1 4 : Link activity blink mode 0 5 : Link activity blink mode 1 6 : Link activity blink mode 0 inversed polarity 7 : Link activity blink mode 1 inversed polarity 7.6.10.5 Default DEVCPU_GCB:SIO_CTRL:SIO_PORT_ENABLE Parent: DEVCPU_GCB:SIO_CTRL Instances: 1 Table 324 • Fields in SIO_PORT_ENABLE Field Name Bit Access Description P_ENA 31:0 R/W Port enable vector with one enable 0x00000000 bit for each port. 0 : Port is disabled. 1 : Port is enabled. Port order: (portN down to port0) 7.6.10.6 Default DEVCPU_GCB:SIO_CTRL:SIO_CONFIG Parent: DEVCPU_GCB:SIO_CTRL Instances: 1 VMDS-10392 VSC7420-02, VSC7421-02, and VSC7422-02 Datasheet Revision 4.3 249 Registers Table 325 • Fields in SIO_CONFIG Field Name Bit Access Description Default SIO_BMODE_1 21:20 R/W 0x0 Configuration for blink mode 1. Supports three different blink modes and a "burst toggle" mode in which blink mode 1 will alternate for each burst. 0 : Blink freq approximately 20Hz 1 : Blink freq approximately 10Hz. 2 : Blink freq approximately 5Hz. 3 : Burst toggle. SIO_BMODE_0 19:18 R/W Configuration of blink mode 0. Supports four different blink modes. 0 : Blink freq approximately 20Hz. 1 : Blink freq approximately 10Hz. 2 : Blink freq approximately 5Hz. 3 : Blink freq approximately 2.5Hz. 0x0 SIO_BLINK_RESET 17 R/W Reset the blink counters. Used to synchronize the blink modes between different chips. 0 : Blink counter is running. 1 : Blink counter is reset until sio_blink_reset is unset again. 0x0 SIO_INT_ENA 16:13 R/W Bit interrupt enable. Enables interrupts for 0x0 the four gpios in a port. Is applied to all ports. 0: Interrupt is disabled for bit n for all ports. 1: Interrupt is enabled for bit n for all ports. SIO_BURST_GAP_DI S 12 R/W Set to disable burst gap. SIO_BURST_GAP 11:7 R/W Configures the length of burst gap in steps 0x00 of approx. 1 ms. Burst gap can be disabled by setting SIO_CONFIG.SIO_BURST_GAP_DIS. 0: 1.05 ms burst gap. 1: 2.10 ms burst gap. 31: 33.55 ms burst gap. SIO_SINGLE_SHOT 6 One-shot Use this to output a single burst. Will be cleared by hardware when the burst has finished. 0x0 SIO_AUTO_REPEAT 5 R/W Use this to output repeated bursts interleaved with burst gaps. Must be manually reset again to stop output of bursts. 0x0 SIO_LD_POLARITY 4 R/W Polarity of the "Ld" signal 0: load signal is active low 1: load signal is active high 0x0 SIO_PORT_WIDTH 3:2 R/W Number of gpios pr. port. 0: 1 gpio pr. port. 1: 2 gpios pr. port. 2: 3 gpios pr. port. 3: 4 gpios pr. port. 0x0 0x0 VMDS-10392 VSC7420-02, VSC7421-02, and VSC7422-02 Datasheet Revision 4.3 250 Registers Table 325 • Fields in SIO_CONFIG (continued) Field Name Bit SIO_REVERSE_OUTP 1 UT Access Description Default R/W Reverse the output bitstream. 0x0 The default order of the output bit stream is (displayed in transmitted order): (portN bit3, portN bit2, ...., port0 bit1, port0 bit0) The reverse order of the output bit stream is (displayed in transmitted order): (port0 bit0, port0 bit1, ...., portN bit2, portN bit3) 0 : Do not reverse. 1 : Reverse. SIO_REVERSE_INPU 0 T 7.6.10.7 R/W 0x0 Reverse the input bitstream. The default order of the input bit stream is (displayed in received order): (port0 bit0, port0 bit1, ...., portN bit2, portN bit3) The reverse order of the input bit stream is (displayed in received order): (portN bit3, portN bit2, ...., port0 bit1, port0 bit0) 0: Do not reverse. 1: Reverse. DEVCPU_GCB:SIO_CTRL:SIO_CLOCK Parent: DEVCPU_GCB:SIO_CTRL Instances: 1 Table 326 • Fields in SIO_CLOCK Field Name Bit Access Description Default SIO_CLK_FREQ 11:0 R/W SIO controller clock frequency. Divides the 250MHz system clk with value of this field. E.g. the system clk is 250 MHz and this field is set to 10, the output frequency will be 25 MHz. 0 : Disable clock. 1 : Reserved, do not use. Others : Clock divider value. 0x000 7.6.10.8 DEVCPU_GCB:SIO_CTRL:SIO_INT_REG Parent: DEVCPU_GCB:SIO_CTRL Instances: 4 VMDS-10392 VSC7420-02, VSC7421-02, and VSC7422-02 Datasheet Revision 4.3 251 Registers Table 327 • Fields in SIO_INT_REG Field Name Bit Access Description Default INT_REG 31:0 Sticky Interrupt register. Bit n from all ports. Disabled gpios are always '0'. 0: No interrupt for given gpio. 1: Interrupt for given gpio. bit order (portM bit-n down to portM bit-0). 0x00000000 7.6.11 DEVCPU_GCB:FAN_CFG Parent: DEVCPU_GCB Instances: 1 Table 328 • Registers in FAN_CFG Register Name Offset within Register Group Instances and Address Spacing Description Details FAN_CFG 0x00000000 1 Page 252 7.6.11.1 Configuration register for the fan controller DEVCPU_GCB:FAN_CFG:FAN_CFG Parent: DEVCPU_GCB:FAN_CFG Instances: 1 Table 329 • Fields in FAN_CFG Field Name Bit Access Description Default PWM_FREQ 5:3 R/W Set the frequency of the PWM output 0x0 0: 25 kHz 1: 120 Hz 2: 100 Hz 3: 80 Hz 4: 60 Hz 5: 40 Hz 6: 20 Hz 7: 10 Hz INV_POL 2 R/W Define the polarity of the PWM output. 0: PWM is logic 1 when "on" 1: PWM is logic 0 when "on" 0x0 VMDS-10392 VSC7420-02, VSC7421-02, and VSC7422-02 Datasheet Revision 4.3 252 Registers Table 329 • Fields in FAN_CFG (continued) Field Name Bit Access Description GATE_ENA 1 R/W Enable gating of the TACH input by 0x0 the PWM output so that only TACH pulses received when PWM is "on" are counted. 0: Disabled 1: Enabled PWM_OPEN_COL_ENA 0 R/W Configure the PWM output to be open collector 0x0 DUTY_CYCLE 23:16 R/W Define the duty cycle 0x00: Always "off" 0xFF: Always "on" 0x00 7.6.12 Default DEVCPU_GCB:FAN_STAT Parent: DEVCPU_GCB Instances: 1 Table 330 • Registers in FAN_STAT Register Name Offset within Register Group Instances and Address Spacing Description Details FAN_CNT 0x00000000 1 Page 253 7.6.12.1 TACH counter DEVCPU_GCB:FAN_STAT:FAN_CNT Parent: DEVCPU_GCB:FAN_STAT Instances: 1 Table 331 • Fields in FAN_CNT Field Name Bit Access Description FAN_CNT 15:0 R/O Counts the number of rising edges 0x0000 on the TACH input. The counter is wrapping. 7.6.13 Default DEVCPU_GCB:MEMITGR Parent: DEVCPU_GCB Instances: 1 The memory integrity monitor is associated with one or more memories with build-in parity-protection and/or error-correction logic. Through the integrity monitor, address locations of failures and/or corrections can be read out. There may be more than one integrity controller in the design, also - not all memories has an associated controller. VMDS-10392 VSC7420-02, VSC7421-02, and VSC7422-02 Datasheet Revision 4.3 253 Registers Table 332 • Registers in MEMITGR Register Name Offset within Register Group Instances and Address Spacing Description Details MEMITGR_CTRL 0x00000000 1 Monitor control Page 254 MEMITGR_STAT 0x00000004 1 Monitor status Page 255 MEMITGR_INFO 0x00000008 1 Memory indication Page 255 MEMITGR_IDX 0x0000000C 1 Memory index Page 256 7.6.13.1 DEVCPU_GCB:MEMITGR:MEMITGR_CTRL Parent: DEVCPU_GCB:MEMITGR Instances: 1 Table 333 • Fields in MEMITGR_CTRL Field Name ACTIVATE Bit 0 Access One-shot Description Default Setting this field transitions the integrity monitor between operating modes. Transitioning between modes takes time, this field remains set until the new mode is reached. During this time the monitor also reports busy (MEMITGR_MODE.MODE_BUSY is set). From IDLE (MEMITGR_MODE.MODE_IDLE is set) the monitor can transition into either DETECT or LISTEN mode, the DETECT mode is entered if a memory reports an indication - the LISTEN mode is entered if no indications are reported. The first time after reset the monitor will not detect indications, that is; it will transition directly from IDLE to LISTEN mode. From DETECT (MEMITGR_MODE.MODE_DETE CT is set) the monitor can transition into either DETECT or LISTEN mode, the DETECT mode is entered if more indications are reported - the LISTEN mode is entered if no more indications are reported. From LISTEN (MEMITGR_MODE.MODE_LISTE N is set) the monitor can transition into IDLE mode. 0x0 VMDS-10392 VSC7420-02, VSC7421-02, and VSC7422-02 Datasheet Revision 4.3 254 Registers 7.6.13.2 DEVCPU_GCB:MEMITGR:MEMITGR_STAT Parent: DEVCPU_GCB:MEMITGR Instances: 1 Table 334 • Fields in MEMITGR_STAT Field Name Bit Access Description INDICATION 4 R/O 0x0 If this field is set then there is an indication from one of the memories that needs to be analyzed. An indication is either a parity detection or an error correction. This field is only set when the monitor is in LISTEN mode (MEMITGR_MODE.MODE_LISTE N is set), in all other states (including BUSY) this field returns 0. MODE_LISTEN 3 R/O This field is set when the monitor is 0x0 in LISTEN mode, during listen mode the monitor continually check for parity/correction indications from the memories. MODE_DETECT 2 R/O This field is set when the monitor is 0x0 in DETECT mode, during detect mode the MEMITGR_INFO register contains valid information about one indication. MODE_IDLE 1 R/O This field is set when the monitor is 0x1 in IDLE mode. MODE_BUSY 0 R/O 0x0 The busy signal is a copy of the MEMITGR_CTRL.ACTIVATE field, see description of that field for more information about the different states/modes of the monitor. 7.6.13.3 Default DEVCPU_GCB:MEMITGR:MEMITGR_INFO Parent: DEVCPU_GCB:MEMITGR Instances: 1 This field is only valid when the monitor is in the DETECT (MEMITGR_MODE.MODE_DETECT is set) mode. Table 335 • Fields in MEMITGR_INFO Field Name Bit Access Description Default MEM_ERR 31 R/O This field is set if the monitor has detected a parity indication (or an unrecoverable correction). 0x0 VMDS-10392 VSC7420-02, VSC7421-02, and VSC7422-02 Datasheet Revision 4.3 255 Registers Table 335 • Fields in MEMITGR_INFO (continued) Field Name Bit Access Description Default MEM_COR 30 R/O This field is set if the monitor has detected a correction. 0x0 MEM_ERR_OVF 29 R/O This field is set if the monitor has 0x0 detected a parity indication (or an unrecoverable correction) for which the address has not been recorded. If MEMITGR_INFO.MEM_ERR is set then there has been more than one indication, then only the address of the newest indication has been kept. If MEMITGR_INFO.MEM_ERR is cleared then an indication has occurred for which the address could not be stored, this is a very rare situation that can only happen if an indication is detected just as the memory is talking to the monitor. MEM_COR_OVF 28 R/O This field is set if the monitor has 0x0 correction indication for which the address has not been recorded. If MEMITGR_INFO.MEM_ERR is set then there has also been a parity indication (or an unrecoverable correction) which takes priority over correction indications. If MEMITGR_INFO.MEM_ERR is cleared and MEMITGR_INFO.MEM_COR is set then there has been more than one correction indication, then only the address of the newest correction indication has been kept. If MEMITGR_INFO.MEM_ERR and MEMITGR_INFO.MEM_COR is both cleared then a correction indication has occurred for which the address could not be stored, this is a very rare situation that can only happen if an indication is detected just as the memory is talking to the monitor. MEM_ADDR 27:0 R/O This field is valid only when MEMITGR.MEM_ERR or MEMITGR.MEM_COR is set. 7.6.13.4 0x0000000 DEVCPU_GCB:MEMITGR:MEMITGR_IDX Parent: DEVCPU_GCB:MEMITGR Instances: 1 VMDS-10392 VSC7420-02, VSC7421-02, and VSC7422-02 Datasheet Revision 4.3 256 Registers This field is only valid when the monitor is in the DETECT (MEMITGR_MODE.MODE_DETECT is set) mode. Table 336 • Fields in MEMITGR_IDX Field Name Bit Access Description Default MEM_IDX 15:0 R/O This field contains a unique index for the memory for which info is currently provided in MEMITGR_MEMINFO. Indexes are counted from 1 (not 0). 0x0000 7.7 DEVCPU_QS Table 337 • Register Groups in DEVCPU_QS 7.7.1 Offset within Register Group Name Target Instances and Address Spacing Description Details XTR 0x00000000 1 Frame Extraction Related Registers Page 257 INJ 0x00000034 1 Frame Injection Related Registers Page 260 DEVCPU_QS:XTR Parent: DEVCPU_QS Instances: 1 CPU queue system registers related to frame extraction. Table 338 • Registers in XTR 7.7.1.1 Register Name Offset within Register Group Instances and Address Spacing Description XTR_FRM_PRUNING 0x00000000 2 0x00000004 Frame Pruning Page 257 XTR_GRP_CFG 0x00000008 2 0x00000004 Group Configuration Page 258 XTR_MAP 0x00000010 2 0x00000004 Map Queue to Group Page 258 XTR_RD 0x00000018 2 0x00000004 Read from Group FIFO Page 259 XTR_QU_FLUSH 0x00000028 1 Queue Flush Page 259 XTR_DATA_PRESENT 0x0000002C 1 Extraction Status Page 260 Details DEVCPU_QS:XTR:XTR_FRM_PRUNING Parent: DEVCPU_QS:XTR VMDS-10392 VSC7420-02, VSC7421-02, and VSC7422-02 Datasheet Revision 4.3 257 Registers Instances: 2 Table 339 • Fields in XTR_FRM_PRUNING Field Name Bit Access Description Default PRUNE_SIZE 7:0 R/W Extracted frames for the corresponding queue are pruned PRUNE_SIZE 32-bit words. 0x00 Note : PRUNE_SIZE is the frame data size, including the IFH. 0 : No pruning 1: Frames extracted are pruned to 8 bytes. 2: Frames extracted are pruned to 12 bytes. . '0xFF': Frames extracted are pruned to 1024 bytes 7.7.1.2 DEVCPU_QS:XTR:XTR_GRP_CFG Parent: DEVCPU_QS:XTR Instances: 2 Table 340 • Fields in XTR_GRP_CFG 7.7.1.3 Field Name Bit Access Description Default BYTE_SWAP 0 R/W 0x1 Controls - per extraction group the byte order of the data word read in XTR_RD. When using little-Endian mode, then the first byte of the destination MAC address is placed at XTR_RD[7:0]. When using network-order, then the first byte of the destination MAC address is placed at XTR_RD[31:25]. 0: Network-order (big-endian). 1: Little-endian. STATUS_WORD_POS 1 R/W Select order of last data and status 0x1 words. 0: Status just before last data. 1: Status just after last data. DEVCPU_QS:XTR:XTR_MAP Parent: DEVCPU_QS:XTR Instances: 2 VMDS-10392 VSC7420-02, VSC7421-02, and VSC7422-02 Datasheet Revision 4.3 258 Registers Table 341 • Fields in XTR_MAP Field Name Bit Access Description Default GRP 4 R/W Maps a queue to a certain extractor group 0x0 MAP_ENA 0 R/W Enables extraction of a queue. 0x0 Disabling of extraction for a queue happens upon next frame boundary. That is, a frame being extracted at the time of queue disabling is not affected. '0' : Queue is not mapped to a queue group ( queue is disabled ) '1' : Queue is mapped to the queue group defined by XTR::XTR_MAP ( queue is enabled ) 7.7.1.4 DEVCPU_QS:XTR:XTR_RD Parent: DEVCPU_QS:XTR Instances: 2 Table 342 • Fields in XTR_RD 7.7.1.5 Field Name Bit Access Description Default DATA 31:0 R/O 0x00000000 Frame Data. Read from this register to obtain the next 32 bits of the frame data currently stored in the CPU queue system. Each read must check for the special values "0x8000000n", 0