VSC8552XKS-02

VSC8552-02 Datasheet Dual-Port 10/100/1000BASE-T PHY with Synchronous Ethernet and QSGMII/SGMII/RGMII MAC Microsemi Headquarters One Enterprise, Aliso Viejo, CA 92656 USA Within the USA: +1 (800) 713-4113 Outside the USA: +1 (949) 380-6100 Sales: +1 (949) 380-6136 Fax: +1 (949) 215-4996 Email: sales.support@microsemi.com www.microsemi.com ©2018 Microsemi, a wholly owned subsidiary of Microchip Technology Inc. All rights reserved. Microsemi and the Microsemi logo are registered trademarks of Microsemi Corporation. All other trademarks and service marks are the property of their respective owners. Microsemi makes no warranty, representation, or guarantee regarding the information contained herein or the suitability of its products and services for any particular purpose, nor does Microsemi assume any liability whatsoever arising out of the application or use of any product or circuit. The products sold hereunder and any other products sold by Microsemi have been subject to limited testing and should not be used in conjunction with mission-critical equipment or applications. Any performance specifications are believed to be reliable but are not verified, and Buyer must conduct and complete all performance and other testing of the products, alone and together with, or installed in, any end-products. Buyer shall not rely on any data and performance specifications or parameters provided by Microsemi. It is the Buyer’s responsibility to independently determine suitability of any products and to test and verify the same. The information provided by Microsemi hereunder is provided “as is, where is” and with all faults, and the entire risk associated with such information is entirely with the Buyer. Microsemi does not grant, explicitly or implicitly, to any party any patent rights, licenses, or any other IP rights, whether with regard to such information itself or anything described by such information. Information provided in this document is proprietary to Microsemi, and Microsemi reserves the right to make any changes to the information in this document or to any products and services at any time without notice. About Microsemi Microsemi, a wholly owned subsidiary of Microchip Technology Inc. (Nasdaq: MCHP), offers a comprehensive portfolio of semiconductor and system solutions for aerospace & defense, communications, data center and industrial markets. Products include high-performance and radiation-hardened analog mixed-signal integrated circuits, FPGAs, SoCs and ASICs; power management products; timing and synchronization devices and precise time solutions, setting the world's standard for time; voice processing devices; RF solutions; discrete components; enterprise storage and communication solutions, security technologies and scalable anti-tamper products; Ethernet solutions; Power-over-Ethernet ICs and midspans; as well as custom design capabilities and services. Learn more at www.microsemi.com. VMDS-10508. 4.2 2/19 Contents 1 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.1 1.2 1.3 1.4 Revision 4.2 Revision 4.1 Revision 4.0 Revision 2.0 ....................................................................... ....................................................................... ....................................................................... ....................................................................... 1 1 1 1 2 Product Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2.1 2.2 Key Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.1.1 Low Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.1.2 Advanced Carrier Ethernet Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.1.3 Wide Range of Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.1.4 Flexibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 3 3 3 3 4 3 Functional Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3.1.1 QSGMII/SGMII MAC-to-1000BASE-X Link Partner . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3.1.2 QSGMII/SGMII MAC-to-100BASE-FX Link Partner . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3.1.3 QSGMII/SGMII MAC-to-AMS and 1000BASE-X Media SerDes . . . . . . . . . . . . . . . . . . . . . . . . 7 3.1.4 QSGMII/SGMII MAC-to-AMS and 100BASE-FX Media SerDes . . . . . . . . . . . . . . . . . . . . . . . . 8 3.1.5 QSGMII/SGMII MAC-to-AMS and Protocol Transfer Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3.1.6 QSGMII/SGMII MAC-to-Cat5 Link Partner . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.1.7 QSGMII/SGMII MAC-to-Protocol Transfer Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.1.8 1000BASE-X MAC-to-Cat5 Link Partner . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 RGMII MAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 SerDes MAC Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.3.1 SerDes MAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.3.2 SGMII MAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.3.3 QSGMII MAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 SerDes Media Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.4.1 QSGMII/RGMII/SGMII to 1000BASE-X . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.4.2 QSGMII/RGMII/SGMII to 100BASE-FX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.4.3 QSGMII to SGMII Protocol Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.4.4 Unidirectional Transport for Fiber Media . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 PHY Addressing and Port Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.5.1 PHY Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.5.2 SerDes Port Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Cat5 Twisted Pair Media Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.6.1 Voltage Mode Line Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.6.2 Cat5 Autonegotiation and Parallel Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.6.3 Automatic Crossover and Polarity Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.6.4 Manual HP Auto-MDIX Setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.6.5 Link Speed Downshift . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.6.6 Energy Efficient Ethernet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.6.7 Ring Resiliency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Automatic Media Sense Interface Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Reference Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.8.1 Configuring the Reference Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.8.2 Single-Ended REFCLK Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.8.3 Differential REFCLK Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Ethernet Inline Powered Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 VMDS-10508 VSC8552-02 Datasheet Revision 4.2 iii 3.10 3.11 3.12 3.13 3.14 3.15 3.16 3.17 3.18 3.19 3.20 IEEE 802.3af PoE Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 ActiPHY Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.11.1 Low Power State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.11.2 Link Partner Wake-Up State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.11.3 Normal Operating State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Media Recovered Clock Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.12.1 Clock Selection Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.12.2 Clock Output Squelch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Serial Management Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.13.1 SMI Frames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.13.2 SMI Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 LED Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.14.1 LED Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.14.2 Extended LED Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 3.14.3 LED Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 3.14.4 Basic Serial LED Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 3.14.5 Enhanced Serial LED Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 3.14.6 LED Port Swapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Fast Link Failure Indication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Integrated Two-Wire Serial Multiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 3.16.1 Read/Write Access Using the Two-Wire Serial MUX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 GPIO Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Testing Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 3.18.1 Ethernet Packet Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 3.18.2 CRC Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 3.18.3 Far-End Loopback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 3.18.4 Near-End Loopback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 3.18.5 Connector Loopback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 3.18.6 SerDes Loopbacks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 3.18.7 VeriPHY Cable Diagnostics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 3.18.8 JTAG Boundary Scan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 3.18.9 JTAG Instruction Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 3.18.10 Boundary Scan Register Cell Order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 100BASE-FX Halt Code Transmission and Reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 3.20.1 Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 4 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 4.1 4.2 Register and Bit Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IEEE 802.3 and Main Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2.1 Mode Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2.2 Mode Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2.3 Device Identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2.4 Autonegotiation Advertisement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2.5 Link Partner Autonegotiation Capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2.6 Autonegotiation Expansion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2.7 Transmit Autonegotiation Next Page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2.8 Autonegotiation Link Partner Next Page Receive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2.9 1000BASE-T Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2.10 1000BASE-T Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2.11 MMD Access Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2.12 MMD Address or Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2.13 1000BASE-T Status Extension 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2.14 100BASE-TX/FX Status Extension . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2.15 1000BASE-T Status Extension 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2.16 Bypass Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VMDS-10508 VSC8552-02 Datasheet Revision 4.2 44 45 46 47 48 48 49 49 50 50 50 51 52 52 52 52 53 54 iv 4.3 4.4 4.5 4.6 4.7 4.2.17 Error Counter 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 4.2.18 Error Counter 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 4.2.19 Error Counter 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 4.2.20 Extended Control and Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 4.2.21 Extended PHY Control Set 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 4.2.22 Extended PHY Control Set 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 4.2.23 Interrupt Mask . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 4.2.24 Interrupt Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 4.2.25 Device Auxiliary Control and Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 4.2.26 LED Mode Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 4.2.27 LED Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 4.2.28 Extended Page Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Extended Page 1 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 4.3.1 SerDes Media Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 4.3.2 Cu Media CRC Good Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 4.3.3 Extended Mode Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 4.3.4 ActiPHY Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 4.3.5 PoE and Miscellaneous Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 4.3.6 Ethernet Packet Generator Control 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 4.3.7 Ethernet Packet Generator Control 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Extended Page 2 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 4.4.1 Cu PMD Transmit Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 4.4.2 EEE Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 4.4.3 RGMII Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 4.4.4 Ring Resiliency Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Extended Page 3 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 4.5.1 MAC SerDes PCS Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 4.5.2 MAC SerDes PCS Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 4.5.3 MAC SerDes Clause 37 Advertised Ability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 4.5.4 MAC SerDes Clause 37 Link Partner Ability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 4.5.5 MAC SerDes Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 4.5.6 Media SerDes Transmit Good Packet Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 4.5.7 Media SerDes Transmit CRC Error Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 4.5.8 Media SerDes PCS Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 4.5.9 Media SerDes PCS Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 4.5.10 Media SerDes Clause 37 Advertised Ability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 4.5.11 Media SerDes Clause 37 Link Partner Ability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 4.5.12 Media SerDes Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 4.5.13 Fiber Media CRC Good Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 4.5.14 Fiber Media CRC Error Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 General Purpose Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 4.6.1 Reserved General Purpose Address Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 4.6.2 SIGDET/GPIO Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 4.6.3 GPIO Control 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 4.6.4 GPIO Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 4.6.5 GPIO Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 4.6.6 GPIO Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 4.6.7 Microprocessor Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 4.6.8 MAC Configuration and Fast Link . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 4.6.9 Two-Wire Serial MUX Control 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 4.6.10 Two-Wire Serial MUX Control 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 4.6.11 Two-Wire Serial MUX Data Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 4.6.12 Recovered Clock 1 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 4.6.13 Recovered Clock 2 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 4.6.14 Enhanced LED Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 4.6.15 Global Interrupt Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 4.6.16 Extended Revision ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 Clause 45 Registers to Support Energy Efficient Ethernet and 802.3bf . . . . . . . . . . . . . . . . . . . . . . . . 87 VMDS-10508 VSC8552-02 Datasheet Revision 4.2 v 4.7.1 4.7.2 4.7.3 4.7.4 4.7.5 PCS Status 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EEE Capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EEE Wake Error Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EEE Advertisement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EEE Link Partner Advertisement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 88 88 89 89 5 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 5.1 5.2 5.3 5.4 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 5.1.1 VDD25 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 5.1.2 LED and GPIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 5.1.3 Internal Pull-Up or Pull-Down Resistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 5.1.4 Reference Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 5.1.5 SerDes Interface (SGMII) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 5.1.6 Enhanced SerDes Interface (QSGMII) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 5.1.7 Current Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 5.1.8 Thermal Diode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 5.2.1 Reference Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 5.2.2 Recovered Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 5.2.3 SerDes Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 5.2.4 SerDes Driver Jitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 5.2.5 SerDes Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 5.2.6 SerDes Receiver Jitter Tolerance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 5.2.7 Enhanced SerDes Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 5.2.8 Basic Serial LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 5.2.9 Enhanced Serial LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 5.2.10 JTAG Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 5.2.11 RGMII, Uncompensated . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 5.2.12 RGMII, Compensated . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 5.2.13 Serial Management Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 5.2.14 Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 Stress Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 6 Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 6.1 6.2 6.3 Pin Identifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pins by Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.3.1 GPIO and SIGDET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.3.2 JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.3.3 Miscellaneous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.3.4 Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.3.5 SGMII/SerDes/QSGMII MAC Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.3.6 SerDes Media Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.3.7 Serial Management Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.3.8 Twisted Pair Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 110 112 113 113 113 114 117 117 118 118 7 Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 7.1 7.2 7.3 Package Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 Thermal Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 Moisture Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 8 Design Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 8.1 8.2 8.3 Link status LED remains on while COMA_MODE pin is asserted high . . . . . . . . . . . . . . . . . . . . . . . . 122 LED pulse stretch enable turns off LED pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 AMS and 100BASE-FX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 VMDS-10508 VSC8552-02 Datasheet Revision 4.2 vi 8.4 8.5 8.6 8.7 8.8 8.9 8.10 8.11 8.12 8.13 8.14 8.15 8.16 8.17 8.18 8.19 8.20 8.21 10BASE-T signal amplitude . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 10BASE-T link recovery failures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 SNR degradation and link drops . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 Clause 45 register 3.22 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 Clause 45 register 3.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 Clause 45 register address post-increment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 Fast link failure indication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 Near-end loopback with AMS enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 Carrier detect assertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 Link status not correct in register 24E3.2 for 100BASE-FX operation . . . . . . . . . . . . . . . . . . . . . . . . . 123 Register 28.14 does not reflect autonegotiation disabled in 100BASE-FX mode . . . . . . . . . . . . . . . . 123 Near-end loopback non-functional in protocol transfer mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 Fiber-media CRC counters non-functional in protocol transfer mode at 10 Mbps and 100 Mbps . . . . 124 Fiber-media recovered clock does not squelch based on link status . . . . . . . . . . . . . . . . . . . . . . . . . . 124 1000BASE-X parallel detect mode with Clause 37 autonegotiation enabled . . . . . . . . . . . . . . . . . . . . 124 Anomalous PCS error indications in Energy Efficient Ethernet mode . . . . . . . . . . . . . . . . . . . . . . . . . 124 Long link-up times while in forced 100BASE-TX mode of operation . . . . . . . . . . . . . . . . . . . . . . . . . . 124 Station managers cannot use MDIO address offsets 0x2 and 0x3 with the PHY . . . . . . . . . . . . . . . . 125 9 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 VMDS-10508 VSC8552-02 Datasheet Revision 4.2 vii Figures Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 Figure 8 Figure 9 Figure 10 Figure 11 Figure 12 Figure 13 Figure 14 Figure 15 Figure 16 Figure 17 Figure 18 Figure 19 Figure 20 Figure 21 Figure 22 Figure 23 Figure 24 Figure 25 Figure 26 Figure 27 Figure 28 Figure 29 Figure 30 Figure 31 Figure 32 Figure 33 Figure 34 Figure 35 Figure 36 Figure 37 Figure 38 Figure 39 Figure 40 Figure 41 Figure 42 Figure 43 Figure 44 Figure 45 Figure 46 Figure 47 Figure 48 Figure 49 Figure 50 Figure 51 Figure 52 Figure 53 Figure 54 Dual Media Application Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Copper Transceiver Application Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Fiber Media Transceiver Application Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 SGMII MAC-to-1000BASE-X Link Partner . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 QSGMII MAC-to-1000BASE-X Link Partner . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 QSGMII/SGMII MAC-to-100BASE-FX Link Partner . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 QSGMII/SGMII MAC-to-AMS and 1000BASE-X Media SerDes . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 QSGMII/SGMII MAC-to-AMS and 100BASE-FX Media SerDes . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 QSGMII/SGMII MAC-to-AMS and Protocol Transfer Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 QSGMII/SGMII MAC-to-Cat5 Link Partner . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 QSGMII/SGMII MAC-to-Protocol Transfer Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 1000BASE-X MAC-to-Cat5 Link Partner . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 RGMII MAC Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 SerDes MAC Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 SGMII MAC Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 QSGMII MAC Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Cat5 Media Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Low Power Idle Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Automatic Media Sense Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.5 V CMOS Single-Ended REFCLK Input Resistor Network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.3 V CMOS Single-Ended REFCLK Input Resistor Network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 5 V CMOS Single-Ended REFCLK Input Resistor Network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 AC Coupling for REFCLK Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Inline Powered Ethernet Switch Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 ActiPHY State Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 SMI Read Frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 SMI Write Frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 MDINT Configured as an Open-Drain (Active-Low) Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 MDINT Configured as an Open-Source (Active-High) Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Two-Wire Serial MUX with SFP Control and Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Two-Wire Serial MUX Read and Write Register Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Far-End Loopback Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Near-End Loopback Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Connector Loopback Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Data Loops of the SerDes Macro . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Test Access Port and Boundary Scan Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Register Space Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 SGMII DC Transmit Test Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 SGMII DC Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 SGMII DC Driver Output Impedance Test Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 SGMII DC Input Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 Test Circuit for Recovered Clock Output Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 QSGMII Transient Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 Basic Serial LED Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 Enhanced Serial LED Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 JTAG Interface Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 Test Circuit for TDO Disable Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 Test Circuit for RGMII Output Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 RGMII Uncompensated Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 Compensated Input RGMII Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 Compensated Output RGMII Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 Serial Management Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 Pin Diagram, Top Left . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 VMDS-10508 VSC8552-02 Datasheet Revision 4.2 viii Figure 55 Figure 56 Pin Diagram, Top Right . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 Package Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 VMDS-10508 VSC8552-02 Datasheet Revision 4.2 ix Tables Table 1 Table 2 Table 3 Table 4 Table 5 Table 6 Table 7 Table 8 Table 9 Table 10 Table 11 Table 12 Table 13 Table 14 Table 15 Table 16 Table 17 Table 18 Table 19 Table 20 Table 21 Table 22 Table 23 Table 24 Table 25 Table 26 Table 27 Table 28 Table 29 Table 30 Table 31 Table 32 Table 33 Table 34 Table 35 Table 36 Table 37 Table 38 Table 39 Table 40 Table 41 Table 42 Table 43 Table 44 Table 45 Table 46 Table 47 Table 48 Table 49 Table 50 Table 51 Table 52 Table 53 Table 54 Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 MAC Interface Mode Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Supported MDI Pair Combinations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 AMS Media Preferences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 REFCLK Frequency Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 LED Drive State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 LED Mode and Function Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Extended LED Mode and Function Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 LED Serial Bitstream Order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Register Bits for GPIO Control and Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 SerDes Macro Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 JTAG Instruction Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 IDCODE JTAG Device Identification Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 USERCODE JTAG Device Identification Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 JTAG Instruction Code IEEE Compliance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Register 18E2 Settings for RGMII . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 IEEE 802.3 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Main Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Mode Control, Address 0 (0x00) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Mode Status, Address 1 (0x01) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Identifier 1, Address 2 (0x02) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Identifier 2, Address 3 (0x03) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Device Autonegotiation Advertisement, Address 4 (0x04) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Autonegotiation Link Partner Ability, Address 5 (0x05) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Autonegotiation Expansion, Address 6 (0x06) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Autonegotiation Next Page Transmit, Address 7 (0x07) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Autonegotiation LP Next Page Receive, Address 8 (0x08) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 1000BASE-T Control, Address 9 (0x09) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 1000BASE-T Status, Address 10 (0x0A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 MMD EEE Access, Address 13 (0x0D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 MMD Address or Data Register, Address 14 (0x0E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 1000BASE-T Status Extension 1, Address 15 (0x0F) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 100BASE-TX/FX Status Extension, Address 16 (0x10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 1000BASE-T Status Extension 2, Address 17 (0x11) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Bypass Control, Address 18 (0x12) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Error Counter 1, Address 19 (0x13) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Error Counter 2, Address 20 (0x14) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Error Counter 3, Address 21 (0x15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Extended Control and Status, Address 22 (0x16) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Extended PHY Control 1, Address 23 (0x17) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Extended PHY Control 2, Address 24 (0x18) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Interrupt Mask, Address 25 (0x19) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Interrupt Status, Address 26 (0x1A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Auxiliary Control and Status, Address 28 (0x1C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 LED Mode Select, Address 29 (0x1D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 LED Behavior, Address 30 (0x1E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Extended/GPIO Register Page Access, Address 31 (0x1F) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Extended Registers Page 1 Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 SerDes Media Control, Address 16E1 (0x10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Cu Media CRC Good Counter, Address 18E1 (0x12) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Extended Mode Control, Address 19E1 (0x13) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Extended PHY Control 3, Address 20E1 (0x14) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Extended PHY Control 4, Address 23E1 (0x17) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 EPG Control Register 1, Address 29E1 (0x1D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 VMDS-10508 VSC8552-02 Datasheet Revision 4.2 x Table 55 Table 56 Table 57 Table 58 Table 59 Table 60 Table 61 Table 62 Table 63 Table 64 Table 65 Table 66 Table 67 Table 68 Table 69 Table 70 Table 71 Table 72 Table 73 Table 74 Table 75 Table 76 Table 77 Table 78 Table 79 Table 80 Table 81 Table 82 Table 83 Table 84 Table 85 Table 86 Table 87 Table 88 Table 89 Table 90 Table 91 Table 92 Table 93 Table 94 Table 95 Table 96 Table 97 Table 98 Table 99 Table 100 Table 101 Table 102 Table 103 Table 104 Table 105 Table 106 Table 107 Table 108 Table 109 Table 110 Table 111 Table 112 Table 113 EPG Control Register 2, Address 30E1 (0x1E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Extended Registers Page 2 Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Cu PMD Transmit Control, Address 16E2 (0x10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 EEE Control, Address 17E2 (0x11) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 RGMII Settings, Address 18E2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Ring Resiliency, Address 30E2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Extended Registers Page 3 Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 MAC SerDes PCS Control, Address 16E3 (0x10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 MAC SerDes PCS Status, Address 17E3 (0x11) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 MAC SerDes Cl37 Advertised Ability, Address 18E3 (0x12) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 MAC SerDes Cl37 LP Ability, Address 19E3 (0x13) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 MAC SerDes Status, Address 20E3 (0x14) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Media SerDes Tx Good Packet Counter, Address 21E3 (0x15) . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Media SerDes Tx CRC Error Counter, Address 22E3 (0x16) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Media SerDes PCS Control, Address 23E3 (0x17) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Media SerDes PCS Status, Address 24E3 (0x18) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 Media SerDes Cl37 Advertised Ability, Address 25E3 (0x19) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 MAC SerDes Cl37 LP Ability, Address 26E3 (0x1A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 Media SerDes Status, Address 27E3 (0x1B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 Fiber Media CRC Good Counter, Address 28E3 (0x1C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 Fiber Media CRC Error Counter, Address 29E3 (0x1D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 General Purpose Registers Page Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 SIGDET/GPIO Control, Address 13G (0x0D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 GPIO Control 2, Address 14G (0x0E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 GPIO Input, Address 15G (0x0F) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 GPIO Output, Address 16G (0x10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 GPIO Input/Output Configuration, Address 17G (0x11) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 Microprocessor Command Register, Address 18G . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 MAC Configuration and Fast Link Register, Address 19G (0x13) . . . . . . . . . . . . . . . . . . . . . . . . . 82 Two-Wire Serial MUX Control 1, Address 20G (0x14) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 Two-Wire Serial MUX Interface Status and Control, Address 21G (0x15) . . . . . . . . . . . . . . . . . . . 83 Two-Wire Serial MUX Data Read/Write, Address 22G (0x16) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 Recovered Clock 1 Control, Address 23G (0x17) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 Recovered Clock 2 Control, Address 24G (0x18) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 Enhanced LED Control, Address 25G (0x19) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 Global Interrupt Status, Address 29G (0x1D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 Extended Revision ID, Address 30G (0x1E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 Clause 45 Registers Page Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 PCS Status 1, Address 3.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 EEE Capability, Address 3.20 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 EEE Wake Error Counter, Address 3.22 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 EEE Advertisement, Address 7.60 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 EEE Advertisement, Address 7.61 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 802.3bf Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 VDD25 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 LED and GPIO Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 Internal Pull-Up or Pull-Down Resistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 Reference Clock DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 SerDes Driver DC Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 SerDes Receiver DC Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 Enhanced SerDes Driver DC Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 Enhanced SerDes Receiver DC Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 Current Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 Thermal Diode Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 Reference Clock AC Characteristics for QSGMII 125 MHz Differential Clock . . . . . . . . . . . . . . . . 97 Recovered Clock AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 SerDes Outputs AC Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 SerDes Driver Jitter Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 SerDes Input AC Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 VMDS-10508 VSC8552-02 Datasheet Revision 4.2 xi Table 114 Table 115 Table 116 Table 117 Table 118 Table 119 Table 120 Table 121 Table 122 Table 123 Table 124 Table 125 Table 126 Table 127 Table 128 Table 129 Table 130 Table 131 Table 132 Table 133 Table 134 Table 135 Table 136 Table 137 Table 138 Table 139 Table 140 Table 141 Table 142 SerDes Receiver Jitter Tolerance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 Enhanced SerDes Outputs AC Specifications, SGMII Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 Enhanced SerDes Outputs AC Specifications, QSGMII Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 Enhanced SerDes Driver Jitter Characteristics, QSGMII Mode . . . . . . . . . . . . . . . . . . . . . . . . . . 101 Enhanced SerDes Input AC Specifications, SGMII Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 Enhanced SerDes Inputs AC Specifications, QSGMII Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 Enhanced SerDes Receiver Jitter Tolerance, QSGMII Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 Basic Serial LEDs AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 Enhanced Serial LEDs AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 JTAG Interface AC Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 AC Characteristics for RGMII Uncompensated . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 PHY Input (RGMIIn_TXCLK Delay When Register 18E2.[6:4]=011’b) . . . . . . . . . . . . . . . . . . . . . 106 PHY Output (RGMIIn_RXCLK Delay When Register 18E2.[3:1]=100’b) . . . . . . . . . . . . . . . . . . . 107 Serial Management Interface AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 Reset Timing Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 Stress Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 Pin Type Symbol Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 GPIO and SIGDET Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 JTAG Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 Miscellaneous Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 Power Supply Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 RGMII Interface Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 SerDes MAC Interface Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 SerDes Media Interface Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 SMI Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 Twisted Pair Interface Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 Thermal Resistances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 VMDS-10508 VSC8552-02 Datasheet Revision 4.2 xii Revision History 1 Revision History This section describes the changes that were implemented in this document. The changes are listed by revision, starting with the most current publication. 1.1 Revision 4.2 Revision 4.2 of this datasheet was published in February 2019. In revision 4.2, VeriPHY descriptions were updated and VeriPHY register information was deleted. For functional details of the VeriPHY suite and the operating instructions, see the ENT-AN0125 PHY, Integrated PHY-Switch VeriPHY - Cable Diagnostics application note. 1.2 Revision 4.1 Revision 4.1 was published in May 2018. The following is a summary of the changes in revision 4.1 of this document. • • • • 1.3 Configuration procedure steps were clarified. For more information, see Configuration, page 42. The description of bit 10 was updated for register 0. For more information, see Table 19, page 46. The description of bit 0 was updated for register 22. For more information, see Extended Control and Status, page 55. Design considerations were updated. For more information, see Design Considerations, page 122. Revision 4.0 Revision 4.0 was published in November 2017. The following is a summary of the changes in revision 4.0 of this document. • • • • • • • • • • • • • • • 1.4 A note was added about enhanced serial LED mode using the VDD LED drive state. Details about LED pulsing were updated. Information on enabling the serial clock was added. Register bits were designated as “sticky” where appropriate. A footnote was added about the fast link failure interrupt mask. The default for the ring resiliency status bits 4:4 was updated from 00 to 11. The default value for the MAC SerDes clause 37 advertised ability register was updated from 0x0000 to 0x01E0. Footnotes regarding required register clears were added to the SIGDET/GPIO control register. All GPIO input register bits marked as read-only and defaults updated. Global interrupt status register defaults were added. Register 30G changed from reserved to extended revision ID register. Current consumption values were updated. Some parameter names and conditions for recovered clock AC characteristics were updated. Product SKUs in the package section were corrected to match the ordering information. Design considerations were removed and new ones added to correctly reflect device functionality. Revision 2.0 Revision 2.0 of this datasheet was published in September 2017. This was the first publication of the document. VMDS-10508 VSC8552-02 Datasheet Revision 4.2 1 Product Overview 2 Product Overview The VSC8552-02 is a low-power, dual-port Gigabit Ethernet transceiver with two SerDes interfaces for dual-port dual media capability. It also includes an integrated dual port two-wire serial multiplexer (MUX) to control SFPs or PoE modules. It has a low electromagnetic interference (EMI) line driver, and integrated line side termination resistors that conserve both power and printed circuit board (PCB) space. The VSC8552-02 includes dual recovered clock outputs to support Synchronous Ethernet applications. Programmable clock squelch control is included to inhibit undesirable clocks from propagating and to help prevent timing loops. The VSC8552-02 also supports a ring resiliency feature that allows a 1000BASE-T connected PHY port to switch between master and slave timing without having to interrupt the 1000BASE-T link. Using Microsemi’s EcoEthernet v2.0 PHY technology, the VSC8552-02 supports energy efficiency features such as Energy Efficient Ethernet (EEE), ActiPHY link down power savings, and PerfectReach that can adjust power based on the cable length. It also supports fully optimized power consumption in all link speeds. Microsemi's mixed signal and digital signal processing (DSP) architecture is a key operational feature of the VSC8552-02, assuring robust performance even under less-than-favorable environmental conditions. It supports both half-duplex and full-duplex 10BASE-T, 100BASE-TX, and 1000BASE-T communication speeds over Category 5 (Cat5) unshielded twisted pair (UTP) cable at distances greater than 100 m, displaying excellent tolerance to NEXT, FEXT, echo, and other types of ambient environmental and system electronic noise. The device also supports two dual media ports that can support up to two 100BASE-FX, 1000BASE-X fiber, and/or triple-speed copper SFPs. The following illustrations show a high-level, general view of typical VSC8552-02 applications. Figure 1 • Dual Media Application Diagram ½ QSGMII, 2x RGMII, 2x SGMII, or 2x 1000BASE-X MAC ½ QSGMII, 2x RGMII, 2x SGMII MAC, or 2x 1000BASE-X MAC Figure 2 • 1.0 V 2.5 V 2× RJ-45 and Magnetics VSC8552-02 2 ports dual media (fiber or copper) RGMII, SGMII, half QSGMII MAC interface SerDes SCL/SDA 2× SFPs (fiber or copper) Copper Transceiver Application Diagram ½ QSGMII, 2x RGMII, 2x SGMII, or 2x 1000BASE-X MAC ½ QSGMII, 2x RGMII, 2x SGMII MAC, or 2x 1000BASE-X MAC 1.0 V 2.5 V VSC8552-02 2 ports copper media RGMII, SGMII, half QSGMII MAC interface VMDS-10508 VSC8552-02 Datasheet Revision 4.2 2× RJ-45 and Magnetics 2 Product Overview Figure 3 • Fiber Media Transceiver Application Diagram ½ QSGMII, 2x RGMII, 2x SGMII, or 2x 1000BASE-X MAC 2.5 V VSC8552-02 ½ QSGMII, 2x RGMII, 2x SGMII MAC, or 2x 1000BASE-X MAC 2.1 1.0 V 2 ports fiber media RGMII, SGMII, half QSGMII MAC interface 4× 1000BASE-X SFP or 4x 100BASE-FX SFP Key Features This section lists the main features and benefits of the VSC8552-02 device. 2.1.1 Low Power • • • • 2.1.2 Advanced Carrier Ethernet Support • • • • • 2.1.3 Recovered clock outputs with programmable clock squelch control and fast link failure indication (> 16) PhyWrite(, 18, reg18); PhyWrite(, 17, patternset[i] & 0xffff); PhyWrite(, 16, 0x8c84); PhyWrite(, 16, 0xbe84); // Dummy read to clear latched mismatch PhyWrite(, 16, 0xbe84); // Read pattern check failure status matchfailed = PhyRead(, 17) & 1; // Extract pattern check failure status } Turning off the pattern checker: PhyWrite(, 16, 0xbe80); reg18 = PhyRead(, 18); reg17 = PhyRead(, 17); reg17 = reg17 & ~4; PhyWrite(, 18, reg18); PhyWrite(, 17, reg17); PhyWrite(, 16, 0x9e80); PhyWrite(, 31, 0); HALT_codeword_detected =!matchfailed; 3.20 Configuration The VSC8552-02 can be configured by setting internal memory registers using the management interface. To configure the device, perform the following steps: 1. 2. 3. 4. 5. 6. 7. 8. COMA_MODE active, drive high (optional). Apply power. Apply RefClk. Release reset, drive high. Power and clock must be stable before releasing reset. Wait 120 ms minimum. Apply patch from PHY_API (required for production released optional for board testing). Configure register 19G for MAC mode (to access register 19G, register 31 must be 0x10). Read register 19G. Set bits 15:14, MAC configuration as follows: 00: SGMII 01: QSGMII 10: RGMII 11: Reserved Write new register 19G. Set RGMII (optional) Table 16 • Register 18E2 Settings for RGMII Bit Name Setting 6:4 rgmii_skew_tx 000 3:1 rgmii_skew_rx 000 0 rgmii_bit_rev 0 VMDS-10508 VSC8552-02 Datasheet Revision 4.2 42 Functional Descriptions 9. Configure register 18G for MAC on all 4 PHYs write: SGMII: 0x80F0 QSGMII: 0x80E0 RGMII: set 19G[15:14] = 0x10 to set PHY0 and PHY1 MAC to be RGMII 10. Read register 18G until bit 15 equals 0. 11. If Fiber Media on all 4 PHYs configure register 18G by writing: Media 1000BASE-X: 0x8FC1 Media 100BASE-FX: 0x8FD1 12. If Fiber Media read register 18G till bit 15 equals 0. 13. Configure register 23 for MAC and Media mode (to access register 23, register 31 must be 0). Read register 23. Set bits 10:8 as follows: 000: Copper 010: 1000BASE-X 011: 100BASE-FX Write new register 23. 14. Software reset. Read register 0 (to access register 0, register 31 must be 0). Set bit 15 to 1. Write new register 0. 15. Read register 0 until bit 15 equals 0. 16. Release the COMA_MODE pin, drive low (only necessary if COMA_MODE pin is driven high or unconnected). Note: All MAC interfaces must be the same — all QSGMII, RGMII, or SGMII. 3.20.1 Initialization The COMA_MODE pin provides an optional feature that may be used to control when the PHYs become active. The typical usage is to keep the PHYs from becoming active before they have been fully initialized. For more information, see Configuration, page 42. By not being active until after complete initialization keeps links from going up and down. Alternatively the COMA_MODE pin may be connected low (ground) and the PHYs will be fully active once out of reset. VMDS-10508 VSC8552-02 Datasheet Revision 4.2 43 Registers 4 Registers This section provides information about how to configure the VSC8552-02 using its internal memory registers and the management interface. The registers marked reserved and factory test should not be read or written to, because doing so may produce undesired effects. The default value documented for registers is based on the value at reset; however, in some cases, that value may change immediately after reset. The access type for each register is shown using the following abbreviations: • • • • • • RO: Read Only ROCR: Read Only, Clear on Read RO/LH: Read Only, Latch High RO/LL: Read Only, Latch Low R/W: Read and Write RWSC: Read Write Self Clearing The VSC8552-02 uses several different types of registers: • • • • IEEE Clause 22 device registers with addresses from 0 to 31 Three pages of extended registers with addresses from 16E1–30E1, 16E2–30E2, and 16E3–30E3 General-purpose registers with addresses from 0G to 30G IEEE Clause 45 devices registers accessible through the Clause 22 registers 13 and 14 to support IEEE 802.3az-2010 energy efficient Ethernet registers The following illustration shows the relationship between the device registers and their address spaces. Figure 38 • Register Space Diagram 0 1 2 3 . . . 13 14 15 0G 1G 2G 3G . . . . . 15G Clause 45 Registers IEEE 802.3 Standard Registers General Purpose Registers 16 17 18 19 . . . . . 30 Main Registers 31 0x0000 16E1 17E1 18E1 19E1 . . . . . 30E1 Extended Registers 1 0x0001 16E2 17E2 18E2 19E2 . . . . . 30E2 Extended Registers 2 0x0002 16E3 17E3 18E3 19E3 . . . . . 30E3 Extended Registers 3 0x0003 16G 17G 18G 19G . . . . . 30G 0x0010 Reserved Registers—For main registers 16–31, extended registers 16E1–30E1, 16E2–30E2, 16E3– 30E3, and general purpose registers 0G–30G, any bits marked as Reserved should be processed as read-only and their states as undefined. Reserved Bits—In writing to registers with reserved bits, use a read-modify-then-write technique, where the entire register is read but only the intended bits to be changed are modified. Reserved bits cannot be changed and their read state cannot be considered static or unchanging. 4.1 Register and Bit Conventions Registers are referred to by their address and bit number in decimal notation. A range of bits is indicated with a colon. For example, a reference to address 26, bits 15 through 14 is shown as 26.15:14. A register with an E and a number attached (example 27E1) means it is a register contained within extended register page number 1. A register with a G attached (example 13G) means it is a GPIO page register. VMDS-10508 VSC8552-02 Datasheet Revision 4.2 44 Registers Bit numbering follows the IEEE standard with bit 15 being the most significant bit and bit 0 being the least significant bit. 4.2 IEEE 802.3 and Main Registers In the VSC8552-02, the page space of the standard registers consists of the IEEE 802.3 standard registers and the Microsemi standard registers. The following table lists the names of the registers associated with the addresses as specified by IEEE 802.3. Table 17 • IEEE 802.3 Registers Address Name 0 Mode Control 1 Mode Status 2 PHY Identifier 1 3 PHY Identifier 2 4 Autonegotiation Advertisement 5 Autonegotiation Link Partner Ability 6 Autonegotiation Expansion 7 Autonegotiation Next-Page Transmit 8 Autonegotiation Link Partner Next-Page Receive 9 1000BASE-T Control 10 1000BASE-T Status 11–12 Reserved 13 Clause 45 Access Registers from IEEE 802.3 Table 22-6 and 22.24.3.11-12 and Annex 22D 14 Clause 45 Access Registers from IEEE 802.3 Table 22-6 and 22.24.3.11-12 and Annex 22D 15 1000BASE-T Status Extension 1 The following table lists the names of the registers in the main page space of the device. These registers are accessible only when register address 31 is set to 0x0000. Table 18 • Main Registers Address Name 16 100BASE-TX status extension 17 1000BASE-T status extension 2 18 Bypass control 19 Error Counter 1 20 Error Counter 2 21 Error Counter 3 22 Extended control and status 23 Extended PHY control 1 24 Extended PHY control 2 25 Interrupt mask 26 Interrupt status VMDS-10508 VSC8552-02 Datasheet Revision 4.2 45 Registers Table 18 • 4.2.1 Main Registers (continued) Address Name 27 Reserved 28 Auxiliary control and status 29 LED mode select 30 LED behavior 31 Extended register page access Mode Control The device register at memory address 0 controls several aspects of VSC8552-02 functionality. The following table shows the available bit settings in this register and what they control. Table 19 • Mode Control, Address 0 (0x00) Bit Name Access Description 15 Software reset R/W Self-clearing. Restores all serial management 0 interface (SMI) registers to default state, except for sticky and super-sticky bits. 1: Reset asserted. 0: Reset de-asserted. Wait [X] after setting this bit to initiate another SMI register access. 14 Loopback R/W 1: Loopback enabled. 0 0: Loopback disabled. When loop back is enabled, the device functions at the current speed setting and with the current duplex mode setting (bits 6, 8, and 13 of this register). 13 Forced speed selection LSB R/W Least significant bit. MSB is bit 6. 00: 10 Mbps. 01: 100 Mbps. 10: 1000 Mbps. 11: Reserved. 0 12 Autonegotiation enable R/W 1: Autonegotiation enabled. 0: Autonegotiation disabled. 1 11 Power-down R/W 1: Power-down enabled. 0 10 Isolate R/W 1: Disconnect the MAC-side interface of the device from the rest of the datapath. Traffic entering the PHY from either the MAC-side or media-side interface will terminate inside the PHY. 0 9 Restart autonegotiation R/W Self-clearing bit. 0 1: Restart autonegotiation on media interface. 8 Duplex R/W 1: Full-duplex. 0: Half-duplex. 7 Collision test enable R/W 1: Collision test enabled. 6 Forced speed selection MSB R/W Default 0 0 (1) Most significant bit. LSB is bit 13. 00: 10 Mbps. 01: 100 Mbps. 10: 1000 Mbps. 11: Reserved. VMDS-10508 VSC8552-02 Datasheet Revision 4.2 10 46 Registers Table 19 • Mode Control, Address 0 (0x00) (continued) Bit Name Access Description 5 Unidirectional enable R/W 4:0 Reserved 1. 4.2.2 Default When bit 0.12 = 1 or bit 0.8 = 0, this bit is 0 ignored. When bit 0.12 = 0 and bit 0.8 = 1, the behavior is as follows: 1: Enable transmit from media independent interface regardless of whether the PHY has determined that a valid link has been established. 0: Enable transmit from media independent interface only when the PHY has determined that a valid link has been established. Note: This bit is only applicable in 100BASE-FX and 1000BASE-X fiber media modes. Reserved. 00000 Before selecting the 1000 Mbps forced speed mode, manually configure the PHY as master or slave by setting bit 11 in register 9 (1000BASE-T Control). Each time the link drops, the PHY needs to be powered down manually to enable it to link up again using the master/slave setting specified in register 9.11. Mode Status The register at address 1 in the device main registers space allows you to read the currently enabled mode setting. The following table shows possible readouts of this register. Table 20 • Mode Status, Address 1 (0x01) Bit Name Access Description Default 15 100BASE-T4 capability RO 1: 100BASE-T4 capable. 0 14 100BASE-TX FDX capability RO 1: 100BASE-TX FDX capable. 1 13 100BASE-TX HDX capability RO 1: 100BASE-TX HDX capable. 1 12 10BASE-T FDX capability RO 1: 10BASE-T FDX capable. 1 11 10BASE-T HDX capability RO 1: 10BASE-T HDX capable. 1 10 100BASE-T2 FDX capability RO 1: 100BASE-T2 FDX capable. 0 9 100BASE-T2 HDX capability RO 1: 100BASE-T2 HDX capable. 0 8 Extended status enable RO 1: Extended status information present in register 15. 1 7 Unidirectional ability RO 1: PHY able to transmit from media independent interface regardless of whether the PHY has determined that a valid link has been established. 0: PHY able to transmit from media independent interface only when the PHY has determined that a valid link has been established. Note: This bit is only applicable to 100BASE-FX and 1000BASE-X fiber media modes. 1 6 Preamble suppression capability RO 1: MF preamble can be suppressed. 0: MF required. 1 VMDS-10508 VSC8552-02 Datasheet Revision 4.2 47 Registers Mode Status, Address 1 (0x01) (continued) Table 20 • Bit Name Access Description Default 5 Autonegotiation complete RO 1: Autonegotiation complete. 0 4 Remote fault RO Latches high. 1: Far-end fault detected. 0 3 Autonegotiation capability RO 1: Autonegotiation capable. 1 2 Link status RO Latches low. 1: Link is up. 0 1 Jabber detect RO Latches high. 1: Jabber condition detected. 0 0 Extended capability RO 1: Extended register capable. 1 4.2.3 Device Identification All 16 bits in both register 2 and register 3 in the VSC8552-02 are used to provide information associated with aspects of the device identification. The following tables list the expected readouts. Identifier 1, Address 2 (0x02) Table 21 • Bit Name Access Description Default 15:0 Organizationally unique identifier (OUI) RO 0×0007 Table 22 • OUI most significant bits (3:18) Identifier 2, Address 3 (0x03) Bit Name Access Description Default 15:10 OUI RO OUI least significant bits (19:24) 000001 9:4 Microsemi model number RO VSC8552-02 (0xE) 001110 3:0 Device revision number RO See register 30G for the extended 0010 revision identification of this device. 4.2.4 Autonegotiation Advertisement The bits in address 4 in the main registers space control the VSC8552-02 ability to notify other devices of the status of its autonegotiation feature. The following table shows the available settings and readouts. Table 23 • Device Autonegotiation Advertisement, Address 4 (0x04) Bit Name Access Description Default 15 Next page transmission request R/W 1: Request enabled 0 14 Reserved RO Reserved 0 13 Transmit remote fault R/W 1: Enabled 0 12 Reserved R/W Reserved 0 11 Advertise asymmetric pause R/W 1: Advertises asymmetric pause 0 10 Advertise symmetric pause R/W 1: Advertises symmetric pause 0 9 Advertise100BASE-T4 R/W 1: Advertises 100BASE-T4 0 8 Advertise100BASE-TX FDX R/W 1: Advertise 100BASE-TX FDX 1 VMDS-10508 VSC8552-02 Datasheet Revision 4.2 48 Registers Device Autonegotiation Advertisement, Address 4 (0x04) (continued) Table 23 • Bit Name Access Description Default 7 Advertise100BASE-TX HDX R/W 1 6 Advertise10BASE-T FDX R/W 1: Advertises 10BASE-T FDX 1 5 Advertise10BASE-T HDX R/W 1: Advertises 10BASE-T HDX 1 4:0 Advertise selector R/W 4.2.5 1: Advertises 100BASE-TX HDX 00001 Link Partner Autonegotiation Capability The bits in main register 5 can be used to determine if the Cat5 link partner (LP) used with the VSC8552-02 is compatible with the autonegotiation functionality. Table 24 • Autonegotiation Link Partner Ability, Address 5 (0x05) Bit Name 15 LP next page transmission request RO 1: Requested 0 14 LP acknowledge RO 1: Acknowledge 0 13 LP remote fault RO 1: Remote fault 0 12 Reserved RO Reserved 0 11 LP advertise asymmetric pause RO 1: Capable of asymmetric pause 0 10 LP advertise symmetric pause RO 1: Capable of symmetric pause 0 9 LP advertise 100BASE-T4 RO 1: Capable of 100BASE-T4 0 8 LP advertise 100BASE-TX FDX RO 1: Capable of 100BASE-TX FDX 0 7 LP advertise 100BASE-TX HDX RO 1: Capable of 100BASE-TX HDX 0 6 LP advertise 10BASE-T FDX RO 1: Capable of 10BASE-T FDX 0 5 LP advertise 10BASE-T HDX RO 1: Capable of 10BASE-T HDX 0 4:0 LP advertise selector RO 4.2.6 Access Description Default 00000 Autonegotiation Expansion The bits in main register 6 work together with those in register 5 to indicate the status of the LP autonegotiation functioning. The following table shows the available settings and readouts. Table 25 • Autonegotiation Expansion, Address 6 (0x06) Bit Name Access Description Default 15:5 Reserved RO Reserved. All zeros 4 Parallel detection fault RO This bit latches high. 1: Parallel detection fault. 0 3 LP next page capable RO 1: LP is next page capable. 0 2 Local PHY next page capable RO 1: Local PHY is next page capable. 1 1 Page received This bit latches low. 1: New page is received. 0 0 LP is autonegotiation capable RO 1: LP is capable of autonegotiation. 0 RO VMDS-10508 VSC8552-02 Datasheet Revision 4.2 49 Registers 4.2.7 Transmit Autonegotiation Next Page The settings in register 7 in the main registers space provide information about the number of pages in an autonegotiation sequence. The following table shows the settings available. Autonegotiation Next Page Transmit, Address 7 (0x07) Table 26 • Bit Name Access Description Default 15 Next page R/W 1: More pages follow 0 14 Reserved RO Reserved 0 13 Message page R/W 1: Message page 0: Unformatted page 1 12 Acknowledge 2 R/W 1: Complies with request 0: Cannot comply with request 0 11 Toggle RO 1: Previous transmitted LCW = 0 0: 0 Previous transmitted LCW = 1 10:0 Message/unformatted code R/W 4.2.8 00000000001 Autonegotiation Link Partner Next Page Receive The bits in register 8 of the main register space work together with register 7 to determine certain aspects of the LP autonegotiation. The following table shows the possible readouts. Autonegotiation LP Next Page Receive, Address 8 (0x08) Table 27 • Bit Name Access Description Default 15 LP next page RO 1: More pages follow 0 14 Acknowledge RO 1: LP acknowledge 0 13 LP message page RO 1: Message page 0: Unformatted page 0 12 LP acknowledge 2 RO 1: LP complies with request 0 11 LP toggle RO 1: Previous transmitted LCW = 0 0: Previous transmitted LCW = 1 0 10:0 LP message/unformatted code RO 4.2.9 All zeros 1000BASE-T Control The VSC8552-02's 1000BASE-T functionality is controlled by the bits in register 9 of the main register space. The following table shows the settings and readouts available. Table 28 • 1000BASE-T Control, Address 9 (0x09) Bit Name Access Description Default 15:13 Transmitter test mode R/W 000: Normal 001: Mode 1: Transmit waveform test 010: Mode 2: Transmit jitter test as master 011: Mode 3: Transmit jitter test as slave 100: Mode 4: Transmitter distortion test 101–111: Reserved 000 12 Master/slave manual configuration R/W 1: Master/slave manual configuration enabled 0 VMDS-10508 VSC8552-02 Datasheet Revision 4.2 50 Registers Table 28 • 1000BASE-T Control, Address 9 (0x09) (continued) Bit Name Access Description Default 11 Master/slave value R/W This register is only valid when bit 9.12 is set to 1. 1: Configure PHY as master during negotiation 0: Configure PHY as slave during negotiation 0 10 Port type R/W 1: Multi-port device 0: Single-port device 1 9 1000BASE-T FDX capability R/W 1: PHY is 1000BASE-T FDX capable 1 8 1000BASE-T HDX capability R/W 1: PHY is 1000BASE-T HDX capable 1 7:0 Reserved R/W Reserved 0x00 Note: Transmitter test mode (bits 15:13) operates in the manner described in IEEE 802.3 section 40.6.1.1.2. When using any of the transmitter test modes, the automatic media sense feature must be disabled. For more information, see Extended PHY Control Set 1, page 56. 4.2.10 1000BASE-T Status The bits in register 10 of the main register space can be read to obtain the status of the 1000BASE-T communications enabled in the device. The following table shows the readouts. Table 29 • 1000BASE-T Status, Address 10 (0x0A) Bit Name Access Description 15 Master/slave configuration fault RO This bit latches high. 0 1: Master/slave configuration fault detected 0: No master/slave configuration fault detected 14 Master/slave configuration resolution RO 1: Local PHY configuration resolved to master 1 0: Local PHY configuration resolved to slave 13 Local receiver status RO 1: Local receiver is operating normally 0 12 Remote receiver status RO 1: Remote receiver OK 0 11 LP 1000BASE-T FDX capability RO 1: LP 1000BASE-T FDX capable 0 10 LP 1000BASE-T HDX capability RO 1: LP 1000BASE-T HDX capable 0 9:8 Reserved RO Reserved 00 7:0 Idle error count RO Self-clearing register 0x00 VMDS-10508 VSC8552-02 Datasheet Revision 4.2 Default 51 Registers 4.2.11 MMD Access Control Register The bits in register 13 of the main register space are a window to the EEE registers as defined in IEEE 802.3az-2010 Clause 45. Table 30 • 4.2.12 MMD EEE Access, Address 13 (0x0D) Bit Name Access Description 15:14 Function R/W 13:5 Reserved R/W Reserved 4:0 DVAD Device address as defined in IEEE 802.3az-2010 table 45–1 R/W 00: Address 01: Data, no post increment 10: Data, post increment for read and write 11: Data, post increment for write only MMD Address or Data Register The bits in register 14 of the main register space are a window to the EEE registers as defined in IEEE 802.3az-2010 Clause 45. MMD Address or Data Register, Address 14 (0x0E) Table 31 • Bit Name Access Description 15:0 Register Address/Data R/W 4.2.13 When register 13.15:14 = 2'b00, address of register of the device that is specified by 13.4:0. Otherwise, the data to be written to or read from the register. 1000BASE-T Status Extension 1 Register 15 provides additional information about the operation of the device 1000BASE-T communications. The following table shows the readouts available. 1000BASE-T Status Extension 1, Address 15 (0x0F) Table 32 • Bit Name 15 1000BASE-X FDX capability RO 1: PHY is 1000BASE-X FDX capable 1 14 1000BASE-X HDX capability RO 1: PHY is 1000BASE-X HDX capable 1 13 1000BASE-T FDX capability RO 1: PHY is 1000BASE-T FDX capable 1 12 1000BASE-T HDX capability RO 1: PHY is 1000BASE-T HDX capable 1 11:0 Reserved Reserved 4.2.14 Access Description RO Default 0x000 100BASE-TX/FX Status Extension Register 16 in the main registers page space of the VSC8552-02 provides additional information about the status of the device's 100BASE-TX/100BASE-FX operation. Table 33 • 100BASE-TX/FX Status Extension, Address 16 (0x10) Bit Name Access Description Default 15 100BASE-TX/FX Descrambler RO 1: Descrambler locked 0 14 100BASE-TX/FX lock error RO Self-clearing bit. 1: Lock error detected 0 VMDS-10508 VSC8552-02 Datasheet Revision 4.2 52 Registers Table 33 • 100BASE-TX/FX Status Extension, Address 16 (0x10) (continued) Bit Name Access Description Default 13 100BASE-TX/FX disconnect state RO Self-clearing bit. 1: PHY 100BASE-TX link disconnect detected 0 12 100BASE-TX/FX current link status RO 1: PHY 100BASE-TX link active 0 11 100BASE-TX/FX receive error RO Self-clearing bit. 1: Receive error detected 0 10 100BASE-TX/FX transmit error RO Self-clearing bit. 1: Transmit error detected 0 9 100BASE-TX/FX SSD error RO Self-clearing bit. 1: Start-of-stream delimiter error detected 0 8 100BASE-TX/FX ESD error RO Self-clearing bit. 1: End-of-stream delimiter error detected 0 7:0 Reserved RO Reserved 4.2.15 1000BASE-T Status Extension 2 The second status extension register is at address 17 in the device main registers space. It provides information about another set of parameters associated with 1000BASE-T communications. For information about the first status extension register, see Table 32, page 52. Table 34 • 1000BASE-T Status Extension 2, Address 17 (0x11) Bit Name Access Description Default 15 1000BASE-T descrambler RO 1: Descrambler locked. 0 14 1000BASE-T lock error RO Self-clearing bit. 1: Lock error detected 0 13 1000BASE-T disconnect state RO Self-clearing bit. 1: PHY 1000BASE-T link disconnect detected 0 12 1000BASE-T current link status RO 1: PHY 1000BASE-T link active 0 11 1000BASE-T receive error RO Self-clearing bit. 1: Receive error detected 0 10 1000BASE-T transmit error RO Self-clearing bit. 1: Transmit error detected 0 9 1000BASE-T SSD error RO Self-clearing bit. 0 1: Start-of-stream delimiter error detected 8 1000BASE-T ESD error RO Self-clearing bit. 0 1: End-of-stream delimiter error detected 7 1000BASE-T carrier extension RO error Self-clearing bit. 1: Carrier extension error detected 0 6 Non-compliant BCM5400 detected RO 1: Non-compliant BCM5400 link partner detected 0 5 MDI crossover error RO 1: MDI crossover error was detected 0 VMDS-10508 VSC8552-02 Datasheet Revision 4.2 53 Registers Table 34 • 1000BASE-T Status Extension 2, Address 17 (0x11) (continued) Bit Name Access Description 4:0 Reserved RO 4.2.16 Default Reserved Bypass Control The bits in this register control aspects of functionality in effect when the device is disabled for the purpose of traffic bypass. The following table shows the settings available. Table 35 • Bypass Control, Address 18 (0x12) Bit Name Access Description Default 15 Transmit disable R/W 1: PHY transmitter disabled 0 14 4B5B encoder/decoder R/W 1: Bypass 4B/5B encoder/decoder 0 13 Scrambler R/W 1: Bypass scrambler 0 12 Descrambler R/W 1: Bypass descrambler 0 11 PCS receive R/W 1: Bypass PCS receiver 0 10 PCS transmit R/W 1: Bypass PCS transmit 0 9 LFI timer R/W 1: Bypass Link Fail Inhibit (LFI) timer 0 8 Reserved RO Reserved 7 HP Auto-MDIX at forced 10/100 R/W 1 Sticky bit. 1: Disable HP Auto-MDIX at forced 10/100 speeds 6 Non-compliant BCM5400 detect disable R/W Sticky bit. 1: Disable non-compliant BCM5400 detection 0 5 Disable pair swap correction (HP Auto-MDIX when autonegotiation enabled) R/W Sticky bit. 1: Disable the automatic pair swap correction 0 4 Disable polarity correction R/W Sticky bit. 1: Disable polarity inversion correction on each subchannel 0 3 Parallel detect control R/W Sticky bit. 1: Do not ignore advertised ability 0: Ignore advertised ability 1 2 Pulse shaping filter R/W 1: Disable pulse shaping filter 0 1 Disable automatic 1000BASE-T next page exchange R/W Sticky bit. 1: Disable automatic 1000BASE T next page exchanges 0 0 Reserved RO Reserved Note: If bit 18.1 is set to 1 in this register, automatic exchange of next pages is disabled, and control is returned to the user through the SMI after the base page is exchanged. The user then must send the correct sequence of next pages to the link partner, determine the common capabilities, and force the device into the correct configuration following the successful exchange of pages. VMDS-10508 VSC8552-02 Datasheet Revision 4.2 54 Registers 4.2.17 Error Counter 1 The bits in register 19 provide an error counter. The following table shows the settings available. Error Counter 1, Address 19 (0x13) Table 36 • Bit Name Access Description 15:8 Reserved RO Reserved. 7:0 100/1000 receive error counter RO 8-bit counter that saturates when it reaches 255. These bits are self-clearing when read. 4.2.18 Default 0x00 Error Counter 2 The bits in register 20 provide an error counter. The following table shows the settings available. Error Counter 2, Address 20 (0x14) Table 37 • Bit Name Access Description 15:8 Reserved RO Reserved. 7:0 100/1000 false carrier counter RO 8-bit counter that saturates when it reaches 255. These bits are self-clearing when read. 4.2.19 Default 0x00 Error Counter 3 The bits in register 21 provide an error counter. The following table shows the settings available. Table 38 • Error Counter 3, Address 21 (0x15) Bit Name Access Description 15:8 Reserved RO Reserved. 7:0 Copper media link disconnect counter RO 8-bit counter that saturates when it reaches 255. These bits are self-clearing when read. 4.2.20 Default 0x00 Extended Control and Status The bits in register 22 provide additional device control and readouts. The following table shows the settings available. Table 39 • Extended Control and Status, Address 22 (0x16) Bit Name Access Description Default 15 Force 10BASE-T link high R/W Sticky bit. 1: Bypass link integrity test 0: Enable link integrity test 0 14 Jabber detect disable R/W Sticky bit. 1: Disable jabber detect 0 13 Disable 10BASE-T echo R/W Sticky bit. 1: Disable 10BASE-T echo 1 12 Disable SQE mode R/W Sticky bit. 1: Disable SQE mode 1 VMDS-10508 VSC8552-02 Datasheet Revision 4.2 55 Registers Table 39 • Extended Control and Status, Address 22 (0x16) (continued) Bit Name Access Description Default 11:10 10BASE-T squelch control R/W Sticky bit. 00: Normal squelch 01: Low squelch 10: High squelch 11: Reserved 00 9 Sticky reset enable R/W Super-sticky bit. 1: Enabled 1 8 EOF Error RO This bit is self-clearing. 1: EOF error detected 0 7 10BASE-T disconnect state RO This bit is self-clearing. 1: 10BASE-T link disconnect detected 0 6 10BASE-T link status RO 1: 10BASE-T link active 0 5:1 Reserved RO Reserved 0 SMI broadcast write R/W Sticky bit. 1: Enabled 0 The following information applies to the extended control and status bits: • • • • 4.2.21 When bit 22.15 is set, the link integrity state machine is bypassed and the PHY is forced into a link pass status. When bits 22.11:10 are set to 00, the squelch threshold levels are based on the IEEE standard for 10BASE-T. When set to 01, the squelch level is decreased, which can improve the bit error rate performance on long loops. When set to 10, the squelch level is increased and can improve the bit error rate in high-noise environments. When bit 22.9 is set, all sticky register bits retain their values during a software reset. Clearing this bit causes all sticky register bits to change to their default values upon software reset. Super-sticky bits retain their values upon software reset regardless of the setting of bit 22.9. When bit 22.0 is set, if a write to any PHY register (registers 0–31, including extended registers), the same write is broadcast to all PHYs. For example, if bit 22.0 is set to 1 and a write to PHY0 is executed (register 0 is set to 0x1040), all PHYs' register 0s are set to 0x1040. This bit must be disabled before performing a software reset of any PHY port (see register 0 bit 15, Table 19, page 46). Disabling this bit restores normal PHY write operation. Reads are still possible when this bit is set, but the value that is read corresponds only to the particular PHY being addressed. Extended PHY Control Set 1 The following table shows the settings available. Table 40 • Extended PHY Control 1, Address 23 (0x17) Bit Name Access Description Default 15:13 Reserved R/W 0 12 MAC interface mode R/W Super-sticky bit. 0 0: RGMII/SGMII 1: 1000BASE-X. Note: Register 19G.15:14 must be = 00 for this selection to be valid. 11 AMS preference Super-sticky bit. 1: Cat5 copper preferred. 0: SerDes fiber/SFP preferred. R/W Reserved VMDS-10508 VSC8552-02 Datasheet Revision 4.2 0 56 Registers Table 40 • Extended PHY Control 1, Address 23 (0x17) (continued) Bit Name Access Description 10:8 Media operating mode R/W Super-sticky bits. 000 000: Cat5 copper only. 001: SerDes fiber/SFP protocol transfer mode only. 010: 1000BASE-X fiber/SFP media only with autonegotiation performed by the PHY. 011: 100BASE-FX fiber/SFP on the fiber media pins only. 101: Automatic media sense (AMS) with Cat5 media or SerDes fiber/SFP protocol transfer mode. 110: AMS with Cat5 media or 1000BASE-X fiber/SFP media with autonegotiation performed by PHY. 111: AMS with Cat5 media or 100BASE-FX fiber/SFP media. 100: AMS. Default 7:6 Force AMS override R/W Sticky bits. 00: Normal AMS selection 01: Force AMS to select SerDes media only 10: Force AMS to select copper media only 11: Reserved 5:4 Reserved RO Reserved. 3 Far-end loopback mode R/W 1: Enabled. 2:0 Reserved RO Reserved. 00 0 Note: After configuring bits 13:8 of the extended PHY control register set 1, a software reset (register 0, bit 15) must be written to change the device operating mode. On read, these bits only indicate the actual operating mode and not the pending operating mode setting before a software reset has taken place. 4.2.22 Extended PHY Control Set 2 The second set of extended controls is located in register 24 in the main register space for the device. The following table shows the settings and readouts available. Table 41 • Extended PHY Control 2, Address 24 (0x18) Bit Name Access Description Default 15:13 100BASE-TX edge rate control R/W Sticky bit. 011: +5 edge rate (slowest) 010: +4 edge rate 001: +3 edge rate 000: +2 edge rate 111: +1 edge rate 110: Default edge rate 101: –1 edge rate 100: –2 edge rate (fastest) 001 12 PICMG 2.16 reduced R/W power mode Sticky bit. 1: Enabled 0 11:6 Reserved Reserved RO VMDS-10508 VSC8552-02 Datasheet Revision 4.2 57 Registers Table 41 • Extended PHY Control 2, Address 24 (0x18) (continued) Bit Name Access Description Default 5:4 Jumbo packet mode R/W Sticky bit. 00: Normal IEEE 1.5 kB packet length 01: 9 kB jumbo packet length (12 kB with 60 ppm or better reference clock) 10: 12 kB jumbo packet length (16 kB with 70 ppm or better reference clock) 11: Reserved 00 3:1 Reserved RO Reserved 0 1000BASE-T connector loopback R/W 1: Enabled 0 Note: When bits 5:4 are set to jumbo packet mode, the default maximum packet values are based on 100 ppm driven reference clock to the device. Controlling the ppm offset between the MAC and the PHY as specified in the bit description results in a higher jumbo packet length. 4.2.23 Interrupt Mask These bits control the device interrupt mask. The following table shows the settings available. Table 42 • Interrupt Mask, Address 25 (0x19) Bit Name Access Description Default 15 MDINT interrupt status enable R/W Sticky bit. 1: Enabled. 0 14 Speed state change mask R/W Sticky bit. 1: Enabled. 0 13 Link state change mask R/W Sticky bit. 1: Enabled. 0 12 FDX state change mask R/W Sticky bit. 1: Enabled. 0 11 Autonegotiation error mask R/W Sticky bit. 1: Enabled. 0 10 Autonegotiation complete mask R/W Sticky bit. 1: Enabled. 0 9 Inline powered device (PoE) detect mask R/W Sticky bit. 1: Enabled. 0 8 Symbol error interrupt mask R/W Sticky bit. 1: Enabled. 0 7 Fast link failure interrupt mask(1) R/W Sticky bit. 1: Enabled. 0 6:5 Reserved R/W 4 AMS media changed mask(2) R/W Sticky bit. 1: Enabled. 0 3 False carrier interrupt mask R/W Sticky bit. 1: Enabled. 0 2 Link speed downshift detect mask R/W Sticky bit. 1: Enabled. 0 1 Master/Slave resolution error mask R/W Sticky bit. 1: Enabled. 0 0 RX_ER interrupt mask R/W Sticky bit. 1: Enabled. 0 1. 2. 0 The interrupt is only valid for 100 Mbps and 1000 Mbps speeds. Notification at 10 Mbps speed requires use of the FASTLINK-FAIL pin. If hardware interrupts are not used, the mask can still be set and the status polled for changes. Note: When bit 25.15 is set, the MDINT pin is enabled. When enabled, the state of this pin reflects the state of bit 26.15. Clearing this bit only inhibits the MDINT pin from being asserted. Also, before enabling this bit, read register 26 to clear any previously inactive interrupts pending that will cause bit 25.15 to be set. VMDS-10508 VSC8552-02 Datasheet Revision 4.2 58 Registers 4.2.24 Interrupt Status The status of interrupts already written to the device is available for reading from register 26 in the main registers space. The following table shows the expected readouts. Table 43 • Interrupt Status, Address 26 (0x1A) Bit Name Access Description Default 15 Interrupt status RO Self-clearing bit. 1: Interrupt pending. 0 14 Speed state change status RO Self-clearing bit. 1: Interrupt pending. 0 13 Link state change status RO Self-clearing bit. 1: Interrupt pending. 0 12 FDX state change status RO Self-clearing bit. 1: Interrupt pending. 0 11 Autonegotiation error status RO Self-clearing bit. 1: Interrupt pending. 0 10 Autonegotiation complete status RO Self-clearing bit. 1: Interrupt pending. 0 9 Inline powered device detect status RO Self-clearing bit. 1: Interrupt pending. 0 8 Symbol error status RO Self-clearing bit. 1: Interrupt pending. 0 7 Fast link failure detect status RO Self-clearing bit. 1: Interrupt pending. 0 6:5 Reserved RO 4 AMS media changed 3 mask(1) 0 RO Self-clearing bit. 1: Interrupt pending. 0 False carrier interrupt status RO Self-clearing bit. 1: Interrupt pending. 0 2 Link speed downshift detect status RO Self-clearing bit. 1: Interrupt pending. 0 1 Master/Slave resolution error status RO Self-clearing bit. 1: Interrupt pending. 0 0 RX_ER interrupt status RO Self-clearing bit. 1: Interrupt pending. 0 1. If hardware interrupts are not used, the mask can still be set and the status polled for changes. The following information applies to the interrupt status bits: • • • • 4.2.25 All set bits in this register are cleared after being read (self-clearing). If bit 26.15 is set, the cause of the interrupt can be read by reading bits 26.14:0. For bits 26.14 and 26.12, bit 0.12 must be set for this interrupt to assert. For bit 26.2, bits 4.8:5 must be set for this interrupt to assert. For bit 26.0, this interrupt will not occur when RX_ER is used for carrier-extension decoding of a link partner's data transmission. Device Auxiliary Control and Status Register 28 provides control and status information for several device functions not controlled or monitored by other device registers. The following table shows the settings available and the expected readouts. Table 44 • Auxiliary Control and Status, Address 28 (0x1C) Bit Name Access Description Default 15 Autonegotiation complete RO Duplicate of bit 1.5 0 14 Autonegotiation disabled RO Inverted duplicate of bit 0.12 0 131 HP Auto-MDIX crossover indication RO 1: HP Auto-MDIX crossover performed internally 0 VMDS-10508 VSC8552-02 Datasheet Revision 4.2 59 Registers Table 44 • Bit Name Access Description Default 12 CD pair swap RO 1: CD pairs are swapped 0 11 A polarity inversion RO 1: Polarity swap on pair A 0 10 B polarity inversion RO 1: Polarity swap on pair B 0 9 C polarity inversion RO 1: Polarity swap on pair C 0 8 D polarity inversion RO 1: Polarity swap on pair D 0 7 ActiPHY link status time-out R/W control [1] Sticky bit. Bits 7 and 2 are part of the 0 ActiPHY Link Status time-out control. Bit 7 is the MSB. 00: 2.3 seconds 01: 3.3 seconds 10: 4.3 seconds 11: 5.3 seconds 6 ActiPHY mode enable R/W Sticky bit. 1: Enabled 0 5 FDX status RO 1: Full-duplex 0: Half-duplex 00 4:3 Speed status RO 0 00: Speed is 10BASE-T 01: Speed is 100BASE-TX or 100BASE-FX 10: Speed is 1000BASE-T or 1000BASE-X 11: Reserved 2 ActiPHY link status time-out R/W control [0] Sticky bit. Bits 7 and 2 are part of the 1 ActiPHY Link Status time-out control. Bit 7 is the MSB. 00: 2.3 seconds 01: 3.3 seconds 10: 4.3 seconds 11: 5.3 seconds 1:0 Media mode status 00: No media selected 01: Copper media selected 10: SerDes (Fiber) media selected 11: Reserved 1. 4.2.26 Auxiliary Control and Status, Address 28 (0x1C) (continued) RO 00 In 1000BT mode, if Force MDI crossover is performed while link is up, the 1000BT link must be re-negotiated in order for this bit to reflect the actual Auto-MDIX setting. LED Mode Select The device LED outputs are controlled using the bits in register 29 of the main register space. The following table shows the information needed to access the functionality of each of the outputs. For more information about LED modes, see Table 7, page 27. For information about enabling the extended LED mode bits in Register 19E1 bits 13 to 12, see Table 8, page 28. Table 45 • LED Mode Select, Address 29 (0x1D) Bit Name Access Description 15:12 LED3 mode select R/W Sticky bit. Select from LED modes 0–15. 1000 11:8 LED2 mode select R/W Sticky bit. Select from LED modes 0–15. 0000 7:4 LED1 mode select R/W Sticky bit. Select from LED modes 0–15. 0010 3:0 LED0 mode select R/W Sticky bit. Select from LED modes 0–15. 0001 VMDS-10508 VSC8552-02 Datasheet Revision 4.2 Default 60 Registers 4.2.27 LED Behavior The bits in register 30 control and enable you to read the status of the pulse or blink rate of the device LEDs. The following table shows the settings you can write to the register or read from the register. Table 46 • LED Behavior, Address 30 (0x1E) Bit Name Access Description 15 Copper and fiber R/W LED combine disable Sticky bit 0: Combine enabled (Copper/Fiber on link/linkXXXX/activity LED) 1: Disable combination (link/linkXXXX/activity LED; indicates copper only) 14 Activity output select R/W Sticky bit 0 1: Activity LED becomes TX_Activity and fiber activity LED becomes RX_Activity 0: TX and RX activity both displayed on activity LEDs 13 Reserved RO Reserved 12 LED pulsing enable R/W 0 Sticky bit 0: Normal operation 1: LEDs pulse with a 5 kHz, programmable duty cycle when active 11:10 LED blink/pulsestretch rate R/W Sticky bit 00: 2.5 Hz blink rate/400 ms pulse-stretch 01: 5 Hz blink rate/200 ms pulse-stretch 10: 10 Hz blink rate/100 ms pulse-stretch 11: 20 Hz blink rate/50 ms pulse-stretch The blink rate selection for PHY0 globally sets the rate used for all LED pins on all PHY ports 9 Reserved RO Reserved 8 LED3 pulsestretch/blink select R/W Sticky bit 1: Pulse-stretch 0: Blink 0 7 LED2 pulsestretch/blink select R/W Sticky bit 1: Pulse-stretch 0: Blink 0 6 LED1 pulsestretch/blink select R/W Sticky bit 1: Pulse-stretch 0: Blink 0 5 LED0 pulsestretch/blink select R/W Sticky bit 1: Pulse-stretch 0: Blink 0 4:2 Reserved RO Reserved 3 LED3 combine feature disable R/W Sticky bit 0: Combine enabled (link/activity, duplex/collision) 1: Disable combination (link only, duplex only) 0 2 LED2 combine feature disable R/W Sticky bit 0: Combine enabled (link/activity, duplex/collision) 1: Disable combination (link only, duplex only) 0 VMDS-10508 VSC8552-02 Datasheet Revision 4.2 Default 0 01 61 Registers Table 46 • LED Behavior, Address 30 (0x1E) (continued) Bit Name Access Description Default 1 LED1 combine feature disable R/W Sticky bit 0: Combine enabled (link/activity, duplex/collision) 1: Disable combination (link only, duplex only) 0 0 LED0 combine feature disable R/W Sticky bit 0: Combine enabled (link/activity, duplex/collision) 1: Disable combination (link only, duplex only) 0 Note: Bits 30.11:10 are active only in port 0 and affect the behavior of LEDs for all the ports. 4.2.28 Extended Page Access To provide functionality beyond the IEEE 802.3-specified registers and main device registers, the VSC8552-02 includes an extended set of registers that provide an additional 15 register spaces. The register at address 31 controls the access to the extended registers for the VSC8552-02. Accessing the GPIO page register space is similar to accessing the extended page registers. The following table shows the settings available. Table 47 • 4.3 Extended/GPIO Register Page Access, Address 31 (0x1F) Bit Name Access Description 15:0 Extended/GPIO page R/W register access Default 0x0000: Register 16–30 accesses main register 0x0000 space. Writing 0x0000 to register 31 restores the main register access. 0x0001: Registers 16–30 access extended register space 1 0x0002: Registers 16–30 access extended register space 2 0x0003: Registers 16–30 access extended register space 3 0x0010: Registers 0–30 access GPIO register space Extended Page 1 Registers To access the extended page 1 registers (16E1–30E1), enable extended register access by writing 0x0001 to register 31. Writing 0x0000 to register 31 restores the main register access. When extended page 1 register access is enabled, reads and writes to registers 16–30 affect the extended registers 16E1–30E1 instead of those same registers in the IEEE-specified register space. Registers 0–15 are not affected by the state of the extended page register access. Table 48 • Extended Registers Page 1 Space Address Name 16E1 SerDes Media Control 17E1 Reserved 18E1 Cu Media CRC good counter 19E1 Extended mode and SIGDET control 20E1 Extended PHY control 3 (ActiPHY) 21E1–22E1 Reserved VMDS-10508 VSC8552-02 Datasheet Revision 4.2 62 Registers Table 48 • Extended Registers Page 1 Space (continued) Address Name 23E1 Extended PHY control 4 (PoE and CRC error counter) 27E1–28E1 Reserved 4.3.1 29E1 Ethernet packet generator (EPG) 1 30E1 EPG 2 SerDes Media Control Register 16E1 controls some functions of the SerDes media interface on ports 0–3. These settings are only valid for those ports. The following table shows the setting available in this register. Table 49 • SerDes Media Control, Address 16E1 (0x10) Bit Name Access Description Default 15:14 Transmit remote fault R/W Remote fault indication sent to link partner (LP) 00 13:12 Link partner (LP) remote fault RO Remote fault bits sent by LP during autonegotiation 00 11:10 Reserved RO Reserved 9 Allow 1000BASE-X link-up R/W Sticky bit. 1 1: Allow 1000BASE-X fiber media link-up capability 0: Suppress 1000BASE-X fiber media link-up capability 8 Allow 100BASE-FX link-up R/W Sticky bit. 1 1: Allow 100BASE-FX fiber media link-up capability 0: Suppress 100BASE-FX fiber media link-up capability 7 Reserved RO Reserved 6 Far end fault detected in 100BASE-FX RO Self-clearing bit. 0 1: Far end fault in 100BASE-FX detected 5:0 Reserved RO Reserved 4.3.2 Cu Media CRC Good Counter Register 18E1 makes it possible to read the contents of the CRC good counter for packets that are received on the Cu media interface; the number of CRC routines that have executed successfully. The following table shows the expected readouts. Table 50 • Cu Media CRC Good Counter, Address 18E1 (0x12) Bit Name Access Description Default 15 Packet since last read RO Self-clearing bit. 1: Packet received since last read. 0 14 Reserved RO Reserved. VMDS-10508 VSC8552-02 Datasheet Revision 4.2 63 Registers Cu Media CRC Good Counter, Address 18E1 (0x12) (continued) Table 50 • Bit Name Access Description Default 13:0 Cu Media CRC good counter contents RO 0x000 4.3.3 Self-clearing bit. Counter containing the number of packets with valid CRCs modulo 10,000; this counter does not saturate and will roll over to zero on the next good packet received after 9,999. Extended Mode Control Register 19E1 controls the extended LED and other chip modes. The following table shows the settings available. Table 51 • Extended Mode Control, Address 19E1 (0x13) Bit Name Access Description Default 15 LED3 Extended Mode R/W Sticky bit. 1: See Extended LED Modes, page 28 0 14 LED2 Extended Mode R/W Sticky bit. 1: See Extended LED Modes, page 28 0 13 LED1 Extended Mode R/W Sticky bit. 1: See Extended LED Modes, page 28 0 12 LED0 Extended Mode R/W Sticky bit. 1: See Extended LED Modes, page 28 0 11 LED Reset Blink Suppress R/W Sticky bit. 0 1: Blink LEDs after COMA_MODE is de-asserted 0: Suppress LED blink after COMA_MODE is de-asserted 10:5 Reserved RO Reserved 0 4 Fast link failure R/W Sticky bit. Enable fast link failure pin. This must be done from PHY0 only. 1: Enabled 0: Disabled (GPIO9 pin becomes general purpose I/O) 0 3:2 Force MDI crossover R/W Sticky bits. 00: Normal HP Auto-MDIX operation 01: Reserved 10: Copper media forced to MDI 11: Copper media forced MDI-X 00 1 Reserved RO Reserved 0 GPIO[1:0]/SIGDET[1:0] pin R/W polarity Sticky bit. 1: Active low 0: Active high VMDS-10508 VSC8552-02 Datasheet Revision 4.2 0 64 Registers 4.3.4 ActiPHY Control Register 20E1 controls the device ActiPHY sleep timer, its wake-up timer, and its link speed downshifting feature. The following table shows the settings available. Table 52 • Extended PHY Control 3, Address 20E1 (0x14) Bit Name Access Description 15 Disable carrier extension R/W 1: Disable carrier extension in 1000BASE-T 1 copper links 14:13 ActiPHY sleep timer R/W Sticky bit. 00: 1 second 01: 2 seconds 10: 3 seconds 11: 4 seconds 01 12:11 ActiPHY wake-up timer R/W Sticky bit. 00: 160 ms 01: 400 ms 10: 800 ms 11: 2 seconds 00 10 Reserved RO Reserved 9 PHY address reversal R/W Sticky bit. Reverse PHY address Enabling causes physical PHY 0 to have address of 3, PHY 1 address of 2, PHY 2 address of 1, and PHY 3 address of 0. Changing this bit to 1 should initially be done from PHY 0 and changing to 0 from PHY3 1: Enabled 0: Disabled 8 Reserved RO Valid only on PHY0 7:6 Media mode status RO 00: No media selected 01: Copper media selected 10: SerDes media selected 11: Reserved 5 Enable 10BASE-T no preamble mode R/W 0 Sticky bit. 1: 10BASE-T will assert RX_DV indication when data is presented to the receiver even without a preamble preceding it 4 Enable link speed autodownshift feature R/W Sticky bit. 1: Enable auto link speed downshift from 1000BASE-T 0 3:2 Link speed auto downshift R/W control Sticky bits. 00: Downshift after 2 failed 1000BASE-T autonegotiation attempts 01: Downshift after 3 failed 1000BASE-T autonegotiation attempts 10: Downshift after 4 failed 1000BASE-T autonegotiation attempts 11: Downshift after 5 failed 1000BASE-T autonegotiation attempts 01 1 Link speed auto downshift RO status 0: No downshift 1: Downshift is required or has occurred 0 VMDS-10508 VSC8552-02 Datasheet Revision 4.2 Default 0 00 65 Registers Table 52 • Extended PHY Control 3, Address 20E1 (0x14) (continued) Bit Name Access Description 0 Reserved RO 4.3.5 Default Reserved PoE and Miscellaneous Functionality The register at address 23E1 controls various aspects of inline powering and the CRC error counter in the VSC8552-02. Table 53 • Extended PHY Control 4, Address 23E1 (0x17) Bit Name Access Description Default 15:11 PHY address RO PHY address; latched on reset 10 Inline powered device detection R/W Sticky bit. 1: Enabled 0 9:8 Inline powered device detection status RO Only valid when bit 10 is set. 00: Searching for devices 01: Device found; requires inline power 10: Device found; does not require inline power 11: Reserved 00 7:0 Cu Media CRC error counter RO Self-clearing bit RC error counter for packets received on the Cu media interface. The value saturates at 0xFF and subsequently clears when read and restarts count.0x00 4.3.6 Ethernet Packet Generator Control 1 The EPG control register provides access to and control of various aspects of the EPG testing feature. There are two separate EPG control registers. The following table shows the settings available in the first register. Table 54 • EPG Control Register 1, Address 29E1 (0x1D) Bit Name Access Description Default 15 EPG enable R/W 1: Enable EPG 0 14 EPG run or stop R/W 1: Run EPG 0 13 Transmission duration R/W 1: Continuous (sends in 10,000-packet increments) 0: Send 30,000,000 packets and stop 0 12:11 Packet length R/W 00: 125 bytes 01: 64 bytes 10: 1518 bytes 11: 10,000 bytes (jumbo packet) 0 10 Interpacket gap R/W 1: 8,192 ns 0: 96 ns 0 9:6 Destination address R/W Lowest nibble of the 6-byte destination address 0001 5:2 Source address R/W Lowest nibble of the 6-byte destination address 0000 VMDS-10508 VSC8552-02 Datasheet Revision 4.2 66 Registers Table 54 • EPG Control Register 1, Address 29E1 (0x1D) (continued) Bit Name Access Description Default 1 Payload type R/W 1: Randomly generated payload pattern 0: Fixed based on payload pattern 0 0 Bad frame check sequence (FCS) generation R/W 1: Generate packets with bad FCS 0: Generate packets with good FCS 0 The following information applies to the EPG control number 1: • • Do not run the EPG when the VSC8552-02 is connected to a live network. bit 29E1.13 (continuous EPG mode control): When enabled, this mode causes the device to send continuous packets. When disabled, the device continues to send packets only until it reaches the next 10,000-packet increment mark. It then ceases to send packets. The 6-byte destination address in bits 9:6 is assigned one of 16 addresses in the range of 0xFF FF FF FF FF F0 through 0xFF FF FF FF FF FF. The 6-byte source address in bits 5:2 is assigned one of 16 addresses in the range of 0xFF FF FF FF FF F0 through 0xFF FF FF FF FF FF. If any of bits 13:0 are changed while the EPG is running (bit 14 is set to 1), bit 14 must be cleared and then set back to 1 for the change to take effect and to restart the EPG. • • • 4.3.7 Ethernet Packet Generator Control 2 Register 30E1 consists of the second set of bits that provide access to and control over the various aspects of the EPG testing feature. The following table shows the settings available. Table 55 • EPG Control Register 2, Address 30E1 (0x1E) Bit Name Access Description 15:0 EPG packet payload R/W Default Data pattern repeated in the payload of 0x00 packets generated by the EPG Note: If any of bits 15:0 in this register are changed while the EPG is running (bit 14 of register 29E1 is set to 1), that bit (29E1.14) must first be cleared and then set back to 1 for the change to take effect and to restart the EPG. 4.4 Extended Page 2 Registers To access the extended page 2 registers (16E2–30E2), enable extended register access by writing 0x0002 to register 31. For more information, see Table 47, page 62. When extended page 2 register access is enabled, reads and writes to registers 16–30 affect the extended registers 16E2–30E2 instead of those same registers in the IEEE-specified register space. Registers 0–15 are not affected by the state of the extended page register access. Writing 0x0000 to register 31 restores the main register access. The following table lists the addresses and register names in the extended register page 2 space. These registers are accessible only when the device register 31 is set to 0x0002. Table 56 • Extended Registers Page 2 Space Address Name 16E2 Cu PMD Transmit Control 17E2 EEE Control 18E2 RGMII Settings 19E2-29E2 Reserved VMDS-10508 VSC8552-02 Datasheet Revision 4.2 67 Registers Table 56 • 4.4.1 Extended Registers Page 2 Space (continued) Address Name 30E2 Ring Resiliency Control Cu PMD Transmit Control The register at address 16E2 consists of the bits that provide control over the amplitude settings for the transmit side Cu PMD interface. These bits provide the ability to make small adjustments in the signal amplitude to compensate for minor variations in the magnetics from different vendors. Extreme caution must be exercised when changing these settings from the default values as they have a direct impact on the signal quality. Changing these settings also affects the linearity and harmonic distortion of the transmitted signals. For help with changing these values, contact your Microsemi representative. Table 57 • Cu PMD Transmit Control, Address 16E2 (0x10) Bit Name Access Description 15:12 1000BASE-T signal R/W amplitude trim(1) Sticky bits. 1000BASE-T signal amplitude 1111: -1.7% 1110: -2.6% 1101: -3.5% 1100: -4.4% 1011: -5.3% 1010: -7% 1001: -8.8% 1000: -10.6% 0111: 5.5% 0110: 4.6% 0101: 3.7% 0100: 2.8% 0011: 1.9% 0010: 1% 0001: 0.1% 0000: -0.8% 0000 11:8 100BASE-TX signal R/W amplitude trim(2) Sticky bits. 100BASE-TX signal amplitude 1111: -1.7% 1110: -2.6% 1101: -3.5% 1100: -4.4% 1011: -5.3% 1010: -7% 1001: -8.8% 1000: -10.6% 0111 5.5% 0110: 4.6% 0101: 3.7% 0100: 2.8% 0011: 1.9% 0010: 1% 0001: 0.1% 0000: -0.8% 0010 VMDS-10508 VSC8552-02 Datasheet Revision 4.2 Default 68 Registers Table 57 • Bit Name Access Description Default 7:4 10BASE-T signal amplitude trim(3) R/W Sticky bits. 10BASE-T signal amplitude 1111: -7% 1110: -7.9% 1101: -8.8% 1100: -9.7% 1011: -10.6% 1010: -11.5% 1001: -12.4% 1000: -13.3% 0111: 0% 0110: -0.7% 0101: -1.6% 0100: -2.5% 0011: -3.4% 0010: -4.3% 0001: -5.2% 0000: -6.1% 1011 3:0 10BASE-Te signal amplitude trim R/W Sticky bits. 10BASE-Te signal amplitude 1111: -30.45% 1110: -31.1% 1101: -31.75% 1100: -32.4% 1011: -33.05% 1010: -33.7% 1001: -34.35% 1000: -35% 0111: -25.25% 0110: -25.9% 0101: -26.55% 0100: -27.2% 0011: -27.85% 0010: -28.5% 0001: -29.15% 0000: -29.8% 1110 1. 2. 3. 4.4.2 Cu PMD Transmit Control, Address 16E2 (0x10) (continued) Changes to 1000BASE-T amplitude may result in unpredictable side effects. Adjust 100BASE-TX to specific magnetics. Amplitude is limited by VCC (2.5 V). EEE Control The register at address 17E2 consists of the bits that provide additional control over the chip behavior in energy efficient Ethernet (IEEE 802.3az-2010) mode. Table 58 • EEE Control, Address 17E2 (0x11) Bit Name Access Description Default 15 Enable 10BASE-Te R/W 0 Sticky bit. Enable energy efficient (IEEE 802.3az-2010) 10BASE-Te operating mode. VMDS-10508 VSC8552-02 Datasheet Revision 4.2 69 Registers Table 58 • EEE Control, Address 17E2 (0x11) (continued) Bit Name Access Description Default 14 Enable LED in fiber unidirectional mode R/W Sticky bit. 1: Enable LED functions in fiber unidirectional mode. 0 13:10 Invert LED polarity R/W Sticky bits. 0000 Invert polarity of LED[3:0]_[1:0] signals. Default is to drive an active low signal on the LED pins. This also applies to enhanced serial LED mode. For more information, see Enhanced Serial LED Mode, page 30. 9:6 Reserved RO Reserved. 5 Enable 1000BASE-T R/W force mode Sticky bit. 0 1: Enable 1000BASE-T force mode to allow PHY to link-up in 1000BASE-T mode without forcing master/slave when register 0, bits 6 and 13 are set to 2’b10. 41 Force transmit LPI Sticky bit. 1: Enable the EPG to transmit LPI on the MDI, ignore data from the MAC interface. 0: Transmit idles being received from the MAC. 3 Inhibit 100BASE-TX R/W transmit EEE LPI Sticky bit. 0 1: Disable transmission of EEE LPI on transmit path MDI in 100BASE-TX mode when receiving LPI from MAC. 2 Inhibit 100BASE-TX R/W receive EEE LPI Sticky bit. 0 1: Disable transmission of EEE LPI on receive path MAC interface in 100BASE-TX mode when receiving LPI from the MDI. 1 Inhibit 1000BASE-T R/W transmit EEE LPI Sticky bit. 1: Disable transmission of EEE LPI on transmit path MDI in 1000BASE-T mode when receiving LPI from MAC. 0 Inhibit 1000BASE-T R/W receive EEE LPI 0 Sticky bit. 1: Disable transmission of EEE LPI on receive path MAC interface in 1000BASE-T mode when receiving LPI from the MDI. 1. R/W 0 0 17E2 bits 4:0 are for debugging purposes only, not for operational use. VMDS-10508 VSC8552-02 Datasheet Revision 4.2 70 Registers 4.4.3 RGMII Settings The following table shows the register settings for the RGMII setting controls at address 18E2. Table 59 • RGMII Settings, Address 18E2 Bit Name Access Description Default 6:4 rgmii_skew_tx R/W 000: 0.2 ns delay 001: 0.8 ns delay 010: 1.1 ns delay 011: 1.7 ns delay 100: 2.0 ns delay 101: 2.3 ns delay 110: 2.6 ns delay 111: 3.4 ns delay 000 3:1 rgmii_skew_rx R/W 000: 0.2 ns delay 001: 0.8 ns delay 010: 1.1 ns delay 011: 1.7 ns delay 100: 2.0 ns delay 101: 2.3 ns delay 110: 2.6 ns delay 111: 3.4 ns delay 000 0 rgmii_bit_rev RO 4.4.4 0 Ring Resiliency Control The following table shows the register settings for the ring resiliency controls at address 30E2. Table 60 • Ring Resiliency, Address 30E2 Bit Name Access Description Default 15 Ring resiliency startup enable (master TR enable) R/W Sticky 0 14 Advertise ring resiliency R/W Sticky 0 13 LP ring resiliency advertisement RO 12 Force ring resiliency R/W enable (override autoneg) Sticky 0 11:6 Reserved RO Reserved 000000 5:4 Ring resiliency status RO Ring resiliency status (from r1000 DSP SM) 00: Timing slave(1) 10: Timing slave becoming master 11: Timing master(1) 01: Timing master becoming slave 11 3:1 Reserved RO Reserved 000 0 Start switchover (only when not in progress) RWSC 1. 0 0 Reflects autoneg master/slave at initial link-up VMDS-10508 VSC8552-02 Datasheet Revision 4.2 71 Registers 4.5 Extended Page 3 Registers To access the extended page 3 registers (16E3–30E3), enable extended register access by writing 0x0003 to register 31. For more information, see Table 47, page 62. When extended page 3 register access is enabled, reads and writes to registers 16–30 affect the extended registers 16E3–30E3 instead of those same registers in the IEEE-specified register space. Registers 0–15 are not affected by the state of the extended page register access. Writing 0x0000 to register 31 restores the main register access. The following table lists the addresses and register names in the extended register page 3 space. These registers are accessible only when the device register 31 is set to 0x0003. Table 61 • 4.5.1 Extended Registers Page 3 Space Address Name 16E3 MAC SerDes PCS Control 17E3 MAC SerDes PCS Status 18E3 MAC SerDes Clause 37 Advertised Ability 19E3 MAC SerDes Clause 37 Link Partner Ability 20E3 MAC SerDes Status 21E3 Media SerDes Transmit Good Packet Counter 22E3 Media SerDes Transmit CRC Error Counter 23E3 Media SerDes PCS Control 24E3 Media SerDes PCS Status 25E3 Media SerDes Clause 37 Advertised Ability 26E3 Media SerDes Clause 37 Link Partner Ability 27E3 Media SerDes status 28E3 Fiber Media CRC Good Counter 29E3 Fiber Media CRC Error Counter 30E3 Reserved MAC SerDes PCS Control The register at address 16E3 consists of the bits that provide access to and control over MAC SerDes PCS block. The following table shows the settings available. Table 62 • MAC SerDes PCS Control, Address 16E3 (0x10) Bit Name Access Description 15 MAC interface disable R/W Sticky bit. 0 1: 1000BASE-X MAC interface disable when media link down. 14 MAC interface restart R/W Sticky bit. 1: 1000BASE-X MAC interface restart on media link change. 0 13 MAC interface PD enable R/W Sticky bit. 1: MAC interface autonegotiation parallel detect enable. 0 VMDS-10508 VSC8552-02 Datasheet Revision 4.2 Default 72 Registers Table 62 • MAC SerDes PCS Control, Address 16E3 (0x10) (continued) Bit Name Access Description Default 12 MAC interface autonegotiation restart R/W Self-clearing bit. 1: Restart MAC interface autonegotiation. 0 11 Force advertised ability R/W 1: Force 16-bit advertised ability from register 0 18E3. 10:8 SGMII preamble control R/W 000: No effect on the start of packet. 001 001: If both the first two nibbles of the 10/100 packet are not 0x5, a byte of 0x55 must be prefixed to the output, otherwise there will be no effect on the start of packet. 010: If both the first two nibbles of the 10/100 packet are not 0x5, a byte of 0x55 must be prefixed to the output. An additional byte of 0x55 must be prefixed to the output if the next two nibbles are also not 0x5. 011–111: Reserved. 7 MAC SerDes autonegotiation enable R/W Sticky bit. 1: MAC SerDes ANEG enable. 6 SerDes polarity at input of R/W MAC 1: Invert polarity of signal received at input of 0 MAC. 5 SerDes polarity at output R/W of MAC 1: Invert polarity of signal at output of MAC. 4 Fast link status enable R/W 1: Use fast link fail indication as link status indication to MAC SerDes. 0: Use normal link status indication to MAC SerDes. 0 3 Reserved R/W Reserved. 0 2:0 Reserved RO Reserved. 4.5.2 0 MAC SerDes PCS Status The register at address 17E3 consists of the bits that provide status from the MAC SerDes PCS block. The following table shows the settings available. Table 63 • MAC SerDes PCS Status, Address 17E3 (0x11) Bit Name Access Description 15:13 Reserved RO Reserved 12 SGMII alignment error RO 1: RGMII/SGMII alignment error occurred 11 MAC interface LP autonegotiation restart RO 1: MAC interface link partner autonegotiation restart request occurred 10 Reserved RO Reserved 9:8 MAC remote fault RO 01, 10, and 11: Remote fault detected from MAC 00: No remote fault detected from MAC 7 Asymmetric pause advertisement RO 1: Asymmetric pause advertised by MAC 6 Symmetric pause advertisement RO 1: Symmetric pause advertised by MAC 5 Full duplex advertisement RO 1: Full duplex advertised by MAC 4 Half duplex advertisement RO 1: Half duplex advertised by MAC VMDS-10508 VSC8552-02 Datasheet Revision 4.2 73 Registers Table 63 • MAC SerDes PCS Status, Address 17E3 (0x11) (continued) Bit Name Access Description 3 MAC interface LP autonegotiation capable RO 1: MAC interface link partner autonegotiation capable 2 MAC interface link status RO 1: MAC interface link status connected 1 MAC interface autonegotiation complete RO 1: MAC interface autonegotiation complete 0 MAC comma detect RO 1: Comma currently detected 0: comma currently not detected 4.5.3 MAC SerDes Clause 37 Advertised Ability The register at address 18E3 consists of the bits that provide access to and control over MAC SerDes Clause 37 advertised ability. The following table shows the settings available. MAC SerDes Cl37 Advertised Ability, Address 18E3 (0x12) Table 64 • Bit Name 15:0 MAC SerDes advertised R/W ability 4.5.4 Access Description Current configuration code word being advertised (this register is read/write if 16E3.11 = 1) Default 0x01E0 MAC SerDes Clause 37 Link Partner Ability The register at address 19E3 consists of the bits that provide status of the MAC SerDes link partner's Clause 37 advertised ability. The following table shows the settings available. Table 65 • MAC SerDes Cl37 LP Ability, Address 19E3 (0x13) Bit Name 15:0 MAC SerDes LP ability RO 4.5.5 Access Description Last configuration code word received from link partner MAC SerDes Status The register at address 20E3 consists of the bits that provide access to MAC SerDes status. The following table shows the settings available. Table 66 • MAC SerDes Status, Address 20E3 (0x14) Bit Name Access Description 15 Reserved RO Reserved 14 MAC comma detect RO Super-sticky bit. Cleared upon SW reset. 1: Comma detected 0: Comma not detected 13 QSGMII sync status RO 12:0 Reserved RO Reserved VMDS-10508 VSC8552-02 Datasheet Revision 4.2 74 Registers 4.5.6 Media SerDes Transmit Good Packet Counter The register at address 21E3 consists of the bits that provide status of the media SerDes transmit good packet counter. The following table shows the settings available. Media SerDes Tx Good Packet Counter, Address 21E3 (0x15) Table 67 • Bit Name Access Description 15 Tx good packet counter active RO 1: Transmit good packet counter active 14 Reserved RO Reserved 13:0 Tx good packet count RO Transmit good packet count modulo 10000 4.5.7 Media SerDes Transmit CRC Error Counter The register at address 22E3 consists of the bits that provide status of the media SerDes transmit packet count that had a CRC error. The following table shows the settings available. Table 68 • 4.5.8 Media SerDes Tx CRC Error Counter, Address 22E3 (0x16) Bit Name Access Description 15:8 Reserved RO 7:0 Tx CRC packet count RO Reserved Transmit CRC packet count (saturates at 255) Media SerDes PCS Control The register at address 23E3 consists of the bits that provide access to and control over Media SerDes PCS control. The following table shows the settings available. Table 69 • Media SerDes PCS Control, Address 23E3 (0x17) Bit Name Access Description 15:14 Reserved RO Reserved 13 Media interface autonegotiation parallel-detection R/W Sticky bit. 1: SerDes media autonegotiation parallel detect enabled Default 0 12 Reserved RO Reserved 11 Force advertised ability R/W 1: Force 16-bit advertised ability from register 25E3.15:0 10:7 Reserved RO Reserved 6 Polarity reversal input Media SerDes polarity reversal input 0: No polarity reversal (default) 1: Polarity reversed 0 5 Polarity reversal output Media SerDes polarity reversal output 0: No polarity reversal (default) 1: Polarity reversed 0 4:0 Reserved RO 0 Reserved VMDS-10508 VSC8552-02 Datasheet Revision 4.2 75 Registers 4.5.9 Media SerDes PCS Status The register at address 24E3 consists of the bits that provide status of the Media SerDes PCS block. The following table shows the settings available. Table 70 • 4.5.10 Media SerDes PCS Status, Address 24E3 (0x18) Bit Name Access Description 15:14 Reserved RO 13 SerDes protocol transfer RO 100 Mb or 100BASE-FX link status 12 SerDes protocol transfer RO 10 Mb link status 11 Media interface link partner autonegotiation restart RO 1: Media interface link partner autonegotiation restart request occurred 10 Reserved RO Reserved 9:8 Remote fault detected RO 01, 10, 11: Remote fault detected from link partner 7 Link partner asymmetric pause RO 1: Asymmetric pause advertised by link partner 6 Link partner symmetric pause RO 1: Symmetric pause advertised by link partner 5 Link partner full duplex advertisement RO 1: Full duplex advertised by link partner 4 Link partner half duplex advertisement RO 1: Half duplex advertised by link partner 3 Link partner autonegotiation capable RO 1: Media interface link partner autonegotiation capable 2 Media interface link status RO 1: Media interface link status 1 Media interface autonegotiation RO complete 1: Media interface autonegotiation complete 0 Reserved Reserved Reserved Media SerDes Clause 37 Advertised Ability The register at address 25E3 consists of the bits that provide access to and control over Media SerDes Clause 37 advertised ability. The following table shows the settings available. Media SerDes Cl37 Advertised Ability, Address 25E3 (0x19) Table 71 • Bit Name Access Description Default 15:0 Media SerDes advertised ability R/W 0x0000 4.5.11 Current configuration code word being advertised. This register is read/write when 23E3.11 = 1. Media SerDes Clause 37 Link Partner Ability The register at address 26E3 consists of the bits that provide status of the media SerDes link partner's Clause 37 advertised ability. The following table shows the settings available. Table 72 • MAC SerDes Cl37 LP Ability, Address 26E3 (0x1A) Bit Name Access Description 15:0 Media SerDes LP ability RO Last configuration code word received from link partner VMDS-10508 VSC8552-02 Datasheet Revision 4.2 76 Registers 4.5.12 Media SerDes Status The register at address 27E3 consists of the bits that provide access to Media SerDes status. The following table shows the settings available. Table 73 • Media SerDes Status, Address 27E3 (0x1B) Bit Name Access Description 15 K28.5 comma realignment RO Self-clearing bit. 1: K28.5 comma re-alignment has occurred 14 Signal detect RO Self-clearing bit. Sticky bit. 1: SerDes media signal detect 13:0 Reserved RO Reserved 4.5.13 Fiber Media CRC Good Counter Register 28E3 makes it possible to read the contents of the CRC good counter for packets that are received on the Fiber media interface; the number of CRC routines that have executed successfully. The following table shows the expected readouts. Fiber Media CRC Good Counter, Address 28E3 (0x1C) Table 74 • Bit Name Access Description Default 15 Packet since last read RO Self-clearing bit. 1: Packet received since last read. 0 14 Reserved RO Reserved. 13:0 Fiber media CRC good counter contents RO Self-clearing bit. Counter containing the number of packets with valid CRCs. This counter does not saturate and will roll over. 4.5.14 0x000 Fiber Media CRC Error Counter Register 29E3 makes it possible to read the contents of the CRC error counter for packets that are received on the Fiber media interface. The following table shows the expected readouts. Table 75 • 4.6 Fiber Media CRC Error Counter, Address 29E3 (0x1D) Bit Name Access Description 15:8 Reserved RO 7:0 Fiber Media CRC RO error counter Default Reserved. Self-clearing bit. CRC error counter for packets received on the Fiber media interface. The value saturates at 0xFF and subsequently clears when read and restarts count. 0x00 General Purpose Registers Accessing the general purpose register space is similar to accessing the extended page registers. Set register 31 to 0x0010. This sets all 32 registers to the general purpose register space. To restore main register page access, write 0x0000 to register 31. VMDS-10508 VSC8552-02 Datasheet Revision 4.2 77 Registers The following table lists the addresses and register names in the general purpose register page space. These registers are accessible only when the device register 31 is set to 0x0010. All general purpose register bits are super-sticky. General Purpose Registers Page Space Table 76 • 4.6.1 Address Name 0G–12G Reserved 13G LED/SIGDET/GPIO Control 14G GPIO Control 2 15G GPIO Input 16G GPIO Output 17G GPIO Output Enable 18G Micro Command 19G MAC Mode and Fast Link Configuration 20G Two-Wire Serial MUX Control 1 21G Two-Wire Serial MUX Control 2 22G Two-Wire Serial MUX Data Read/Write 23G Recovered Clock 0 Control 24G Recovered Clock 1 Control 25G Enhanced LED Control 26G Reserved 27G Reserved 28G Reserved 29G Global Interrupt Status 30G Extended Revision ID Reserved General Purpose Address Space The bits in registers 0G to 12G of the general purpose register space are reserved. 4.6.2 SIGDET/GPIO Control The SIGDET control bits configure the GPIO[1:0]/SIGDET[1:0] pins to function either as signal detect pins for each fiber media port, or as GPIOs. The following table shows the values that can be written. Table 77 • SIGDET/GPIO Control, Address 13G (0x0D) Bit Name Access Description Default 15:12 Reserved RO Reserved 00 11:10 GPIO5/I2C_SCL_1 R/W 00: SCL for PHY1 01: Reserved 10: Reserved 11: Controlled by MII registers 15G to 17G1 00 9:8 GPIO4/I2C_SCL_0 R/W 00: SCL for PHY0 01: Reserved 10: Reserved 11: Controlled by MII registers 15G to 17G2 00 7:4 Reserved Reserved 00 RO VMDS-10508 VSC8552-02 Datasheet Revision 4.2 78 Registers SIGDET/GPIO Control, Address 13G (0x0D) (continued) Table 77 • Bit Name Access Description Default 3:2 GPIO1/SIGDET1 control R/W 00: SIGDET operation 01: Reserved 10: Reserved 11: Controlled by MII registers 15G to 17G 00 1:0 GPIO0/SIGDET0 control R/W 00: SIGDET operation 01: Reserved 10: Reserved 11: Controlled by MII registers 15G to 17G 00 1. 2. 4.6.3 Register 20G bit 1 must be clear in order for this setting to take effect. Register 20G bit 0 must be clear in order for this setting to take effect. GPIO Control 2 The GPIO control 2 register configures the functionality of the COMA_MODE input pins, and provides control for possible GPIO pin options. Table 78 • GPIO Control 2, Address 14G (0x0E) Bit Name Access Description 15:14 GPIO12 and GPIO13 R/W GPIO12 and GPIO13 control. 00: Reserved 01: Reserved. 10: Reserved. 11: GPIO12/GPIO13 operation. Controlled by MII registers 15G to 17G. 13 COMA_MODE output enable (active low) R/W 1: COMA_MODE pin is an input. 0: COMA_MODE pin is an output. 1 12 COMA_MODE output data R/W Value to output on the COMA_MODE pin when it is configured as an output. 0 11 COMA_MODE input data RO Data read from the COMA_MODE pin. 10 Tri-state enable for two-wire serial bus R/W 1: Tri-states two-wire serial bus output signals instead of driving them high. This allows those signals to be pulled above VDD25 using an external pull-up resistor. 0: Drive two-wire serial bus output signals to high and low values as appropriate. 9 Tri-state enable for LEDs R/W 1 1: Tri-state LED output signals instead of driving them high. This allows the signals to be pulled above VDDIO using an external pull-up resistor. 0: Drive LED bus output signals to high and low values. 8 Reserved RO Reserved 7:6 GPIO11 R/W GPIO11 control. 00: Reserved 01: Reserved 10: Reserved 11: Controlled by MII registers 15G to 17G VMDS-10508 VSC8552-02 Datasheet Revision 4.2 Default 1 0 79 Registers Table 78 • GPIO Control 2, Address 14G (0x0E) (continued) Bit Name Access Description 5:4 GPIO10 R/W GPIO10 control. 00: Reserved 01: Reserved 10: Reserved 11: Controlled by MII registers 15G to 17G 3:2 GPIO9/FASTLINK_FAIL R/W GPIO9/FASTLINK_FAIL control. 00: FASTLINK_FAIL operation 01: Reserved 10: Reserved 11: Controlled by MII registers 15G to 17G 1:0 GPIO8/I2C_SDA R/W GPIO8/I2C_SDA control. 00: I2C_SDA operation 01: Reserved 10: Reserved 11: Controlled by MII registers 15G to 17G 4.6.4 Default GPIO Input The input register contains information about the input to the device GPIO pins. Read from this register to access the data on the device GPIO pins. The following table shows the readout you can expect. Table 79 • GPIO Input, Address 15G (0x0F) Bit Name Access Description Default 15:14 Reserved RO Reserved 00 13 GPIO13 RO GPIO13 input 1 12 GPIO12 RO GPIO12 input 1 11 GPIO11 RO GPIO11 input 0 10 GPIO10 RO GPIO10 input 0 9 GPIO9/FASTLINK_FAIL RO GPIO9/FASTLINK_FAIL input 1 8 GPIO8/I2C_SDA RO GPIO8/I2C_SDA input 1 7:6 Reserved RO Reserved 0 5 GPIO5/I2C_SCL_1 RO GPIO5/I2C_SCL_1 input 1 4 GPIO4/I2C_SCL_0 RO GPIO4/I2C_SCL_0 input 1 3:2 Reserved RO Reserved 1 GPIO1/SIGDET1 RO GPIO1/SIGDET1 input 1 0 GPIO0/SIGDET0 RO GPIO0/SIGDET0 input 0 4.6.5 GPIO Output The output register allows you to access and control the output from the device GPIO pins. The following table shows the values you can write. Table 80 • GPIO Output, Address 16G (0x10) Bit Name Access Description 15:14 Reserved RO Reserved 13 GPIO13 R/W GPIO13 output VMDS-10508 VSC8552-02 Datasheet Revision 4.2 Default 0 80 Registers Table 80 • GPIO Output, Address 16G (0x10) (continued) Bit Name Access Description Default 12 GPIO12 R/W 0 GPIO12 output 11 GPIO11 R/W GPIO11 output 0 10 GPIO10 R/W GPIO10 output 0 9 GPIO9/FASTLINK_FAIL R/W GPIO9/FASTLINK_FAIL output 0 8 GPIO8/I2C_SDA R/W GPIO8/I2C_SDA output 0 7:6 Reserved RO Reserved 0 5 GPIO5/I2C_SCL_1 R/W GPIO5/I2C_SCL_1 output 0 4 GPIO4/I2C_SCL_0 R/W GPIO4/I2C_SCL_0 output 0 3:2 Reserved RO Reserved 1 GPIO1/SIGDET1 R/W GPIO1/SIGDET1 output 0 0 GPIO0/SIGDET0 R/W GPIO0/SIGDET0 output 0 4.6.6 GPIO Pin Configuration Register 17G in the GPIO register space controls whether a particular GPIO pin functions as an input or an output. The following table shows the settings available. Table 81 • 4.6.7 GPIO Input/Output Configuration, Address 17G (0x11) Bit Name Access Description Default 15:14 Reserved RO Reserved 13 GPIO13 R/W GPIO13 output enable 0 12 GPIO12 R/W GPIO12 output enable 0 11 GPIO11 R/W GPIO11 output enable 0 10 GPIO10 R/W GPIO10 output enable 0 9 GPIO9/FASTLINK_FAIL R/W GPIO9/FASTLINK_FAIL output enable 0 8 GPIO8/I2C_SDA R/W GPIO8/I2C_SDA output enable 0 7:6 Reserved RO Reserved 0 5 GPIO5/I2C_SCL_1 R/W GPIO5/I2C_SCL_1 output enable 0 4 GPIO4/I2C_SCL_0 R/W GPIO4/I2C_SCL_0 output enable 0 3:2 Reserved RO Reserved 1 GPIO1/SIGDET1 R/W GPIO1/SIGDET1 output enable 0 0 GPIO0/SIGDET0 R/W GPIO0/SIGDET0 output 0 Microprocessor Command Register 18G is a command register. Bit 15 tells the internal processor to execute the command. When bit 15 is cleared the command has completed. Software needs to wait until bit 15 = 0 before proceeding with the next PHY register access. Bit 14 = 1 typically indicates an error condition where the squelch patch was not loaded. Use the following steps to execute the command: 1. 2. 3. Write desired command Check bit 15 (move existing text) Check bit 14 (if set, then error) Commands may take up to 25 ms to complete before bit 15 changes to 0. VMDS-10508 VSC8552-02 Datasheet Revision 4.2 81 Registers Note: All MAC interfaces must be the same — all QSGMII, RGMII, or SGMII. Microprocessor Command Register, Address 18G Table 82 • Command Setting Enable 2 ports MAC SGMII 0x80F0 Enable 2 ports MAC 1/2 QSGMII 0x80E0 (1) QSGMII transmitter control Enable 2 ports Media 1000BASE-X 0x8FC1(2) Enable 2 ports Media 100BASE-FX 0x8FD1(2) 1. Contact your Microsemi representative for an initialization script that greatly simplifies the programming of QSGMII transmit controls. The “F” in the command has a bit representing each of the four PHYs. To exclude a PHY from the configuration, set its bit to 0. For example, the configuration of PHY 3 and PHY 2 to 1000BASE-X would be 1100 or a “C” and the command would be 0x8CC1. 2. 4.6.8 MAC Configuration and Fast Link Register 19G in the GPIO register space controls the MAC interface mode and the selection of the source PHY for the fast link failure indication. The following table shows the settings available for the GPIO9/FASTLINK-FAIL pin. Table 83 • MAC Configuration and Fast Link Register, Address 19G (0x13) Bit Name Access Description Default 15:14 MAC configuration R/W Select MAC interface mode 00: SGMII 01: QSGMII 10: RGMII 11: Reserved 00 13:4 Reserved RO Reserved 3:0 Fast link failure port setting R/W Select fast link failure PHY source 0000: Port0 0001: Port1 0010: Reserved 0011: Reserved 1100–1111: Output disabled 4.6.9 0xF Two-Wire Serial MUX Control 1 The following table shows the settings available to control the integrated two-wire serial MUX. Table 84 • Two-Wire Serial MUX Control 1, Address 20G (0x14) Bit Name Access Description 15:9 Two-wire serial device address R/W Top 7 bits of the 8-bit address sent out on the two 0xA0 wire serial stream. The bottom bit is the read/write signal, which is controlled by register 21G, bit 8. SFPs use 0xA0. 8:6 Reserved RO Reserved. 5:4 Two-wire serial SCL clock frequency R/W 00: 50 kHz 01: 100 kHz 10: 400 kHz 11: 2 MHz VMDS-10508 VSC8552-02 Datasheet Revision 4.2 Default 01 82 Registers Table 84 • Two-Wire Serial MUX Control 1, Address 20G (0x14) (continued) Bit Name Access Description 3 Two-wire serial MUX port 3 enable R/W 1: Enabled. 0 0: Two-wire serial disabled. Becomes GPIO pin. 2 Two-wire serial MUX port 2 enable R/W 1: Enabled. 0 0: Two-wire serial disabled. Becomes GPIO pin. 1 Two-wire serial MUX port 1 enable R/W 1: Enabled. 0 0: Two-wire serial disabled. Becomes GPIO pin. 0 Two-wire serial MUX port 0 enable R/W 0 1: Enabled. 0: Two-wire serial disabled. Two-wire serial MUX port 0 becomes GPIO pin if serial LED function is enabled, regardless of the settings of this bit. 4.6.10 Default Two-Wire Serial MUX Control 2 Register 21G is used to control the two-wire serial MUX for status and control of two-wire serial slave devices. Table 85 • Two-Wire Serial MUX Interface Status and Control, Address 21G (0x15) Bit Name Access Description Default 15 Two-wire serial MUX ready RO 1: Two-wire serial MUX is ready for read or write 1 14:12 Reserved RO Reserved 11:10 PHY port Address R/W Specific VSC8552-02 PHY port being addressed. 9 Enable two-wire serial MUX access R/W Self-clearing bit. 0 1: Execute read or write through the two-wire serial MUX based on the settings of register bit 21G.8 8 Two-wire serial MUX read or write R/W 1: Read from two-wire serial MUX 0: Write to two-wire serial MUX 7:0 Two-wire serial MUX address R/W Sets the address of the two-wire serial MUX 0x00 used to direct read or write operations. 4.6.11 00 1 Two-Wire Serial MUX Data Read/Write Register 22G in the extended register space enables access to the two-wire serial MUX. Table 86 • Two-Wire Serial MUX Data Read/Write, Address 22G (0x16) Bit Name Access Description 15:8 Two-wire serial MUX RO read data Eight-bit data read from two-wire serial MUX; requires setting both register 21G.9 and 21G.8 to 1. 7:0 Two-wire serial MUX R/W write data Eight-bit data to be written to two-wire serial MUX. 0x00 VMDS-10508 VSC8552-02 Datasheet Revision 4.2 Default 83 Registers 4.6.12 Recovered Clock 1 Control Register 23G in the extended register space controls the functionality of the recovered clock 1 output signal. Table 87 • Recovered Clock 1 Control, Address 23G (0x17) Bit Name Access Description Default 15 Enable RCVRDCLK1 R/W 1: Enable recovered clock 1 output 0: Disable recovered clock 1 output 0 14:11 Clock source select R/W Select bits for source PHY for recovered clock: 0000: PHY0 0001: PHY1 0100–1111: Reserved 0000 10:8 Clock frequency select R/W Select output clock frequency: 000: 25 MHz output clock 001: 125 MHz output clock 010: 31.25 MHz output clock 011–111: Reserved 000 7:6 Reserved RO Reserved. 5:4 Clock squelch level R/W Select clock squelch level 00: Automatically squelch clock to low when the link is not up, is unstable, is up in a mode that does not support the generation of a recovered clock (1000BASE-T master or 10BASE-T), or is up in EEE mode (100BASE-TX or 1000BASE-T slave). 01: Same as 00 except that the clock is also generated in 1000BASE-T master and 10BASE-T link-up modes. This mode also generates a recovered clock output in EEE mode during reception of LP_IDLE. 10: Squelch only when the link is not up. 11: Disable clock squelch. Note: A clock from the SerDes or Cu PHY will be output on the recovered clock output in this mode when the link is down. When the CLK_SQUELCH_IN pin is set high, it squelches the recovered clocks regardless of bit settings. 3 Reserved RO Reserved. 2:0 Clock selection for specified PHY R/W 000: Serial media recovered clock 001: Copper PHY recovered clock 010: Copper PHY transmitter TCLK 011–111: Reserved VMDS-10508 VSC8552-02 Datasheet Revision 4.2 000 84 Registers 4.6.13 Recovered Clock 2 Control Register 24G in the extended register space controls the functionality of the recovered clock 2 output signal. Table 88 • Recovered Clock 2 Control, Address 24G (0x18) Bit Name Access Description Default 15 Enable RCVRDCLK2 R/W Enable recovered clock 2 output 14:11 Clock source select R/W Select bits for source PHY for recovered clock: 0000 0000: PHY0 0001: PHY1 0100–1111: Reserved 10:8 Clock frequency select R/W Select output clock frequency: 000: 25 MHz output clock 001: 125 MHz output clock 010: 31.25 MHz output clock 011–111: Reserved 7:6 Reserved RO Reserved 5:4 Clock squelch level R/W Select clock squelch level: 00: Automatically squelch clock to low when the link is not up, is unstable, is up in a mode that does not support the generation of a recovered clock (1000BASE-T master or 10BASE-T), or is up in EEE mode (100BASE-TX or 1000BASE-T slave). 01: Same as 00 except that the clock is also generated in 1000BASE-T master and 10BASE-T link-up modes. This mode also generates a recovered clock output in EEE mode during reception of LP_IDLE 10: Squelch only when the link is not up 11: Disable clock squelch. Note: A clock from the SerDes or Cu PHY will be output on the recovered clock output in this mode when the link is down. 0 000 Note: A clock from the SerDes or Cu PHY will be output on the recovered clock output in this mode when the link is down. When the CLK_SQUELCH_IN pin is set high, it squelches the recovered clocks regardless of bit settings. 3 Reserved RO Reserved 2:0 Clock selection for specified PHY R/W 000: Serial media recovered clock 001: Copper PHY recovered clock 010–111: Reserved VMDS-10508 VSC8552-02 Datasheet Revision 4.2 000 85 Registers 4.6.14 Enhanced LED Control The following table contains the bits to control advanced functionality of the parallel and serial LED signals. Table 89 • 4.6.15 Enhanced LED Control, Address 25G (0x19) Bit Name Access Description Default 15:8 LED pulsing duty cycle control R/W 7 Port 1 enhanced serial LED R/W output enable Enable the enhanced serial LED output functionality for port 1 LED pins. 1: Enhanced serial LED outputs 0: Normal function 0 6 Port 0 enhanced serial LED R/W output enable Enable the enhanced serial LED output functionality for port 0 LED pins. 1: Enhanced serial LED outputs 0: Normal function 0 5:3 Serial LED frame rate selection R/W Select frame rate of serial LED stream 000: 2500 Hz frame rate 001: 1000 Hz frame rate 010: 500 Hz frame rate 011: 250 Hz frame rate 100: 200 Hz frame rate 101: 125 Hz frame rate 110: 40 Hz frame rate 111: Output basic serial LED stream See Table 9, page 29. 2:1 Serial LED select R/W Select which LEDs from each PHY to enable on the serial stream 00: Enable all four LEDs of each PHY 01: Enable LEDs 2, 1 and 0 of each PHY 10: Enable LEDs 1 and 0 of each PHY 11: Enable LED 0 of each PHY 0 LED port swapping R/W See LED Port Swapping, page 30. Programmable control for LED pulsing 00 duty cycle when bit 30.12 is set to 1. Valid settings are between 0 and 198. A setting of 0 corresponds to a 0.5% duty cycle and 198 corresponds to a 99.5% duty cycle. Intermediate values change the duty cycle in 0.5% increments 00 Global Interrupt Status The following table contains the interrupt status from the various sources to indicate which one caused that last interrupt on the pin. Table 90 • Global Interrupt Status, Address 29G (0x1D) Bit Name 15:2 Reserved 1 Access Default Description PHY1 interrupt source (1) RO 0x07FF Reserved RO 1 PHY1 interrupt source indication 0: PHY1 caused the interrupt 1: PHY1 did not cause the interrupt VMDS-10508 VSC8552-02 Datasheet Revision 4.2 86 Registers Table 90 • Global Interrupt Status, Address 29G (0x1D) (continued) Bit Name 0 PHY0 interrupt source(1) RO 1. Access Default Description 1 PHY0 interrupt source indication 0: PHY0 caused the interrupt 1: PHY0 did not cause the interrupt This bit is set to 1 when the corresponding PHY’s Interrupt Status register 26 (0x1A) is read. 4.6.16 Extended Revision ID The following table lists the extended revision ID information. Table 91 • 4.7 Extended Revision ID, Address 30G (0x1E) Bit Name Access Default Description 15:1 Reserved RO 0x0000 Reserved 0 Ext Rev ID RO 0x1 Revision E Clause 45 Registers to Support Energy Efficient Ethernet and 802.3bf This section describes the Clause 45 registers that are required to support energy efficient Ethernet. Access to these registers is through the IEEE standard registers 13 and 14 (MMD access control and MMD data or address registers) as described in section 4.2.11 and 4.2.12. The following table lists the addresses and register names in the Clause 45 register page space. When the link is down, 0 is the value returned for the x.180x addresses. Table 92 • Clause 45 Registers Page Space Address Name 1.1801 Tx maximum delay through PHY 1.1803 Tx minimum delay through PHY 1.1805 Rx maximum delay through PHY 1.1807 Rx minimum delay through PHY 3.1 PCS status 1 3.20 EEE capability 3.22 EEE wake error counter 4.1801 Tx maximum delay through xMII (RGMII, SGMII, QSGMII, including FIFO variations) 4.1803 Tx minimum delay through xMII (RGMII, SGMII, QSGMII, including FIFO variations) 4.1805 Rx maximum delay through xMII (RGMII, SGMII, QSGMII, including FIFO variations) 4.1807 Rx minimum delay through xMII (RGMII, SGMII, QSGMII, including FIFO variations) 7.60 EEE advertisement 7.61 EEE link partner advertisement VMDS-10508 VSC8552-02 Datasheet Revision 4.2 87 Registers 4.7.1 PCS Status 1 The bits in the PCS Status 1 register provide a status of the EEE operation from the PCS for the link that is currently active. Table 93 • 4.7.2 PCS Status 1, Address 3.1 Bit Name Access Description 15:12 Reserved RO Reserved 11 Tx LPI received RO/LH 1: Tx PCS has received LPI 0: LPI not received 10 Rx LPI received RO/LH 1: Rx PCS has received LPI 0: LPI not received 9 Tx LPI indication RO 1: Tx PCS is currently receiving LPI 0: PCS is not currently receiving LPI 8 Rx LPI indication RO 1: Rx PCS is currently receiving LPI 0: PCS is not currently receiving LPI 7:3 Reserved RO 2 PCS receive link status RO 1: PCS receive link up 0: PCS receive link down 1:0 Reserved Reserved Reserved RO EEE Capability This register is used to indicate the capability of the PCS to support EEE functions for each PHY type. The following table shows the bit assignments for the EEE capability register. Table 94 • Bit 4.7.3 EEE Capability, Address 3.20 Name Access Description 15:3 Reserved RO 2 1000BASE-T EEE RO 1: EEE is supported for 1000BASE-T 0: EEE is not supported for 1000BASE-T 1 100BASE-TX EEE RO 1: EEE is supported for 100BASE-TX 0: EEE is not supported for 100BASE-TX 0 Reserved RO Reserved Reserved EEE Wake Error Counter This register is used by PHY types that support EEE to count wake time faults where the PHY fails to complete its normal wake sequence within the time required for the specific PHY type. The definition of the fault event to be counted is defined for each PHY and can occur during a refresh or a wakeup as defined by the PHY. This 16-bit counter is reset to all zeros when the EEE wake error counter is read or when the PHY undergoes hardware or software reset. EEE Wake Error Counter, Address 3.22 Table 95 • Bit Name Access Description 15:0 Wake error counter RO Count of wake time faults for a PHY VMDS-10508 VSC8552-02 Datasheet Revision 4.2 88 Registers 4.7.4 EEE Advertisement This register defines the EEE advertisement that is sent in the unformatted next page following a EEE technology message code. The following table shows the bit assignments for the EEE advertisement register. Table 96 • EEE Advertisement, Address 7.60 Bit Name Access Description 15:3 Reserved RO 2 1000BASE-T EEE R/W 1: Advertise that the 1000BASE-T has EEE capability 0: Do not advertise that the 1000BASE-T has EEE capability 0 1 100BASE-TX EEE R/W 1: Advertise that the 100BASE-TX has EEE capability 0: Do not advertise that the 100BASE-TX has EEE capability 0 0 Reserved RO Reserved 4.7.5 Default Reserved EEE Link Partner Advertisement All the bits in the EEE LP Advertisement register are read only. A write to the EEE LP advertisement register has no effect. When the AN process has been completed, this register will reflect the contents of the link partner's EEE advertisement register. The following table shows the bit assignments for the EEE advertisement register. Table 97 • EEE Advertisement, Address 7.61 Bit Name Access Description 15:3 Reserved RO 2 1000BASE-T EEE RO 1: Link partner is advertising EEE capability for 1000BASE-T 0: Link partner is not advertising EEE capability for 1000BASE-T 1 100BASE-TX EEE RO 1: Link partner is advertising EEE capability for 100BASE-TX 0: Link partner is not advertising EEE capability for 100BASE-TX 0 Reserved RO Reserved Reserved The following table shows the bit assignments for the 802.3bf registers. When the link is down, 0 is the value returned. cl45reg1_1801 would be device address of 1 and register address of 1801. Table 98 • 802.3bf Registers Register Name Function 1.1801 cl45reg1_1801_val[15:0] Tx maximum delay through PHY (PMA/PMD/PCS) 1.1803 cl45reg1_1803_val[15:0] Tx minimum delay through PHY (PMA/PMD/PCS) 1.1805 cl45reg1_1805_val[15:0] Rx maximum delay through PHY (PMA/PMD/PCS) 1.1807 cl45reg1_1807_val[15:0] Rx minimum delay through PHY (PMA/PMD/PCS) 4.1801 cl45reg4_1801_val[15:0] Tx maximum delay through xMII (RGMII, SGMII, QSGMII, including FIFO variations) VMDS-10508 VSC8552-02 Datasheet Revision 4.2 89 Registers Table 98 • 802.3bf Registers (continued) Register Name Function 4.1803 cl45reg4_1803_val[15:0] Tx minimum delay through xMII (RGMII, SGMII, QSGMII, including FIFO variations) 4.1805 cl45reg4_1805_val[15:0] Rx maximum delay through xMII (RGMII, SGMII, QSGMII, including FIFO variations) 4.1807 cl45reg4_1807_val[15:0] Rx minimum delay through xMII (RGMII, SGMII, QSGMII, including FIFO variations) VMDS-10508 VSC8552-02 Datasheet Revision 4.2 90 Electrical Specifications 5 Electrical Specifications This section provides the DC characteristics, AC characteristics, recommended operating conditions, and stress ratings for the VSC8552-02 device. 5.1 DC Characteristics This section contains the DC specifications for the VSC8552-02 device. 5.1.1 VDD25 The following table shows the DC specifications for the pins referenced to VDD25. The specifications listed in the following table are valid only when VDD1 = 1.0 V, VDD1A = 1.0 V, or VDD25A = 2.5 V. Table 99 • VDD25 DC Characteristics Parameter Symbol Minimum Output high voltage VOH 2.0 Output low voltage VOL Input high voltage VIH Input low voltage Unit Condition V IOH = –1.0 mA 0.4 V IOL = 1.0 mA 1.85 3.3 V VIL –0.3 0.7 V Input leakage current IILEAK –32 32 µA Internal resistor included Output leakage current IOLEAK –32 32 µA Internal resistor included 6 mA Output low current drive IOL strength Output high current drive IOH strength 5.1.2 Maximum –6 mA LED and GPIO The following table shows the DC specifications for the LED and GPIO pins. Table 100 • LED and GPIO Characteristics 5.1.3 Pin Symbol LED IOH LED IOL GPIO IOH GPIO IOL Minimum Maximum Unit 24 mA –24 mA 12 mA –12 mA Internal Pull-Up or Pull-Down Resistors Internal pull-up or pull-down resistors are specified in the following table. For more information about signals with internal pull-up or pull-down resistors, see Pins by Function, page 112. All internal pull-up resistors are connected to their respective I/O supply. Table 101 • Internal Pull-Up or Pull-Down Resistors Parameter Symbol Minimum Typical Maximum Unit Internal pull-up resistor, GPIO RPU_GPIO 33 53 90 kΩ VMDS-10508 VSC8552-02 Datasheet Revision 4.2 91 Electrical Specifications Table 101 • Internal Pull-Up or Pull-Down Resistors (continued) Parameter Symbol Minimum Typical Maximum Unit Internal pull-up resistor, all others RPU 96 120 144 kΩ Internal pull-down resistor RPD 96 120 144 kΩ 5.1.4 Reference Clock The following table shows the DC specifications for a differential reference clock input signal Table 102 • Reference Clock DC Characteristics Parameter Symbol Minimum Input voltage range VIP,VIN Input differential peak-to-peak voltage |VID| Input common-mode voltage VICM Differential input impedance RI 1. 2. 5.1.5 Typical Maximum Unit –25 1260 mV 1501 1200 mV 0 12002 mV Ω 100 To meet jitter specifications, the minimum |VID| must be 400 mV. When using a single-ended clock input, the REFCLK_P low voltage must be less than VDDA – 200 mV, and the high voltage level must be greater than VDDA + 200 mV The maximum common-mode voltage is provided without a differential signal. The common-mode voltage is only limited by the maximum and minimum input voltage range and by the differential amplitude of the input signal. SerDes Interface (SGMII) The SerDes output drivers are designed to operate in SGMII/LVDS mode. The SGMII/LVDS mode meets or exceeds the DC requirements of Serial-GMII Specification Revision 1.9 (ENG-46158), unless otherwise noted. The following table lists the DC specifications for the SGMII driver. The values are valid for all configurations, unless stated otherwise. Table 103 • SerDes Driver DC Specifications Parameter Symbol Maximum Unit Condition Output high voltage, VOA or VOB VOH 1050 mV RL = 100 Ω ±1% Output low voltage, VOA or VOB VOL 0 mV RL = 100 Ω ±1% Output differential peak voltage |VOD| 350 450 mV VDD_VS = 1.0 V RL = 100 Ω ±1% Output differential peak voltage, fiber media 1000BASE-X |VOD| 350 450 mV VDD_VS = 1.0 V RL = 100 Ω ±1% Output offset voltage(1) VOS 420 580 mV VDD_VS = 1.0 V RL = 100 Ω ±1% DC output impedance, single-ended, SGMII mode RO 40 140 Ω VC = 1.0 V See Figure 41, page 93 RO mismatch between A and B, SGMII mode(2) ΔRO 10 % VC = 1.0 V See Figure 41, page 93 25 mV RL = 100 Ω ±1% Change in |VOD| between 0 and 1, Δ|VOD| SGMII mode Minimum VMDS-10508 VSC8552-02 Datasheet Revision 4.2 92 Electrical Specifications Table 103 • SerDes Driver DC Specifications (continued) Parameter Symbol Change in VOS between 0 and 1, SGMII mode Minimum Maximum Unit Condition ΔVOS 25 mV RL = 100 Ω ±1% Output current, driver shorted to GND, SGMII mode |IOSA|, |IOSB| 40 mA Output current, drivers shorted together, SGMII mode |IOSAB| 12 mA 1. Requires AC-coupling for SGMII compliance. 2. Matching of reflection coefficients. For more information about test methods, see IEEE Std 1596.3-1996. Figure 39 • SGMII DC Transmit Test Circuit VOA 100 Ω ± 1% VOD = VOA – VOB VOS = ½ (VOA + VOB) VOB Figure 40 • SGMII DC Definitions VOA VOB GND VOD 0 V differential |VOD| |VOD| 0 V differential VOS GND VOS Δ|VOD| = | |VOAH – VOBL| – |VOBH – VOAL| | ΔVOS = | ½(VOAH + VOBL) – ½(VOAL + VOBH) | Figure 41 • SGMII DC Driver Output Impedance Test Circuit VOA 50 Ω ± 0.1% +V – c 0 and 1 VOB 50 Ω ± 0.1% The following table lists the DC specifications for the SGMII receivers. Table 104 • SerDes Receiver DC Specifications Parameter Symbol Minimum Maximum Unit Input voltage range, VIA or VIB VI –25 1250 mV VMDS-10508 VSC8552-02 Datasheet Revision 4.2 Condition 93 Electrical Specifications Table 104 • SerDes Receiver DC Specifications (continued) Parameter Symbol Minimum Maximum Unit Input differential peak-to-peak voltage |VID| 100 1000 mV Input common-mode voltage(1) VICM 0 VDD_A(2) mV Receiver differential input impedance RI 80 120 Ω Input differential hysteresis, SGMII mode VHYST 25 1. 2. Condition Without any differential signal mV SGMII compliancy requires external AC-coupling. When interfacing with specific Microsemi devices, DCcoupling is possible. For more information, contact your local Microsemi sales representative. The common-mode voltage is only limited by the maximum and minimum input voltage range and the input signal’s differential amplitude. Figure 42 • SGMII DC Input Definitions VIA VID = VIA – VIB VIC = ½ (VIA + VIB) VIB 5.1.6 Enhanced SerDes Interface (QSGMII) All DC specifications for the enhanced SerDes interface are compliant with QSGMII Specification Revision 1.3 and meet or exceed the requirements in the standard. They are also compliant with OIFCEI-02.0 requirements where applicable. The enhanced SerDes interface supports the following operating modes: SGMII, QSGMII, and SFP. The values in the following table apply to the modes specified in the condition column. The following table shows the DC specifications for the enhanced SerDes driver. Table 105 • Enhanced SerDes Driver DC Specifications Parameter Symbol Minimum Maximum Unit Condition Output differential peak voltage, SFP and QSGMII modes |VODp| 250 400 mV VDD_VS = 1.0 V RL = 100 Ω ±1% maximum drive Output differential peak voltage, SGMII mode(1) |VODp| 150 400 mV VDD_VS = 1.0 V RL = 100 Ω ±1% DC output impedance, single-ended, SGMII mode RO 40 140 Ω VC = 1.0 V See Figure 41, page 93 RO mismatch between A and B, SGMII mode(2) ΔRO 10 % VC = 1.0 V See Figure 41, page 93 25 mV RL = 100 Ω ±1% 25 mV RL = 100 Ω ±1% Change in |VOD| between 0 and 1, Δ|VOD| SGMII mode Change in VOS between 0 and 1, SGMII mode ΔVOS VMDS-10508 VSC8552-02 Datasheet Revision 4.2 94 Electrical Specifications Table 105 • Enhanced SerDes Driver DC Specifications (continued) Parameter Symbol Output current, drivers shorted to ground, SGMII and QSGMII modes Output current, drivers shorted together, SGMII and QSGMII modes Minimum Maximum Unit |IOSA|, |IOSB| 40 mA |IOSAB| 12 mA Condition 1. Voltage is adjustable in 64 steps. 2. Matching of reflection coefficients. For more information about test methods, see IEEE Std 1596.3-1996. The following table lists the DC specifications for the enhanced SerDes receiver. Table 106 • Enhanced SerDes Receiver DC Specifications Parameter Symbol Minimum Maximum Unit VI –0.25 1.2 V Input differential peak-to-peak voltage |VID| 100 1600 mV Input common-mode voltage VICM 0 1200 mV Receiver differential input impedance RI 80 120 Ω Input voltage range, VIA or 1. 5.1.7 VIB(1) Typical 100 QSGMII DC input sensitivity is less than 400 mV. Current Consumption The following tables show the current consumption values for each mode. Add significant margin above the values for sizing power supplies. Table 107 • Current Consumption Mode Typical Maximum Unit Condition 1V Digital 1V 2.5 V Analog Digital 2.5 V 1V Analog Digital 1V 2.5 V Analog Digital 2.5 V Analog Reset 52 55 9 1 460 110 13 5 mA Power down 110 170 10 20 525 220 15 25 mA 1000BASE-T 250 180 15 250 755 245 15 265 mA 2-port SGMII 100BASE-TX 155 175 15 170 645 235 15 190 mA 2-port SGMII 10BASE-T 130 170 15 145 615 230 15 150 mA 2-port SGMII 10BASE-Te 130 170 15 135 615 230 15 140 mA 2-port SGMII 1000BASE-X 145 205 15 35 685 265 15 40 mA 2-port SGMII 100BASE-FX 135 200 15 35 645 260 15 40 mA 2-port SGMII 1000BASE-T 235 100 55 250 740 160 65 265 mA 2-port RGMII 100BASE-TX 140 95 20 170 630 150 20 190 mA 2-port RGMII 10BASE-T 115 90 15 145 600 145 15 150 mA 2-port RGMII 10BASE-Te 115 90 15 135 600 145 15 140 mA 2-port RGMII 1000BASE-X 130 120 55 35 670 180 65 40 mA 2-port RGMII 100BASE-FX 120 115 20 35 630 175 20 40 mA 2-port RGMII VMDS-10508 VSC8552-02 Datasheet Revision 4.2 95 Electrical Specifications Table 107 • Current Consumption (continued) Mode Typical Maximum Unit Condition 1V Digital 1V 2.5 V Analog Digital 2.5 V 1V Analog Digital 1V 2.5 V Analog Digital 2.5 V Analog 1000BASE-T 250 145 10 250 755 210 15 265 mA 2-port half QSGMII 100BASE-TX 155 140 10 170 645 200 15 190 mA 2-port half QSGMII 10BASE-T 130 135 10 145 615 195 15 150 mA 2-port half QSGMII 10BASE-Te 130 135 10 135 615 195 15 140 mA 2-port half QSGMII 1000BASE-X 145 170 10 35 685 230 15 40 mA 2-port half QSGMII 100BASE-FX 135 165 10 35 645 225 15 40 mA 2-port half QSGMII 5.1.8 Thermal Diode The VSC8552-02 device includes an on-die diode and internal circuitry for monitoring die temperature (junction temperature). The operation and accuracy of the diode is not guaranteed and should only be used as a reference. Care should be taken to find compatible grounded cathode temperature monitoring device. A thermal sensor, located on the board or in a stand-alone measurement kit, can monitor and display the die temperature of the switch for thermal management or instrumentation purposes. Temperature measurement using a thermal diode is very sensitive to noise. The following table provides the diode parameter and interface specifications. Note that the ThermDC pin is connected to VSS internally in the device. Table 108 • Thermal Diode Parameters Parameter Symbol Forward bias current IFW Diode ideality factor n Typical Maximum Unit 1 mA 1.008 Note: Microsemi does not support or recommend operation of the thermal diode under reverse bias. The ideality factor, n, represents the deviation from ideal diode behavior as exemplified by the diode equation: I FW = I S ×  e q V d × ---------nkT  – 1 where, Is = saturation current, q = electronic charge, Vd = voltage across the diode, k = Boltzmann Constant, and T = absolute temperature (Kelvin). 5.2 AC Characteristics This section provides the AC specifications for the VSC8552-02 device. 5.2.1 Reference Clock The following table shows the AC specifications for a 125 MHz differential reference clock source. Performance is guaranteed for 125 MHz differential clocks only; however, 125 MHz single-ended clocks are also supported for QSGMII interfaces. VMDS-10508 VSC8552-02 Datasheet Revision 4.2 96 Electrical Specifications 25 MHz clock implementations are available but are limited to SGMII interfaces. For more information, contact your Microsemi representative. Table 109 • Reference Clock AC Characteristics for QSGMII 125 MHz Differential Clock Parameter Symbol Reference clock frequency, REFCLK_SEL2 = 1 ƒ Duty cycle DC Rise time and fall time tr, tf Minimum 40 50 Maximum Unit Condition MHz ±100 ppm 60 % 1.5 ns 20% to 80% threshold RefClk input RMS jitter requirement, bandwidth between 12 kHz and 500 kHz(1) 20 ps To meet jitter generation of 1G output data per IEEE 802.3z RefClk input RMS jitter requirement, bandwidth between 500 kHz and 15 MHz(1) 4 ps To meet jitter generation of 1G output data per IEEE 802.3z RefClk input RMS jitter requirement, bandwidth between 15 MHz and 40 MHz(1) 20 ps To meet jitter generation of 1G output data per IEEE 802.3z RefClk input RMS jitter requirement, bandwidth between 40 MHz and 80 MHz(1) 100 ps To meet jitter generation of 1G output data per IEEE 802.3z Jitter gain from RefClk to SerDes output, bandwidth between 0 MHz and 0.1 MHz 0.3 dB 3 dB 3–20 × log (ƒ/7 MHz) dB Jitter gain from RefClk to SerDes output, bandwidth between 0.1 MHz and 7 MHz 1 Jitter gain from RefClk to SerDes output, bandwidth above 7 MHz 1. 5.2.2 Typical 125.00 1–20 × log (ƒ/7 MHz) Maximum RMS jitter allowed at the RefClk input for the given bandwidth. Recovered Clock This section provides the AC characteristics for the recovered clock output signals. The following illustration shows the test circuit for the recovered clock output signals. Figure 43 • Test Circuit for Recovered Clock Output Signals 39 Ω 50 Ω 8 pF Device Under Test Signal Measurement Point VMDS-10508 VSC8552-02 Datasheet Revision 4.2 97 Electrical Specifications The following table shows the AC specifications for the RCVRDCLK1 and RCVRDCLK2 outputs. Table 110 • Recovered Clock AC Characteristics 5.2.3 Parameter Symbol Recovered clock frequency ƒ 125.00 MHz Recovered clock frequency ƒ 31.25 MHz Recovered clock frequency ƒ 25.00 MHz Recovered clock cycle tRCYC time 8.0 ns Recovered clock cycle tRCYC time 32.0 ns Recovered clock cycle tRCYC time 40.0 ns Frequency stability ƒSTABILITY Duty cycle, master mode DC Clock rise time and fall time tR, tF Minimum 40 Typical 50 Maximum Unit 50 ppm 60 % 600 Condition ps 20% to 80% Peak-to-peak jitter, JPPCLK_Cu copper media interface (1000BASET slave mode) 400 ps 10K samples Peak-to-peak jitter, fiber media interface, 100BASE-FX JPPCLK_FiFX 1.2 ns 10K samples Peak-to-peak jitter, fiber media interface, 1000BASE-X JPPCLK_FiX 250 ps 10K samples SerDes Outputs The values listed in the following table are valid for all configurations, unless otherwise noted. Table 111 • SerDes Outputs AC Specifications Parameter Symbol VOD ringing compared to VS, RGMII/SGMII mode VRING VOD rise time and fall time, tR, tF RGMII/SGMII mode Minimum 100 Maximum Unit Condition ±10 % RL = 100 Ω ±1% 200 ps 20% to 80% of VS RL = 100 Ω ±1% 30 mV Tx disabled Differential peak-to-peak output voltage VOD Differential output return loss, 50 MHz to 625 MHz RLO_DIFF ≥10 dB RL = 100 Ω ±1% Differential output return loss, 625 MHz to 1250 MHz RLO_DIFF 10–10 × log (ƒ/625 MHz) dB RL = 100 Ω ±1% VMDS-10508 VSC8552-02 Datasheet Revision 4.2 98 Electrical Specifications Table 111 • SerDes Outputs AC Specifications (continued) 5.2.4 Parameter Symbol Minimum Common-mode return loss, 50 MHz to 625 MHz RLOCM 6 Interpair skew, RGMII/SGMII mode tSKEW Maximum Unit Condition dB 20 ps SerDes Driver Jitter The following table lists the jitter characteristics for the SerDes output driver. Table 112 • SerDes Driver Jitter Characteristics 5.2.5 Parameter Symbol Maximum Unit Condition Total jitter TJO 192 ps Measured according to IEEE 802.3.38.5 Deterministic jitter DJO 80 ps Measured according to IEEE 802.3.38.5 SerDes Inputs The following table lists the AC specifications for the SerDes inputs. Table 113 • SerDes Input AC Specifications 5.2.6 Parameter Maximum Unit Condition Differential input return loss, 50 MHz to 625 MHz ≥10 dB RL = 100 Ω ±1% Differential input return loss, 625 MHz to 1250 MHz 10–10 × log (ƒ/625 MHz) dB RL = 100 Ω ±1% SerDes Receiver Jitter Tolerance The following table lists jitter tolerances for the SerDes receiver. Table 114 • SerDes Receiver Jitter Tolerance 5.2.7 Parameter Symbol Minimum Unit Condition Total jitter tolerance, greater than 637 kHz, SFP mode TJTI 600 ps Measured according to IEEE 802.3 38.6.8 Deterministic jitter tolerance, greater than 637 kHz, SFP mode DJTI 370 ps Measured according to IEEE 802.3 38.6.8 Cycle distortion jitter tolerance, 100BASE-FX mode JTCD 1.4 ns Measured according to ISO/IEC 9314-3:1990 Data-dependent jitter tolerance, 100BASE-FX mode DDJ 2.2 ns Measured according to ISO/IEC 9314-3:1990 Random peak-to-peak jitter tolerance, 100BASE-FX mode RJT 2.27 ns Measured according to ISO/IEC 9314-3:1990 Enhanced SerDes Interface All AC specifications for the enhanced SerDes interface are compliant with QSGMII Specification Revision 1.3 and meet or exceed the requirements in the standard. They are also compliant with the OIFCEI-02.0 requirements where applicable. VMDS-10508 VSC8552-02 Datasheet Revision 4.2 99 Electrical Specifications The enhanced SerDes interface supports the following modes of operation: SGMII, QSGMII, and SFP. The values in the tables in the following sections apply to the QSGMII modes listed in the condition column and are based on the test circuit shown in Figure 39, page 93. The transmit and receive eye specifications relate to the eye diagrams shown in the following illustration, with the compliance load as defined in the test circuit. Figure 44 • QSGMII Transient Parameters Transmitter Eye Mask Receiver Eye Mask R_Y2 Amplitude (mV) Amplitude (mV) T_Y2 T_Y1 0 –T_Y1 –T_Y2 R_Y1 0 –R_Y1 –R_Y2 0 T_X1 T_X2 1–T_X2 1–T_X1 1.0 0 R_X1 Time (UI) 5.2.7.1 0.5 1–R_X1 1.0 Time (UI) Enhanced SerDes Outputs The following table provides the AC specifications for the enhanced SerDes outputs in SGMII mode. Table 115 • Enhanced SerDes Outputs AC Specifications, SGMII Mode Parameter Symbol Unit interval, 1.25G mode UI VOD ringing compared to VS VRING VOD rise time and fall time t R , tF Minimum Maximum Unit Condition 800 ps 100 Differential peak-to-peak output VOD voltage ±10 % RL = 100 Ω ±1% 200 ps 20% to 80% of VS RL = 100 Ω ±1% 30 mV Tx disabled Differential output return loss, 50 MHz to 625 MHz RLO_DIFF ≥10 dB RL = 100 Ω ±1% Differential output return loss, 625 MHz to 1250 MHz RLO_DIFF 10–10 × log (ƒ/625 MHz) dB RL = 100 Ω ±1% Common-mode return loss, 50 MHz to 625 MHz RLOCM dB Intrapair skew tSKEW 6 20 ps The following table provides the AC specifications for the enhanced SerDes outputs in QSGMII mode. Table 116 • Enhanced SerDes Outputs AC Specifications, QSGMII Mode Parameter Symbol Unit interval, 5G UI VOD rise time and fall time tR, tF Differential peak-to-peak output voltage VOD Minimum Maximum Unit Condition 200 ps 30 96 ps 20% to 80% of VS RL = 100 Ω ±1% 30 mV Tx disabled VMDS-10508 VSC8552-02 Datasheet Revision 4.2 100 Electrical Specifications Table 116 • Enhanced SerDes Outputs AC Specifications, QSGMII Mode 5.2.7.2 Parameter Symbol Differential output return loss, 100 MHz to 2.5 GHz Minimum Maximum Unit Condition RLO_DIFF 8 dB RL = 100 Ω ±1% Differential output return loss, 2.5 GHz to 5 GHz RLO_DIFF 8 dB – 16.6 log (ƒ/2.5 GHz) dB RL = 100 Ω ±1% Eye mask X1 T_X1 0.15 UI Eye mask X2 T_X2 0.4 UI Eye mask Y1 T_Y1 Eye mask Y2 T_Y2 200 mV 450 mV Enhanced SerDes Driver Jitter Characteristics The following table lists the jitter characteristics for the enhanced SerDes driver in QSGMII mode. For information about jitter characteristics for the enhanced SerDes driver in SGMII mode, see Table 112, page 99. Table 117 • Enhanced SerDes Driver Jitter Characteristics, QSGMII Mode 5.2.7.3 Parameter Symbol Maximum Unit Condition Total output jitter TJO 60 ps Measured according to IEEE 802.3.38.5. Deterministic output jitter DJO 10 ps Measured according to IEEE 802.3.38.5. Enhanced SerDes Inputs The following table lists the AC specifications for the enhanced SerDes inputs in SGMII mode. Table 118 • Enhanced SerDes Input AC Specifications, SGMII Mode Parameter Symbol Unit interval, 1.25G Minimum Unit Condition UI ps 800 ps Differential input return loss, 50 MHz to 625 MHz RLI_DIFF 10 dB RL = 100 Ω ±1% Common-mode input return loss, 50 MHz to 625 MHz RLICM dB 6 The following table lists the AC specifications for the enhanced SerDes inputs in QSGMII mode. Table 119 • Enhanced SerDes Inputs AC Specifications, QSGMII Mode Parameter Symbol Minimum Maximum Unit Condition Unit interval, 5G UI Differential input return loss, 100 MHz to 2.5 GHz RLI_DIFF 8 dB RL = 100 Ω ±1% Differential input return loss, 2.5 GHz to 5 GHz RLI_DIFF 8 dB – 16.6 log (ƒ/2.5 GHz) dB RL = 100 Ω ±1% Common-mode input return loss, 100 MHz to 2.5 GHz RLICM dB Eye mask X1 R_X1 200 ps 6 0.3 UI VMDS-10508 VSC8552-02 Datasheet Revision 4.2 101 Electrical Specifications Table 119 • Enhanced SerDes Inputs AC Specifications, QSGMII Mode Parameter Symbol Eye mask Y1 Eye mask Y2 5.2.7.4 Minimum Maximum Unit R_Y1 50 mV R_Y2 450 mV Condition Enhanced SerDes Receiver Jitter Tolerance The following table lists the jitter tolerance for the enhanced SerDes receiver in QSGMII mode. For information about jitter tolerance for the enhanced SerDes receiver in SGMII mode, see Table 114, page 99. Table 120 • Enhanced SerDes Receiver Jitter Tolerance, QSGMII Mode Parameter Symbol Maximum Unit Condition BHPJ 90 ps 92 ps peak-to-peak random jitter and 38 ps sinusoidal jitter (SJHF). Sinusoidal jitter, maximum SJMAX 1000 ps Sinusoidal jitter, high frequency SJHF 10 ps Total jitter tolerance TJTI 120 ps Bounded high-probability jitter 1. 5.2.8 (1) 92 ps peak-to-peak random jitter and 38 ps sinusoidal jitter (SJHF). This is the sum of uncorrelated bounded high probability jitter (0.15 UI), and correlated bounded high probability jitter (0.30 UI). Uncorrelated bounded high probability jitter is distribution where the value of the jitter shows no correlation to any signal level being transmitted, formally defined as deterministic jitter (DJ). Correlated bounded high probability jitter is jitter distribution where the value of the jitter shows a strong correlation to the signal level being transmitted. Basic Serial LEDs This section contains the AC specifications for the basic serial LEDs. Table 121 • Basic Serial LEDs AC Characteristics Parameter Symbol Typical Unit LED_CLK cycle time tCYC 1024 ns Pause between LED port sequences tPAUSE_port 3072 ns Pause between LED bit sequences tPAUSE_bit 25.541632 ms LED_CLK to LED_DATA tCO 1 ns Figure 45 • Basic Serial LED Timing tcyc LED_CLK LED_DATA tPAUSE_port tco Bit 1 Bit 2 Bit X VMDS-10508 VSC8552-02 Datasheet Revision 4.2 Bit 1 102 Electrical Specifications 5.2.9 Enhanced Serial LEDs This section contains the AC specifications for the enhanced serial LEDs. The duty cycle of the LED_PULSE signal is programmable and can be varied between 0.5% and 99.5%. Table 122 • Enhanced Serial LEDs AC Characteristics Parameter Symbol LED_CLK cycle time tCYC Pause between LED_DATA bit sequences tPAUSE Minimum Typical Maximum 256 Unit ns 0.396 24.996 ms LED_CLK to LED_DATA tCO 127 ns LED_CLK to LED_LD tCL 256 ns LED_LD pulse width tLW LED_PULSE cycle time tPULSE 128 ns 199 201 µs Figure 46 • Enhanced Serial LED Timing tcyc tpause LED_CLK tcl tco LED_DATA Bit 1 Bit 2 Bit X Bit 1 Bit 2 t lw LED_LD tpulse LED_PULSE 5.2.10 JTAG Interface This section provides the AC specifications for the JTAG interface. The specifications meet or exceed the requirements of IEEE 1149.1-2001. The JTAG receive signal requirements are requested at the pin of the device. The JTAG_TRST signal is asynchronous to the clock, and does not have a setup or hold time requirement. Table 123 • JTAG Interface AC Specifications Parameter Symbol Minimum TCK frequency ƒ TCK cycle time tC 100 ns TCK high time tW(CH) 40 ns TCK low time tW(CL) 40 ns Setup time to TCK rising tSU 10 ns Hold time from TCK rising tH 10 ns TDO valid after TCK falling tV(C) TDO hold time from TCK falling tH(TDO) TDO disable time(1) tDIS Maximum Unit 10 MHz 28 0 30 Condition ns CL = 10 pF ns CL = 0 pF ns See Figure 48, page 104. VMDS-10508 VSC8552-02 Datasheet Revision 4.2 103 Electrical Specifications Table 123 • JTAG Interface AC Specifications (continued) Parameter Symbol Minimum TRST time low tW(TL) 30 1. Maximum Unit Condition ns The pin begins to float when a 300 mV change from the actual VOH/VOL level occurs. Figure 47 • JTAG Interface Timing Diagram tc TCK t W(CH) tW(CL) TDI TMS t SU tH tV(C) TDO tH(TDO) tDIS See definition nTRST tW(TL) Figure 48 • Test Circuit for TDO Disable Time 3.3 V 500 Ω F rom output under test 5 pF 500 Ω 5.2.11 RGMII, Uncompensated The following illustration shows the test circuit for the RGMII output signals. Figure 49 • Test Circuit for RGMII Output Signals 39 Ω 50 Ω 8 pF Device Under Test Signal Measurement Point VMDS-10508 VSC8552-02 Datasheet Revision 4.2 104 Electrical Specifications The following table lists the characteristics when using the device in RGMII uncompensated mode. For more information about the RGMII uncompensated timing, see Figure 50, page 106. Table 124 • AC Characteristics for RGMII Uncompensated Parameter Symbol Minimum Clock frequency 1000BASE-T duty cycle Typical Maximum 125 25 2.5 tDUTY1000 Unit Condition MHz 1000BASE-T operation 100BASE-TX operation 10BASE-T operation 40 50 60 % 10/100BASE-T tDUTY10/100 duty cycle 35 38 65 % 10BASE-T 10/100BASE-T tDUTY10/100 duty cycle 40 50 60 % 100BASE-TX Data to clock tSKEWT output skew1 (at transmitter) –500 0 500 ps 1.0 1.8 2.6 ns Data to clock output skew1 (at receiver) tSKEWR TX_CLK switching threshold VTHRESH 1.25 V VDD25 = 2.5 Clock/data tR and tF output rise and fall times 750 ps 20% to 80%, 1000BASE-T Clock/data tR and tF output rise and fall times 1000 ps 20% to 80%, 10BASE-T/ 100BASE-TX 1. When operating in uncompensated mode, the PC board design requires a clock to be routed so that an additional trace delay of greater than 1.5 ns is added to the associated clock signal. VMDS-10508 VSC8552-02 Datasheet Revision 4.2 105 Electrical Specifications Figure 50 • RGMII Uncompensated Timing t SKEW T R G MIIn_TXC LK (at Transmitter ) TXD [3:0] R GMIIn_TXD[3:0] TXEN R GMIIn_TXC TL TXD [7:4] TXER R t SKEW R R GMIIn_TXC LK (at R eceiver) V TH R ESH tR , tF R GMIIn_R XC LK (at Transmitter ) tSKEW T 80% 20% R XD [3:0] R G MIIn_R XD [3:0] R XD V R GMIIn_R XC TL R XD[7:4] R XER R tSKEW R t C YC R G MIIn_R XC LK (at R eceiver) n= 0 or 1 , corresponding to PH Y n . 5.2.12 RGMII, Compensated The following table lists the characteristics when using the device in RGMII compensated mode. Table 125 • PHY Input (RGMIIn_TXCLK Delay When Register 18E2.[6:4]=011’b) Parameter Symbol Minimum Typical Data to clock setup (TX_CLK delay = 011’b) tSETUP_R –1.0 ns Clock to data hold (TX_CLK delay = 011’b) tHOLD_R ns 2.8 VMDS-10508 VSC8552-02 Datasheet Revision 4.2 Maximum Unit 106 Electrical Specifications Figure 51 • Compensated Input RGMII Timing RGMIIn_TXCLK t SETUP_R TXD[3:0] RGMIIn_TXD[3:0] TXD[7:4] tHOLD_R TXEN RGMIIn_TXCTL TXERR n= 0 or 1, corresponding to PHY n. Table 126 • PHY Output (RGMIIn_RXCLK Delay When Register 18E2.[3:1]=100’b) Parameter Symbol Minimum Data to clock setup (RX_CLK delay = 100’b) tSETUP_T 1.3 2.0 ns Clock to data hold (RX_CLK delay = 100’b) tHOLD_T 2.0 ns 1.4 Typical Maximum Unit Figure 52 • Compensated Output RGMII Timing RX_CLK delay = 100'b RX_CLK with Internal Delay Added RGMIIn_RXCLK RXD[3:0] RGMIIn_RXD[3:0] tSETUP _T RXD[7:4] tHOLD_T RXEN RGMIIn_RXCTL RXERR n= 0 or 1, corresponding to PHY n . 5.2.13 Serial Management Interface This section contains the AC specifications for the serial management interface (SMI). Table 127 • Serial Management Interface AC Characteristics Parameter Symbol Minimum Typical Maximum Unit MDC frequency(1) fCLK 2.5 12.5 MHz MDC cycle time tCYC 80 400 ns MDC time high tWH 20 50 ns MDC time low tWL 20 50 ns Setup to MDC rising tSU 10 ns Hold from MDC rising tH 10 ns MDC rise time tR 100 tCYC × 10%(1) ns VMDS-10508 VSC8552-02 Datasheet Revision 4.2 Condition MDC = 0: 1 MHz MDC = 1: MHz – fCLK maximum 107 Electrical Specifications Table 127 • Serial Management Interface AC Characteristics (continued) Parameter Symbol Minimum MDC fall time tF MDC to MDIO valid tCO 1. Typical Maximum Unit Condition ns Time-dependant on the value of the external pull-up resistor on the MDIO pin 100 tCYC × 10%(1) 10 300 For fCLK above 1 MHz, the minimum rise time and fall time is in relation to the frequency of the MDC clock period. For example, if fCLK is 2 MHz, the minimum clock rise time and fall time is 50 ns. Figure 53 • Serial Management Interface Timing tWL tWH M DC t C YC tSU tH M DIO (write) Data tCO M DIO (read) 5.2.14 Data Reset Timing This section contains the AC specifications that apply to device reset functionality. The signal applied to the NRESET input must comply with the specifications listed in the following table. Table 128 • Reset Timing Specifications Parameter Symbol Minimum NRESET assertion time after power supplies and clock stabilize tW 2 Recovery time from reset inactive to device fully active tREC NRESET pulse width tW(RL) Wait time between NRESET de-assert tWAIT and access of the SMI interface Maximum Unit ms 105 ms 100 ns 105 ms VMDS-10508 VSC8552-02 Datasheet Revision 4.2 108 Electrical Specifications 5.3 Operating Conditions The following table shows the recommended operating conditions for the VSC8552-02 device. Table 129 • Recommended Operating Conditions Parameter Symbol Minimum Typical Maximum Unit Power supply voltage for VDD1 VDD1 0.95 1.00 1.05 V Power supply voltage for VDD1A VDD1A 0.95 1.00 1.05 V Power supply voltage for VDD25 VDD25 2.38 2.50 2.62 V Power supply voltage for VDD25A 2.50 2.62 V VDD25A 2.38 VSC8552-02 operating temperature(1) T 0 125 °C VSC8552-05 operating temperature(1) T –40 125 °C 1. 5.4 Minimum specification is ambient temperature, and the maximum is junction temperature. For carrier class applications, the maximum operating temperature is 110 °C junction. Stress Ratings This section contains the stress ratings for the VSC8552-02 device. Warning Stresses listed in the following table may be applied to devices one at a time without causing permanent damage. Functionality at or exceeding the values listed is not implied. Exposure to these values for extended periods may affect device reliability. Table 130 • Stress Ratings Parameter Symbol Minimum Maximum Unit Power supply voltage for core supply VVDD1 –0.3 1.10 V Power supply voltage for analog circuits VVDD1A –0.3 1.10 V Power supply voltage for analog circuits VVDD25A –0.3 2.75 V Power supply voltage for digital I/O VVDD25 –0.3 2.75 V 3.3 V Input voltage for GPIO and logic input pins Storage temperature TS –55 125 °C Electrostatic discharge voltage, charged device model VESD_CDM –250 250 V Electrostatic discharge voltage, human body model VESD_HBM See note(1) 1. V This device has completed all required testing as specified in the JEDEC standard JESD22-A114, Electrostatic Discharge (ESD) Sensitivity Testing Human Body Model (HBM), and complies with a Class 2 rating. The definition of Class 2 is any part that passes an ESD pulse of 2000 V, but fails an ESD pulse of 4000 V. Warning This device can be damaged by electrostatic discharge (ESD) voltage. Microsemi recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures may adversely affect reliability of the device. VMDS-10508 VSC8552-02 Datasheet Revision 4.2 109 Pin Descriptions 6 Pin Descriptions The VSC8552-02 device has 256 pins, which are described in this section. The pin information is also provided as an attached Microsoft Excel file so that you can copy it electronically. In Acrobat, double-click the attachment icon. 6.1 Pin Identifications This section contains the pin descriptions for the VSC8552-02 device. The following table provides notations for definitions of the various pin types. Table 131 • Pin Type Symbol Definitions Symbol Pin Type 3V 6.2 Description 3.3 V-tolerant pin. ABIAS Analog bias Analog bias pin. ADIFF Analog differential Analog differential signal pair. I Input Input without on-chip pull-up or pull-down resistor. I/O Bidirectional Bidirectional input or output signal. NC No connect No connect pins must be left floating. O Output Output signal. OD Open drain Open drain output. OS Open source Open source output. PD Pull-down On-chip pull-down resistor to VSS. PU Pull-up On-chip pull-up resistor to VDD_IO. ST Schmitt-trigger Input has Schmitt-trigger circuitry. Pin Diagram The following illustrations show the pin diagram for the VSC8552-02 device. For clarity, the device is shown in two halves, the top left and top right. VMDS-10508 VSC8552-02 Datasheet Revision 4.2 110 Pin Descriptions Figure 54 • Pin Diagram, Top Left 1 2 3 4 5 6 7 8 A NC _1 RESERVED_54 RESERVED_56 RESERVED_58 RESERVED_60 RESERVED_62 RESERVED_64 RESERVED_66 B VSS_1 RESERVED_55 RESERVED_57 RESERVED_59 RESERVED_61 RESERVED_63 RESERVED_65 RESERVED_67 C REFC LK_N VDD25A_1 THERMDA VDD25A_2 VSS_3 VDD25A_3 VDD1A_1 VDD1A_2 D REFC LK_P THERMDC_VSS REF_FILT_A R EF_R EXT_A VSS_6 VSS_7 VSS_8 VSS_9 E REFCLK_SEL2 TMS TRST VDD25A_6 VDD1_1 VSS_14 VSS_15 VSS_16 F TDO TDI TC K VSS_20 VDD1_3 VSS_21 VSS_22 VSS_23 G LED0_0 LED1_0 LED2_0 LED3_0 VDD1_5 VSS_27 VSS_28 VSS_29 H LED0_1 LED1_1 LED2_1 LED3_1 VDD1_7 VSS_33 VSS_34 VSS_35 J RGMII1_RXD0 RGMII1_RXD1 RGMII1_RXD2 RGMII1_RXD3 VDD1_9 VSS_39 VSS_40 VSS_41 K RGMII1_TXCLK RGMII1_TXCTL RGMII1_RXCTL RGMII1_RXCLK VDD1_11 VSS_45 VSS_46 VSS_47 L RGMII1_TXD0 RESERVED_73 COMA_MODE R ESER VED_3 VDD1_13 VSS_51 VSS_52 VSS_53 M RGMII1_TXD1 MDINT NRESET VDD25_2 VDD1_15 VSS_57 VSS_58 VSS_59 N RGMII1_TXD2 MDIO RESERVED_71 RESERVED_72 VDD1_17 VSS_63 VSS_64 VSS_65 P RGMII1_TXD3 MDC VDD25_4 VDD1A_5 VDD1A_6 VDD1A_7 R VSS_69 RESERVED_22 RESERVED_24 RESERVED_26 RESERVED_28 RESERVED_30 RESERVED_32 RESERVED_34 T NC _3 RESERVED_23 RESERVED_25 RESERVED_27 RESERVED_29 RESERVED_31 RESERVED_33 RESERVED_35 R ESER VED_4 VDD25A_8 VMDS-10508 VSC8552-02 Datasheet Revision 4.2 111 Pin Descriptions Figure 55 • Pin Diagram, Top Right 9 10 11 12 13 14 15 16 RESERVED_68 TXVPA_1 TXVPB_1 TXVPC _1 TXVPD_1 TXVPA_0 TXVPB_0 NC _2 A RESERVED_69 TXVNA_1 TXVNB_1 TXVNC _1 TXVND_1 TXVNA_0 TXVNB_0 VSS_2 B VSS_4 VDD1A_4 VDD25A_5 TXVNC _0 TXVPC _0 C VDD1A_3 R ESER VED_1 VDD25A_4 VSS_10 VSS_11 VSS_12 VSS_13 RESERVED_2 RGMII0_TXD3 TXVND_0 TXVPD_0 D VSS_17 VSS_18 VSS_19 VDD1_2 VDD25A_7 RGMII0_TXD2 CLK_SQUELCH_IN RESERVED_70 E VSS_24 VSS_25 VSS_26 VDD1_4 RGMII0_TXD1 PHYADD4 RGMII0_TXD0 R C VR DCLK1 F VSS_30 VSS_31 VSS_32 VDD1_6 PHYADD2 PHYADD3 RGMII0_TXCLK R C VR DCLK2 G VSS_36 VSS_37 VSS_38 VDD1_8 VDD25_1 GPIO13 RGMII0_TXCTL RGMII0_RXCLK H VSS_42 VSS_43 VSS_44 VDD1_10 RGMII0_RXCTL GPIO12 RESERVED_18 RESERVED_19 J VSS_48 VSS_49 VSS_50 VDD1_12 GPIO8/I2C_SDA GPIO9/FASTLINK-FAIL GPIO10 GPIO11 K VSS_54 VSS_55 VSS_56 VDD1_14 GPIO4/I2C_SCL_0 GPIO5/I2C_SCL_1 RGMII0_RXD0 RGMII0_RXD1 L VSS_60 VSS_61 VSS_62 VDD1_16 VDD25_3 GPIO1/SIGDET1 RGMII0_RXD2 RGMII0_RXD3 M VSS_66 VSS_67 VSS_68 VDD1_18 SerDes_Rext_1 GPIO0/SIGDET0 TDP_0 TDN_0 N VDD1A_8 VDD1A_9 VDD1A_10 SerDes_Rext_0 RDP_0 RDN_0 P RESERVED_36 FIBROP_1 FIBRIP_1 RDP_1 TDP_1 FIBROP_0 FIBRIP_0 VSS_70 R RESERVED_37 FIBRON_1 FIBRIN_1 RDN_1 TDN_1 FIBRON_0 FIBRIN_0 NC _4 T 6.3 VDD25A_9 VDD25A_10 Pins by Function This section contains the functional pin descriptions for the VSC8552-02 device. VMDS-10508 VSC8552-02 Datasheet Revision 4.2 112 Pin Descriptions 6.3.1 GPIO and SIGDET The following table lists the GPIO and SIGDET pins. Table 132 • GPIO and SIGDET Pins 6.3.2 Name Pin Type Description GPIO0/SIGDET0 GPIO1/SIGDET1 GPIO4/I2C_SCL_0 GPIO5/I2C_SCL_1 GPIO8/I2C_SDA GPIO9/FASTLINK-FAIL GPIO10 GPIO11 GPIO12 GPIO13 N14 M14 L13 L14 K13 K14 K15 K16 J14 H14 I/O, PU, 3 V General purpose input/output (GPIO). The multipurpose SIGDET pins, two-wire serial controller pins, and fast link fail pin can be configured to serve as GPIOs. JTAG The following table lists the JTAG test pins. Table 133 • JTAG Pins 6.3.3 Name Pin Type Description TCK F3 I, PU, ST, 3 V JTAG test clock input. TDI F2 I, PU, ST, 3 V JTAG test serial data input. TDO F1 O JTAG test serial data output. TMS E2 I, PU, ST, 3 V JTAG test mode select. TRST E3 I, PU, ST, 3 V JTAG reset. Important When JTAG is not in use, this pin must be tied to ground with a pull-down resistor for normal operation. Miscellaneous The following table lists the miscellaneous pins. Table 134 • Miscellaneous Pins Name Pin Type Description CLK_SQUELCH_IN E15 I, PU, 3V Input control to squelch recovered clock. COMA_MODE L3 I, PU, 3V When this pin is asserted high, all PHYs are held in a powered down state. When de-asserted low, all PHYs are powered up and resume normal operation. This signal is also used to synchronize the operation of multiple chips on the same PCB to provide visual synchronization for LEDs driven by separate chips.(1) LED0_[0:1] LED1_[0:1] LED2_[0:1] LED3_[0:1] G1, H1 G2, H2 G3, H3, G4, H4, O LED direct-drive outputs. All LEDs pins are active-low. A serial LED stream can also be implemented. See LED Mode Select, page 60. Note: LEDbit_port, where port = PHY port number and bit = the particular LED for the port. VMDS-10508 VSC8552-02 Datasheet Revision 4.2 113 Pin Descriptions Table 134 • Miscellaneous Pins (continued) Name Pin Type Description NC_1 NC_2 NC_3 NC_4 A1 A16 T1 T16 NC No connect. PHYADD2 PHYADD3 PHYADD4 G13 G14 F14 I, PD, 3V Device SMI address bits 4:2. RCVRDCLK1 RCVRDCLK2 F16 G16 O Clock output can be enabled or disabled and also output a clock frequency of 125 MHz or 25 MHz based on the selected active recovered media programmed for this pin. This pin is not active when NRESET is asserted. When disabled, the pin is held low. REF_FILT_A D3 ABIAS Reference filter connects to an external 1 µF capacitor to analog ground. REF_REXT_A D4 ABIAS Reference external connects to an external 2 kΩ (1%) resistor to analog ground. REFCLK_N REFCLK_P C1 D1 I, ADIFF 125 MHz or 25 MHz reference clock input pair. Must be capacitively coupled and LVDS compatible. REFCLK_SEL2 E1 I, PU, 3V Selects the reference clock speed: 0: 25 MHz (VSS) 1: 125 MHz (2.5 V) Use 125 MHz for typical applications. RESERVED_[1:4] C10, D13, L4, P4 NC Leave these pins unconnected (floating). NC Leave these pins unconnected (floating). RESERVED_[22:37] R2, T2, R3, T3, NC R4, T4, R5, T5, R6, T6, R7, T7, R8, T8, R9, T9 Leave these pins unconnected (floating). RESERVED_[54:69] A2, B2, A3, B3, A4, B4, A5, B5, A6, B6, A7, B7, A8, B8, A9, B9 NC Leave these pins unconnected (floating). RESERVED_[18:19] J15, J16 RESERVED_[70:73] E16, N3, N4, L2 NC Leave these pins unconnected (floating). THERMDA C3 A Thermal diode anode. THERMDC_VSS D2 A Thermal diode cathode connected to device ground. Temperature sensor must be chosen accordingly. 1. 6.3.4 For more information, see Initialization, page 43. For a typical bring-up example, see Configuration, page 42. Power Supply The following table lists the power supply pins and associated functional pins. All power supply pins must be connected to their respective voltage input, even if certain functions are not used for a specific VMDS-10508 VSC8552-02 Datasheet Revision 4.2 114 Pin Descriptions application. No power supply sequencing is required. However, clock and power must be stable before releasing Reset. Table 135 • Power Supply Pins 6.3.4.1 Name Pin Type Description VDD1_[1:18] E5, E12, F5, F12, G5, G12, H5, H12, J5, J12, K5, K12, L5, L12, M5, M12, N5, N12 1.0 V 1.0 V internal digital logic. VDD1A_[1:10] C7, C8, C9, C13, P6, P7, P8, 1.0 V P9, P10, P11 1.0 V analog power requiring additional PCB power supply filtering.Associated with the QSGMII/SGMII MAC receiver output pins. VDD25_[1:4] H13, M4, M13, P3 2.5 V 2.5 V general digital power supply. Associated with the LED, GPIO, JTAG, twisted pair interface, reference filter, reference external supply connect, and recovered clock pins. VDD25A_[1:10] C2, C4, C6, C11, C14, E4, E13, P5, P12, P13 2.5 V 2.5 V general analog power supply. VSS_[1:4] VSS_[6:70] B1, B16, C5, C12 0V D5, D6, D7, D8, D9, D10, D11, D12, E6, E7, E8, E9, E10, E11, F4, F6, F7, F8, F9, F10, F11, G6, G7, G8, G9, G10, G11, H6, H7, H8, H9, H10, H11, J6, J7, J8, J9, J10, J11, K6, K7, K8, K9, K10, K11, L6, L7, L8, L9, L10, L11, M6, M7, M8, M9, M10, M11, N6, N7, N8, N9, N10, N11, R1, R16 General device ground. RGMII Interface The following table lists the RGMII interface pins. Note: Unused RGMII port pins cannot be used as GPIOs. Table 136 • RGMII Interface Pins Name Pin Type Description RGMII0_RXCLK H16 O Receive clock. Receive data is sourced from the PHY synchronously on the rising edge of RXCLK and is the recovered clock from the media. RGMII0_RXCTL J13 O Multiplexed receive data valid, receive error. This output is sampled by the MAC on opposite edges of RXCLK to indicate two receive conditions from the PHY: 1. On the rising edge of RXCLK, this output serves as RXDV and signals valid data is available on the RXD input data bus. 2. On the falling edge of RXCLK, this output signals a receive error from the PHY, based on a logical derivative of RXDV and RXER, as stated by the RGMII specification. VMDS-10508 VSC8552-02 Datasheet Revision 4.2 115 Pin Descriptions Table 136 • RGMII Interface Pins (continued) Name Pin Type Description RGMII0_RXD0 RGMII0_RXD1 RGMII0_RXD2 RGMII0_RXD3 L15 L16 M15 M16 O Multiplexed receive data. Bits 3:0 are synchronously output on the rising edge of RXCLK and bits 7:4 on the falling edge of RXCLK. RGMII0_TXCLK G15 I Transmit clock. This clock is 2.5 MHz for 10 Mbps mode, 25 MHz for 100 Mbps mode, and 125 MHz for 1000 Mbps mode. If left unconnected, these pins require a pull-down resistor to ground. RGMII0_TXCTL H15 I Multiplexed transmit enable, transmit error. This input is sampled by the PHY on opposite edges of TXCLK to indicate two transmit conditions of the MAC: 1. On the rising edge of TXCLK, this input serves as TXEN, indicating valid data is available on the TXD input data bus. 2. On the falling edge of TXCLK, this input signals a transmit error from the MAC, based on a logical derivative of TXEN and TXER, as stated by the RGMII specification. RGMII0_TXD0 RGMII0_TXD1 RGMII0_TXD2 RGMII0_TXD3 F15 F13 E14 D14 I Multiplexed transmit data. Bits 3:0 are synchronously output on the rising edge of TXCLK and bits 7:4 on the falling edge of TXCLK. RGMII1_RXCLK K4 O Receive clock. Receive data is sourced from the PHY synchronously on the rising edge of RXCLK and is the recovered clock from the media. RGMII1_RXCTL K3 O Multiplexed receive data valid, receive error. This output is sampled by the MAC on opposite edges of RXCLK to indicate two receive conditions from the PHY: 1. On the rising edge of RXCLK, this output serves as RXDV and signals valid data is available on the RXD input data bus. 2. On the falling edge of RXCLK, this output signals a receive error from the PHY, based on a logical derivative of RXDV and RXER, as stated by the RGMII specification. RGMII1_RXD0 RGMII1_RXD1 RGMII1_RXD2 RGMII1_RXD3 J1 J2 J3 J4 O Multiplexed receive data. Bits 3:0 are synchronously output on the rising edge of RXCLK and bits 7:4 on the falling edge of RXCLK. RGMII1_TXCLK K1 I Transmit clock. This clock is 2.5 MHz for 10 Mbps mode, 25 MHz for 100 Mbps mode, and 125 MHz for 1000 Mbps mode. If left unconnected, these pins require a pull-down resistor to ground. VMDS-10508 VSC8552-02 Datasheet Revision 4.2 116 Pin Descriptions Table 136 • RGMII Interface Pins (continued) Name Pin Type Description RGMII1_TXCTL K2 I Multiplexed transmit enable, transmit error. This input is sampled by the PHY on opposite edges of TXCLK to indicate two transmit conditions of the MAC: 1. On the rising edge of TXCLK, this input serves as TXEN, indicating valid data is available on the TXD input data bus. 2. On the falling edge of TXCLK, this input signals a transmit error from the MAC, based on a logical derivative of TXEN and TXER, as stated by the RGMII specification. L1 M1 N1 P1 RGMII1_TXD0 RGMII1_TXD1 RGMII1_TXD2 RGMII1_TXD3 6.3.5 I Multiplexed transmit data. Bits 3:0 are synchronously output on the rising edge of TXCLK and bits 7:4 on the falling edge of TXCLK. SGMII/SerDes/QSGMII MAC Interface The following table lists the SerDes MAC interface pins. Table 137 • SerDes MAC Interface Pins 6.3.6 Name Pin Type Description RDN_0 RDP_0 P16 P15 O, ADIFF PHY0 QSGMII/SGMII/SerDes MAC receiver output pair. RDN_1 RDP_1 T12 R12 O, ADIFF SGMII/SerDes MAC receiver output pair. SerDes_Rext_0 P14 ABIAS SerDes bias pins. Connect to a 620 Ω 1% resistor between SerDes_Rext_0 and SerDes_Rext_1. SerDes_Rext_1 N13 ABIAS SerDes bias pins. Connect to a 620 Ω 1% resistor between SerDes_Rext_0 and SerDes_Rext_1. TDN_0 TDP_0 N16 N15 I, ADIFF PHY0 QSGMII/SGMII/SerDes MAC transmitter input pair. TDN_1 TDP_1 T13 R13 I, ADIFF SGMII/SerDes MAC transmitter input pair. SerDes Media Interface The following table lists the SerDes media interface pins. Table 138 • SerDes Media Interface Pins Name Pin Type Description FIBRIN_0 FIBRIN_1 T15 I, ADIFF T11 SerDes media receiver input pair. FIBRIP_0 FIBRIP_1 R15 I, ADIFF R11 SerDes media receiver input pair. FIBRON_0 T14 O, ADIFF SerDes media transmitter output pair. FIBRON_1 T10 FIBROP_0 R14 O, ADIFF SerDes media transmitter output pair. FIBROP_1 R10 VMDS-10508 VSC8552-02 Datasheet Revision 4.2 117 Pin Descriptions 6.3.7 Serial Management Interface The following table lists the serial management interface (SMI) pins. The SMI pins are referenced to VDD25 and can be set to a 2.5 V power supply. Table 139 • SMI Pins Name Pin Type Description MDC P2 I, PD, 3 V Management data clock. A 0 MHz to 12.5 MHz reference input is used to clock serial MDIO data into and out of the PHY. MDINT M2 I/O, OS, OD Management interrupt signal. Upon reset the device will configure these pins as active-low (open drain) or active-high (open source) based on the polarity of an external 10 kΩ resistor connection. These pins can be tied together in a wired-OR configuration with only a single pull-up or pull-down resistor. MDIO N2 I/O, OD Management data input/output pin. Serial data is written or read from this pin bidirectionally between the PHY and Station Manager, synchronously on the positive edge of MDC. One external pull-up resistor is required at the Station Manager, and its value depends on the MDC clock frequency and the total sum of the capacitive loads from the MDIO pins. NRESET M3 6.3.8 I, PD, ST, 3 V Device reset. Active low input that powers down the device and sets all register bits to their default state. Twisted Pair Interface The following table lists the twisted pair interface pins. Table 140 • Twisted Pair Interface Pins Name Pin Type Description TXVNA_0 TXVNA_1 B14 B10 ADIFF TX/RX channel A negative signal TXVNB_0 TXVNB_1 B15 B11 ADIFF TX/RX channel B negative signal TXVNC_0 TXVNC_1 C15 B12 ADIFF TX/RX channel C negative signal TXVND_0 TXVND_1 D15 B13 ADIFF TX/RX channel D negative signal TXVPA_0 TXVPA_1 A14 A10 ADIFF TX/RX channel A positive signal TXVPB_0 TXVPB_1 A15 A11 ADIFF TX/RX channel B positive signal TXVPC_0 TXVPC_1 C16 A12 ADIFF TX/RX channel C positive signal TXVPD_0 TXVPD_1 D16 A13 ADIFF TX/RX channel D positive signal VMDS-10508 VSC8552-02 Datasheet Revision 4.2 118 Package Information 7 Package Information VSC8552XKS-02 and VSC8552XKS-05 are packaged in a lead(Pb)-free, 256-pin, plastic ball grid array (BGA) with a 17 mm × 17 mm body size, 1 mm pin pitch, and 1.8 mm maximum height. Lead(Pb)-free products from Microsemi comply with the temperatures and profiles defined in the joint IPC and JEDEC standard IPC/JEDEC J-STD-020. For more information, see the IPC and JEDEC standard. This section provides the package drawing, thermal specifications, and moisture sensitivity rating for the VSC8552-02 device. 7.1 Package Drawing The following illustration shows the package drawing for the VSC8552-02 device. The drawing contains the top view, bottom view, side view, dimensions, tolerances, and notes. VMDS-10508 VSC8552-02 Datasheet Revision 4.2 119 Package Information Figure 56 • Package Drawing Top View Bottom View 0.20 (4×) Pin A1 corner X 17.00 Pin A1 corner 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 A B C D E F G H J K L M N P R T 1.00 15.00 17.00 1.00 Y 15.00 0.31–0.43 Side View 0.25 Z 1.8 maximum 4 Z Seating plane 5 0.20 Z Ø 0.45–0.64 Ø 0.25 M Ø 0.10 M Z X Y Z Notes 1. All dimensions and tolerances are in millimeters (mm). 2. Ball diameter is 0.50 mm. 3. Radial true position is represented by typical values. 4. Primary datum Z and seating plane are defined by the spherical crowns of the solder balls. 5. Dimension is measured at the maximum solder ball diameter, parallel to primary datum Z. 7.2 Thermal Specifications Thermal specifications for this device are based on the JEDEC JESD51 family of documents. These documents are available on the JEDEC Web site at www.jedec.org. The thermal specifications are modeled using a four-layer test board with two signal layers, a power plane, and a ground plane (2s2p VMDS-10508 VSC8552-02 Datasheet Revision 4.2 120 Package Information PCB). For more information about the thermal measurement method used for this device, see the JESD51-1 standard. Table 141 • Thermal Resistances Symbol °C/W Parameter θJCtop 5.9 Die junction to package case top θJB 12.7 Die junction to printed circuit board θJA 22 Die junction to ambient θJMA at 1 m/s 18.5 Die junction to moving air measured at an air speed of 1 m/s θJMA at 2 m/s 16.3 Die junction to moving air measured at an air speed of 2 m/s To achieve results similar to the modeled thermal measurements, the guidelines for board design described in the JESD51 family of publications must be applied. For information about applications using BGA packages, see the following: • • • • 7.3 JESD51-2A, Integrated Circuits Thermal Test Method Environmental Conditions, Natural Convection (Still Air) JESD51-6, Integrated Circuit Thermal Test Method Environmental Conditions, Forced Convection (Moving Air) JESD51-8, Integrated Circuit Thermal Test Method Environmental Conditions, Junction-to-Board JESD51-9, Test Boards for Area Array Surface Mount Package Thermal Measurements Moisture Sensitivity This device is rated moisture sensitivity level 4 as specified in the joint IPC and JEDEC standard IPC/JEDEC J-STD-020. For more information, see the IPC and JEDEC standard. VMDS-10508 VSC8552-02 Datasheet Revision 4.2 121 Design Considerations 8 Design Considerations This section provides information about design considerations for the VSC8552-02 device. 8.1 Link status LED remains on while COMA_MODE pin is asserted high When the COMA_MODE is asserted high, the link status LED may not deactivate unless the media cable is disconnected from the device. While using COMA_MODE, link status should be verified using status registers rather than LED indicators. 8.2 LED pulse stretch enable turns off LED pins Enabling the pulse stretch function for LED0 or LED1 by setting register 30, bits 5:6 shuts off those LED pins. Use the default blink function setting of LED0 and LED1 rather than pulse stretching. For more information, see LED Behavior, page 61. 8.3 AMS and 100BASE-FX When the PHY operating mode (set in register 23) is AMS and the current active media is 100BASE-FX, register 0 bit 12 will be 0. This would normally indicate that auto-negotiation is disabled and the PHY is in forced mode. But in this mode, it has other meanings. The workaround is to ensure that bit 12 is always written as 1 when doing writes or updates to register 0 in AMS mode. 8.4 10BASE-T signal amplitude 10BASE-T signal amplitude can be lower than the minimum specified in IEEE 802.3 paragraph 14.3.1.2.1 (2.2 V) at low supply voltages. This issue is not estimated to present any system level impact. Performance is not impaired with cables up to 130 m with various link partners. 8.5 10BASE-T link recovery failures If the link disconnects when traffic is flowing while the device operates in a 10BASE-T mode, the PHY may not re-link. There is a software workaround for this issue in which the device's internal microcontroller monitors link transitions in 10BASE-T mode and forces a soft power-down/power-up procedure to prevent a re-link failure. A side effect of this software workaround is that non-sticky registers will be cleared (for example, the copper media link disconnect counter in register 21, see Error Counter 3, page 55). 8.6 SNR degradation and link drops The link may drop after approximately 100 master/slave relationship swaps with the ring resiliency feature when using Category 5 (Cat5) cables that are longer than 75 m. The workaround is to use a combination of an initialization script and a procedure change. Contact Microsemi for the workaround solution if the ring resiliency feature is being enabled. 8.7 Clause 45 register 3.22 The clause 45, register 3.22 is cleared upon read only when the extended page access register (register 31) is set to 0. VMDS-10508 VSC8552-02 Datasheet Revision 4.2 122 Design Considerations This register cannot be read when the page access register is set to a value other than 0. The workaround is to set extended page access register to 0 before accessing clause 45, register 3.22. 8.8 Clause 45 register 3.1 Clause 45, register 3.1, Rx and Tx LPI received bits are cleared upon read only when the extended page access register (register 31) is set to 0. This has a minor implication for software that needs to ensure that the extended page access register is set to 0 before reading clause 45, register 3.1. The workaround is to set extended page access register to 0 before accessing clause 45, register 3.1. 8.9 Clause 45 register address post-increment Clause 45 register address post-increment only works when reading registers and only when extended page access register (register 31) is set to 0. The workaround is to access the registers individually. 8.10 Fast link failure indication The fast link failure indication for all the ports is enabled using port 0, register 19E.4. The workaround is to set register 19E.4 = 1 in PHY 0 to enable Fast Link Fail indication. 8.11 Near-end loopback with AMS enabled Near-end loopback does not work when AMS is enabled. Near-end loopback is controlled by setting bit 14 of register 0. The workaround is to disable AMS when enabling loopback. This is a debug feature and does not have any real life implications. 8.12 Carrier detect assertion Carrier detect assertion is set to false incorrectly when 9 out of 10 bits in the K28.1 word are in error. No real life implication is expected, because the event that can trigger this error is extremely unlikely. If it does occur, the link may drop momentarily and come back up. 8.13 Link status not correct in register 24E3.2 for 100BASEFX operation The link status in register 24E3.2 only reflects the status of 1000BASE-X links. It does not reflect the status of 100BASE-FX links. The workaround is to check register 28.4:3 for media operating mode (10 for fiber), 28.4:3 for speed status (100 for 100 Mbps), and then check 16.12 for current link status. 8.14 Register 28.14 does not reflect autonegotiation disabled in 100BASE-FX mode Register 28.14 does not reflect autonegotiation status in 100BASE-FX mode. It works correctly in all copper and 1000BASE-X media modes. The workaround is to use register 0.12 for autonegotiation status in 100BASE-FX mode when AMS is disabled. For more information about limitations when AMS is enabled, see AMS and 100BASE-FX, page 122. VMDS-10508 VSC8552-02 Datasheet Revision 4.2 123 Design Considerations 8.15 Near-end loopback non-functional in protocol transfer mode Near-end loopback does not work correctly when the device is configured in protocol transfer mode. This is a debug feature and does not have any effect on the normal operation of the device. 8.16 Fiber-media CRC counters non-functional in protocol transfer mode at 10 Mbps and 100 Mbps Packets received on the media SerDes interface will not be counted correctly in registers 28E3 and 29E3 when the device is configured in protocol transfer mode and operating at 10 Mbps or 100 Mbps speeds. These counters are used for debugging and there is no effect on the normal operation of the device. 8.17 Fiber-media recovered clock does not squelch based on link status To squelch the clock in fiber media mode, code sync status is used instead of link status. This causes the clock to not be squelched if the device is configured in 1000BASE-X mode with autonegotiation enabled when the transmit fiber is unplugged. There is a software workaround for this issue where the device's internal microcontroller monitors link status and forces the clock off when no link is present. 8.18 1000BASE-X parallel detect mode with Clause 37 autonegotiation enabled When connected to a forced-mode link partner and attempting autonegotiation, the PHY in 1000BASEX parallel detect mode requires a minimum 250 ms IDLE stream in order to establish a link. If the PHY port is programmed with 1000BASE-X parallel detect-enabled (MAC-side register 16E3 bit 13, or media-side register 23E3 bit 13), then a forced-mode link partner sending traffic with an inter-packet gap less than 250 ms will not allow the local device’s PCS to transition from a link-down to link-up state. 8.19 Anomalous PCS error indications in Energy Efficient Ethernet mode When a port is processing traffic with Energy Efficient Ethernet enabled on the link, certain PCS errors (such as false carriers, spurious start-of-stream detection, and idle errors) and EEE wake errors may occur. There is no effect on traffic bit error rate for cable lengths up to 75 meters, and minor packet loss may occur on links longer than 75 meters. Regardless of cable length, some error indications should not be used while EEE is enabled. These error indications include false carrier interrupts (Interrupt Status register 26 bit 3), receive error interrupts (Interrupt Status register 26 bit 0), and EEE wake error interrupts. Contact Microsemi for a script that needs to be applied during system initialization if EEE will be enabled. 8.20 Long link-up times while in forced 100BASE-TX mode of operation While in forced 100BASE-TX operation and attempting to link up, the device may experience abnormally long link-up times. This issue can only occur if the Unified API is not used with the device. In those circumstances, the workaround for this issue is to clear all speed advertisements in the autonegotiation advertisement registers (register 4, bits 9:5 and register 9, bits 9:8), then toggle the auto-negotiation enable bit of the mode control register (register 0, bit 12) for a port upon detecting its link is down. Any advertisements temporarily cleared can then be restored once register 0, bit 12 is cleared. VMDS-10508 VSC8552-02 Datasheet Revision 4.2 124 Design Considerations Contact Microsemi for the latest code sequence included in the Unified API. 8.21 Station managers cannot use MDIO address offsets 0x2 and 0x3 with the PHY In addition to responding to the two lowest MDIO addresses that can be resolved with device serial management interface address bits 4:2, the device will unexpectedly respond to offsets that have bit 1 set (for a detailed addressing diagram, see SMI Frames, page 24). However, PHY2 and PHY3 are unusable targets on this device, so their corresponding MDIO addresses must not be used by the SMI station manager that controls this device. It is essential to avoid assigning addresses to other devices on the bus that would overlap the 0x2 and 0x3 offsets. The workaround for this issue is to ensure the station manager connected to this device avoids using the two MDIO addresses immediately following the PHY1 target. VMDS-10508 VSC8552-02 Datasheet Revision 4.2 125 Ordering Information 9 Ordering Information The VSC8552 device is offered with two operating temperature ranges. The range for VSC8552-02 is 0 °C ambient to 125 °C junction, and the range for VSC8552-05 is -40 °C ambient to 125 °C junction. VSC8552XKS-02 and VSC8552XKS-05 are packaged in a lead(Pb)-free, 256-pin, plastic ball grid array (BGA) with a 17 mm × 17 mm body size, 1 mm pin pitch, and 1.8 mm maximum height. Lead(Pb)-free products from Microsemi comply with the temperatures and profiles defined in the joint IPC and JEDEC standard IPC/JEDEC J-STD-020. For more information, see the IPC and JEDEC standard. The following table lists the ordering information for the VSC8552-02 device. Table 142 • Ordering Information Part Order Number Description VSC8552XKS-02 Lead-free, 256-pin, plastic BGA with a 17 mm × 17 mm body size, 1 mm pin pitch, and 1.8 mm maximum height. The operating temperature is 0 °C ambient to 125 °C junction1. VSC8552XKS-05 Lead-free, 256-pin, plastic BGA with a 17 mm × 17 mm body size, 1 mm pin pitch, and 1.8 mm maximum height. The operating temperature is –40 °C ambient to 125 °C junction1. 1. For carrier class applications, the maximum operating temperature is 110 °C junction. VMDS-10508 VSC8552-02 Datasheet Revision 4.2 126