VSC8572XKS-02

VSC8572-02 Datasheet Dual-Port 10/100/1000BASE-T PHY with Synchronous Ethernet, IEEE 1588, and QSGMII/SGMII/RGMII MAC Microsemi Headquarters One Enterprise, Aliso Viejo, CA 92656 USA Within the USA: +1 (800) 713-4113 Outside the USA: +1 (949) 380-6100 Sales: +1 (949) 380-6136 Fax: +1 (949) 215-4996 Email: sales.support@microsemi.com www.microsemi.com ©2018 Microsemi, a wholly owned subsidiary of Microchip Technology Inc. All rights reserved. Microsemi and the Microsemi logo are registered trademarks of Microsemi Corporation. All other trademarks and service marks are the property of their respective owners. Microsemi makes no warranty, representation, or guarantee regarding the information contained herein or the suitability of its products and services for any particular purpose, nor does Microsemi assume any liability whatsoever arising out of the application or use of any product or circuit. The products sold hereunder and any other products sold by Microsemi have been subject to limited testing and should not be used in conjunction with mission-critical equipment or applications. Any performance specifications are believed to be reliable but are not verified, and Buyer must conduct and complete all performance and other testing of the products, alone and together with, or installed in, any end-products. Buyer shall not rely on any data and performance specifications or parameters provided by Microsemi. It is the Buyer’s responsibility to independently determine suitability of any products and to test and verify the same. The information provided by Microsemi hereunder is provided “as is, where is” and with all faults, and the entire risk associated with such information is entirely with the Buyer. Microsemi does not grant, explicitly or implicitly, to any party any patent rights, licenses, or any other IP rights, whether with regard to such information itself or anything described by such information. Information provided in this document is proprietary to Microsemi, and Microsemi reserves the right to make any changes to the information in this document or to any products and services at any time without notice. About Microsemi Microsemi, a wholly owned subsidiary of Microchip Technology Inc. (Nasdaq: MCHP), offers a comprehensive portfolio of semiconductor and system solutions for aerospace & defense, communications, data center and industrial markets. Products include high-performance and radiation-hardened analog mixed-signal integrated circuits, FPGAs, SoCs and ASICs; power management products; timing and synchronization devices and precise time solutions, setting the world's standard for time; voice processing devices; RF solutions; discrete components; enterprise storage and communication solutions, security technologies and scalable anti-tamper products; Ethernet solutions; Power-over-Ethernet ICs and midspans; as well as custom design capabilities and services. Learn more at www.microsemi.com. VMDS-10509. 4.2 4/19 Contents 1 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.1 1.2 1.3 1.4 Revision 4.2 Revision 4.1 Revision 4.0 Revision 2.0 ....................................................................... ....................................................................... ....................................................................... ....................................................................... 1 1 2 2 2 Product Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2.1 2.2 Key Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.1.1 Low Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.1.2 Advanced Carrier Ethernet Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.1.3 Wide Range of Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.1.4 Flexibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 4 4 4 4 5 3 Functional Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3.1.1 QSGMII/SGMII MAC-to-1000BASE-X Link Partner . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3.1.2 QSGMII/SGMII MAC-to-100BASE-FX Link Partner . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3.1.3 QSGMII/SGMII MAC-to-AMS and 1000BASE-X Media SerDes . . . . . . . . . . . . . . . . . . . . . . . . 8 3.1.4 QSGMII/SGMII MAC-to-AMS and 100BASE-FX Media SerDes . . . . . . . . . . . . . . . . . . . . . . . . 9 3.1.5 QSGMII/SGMII MAC-to-AMS and Protocol Transfer Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.1.6 QSGMII/SGMII MAC-to-Cat5 Link Partner . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.1.7 QSGMII/SGMII MAC-to-Protocol Transfer Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.1.8 1000BASE-X MAC-to-Cat5 Link Partner . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 RGMII MAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 SerDes MAC Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.3.1 SerDes MAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.3.2 SGMII MAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.3.3 QSGMII MAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 SerDes Media Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.4.1 QSGMII/RGMII/SGMII to 1000BASE-X . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.4.2 QSGMII/RGMII/SGMII to 100BASE-FX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.4.3 QSGMII to SGMII Protocol Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.4.4 Unidirectional Transport for Fiber Media . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 PHY Addressing and Port Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.5.1 PHY Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.5.2 SerDes Port Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Cat5 Twisted Pair Media Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.6.1 Voltage Mode Line Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.6.2 Cat5 Autonegotiation and Parallel Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.6.3 Automatic Crossover and Polarity Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.6.4 Manual HP Auto-MDIX Setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.6.5 Link Speed Downshift . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.6.6 Energy Efficient Ethernet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.6.7 Ring Resiliency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Automatic Media Sense Interface Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Reference Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.8.1 Configuring the Reference Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.8.2 Single-Ended REFCLK Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.8.3 Differential REFCLK Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 1588 Reference Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 VMDS-10509 VSC8572-02 Datasheet Revision 4.2 iii 3.10 3.11 3.12 3.13 3.14 3.15 3.16 3.17 3.18 3.19 3.20 Ethernet Inline Powered Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IEEE 802.3af PoE Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ActiPHY Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.12.1 Low Power State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.12.2 Link Partner Wake-Up State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.12.3 Normal Operating State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IEEE 1588 Timestamping Engine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.13.1 IEEE 1588 Block Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.13.2 Supporting IEEE 1588 Timestamping Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.13.3 Application 1: IEEE 1588 One-Step E2E TC in Systems . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.13.4 Application 2: IEEE 1588 TC and BC in Systems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.13.5 Application 3: Enhancing IEEE 1588 Accuracy for CE Switches and MACs . . . . . . . . . . . . . . 3.13.6 Supporting One-Step Peer-to-Peer Transparent Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.13.7 Supporting One-Step Boundary Clock/Ordinary Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.13.8 Supporting Two- Step Boundary/Ordinary Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.13.9 Supporting Two-Step Transparent Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.13.10 Calculating Y.1731 OAM Delay Measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.13.11 One-Way Delay Measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.13.12 Two-Way Delay Measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.13.13 IEEE 1588 Device Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.13.14 Timestamp Update . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.13.15 Analyzer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.13.16 Timestamp Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.13.17 Timestamp FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.13.18 Serial Timestamp Output Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.13.19 Rewriter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.13.20 Local Time Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.13.21 Accuracy and Resolution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.13.22 Accessing 1588 IP Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.13.23 1588_DIFF_INPUT_CLK Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Media Recovered Clock Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.14.1 Clock Selection Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.14.2 Clock Output Squelch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Serial Management Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.15.1 SMI Frames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.15.2 SMI Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . LED Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.16.1 LED Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.16.2 Extended LED Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.16.3 LED Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.16.4 Basic Serial LED Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.16.5 Enhanced Serial LED Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.16.6 LED Port Swapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Fast Link Failure Indication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Integrated Two-Wire Serial Multiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.18.1 Read/Write Access Using the Two-Wire Serial MUX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GPIO Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Testing Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.20.1 Ethernet Packet Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.20.2 CRC Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.20.3 Far-End Loopback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.20.4 Near-End Loopback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.20.5 Connector Loopback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.20.6 SerDes Loopbacks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.20.7 VeriPHY Cable Diagnostics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.20.8 JTAG Boundary Scan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.20.9 JTAG Instruction Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VMDS-10509 VSC8572-02 Datasheet Revision 4.2 22 24 24 25 25 25 25 25 30 30 30 31 31 35 37 38 39 39 41 43 43 47 65 66 67 68 70 71 72 73 73 73 73 73 74 75 75 76 77 78 78 79 79 80 80 80 81 82 82 82 83 83 83 84 87 88 89 iv 3.21 3.22 3.20.10 Boundary Scan Register Cell Order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100BASE-FX Halt Code Transmission and Reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.22.1 Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 91 92 93 4 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 4.1 4.2 4.3 4.4 4.5 Register and Bit Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 IEEE 802.3 and Main Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 4.2.1 Mode Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 4.2.2 Mode Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 4.2.3 Device Identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 4.2.4 Autonegotiation Advertisement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 4.2.5 Link Partner Autonegotiation Capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 4.2.6 Autonegotiation Expansion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 4.2.7 Transmit Autonegotiation Next Page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 4.2.8 Autonegotiation Link Partner Next Page Receive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 4.2.9 1000BASE-T Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 4.2.10 1000BASE-T Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 4.2.11 MMD Access Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 4.2.12 MMD Address or Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 4.2.13 1000BASE-T Status Extension 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 4.2.14 100BASE-TX/FX Status Extension . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 4.2.15 1000BASE-T Status Extension 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 4.2.16 Bypass Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 4.2.17 Error Counter 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 4.2.18 Error Counter 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 4.2.19 Error Counter 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 4.2.20 Extended Control and Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 4.2.21 Extended PHY Control Set 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 4.2.22 Extended PHY Control Set 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 4.2.23 Interrupt Mask . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 4.2.24 Interrupt Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 4.2.25 Device Auxiliary Control and Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 4.2.26 LED Mode Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 4.2.27 LED Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 4.2.28 Extended Page Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 Extended Page 1 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 4.3.1 SerDes Media Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 4.3.2 Cu Media CRC Good Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 4.3.3 Extended Mode Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 4.3.4 ActiPHY Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 4.3.5 PoE and Miscellaneous Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 4.3.6 VeriPHY Control 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 4.3.7 VeriPHY Control 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 4.3.8 VeriPHY Control 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 4.3.9 Ethernet Packet Generator Control 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 4.3.10 Ethernet Packet Generator Control 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 Extended Page 2 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 4.4.1 Cu PMD Transmit Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 4.4.2 EEE Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 4.4.3 RGMII Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 4.4.4 Ring Resiliency Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 Extended Page 3 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 4.5.1 MAC SerDes PCS Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 4.5.2 MAC SerDes PCS Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 4.5.3 MAC SerDes Clause 37 Advertised Ability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 4.5.4 MAC SerDes Clause 37 Link Partner Ability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 VMDS-10509 VSC8572-02 Datasheet Revision 4.2 v 4.6 4.7 4.8 4.9 4.10 4.11 4.12 4.13 4.14 4.5.5 MAC SerDes Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 4.5.6 Media SerDes Transmit Good Packet Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 4.5.7 Media SerDes Transmit CRC Error Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 4.5.8 Media SerDes PCS Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 4.5.9 Media SerDes PCS Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 4.5.10 Media SerDes Clause 37 Advertised Ability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 4.5.11 Media SerDes Clause 37 Link Partner Ability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 4.5.12 Media SerDes Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 4.5.13 Fiber Media CRC Good Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 4.5.14 Fiber Media CRC Error Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 General Purpose Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 4.6.1 Reserved General Purpose Address Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 4.6.2 SIGDET/GPIO Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 4.6.3 GPIO Control 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 4.6.4 GPIO Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 4.6.5 GPIO Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 4.6.6 GPIO Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 4.6.7 Microprocessor Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 4.6.8 MAC Configuration and Fast Link . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 4.6.9 Two-Wire Serial MUX Control 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 4.6.10 Two-Wire Serial MUX Control 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 4.6.11 Two-Wire Serial MUX Data Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 4.6.12 Recovered Clock 1 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 4.6.13 Recovered Clock 2 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 4.6.14 Enhanced LED Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 4.6.15 Global Interrupt Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 4.6.16 Extended Revision ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 Clause 45 Registers to Support Energy Efficient Ethernet and 802.3bf . . . . . . . . . . . . . . . . . . . . . . . 138 4.7.1 PCS Status 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 4.7.2 EEE Capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 4.7.3 EEE Wake Error Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 4.7.4 EEE Advertisement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 4.7.5 EEE Link Partner Advertisement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 1588 IP Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 1588 IP Block Configuration and Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 1588 IP Control and Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 4.10.1 Interface Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 4.10.2 Analyzer Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 4.10.3 Spare Scratchpad . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 1588 IP Local Time Counter Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 4.11.1 LTC Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 4.11.2 LTC Load Seconds (High) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 4.11.3 LTC Load Seconds (Low) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 4.11.4 LTC Load Nanoseconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 4.11.5 LTC Saved Seconds (High) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 4.11.6 LTC Saved Seconds (Low) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 4.11.7 LTC Saved Nanoseconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 4.11.8 LTC Sequence Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 4.11.9 LTC Sequence Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 4.11.10 LTC Auto Adjustment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 Timestamp FIFO Serial Interface Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 4.12.1 Timestamp FIFO Serial Interface Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 4.12.2 Transmitted Timestamp Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 Ingress (Rx) Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 4.13.1 Ingress Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 Egress (Tx) Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 4.14.1 Egress Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 VMDS-10509 VSC8572-02 Datasheet Revision 4.2 vi 4.15 4.16 4.17 4.18 4.19 4.20 4.21 4.22 4.23 4.24 4.25 4.26 4.27 1588 IP Ingress Control and Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 4.15.1 IP 1588 Interrupt Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 4.15.2 IP 1588 Interrupt Mask . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 4.15.3 Spare Scratchpad . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 1588 IP Ingress Timestamp Processor Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 4.16.1 TSP Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 4.16.2 TSP Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 4.16.3 Local Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 4.16.4 Path Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 4.16.5 DelayAsymmetry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 1588 IP Ingress Delay FIFO Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 4.17.1 Configuration and Control for the Delay FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 1588 IP Ingress Rewriter Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 4.18.1 Rewriter Configuration and Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 4.18.2 Count of Modified Frames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 4.18.3 Count of FCS Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 4.18.4 Count of the Number of Preamble Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 1588 IP Egress Control & Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 4.19.1 IP 1588 Interrupt Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 4.19.2 IP 1588 Interrupt Mask . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 4.19.3 Spare Scratchpad . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 1588 IP Egress Timestamp Processor Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 4.20.1 TSP Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 4.20.2 TSP Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 4.20.3 Local Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 4.20.4 Path Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 4.20.5 DelayAsymmetry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 1588 IP Egress Delay FIFO Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 4.21.1 Configuration and Control for the Delay FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 1588 IP Egress Timestamp FIFO Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 4.22.1 Timestamp FIFO Configuration and Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 4.22.2 Data Value from the Timestamp FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 4.22.3 Data Value from the Timestamp FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 4.22.4 Data Value from the Timestamp FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 4.22.5 Data Value from the Timestamp FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 4.22.6 Data Value from the Timestamp FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 4.22.7 Data Value from the Timestamp FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 4.22.8 Data Value from the Timestamp FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 4.22.9 Count of Dropped Timestamps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 1588 IP Egress Rewriter Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 4.23.1 Rewriter Configuration and Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 4.23.2 Count of Modified Frames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 4.23.3 Count of FCS Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 4.23.4 Count of the Number of Preamble Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 1588 IP Ingress Debug Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 4.24.1 Software Pop FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 1588 IP Egress Debug Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 4.25.1 Software Pop FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 Ingress0 Analyzer Engine Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 Ingress0 Ethernet Next Protocol Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 4.27.1 Ethernet Next Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 4.27.2 VLAN TPID Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 4.27.3 Ethernet Tag Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 4.27.4 Ethertype Match . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 4.27.5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 4.27.6 Ethernet Flow Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 VMDS-10509 VSC8572-02 Datasheet Revision 4.2 vii 4.28 4.27.7 Ethernet Protocol Match Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 4.27.8 Ethernet Address Match Part 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 4.27.9 Ethernet Address Match Part 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 4.27.10 Ethernet VLAN Tag Range Match . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 4.27.11 VLAN Tag 1 Match/Mask . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 4.27.12 Match/Mask For VLAN Tag 2 or I-Tag Match . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 4.27.13 Ethernet Next Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 4.27.14 VLAN TPID Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 4.27.15 Ethertype Match . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 4.27.16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 4.27.17 Ethernet Flow Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 4.27.18 Ethernet Protocol Match Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 4.27.19 Ethernet Address Match Part 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 4.27.20 Ethernet Address Match Part 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 4.27.21 Ethernet VLAN Tag Range Match . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 4.27.22 VLAN Tag 1 Match/Mask . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 4.27.23 Match/Mask for VLAN Tag 2 or I-Tag Match . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 Ingress0 MPLS Next Protocol Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 4.28.1 MPLS Next Protocol Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 4.28.2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 4.28.3 MPLS Flow Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 4.28.4 MPLS Label 0 Match Range Lower Value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 4.28.5 MPLS Label 0 Match Range Upper Value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 4.28.6 MPLS Label 1 Match Range Lower Value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 4.28.7 MPLS Label 1 Match Range Lower Value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 4.28.8 MPLS Label 2 Match Range Lower Value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 4.28.9 MPLS Label 2 Match Range Lower Value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 4.28.10 MPLS Label 3 Match Range Lower Value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 4.28.11 MPLS Label 3 Match Range Lower Value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 4.28.12 IP Next Comparator Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 4.28.13 IP Comparator Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 4.28.14 IP Match Register Set 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 4.28.15 Upper Portion of Match 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 4.28.16 Lower Portion of Match 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 4.28.17 Upper Portion of Match Mask 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 4.28.18 Lower Portion of Match Mask 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 4.28.19 Match Offset 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 4.28.20 IP/UDP Checksum Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 4.28.21 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 4.28.22 IP Flow Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 4.28.23 Upper Portion of the IP Flow Match . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 4.28.24 Upper Mid Portion of the IP Flow Match . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 4.28.25 Lower Mid Portion of the IP Flow Match . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 4.28.26 Lower Portion of the IP Flow Match . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 4.28.27 IP Flow Match Mask . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 4.28.28 Upper Mid Portion of the IP Flow Mask . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 4.28.29 Lower Mid Portion of the IP Flow Mask . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 4.28.30 Lower Portion of the IP Flow Mask . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 4.28.31 IP Next Comparator Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 4.28.32 IP Comparator Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 4.28.33 IP Match Set 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 4.28.34 Upper Portion of Match 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 4.28.35 Lower Portion of Match 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 4.28.36 Upper Portion of Match Mask 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 4.28.37 Lower Portion of Match Mask 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 4.28.38 Match Offset 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 4.28.39 IP/UDP Checksum Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 4.28.40 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 VMDS-10509 VSC8572-02 Datasheet Revision 4.2 viii 4.29 4.30 4.31 4.32 4.28.41 IP Flow Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 4.28.42 Upper Portion of the IP Flow Match . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 4.28.43 Upper Mid Portion of the IP Flow Match . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 4.28.44 Lower Mid Portion of the IP Flow Match . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 4.28.45 Lower Portion of the IP Flow Match . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 4.28.46 IP Flow Match Mask . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 4.28.47 Upper Mid Portion of the IP Flow Mask . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 4.28.48 Lower Mid Portion of the IP Flow Mask . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 4.28.49 Lower Portion of the IP Flow Mask . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 4.28.50 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 4.28.51 PTP/OAM Flow Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 4.28.52 Upper Half of PTP/OAM Flow Match Field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 4.28.53 Lower Half of PTP/OAM Flow Match Field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 4.28.54 Upper Half of PTP/OAM Flow Match Mask . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 4.28.55 Lower Half of PTP/OAM Flow Match Mask . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 4.28.56 PTP/OAM Range Match . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 4.28.57 PTP Action Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202 4.28.58 PTP Action Control 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 4.28.59 Zero Field Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 Ingress0 IP Checksum Field Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204 4.29.1 IP Checksum Block Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204 Egress0 Analyzer Engine Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204 Egress0 Ethernet Next Protocol Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209 4.31.1 Ethernet Next Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209 4.31.2 VLAN TPID Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209 4.31.3 Ethernet Tag Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209 4.31.4 Ethertype Match . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 4.31.5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 4.31.6 Ethernet Flow Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 4.31.7 Ethernet Protocol Match Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 4.31.8 Ethernet Address Match Part 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212 4.31.9 Ethernet Address Match Part 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212 4.31.10 Ethernet VLAN Tag Range Match . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213 4.31.11 VLAN Tag 1 Match/Mask . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213 4.31.12 Match/Mask For VLAN Tag 2 or I-Tag Match . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214 4.31.13 Ethernet Next Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214 4.31.14 VLAN TPID Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 4.31.15 Ethertype Match . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 4.31.16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 4.31.17 Ethernet Flow Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 4.31.18 Ethernet Protocol Match Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216 4.31.19 Ethernet Address Match Part 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217 4.31.20 Ethernet Address Match Part 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217 4.31.21 Ethernet VLAN Tag Range Match . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218 4.31.22 VLAN Tag 1 Match/Mask . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218 4.31.23 Match/Mask For VLAN Tag 2 or I-Tag Match . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219 Egress0 MPLS Next Protocol Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219 4.32.1 MPLS Next Protocol Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219 4.32.2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 4.32.3 MPLS Flow Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 4.32.4 MPLS Label 0 Match Range Lower Value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221 4.32.5 MPLS Label 0 Match Range Upper Value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221 4.32.6 MPLS Label 1 Match Range Lower Value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222 4.32.7 MPLS Label 1 Match Range Lower Value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222 4.32.8 MPLS Label 2 Match Range Lower Value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222 4.32.9 MPLS Label 2 Match Range Lower Value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223 4.32.10 MPLS Label 3 Match Range Lower Value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223 4.32.11 MPLS Label 3 Match Range Lower Value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224 VMDS-10509 VSC8572-02 Datasheet Revision 4.2 ix 4.33 4.34 4.32.12 IP Next Comparator Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224 4.32.13 IP Comparator Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224 4.32.14 IP Match Set 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 4.32.15 Upper Portion of Match 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 4.32.16 Lower Portion of Match 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 4.32.17 Upper Portion of Match Mask 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 4.32.18 Lower Portion of Match Mask 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226 4.32.19 Match Offset 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226 4.32.20 IP/UDP Checksum Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226 4.32.21 IP Frame Signature Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227 4.32.22 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227 4.32.23 IP Flow Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227 4.32.24 Upper Portion of the IP Flow Match . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228 4.32.25 Upper Mid Portion of the IP Flow Match . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228 4.32.26 Lower Mid Portion of the IP Flow Match . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229 4.32.27 Lower Portion of the IP Flow Match . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229 4.32.28 IP Flow Match Mask . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229 4.32.29 Upper Mid Portion Of IP Flow Mask . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230 4.32.30 Lower Mid Portion of IP Flow Mask . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230 4.32.31 Lower Portion of IP Flow Mask . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231 4.32.32 IP Next Comparator Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231 4.32.33 IP Comparator Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231 4.32.34 IP Match Register Set 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232 4.32.35 Upper Portion of Match 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232 4.32.36 Lower Portion of Match 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232 4.32.37 Upper Portion of Match Mask 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232 4.32.38 Lower Portion of Match Mask 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233 4.32.39 Match Offset Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233 4.32.40 IP/UDP Checksum Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233 4.32.41 IP Frame Signature Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234 4.32.42 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234 4.32.43 IP Flow Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234 4.32.44 Upper Portion of the IP Flow Match . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235 4.32.45 Upper Mid Portion of the IP Flow Match . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235 4.32.46 Lower Mid Portion of the IP Flow Match . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236 4.32.47 Lower Portion of the IP Flow Match . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236 4.32.48 Upper Portion of the IP Flow Match Mask . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236 4.32.49 Upper Mid Portion of the IP Flow Match Mask . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237 4.32.50 Lower Mid Portion of the IP Flow Match Mask . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237 4.32.51 Lower Portion of the IP Flow Match Mask . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238 4.32.52 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238 4.32.53 PTP/OAM Flow Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238 4.32.54 Upper Half of PTP/OAM Flow Match Field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239 4.32.55 Lower Half of PTP/OAM Flow Match Field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239 4.32.56 Upper Half of PTP/OAM Flow Match Mask . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239 4.32.57 Lower Half of PTP/OAM Flow Match Mask . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240 4.32.58 PTP/OAM Range Match . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240 4.32.59 PTP Action Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240 4.32.60 PTP Action Control 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242 4.32.61 Zero Field Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242 Egress0 IP Checksum Field Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242 4.33.1 IP Checksum Block Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242 Egress0 Frame Signature Builder Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243 4.34.1 Frame Signature Builder Mode Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243 4.34.2 Frame Signature Builder Mapping 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243 4.34.3 Frame Signature Builder Mapping 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244 4.34.4 Frame Signature Builder Mapping 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244 4.34.5 Frame Signature Builder Mapping 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244 VMDS-10509 VSC8572-02 Datasheet Revision 4.2 x 4.35 4.36 4.37 4.38 4.39 Ingress2 Analyzer Engine Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245 Ingress2 Ethernet Next Protocol Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247 4.36.1 Ethernet Next Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247 4.36.2 VLAN TPID Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247 4.36.3 Ethernet Tag Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248 4.36.4 Ethertype Match . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248 4.36.5 Ethernet Next Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248 4.36.6 VLAN TPID Configuration B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249 4.36.7 Ethernet Tag Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249 4.36.8 Ethertype Match . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249 4.36.9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249 4.36.10 Ethernet Flow Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250 4.36.11 Ethernet Protocol Match Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250 4.36.12 Ethernet Address Match Part 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251 4.36.13 Ethernet Address Match Part 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252 4.36.14 Ethernet VLAN Tag Range Match . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252 4.36.15 VLAN Tag 1 Match/Mask . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253 4.36.16 Match/Mask For VLAN Tag 2 or I-Tag Match . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253 4.36.17 Ethernet Next Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254 4.36.18 VLAN TPID Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254 4.36.19 Ethertype Match . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254 4.36.20 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254 4.36.21 Ethernet Flow Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255 4.36.22 Ethernet Protocol Match Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255 4.36.23 Ethernet Address Match Part 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256 4.36.24 Ethernet Address Match Part 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257 4.36.25 Ethernet VLAN Tag Range Match . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257 4.36.26 VLAN Tag 1 Match/Mask . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258 4.36.27 Match/Mask For VLAN Tag 2 or I-Tag Match . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258 Ingress2 MPLS Next Protocol Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259 4.37.1 MPLS Next Protocol Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259 4.37.2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259 4.37.3 MPLS Flow Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259 4.37.4 MPLS Label 0 Match Range Lower Value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260 4.37.5 MPLS Label 0 Match Range Lower Value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260 4.37.6 MPLS Label 1 Match Range Lower Value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261 4.37.7 MPLS Label 1 Match Range Lower Value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261 4.37.8 MPLS Label 2 Match Range Lower Value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262 4.37.9 MPLS Label 2 Match Range Lower Value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262 4.37.10 MPLS Label 3 Match Range Lower Value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262 4.37.11 MPLS Label 3 Match Range Lower Value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263 4.37.12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263 4.37.13 PTP/OAM Flow Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263 4.37.14 Upper Half of PTP/OAM Flow Match Field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264 4.37.15 Lower Half of PTP/OAM Flow Match Field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264 4.37.16 Upper Half of PTP/OAM Flow Match Mask . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265 4.37.17 Lower Half of PTP/OAM Flow Match Mask . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265 4.37.18 PTP/OAM Range Match . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265 4.37.19 PTP Action Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266 4.37.20 PTP Action Control 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267 4.37.21 Zero Field Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267 Egress2 Analyzer Engine Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268 Egress2 Ethernet Next Protocol Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270 4.39.1 Ethernet Next Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270 4.39.2 VLAN TPID Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271 4.39.3 Ethernet Tag Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271 4.39.4 Ethertype Match . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271 4.39.5 Ethernet Next Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272 VMDS-10509 VSC8572-02 Datasheet Revision 4.2 xi 4.40 4.39.6 VLAN TPID Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272 4.39.7 Ethernet Tag Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272 4.39.8 Ethertype Match . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272 4.39.9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273 4.39.10 Ethernet Flow Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273 4.39.11 Ethernet Protocol Match Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273 4.39.12 Ethernet Address Match Part 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275 4.39.13 Ethernet Address Match Part 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275 4.39.14 Ethernet VLAN Tag Range Match . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275 4.39.15 VLAN Tag 1 Match/Mask . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276 4.39.16 Match/Mask For VLAN Tag 2 or I-Tag Match . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276 4.39.17 Ethernet Next Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277 4.39.18 VLAN TPID Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277 4.39.19 Ethertype Match . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277 4.39.20 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278 4.39.21 Ethernet Flow Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278 4.39.22 Ethernet Protocol Match Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278 4.39.23 Ethernet Address Match Part 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279 4.39.24 Ethernet Address Match Part 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280 4.39.25 Ethernet VLAN Tag Range Match . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280 4.39.26 VLAN Tag 1 Match/Mask . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281 4.39.27 Match/Mask For VLAN Tag 2 or I-Tag Match . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281 Egress2 MPLS Next Protocol Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282 4.40.1 MPLS Next Protocol Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282 4.40.2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282 4.40.3 MPLS Flow Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282 4.40.4 MPLS Label 0 Match Range Lower Value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283 4.40.5 MPLS Label 0 Match Range Lower Value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283 4.40.6 MPLS Label 1 Match Range Lower Value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284 4.40.7 MPLS Label 1 Match Range Lower Value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284 4.40.8 MPLS Label 2 Match Range Lower Value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285 4.40.9 MPLS Label 2 Match Range Lower Value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285 4.40.10 MPLS Label 3 Match Range Lower Value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285 4.40.11 MPLS Label 3 Match Range Lower Value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286 4.40.12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286 4.40.13 PTP/OAM Flow Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286 4.40.14 Upper Half of PTP/OAM Flow Match Field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287 4.40.15 Lower Half of PTP/OAM Flow Match Field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287 4.40.16 Upper Half of PTP/OAM Flow Match Mask . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288 4.40.17 Lower Half of PTP/OAM Flow Match Mask . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288 4.40.18 PTP/OAM Range Match . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288 4.40.19 PTP Action Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289 4.40.20 PTP Action Control 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290 4.40.21 Zero Field Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290 5 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292 5.1 5.2 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292 5.1.1 VDD25 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292 5.1.2 LED and GPIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292 5.1.3 Internal Pull-Up or Pull-Down Resistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292 5.1.4 Reference Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293 5.1.5 1588 Reference Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293 5.1.6 SerDes Interface (SGMII) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293 5.1.7 Enhanced SerDes Interface (QSGMII) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295 5.1.8 Current Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296 5.1.9 Thermal Diode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 298 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 298 5.2.1 Reference Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 298 VMDS-10509 VSC8572-02 Datasheet Revision 4.2 xii 5.3 5.4 5.2.2 Recovered Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299 5.2.3 SerDes Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300 5.2.4 SerDes Driver Jitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301 5.2.5 SerDes Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301 5.2.6 SerDes Receiver Jitter Tolerance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301 5.2.7 Enhanced SerDes Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301 5.2.8 Basic Serial LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 304 5.2.9 Enhanced Serial LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305 5.2.10 JTAG Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305 5.2.11 RGMII, Uncompensated . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306 5.2.12 RGMII, Compensated . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308 5.2.13 Serial Management Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 309 5.2.14 Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 310 5.2.15 1588 Timing Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 311 5.2.16 Serial Timestamp Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 311 5.2.17 Local Time Counter Load/Save Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 311 Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 312 Stress Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 312 6 Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314 6.1 6.2 6.3 Pin Identifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pins by Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.3.1 1588 Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.3.2 GPIO and 1588 Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.3.3 GPIO and SIGDET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.3.4 JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.3.5 Miscellaneous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.3.6 Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.3.7 SGMII/SerDes/QSGMII MAC Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.3.8 SerDes Media Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.3.9 Serial Management Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.3.10 Twisted Pair Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314 314 316 316 317 317 317 318 319 321 322 322 322 7 Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 324 7.1 7.2 7.3 Package Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 324 Thermal Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 325 Moisture Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 326 8 Design Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 327 8.1 8.2 8.3 8.4 8.5 8.6 8.7 8.8 8.9 8.10 8.11 8.12 8.13 8.14 Link status LED remains on while COMA_MODE pin is asserted high . . . . . . . . . . . . . . . . . . . . . . . . 327 LED pulse stretch enable turns off LED pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 327 AMS and 100BASE-FX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 327 10BASE-T signal amplitude . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 327 10BASE-T link recovery failures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 327 SNR degradation and link drops . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 327 Clause 45 register 3.22 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 327 Clause 45 register 3.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 328 Clause 45 register address post-increment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 328 Fast link failure indication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 328 Timestamp accuracy in 10BASE-T mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 328 Near-end loopback with AMS enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 328 Carrier detect assertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 328 Link status not correct in register 24E3.2 for 100BASE-FX operation . . . . . . . . . . . . . . . . . . . . . . . . . 328 VMDS-10509 VSC8572-02 Datasheet Revision 4.2 xiii 8.15 8.16 8.17 8.18 8.19 8.20 8.21 8.22 8.23 8.24 8.25 Register 28.14 does not reflect autonegotiation disabled in 100BASE-FX mode . . . . . . . . . . . . . . . . 328 Near-end loopback non-functional in protocol transfer mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 329 Fiber-media CRC counters non-functional in protocol transfer mode at 10 Mbps and 100 Mbps . . . . 329 Fiber-media recovered clock does not squelch based on link status . . . . . . . . . . . . . . . . . . . . . . . . . . 329 1000BASE-X parallel detect mode with Clause 37 autonegotiation enabled . . . . . . . . . . . . . . . . . . . . 329 Anomalous PCS error indications in Energy Efficient Ethernet mode . . . . . . . . . . . . . . . . . . . . . . . . . 329 Long link-up times while in forced 100BASE-TX mode of operation . . . . . . . . . . . . . . . . . . . . . . . . . . 329 Timestamp errors due to IEEE 1588 Reference Clock interruption . . . . . . . . . . . . . . . . . . . . . . . . . . . 330 1588 bypass shall be enabled during engine reconfiguration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 330 Missing clock pulses on serial timestamp output interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 330 Station managers cannot use MDIO address offsets 0x2 and 0x3 with the PHY . . . . . . . . . . . . . . . . 330 9 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 331 VMDS-10509 VSC8572-02 Datasheet Revision 4.2 xiv Figures Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 Figure 8 Figure 9 Figure 10 Figure 11 Figure 12 Figure 13 Figure 14 Figure 15 Figure 16 Figure 17 Figure 18 Figure 19 Figure 20 Figure 21 Figure 22 Figure 23 Figure 24 Figure 25 Figure 26 Figure 27 Figure 28 Figure 29 Figure 30 Figure 31 Figure 32 Figure 33 Figure 34 Figure 35 Figure 36 Figure 37 Figure 38 Figure 39 Figure 40 Figure 41 Figure 42 Figure 43 Figure 44 Figure 45 Figure 46 Figure 47 Figure 48 Figure 49 Figure 50 Figure 51 Figure 52 Figure 53 Figure 54 Dual Media Application Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Copper Transceiver Application Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Fiber Media Transceiver Application Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 SGMII MAC-to-1000BASE-X Link Partner . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 QSGMII MAC-to-1000BASE-X Link Partner . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 QSGMII/SGMII MAC-to-100BASE-FX Link Partner . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 QSGMII/SGMII MAC-to-AMS and 1000BASE-X Media SerDes . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 QSGMII/SGMII MAC-to-AMS and 100BASE-FX Media SerDes . . . . . . . . . . . . . . . . . . . . . . . . . . 10 QSGMII/SGMII MAC-to-AMS and Protocol Transfer Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 QSGMII/SGMII MAC-to-Cat5 Link Partner . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 QSGMII/SGMII MAC-to-Protocol Transfer Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 1000BASE-X MAC-to-Cat5 Link Partner . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 RGMII MAC Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 SerDes MAC Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 SGMII MAC Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 QSGMII MAC Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Cat5 Media Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Low Power Idle Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Automatic Media Sense Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2.5 V CMOS Single-Ended REFCLK Input Resistor Network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.3 V CMOS Single-Ended REFCLK Input Resistor Network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 5 V CMOS Single-Ended REFCLK Input Resistor Network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 AC Coupling for REFCLK Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Inline Powered Ethernet Switch Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 ActiPHY State Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 IEEE 1588 Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 One-Step E2E TC Mode A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 One-Step E2E TC Mode B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Linecard E2E TC PHY application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 BC Linecard Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Delay Measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 One-Step P2P TC Standard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 One-Step E2E BC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Two-Step E2E BC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Two-Step E2E TC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Y.1731 1DM PDU Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Y.1731 One-Way Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Y.1731 DMM PDU Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Y.1731 Two-Way Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 PTP Packet Encapsulations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 OAM Packet Encapsulations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 TSU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Analyzer Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Type II Ethernet Basic Frame Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Ethernet Frame with SNAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Ethernet Frame with VLAN Tag and SNAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Ethernet Frame with VLAN Tags and SNAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 PBB Ethernet Frame Format (No B-Tag) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 PBB Ethernet Frame Format (1 B-Tag) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 MPLS Label Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 MPLS Label Stack within an Ethernet Frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 MPLS Labels and Control Word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 IPv4 with UDP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 VMDS-10509 VSC8572-02 Datasheet Revision 4.2 xv Figure 55 Figure 56 Figure 57 Figure 58 Figure 59 Figure 60 Figure 61 Figure 62 Figure 63 Figure 64 Figure 65 Figure 66 Figure 67 Figure 68 Figure 69 Figure 70 Figure 71 Figure 72 Figure 73 Figure 74 Figure 75 Figure 76 Figure 77 Figure 78 Figure 79 Figure 80 Figure 81 Figure 82 Figure 83 Figure 84 Figure 85 Figure 86 Figure 87 Figure 88 Figure 89 Figure 90 Figure 91 Figure 92 Figure 93 Figure 94 Figure 95 Figure 96 Figure 97 Figure 98 IPv6 with UDP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 ACH Header Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 ACH Header with Protocol ID Field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 IPSec Header Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 IPv6 with UDP and IPSec . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 PTP Frame Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 OAM 1DM Frame Header Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 OAM DMM Frame Header Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 OAM DMR Frame Header Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Serial Time Stamp/Frame Signature Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Preamble Reduction in Rewriter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Local Time Counter Load/Save Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 SMI Read Frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 SMI Write Frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 MDINT Configured as an Open-Drain (Active-Low) Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 MDINT Configured as an Open-Source (Active-High) Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Two-Wire Serial MUX with SFP Control and Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 Two-Wire Serial MUX Read and Write Register Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 Far-End Loopback Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 Near-End Loopback Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 Connector Loopback Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 Data Loops of the SerDes Macro . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 Test Access Port and Boundary Scan Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 Register Space Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 SGMII DC Transmit Test Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294 SGMII DC Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294 SGMII DC Driver Output Impedance Test Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295 SGMII DC Input Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295 Test Circuit for Recovered Clock Output Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299 QSGMII Transient Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302 Basic Serial LED Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 304 Enhanced Serial LED Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305 JTAG Interface Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306 Test Circuit for TDO Disable Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306 Test Circuit for RGMII Output Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306 RGMII Uncompensated Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308 Compensated Input RGMII Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 309 Compensated Output RGMII Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 309 Serial Management Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 310 Serial Timestamp Interface Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 311 Local Time Counter Load/Save Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 312 Pin Diagram, Top Left . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 315 Pin Diagram, Top Right . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 316 Package Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 325 VMDS-10509 VSC8572-02 Datasheet Revision 4.2 xvi Tables Table 1 Table 2 Table 3 Table 4 Table 5 Table 6 Table 7 Table 8 Table 9 Table 10 Table 11 Table 12 Table 13 Table 14 Table 15 Table 16 Table 17 Table 18 Table 19 Table 20 Table 21 Table 22 Table 23 Table 24 Table 25 Table 26 Table 27 Table 28 Table 29 Table 30 Table 31 Table 32 Table 33 Table 34 Table 35 Table 36 Table 37 Table 38 Table 39 Table 40 Table 41 Table 42 Table 43 Table 44 Table 45 Table 46 Table 47 Table 48 Table 49 Table 50 Table 51 Table 52 Table 53 Table 54 Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 MAC Interface Mode Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Supported MDI Pair Combinations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 AMS Media Preferences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 REFCLK Frequency Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Flows Per Engine Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Ethernet Comparator: Next Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Comparator ID Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Ethernet Comparator (Next Protocol) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Ethernet Comparator (Flow) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 MPLS Comparator: Next Word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Next MPLS Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 MPLS Comparator: Per-Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 MPLS Range_Upper/Lower Label Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Next-Protocol Registers in OAM-Version of MPLS Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Comparator Field Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 IP/ACH Next-Protocol Comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 IP/ACH Comparator Flow Verification Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 PTP Comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 PTP Comparison: Common Controls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 PTP Comparison: Additions for OAM-Optimized Engine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Frame Signature Byte Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Frame Signature Address Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Register 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Register 17 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Register 18 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 LED Drive State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 LED Mode and Function Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 Extended LED Mode and Function Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 LED Serial Bitstream Order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Register Bits for GPIO Control and Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 SerDes Macro Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 JTAG Instruction Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 IDCODE JTAG Device Identification Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 USERCODE JTAG Device Identification Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 JTAG Instruction Code IEEE Compliance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 Register 18E2 Settings for RGMII . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 IEEE 802.3 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 Main Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 Mode Control, Address 0 (0x00) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 Mode Status, Address 1 (0x01) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 Identifier 1, Address 2 (0x02) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 Identifier 2, Address 3 (0x03) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 Device Autonegotiation Advertisement, Address 4 (0x04) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 Autonegotiation Link Partner Ability, Address 5 (0x05) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 Autonegotiation Expansion, Address 6 (0x06) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 Autonegotiation Next Page Transmit, Address 7 (0x07) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 Autonegotiation LP Next Page Receive, Address 8 (0x08) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 1000BASE-T Control, Address 9 (0x09) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 1000BASE-T Status, Address 10 (0x0A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 MMD EEE Access, Address 13 (0x0D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 MMD Address or Data Register, Address 14 (0x0E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 1000BASE-T Status Extension 1, Address 15 (0x0F) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 100BASE-TX/FX Status Extension, Address 16 (0x10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 VMDS-10509 VSC8572-02 Datasheet Revision 4.2 xvii Table 55 Table 56 Table 57 Table 58 Table 59 Table 60 Table 61 Table 62 Table 63 Table 64 Table 65 Table 66 Table 67 Table 68 Table 69 Table 70 Table 71 Table 72 Table 73 Table 74 Table 75 Table 76 Table 77 Table 78 Table 79 Table 80 Table 81 Table 82 Table 83 Table 84 Table 85 Table 86 Table 87 Table 88 Table 89 Table 90 Table 91 Table 92 Table 93 Table 94 Table 95 Table 96 Table 97 Table 98 Table 99 Table 100 Table 101 Table 102 Table 103 Table 104 Table 105 Table 106 Table 107 Table 108 Table 109 Table 110 Table 111 Table 112 Table 113 1000BASE-T Status Extension 2, Address 17 (0x11) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 Bypass Control, Address 18 (0x12) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 Error Counter 1, Address 19 (0x13) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 Error Counter 2, Address 20 (0x14) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 Error Counter 3, Address 21 (0x15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 Extended Control and Status, Address 22 (0x16) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 Extended PHY Control 1, Address 23 (0x17) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 Extended PHY Control 2, Address 24 (0x18) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 Interrupt Mask, Address 25 (0x19) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 Interrupt Status, Address 26 (0x1A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 Auxiliary Control and Status, Address 28 (0x1C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 LED Mode Select, Address 29 (0x1D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 LED Behavior, Address 30 (0x1E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 Extended/GPIO Register Page Access, Address 31 (0x1F) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 Extended Registers Page 1 Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 SerDes Media Control, Address 16E1 (0x10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 Cu Media CRC Good Counter, Address 18E1 (0x12) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 Extended Mode Control, Address 19E1 (0x13) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 Extended PHY Control 3, Address 20E1 (0x14) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 Extended PHY Control 4, Address 23E1 (0x17) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 VeriPHY Control Register 1, Address 24E1 (0x18) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 VeriPHY Control Register 2, Address 25E1 (0x19) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 VeriPHY Control Register 3, Address 26E1 (0x1A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 VeriPHY Control Register 3 Fault Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 EPG Control Register 1, Address 29E1 (0x1D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 EPG Control Register 2, Address 30E1 (0x1E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 Extended Registers Page 2 Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 Cu PMD Transmit Control, Address 16E2 (0x10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 EEE Control, Address 17E2 (0x11) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 RGMII Settings, Address 18E2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 Ring Resiliency, Address 30E2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 Extended Registers Page 3 Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 MAC SerDes PCS Control, Address 16E3 (0x10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 MAC SerDes PCS Status, Address 17E3 (0x11) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 MAC SerDes Cl37 Advertised Ability, Address 18E3 (0x12) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 MAC SerDes Cl37 LP Ability, Address 19E3 (0x13) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 MAC SerDes Status, Address 20E3 (0x14) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 Media SerDes Tx Good Packet Counter, Address 21E3 (0x15) . . . . . . . . . . . . . . . . . . . . . . . . . . 126 Media SerDes Tx CRC Error Counter, Address 22E3 (0x16) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 Media SerDes PCS Control, Address 23E3 (0x17) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 Media SerDes PCS Status, Address 24E3 (0x18) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 Media SerDes Cl37 Advertised Ability, Address 25E3 (0x19) . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 MAC SerDes Cl37 LP Ability, Address 26E3 (0x1A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 Media SerDes Status, Address 27E3 (0x1B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 Fiber Media CRC Good Counter, Address 28E3 (0x1C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 Fiber Media CRC Error Counter, Address 29E3 (0x1D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 General Purpose Registers Page Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 SIGDET/GPIO Control, Address 13G (0x0D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 GPIO Control 2, Address 14G (0x0E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 GPIO Input, Address 15G (0x0F) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 GPIO Output, Address 16G (0x10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 GPIO Input/Output Configuration, Address 17G (0x11) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 Microprocessor Command Register, Address 18G . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 MAC Configuration and Fast Link Register, Address 19G (0x13) . . . . . . . . . . . . . . . . . . . . . . . . 133 Two-Wire Serial MUX Control 1, Address 20G (0x14) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 Two-Wire Serial MUX Interface Status and Control, Address 21G (0x15) . . . . . . . . . . . . . . . . . . 134 Two-Wire Serial MUX Data Read/Write, Address 22G (0x16) . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 Recovered Clock 1 Control, Address 23G (0x17) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 Recovered Clock 2 Control, Address 24G (0x18) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 VMDS-10509 VSC8572-02 Datasheet Revision 4.2 xviii Table 114 Table 115 Table 116 Table 117 Table 118 Table 119 Table 120 Table 121 Table 122 Table 123 Table 124 Table 125 Table 126 Table 127 Table 128 Table 129 Table 130 Table 131 Table 132 Table 133 Table 134 Table 135 Table 136 Table 137 Table 138 Table 139 Table 140 Table 141 Table 142 Table 143 Table 144 Table 145 Table 146 Table 147 Table 148 Table 149 Table 150 Table 151 Table 152 Table 153 Table 154 Table 155 Table 156 Table 157 Table 158 Table 159 Table 160 Table 161 Table 162 Table 163 Table 164 Table 165 Table 166 Table 167 Table 168 Table 169 Table 170 Table 171 Table 172 Enhanced LED Control, Address 25G (0x19) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 Global Interrupt Status, Address 29G (0x1D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 Extended Revision ID, Address 30G (0x1E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 Clause 45 Registers Page Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 PCS Status 1, Address 3.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 EEE Capability, Address 3.20 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 EEE Wake Error Counter, Address 3.22 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 EEE Advertisement, Address 7.60 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 EEE Advertisement, Address 7.61 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 802.3bf Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 IP_1588_TOP_CFG_STAT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 IP_1588_LTC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 TS_FIFO_SI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 INGR_PREDICTOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 EGR_PREDICTOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 INGR_IP_1588_CFG_STAT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 INGR_IP_1588_TSP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 INGR_IP_1588_DF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 INGR_IP_1588_RW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 EGR_IP_1588_CFG_STAT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 EGR_IP_1588_TSP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 EGR_IP_1588_DF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 EGR_IP_1588_TSFIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 EGR_IP_1588_RW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 INGR_IP_1588_DEBUG_REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 EGR_IP_1588_DEBUG_REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 Interface Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 Analyzer Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 Spare Scratchpad Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 LTC Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 LTC Load Seconds (High) Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 LTC Load Seconds (Low) Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 LTC Load Nanoseconds Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 LTC Saved Seconds (High) Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 LTC Saved Seconds (Low) Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 LTC Saved Nanoseconds Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 LTC Sequence Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 LTC Sequence Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 LTC Auto Adjustment Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 Timestamp FIFO Serial Interface Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 Transmitted Timestamp Count Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 Ingress Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 Egress Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 IP 1588 Interrupt Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 IP 1588 Interrupt Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 Spare Scratchpad Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 TSP Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 TSP Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 Local Latency Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 Path Delay Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 DelayAsymmetry Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 Configuration and Control Register for the Delay FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 Rewriter Configuration and Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 Count of Modified Frames Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 Count of FCS Errors Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 Count of the Number of Preamble Errors Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 IP 1588 Interrupt Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 IP 1588 Interrupt Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 Spare Scratchpad Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 VMDS-10509 VSC8572-02 Datasheet Revision 4.2 xix Table 173 Table 174 Table 175 Table 176 Table 177 Table 178 Table 179 Table 180 Table 181 Table 182 Table 183 Table 184 Table 185 Table 186 Table 187 Table 188 Table 189 Table 190 Table 191 Table 192 Table 193 Table 194 Table 195 Table 196 Table 197 Table 198 Table 199 Table 200 Table 201 Table 202 Table 203 Table 204 Table 205 Table 206 Table 207 Table 208 Table 209 Table 210 Table 211 Table 212 Table 213 Table 214 Table 215 Table 216 Table 217 Table 218 Table 219 Table 220 Table 221 Table 222 Table 223 Table 224 Table 225 Table 226 Table 227 Table 228 Table 229 Table 230 Table 231 TSP Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 TSP Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 Local Latency Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 Path Delay Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 DelayAsymmetry Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 Configuration and Control Register for the Delay FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 Timestamp FIFO Configuration and Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 Data Value from the Timestamp FIFO Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 Data Value from the Timestamp FIFO Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 Data Value from the Timestamp FIFO Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 Data Value from the Timestamp FIFO Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 Data Value from the Timestamp FIFO Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 Data Value from the Timestamp FIFO Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 Data Value from the Timestamp FIFO Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 Count of Dropped Timestamps Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 Rewriter Configuration and Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 Count of Modified Frames Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 Count of FCS Errors Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 Count of the Number of Preamble Errors Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 INGR_SW_POP_FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 EGR_SW_POP_FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 INGR0_ETH1_NXT_PROTOCOL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 INGR0_ETH1_FLOW_CFG (8 instances) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 INGR0_ETH2_NXT_PROTOCOL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 INGR0_ETH2_FLOW_CFG (8 instances) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 INGR0_MPLS_NXT_COMPARATOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 INGR0_MPLS_FLOW_CFG (8 instances) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 INGR0_IP1_NXT_PROTOCOL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 INGR0_IP1_FLOW_CFG (8 instances) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 INGR0_IP2_NXT_PROTOCOL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 INGR0_IP2_FLOW_CFG (8 instances) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 INGR0_PTP_FLOW (6 instances) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 INGR0_PTP_IP_CHKSUM_CTL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 Ethernet Next Protocol Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 VLAN TPID Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 Ethernet Tag Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 Ethertype Match Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 Ethernet Flow Enable Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 Ethernet Protocol Match Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 Ethernet Address Match Part 1 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 Ethernet Address Match Part 2 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 Ethernet VLAN Tag Range Match Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 VLAN Tag 1 Match/Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 Match/Mask For VLAN Tag 2 or I-Tag Match Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 Ethernet Next Protocol Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 VLAN TPID Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 Ethertype Match Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 Ethernet Flow Enable Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 Ethernet Protocol Match Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 Ethernet Address Match Part 1 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 Ethernet Address Match Part 2 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 Ethernet VLAN Tag Range Match Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 VLAN Tag 1 Match/Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 Match/Mask for VLAN Tag 2 or I-Tag Match Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 MPLS Next Protocol Comparator Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 MPLS Flow Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 MPLS Label 0 Match Range Lower Value Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 MPLS Label 0 Match Range Upper Value Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 MPLS Label 1 Match Range Lower Value Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 VMDS-10509 VSC8572-02 Datasheet Revision 4.2 xx Table 232 Table 233 Table 234 Table 235 Table 236 Table 237 Table 238 Table 239 Table 240 Table 241 Table 242 Table 243 Table 244 Table 245 Table 246 Table 247 Table 248 Table 249 Table 250 Table 251 Table 252 Table 253 Table 254 Table 255 Table 256 Table 257 Table 258 Table 259 Table 260 Table 261 Table 262 Table 263 Table 264 Table 265 Table 266 Table 267 Table 268 Table 269 Table 270 Table 271 Table 272 Table 273 Table 274 Table 275 Table 276 Table 277 Table 278 Table 279 Table 280 Table 281 Table 282 Table 283 Table 284 Table 285 Table 286 Table 287 Table 288 Table 289 Table 290 MPLS Label 1 Match Range Lower Value Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 MPLS Label 2 Match Range Lower Value Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 MPLS Label 2 Match Range Lower Value Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 MPLS Label 3 Match Range Lower Value Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 MPLS Label 3 Match Range Lower Value Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 IP Next Comparator Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 IP Comparator Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 IP Match Register Set 1 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 Upper Portion of Match 2 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 Lower Portion of Match 2 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 Upper Portion of Match Mask 2 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 Lower Portion of Match Mask 2 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 Match Offset 2 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 IP/UDP Checksum Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 IP Flow Enable Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 Upper Portion of the IP Flow Match Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 Upper Mid Portion of the IP Flow Match Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 Lower Mid Portion of the IP Flow Match Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 Lower Portion of the IP Flow Match Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 IP Flow Match Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 Upper Mid Portion of the IP Flow Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 Lower Mid Portion of the IP Flow Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 Lower Portion of the IP Flow Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 IP Next Comparator Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 IP Comparator Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 IP Match Set 1 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 Upper Portion of Match 2 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 Lower Portion of Match 2 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 Upper Portion of Match Mask 2 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 Lower Portion of Match Mask 2 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 Match Offset 2 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 IP/UDP Checksum Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 IP Flow Enable Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 Upper Portion of the IP Flow Match Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 Upper Mid Portion of the IP Flow Match Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 Lower Mid Portion of the IP Flow Match Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 Lower Portion of the IP Flow Match Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 IP Flow Match Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 Upper Mid Portion of the IP Flow Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 Lower Mid Portion of the IP Flow Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 Lower Portion of the IP Flow Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 PTP/OAM Flow Enable Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 Upper Half of PTP/OAM Flow Match Field Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 Lower Half of PTP/OAM Flow Match Field Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 Upper Half of PTP/OAM Flow Match Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 Lower Half of PTP/OAM Flow Match Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 PTP/OAM Range Match Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202 PTP Action Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202 PTP Action Control 2 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 Zero Field Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204 IP Checksum Block Select Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204 EGR0_ETH1_NXT_PROTOCOL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204 EGR0_ETH1_FLOW_CFG (8 instances) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204 EGR0_ETH2_NXT_PROTOCOL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 EGR0_ETH2_FLOW_CFG (8 instances) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 EGR0_MPLS_NXT_COMPARATOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 EGR0_MPLS_FLOW_CFG (8 instances) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 EGR0_IP1_NXT_PROTOCOL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206 EGR0_IP1_FLOW_CFG (8 instances) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206 VMDS-10509 VSC8572-02 Datasheet Revision 4.2 xxi Table 291 Table 292 Table 293 Table 294 Table 295 Table 296 Table 297 Table 298 Table 299 Table 300 Table 301 Table 302 Table 303 Table 304 Table 305 Table 306 Table 307 Table 308 Table 309 Table 310 Table 311 Table 312 Table 313 Table 314 Table 315 Table 316 Table 317 Table 318 Table 319 Table 320 Table 321 Table 322 Table 323 Table 324 Table 325 Table 326 Table 327 Table 328 Table 329 Table 330 Table 331 Table 332 Table 333 Table 334 Table 335 Table 336 Table 337 Table 338 Table 339 Table 340 Table 341 Table 342 Table 343 Table 344 Table 345 Table 346 Table 347 Table 348 Table 349 EGR0_IP2_NXT_PROTOCOL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 EGR0_IP2_FLOW_CFG (8 instances) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 EGR0_PTP_FLOW (6 instances) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208 EGR0_PTP_IP_CHKSUM_CTL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208 EGR0_FRAME_SIG_CFG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208 Ethernet Next Protocol Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209 VLAN TPID Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209 Ethernet Tag Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 Ethertype Match Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 Ethernet Flow Enable Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 Ethernet Protocol Match Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 Ethernet Address Match Part 1 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212 Ethernet Address Match Part 2 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213 Ethernet VLAN Tag Range Match Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213 VLAN Tag 1 Match/Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214 Match/Mask For VLAN Tag 2 or I-Tag Match Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214 Ethernet Next Protocol Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214 VLAN TPID Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 Ethertype Match Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 Ethernet Flow Enable Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216 Ethernet Protocol Match Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216 Ethernet Address Match Part 1 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217 Ethernet Address Match Part 2 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218 Ethernet VLAN Tag Range Match Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218 VLAN Tag 1 Match/Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219 Match/Mask For VLAN Tag 2 or I-Tag Match Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219 MPLS Next Protocol Comparator Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219 MPLS Flow Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 MPLS Label 0 Match Range Lower Value Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221 MPLS Label 0 Match Range Upper Value Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222 MPLS Label 1 Match Range Lower Value Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222 MPLS Label 1 Match Range Lower Value Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222 MPLS Label 2 Match Range Lower Value Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223 MPLS Label 2 Match Range Lower Value Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223 MPLS Label 3 Match Range Lower Value Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224 MPLS Label 3 Match Range Lower Value Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224 IP Next Comparator Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224 IP Comparator Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 IP Match Set 1 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 Upper Portion of Match 2 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 Lower Portion of Match 2 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 Upper Portion of Match Mask 2 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226 Lower Portion of Match Mask 2 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226 Match Offset 2 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226 IP/UDP Checksum Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226 IP Frame Signature Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227 IP Flow Enabler Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228 Upper Portion of the IP Flow Match Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228 Upper Mid Portion of the IP Flow Match Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229 Lower Mid Portion of the IP Flow Match Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229 Lower Portion of the IP Flow Match Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229 IP Flow Match Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230 Upper Mid Portion of IP Flow Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230 Lower Mid Portion of IP Flow Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231 Lower Portion of IP Flow Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231 IP Next Comparator Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231 IP Comparator Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232 IP Match Register Set 1 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232 Upper Portion of Match 2 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232 VMDS-10509 VSC8572-02 Datasheet Revision 4.2 xxii Table 350 Table 351 Table 352 Table 353 Table 354 Table 355 Table 356 Table 357 Table 358 Table 359 Table 360 Table 361 Table 362 Table 363 Table 364 Table 365 Table 366 Table 367 Table 368 Table 369 Table 370 Table 371 Table 372 Table 373 Table 374 Table 375 Table 376 Table 377 Table 378 Table 379 Table 380 Table 381 Table 382 Table 383 Table 384 Table 385 Table 386 Table 387 Table 388 Table 389 Table 390 Table 391 Table 392 Table 393 Table 394 Table 395 Table 396 Table 397 Table 398 Table 399 Table 400 Table 401 Table 402 Table 403 Table 404 Table 405 Table 406 Table 407 Table 408 Lower Portion of Match 2 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232 Upper Portion of Match Mask 2 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233 Lower Portion of Match Mask 2 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233 Match Offset 2 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233 IP/UDP Checksum Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233 IP Frame Signature Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234 IP Flow Enable Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235 Upper Portion of the IP Flow Match Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235 Upper Mid Portion of the IP Flow Match Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236 Lower Mid Portion of the IP Flow Match Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236 Lower Portion of the IP Flow Match Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236 Upper Portion of the IP Flow Match Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237 Upper Mid Portion of the IP Flow Match Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237 Lower Mid Portion of the IP Flow Match Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238 Lower Portion of the IP Flow Match Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238 PTP/OAM Flow Enable Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239 Upper Half of PTP/OAM Flow Match Field Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239 Lower Half of PTP/OAM Flow Match Field Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239 Upper Half of PTP/OAM Flow Match Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240 Lower Half of PTP/OAM Flow Match Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240 PTP/OAM Range Match Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240 PTP Action Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241 PTP Action Control 2 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242 Zero Field Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242 IP Checksum Block Select Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243 Frame Signature Builder Mode Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243 Source Bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243 Frame Signature Builder Mapping 0 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244 Frame Signature Builder Mapping 1 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244 Frame Signature Builder Mapping 2 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244 Frame Signature Builder Mapping 3 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244 INGR2_ETH1_NXT_PROTOCOL_A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245 INGR2_ETH1_NXT_PROTOCOL_B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245 INGR2_ETH1_FLOW_CFG (8 instances) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245 INGR2_ETH2_NXT_PROTOCOL_A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245 INGR2_ETH2_FLOW_CFG (8 instances) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246 INGR2_MPLS_NXT_COMPARATOR_A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246 INGR2_MPLS_FLOW_CFG (8 instances) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246 INGR2_PTP_FLOW (6 instances) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247 Ethernet Next Protocol Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247 VLAN TPID Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248 Ethernet Tag Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248 Ethertype Match Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248 Ethernet Next Protocol Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248 VLAN TPID Configuration B Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249 Ethernet Tag Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249 Ethertype Match Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249 Ethernet Flow Enable Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250 Ethernet Protocol Match Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250 Ethernet Address Match Part 1 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251 Ethernet Address Match Part 2 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252 Ethernet VLAN Tag Range Match Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252 VLAN Tag 1 Match/Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253 Match/Mask For VLAN Tag 2 or I-Tag Match Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253 Ethernet Next Protocol Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254 VLAN TPID Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254 Ethertype Match Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254 Ethernet Flow Enable Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255 Ethernet Protocol Match Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256 VMDS-10509 VSC8572-02 Datasheet Revision 4.2 xxiii Table 409 Table 410 Table 411 Table 412 Table 413 Table 414 Table 415 Table 416 Table 417 Table 418 Table 419 Table 420 Table 421 Table 422 Table 423 Table 424 Table 425 Table 426 Table 427 Table 428 Table 429 Table 430 Table 431 Table 432 Table 433 Table 434 Table 435 Table 436 Table 437 Table 438 Table 439 Table 440 Table 441 Table 442 Table 443 Table 444 Table 445 Table 446 Table 447 Table 448 Table 449 Table 450 Table 451 Table 452 Table 453 Table 454 Table 455 Table 456 Table 457 Table 458 Table 459 Table 460 Table 461 Table 462 Table 463 Table 464 Table 465 Table 466 Table 467 Ethernet Address Match Part 1 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257 Ethernet Address Match Part 2 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257 Ethernet VLAN Tag Range Match Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258 VLAN Tag 1 Match/Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258 Match/Mask For VLAN Tag 2 or I-Tag Match Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258 MPLS Next Protocol Comparator Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259 MPLS Flow Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260 MPLS Label 0 Match Range Lower Value Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260 MPLS Label 0 Match Range Lower Value Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261 MPLS Label 1 Match Range Lower Value Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261 MPLS Label 1 Match Range Lower Value Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261 MPLS Label 2 Match Range Lower Value Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262 MPLS Label 2 Match Range Lower Value Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262 MPLS Label 3 Match Range Lower Value Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263 MPLS Label 3 Match Range Lower Value Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263 PTP/OAM Flow Enable Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264 Upper Half of PTP/OAM Flow Match Field Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264 Lower Half of PTP/OAM Flow Match Field Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264 Upper Half of PTP/OAM Flow Match Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265 Lower Half of PTP/OAM Flow Match Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265 PTP/OAM Range Match Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265 PTP Action Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266 PTP Action Control 2 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267 Zero Field Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268 EGR2_ETH1_NXT_PROTOCOL_A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268 EGR2_ETH1_NXT_PROTOCOL_B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268 EGR2_ETH1_FLOW_CFG (8 instances) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268 EGR2_ETH2_NXT_PROTOCOL_A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269 EGR2_ETH2_FLOW_CFG (8 instances) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269 EGR2_MPLS_NXT_COMPARATOR_A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269 EGR2_MPLS_FLOW_CFG (8 instances) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269 EGR2_PTP_FLOW (6 instances) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270 Ethernet Next Protocol Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271 VLAN TPID Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271 Ethernet Tag Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271 Ethertype Match Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271 Ethernet Next Protocol Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272 VLAN TPID Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272 Ethernet Tag Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272 Ethertype Match Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273 Ethernet Flow Enable Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273 Ethernet Protocol Match Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274 Ethernet Address Match Part 1 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275 Ethernet Address Match Part 2 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275 Ethernet VLAN Tag Range Match Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276 VLAN Tag 1 Match/Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276 Match/Mask For VLAN Tag 2 or I-Tag Match Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277 Ethernet Next Protocol Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277 VLAN TPID Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277 Ethertype Match Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278 Ethernet Flow Enable Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278 Ethernet Protocol Match Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279 Ethernet Address Match Part 1 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280 Ethernet Address Match Part 2 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280 Ethernet VLAN Tag Range Match Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281 VLAN Tag 1 Match/Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281 Match/Mask For VLAN Tag 2 or I-Tag Match Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281 MPLS Next Protocol Comparator Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282 MPLS Flow Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283 VMDS-10509 VSC8572-02 Datasheet Revision 4.2 xxiv Table 468 Table 469 Table 470 Table 471 Table 472 Table 473 Table 474 Table 475 Table 476 Table 477 Table 478 Table 479 Table 480 Table 481 Table 482 Table 483 Table 484 Table 485 Table 486 Table 487 Table 488 Table 489 Table 490 Table 491 Table 492 Table 493 Table 494 Table 495 Table 496 Table 497 Table 498 Table 499 Table 500 Table 501 Table 502 Table 503 Table 504 Table 505 Table 506 Table 507 Table 508 Table 509 Table 510 Table 511 Table 512 Table 513 Table 514 Table 515 Table 516 Table 517 Table 518 Table 519 Table 520 Table 521 Table 522 Table 523 Table 524 Table 525 Table 526 MPLS Label 0 Match Range Lower Value Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283 MPLS Label 0 Match Range Lower Value Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284 MPLS Label 1 Match Range Lower Value Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284 MPLS Label 1 Match Range Lower Value Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284 MPLS Label 2 Match Range Lower Value Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285 MPLS Label 2 Match Range Lower Value Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285 MPLS Label 3 Match Range Lower Value Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286 MPLS Label 3 Match Range Lower Value Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286 PTP/OAM Flow Enable Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287 Upper Half of PTP/OAM Flow Match Field Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287 Lower Half of PTP/OAM Flow Match Field Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287 Upper Half of PTP/OAM Flow Match Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288 Lower Half of PTP/OAM Flow Match Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288 PTP/OAM Range Match Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288 PTP Action Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289 PTP Action Control 2 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290 Zero Field Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291 VDD25 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292 LED and GPIO Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292 Internal Pull-Up or Pull-Down Resistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292 Reference Clock DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293 1588 Reference Clock DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293 SerDes Driver DC Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293 SerDes Receiver DC Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295 Enhanced SerDes Driver DC Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295 Enhanced SerDes Receiver DC Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296 Current Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296 Thermal Diode Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 298 Reference Clock AC Characteristics for QSGMII 125 MHz Differential Clock . . . . . . . . . . . . . . . 298 Recovered Clock AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300 SerDes Outputs AC Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300 SerDes Driver Jitter Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301 SerDes Input AC Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301 SerDes Receiver Jitter Tolerance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301 Enhanced SerDes Outputs AC Specifications, SGMII Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302 Enhanced SerDes Outputs AC Specifications, QSGMII Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 302 Enhanced SerDes Driver Jitter Characteristics, QSGMII Mode . . . . . . . . . . . . . . . . . . . . . . . . . . 303 Enhanced SerDes Input AC Specifications, SGMII Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303 Enhanced SerDes Inputs AC Specifications, QSGMII Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303 Enhanced SerDes Receiver Jitter Tolerance, QSGMII Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 304 Basic Serial LEDs AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 304 Enhanced Serial LEDs AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305 JTAG Interface AC Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305 AC Characteristics for RGMII Uncompensated . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 307 PHY Input (RGMIIn_TXCLK Delay When Register 18E2.[6:4]=011’b) . . . . . . . . . . . . . . . . . . . . . 308 PHY Output (RGMIIn_RXCLK Delay When Register 18E2.[3:1]=100’b) . . . . . . . . . . . . . . . . . . . 309 Serial Management Interface AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 309 Reset Timing Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 310 1588 Timing Specifications AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 311 Serial Timestamp Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 311 Local Time Counter Load/Save Timing Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 312 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 312 Stress Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 312 Pin Type Symbol Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314 1588 Support Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 316 GPIO and 1588 Support Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 317 GPIO and SIGDET Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 317 JTAG Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 317 Miscellaneous Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 318 VMDS-10509 VSC8572-02 Datasheet Revision 4.2 xxv Table 527 Table 528 Table 529 Table 530 Table 531 Table 532 Table 533 Table 534 Power Supply Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RGMII Interface Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SerDes MAC Interface Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SerDes Media Interface Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SMI Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Twisted Pair Interface Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Thermal Resistances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VMDS-10509 VSC8572-02 Datasheet Revision 4.2 319 320 321 322 322 322 326 331 xxvi Revision History 1 Revision History This section describes the changes that were implemented in this document. The changes are listed by revision, starting with the most current publication. 1.1 Revision 4.2 Revision 4.2 was published in April 2019. The following is a summary of the changes in revision 4.2 of this document. • • • • • • • • • • • • • • • • • • • • • • 1.2 The Block Diagram figure was updated. For more information, see Figure 4, page 5. The IEEE 1588 Architecture figure was updated by removing reference to the pps functionality. For more information, see Figure 27, page 26. The IEEE 1588 Device Synchronization section was updated by removing reference to the pps functionality. For more information, see IEEE 1588 Device Synchronization, page 43. The Timestamp Update section was updated by removing reference to the pps functionality. For more information, see Timestamp Update, page 43. The Timestamp Update section was updated by removing reference to the pps functionality. For more information, see Timestamp Update, page 43. The Local Time Counter section was updated by removing reference to the PPS0 functionality and the Local Time Counter Load/Save Timing figure. For more information, see Local Time Counter, page 70. The 1588_PPS_0/1 Mux Control section was deleted. The Register Bits for GPIO Control and Status table was updated by removing reference to the pps functionality. For more information, see Table 31, page 81. The GPIO Control 2, Address 14G (0x0E) table was updated by removing reference to the pps functionality. For more information, see Table 103, page 130. The GPIO Input, Address 15G (0x0F) table was updated by removing reference to the pps functionality. For more information, see Table 104, page 131. The GPIO Output, Address 16G (0x10) table was updated by removing reference to the pps functionality. For more information, see Table 105, page 131. The GPIO Input/Output Configuration, Address 17G (0x11) table was updated by removing reference to the pps functionality. For more information, see Table 106, page 132. The MISC_CFG table was removed. The Registers in IP_1588_LTC table was updated by removing reference to the pps functionality. For more information, see Table 125, page 142. The Fields in LTC_CTRL table was updated by removing reference to the pps functionality. For more information, see Table 143, page 147. The LTC 1 Pulse per Second Width Adjustment section was removed. The IP_1588:MISC_CFG section was removed. The diagrams have been updated by removing references to the pps functionality. For more information, see Figure 96, page 315 and Figure 97, page 316. The 1588 Support Pins table was updated by removing references to the pps functionality. For more information, see Table 522, page 316. The GPIO and 1588 Support Pins table was updated by removing references to the pps functionality. For more information, see Table 523, page 317. The GPIO and SIGDET Pins table was updated by removing references to the pps functionality. For more information, see Table 524, page 317. The 10BASE-T link recovery failures section was updated. For more information, see 10BASE-T link recovery failures, page 327. Revision 4.1 Revision 4.1 was published in May 2018. The following is a summary of the changes in revision 4.1 of this document. • • Configuration procedure steps were clarified. For more information, see Configuration, page 92. The description of bit 10 was updated for register 0. For more information, see Table 40, page 96. VMDS-10509 VSC8572-02 Datasheet Revision 4.2 1 Revision History • • • 1.3 The description of bit 0 was updated for register 22. For more information, see Extended Control and Status, page 105. Serial timestamp interface characteristics were updated. For more information, see Table 517, page 311. Design considerations were updated. For more information, see Design Considerations, page 327. Revision 4.0 Revision 4.0 was published in November 2017. The following is a summary of the changes in revision 4.0 of this document. • • • • • • • • • • • • • • • • 1.4 A note was added about enhanced serial LED mode using the VDD LED drive state. Details about LED pulsing were updated. Information on enabling the serial clock was added. Register bits were designated as “sticky” where appropriate. A footnote was added about the fast link failure interrupt mask. The default for the ring resiliency status bits 4:4 was updated from 00 to 11. The default value for the MAC SerDes clause 37 advertised ability register was updated from 0x0000 to 0x01E0. Footnotes regarding required register clears were added to the SIGDET/GPIO control register. All GPIO input register bits marked as read-only and defaults updated. Global interrupt status register defaults were added. Register 30G changed from reserved to extended revision ID register. Footnotes were added for INGR_BYPASS_ON and EGR_BYPASS_ON 1588 register bits. Current consumption values were updated. Some parameter names and conditions for recovered clock AC characteristics were updated. Product SKUs in the package section were corrected to match the ordering information. Design considerations were removed and new ones added to correctly reflect device functionality. Revision 2.0 Revision 2.0 of this datasheet was published in September 2017. This was the first publication of the document. VMDS-10509 VSC8572-02 Datasheet Revision 4.2 2 Product Overview 2 Product Overview The VSC8572-02 is a low-power, dual-port Gigabit Ethernet transceiver with two SerDes interfaces for dual-port dual media capability. It also includes an integrated dual port two-wire serial multiplexer (MUX) to control SFPs or PoE modules. It has a low electromagnetic interference (EMI) line driver, and integrated line side termination resistors that conserve both power and printed circuit board (PCB) space. The VSC8572-02 includes Microsemi’s IEEE 1588 timestamping solution with encapsulation support. The device also includes dual recovered clock outputs to support Synchronous Ethernet applications. Programmable clock squelch control is included to inhibit undesirable clocks from propagating and to help prevent timing loops. The VSC8572-02 also supports a ring resiliency feature that allows a 1000BASE-T connected PHY port to switch between master and slave timing without having to interrupt the 1000BASE-T link. Using Microsemi’s EcoEthernet v2.0 PHY technology, the VSC8572-02 supports energy efficiency features such as Energy Efficient Ethernet (EEE), ActiPHY link down power savings, and PerfectReach that can adjust power based on the cable length. It also supports fully optimized power consumption in all link speeds. Microsemi's mixed signal and digital signal processing (DSP) architecture is a key operational feature of the VSC8572-02, assuring robust performance even under less-than-favorable environmental conditions. It supports both half-duplex and full-duplex 10BASE-T, 100BASE-TX, and 1000BASE-T communication speeds over Category 5 (Cat5) unshielded twisted pair (UTP) cable at distances greater than 100 m, displaying excellent tolerance to NEXT, FEXT, echo, and other types of ambient environmental and system electronic noise. The device also supports two dual media ports that can support up to two 100BASE-FX, 1000BASE-X fiber, and/or triple-speed copper SFPs. The following illustrations show a high-level, general view of typical VSC8572-02 applications. Figure 1 • Dual Media Application Diagram ½ QSGMII, 2x RGMII, 2x SGMII, or 2x 1000BASE-X MAC ½ QSGMII, 2x RGMII, 2x SGMII MAC, or 2x 1000BASE-X MAC Figure 2 • 1.0 V 2.5 V 2× RJ-45 and Magnetics VSC8572-02 2 ports dual media (fiber or copper) RGMII, SGMII, half QSGMII MAC interface SerDes SCL/SDA 2× SFPs (fiber or copper) Copper Transceiver Application Diagram ½ QSGMII, 2x RGMII, 2x SGMII, or 2x 1000BASE-X MAC ½ QSGMII, 2x RGMII, 2x SGMII MAC, or 2x 1000BASE-X MAC 1.0 V 2.5 V VSC8572-02 2 ports copper media RGMII, SGMII, half QSGMII MAC interface VMDS-10509 VSC8572-02 Datasheet Revision 4.2 2× RJ-45 and Magnetics 3 Product Overview Figure 3 • Fiber Media Transceiver Application Diagram 1.0 V ½ QSGMII, 2x RGMII, 2x SGMII, or 2x 1000BASE-X MAC VSC8572-02 ½ QSGMII, 2x RGMII, 2x SGMII MAC, or 2x 1000BASE-X MAC 2.1 2.5 V 2 ports fiber media RGMII, SGMII, half QSGMII MAC interface 4× 1000BASE-X SFP or 4x 100BASE-FX SFP Key Features This section lists the main features and benefits of the VSC8572-02 device. 2.1.1 Low Power • • • • 2.1.2 Advanced Carrier Ethernet Support • • • • • • 2.1.3 Support for IEEE 1588-2008 timestamping with encapsulation support Recovered clock outputs with programmable clock squelch control and fast link failure indication ( 12); PhyWrite(, 31, 0); The returned average absolute error is in units of 1/2,048 and can be found in the mse variable. PhyWrite(, 31, 0x52b5); PhyWrite(, 16, 0xa3c0); PhyRead(, 16); tmp17 = PhyRead(, 17); tmp18 = PhyRead(, 18); mseA = (tmp18 > 12); mseB = tmp17 & 0x0fff; PhyWrite(, 16, 0xa3c2); PhyRead(, 16); tmp17 = PhyRead(, 17); tmp18 = PhyRead(, 18); mseC = (tmp18 > 12); mseD = tmp17 & 0x0fff; PhyWrite(, 31, 0); The returned average absolute error is in units of 1/2,048 and can be found in the mseA, mseB, mseC, and mseD variables for each twisted pair. 3.20.8 JTAG Boundary Scan The VSC8572-02 supports the test access port (TAP) and boundary scan architecture described in IEEE 1149.1. The device includes an IEEE 1149.1-compliant test interface, referred to as a JTAG TAP interface. The JTAG boundary scan logic on the VSC8572-02, accessed using its TAP interface, consists of a boundary scan register and other logic control blocks. The TAP controller includes all IEEE-required signals (TMS, TCK, TDI, and TDO), in addition to the optional asynchronous reset signal TRST. The following illustration shows the TAP and boundary scan architecture. Important When JTAG is not in use, the TRST pin must be tied to ground with a pull-down resistor for normal operation. VMDS-10509 VSC8572-02 Datasheet Revision 4.2 88 Functional Descriptions Figure 77 • Test Access Port and Boundary Scan Architecture Boundary Scan Register Device Identification Register Bypass Register Control Instruction Register, Instruction Decode Control TDI TMS NTRST MUX, DFF TDO Control Test Access Port Controller Select TDO Enable TCK After a TAP reset, the device identification register is serially connected between TDI and TDO by default. The TAP instruction register is loaded either from a shift register when a new instruction is shifted in, or, if there is no new instruction in the shift register, a default value of 6'b100000 (IDCODE) is loaded. Using this method, there is always a valid code in the instruction register, and the problem of toggling instruction bits during a shift is avoided. Unused codes are mapped to the BYPASS instruction. 3.20.9 JTAG Instruction Codes The VSC8572-02 supports the following instruction codes: Table 33 • JTAG Instruction Codes Instruction Code Description BYPASS The bypass register contains a single shift-register stage and is used to provide a minimum-length serial path (one TCK clock period) between TDI and TDO to bypass the device when no test operation is required. CLAMP Allows the state of the signals driven from the component pins to be determined from the boundary scan register while the bypass register is selected as the serial path between TDI and TDO. While the CLAMP instruction is selected, the signals driven from the component pins do not change. EXTEST Allows tests of the off-chip circuitry and board-level interconnections by sampling input pins and loading data onto output pins. Outputs are driven by the contents of the boundary scan cells, which have to be updated with valid values, with the PRELOAD instruction, prior to the EXTEST instruction. VMDS-10509 VSC8572-02 Datasheet Revision 4.2 89 Functional Descriptions JTAG Instruction Codes (continued) Table 33 • Instruction Code Description HIGHZ Places the component in a state in which all of its system logic outputs are placed in a high-impedance state. In this state, an incircuit test system can drive signals onto the connections normally driven by a component output without incurring a risk of damage to the component. This makes it possible to use a board where not all of the components are compatible with the IEEE 1149.1 standard. IDCODE Provides the version number (bits 31:28), device family ID (bits 27:12), and the manufacturer identity (bits 11:1) to be serially read from the device. SAMPLE/PRELOA Allows a snapshot of inputs and outputs during normal system D operation to be taken and examined. It also allows data values to be loaded into the boundary scan cells prior to the selection of other boundary scan test instructions. USERCODE Provides the version number (bits 31:28), part number (bits 27:12), and the manufacturer identity (bits 11:1) to be serially read from the device. The following tables provide information about the IDCODE and USERCODE binary values stored in the device JTAG registers. Table 34 • IDCODE JTAG Device Identification Register Descriptions Description Device Version Family ID Manufacturing Identity LSB Bit field 31–28 27–12 11–1 0 Binary value 0000 1000 0101 0111 0100 000 0111 0100 1 Table 35 • USERCODE JTAG Device Identification Register Descriptions Description Device Version Model Number Manufacturing Identity LSB Bit field 31–28 27–12 11–1 0 Binary value 0010 1000 0101 0111 0010 000 0111 0100 1 The following table provides information about the location and IEEE compliance of the JTAG instruction codes used in the VSC8572-02. Instructions not explicitly listed in the table are reserved. For more information about these IEEE specifications, visit the IEEE Web site at www.IEEE.org. Table 36 • JTAG Instruction Code IEEE Compliance Instruction Code Selected Register Register Width IEEE 1149.1 EXTEST 6'b000000 Boundary Scan 161 Mandatory SAMPLE/PRELOA D 6'b000001 Boundary Scan 161 Mandatory IDCODE 6'b100000 Device Identification 32 Optional USERCODE 6'b100101 Device Identification 32 Optional CLAMP 6'b000010 Bypass Register 1 Optional HIGHZ 6'b000101 Bypass Register 1 Optional BYPASS 6'b111111 Bypass Register 1 Mandatory VMDS-10509 VSC8572-02 Datasheet Revision 4.2 90 Functional Descriptions 3.20.10 Boundary Scan Register Cell Order All inputs and outputs are observed in the boundary scan register cells. All outputs are additionally driven by the contents of boundary scan register cells. Bidirectional pins have all three related boundary scan register cells: input, output, and control. The complete boundary scan cell order is available as a BSDL file format on the Microsemi Web site at www.Microsemi.com. 3.21 100BASE-FX Halt Code Transmission and Reception The VSC8572-02 device supports transmission and reception of halt code words in 100BASE-FX mode. There are three separate scripts provided to initiate transmission of halt code words, stop transmission of halt code words and detect reception of halt code words. Use the following scripts to implement each of these functions: Sending the HALT codeword: PhyWrite(, 31, 0x52b5); PhyWrite(, 16, 0xac82); reg18 = PhyRead(, 18); reg18 = (reg18 & 0xf0) | 0x0c; PhyWrite(, 18, reg18); PhyWrite(, 17, 0xe739); PhyWrite(, 16, 0x8c82); PhyWrite< , 16, 0xbe80); reg17 = PhyRead(, 17); reg18 = PhyRead(, 18); reg17 = reg17 | 0x0040; PhyWrite(, 18, reg18); PhyWrite(, 17, reg17); PhyWrite(, 16, 0x9e80); PhyWrite(, 31, 0); Stop sending the HALT codeword: PhyWrite(, 31, 0x52b5); PhyWrite< , 16, 0xbe80); reg17 = PhyRead(, 17); reg18 = PhyRead(, 18); reg17 = reg17 & ~0x0040; PhyWrite(, 18, reg18); PhyWrite(, 17, reg17); PhyWrite(, 16, 0x9e80); PhyWrite(, 31, 0); Detecting whether the HALT codeword is being sent by the link partner: long patternset[5] = { 0xce739, 0xe739c, 0x739ce, 0x39ce7, 0x9ce73 }; Turning on the pattern checker: PhyWrite(, 31, 0x52b5); PhyWrite(, 16, 0xbe80); reg18 = PhyRead(, 18); reg17 = PhyRead(, 17); reg17 = reg17 | 4; VMDS-10509 VSC8572-02 Datasheet Revision 4.2 91 Functional Descriptions PhyWrite(, 18, reg18); PhyWrite(, 17, reg17); PhyWrite(, 16, 0x9e80); Sweeping through all five pattern shifts checking for a match: for (i = 0, matchfailed = 1; i < 5 && matchfailed; ++i) { PhyWrite(, 16, 0xac84); reg18 = PhyRead(, 18); reg18 = (reg18 & 0xf0) | (patternset[i] >> 16) PhyWrite(, 18, reg18); PhyWrite(, 17, patternset[i] & 0xffff); PhyWrite(, 16, 0x8c84); PhyWrite(, 16, 0xbe84); // Dummy read to clear latched mismatch PhyWrite(, 16, 0xbe84); // Read pattern check failure status matchfailed = PhyRead(, 17) & 1; // Extract pattern check failure status } Turning off the pattern checker: PhyWrite(, 16, 0xbe80); reg18 = PhyRead(, 18); reg17 = PhyRead(, 17); reg17 = reg17 & ~4; PhyWrite(, 18, reg18); PhyWrite(, 17, reg17); PhyWrite(, 16, 0x9e80); PhyWrite(, 31, 0); HALT_codeword_detected =!matchfailed; 3.22 Configuration The VSC8572-02 can be configured by setting internal memory registers using the management interface. To configure the device, perform the following steps: 1. 2. 3. 4. 5. 6. 7. 8. COMA_MODE active, drive high (optional). Apply power. Apply RefCLK and IEEE 1588 reference clock. Release reset, drive high. Power and clock must be stable before releasing reset. Wait 120 ms minimum. Apply patch from PHY_API (required for production released optional for board testing). Configure register 19G for MAC mode (to access register 19G, register 31 must be 0x10). Read register 19G. Set bits 15:14, MAC configuration as follows: 00: SGMII 01: QSGMII 10: RGMII 11: Reserved Write new register 19G. Set RGMII (optional) Table 37 • Register 18E2 Settings for RGMII Bit Name Setting 6:4 rgmii_skew_tx 000 3:1 rgmii_skew_rx 000 0 rgmii_bit_rev 0 VMDS-10509 VSC8572-02 Datasheet Revision 4.2 92 Functional Descriptions 9. Configure register 18G for MAC on all 4 PHYs write: SGMII: 0x80F0 QSGMII: 0x80E0 RGMII: set 19G[15:14] = 0x10 to set PHY0 and PHY1 MAC to be RGMII 10. Read register 18G until bit 15 equals 0. 11. If Fiber Media on all 4 PHYs configure register 18G by writing: Media 1000BASE-X: 0x8FC1 Media 100BASE-FX: 0x8FD1 12. If Fiber Media read register 18G till bit 15 equals 0. 13. Configure register 23 for MAC and Media mode (to access register 23, register 31 must be 0). Read register 23. Set bits 10:8 as follows: 000: Copper 010: 1000BASE-X 011: 100BASE-FX Write new register 23. 14. Software reset. Read register 0 (to access register 0, register 31 must be 0). Set bit 15 to 1. Write new register 0. 15. Read register 0 until bit 15 equals 0. 16. Release the COMA_MODE pin, drive low (only necessary if COMA_MODE pin is driven high or unconnected). Note: All MAC interfaces must be the same — all QSGMII, RGMII, or SGMII. 3.22.1 Initialization The COMA_MODE pin provides an optional feature that may be used to control when the PHYs become active. The typical usage is to keep the PHYs from becoming active before they have been fully initialized. For more information, see Configuration, page 92. By not being active until after complete initialization keeps links from going up and down. Alternatively the COMA_MODE pin may be connected low (ground) and the PHYs will be fully active once out of reset. VMDS-10509 VSC8572-02 Datasheet Revision 4.2 93 Registers 4 Registers This section provides information about how to configure the VSC8572-02 using its internal memory registers and the management interface. The registers marked reserved and factory test should not be read or written to, because doing so may produce undesired effects. The default value documented for registers is based on the value at reset; however, in some cases, that value may change immediately after reset. The access type for each register is shown using the following abbreviations: • • • • • • RO: Read Only ROCR: Read Only, Clear on Read RO/LH: Read Only, Latch High RO/LL: Read Only, Latch Low R/W: Read and Write RWSC: Read Write Self Clearing The VSC8572-02 uses several different types of registers: • • • • IEEE Clause 22 device registers with addresses from 0 to 31 Three pages of extended registers with addresses from 16E1–30E1, 16E2–30E2, and 16E3–30E3 General-purpose registers with addresses from 0G to 30G IEEE Clause 45 devices registers accessible through the Clause 22 registers 13 and 14 to support IEEE 802.3az-2010 energy efficient Ethernet registers The following illustration shows the relationship between the device registers and their address spaces. Figure 78 • Register Space Diagram 0 1 2 3 . . . 13 14 15 0G 1G 2G 3G . . . . . 15G Clause 45 Registers IEEE 802.3 Standard Registers General Purpose Registers 16 17 18 19 . . . . . 30 Main Registers 31 0x0000 16E1 17E1 18E1 19E1 . . . . . 30E1 Extended Registers 1 0x0001 16E2 17E2 18E2 19E2 . . . . . 30E2 Extended Registers 2 0x0002 16E3 17E3 18E3 19E3 . . . . . 30E3 Extended Registers 3 0x0003 16G 17G 18G 19G . . . . . 30G 16 17 18 0x0010 1588 Registers 0x1588 Reserved Registers—For main registers 16–31, extended registers 16E1–30E1, 16E2–30E2, 16E3– 30E3, and general purpose registers 0G–30G, any bits marked as Reserved should be processed as read-only and their states as undefined. Reserved Bits—In writing to registers with reserved bits, use a read-modify-then-write technique, where the entire register is read but only the intended bits to be changed are modified. Reserved bits cannot be changed and their read state cannot be considered static or unchanging. 4.1 Register and Bit Conventions Registers are referred to by their address and bit number in decimal notation. A range of bits is indicated with a colon. For example, a reference to address 26, bits 15 through 14 is shown as 26.15:14. VMDS-10509 VSC8572-02 Datasheet Revision 4.2 94 Registers A register with an E and a number attached (example 27E1) means it is a register contained within extended register page number 1. A register with a G attached (example 13G) means it is a GPIO page register. Bit numbering follows the IEEE standard with bit 15 being the most significant bit and bit 0 being the least significant bit. 4.2 IEEE 802.3 and Main Registers In the VSC8572-02, the page space of the standard registers consists of the IEEE 802.3 standard registers and the Microsemi standard registers. The following table lists the names of the registers associated with the addresses as specified by IEEE 802.3. Table 38 • IEEE 802.3 Registers Address Name 0 Mode Control 1 Mode Status 2 PHY Identifier 1 3 PHY Identifier 2 4 Autonegotiation Advertisement 5 Autonegotiation Link Partner Ability 6 Autonegotiation Expansion 7 Autonegotiation Next-Page Transmit 8 Autonegotiation Link Partner Next-Page Receive 9 1000BASE-T Control 10 1000BASE-T Status 11–12 Reserved 13 Clause 45 Access Registers from IEEE 802.3 Table 22-6 and 22.24.3.11-12 and Annex 22D 14 Clause 45 Access Registers from IEEE 802.3 Table 22-6 and 22.24.3.11-12 and Annex 22D 15 1000BASE-T Status Extension 1 The following table lists the names of the registers in the main page space of the device. These registers are accessible only when register address 31 is set to 0x0000. Table 39 • Main Registers Address Name 16 100BASE-TX status extension 17 1000BASE-T status extension 2 18 Bypass control 19 Error Counter 1 20 Error Counter 2 21 Error Counter 3 22 Extended control and status 23 Extended PHY control 1 VMDS-10509 VSC8572-02 Datasheet Revision 4.2 95 Registers Table 39 • 4.2.1 Main Registers (continued) Address Name 24 Extended PHY control 2 25 Interrupt mask 26 Interrupt status 27 Reserved 28 Auxiliary control and status 29 LED mode select 30 LED behavior 31 Extended register page access Mode Control The device register at memory address 0 controls several aspects of VSC8572-02 functionality. The following table shows the available bit settings in this register and what they control. Table 40 • Mode Control, Address 0 (0x00) Bit Name Access Description 15 Software reset R/W Self-clearing. Restores all serial management 0 interface (SMI) registers to default state, except for sticky and super-sticky bits. 1: Reset asserted. 0: Reset de-asserted. Wait [X] after setting this bit to initiate another SMI register access. 14 Loopback R/W 1: Loopback enabled. 0 0: Loopback disabled. When loop back is enabled, the device functions at the current speed setting and with the current duplex mode setting (bits 6, 8, and 13 of this register). 13 Forced speed selection LSB R/W Least significant bit. MSB is bit 6. 00: 10 Mbps. 01: 100 Mbps. 10: 1000 Mbps. 11: Reserved. 0 12 Autonegotiation enable R/W 1: Autonegotiation enabled. 0: Autonegotiation disabled. 1 11 Power-down R/W 1: Power-down enabled. 0 10 Isolate R/W 1: Disconnect the MAC-side interface of the device from the rest of the datapath. Traffic entering the PHY from either the MAC-side or media-side interface will terminate inside the PHY. 0 9 Restart autonegotiation R/W Self-clearing bit. 0 1: Restart autonegotiation on media interface. 8 Duplex(1) R/W 1: Full-duplex. 0: Half-duplex. 0 7 Collision test enable R/W 1: Collision test enabled. 0 VMDS-10509 VSC8572-02 Datasheet Revision 4.2 Default 96 Registers Table 40 • Mode Control, Address 0 (0x00) (continued) Bit Name Access Description 6 Forced speed selection MSB R/W Most significant bit. LSB is bit 13.(2) 00: 10 Mbps. 01: 100 Mbps. 10: 1000 Mbps. 11: Reserved. 5 Unidirectional enable R/W When bit 0.12 = 1 or bit 0.8 = 0, this bit is 0 ignored. When bit 0.12 = 0 and bit 0.8 = 1, the behavior is as follows: 1: Enable transmit from media independent interface regardless of whether the PHY has determined that a valid link has been established. 0: Enable transmit from media independent interface only when the PHY has determined that a valid link has been established. Note: This bit is only applicable in 100BASE-FX and 1000BASE-X fiber media modes. 4:0 Reserved 1. 2. 4.2.2 Reserved. Default 10 00000 Half-duplex is not supported when the 1588 unit is operating. Before selecting the 1000 Mbps forced speed mode, manually configure the PHY as master or slave by setting bit 11 in register 9 (1000BASE-T Control). Each time the link drops, the PHY needs to be powered down manually to enable it to link up again using the master/slave setting specified in register 9.11. Mode Status The register at address 1 in the device main registers space allows you to read the currently enabled mode setting. The following table shows possible readouts of this register. Table 41 • Mode Status, Address 1 (0x01) Bit Name Access Description Default 15 100BASE-T4 capability RO 1: 100BASE-T4 capable. 0 14 100BASE-TX FDX capability RO 1: 100BASE-TX FDX capable. 1 13 100BASE-TX HDX capability RO 1: 100BASE-TX HDX capable. 1 12 10BASE-T FDX capability RO 1: 10BASE-T FDX capable. 1 11 10BASE-T HDX capability RO 1: 10BASE-T HDX capable. 1 10 100BASE-T2 FDX capability RO 1: 100BASE-T2 FDX capable. 0 9 100BASE-T2 HDX capability RO 1: 100BASE-T2 HDX capable. 0 8 Extended status enable 1: Extended status information present in register 15. 1 RO VMDS-10509 VSC8572-02 Datasheet Revision 4.2 97 Registers Mode Status, Address 1 (0x01) (continued) Table 41 • Bit Name Access Description Default 7 Unidirectional ability RO 1: PHY able to transmit from media independent interface regardless of whether the PHY has determined that a valid link has been established. 0: PHY able to transmit from media independent interface only when the PHY has determined that a valid link has been established. Note: This bit is only applicable to 100BASE-FX and 1000BASE-X fiber media modes. 1 6 Preamble suppression capability RO 1: MF preamble can be suppressed. 0: MF required. 1 5 Autonegotiation complete RO 1: Autonegotiation complete. 0 4 Remote fault RO Latches high. 1: Far-end fault detected. 0 3 Autonegotiation capability RO 1: Autonegotiation capable. 1 2 Link status RO Latches low. 1: Link is up. 0 1 Jabber detect RO Latches high. 1: Jabber condition detected. 0 0 Extended capability RO 1: Extended register capable. 1 4.2.3 Device Identification All 16 bits in both register 2 and register 3 in the VSC8572-02 are used to provide information associated with aspects of the device identification. The following tables list the expected readouts. Identifier 1, Address 2 (0x02) Table 42 • Bit Name Access Description Default 15:0 Organizationally unique identifier (OUI) RO 0×0007 Table 43 • OUI most significant bits (3:18) Identifier 2, Address 3 (0x03) Bit Name Access Description Default 15:10 OUI RO OUI least significant bits (19:24) 000001 9:4 Microsemi model number RO VSC8572-02 (0xD) 001101 3:0 Device revision number RO See register 30G for the extended 0010 revision identification of this device. VMDS-10509 VSC8572-02 Datasheet Revision 4.2 98 Registers 4.2.4 Autonegotiation Advertisement The bits in address 4 in the main registers space control the VSC8572-02 ability to notify other devices of the status of its autonegotiation feature. The following table shows the available settings and readouts. Device Autonegotiation Advertisement, Address 4 (0x04) Table 44 • Bit Name Access Description Default 15 Next page transmission request R/W 1: Request enabled 0 14 Reserved RO Reserved 0 13 Transmit remote fault R/W 1: Enabled 0 12 Reserved R/W Reserved 0 11 Advertise asymmetric pause R/W 1: Advertises asymmetric pause 0 10 Advertise symmetric pause R/W 1: Advertises symmetric pause 0 9 Advertise100BASE-T4 R/W 1: Advertises 100BASE-T4 0 8 Advertise100BASE-TX FDX R/W 1: Advertise 100BASE-TX FDX 1 7 Advertise100BASE-TX HDX R/W 1: Advertises 100BASE-TX HDX 1 6 Advertise10BASE-T FDX R/W 1: Advertises 10BASE-T FDX 1 5 Advertise10BASE-T HDX R/W 1: Advertises 10BASE-T HDX 4:0 Advertise selector R/W 4.2.5 1 00001 Link Partner Autonegotiation Capability The bits in main register 5 can be used to determine if the Cat5 link partner (LP) used with the VSC8572-02 is compatible with the autonegotiation functionality. Table 45 • Autonegotiation Link Partner Ability, Address 5 (0x05) Bit Name Access Description 15 LP next page transmission request RO 1: Requested 0 14 LP acknowledge RO 1: Acknowledge 0 13 LP remote fault RO 1: Remote fault 0 12 Reserved RO Reserved 0 11 LP advertise asymmetric pause RO 1: Capable of asymmetric pause 0 10 LP advertise symmetric pause RO 1: Capable of symmetric pause 0 9 LP advertise 100BASE-T4 RO 1: Capable of 100BASE-T4 0 8 LP advertise 100BASE-TX FDX RO 1: Capable of 100BASE-TX FDX 0 7 LP advertise 100BASE-TX HDX RO 1: Capable of 100BASE-TX HDX 0 6 LP advertise 10BASE-T FDX RO 1: Capable of 10BASE-T FDX 0 5 LP advertise 10BASE-T HDX RO 1: Capable of 10BASE-T HDX 0 4:0 LP advertise selector RO VMDS-10509 VSC8572-02 Datasheet Revision 4.2 Default 00000 99 Registers 4.2.6 Autonegotiation Expansion The bits in main register 6 work together with those in register 5 to indicate the status of the LP autonegotiation functioning. The following table shows the available settings and readouts. Autonegotiation Expansion, Address 6 (0x06) Table 46 • Bit Name Access Description Default 15:5 Reserved RO Reserved. All zeros 4 Parallel detection fault RO This bit latches high. 1: Parallel detection fault. 0 3 LP next page capable RO 1: LP is next page capable. 0 2 Local PHY next page capable RO 1: Local PHY is next page capable. 1 1 Page received This bit latches low. 1: New page is received. 0 0 LP is autonegotiation capable RO 1: LP is capable of autonegotiation. 0 4.2.7 RO Transmit Autonegotiation Next Page The settings in register 7 in the main registers space provide information about the number of pages in an autonegotiation sequence. The following table shows the settings available. Table 47 • 4.2.8 Autonegotiation Next Page Transmit, Address 7 (0x07) Bit Name Access Description Default 15 Next page R/W 1: More pages follow 0 14 Reserved RO Reserved 0 13 Message page R/W 1: Message page 0: Unformatted page 1 12 Acknowledge 2 R/W 1: Complies with request 0: Cannot comply with request 0 11 Toggle RO 1: Previous transmitted LCW = 0 0: 0 Previous transmitted LCW = 1 10:0 Message/unformatted code R/W 00000000001 Autonegotiation Link Partner Next Page Receive The bits in register 8 of the main register space work together with register 7 to determine certain aspects of the LP autonegotiation. The following table shows the possible readouts. Table 48 • Autonegotiation LP Next Page Receive, Address 8 (0x08) Bit Name Access Description Default 15 LP next page RO 1: More pages follow 0 14 Acknowledge RO 1: LP acknowledge 0 13 LP message page RO 1: Message page 0: Unformatted page 0 12 LP acknowledge 2 RO 1: LP complies with request 0 11 LP toggle RO 1: Previous transmitted LCW = 0 0: Previous transmitted LCW = 1 0 10:0 LP message/unformatted code RO VMDS-10509 VSC8572-02 Datasheet Revision 4.2 All zeros 100 Registers 4.2.9 1000BASE-T Control The VSC8572-02's 1000BASE-T functionality is controlled by the bits in register 9 of the main register space. The following table shows the settings and readouts available. Table 49 • 1000BASE-T Control, Address 9 (0x09) Bit Name Access Description Default 15:13 Transmitter test mode R/W 000: Normal 001: Mode 1: Transmit waveform test 010: Mode 2: Transmit jitter test as master 011: Mode 3: Transmit jitter test as slave 100: Mode 4: Transmitter distortion test 101–111: Reserved 000 12 Master/slave manual configuration R/W 1: Master/slave manual configuration enabled 0 11 Master/slave value R/W This register is only valid when bit 9.12 is set to 1. 1: Configure PHY as master during negotiation 0: Configure PHY as slave during negotiation 0 10 Port type R/W 1: Multi-port device 0: Single-port device 1 9 1000BASE-T FDX capability R/W 1: PHY is 1000BASE-T FDX capable 1 8 1000BASE-T HDX capability R/W 1: PHY is 1000BASE-T HDX capable 1 7:0 Reserved R/W Reserved 0x00 Note: Transmitter test mode (bits 15:13) operates in the manner described in IEEE 802.3 section 40.6.1.1.2. When using any of the transmitter test modes, the automatic media sense feature must be disabled. For more information, see Extended PHY Control Set 1, page 106. 4.2.10 1000BASE-T Status The bits in register 10 of the main register space can be read to obtain the status of the 1000BASE-T communications enabled in the device. The following table shows the readouts. Table 50 • 1000BASE-T Status, Address 10 (0x0A) Bit Name Access Description 15 Master/slave configuration fault RO This bit latches high. 0 1: Master/slave configuration fault detected 0: No master/slave configuration fault detected 14 Master/slave configuration resolution RO 1: Local PHY configuration resolved to master 1 0: Local PHY configuration resolved to slave 13 Local receiver status RO 1: Local receiver is operating normally 0 12 Remote receiver status RO 1: Remote receiver OK 0 11 LP 1000BASE-T FDX capability RO 1: LP 1000BASE-T FDX capable 0 10 LP 1000BASE-T HDX capability RO 1: LP 1000BASE-T HDX capable 0 9:8 Reserved RO Reserved 00 VMDS-10509 VSC8572-02 Datasheet Revision 4.2 Default 101 Registers Table 50 • 1000BASE-T Status, Address 10 (0x0A) (continued) Bit Name Access Description Default 7:0 Idle error count RO 0x00 4.2.11 Self-clearing register MMD Access Control Register The bits in register 13 of the main register space are a window to the EEE registers as defined in IEEE 802.3az-2010 Clause 45. Table 51 • 4.2.12 MMD EEE Access, Address 13 (0x0D) Bit Name Access Description 15:14 Function R/W 13:5 Reserved R/W Reserved 4:0 DVAD Device address as defined in IEEE 802.3az-2010 table 45–1 R/W 00: Address 01: Data, no post increment 10: Data, post increment for read and write 11: Data, post increment for write only MMD Address or Data Register The bits in register 14 of the main register space are a window to the EEE registers as defined in IEEE 802.3az-2010 Clause 45. Table 52 • 4.2.13 MMD Address or Data Register, Address 14 (0x0E) Bit Name Access Description 15:0 Register Address/Data R/W When register 13.15:14 = 2'b00, address of register of the device that is specified by 13.4:0. Otherwise, the data to be written to or read from the register. 1000BASE-T Status Extension 1 Register 15 provides additional information about the operation of the device 1000BASE-T communications. The following table shows the readouts available. Table 53 • 1000BASE-T Status Extension 1, Address 15 (0x0F) Bit Name Access Description 15 1000BASE-X FDX capability RO 1: PHY is 1000BASE-X FDX capable 1 14 1000BASE-X HDX capability RO 1: PHY is 1000BASE-X HDX capable 1 13 1000BASE-T FDX capability RO 1: PHY is 1000BASE-T FDX capable 1 12 1000BASE-T HDX capability RO 1: PHY is 1000BASE-T HDX capable 1 11:0 Reserved Reserved RO VMDS-10509 VSC8572-02 Datasheet Revision 4.2 Default 0x000 102 Registers 4.2.14 100BASE-TX/FX Status Extension Register 16 in the main registers page space of the VSC8572-02 provides additional information about the status of the device's 100BASE-TX/100BASE-FX operation. Table 54 • 100BASE-TX/FX Status Extension, Address 16 (0x10) Bit Name Access Description Default 15 100BASE-TX/FX Descrambler RO 1: Descrambler locked 0 14 100BASE-TX/FX lock error RO Self-clearing bit. 1: Lock error detected 0 13 100BASE-TX/FX disconnect state RO Self-clearing bit. 1: PHY 100BASE-TX link disconnect detected 0 12 100BASE-TX/FX current link status RO 1: PHY 100BASE-TX link active 0 11 100BASE-TX/FX receive error RO Self-clearing bit. 1: Receive error detected 0 10 100BASE-TX/FX transmit error RO Self-clearing bit. 1: Transmit error detected 0 9 100BASE-TX/FX SSD error RO Self-clearing bit. 1: Start-of-stream delimiter error detected 0 8 100BASE-TX/FX ESD error RO Self-clearing bit. 1: End-of-stream delimiter error detected 0 7:0 Reserved RO Reserved 4.2.15 1000BASE-T Status Extension 2 The second status extension register is at address 17 in the device main registers space. It provides information about another set of parameters associated with 1000BASE-T communications. For information about the first status extension register, see Table 53, page 102. Table 55 • 1000BASE-T Status Extension 2, Address 17 (0x11) Bit Name Access Description Default 15 1000BASE-T descrambler RO 1: Descrambler locked. 0 14 1000BASE-T lock error RO Self-clearing bit. 1: Lock error detected 0 13 1000BASE-T disconnect state RO Self-clearing bit. 1: PHY 1000BASE-T link disconnect detected 0 12 1000BASE-T current link status RO 1: PHY 1000BASE-T link active 0 11 1000BASE-T receive error RO Self-clearing bit. 1: Receive error detected 0 10 1000BASE-T transmit error RO Self-clearing bit. 1: Transmit error detected 0 9 1000BASE-T SSD error RO Self-clearing bit. 0 1: Start-of-stream delimiter error detected VMDS-10509 VSC8572-02 Datasheet Revision 4.2 103 Registers Table 55 • 1000BASE-T Status Extension 2, Address 17 (0x11) (continued) Bit Name Access Description 8 1000BASE-T ESD error RO 7 1000BASE-T carrier extension RO error Self-clearing bit. 1: Carrier extension error detected 0 6 Non-compliant BCM5400 detected RO 1: Non-compliant BCM5400 link partner detected 0 5 MDI crossover error RO 1: MDI crossover error was detected 0 4:0 Reserved RO Reserved 4.2.16 Default Self-clearing bit. 0 1: End-of-stream delimiter error detected Bypass Control The bits in this register control aspects of functionality in effect when the device is disabled for the purpose of traffic bypass. The following table shows the settings available. Table 56 • Bypass Control, Address 18 (0x12) Bit Name Access Description Default 15 Transmit disable R/W 1: PHY transmitter disabled 0 14 4B5B encoder/decoder R/W 1: Bypass 4B/5B encoder/decoder 0 13 Scrambler R/W 1: Bypass scrambler 0 12 Descrambler R/W 1: Bypass descrambler 0 11 PCS receive R/W 1: Bypass PCS receiver 0 10 PCS transmit R/W 1: Bypass PCS transmit 0 9 LFI timer R/W 1: Bypass Link Fail Inhibit (LFI) timer 0 8 Reserved RO Reserved 7 HP Auto-MDIX at forced 10/100 R/W Sticky bit. 1 1: Disable HP Auto-MDIX at forced 10/100 speeds 6 Non-compliant BCM5400 detect disable R/W Sticky bit. 1: Disable non-compliant BCM5400 detection 0 5 Disable pair swap correction (HP Auto-MDIX when autonegotiation enabled) R/W Sticky bit. 1: Disable the automatic pair swap correction 0 4 Disable polarity correction R/W Sticky bit. 1: Disable polarity inversion correction on each subchannel 0 3 Parallel detect control R/W Sticky bit. 1: Do not ignore advertised ability 0: Ignore advertised ability 1 2 Pulse shaping filter R/W 1: Disable pulse shaping filter 0 1 Disable automatic 1000BASE-T next page exchange R/W Sticky bit. 1: Disable automatic 1000BASE T next page exchanges 0 0 Reserved RO Reserved VMDS-10509 VSC8572-02 Datasheet Revision 4.2 104 Registers Note: If bit 18.1 is set to 1 in this register, automatic exchange of next pages is disabled, and control is returned to the user through the SMI after the base page is exchanged. The user then must send the correct sequence of next pages to the link partner, determine the common capabilities, and force the device into the correct configuration following the successful exchange of pages. 4.2.17 Error Counter 1 The bits in register 19 provide an error counter. The following table shows the settings available. Error Counter 1, Address 19 (0x13) Table 57 • Bit Name Access Description 15:8 Reserved RO Reserved. 7:0 100/1000 receive error counter RO 8-bit counter that saturates when it reaches 255. These bits are self-clearing when read. 4.2.18 Default 0x00 Error Counter 2 The bits in register 20 provide an error counter. The following table shows the settings available. Error Counter 2, Address 20 (0x14) Table 58 • Bit Name Access Description 15:8 Reserved RO Reserved. 7:0 100/1000 false carrier counter RO 8-bit counter that saturates when it reaches 255. These bits are self-clearing when read. 4.2.19 Default 0x00 Error Counter 3 The bits in register 21 provide an error counter. The following table shows the settings available. Table 59 • Error Counter 3, Address 21 (0x15) Bit Name Access Description 15:8 Reserved RO Reserved. 7:0 Copper media link disconnect counter RO 8-bit counter that saturates when it reaches 255. These bits are self-clearing when read. 4.2.20 Default 0x00 Extended Control and Status The bits in register 22 provide additional device control and readouts. The following table shows the settings available. Table 60 • Extended Control and Status, Address 22 (0x16) Bit Name Access Description Default 15 Force 10BASE-T link high R/W Sticky bit. 1: Bypass link integrity test 0: Enable link integrity test 0 14 Jabber detect disable R/W Sticky bit. 1: Disable jabber detect 0 13 Disable 10BASE-T echo R/W Sticky bit. 1: Disable 10BASE-T echo 1 12 Disable SQE mode R/W Sticky bit. 1: Disable SQE mode 1 VMDS-10509 VSC8572-02 Datasheet Revision 4.2 105 Registers Table 60 • Extended Control and Status, Address 22 (0x16) (continued) Bit Name Access Description Default 11:10 10BASE-T squelch control R/W Sticky bit. 00: Normal squelch 01: Low squelch 10: High squelch 11: Reserved 00 9 Sticky reset enable R/W Super-sticky bit. 1: Enabled 1 8 EOF Error RO This bit is self-clearing. 1: EOF error detected 0 7 10BASE-T disconnect state RO This bit is self-clearing. 1: 10BASE-T link disconnect detected 0 6 10BASE-T link status RO 1: 10BASE-T link active 0 5:1 Reserved RO Reserved 0 SMI broadcast write R/W Sticky bit. 1: Enabled 0 The following information applies to the extended control and status bits: • • • • 4.2.21 When bit 22.15 is set, the link integrity state machine is bypassed and the PHY is forced into a link pass status. When bits 22.11:10 are set to 00, the squelch threshold levels are based on the IEEE standard for 10BASE-T. When set to 01, the squelch level is decreased, which can improve the bit error rate performance on long loops. When set to 10, the squelch level is increased and can improve the bit error rate in high-noise environments. When bit 22.9 is set, all sticky register bits retain their values during a software reset. Clearing this bit causes all sticky register bits to change to their default values upon software reset. Super-sticky bits retain their values upon software reset regardless of the setting of bit 22.9. When bit 22.0 is set, if a write to any PHY register (registers 0–31, including extended registers), the same write is broadcast to all PHYs. For example, if bit 22.0 is set to 1 and a write to PHY0 is executed (register 0 is set to 0x1040), all PHYs' register 0s are set to 0x1040. This bit must be disabled before performing a software reset of any PHY port (see register 0 bit 15, Table 40, page 96). Disabling this bit restores normal PHY write operation. Reads are still possible when this bit is set, but the value that is read corresponds only to the particular PHY being addressed. Extended PHY Control Set 1 The following table shows the settings available. Table 61 • Extended PHY Control 1, Address 23 (0x17) Bit Name Access Description Default 15:13 Reserved R/W 0 12 MAC interface mode R/W Super-sticky bit. 0 0: RGMII/SGMII 1: 1000BASE-X. Note: Register 19G.15:14 must be = 00 for this selection to be valid. 11 AMS preference Super-sticky bit. 1: Cat5 copper preferred. 0: SerDes fiber/SFP preferred. R/W Reserved VMDS-10509 VSC8572-02 Datasheet Revision 4.2 0 106 Registers Table 61 • Extended PHY Control 1, Address 23 (0x17) (continued) Bit Name Access Description Default 10:8 Media operating mode R/W Super-sticky bits. 000 000: Cat5 copper only. 001: SerDes fiber/SFP protocol transfer mode only. 010: 1000BASE-X fiber/SFP media only with autonegotiation performed by the PHY. 011: 100BASE-FX fiber/SFP on the fiber media pins only. 101: Automatic media sense (AMS) with Cat5 media or SerDes fiber/SFP protocol transfer mode. 110: AMS with Cat5 media or 1000BASE-X fiber/SFP media with autonegotiation performed by PHY. 111: AMS with Cat5 media or 100BASE-FX fiber/SFP media. 100: AMS. 7:6 Force AMS override R/W Sticky bits. 00: Normal AMS selection 01: Force AMS to select SerDes media only 10: Force AMS to select copper media only 11: Reserved 5:4 Reserved RO Reserved. 3 Far-end loopback mode R/W 1: Enabled. 2:0 Reserved RO Reserved. 00 0 Note: After configuring bits 13:8 of the extended PHY control register set 1, a software reset (register 0, bit 15) must be written to change the device operating mode. On read, these bits only indicate the actual operating mode and not the pending operating mode setting before a software reset has taken place. 4.2.22 Extended PHY Control Set 2 The second set of extended controls is located in register 24 in the main register space for the device. The following table shows the settings and readouts available. Table 62 • Extended PHY Control 2, Address 24 (0x18) Bit Name Access Description Default 15:13 100BASE-TX edge rate control R/W Sticky bit. 011: +5 edge rate (slowest) 010: +4 edge rate 001: +3 edge rate 000: +2 edge rate 111: +1 edge rate 110: Default edge rate 101: –1 edge rate 100: –2 edge rate (fastest) 001 12 PICMG 2.16 reduced R/W power mode Sticky bit. 1: Enabled 0 11:6 Reserved Reserved RO VMDS-10509 VSC8572-02 Datasheet Revision 4.2 107 Registers Table 62 • Extended PHY Control 2, Address 24 (0x18) (continued) Bit Name Access Description Default 5:4 Jumbo packet mode R/W Sticky bit. 00: Normal IEEE 1.5 kB packet length 01: 9 kB jumbo packet length (12 kB with 60 ppm or better reference clock) 10: 12 kB jumbo packet length (16 kB with 70 ppm or better reference clock) 11: Reserved 00 3:1 Reserved RO Reserved 0 1000BASE-T connector loopback R/W 1: Enabled 0 Note: When bits 5:4 are set to jumbo packet mode, the default maximum packet values are based on 100 ppm driven reference clock to the device. Controlling the ppm offset between the MAC and the PHY as specified in the bit description results in a higher jumbo packet length. 4.2.23 Interrupt Mask These bits control the device interrupt mask. The following table shows the settings available. Table 63 • Interrupt Mask, Address 25 (0x19) Bit Name Access Description Default 15 MDINT interrupt status enable R/W Sticky bit. 1: Enabled. 0 14 Speed state change mask R/W Sticky bit. 1: Enabled. 0 13 Link state change mask R/W Sticky bit. 1: Enabled. 0 12 FDX state change mask R/W Sticky bit. 1: Enabled. 0 11 Autonegotiation error mask R/W Sticky bit. 1: Enabled. 0 10 Autonegotiation complete mask R/W Sticky bit. 1: Enabled. 0 9 Inline powered device (PoE) detect mask R/W Sticky bit. 1: Enabled. 0 8 Symbol error interrupt mask R/W Sticky bit. 1: Enabled. 0 7 Fast link failure interrupt mask(1) R/W Sticky bit. 1: Enabled. 0 6:5 Reserved R/W 4 AMS media changed mask(2) R/W Sticky bit. 1: Enabled. 0 3 False carrier interrupt mask R/W Sticky bit. 1: Enabled. 0 2 Link speed downshift detect mask R/W Sticky bit. 1: Enabled. 0 1 Master/Slave resolution error mask R/W Sticky bit. 1: Enabled. 0 0 RX_ER interrupt mask R/W Sticky bit. 1: Enabled. 0 1. 2. 0 The interrupt is only valid for 100 Mbps and 1000 Mbps speeds. Notification at 10 Mbps speed requires use of the FASTLINK-FAIL pin. If hardware interrupts are not used, the mask can still be set and the status polled for changes. Note: When bit 25.15 is set, the MDINT pin is enabled. When enabled, the state of this pin reflects the state of bit 26.15. Clearing this bit only inhibits the MDINT pin from being asserted. Also, before enabling this bit, read register 26 to clear any previously inactive interrupts pending that will cause bit 25.15 to be set. VMDS-10509 VSC8572-02 Datasheet Revision 4.2 108 Registers 4.2.24 Interrupt Status The status of interrupts already written to the device is available for reading from register 26 in the main registers space. The following table shows the expected readouts. Table 64 • Interrupt Status, Address 26 (0x1A) Bit Name Access Description Default 15 Interrupt status RO Self-clearing bit. 1: Interrupt pending. 0 14 Speed state change status RO Self-clearing bit. 1: Interrupt pending. 0 13 Link state change status RO Self-clearing bit. 1: Interrupt pending. 0 12 FDX state change status RO Self-clearing bit. 1: Interrupt pending. 0 11 Autonegotiation error status RO Self-clearing bit. 1: Interrupt pending. 0 10 Autonegotiation complete status RO Self-clearing bit. 1: Interrupt pending. 0 9 Inline powered device detect status RO Self-clearing bit. 1: Interrupt pending. 0 8 Symbol error status RO Self-clearing bit. 1: Interrupt pending. 0 7 Fast link failure detect status RO Self-clearing bit. 1: Interrupt pending. 0 6:5 Reserved RO 4 AMS media changed 3 mask(1) 0 RO Self-clearing bit. 1: Interrupt pending. 0 False carrier interrupt status RO Self-clearing bit. 1: Interrupt pending. 0 2 Link speed downshift detect status RO Self-clearing bit. 1: Interrupt pending. 0 1 Master/Slave resolution error status RO Self-clearing bit. 1: Interrupt pending. 0 0 RX_ER interrupt status RO Self-clearing bit. 1: Interrupt pending. 0 1. If hardware interrupts are not used, the mask can still be set and the status polled for changes. The following information applies to the interrupt status bits: • • • • 4.2.25 All set bits in this register are cleared after being read (self-clearing). If bit 26.15 is set, the cause of the interrupt can be read by reading bits 26.14:0. For bits 26.14 and 26.12, bit 0.12 must be set for this interrupt to assert. For bit 26.2, bits 4.8:5 must be set for this interrupt to assert. For bit 26.0, this interrupt will not occur when RX_ER is used for carrier-extension decoding of a link partner's data transmission. Device Auxiliary Control and Status Register 28 provides control and status information for several device functions not controlled or monitored by other device registers. The following table shows the settings available and the expected readouts. Table 65 • Auxiliary Control and Status, Address 28 (0x1C) Bit Name Access Description Default 15 Autonegotiation complete RO Duplicate of bit 1.5 0 14 Autonegotiation disabled RO Inverted duplicate of bit 0.12 0 131 HP Auto-MDIX crossover indication RO 1: HP Auto-MDIX crossover performed internally 0 VMDS-10509 VSC8572-02 Datasheet Revision 4.2 109 Registers Table 65 • Bit Name Access Description Default 12 CD pair swap RO 1: CD pairs are swapped 0 11 A polarity inversion RO 1: Polarity swap on pair A 0 10 B polarity inversion RO 1: Polarity swap on pair B 0 9 C polarity inversion RO 1: Polarity swap on pair C 0 8 D polarity inversion RO 1: Polarity swap on pair D 0 7 ActiPHY link status time-out R/W control [1] Sticky bit. Bits 7 and 2 are part of the 0 ActiPHY Link Status time-out control. Bit 7 is the MSB. 00: 2.3 seconds 01: 3.3 seconds 10: 4.3 seconds 11: 5.3 seconds 6 ActiPHY mode enable R/W Sticky bit. 1: Enabled 0 5 FDX status RO 1: Full-duplex 0: Half-duplex 00 4:3 Speed status RO 00: Speed is 10BASE-T 0 01: Speed is 100BASE-TX or 100BASE-FX 10: Speed is 1000BASE-T or 1000BASE-X 11: Reserved 2 ActiPHY link status time-out R/W control [0] Sticky bit. Bits 7 and 2 are part of the 1 ActiPHY Link Status time-out control. Bit 7 is the MSB. 00: 2.3 seconds 01: 3.3 seconds 10: 4.3 seconds 11: 5.3 seconds 1:0 Media mode status 00: No media selected 01: Copper media selected 10: SerDes (Fiber) media selected 11: Reserved 1. 4.2.26 Auxiliary Control and Status, Address 28 (0x1C) (continued) RO 00 In 1000BT mode, if Force MDI crossover is performed while link is up, the 1000BT link must be re-negotiated in order for this bit to reflect the actual Auto-MDIX setting. LED Mode Select The device LED outputs are controlled using the bits in register 29 of the main register space. The following table shows the information needed to access the functionality of each of the outputs. For more information about LED modes, see Table 28, page 76. For information about enabling the extended LED mode bits in Register 19E1 bits 13 to 12, see Table 29, page 77. Table 66 • LED Mode Select, Address 29 (0x1D) Bit Name Access Description 15:12 LED3 mode select R/W Sticky bit. Select from LED modes 0–15. 1000 11:8 LED2 mode select R/W Sticky bit. Select from LED modes 0–15. 0000 7:4 LED1 mode select R/W Sticky bit. Select from LED modes 0–15. 0010 3:0 LED0 mode select R/W Sticky bit. Select from LED modes 0–15. 0001 VMDS-10509 VSC8572-02 Datasheet Revision 4.2 Default 110 Registers 4.2.27 LED Behavior The bits in register 30 control and enable you to read the status of the pulse or blink rate of the device LEDs. The following table shows the settings you can write to the register or read from the register. Table 67 • LED Behavior, Address 30 (0x1E) Bit Name Access Description 15 Copper and fiber R/W LED combine disable Sticky bit 0: Combine enabled (Copper/Fiber on link/linkXXXX/activity LED) 1: Disable combination (link/linkXXXX/activity LED; indicates copper only) 14 Activity output select R/W 0 Sticky bit 1: Activity LED becomes TX_Activity and fiber activity LED becomes RX_Activity 0: TX and RX activity both displayed on activity LEDs 13 Reserved RO Reserved 12 LED pulsing enable R/W Sticky bit 0 0: Normal operation 1: LEDs pulse with a 5 kHz, programmable duty cycle when active 11:10 LED blink/pulsestretch rate R/W Sticky bit 00: 2.5 Hz blink rate/400 ms pulse-stretch 01: 5 Hz blink rate/200 ms pulse-stretch 10: 10 Hz blink rate/100 ms pulse-stretch 11: 20 Hz blink rate/50 ms pulse-stretch The blink rate selection for PHY0 globally sets the rate used for all LED pins on all PHY ports 9 Reserved RO Reserved 8 LED3 pulsestretch/blink select R/W Sticky bit 1: Pulse-stretch 0: Blink 0 7 LED2 pulsestretch/blink select R/W Sticky bit 1: Pulse-stretch 0: Blink 0 6 LED1 pulsestretch/blink select R/W Sticky bit 1: Pulse-stretch 0: Blink 0 5 LED0 pulsestretch/blink select R/W Sticky bit 1: Pulse-stretch 0: Blink 0 4:2 Reserved RO Reserved 3 LED3 combine feature disable R/W Sticky bit 0: Combine enabled (link/activity, duplex/collision) 1: Disable combination (link only, duplex only) 0 2 LED2 combine feature disable R/W Sticky bit 0: Combine enabled (link/activity, duplex/collision) 1: Disable combination (link only, duplex only) 0 VMDS-10509 VSC8572-02 Datasheet Revision 4.2 Default 0 01 111 Registers Table 67 • LED Behavior, Address 30 (0x1E) (continued) Bit Name Access Description Default 1 LED1 combine feature disable R/W Sticky bit 0: Combine enabled (link/activity, duplex/collision) 1: Disable combination (link only, duplex only) 0 0 LED0 combine feature disable R/W Sticky bit 0: Combine enabled (link/activity, duplex/collision) 1: Disable combination (link only, duplex only) 0 Note: Bits 30.11:10 are active only in port 0 and affect the behavior of LEDs for all the ports. 4.2.28 Extended Page Access To provide functionality beyond the IEEE 802.3-specified registers and main device registers, the VSC8572-02 includes an extended set of registers that provide an additional 15 register spaces. The register at address 31 controls the access to the extended registers for the VSC8572-02. Accessing the GPIO page register space is similar to accessing the extended page registers. The following table shows the settings available. Table 68 • 4.3 Extended/GPIO Register Page Access, Address 31 (0x1F) Bit Name Access Description 15:0 Extended/GPIO page R/W register access Default 0x0000: Register 16–30 accesses main register 0x0000 space. Writing 0x0000 to register 31 restores the main register access. 0x0001: Registers 16–30 access extended register space 1 0x0002: Registers 16–30 access extended register space 2 0x0003: Registers 16–30 access extended register space 3 0x0010: Registers 0–30 access GPIO register space 0x1588: Registers 16-18 1588 registers Extended Page 1 Registers To access the extended page 1 registers (16E1–30E1), enable extended register access by writing 0x0001 to register 31. Writing 0x0000 to register 31 restores the main register access. When extended page 1 register access is enabled, reads and writes to registers 16–30 affect the extended registers 16E1–30E1 instead of those same registers in the IEEE-specified register space. Registers 0–15 are not affected by the state of the extended page register access. Table 69 • Extended Registers Page 1 Space Address Name 16E1 SerDes Media Control 17E1 Reserved 18E1 Cu Media CRC good counter 19E1 Extended mode and SIGDET control 20E1 Extended PHY control 3 (ActiPHY) VMDS-10509 VSC8572-02 Datasheet Revision 4.2 112 Registers Table 69 • Extended Registers Page 1 Space (continued) Address Name 21E1–22E1 Reserved 23E1 Extended PHY control 4 (PoE and CRC error counter) 24E1 VeriPHY 1 25E1 VeriPHY 2 26E1 VeriPHY 3 27E1–28E1 Reserved 4.3.1 29E1 Ethernet packet generator (EPG) 1 30E1 EPG 2 SerDes Media Control Register 16E1 controls some functions of the SerDes media interface on ports 0–3. These settings are only valid for those ports. The following table shows the setting available in this register. Table 70 • SerDes Media Control, Address 16E1 (0x10) Bit Name Access Description Default 15:14 Transmit remote fault R/W Remote fault indication sent to link partner (LP) 00 13:12 Link partner (LP) remote fault RO Remote fault bits sent by LP during autonegotiation 00 11:10 Reserved RO Reserved 9 Allow 1000BASE-X link-up R/W Sticky bit. 1 1: Allow 1000BASE-X fiber media link-up capability 0: Suppress 1000BASE-X fiber media link-up capability 8 Allow 100BASE-FX link-up R/W Sticky bit. 1 1: Allow 100BASE-FX fiber media link-up capability 0: Suppress 100BASE-FX fiber media link-up capability 7 Reserved RO Reserved 6 Far end fault detected in 100BASE-FX RO Self-clearing bit. 0 1: Far end fault in 100BASE-FX detected 5:0 Reserved RO Reserved 4.3.2 Cu Media CRC Good Counter Register 18E1 makes it possible to read the contents of the CRC good counter for packets that are received on the Cu media interface; the number of CRC routines that have executed successfully. The following table shows the expected readouts. Table 71 • Cu Media CRC Good Counter, Address 18E1 (0x12) Bit Name Access Description Default 15 Packet since last read RO 0 Self-clearing bit. 1: Packet received since last read. VMDS-10509 VSC8572-02 Datasheet Revision 4.2 113 Registers Cu Media CRC Good Counter, Address 18E1 (0x12) (continued) Table 71 • Bit Name Access Description 14 Reserved RO Reserved. 13:0 Cu Media CRC good counter contents RO Self-clearing bit. Counter containing the number of packets with valid CRCs modulo 10,000; this counter does not saturate and will roll over to zero on the next good packet received after 9,999. 4.3.3 Default 0x000 Extended Mode Control Register 19E1 controls the extended LED and other chip modes. The following table shows the settings available. Table 72 • Extended Mode Control, Address 19E1 (0x13) Bit Name Access Description Default 15 LED3 Extended Mode R/W Sticky bit. 1: See Extended LED Modes, page 77 0 14 LED2 Extended Mode R/W Sticky bit. 1: See Extended LED Modes, page 77 0 13 LED1 Extended Mode R/W Sticky bit. 1: See Extended LED Modes, page 77 0 12 LED0 Extended Mode R/W Sticky bit. 1: See Extended LED Modes, page 77 0 11 LED Reset Blink Suppress R/W Sticky bit. 0 1: Blink LEDs after COMA_MODE is de-asserted 0: Suppress LED blink after COMA_MODE is de-asserted 10:5 Reserved RO Reserved 0 4 Fast link failure R/W Sticky bit. Enable fast link failure pin. This must be done from PHY0 only. 1: Enabled 0: Disabled (GPIO9 pin becomes general purpose I/O) 0 3:2 Force MDI crossover R/W Sticky bits. 00: Normal HP Auto-MDIX operation 01: Reserved 10: Copper media forced to MDI 11: Copper media forced MDI-X 00 1 Reserved RO Reserved 0 GPIO[1:0]/SIGDET[1:0] pin R/W polarity Sticky bit. 1: Active low 0: Active high VMDS-10509 VSC8572-02 Datasheet Revision 4.2 0 114 Registers 4.3.4 ActiPHY Control Register 20E1 controls the device ActiPHY sleep timer, its wake-up timer, and its link speed downshifting feature. The following table shows the settings available. Table 73 • Extended PHY Control 3, Address 20E1 (0x14) Bit Name Access Description Default 15 Disable carrier extension R/W 1: Disable carrier extension in RGMII/1000BASE-T copper links 1 14:13 ActiPHY sleep timer R/W Sticky bit. 00: 1 second 01: 2 seconds 10: 3 seconds 11: 4 seconds 01 12:11 ActiPHY wake-up timer R/W Sticky bit. 00: 160 ms 01: 400 ms 10: 800 ms 11: 2 seconds 00 10 Reserved RO Reserved 9 PHY address reversal R/W Sticky bit. Reverse PHY address Enabling causes physical PHY 0 to have address of 3, PHY 1 address of 2, PHY 2 address of 1, and PHY 3 address of 0. Changing this bit to 1 should initially be done from PHY 0 and changing to 0 from PHY3 1: Enabled 0: Disabled 8 Reserved RO Valid only on PHY0 7:6 Media mode status RO 00: No media selected 01: Copper media selected 10: SerDes media selected 11: Reserved 5 Enable 10BASE-T no preamble mode R/W Sticky bit. 0 1: 10BASE-T will assert RX_DV indication when data is presented to the receiver even without a preamble preceding it 4 Enable link speed autodownshift feature R/W Sticky bit. 1: Enable auto link speed downshift from 1000BASE-T 0 3:2 Link speed auto downshift R/W control Sticky bits. 00: Downshift after 2 failed 1000BASE-T autonegotiation attempts 01: Downshift after 3 failed 1000BASE-T autonegotiation attempts 10: Downshift after 4 failed 1000BASE-T autonegotiation attempts 11: Downshift after 5 failed 1000BASE-T autonegotiation attempts 01 1 Link speed auto downshift RO status 0: No downshift 1: Downshift is required or has occurred 0 VMDS-10509 VSC8572-02 Datasheet Revision 4.2 0 00 115 Registers Table 73 • Extended PHY Control 3, Address 20E1 (0x14) (continued) Bit Name Access Description 0 Reserved RO 4.3.5 Default Reserved PoE and Miscellaneous Functionality The register at address 23E1 controls various aspects of inline powering and the CRC error counter in the VSC8572-02. Table 74 • Extended PHY Control 4, Address 23E1 (0x17) Bit Name Access Description Default 15:11 PHY address RO PHY address; latched on reset 10 Inline powered device detection R/W Sticky bit. 1: Enabled 0 9:8 Inline powered device detection status RO Only valid when bit 10 is set. 00: Searching for devices 01: Device found; requires inline power 10: Device found; does not require inline power 11: Reserved 00 7:0 Cu Media CRC error counter RO Self-clearing bit RC error counter for packets received on the Cu media interface. The value saturates at 0xFF and subsequently clears when read and restarts count.0x00 4.3.6 VeriPHY Control 1 Register 24E1 in the extended register space provides control over the device VeriPHY diagnostics features. There are three separate VeriPHY control registers. The following table shows the settings available and describes the expected readouts. Table 75 • VeriPHY Control Register 1, Address 24E1 (0x18) Bit Name Access Description Default 15 VeriPHY trigger R/W Self-clearing bit. 1: Triggers the VeriPHY algorithm and clears when VeriPHY has completed. Settings in registers 24E–26E become valid after this bit clears. 0 14 VeriPHY valid RO 1: VeriPHY results in registers 24E–26E are valid. 0 13:8 Pair A (1, 2) distance RO Loop length or distance to anomaly for pair A (1, 0x00 2). 7:6 Reserved RO Reserved. 5:0 Pair B (3, 6) distance RO Loop length or distance to anomaly for pair B (3, 0x00 6). Note: The resolution of the 6-bit length field is 3 meters. VMDS-10509 VSC8572-02 Datasheet Revision 4.2 116 Registers 4.3.7 VeriPHY Control 2 The register at address 25E1 consists of the second of the three device registers that provide control over VeriPHY diagnostics features. The following table shows the expected readouts. Table 76 • VeriPHY Control Register 2, Address 25E1 (0x19) Bit Name Access Description 15:14 Reserved RO Reserved 13:8 Pair C (4, 5) distance RO Loop length or distance to anomaly for pair C (4, 5) 7:6 Reserved RO Reserved 5:0 Pair D (7, 8) distance RO Loop length or distance to anomaly for pair D (7, 8) Default 0x00 0x00 Note: The resolution of the 6-bit length field is 3 meters. 4.3.8 VeriPHY Control 3 The register at address 26E1 consists of the third of the three device registers that provide control over VeriPHY diagnostics features. Specifically, this register provides information about the termination status (fault condition) for all two link partner pairs. The following table shows the expected readouts. Table 77 • VeriPHY Control Register 3, Address 26E1 (0x1A) Bit Name Access Description Default 15:12 Pair A (1, 2) termination status RO Termination fault for pair A (1, 2) 0x00 11:8 Pair B (3, 6) termination status RO Termination fault for pair B (3, 4) 0x00 7:4 Pair C (4, 5) termination status RO Termination fault for pair C (4, 5) 0x00 3:0 Pair D (7, 8) termination status RO Termination fault for pair D (7, 8) 0x00 The following table shows the meanings for the various fault codes. Table 78 • VeriPHY Control Register 3 Fault Codes Code Denotes 0000 Correctly terminated pair 0001 Open pair 0010 Shorted pair 0100 Abnormal termination 1000 Cross-pair short to pair A 1001 Cross-pair short to pair B 1010 Cross-pair short to pair C 1011 Cross-pair short to pair D 1100 Abnormal cross-pair coupling with pair A 1101 Abnormal cross-pair coupling with pair B 1110 Abnormal cross-pair coupling with pair C 1111 Abnormal cross-pair coupling with pair D VMDS-10509 VSC8572-02 Datasheet Revision 4.2 117 Registers 4.3.9 Ethernet Packet Generator Control 1 The EPG control register provides access to and control of various aspects of the EPG testing feature. There are two separate EPG control registers. The following table shows the settings available in the first register. Table 79 • EPG Control Register 1, Address 29E1 (0x1D) Bit Name Access Description Default 15 EPG enable R/W 1: Enable EPG 0 14 EPG run or stop R/W 1: Run EPG 0 13 Transmission duration R/W 1: Continuous (sends in 10,000-packet increments) 0: Send 30,000,000 packets and stop 0 12:11 Packet length R/W 00: 125 bytes 01: 64 bytes 10: 1518 bytes 11: 10,000 bytes (jumbo packet) 0 10 Interpacket gap R/W 1: 8,192 ns 0: 96 ns 0 9:6 Destination address R/W Lowest nibble of the 6-byte destination address 0001 5:2 Source address R/W Lowest nibble of the 6-byte destination address 0000 1 Payload type R/W 1: Randomly generated payload pattern 0: Fixed based on payload pattern 0 0 Bad frame check sequence (FCS) generation R/W 1: Generate packets with bad FCS 0: Generate packets with good FCS 0 The following information applies to the EPG control number 1: • • Do not run the EPG when the VSC8572-02 is connected to a live network. bit 29E1.13 (continuous EPG mode control): When enabled, this mode causes the device to send continuous packets. When disabled, the device continues to send packets only until it reaches the next 10,000-packet increment mark. It then ceases to send packets. The 6-byte destination address in bits 9:6 is assigned one of 16 addresses in the range of 0xFF FF FF FF FF F0 through 0xFF FF FF FF FF FF. The 6-byte source address in bits 5:2 is assigned one of 16 addresses in the range of 0xFF FF FF FF FF F0 through 0xFF FF FF FF FF FF. If any of bits 13:0 are changed while the EPG is running (bit 14 is set to 1), bit 14 must be cleared and then set back to 1 for the change to take effect and to restart the EPG. • • • 4.3.10 Ethernet Packet Generator Control 2 Register 30E1 consists of the second set of bits that provide access to and control over the various aspects of the EPG testing feature. The following table shows the settings available. Table 80 • EPG Control Register 2, Address 30E1 (0x1E) Bit Name Access Description 15:0 EPG packet payload R/W Default Data pattern repeated in the payload of 0x00 packets generated by the EPG VMDS-10509 VSC8572-02 Datasheet Revision 4.2 118 Registers Note: If any of bits 15:0 in this register are changed while the EPG is running (bit 14 of register 29E1 is set to 1), that bit (29E1.14) must first be cleared and then set back to 1 for the change to take effect and to restart the EPG. 4.4 Extended Page 2 Registers To access the extended page 2 registers (16E2–30E2), enable extended register access by writing 0x0002 to register 31. For more information, see Table 68, page 112. When extended page 2 register access is enabled, reads and writes to registers 16–30 affect the extended registers 16E2–30E2 instead of those same registers in the IEEE-specified register space. Registers 0–15 are not affected by the state of the extended page register access. Writing 0x0000 to register 31 restores the main register access. The following table lists the addresses and register names in the extended register page 2 space. These registers are accessible only when the device register 31 is set to 0x0002. Table 81 • 4.4.1 Extended Registers Page 2 Space Address Name 16E2 Cu PMD Transmit Control 17E2 EEE Control 18E2 RGMII Settings 19E2-29E2 Reserved 30E2 Ring Resiliency Control Cu PMD Transmit Control The register at address 16E2 consists of the bits that provide control over the amplitude settings for the transmit side Cu PMD interface. These bits provide the ability to make small adjustments in the signal amplitude to compensate for minor variations in the magnetics from different vendors. Extreme caution must be exercised when changing these settings from the default values as they have a direct impact on the signal quality. Changing these settings also affects the linearity and harmonic distortion of the transmitted signals. For help with changing these values, contact your Microsemi representative. Table 82 • Cu PMD Transmit Control, Address 16E2 (0x10) Bit Name Access Description 15:12 1000BASE-T signal R/W amplitude trim(1) Sticky bits. 1000BASE-T signal amplitude 1111: -1.7% 1110: -2.6% 1101: -3.5% 1100: -4.4% 1011: -5.3% 1010: -7% 1001: -8.8% 1000: -10.6% 0111: 5.5% 0110: 4.6% 0101: 3.7% 0100: 2.8% 0011: 1.9% 0010: 1% 0001: 0.1% 0000: -0.8% VMDS-10509 VSC8572-02 Datasheet Revision 4.2 Default 0000 119 Registers Table 82 • Cu PMD Transmit Control, Address 16E2 (0x10) (continued) Bit Name Access Description 11:8 100BASE-TX signal R/W amplitude trim(2) 7:4 10BASE-T signal amplitude trim(3) 3:0 10BASE-Te signal amplitude trim Default Sticky bits. 100BASE-TX signal amplitude 1111: -1.7% 1110: -2.6% 1101: -3.5% 1100: -4.4% 1011: -5.3% 1010: -7% 1001: -8.8% 1000: -10.6% 0111 5.5% 0110: 4.6% 0101: 3.7% 0100: 2.8% 0011: 1.9% 0010: 1% 0001: 0.1% 0000: -0.8% 0010 R/W Sticky bits. 10BASE-T signal amplitude 1111: -7% 1110: -7.9% 1101: -8.8% 1100: -9.7% 1011: -10.6% 1010: -11.5% 1001: -12.4% 1000: -13.3% 0111: 0% 0110: -0.7% 0101: -1.6% 0100: -2.5% 0011: -3.4% 0010: -4.3% 0001: -5.2% 0000: -6.1% 1011 R/W Sticky bits. 10BASE-Te signal amplitude 1111: -30.45% 1110: -31.1% 1101: -31.75% 1100: -32.4% 1011: -33.05% 1010: -33.7% 1001: -34.35% 1000: -35% 0111: -25.25% 0110: -25.9% 0101: -26.55% 0100: -27.2% 0011: -27.85% 0010: -28.5% 0001: -29.15% 0000: -29.8% 1110 VMDS-10509 VSC8572-02 Datasheet Revision 4.2 120 Registers 1. 2. 3. 4.4.2 Changes to 1000BASE-T amplitude may result in unpredictable side effects. Adjust 100BASE-TX to specific magnetics. Amplitude is limited by VCC (2.5 V). EEE Control The register at address 17E2 consists of the bits that provide additional control over the chip behavior in energy efficient Ethernet (IEEE 802.3az-2010) mode. Table 83 • EEE Control, Address 17E2 (0x11) Bit Name Access Description Default 15 Enable 10BASE-Te R/W Sticky bit. Enable energy efficient (IEEE 802.3az-2010) 10BASE-Te operating mode. 0 14 Enable LED in fiber unidirectional mode R/W Sticky bit. 1: Enable LED functions in fiber unidirectional mode. 0 13:10 Invert LED polarity R/W Sticky bits. 0000 Invert polarity of LED[3:0]_[1:0] signals. Default is to drive an active low signal on the LED pins. This also applies to enhanced serial LED mode. For more information, see Enhanced Serial LED Mode, page 79. 9:6 Reserved RO Reserved. 5 Enable 1000BASE-T R/W force mode 0 Sticky bit. 1: Enable 1000BASE-T force mode to allow PHY to link-up in 1000BASE-T mode without forcing master/slave when register 0, bits 6 and 13 are set to 2’b10. 41 Force transmit LPI Sticky bit. 1: Enable the EPG to transmit LPI on the MDI, ignore data from the MAC interface. 0: Transmit idles being received from the MAC. 3 Inhibit 100BASE-TX R/W transmit EEE LPI Sticky bit. 0 1: Disable transmission of EEE LPI on transmit path MDI in 100BASE-TX mode when receiving LPI from MAC. 2 Inhibit 100BASE-TX R/W receive EEE LPI Sticky bit. 0 1: Disable transmission of EEE LPI on receive path MAC interface in 100BASE-TX mode when receiving LPI from the MDI. 1 Inhibit 1000BASE-T R/W transmit EEE LPI Sticky bit. 1: Disable transmission of EEE LPI on transmit path MDI in 1000BASE-T mode when receiving LPI from MAC. 0 Inhibit 1000BASE-T R/W receive EEE LPI Sticky bit. 0 1: Disable transmission of EEE LPI on receive path MAC interface in 1000BASE-T mode when receiving LPI from the MDI. 1. R/W 0 0 17E2 bits 4:0 are for debugging purposes only, not for operational use. VMDS-10509 VSC8572-02 Datasheet Revision 4.2 121 Registers 4.4.3 RGMII Settings The following table shows the register settings for the RGMII setting controls at address 18E2. Table 84 • RGMII Settings, Address 18E2 Bit Name Access Description Default 6:4 rgmii_skew_tx R/W 000: 0.2 ns delay 001: 0.8 ns delay 010: 1.1 ns delay 011: 1.7 ns delay 100: 2.0 ns delay 101: 2.3 ns delay 110: 2.6 ns delay 111: 3.4 ns delay 000 3:1 rgmii_skew_rx R/W 000: 0.2 ns delay 001: 0.8 ns delay 010: 1.1 ns delay 011: 1.7 ns delay 100: 2.0 ns delay 101: 2.3 ns delay 110: 2.6 ns delay 111: 3.4 ns delay 000 0 rgmii_bit_rev RO 4.4.4 0 Ring Resiliency Control The following table shows the register settings for the ring resiliency controls at address 30E2. Table 85 • Ring Resiliency, Address 30E2 Bit Name Access Description Default 15 Ring resiliency startup enable (master TR enable) R/W Sticky 0 14 Advertise ring resiliency R/W Sticky 0 13 LP ring resiliency advertisement RO 12 Force ring resiliency R/W enable (override autoneg) Sticky 0 11:6 Reserved RO Reserved 000000 5:4 Ring resiliency status RO Ring resiliency status (from r1000 DSP SM) 00: Timing slave(1) 10: Timing slave becoming master 11: Timing master(1) 01: Timing master becoming slave 11 3:1 Reserved RO Reserved 000 0 Start switchover (only when not in progress) RWSC 1. 0 0 Reflects autoneg master/slave at initial link-up VMDS-10509 VSC8572-02 Datasheet Revision 4.2 122 Registers 4.5 Extended Page 3 Registers To access the extended page 3 registers (16E3–30E3), enable extended register access by writing 0x0003 to register 31. For more information, see Table 68, page 112. When extended page 3 register access is enabled, reads and writes to registers 16–30 affect the extended registers 16E3–30E3 instead of those same registers in the IEEE-specified register space. Registers 0–15 are not affected by the state of the extended page register access. Writing 0x0000 to register 31 restores the main register access. The following table lists the addresses and register names in the extended register page 3 space. These registers are accessible only when the device register 31 is set to 0x0003. Table 86 • 4.5.1 Extended Registers Page 3 Space Address Name 16E3 MAC SerDes PCS Control 17E3 MAC SerDes PCS Status 18E3 MAC SerDes Clause 37 Advertised Ability 19E3 MAC SerDes Clause 37 Link Partner Ability 20E3 MAC SerDes Status 21E3 Media SerDes Transmit Good Packet Counter 22E3 Media SerDes Transmit CRC Error Counter 23E3 Media SerDes PCS Control 24E3 Media SerDes PCS Status 25E3 Media SerDes Clause 37 Advertised Ability 26E3 Media SerDes Clause 37 Link Partner Ability 27E3 Media SerDes status 28E3 Fiber Media CRC Good Counter 29E3 Fiber Media CRC Error Counter 30E3 Reserved MAC SerDes PCS Control The register at address 16E3 consists of the bits that provide access to and control over MAC SerDes PCS block. The following table shows the settings available. Table 87 • MAC SerDes PCS Control, Address 16E3 (0x10) Bit Name Access Description 15 MAC interface disable R/W Sticky bit. 0 1: 1000BASE-X MAC interface disable when media link down. 14 MAC interface restart R/W Sticky bit. 1: 1000BASE-X MAC interface restart on media link change. 0 13 MAC interface PD enable R/W Sticky bit. 1: MAC interface autonegotiation parallel detect enable. 0 VMDS-10509 VSC8572-02 Datasheet Revision 4.2 Default 123 Registers Table 87 • MAC SerDes PCS Control, Address 16E3 (0x10) (continued) Bit Name Access Description Default 12 MAC interface autonegotiation restart R/W Self-clearing bit. 1: Restart MAC interface autonegotiation. 0 11 Force advertised ability R/W 1: Force 16-bit advertised ability from register 0 18E3. 10:8 SGMII preamble control R/W 000: No effect on the start of packet. 001 001: If both the first two nibbles of the 10/100 packet are not 0x5, a byte of 0x55 must be prefixed to the output, otherwise there will be no effect on the start of packet. 010: If both the first two nibbles of the 10/100 packet are not 0x5, a byte of 0x55 must be prefixed to the output. An additional byte of 0x55 must be prefixed to the output if the next two nibbles are also not 0x5. 011–111: Reserved. 7 MAC SerDes autonegotiation enable R/W Sticky bit. 1: MAC SerDes ANEG enable. 6 SerDes polarity at input of R/W MAC 1: Invert polarity of signal received at input of 0 MAC. 5 SerDes polarity at output R/W of MAC 1: Invert polarity of signal at output of MAC. 4 Fast link status enable R/W 1: Use fast link fail indication as link status indication to MAC SerDes. 0: Use normal link status indication to MAC SerDes. 0 3 Reserved R/W Reserved. 0 2:0 Reserved RO Reserved. 4.5.2 0 MAC SerDes PCS Status The register at address 17E3 consists of the bits that provide status from the MAC SerDes PCS block. The following table shows the settings available. Table 88 • MAC SerDes PCS Status, Address 17E3 (0x11) Bit Name Access Description 15:13 Reserved RO Reserved 12 SGMII alignment error RO 1: RGMII/SGMII alignment error occurred 11 MAC interface LP autonegotiation restart RO 1: MAC interface link partner autonegotiation restart request occurred 10 Reserved RO Reserved 9:8 MAC remote fault RO 01, 10, and 11: Remote fault detected from MAC 00: No remote fault detected from MAC 7 Asymmetric pause advertisement RO 1: Asymmetric pause advertised by MAC 6 Symmetric pause advertisement RO 1: Symmetric pause advertised by MAC 5 Full duplex advertisement RO 1: Full duplex advertised by MAC 4 Half duplex advertisement RO 1: Half duplex advertised by MAC VMDS-10509 VSC8572-02 Datasheet Revision 4.2 124 Registers Table 88 • MAC SerDes PCS Status, Address 17E3 (0x11) (continued) Bit Name Access Description 3 MAC interface LP autonegotiation capable RO 1: MAC interface link partner autonegotiation capable 2 MAC interface link status RO 1: MAC interface link status connected 1 MAC interface autonegotiation complete RO 1: MAC interface autonegotiation complete 0 MAC comma detect RO 1: Comma currently detected 0: comma currently not detected 4.5.3 MAC SerDes Clause 37 Advertised Ability The register at address 18E3 consists of the bits that provide access to and control over MAC SerDes Clause 37 advertised ability. The following table shows the settings available. MAC SerDes Cl37 Advertised Ability, Address 18E3 (0x12) Table 89 • Bit Name 15:0 MAC SerDes advertised R/W ability 4.5.4 Access Description Current configuration code word being advertised (this register is read/write if 16E3.11 = 1) Default 0x01E0 MAC SerDes Clause 37 Link Partner Ability The register at address 19E3 consists of the bits that provide status of the MAC SerDes link partner's Clause 37 advertised ability. The following table shows the settings available. Table 90 • MAC SerDes Cl37 LP Ability, Address 19E3 (0x13) Bit Name 15:0 MAC SerDes LP ability RO 4.5.5 Access Description Last configuration code word received from link partner MAC SerDes Status The register at address 20E3 consists of the bits that provide access to MAC SerDes status. The following table shows the settings available. Table 91 • MAC SerDes Status, Address 20E3 (0x14) Bit Name Access Description 15 Reserved RO Reserved 14 MAC comma detect RO Super-sticky bit. Cleared upon SW reset. 1: Comma detected 0: Comma not detected 13 QSGMII sync status RO 12:0 Reserved RO Reserved VMDS-10509 VSC8572-02 Datasheet Revision 4.2 125 Registers 4.5.6 Media SerDes Transmit Good Packet Counter The register at address 21E3 consists of the bits that provide status of the media SerDes transmit good packet counter. The following table shows the settings available. Media SerDes Tx Good Packet Counter, Address 21E3 (0x15) Table 92 • Bit Name Access Description 15 Tx good packet counter active RO 1: Transmit good packet counter active 14 Reserved RO Reserved 13:0 Tx good packet count RO Transmit good packet count modulo 10000 4.5.7 Media SerDes Transmit CRC Error Counter The register at address 22E3 consists of the bits that provide status of the media SerDes transmit packet count that had a CRC error. The following table shows the settings available. Table 93 • 4.5.8 Media SerDes Tx CRC Error Counter, Address 22E3 (0x16) Bit Name Access Description 15:8 Reserved RO 7:0 Tx CRC packet count RO Reserved Transmit CRC packet count (saturates at 255) Media SerDes PCS Control The register at address 23E3 consists of the bits that provide access to and control over Media SerDes PCS control. The following table shows the settings available. Table 94 • Media SerDes PCS Control, Address 23E3 (0x17) Bit Name Access Description 15:14 Reserved RO Reserved 13 Media interface autonegotiation parallel-detection R/W Sticky bit. 1: SerDes media autonegotiation parallel detect enabled Default 0 12 Reserved RO Reserved 11 Force advertised ability R/W 1: Force 16-bit advertised ability from register 25E3.15:0 10:7 Reserved RO Reserved 6 Polarity reversal input Media SerDes polarity reversal input 0: No polarity reversal (default) 1: Polarity reversed 0 5 Polarity reversal output Media SerDes polarity reversal output 0: No polarity reversal (default) 1: Polarity reversed 0 4:0 Reserved RO 0 Reserved VMDS-10509 VSC8572-02 Datasheet Revision 4.2 126 Registers 4.5.9 Media SerDes PCS Status The register at address 24E3 consists of the bits that provide status of the Media SerDes PCS block. The following table shows the settings available. Table 95 • 4.5.10 Media SerDes PCS Status, Address 24E3 (0x18) Bit Name Access Description 15:14 Reserved RO 13 SerDes protocol transfer RO 100 Mb or 100BASE-FX link status 12 SerDes protocol transfer RO 10 Mb link status 11 Media interface link partner autonegotiation restart RO 1: Media interface link partner autonegotiation restart request occurred 10 Reserved RO Reserved 9:8 Remote fault detected RO 01, 10, 11: Remote fault detected from link partner 7 Link partner asymmetric pause RO 1: Asymmetric pause advertised by link partner 6 Link partner symmetric pause RO 1: Symmetric pause advertised by link partner 5 Link partner full duplex advertisement RO 1: Full duplex advertised by link partner 4 Link partner half duplex advertisement RO 1: Half duplex advertised by link partner 3 Link partner autonegotiation capable RO 1: Media interface link partner autonegotiation capable 2 Media interface link status RO 1: Media interface link status 1 Media interface autonegotiation RO complete 1: Media interface autonegotiation complete 0 Reserved Reserved Reserved Media SerDes Clause 37 Advertised Ability The register at address 25E3 consists of the bits that provide access to and control over Media SerDes Clause 37 advertised ability. The following table shows the settings available. Media SerDes Cl37 Advertised Ability, Address 25E3 (0x19) Table 96 • Bit Name Access Description Default 15:0 Media SerDes advertised ability R/W 0x0000 4.5.11 Current configuration code word being advertised. This register is read/write when 23E3.11 = 1. Media SerDes Clause 37 Link Partner Ability The register at address 26E3 consists of the bits that provide status of the media SerDes link partner's Clause 37 advertised ability. The following table shows the settings available. Table 97 • MAC SerDes Cl37 LP Ability, Address 26E3 (0x1A) Bit Name Access Description 15:0 Media SerDes LP ability RO Last configuration code word received from link partner VMDS-10509 VSC8572-02 Datasheet Revision 4.2 127 Registers 4.5.12 Media SerDes Status The register at address 27E3 consists of the bits that provide access to Media SerDes status. The following table shows the settings available. Table 98 • Media SerDes Status, Address 27E3 (0x1B) Bit Name Access Description 15 K28.5 comma realignment RO Self-clearing bit. 1: K28.5 comma re-alignment has occurred 14 Signal detect RO Self-clearing bit. Sticky bit. 1: SerDes media signal detect 13:0 Reserved RO Reserved 4.5.13 Fiber Media CRC Good Counter Register 28E3 makes it possible to read the contents of the CRC good counter for packets that are received on the Fiber media interface; the number of CRC routines that have executed successfully. The following table shows the expected readouts. Table 99 • Fiber Media CRC Good Counter, Address 28E3 (0x1C) Bit Name Access Description Default 15 Packet since last read RO Self-clearing bit. 1: Packet received since last read. 0 14 Reserved RO Reserved. 13:0 Fiber media CRC good counter contents RO Self-clearing bit. Counter containing the number of packets with valid CRCs. This counter does not saturate and will roll over. 4.5.14 0x000 Fiber Media CRC Error Counter Register 29E3 makes it possible to read the contents of the CRC error counter for packets that are received on the Fiber media interface. The following table shows the expected readouts. Table 100 • Fiber Media CRC Error Counter, Address 29E3 (0x1D) 4.6 Bit Name Access Description 15:8 Reserved RO 7:0 Fiber Media CRC RO error counter Default Reserved. Self-clearing bit. CRC error counter for packets received on the Fiber media interface. The value saturates at 0xFF and subsequently clears when read and restarts count. 0x00 General Purpose Registers Accessing the general purpose register space is similar to accessing the extended page registers. Set register 31 to 0x0010. This sets all 32 registers to the general purpose register space. To restore main register page access, write 0x0000 to register 31. VMDS-10509 VSC8572-02 Datasheet Revision 4.2 128 Registers The following table lists the addresses and register names in the general purpose register page space. These registers are accessible only when the device register 31 is set to 0x0010. All general purpose register bits are super-sticky. Table 101 • General Purpose Registers Page Space 4.6.1 Address Name 0G–12G Reserved 13G LED/SIGDET/GPIO Control 14G GPIO Control 2 15G GPIO Input 16G GPIO Output 17G GPIO Output Enable 18G Micro Command 19G MAC Mode and Fast Link Configuration 20G Two-Wire Serial MUX Control 1 21G Two-Wire Serial MUX Control 2 22G Two-Wire Serial MUX Data Read/Write 23G Recovered Clock 0 Control 24G Recovered Clock 1 Control 25G Enhanced LED Control 26G Reserved 27G Reserved 28G Reserved 29G Global Interrupt Status 30G Extended Revision ID Reserved General Purpose Address Space The bits in registers 0G to 12G of the general purpose register space are reserved. 4.6.2 SIGDET/GPIO Control The SIGDET control bits configure the GPIO[1:0]/SIGDET[1:0] pins to function either as signal detect pins for each fiber media port, or as GPIOs. The following table shows the values that can be written. Table 102 • SIGDET/GPIO Control, Address 13G (0x0D) Bit Name Access Description Default 15:12 Reserved RO Reserved 00 11:10 GPIO5/I2C_SCL_1 R/W 00: SCL for PHY1 01: Reserved 10: Reserved 11: Controlled by MII registers 15G to 17G1 00 9:8 GPIO4/I2C_SCL_0 R/W 00: SCL for PHY0 01: Reserved 10: Reserved 11: Controlled by MII registers 15G to 17G2 00 7:4 Reserved Reserved 00 RO VMDS-10509 VSC8572-02 Datasheet Revision 4.2 129 Registers Table 102 • SIGDET/GPIO Control, Address 13G (0x0D) (continued) Bit Name Access Description Default 3:2 GPIO1/SIGDET1 control R/W 00: SIGDET operation 01: Reserved 10: Reserved 11: Controlled by MII registers 15G to 17G 00 1:0 GPIO0/SIGDET0 control R/W 00: SIGDET operation 01: Reserved 10: Reserved 11: Controlled by MII registers 15G to 17G 00 1. 2. 4.6.3 Register 20G bit 1 must be clear in order for this setting to take effect. Register 20G bit 0 must be clear in order for this setting to take effect. GPIO Control 2 The GPIO control 2 register configures the functionality of the COMA_MODE and 1588 control input pins, and provides control for possible GPIO pin options. Table 103 • GPIO Control 2, Address 14G (0x0E) Bit Name Access Description 15:14 GPIO12/1588_SPI_CS and GPIO13/1588_SPI_DO R/W GPIO12/1588_SPI_CS and GPIO13/1588_SPI_DO control. 00: 1588_SPI_CS/1588_SPI_DO operation. 01: Reserved. 10: Reserved. 11: GPIO12/GPIO13 operation. Controlled by MII registers 15G to 17G. 13 COMA_MODE output enable (active low) R/W 1: COMA_MODE pin is an input. 0: COMA_MODE pin is an output. 1 12 COMA_MODE output data R/W Value to output on the COMA_MODE pin when it is configured as an output. 0 11 COMA_MODE input data RO Data read from the COMA_MODE pin. 10 Tri-state enable for two-wire serial bus R/W 1: Tri-states two-wire serial bus output signals instead of driving them high. This allows those signals to be pulled above VDD25 using an external pull-up resistor. 0: Drive two-wire serial bus output signals to high and low values as appropriate. 9 Tri-state enable for LEDs R/W 1 1: Tri-state LED output signals instead of driving them high. This allows the signals to be pulled above VDDIO using an external pull-up resistor. 0: Drive LED bus output signals to high and low values. 8 Reserved RO Reserved 7:6 GPIO11 R/W GPIO11 control. 00: Reserved 01: Reserved 10: Reserved 11: Controlled by MII registers 15G to 17G VMDS-10509 VSC8572-02 Datasheet Revision 4.2 Default 1 0 130 Registers Table 103 • GPIO Control 2, Address 14G (0x0E) (continued) Bit Name 5:4 GPIO10/1588_LOAD_SA R/W VE GPIO10/1588_LOAD_SAVE control. 00: 1588_LOAD_SAVE operation 01: Reserved 10: Reserved 11: Controlled by MII registers 15G to 17G 3:2 GPIO9/FASTLINK_FAIL R/W GPIO9/FASTLINK_FAIL control. 00: FASTLINK_FAIL operation 01: Reserved 10: Reserved 11: Controlled by MII registers 15G to 17G 1:0 GPIO8/I2C_SDA R/W GPIO8/I2C_SDA control. 00: I2C_SDA operation 01: Reserved 10: Reserved 11: Controlled by MII registers 15G to 17G 4.6.4 Access Description Default GPIO Input The input register contains information about the input to the device GPIO pins. Read from this register to access the data on the device GPIO pins. The following table shows the readout you can expect. Table 104 • GPIO Input, Address 15G (0x0F) Bit Name Access Description Default 15:14 Reserved RO Reserved 00 13 GPIO13/1588_SPI_DO RO GPIO13/1588_SPI_DO input 1 12 GPIO12/1588_SPI_CS RO GPIO12/1588_SPI_CS input 1 11 GPIO11 RO GPIO11 input 0 10 GPIO10/1588_LOAD_SAVE RO GPIO10/1588_LOAD_SAVE input 0 9 GPIO9/FASTLINK_FAIL RO GPIO9/FASTLINK_FAIL input 1 8 GPIO8/I2C_SDA RO GPIO8/I2C_SDA input 1 7:6 Reserved RO Reserved 0 5 GPIO5/I2C_SCL_1 RO GPIO5/I2C_SCL_1 input 1 4 GPIO4/I2C_SCL_0 RO GPIO4/I2C_SCL_0 input 1 3:2 Reserved RO Reserved 1 GPIO1/SIGDET1 RO GPIO1/SIGDET1 input 1 0 GPIO0/SIGDET0 RO GPIO0/SIGDET0 input 0 4.6.5 GPIO Output The output register allows you to access and control the output from the device GPIO pins. The following table shows the values you can write. Table 105 • GPIO Output, Address 16G (0x10) Bit Name Access Description 15:14 Reserved RO Reserved 13 GPIO13/1588_SPI_DO R/W GPIO13/1588_SPI_DO output VMDS-10509 VSC8572-02 Datasheet Revision 4.2 Default 0 131 Registers Table 105 • GPIO Output, Address 16G (0x10) (continued) Bit Name Access Description Default 12 GPIO12/1588_SPI_CS R/W GPIO12/1588_SPI_CS output 0 11 GPIO11 R/W GPIO11 output 0 10 GPIO10/1588_LOAD_SAVE R/W GPIO10/1588_LOAD_SAVE output 0 9 GPIO9/FASTLINK_FAIL R/W GPIO9/FASTLINK_FAIL output 0 8 GPIO8/I2C_SDA R/W GPIO8/I2C_SDA output 0 7:6 Reserved RO Reserved 0 5 GPIO5/I2C_SCL_1 R/W GPIO5/I2C_SCL_1 output 0 4 GPIO4/I2C_SCL_0 R/W GPIO4/I2C_SCL_0 output 0 3:2 Reserved RO Reserved 1 GPIO1/SIGDET1 R/W GPIO1/SIGDET1 output 0 0 GPIO0/SIGDET0 R/W GPIO0/SIGDET0 output 0 4.6.6 GPIO Pin Configuration Register 17G in the GPIO register space controls whether a particular GPIO pin functions as an input or an output. The following table shows the settings available. Table 106 • GPIO Input/Output Configuration, Address 17G (0x11) 4.6.7 Bit Name Access Description Default 15:14 Reserved RO Reserved 13 GPIO13/1588_SPI_DO R/W GPIO13/1588_SPI_DO output enable 0 12 GPIO12/1588_SPI_CS R/W GPIO12/1588_SPI_CS output enable 0 11 GPIO11 R/W GPIO11 output enable 0 10 GPIO10/1588_LOAD_SAVE R/W GPIO10/1588_LOAD_SAVE output enable 0 9 GPIO9/FASTLINK_FAIL R/W GPIO9/FASTLINK_FAIL output enable 0 8 GPIO8/I2C_SDA R/W GPIO8/I2C_SDA output enable 0 7:6 Reserved RO Reserved 0 5 GPIO5/I2C_SCL_1 R/W GPIO5/I2C_SCL_1 output enable 0 4 GPIO4/I2C_SCL_0 R/W GPIO4/I2C_SCL_0 output enable 0 3:2 Reserved RO Reserved 1 GPIO1/SIGDET1 R/W GPIO1/SIGDET1 output enable 0 0 GPIO0/SIGDET0 R/W GPIO0/SIGDET0 output 0 Microprocessor Command Register 18G is a command register. Bit 15 tells the internal processor to execute the command. When bit 15 is cleared the command has completed. Software needs to wait until bit 15 = 0 before proceeding with the next PHY register access. Bit 14 = 1 typically indicates an error condition where the squelch patch was not loaded. Use the following steps to execute the command: 1. 2. 3. Write desired command Check bit 15 (move existing text) Check bit 14 (if set, then error) VMDS-10509 VSC8572-02 Datasheet Revision 4.2 132 Registers Commands may take up to 25 ms to complete before bit 15 changes to 0. Note: All MAC interfaces must be the same — all QSGMII, RGMII, or SGMII. Table 107 • Microprocessor Command Register, Address 18G Command Setting Enable 2 ports MAC SGMII 0x80F0 Enable 2 ports MAC 1/2 QSGMII 0x80E0 QSGMII transmitter control(1) 1588 initialization(2) 0x801A Enable 2 ports Media 1000BASE-X 0x8FC1(3) Enable 2 ports Media 100BASE-FX 0x8FD1(3) 1. Contact your Microsemi representative for an initialization script that greatly simplifies the programming of QSGMII transmit controls. Initializes six analyzers in both 1588 IP blocks A and B. This needs to be done after reset and before the 1588 blocks are used. The “F” in the command has a bit representing each of the four PHYs. To exclude a PHY from the configuration, set its bit to 0. For example, the configuration of PHY 3 and PHY 2 to 1000BASE-X would be 1100 or a “C” and the command would be 0x8CC1. 2. 3. 4.6.8 MAC Configuration and Fast Link Register 19G in the GPIO register space controls the MAC interface mode and the selection of the source PHY for the fast link failure indication. The following table shows the settings available for the GPIO9/FASTLINK-FAIL pin. Table 108 • MAC Configuration and Fast Link Register, Address 19G (0x13) Bit Name Access Description Default 15:14 MAC configuration R/W Select MAC interface mode 00: SGMII 01: QSGMII 10: RGMII 11: Reserved 00 13:4 Reserved RO Reserved 3:0 Fast link failure port setting R/W Select fast link failure PHY source 0000: Port0 0001: Port1 0010: Reserved 0011: Reserved 1100–1111: Output disabled 4.6.9 0xF Two-Wire Serial MUX Control 1 The following table shows the settings available to control the integrated two-wire serial MUX. Table 109 • Two-Wire Serial MUX Control 1, Address 20G (0x14) Bit Name Access Description 15:9 Two-wire serial device address R/W Default Top 7 bits of the 8-bit address sent out on the two 0xA0 wire serial stream. The bottom bit is the read/write signal, which is controlled by register 21G, bit 8. SFPs use 0xA0. VMDS-10509 VSC8572-02 Datasheet Revision 4.2 133 Registers Table 109 • Two-Wire Serial MUX Control 1, Address 20G (0x14) (continued) Bit Name Access Description 8:6 Reserved RO Reserved. 5:4 Two-wire serial SCL clock frequency R/W 00: 50 kHz 01: 100 kHz 10: 400 kHz 11: 2 MHz 3 Two-wire serial MUX port 3 enable R/W 1: Enabled. 0 0: Two-wire serial disabled. Becomes GPIO pin. 2 Two-wire serial MUX port 2 enable R/W 1: Enabled. 0 0: Two-wire serial disabled. Becomes GPIO pin. 1 Two-wire serial MUX port 1 enable R/W 1: Enabled. 0 0: Two-wire serial disabled. Becomes GPIO pin. 0 Two-wire serial MUX port 0 enable R/W 1: Enabled. 0 0: Two-wire serial disabled. Two-wire serial MUX port 0 becomes GPIO pin if serial LED function is enabled, regardless of the settings of this bit. 4.6.10 Default 01 Two-Wire Serial MUX Control 2 Register 21G is used to control the two-wire serial MUX for status and control of two-wire serial slave devices. Table 110 • Two-Wire Serial MUX Interface Status and Control, Address 21G (0x15) Bit Name Access Description Default 15 Two-wire serial MUX ready RO 1: Two-wire serial MUX is ready for read or write 1 14:12 Reserved RO Reserved 11:10 PHY port Address R/W Specific VSC8572-02 PHY port being addressed. 9 Enable two-wire serial MUX access R/W Self-clearing bit. 0 1: Execute read or write through the two-wire serial MUX based on the settings of register bit 21G.8 8 Two-wire serial MUX read or write R/W 1: Read from two-wire serial MUX 0: Write to two-wire serial MUX 7:0 Two-wire serial MUX address R/W Sets the address of the two-wire serial MUX 0x00 used to direct read or write operations. 4.6.11 00 1 Two-Wire Serial MUX Data Read/Write Register 22G in the extended register space enables access to the two-wire serial MUX. Table 111 • Two-Wire Serial MUX Data Read/Write, Address 22G (0x16) Bit Name Access Description 15:8 Two-wire serial MUX RO read data Eight-bit data read from two-wire serial MUX; requires setting both register 21G.9 and 21G.8 to 1. 7:0 Two-wire serial MUX R/W write data Eight-bit data to be written to two-wire serial MUX. 0x00 VMDS-10509 VSC8572-02 Datasheet Revision 4.2 Default 134 Registers 4.6.12 Recovered Clock 1 Control Register 23G in the extended register space controls the functionality of the recovered clock 1 output signal. Table 112 • Recovered Clock 1 Control, Address 23G (0x17) Bit Name Access Description Default 15 Enable RCVRDCLK1 R/W 1: Enable recovered clock 1 output 0: Disable recovered clock 1 output 0 14:11 Clock source select R/W Select bits for source PHY for recovered clock: 0000: PHY0 0001: PHY1 0100–1111: Reserved 0000 10:8 Clock frequency select R/W Select output clock frequency: 000: 25 MHz output clock 001: 125 MHz output clock 010: 31.25 MHz output clock 011–111: Reserved 000 7:6 Reserved RO Reserved. 5:4 Clock squelch level R/W Select clock squelch level 00: Automatically squelch clock to low when the link is not up, is unstable, is up in a mode that does not support the generation of a recovered clock (1000BASE-T master or 10BASE-T), or is up in EEE mode (100BASE-TX or 1000BASE-T slave). 01: Same as 00 except that the clock is also generated in 1000BASE-T master and 10BASE-T link-up modes. This mode also generates a recovered clock output in EEE mode during reception of LP_IDLE. 10: Squelch only when the link is not up. 11: Disable clock squelch. Note: A clock from the SerDes or Cu PHY will be output on the recovered clock output in this mode when the link is down. When the CLK_SQUELCH_IN pin is set high, it squelches the recovered clocks regardless of bit settings. 3 Reserved RO Reserved. 2:0 Clock selection for specified PHY R/W 000: Serial media recovered clock 001: Copper PHY recovered clock 010: Copper PHY transmitter TCLK 011–111: Reserved VMDS-10509 VSC8572-02 Datasheet Revision 4.2 000 135 Registers 4.6.13 Recovered Clock 2 Control Register 24G in the extended register space controls the functionality of the recovered clock 2 output signal. Table 113 • Recovered Clock 2 Control, Address 24G (0x18) Bit Name Access Description Default 15 Enable RCVRDCLK2 R/W Enable recovered clock 2 output 14:11 Clock source select R/W Select bits for source PHY for recovered clock: 0000 0000: PHY0 0001: PHY1 0100–1111: Reserved 10:8 Clock frequency select R/W Select output clock frequency: 000: 25 MHz output clock 001: 125 MHz output clock 010: 31.25 MHz output clock 011–111: Reserved 7:6 Reserved RO Reserved 5:4 Clock squelch level R/W Select clock squelch level: 00: Automatically squelch clock to low when the link is not up, is unstable, is up in a mode that does not support the generation of a recovered clock (1000BASE-T master or 10BASE-T), or is up in EEE mode (100BASE-TX or 1000BASE-T slave). 01: Same as 00 except that the clock is also generated in 1000BASE-T master and 10BASE-T link-up modes. This mode also generates a recovered clock output in EEE mode during reception of LP_IDLE 10: Squelch only when the link is not up 11: Disable clock squelch. Note: A clock from the SerDes or Cu PHY will be output on the recovered clock output in this mode when the link is down. 0 000 Note: A clock from the SerDes or Cu PHY will be output on the recovered clock output in this mode when the link is down. When the CLK_SQUELCH_IN pin is set high, it squelches the recovered clocks regardless of bit settings. 3 Reserved RO Reserved 2:0 Clock selection for specified PHY R/W 000: Serial media recovered clock 001: Copper PHY recovered clock 010–111: Reserved VMDS-10509 VSC8572-02 Datasheet Revision 4.2 000 136 Registers 4.6.14 Enhanced LED Control The following table contains the bits to control advanced functionality of the parallel and serial LED signals. Table 114 • Enhanced LED Control, Address 25G (0x19) Bit Name Access Description 15:8 LED pulsing duty cycle control R/W 7 Port 1 enhanced serial LED R/W output enable Enable the enhanced serial LED output functionality for port 1 LED pins. 1: Enhanced serial LED outputs 0: Normal function 0 6 Port 0 enhanced serial LED R/W output enable Enable the enhanced serial LED output functionality for port 0 LED pins. 1: Enhanced serial LED outputs 0: Normal function 0 5:3 Serial LED frame rate selection R/W Select frame rate of serial LED stream 000: 2500 Hz frame rate 001: 1000 Hz frame rate 010: 500 Hz frame rate 011: 250 Hz frame rate 100: 200 Hz frame rate 101: 125 Hz frame rate 110: 40 Hz frame rate 111: Output basic serial LED stream See Table 30, page 79. 2:1 Serial LED select R/W Select which LEDs from each PHY to enable on the serial stream 00: Enable all four LEDs of each PHY 01: Enable LEDs 2, 1 and 0 of each PHY 10: Enable LEDs 1 and 0 of each PHY 11: Enable LED 0 of each PHY 0 LED port swapping R/W See LED Port Swapping, page 79. 4.6.15 Default Programmable control for LED pulsing 00 duty cycle when bit 30.12 is set to 1. Valid settings are between 0 and 198. A setting of 0 corresponds to a 0.5% duty cycle and 198 corresponds to a 99.5% duty cycle. Intermediate values change the duty cycle in 0.5% increments 00 Global Interrupt Status The following table contains the interrupt status from the various sources to indicate which one caused that last interrupt on the pin. Table 115 • Global Interrupt Status, Address 29G (0x1D) Bit Name 15:10 Reserved 9 Access Default Description (1) PHY1 1588 RO 000111 Reserved RO 1 PHY 1 1588 interrupt source indication 0: PHY1 1588 caused the interrupt 1: PHY1 1588 did not cause the interrupt VMDS-10509 VSC8572-02 Datasheet Revision 4.2 137 Registers Table 115 • Global Interrupt Status, Address 29G (0x1D) (continued) Bit Name Access Default Description 8 PHY0 1588(1) RO 1 PHY 0 1588 interrupt source indication 0: PHY0 1588 caused the interrupt 1: PHY0 1588 did not cause the interrupt 7:2 Reserved R 111111 Reserved source(1) 1 PHY1 interrupt RO 1 PHY1 interrupt source indication 0: PHY1 caused the interrupt 1: PHY1 did not cause the interrupt 0 PHY0 interrupt source(1) RO 1 PHY0 interrupt source indication 0: PHY0 caused the interrupt 1: PHY0 did not cause the interrupt 1. This bit is set to 1 when the corresponding PHY’s Interrupt Status register 26 (0x1A) is read. For information about 1588 IP register access, see Accessing 1588 IP Registers, page 72. 4.6.16 Extended Revision ID The following table lists the extended revision ID information. Table 116 • Extended Revision ID, Address 30G (0x1E) 4.7 Bit Name Access Default Description 15:1 Reserved RO 0x0000 Reserved 0 Ext Rev ID RO 0x1 Revision E Clause 45 Registers to Support Energy Efficient Ethernet and 802.3bf This section describes the Clause 45 registers that are required to support energy efficient Ethernet. Access to these registers is through the IEEE standard registers 13 and 14 (MMD access control and MMD data or address registers) as described in section 4.2.11 and 4.2.12. The following table lists the addresses and register names in the Clause 45 register page space. When the link is down, 0 is the value returned for the x.180x addresses. Table 117 • Clause 45 Registers Page Space Address Name 1.1801 Tx maximum delay through PHY (PMA/PMD/PCS, until 1588 block) 1.1803 Tx minimum delay through PHY (PMA/PMD/PCS, until 1588 block) 1.1805 Rx maximum delay through PHY (PMA/PMD/PCS, until 1588 block) 1.1807 Rx minimum delay through PHY (PMA/PMD/PCS, until 1588 block) 3.1 PCS status 1 3.1801 Tx maximum delay through 1588 3.1803 Tx minimum delay through 1588 3.1805 Rx maximum delay through 1588 3.1807 Rx minimum delay through 1588 3.20 EEE capability 3.22 EEE wake error counter VMDS-10509 VSC8572-02 Datasheet Revision 4.2 138 Registers Table 117 • Clause 45 Registers Page Space (continued) Address Name 4.1801 Tx maximum delay through xMII (RGMII, SGMII, QSGMII, including FIFO variations) 4.1803 Tx minimum delay through xMII (RGMII, SGMII, QSGMII, including FIFO variations) 4.1805 Rx maximum delay through xMII (RGMII, SGMII, QSGMII, including FIFO variations) 4.1807 Rx minimum delay through xMII (RGMII, SGMII, QSGMII, including FIFO variations) 7.60 EEE advertisement 7.61 EEE link partner advertisement 4.7.1 PCS Status 1 The bits in the PCS Status 1 register provide a status of the EEE operation from the PCS for the link that is currently active. Table 118 • PCS Status 1, Address 3.1 4.7.2 Bit Name Access Description 15:12 Reserved RO Reserved 11 Tx LPI received RO/LH 1: Tx PCS has received LPI 0: LPI not received 10 Rx LPI received RO/LH 1: Rx PCS has received LPI 0: LPI not received 9 Tx LPI indication RO 1: Tx PCS is currently receiving LPI 0: PCS is not currently receiving LPI 8 Rx LPI indication RO 1: Rx PCS is currently receiving LPI 0: PCS is not currently receiving LPI 7:3 Reserved RO Reserved 2 PCS receive link status RO 1: PCS receive link up 0: PCS receive link down 1:0 Reserved Reserved RO EEE Capability This register is used to indicate the capability of the PCS to support EEE functions for each PHY type. The following table shows the bit assignments for the EEE capability register. Table 119 • EEE Capability, Address 3.20 4.7.3 Bit Name Access Description 15:3 Reserved RO 2 1000BASE-T EEE RO 1: EEE is supported for 1000BASE-T 0: EEE is not supported for 1000BASE-T 1 100BASE-TX EEE RO 1: EEE is supported for 100BASE-TX 0: EEE is not supported for 100BASE-TX 0 Reserved RO Reserved Reserved EEE Wake Error Counter This register is used by PHY types that support EEE to count wake time faults where the PHY fails to complete its normal wake sequence within the time required for the specific PHY type. The definition of VMDS-10509 VSC8572-02 Datasheet Revision 4.2 139 Registers the fault event to be counted is defined for each PHY and can occur during a refresh or a wakeup as defined by the PHY. This 16-bit counter is reset to all zeros when the EEE wake error counter is read or when the PHY undergoes hardware or software reset. Table 120 • EEE Wake Error Counter, Address 3.22 4.7.4 Bit Name Access Description 15:0 Wake error counter RO Count of wake time faults for a PHY EEE Advertisement This register defines the EEE advertisement that is sent in the unformatted next page following a EEE technology message code. The following table shows the bit assignments for the EEE advertisement register. Table 121 • EEE Advertisement, Address 7.60 Bit Name Access Description 15:3 Reserved RO 2 1000BASE-T EEE R/W 1: Advertise that the 1000BASE-T has EEE capability 0: Do not advertise that the 1000BASE-T has EEE capability 0 1 100BASE-TX EEE R/W 1: Advertise that the 100BASE-TX has EEE capability 0: Do not advertise that the 100BASE-TX has EEE capability 0 0 Reserved RO Reserved 4.7.5 Default Reserved EEE Link Partner Advertisement All the bits in the EEE LP Advertisement register are read only. A write to the EEE LP advertisement register has no effect. When the AN process has been completed, this register will reflect the contents of the link partner's EEE advertisement register. The following table shows the bit assignments for the EEE advertisement register. Table 122 • EEE Advertisement, Address 7.61 Bit Name Access Description 15:3 Reserved RO 2 1000BASE-T EEE RO 1: Link partner is advertising EEE capability for 1000BASE-T 0: Link partner is not advertising EEE capability for 1000BASE-T 1 100BASE-TX EEE RO 1: Link partner is advertising EEE capability for 100BASE-TX 0: Link partner is not advertising EEE capability for 100BASE-TX 0 Reserved RO Reserved Reserved VMDS-10509 VSC8572-02 Datasheet Revision 4.2 140 Registers The following table shows the bit assignments for the 802.3bf registers. When the link is down, 0 is the value returned. cl45reg1_1801 would be device address of 1 and register address of 1801. Table 123 • 802.3bf Registers Register Name Function 1.1801 cl45reg1_1801_val[15:0] Tx maximum delay through PHY (PMA/PMD/PCS, until 1588 block) 1.1803 cl45reg1_1803_val[15:0] Tx minimum delay through PHY (PMA/PMD/PCS, until 1588 block) 1.1805 cl45reg1_1805_val[15:0] Rx maximum delay through PHY (PMA/PMD/PCS, until 1588 block) 1.1807 cl45reg1_1807_val[15:0] Rx minimum delay through PHY (PMA/PMD/PCS, until 1588 block) 3.1801 cl45reg3_1801_val[15:0] Tx maximum delay through 1588 3.1803 cl45reg3_1803_val[15:0] Tx minimum delay through 1588 3.1805 cl45reg3_1805_val[15:0] Rx maximum delay through 1588 3.1807 cl45reg3_1807_val[15:0] Rx minimum delay through 1588 4.1801 cl45reg4_1801_val[15:0] Tx maximum delay through xMII (RGMII, SGMII, QSGMII, including FIFO variations) 4.1803 cl45reg4_1803_val[15:0] Tx minimum delay through xMII (RGMII, SGMII, QSGMII, including FIFO variations) 4.1805 cl45reg4_1805_val[15:0] Rx maximum delay through xMII (RGMII, SGMII, QSGMII, including FIFO variations) 4.1807 cl45reg4_1807_val[15:0] Rx minimum delay through xMII (RGMII, SGMII, QSGMII, including FIFO variations) VMDS-10509 VSC8572-02 Datasheet Revision 4.2 141 4.8 1588 IP Registers This section lists the 1588 IP registers. 4.9 1588 IP Block Configuration and Status Registers This section lists the overviews for the 1588 IP block configuration and status registers. The registers documented in this section are present in both channels. Note: For more information about accessing the 1588 IP registers, see Accessing 1588 IP Registers, page 72. Table 124 • IP_1588_TOP_CFG_STAT Address Name Details 0x00 INTERFACE_CTL Interface Control, page 145 0x01 ANALYZER_MODE Analyzer Mode, page 146 0x02 SPARE_REGISTER Spare Scratchpad, page 146 Table 125 • IP_1588_LTC Address Name Details 0x10 LTC_CTRL LTC Control, page 146 0x11 LTC_LOAD_SEC_H LTC Load Seconds (High), page 148 0x12 LTC_LOAD_SEC_L LTC Load Seconds (Low), page 148 0x13 LTC_LOAD_NS LTC Load Nanoseconds, page 148 0x14 LTC_SAVED_SEC_H LTC Saved Seconds (High), page 148 0x15 LTC_SAVED_SEC_L LTC Saved Seconds (Low), page 148 0x16 LTC_SAVED_NS LTC Saved Nanoseconds, page 149 0x17 LTC_SEQUENCE LTC Sequence Configuration, page 149 0x18 LTC_SEQ LTC Sequence Configuration, page 149 0x1A LTC_AUTO_ADJUST LTC Auto Adjustment, page 150 Table 126 • TS_FIFO_SI Address Name Details 0x20 TS_FIFO_SI_CFG Timestamp FIFO Serial Interface Configuration, page 150 0x21 TS_FIFO_SI_TX_CNT Transmitted Timestamp Count, page 151 Table 127 • INGR_PREDICTOR Address Name Details 0x22 IG_CFG Ingress Configuration, page 151 VMDS-10509 VSC8572-02 Datasheet Revision 4.2 142 Table 128 • EGR_PREDICTOR Address Name Details 0x26 EG_CFG Egress Configuration, page 151 Table 129 • INGR_IP_1588_CFG_STAT Address Name Details 0x2D INGR_INT_STATUS IP 1588 Interrupt Status, page 152 0x2E INGR_INT_MASK IP 1588 Interrupt Mask, page 153 0x2F INGR_SPARE_REGISTER Spare Scratchpad, page 153 Table 130 • INGR_IP_1588_TSP Address Name Details 0x35 INGR_TSP_CTRL TSP Control, page 154 0x36 INGR_TSP_STAT TSP Status, page 154 0x37 INGR_LOCAL_LATENCY Local Latency, page 154 0x38 INGR_PATH_DELAY Path Delay, page 155 0x39 INGR_DELAY_ASYMMETRY DelayAsymmetry, page 155 Table 131 • INGR_IP_1588_DF Address Name Details 0x3A INGR_DF_CTRL Configuration and Control for the Delay FIFO, page 155 Table 132 • INGR_IP_1588_RW Address Name Details 0x44 INGR_RW_CTRL Rewriter Configuration and Control, page 156 0x45 INGR_RW_MODFRM_CNT Count of Modified Frames, page 156 0x46 INGR_RW_FCS_ERR_CNT Count of FCS Errors, page 156 0x47 INGR_RW_PREAMBLE_ERR_C Count of the Number of Preamble Errors, page 157 NT Table 133 • EGR_IP_1588_CFG_STAT Address Name Details 0x4D EGR_INT_STATUS IP 1588 Interrupt Status, page 157 VMDS-10509 VSC8572-02 Datasheet Revision 4.2 143 Table 133 • EGR_IP_1588_CFG_STAT (continued) Address Name Details 0x4E EGR_INT_MASK IP 1588 Interrupt Mask, page 158 0x4F EGR_SPARE_REGISTER Spare Scratchpad, page 159 Table 134 • EGR_IP_1588_TSP Address Name Details 0x55 EGR_TSP_CTRL TSP Control, page 159 0x56 EGR_TSP_STAT TSP Status, page 159 0x57 EGR_LOCAL_LATENCY Local Latency, page 160 0x58 EGR_PATH_DELAY Path Delay, page 160 0x59 EGR_DELAY_ASYMMETR DelayAsymmetry, page 160 Y Table 135 • EGR_IP_1588_DF Address Name Details 0x5A EGR_DF_CTRL Configuration and Control for the Delay FIFO, page 161 Table 136 • EGR_IP_1588_TSFIFO Address Name Details 0x5B EGR_TSFIFO_CSR Timestamp FIFO Configuration and Status, page 161 0x5C EGR_TSFIFO_0 Data Value from the Timestamp FIFO, page 161 0x5D EGR_TSFIFO_1 Data Value from the Timestamp FIFO, page 162 0x5E EGR_TSFIFO_2 Data Value from the Timestamp FIFO, page 163 0x5F EGR_TSFIFO_3 Data Value from the Timestamp FIFO, page 163 0x60 EGR_TSFIFO_4 Data Value from the Timestamp FIFO, page 163 0x61 EGR_TSFIFO_5 Data Value from the Timestamp FIFO, page 163 0x62 EGR_TSFIFO_6 Data Value from the Timestamp FIFO, page 163 0x63 EGR_TSFIFO_DROP_CN Count of Dropped Timestamps, page 164 T Table 137 • EGR_IP_1588_RW Address Name Details 0x64 EGR_RW_CTRL Rewriter Configuration and Control, page 164 0x65 EGR_RW_MODFRM_CNT Count of Modified Frames, page 164 0x66 EGR_RW_FCS_ERR_CNT Count of FCS Errors, page 165 VMDS-10509 VSC8572-02 Datasheet Revision 4.2 144 Table 137 • EGR_IP_1588_RW (continued) Address Name Details 0x67 EGR_RW_PREAMBLE_ERR_C Count of the Number of Preamble Errors, page 165 NT Table 138 • INGR_IP_1588_DEBUG_REGISTERS Address Name Details 0x9F INGR_SW_POP_FIFO 1588 IP Ingress Debug Register, page 165 Table 139 • EGR_IP_1588_DEBUG_REGISTERS Address Name Details 0xC0 EGR_SW_POP_FIFO 1588 IP Egress Debug Registers, page 166 4.10 1588 IP Control and Status Registers This section provides information about the 1588 IP control and status registers. 4.10.1 Interface Control Short Name: INTERFACE_CTL Address: 0x00 Table 140 • Interface Control Register Bit Name Description 6 CLK_ENA Enables the data path clocks in the 1588 IP R/W block. The 1588 logic, including all configuration registers, is held in a reset state when the clocks are disabled. 0: Clocks Disabled 1: Clocks Enabled 0x0 2 BYPASS When 1, the 1588 IP block is bypassed. This is R/W the default state. Changing this bit to 0 will allow 1588 processed data to flow out of the block. This bit is internally registered so that it only takes effect during an IDLE period in the data stream. This allows for a more seamless transition from bypass to data passing modes. 0: Data mode 1: Bypass mode Data flows through the bypass data path even if register bit CLK_ENA = 0. 0x1 1:0 MII_PROTOCOL Defines the operating mode that the attached PCS block operates in 0: reserved 1: reserved 2: GMII 3: reserved Note: These bits must be set to 0x2 0x0 VMDS-10509 VSC8572-02 Datasheet Revision 4.2 Access R/W Default 145 4.10.2 Analyzer Mode Short Name: ANALYZER_MODE Address: 0x01 Table 141 • Analyzer Mode Register Bit Name Description 18:16 ENCAP_FLOW_MODE Defines how flow matching is performed in each R/W encapsulation engine. For each engine 0: Match any flow 1: Strict matching 0x0 6:4 EGR_ENCAP_ENGINE_ENA Enables for the egress encapsulation engines. R/W Enable bit 0 & 1 are for the PTP engines and bit 2 is for the OAM engine. For each engine 0: Disabled 1: Enabled 0x0 2:0 INGR_ENCAP_ENGINE_EN Enables for the ingress encapsulation engines. R/W A Enable bit 0 & 1 are for the PTP engines and bit 2 is for the OAM engine. For each engine 0: Disabled 1: Enabled 0x0 4.10.3 Access Default Spare Scratchpad Short Name: SPARE_REGISTER Address: 0x02 Table 142 • Spare Scratchpad Register Bit Name Description Access Default 31:0 SPARE_REGISTER Spare scratchpad register R/W 0x00000000 4.11 1588 IP Local Time Counter Registers This section provides information about the 1588 IP local time counter configuration and status registers. 4.11.1 LTC Control Short Name: LTC_CTRL VMDS-10509 VSC8572-02 Datasheet Revision 4.2 146 Address: 0x10 Table 143 • LTC Control Register Bit Name Description Access 14:12 LTC_CLK_SEL This field is used to select the clock source for R/W the LTC block. The actual clock mux is external to the IP block, this field merely provides the select lines to the clock mux. These 3 select lines are outputs of the IP block and are not used internally. The single clock signal is then fed to the LTC input pin. The 3 bits allows for one of up to 8 possible clock sources to be selected. 0: External clock (supports 125 MHz, 156.25 MHz, and 250 MHz) 1: Client Rx Clock (QSGMII/SGMII recovered clock), 125 MHz 2: Client Tx Clock, 125 MHz 3: Line Rx Clock, 125 MHz 4: Line Tx Clock, 125 MHz 5: Local reference clock, 250 MHz 6: INVALID 7: INVALID Default 0x0 10:6 Reserved Reserved RO 5 Reserved Reserved RO 4 LTC_AUTO_ADJUST_UPDA When written to a '1' causes the Local Time One-shot 0x0 TE Counter to update the automatic adjustment values from the LTC_AUTO_ADJUST register. The current automatic adjustment is reset to start with the new values. Automatically cleared. 0: No change to any previous updates (write), or update has completed (read) 1: Use new values from LTC_AUTO_ADJUST register. 3 LTC_ADD_SUB_1NS_REQ When written to a '1' causes a request for 1ns to One-shot 0x0 be added or subtracted (depending upon the LTC_ADD_SUB_1NS field) from the Local time. Automatically cleared. 0: No Add/Subtract from local time (write), Bit has auto cleared (read) 1: Add/Subtract 1ns from the local time. 2 LTC_ADD_SUB_1NS This bit selects whether a write to the LTC_ADD_SUB_1NS_REQ register causes an add or subtract. 0: Subtract 1 ns 1: Add 1ns to the local time. R/W 0x0 1 LTC_SAVE_ENA LTC save enable. Enables the chip save pin to save the LTC_SAVE seconds/nanoseconds registers. R/W 0x0 0 LTC_LOAD_ENA LTC load enable. Enables the chip load pin to load the LTC_LOAD seconds/nanoseconds registers. R/W 0x0 VMDS-10509 VSC8572-02 Datasheet Revision 4.2 147 4.11.2 LTC Load Seconds (High) Short Name: LTC_LOAD_SEC_H Address: 0x11 LTC load seconds (high) Table 144 • LTC Load Seconds (High) Register Bit Name Description Access Default 15:0 LTC_LOAD_SEC_H LTC load seconds (high) R/W 0x0000 4.11.3 LTC Load Seconds (Low) Short Name: LTC_LOAD_SEC_L Address: 0x12 LTC load seconds (low) Table 145 • LTC Load Seconds (Low) Register Bit Name Description Access Default 31:0 LTC_LOAD_SEC_L LTC load seconds (low) R/W 0x00000000 4.11.4 LTC Load Nanoseconds Short Name: LTC_LOAD_NS Address: 0x13 LTC load nanoseconds Table 146 • LTC Load Nanoseconds Register Bit Name Description Access Default 31:0 LTC_LOAD_NS LTC load nanoseconds R/W 0x00000000 4.11.5 LTC Saved Seconds (High) Short Name: LTC_SAVED_SEC_H Address: 0x14 LTC saved seconds (high) Table 147 • LTC Saved Seconds (High) Register Bit Name Description Access Default 15:0 LTC_SAVED_SEC_H LTC saved seconds (high) R/O 0x0000 4.11.6 LTC Saved Seconds (Low) Short Name: LTC_SAVED_SEC_L Address: 0x15 VMDS-10509 VSC8572-02 Datasheet Revision 4.2 148 LTC saved seconds (low) Table 148 • LTC Saved Seconds (Low) Register Bit Name Description Access Default 31:0 LTC_SAVED_SEC_L LTC saved seconds (low) R/O 0x00000000 4.11.7 LTC Saved Nanoseconds Short Name: LTC_SAVED_NS Address: 0x16 LTC saved nanoseconds Table 149 • LTC Saved Nanoseconds Register Bit Name Description Access Default 31:0 LTC_SAVED_NS LTC load nanoseconds R/O 0x00000000 4.11.8 LTC Sequence Configuration Short Name: LTC_SEQUENCE Address: 0x17 LTC sequence configuration Table 150 • LTC Sequence Configuration Register Bit Name Description Access Default 19:12 Reserved Must be set to its default. R/W 0x01 11:8 Reserved Must be set to its default. R/W 0x4 7:4 Reserved Must be set to its default. R/W 0x4 3:0 LTC_SEQUENCE_A LTC sequence of increments (nanoseconds) R/W 0x4 4.11.9 LTC Sequence Configuration Short Name: LTC_SEQ Address: 0x18 LTC sequence configuration Table 151 • LTC Sequence Configuration Register Bit Name Description Access Default 20 Reserved Must be set to its default. R/W 0x1 19 LTC_SEQ_ADD_SUB LTC sequence correction sign 0: subtract 1ns adjustment 1: add 1ns adjustment R/W 0x1 VMDS-10509 VSC8572-02 Datasheet Revision 4.2 149 Table 151 • LTC Sequence Configuration Register (continued) Bit Name Description Access Default 18:0 LTC_SEQ_E LTC sequence correction (nanoseconds * 1 million) Example for 6.4 ns period (156.25MHz): LTC_SEQUENCE.LTC_SEQUENCE_A = 6 (6 ns) LTC_SEQ.LTC_SEQ_ADD_SUB = 1 (add 1ns) LTC_SEQ.LTC_SEQ_E = 400000 (0.4ns * 1,000,000) R/W 0x00000 4.11.10 LTC Auto Adjustment Short Name: LTC_AUTO_ADJUST Address: 0x1A LTC auto adjustment Table 152 • LTC Auto Adjustment Register Bit Name 31:30 29:0 4.12 Description Access Default LTC_AUTO_ADD_SUB_1NS LTC auto adjustment add/subtract 1ns 0,3: No adjustment 1: Adjust by adding 1ns upon rollover. 2: Adjust by subtracting 1ns upon rollover. R/W 0x0 LTC_AUTO_ADJUST_NS R/W 0x00000000 LTC auto adjustment rollover (nanoseconds) Timestamp FIFO Serial Interface Registers This section provides information about the timestamp FIFO serial interface registers. 4.12.1 Timestamp FIFO Serial Interface Configuration Short Name: TS_FIFO_SI_CFG Address: 0x20 Polarity and cycle counts are configurable from port 0 only. Table 153 • Timestamp FIFO Serial Interface Configuration Register Bit Name Description Access Default 25 SI_CLK_PHA Timestamp serial interface clock phase control. 0=SPI_CLK falling edge changes output data 1=SPI_CLK rising edge changes output data R/W 0x0 24 SI_CLK_POL Timestamp FIFO serial interface clock polarity control. 0=SPI_CLK starts and ends (idles) low 1=SPI_CLK starts and ends (idles) high R/W 0x0 23:20 SI_EN_DES_CYCS Number of CSR clock periods SPI_CS negates between writes (deselected). The CSR clock frequency is one-half the XREFCK frequency. R/W 0x0 VMDS-10509 VSC8572-02 Datasheet Revision 4.2 150 Table 153 • Timestamp FIFO Serial Interface Configuration Register (continued) Bit Name Description 10:6 SI_CLK_HI_CYCS Number of CSR clock periods that the SPI_CLK R/W is high. Registers SI_CLK_HI_CYCS and SI_CLK_LO_CYCS determine the frequency of the SPI_CLK pin when the timestamp FIFO serial interface is enabled. The CSR clock frequency is one-half the XREFCK frequency. Zero is an invalid setting. 0x02 5:1 SI_CLK_LO_CYCS Number of CSR clock periods that the SPI_CLK R/W is low. Registers SI_CLK_HI_CYCS and SI_CLK_LO_CYCS determine the frequency of the SPI_CLK pin when the timestamp FIFO serial interface is enabled. The CSR clock frequency is one-half the XREFCK frequency. Zero is an invalid setting. 0x02 0 TS_FIFO_SI_ENA When 1, the Timestamp FIFO Serial Interface block is enabled 0=Disabled 1=Enabled R/W 0x0 4.12.2 Access Default Transmitted Timestamp Count Short Name: TS_FIFO_SI_TX_CNT Address: 0x21 Counter for the number of timestamps transmitted to the interface. Table 154 • Transmitted Timestamp Count Register Bit Name Description Access Default 31:0 TS_FIFO_SI_TX_CNT Counter value R/W 0x00000000 4.13 Ingress (Rx) Registers This section provides information about the ingress registers. 4.13.1 Ingress Configuration Short Name: IG_CFG Address: 0x22 Table 155 • Ingress Configuration Register Bit Name Description Access Default 0 IG_ENABLE When 1, the Ingress prediction block is enabled 0=Disabled 1=Enabled R/W 0x0 4.14 Egress (Tx) Registers This section provides information about the egress registers. 4.14.1 Egress Configuration Short Name: EG_CFG VMDS-10509 VSC8572-02 Datasheet Revision 4.2 151 Address: 0x26 Table 156 • Egress Configuration Register Bit Name Description 0 EG_ENABLE When 1, the Egress prediction block is enabled. R/W 0=Disabled 1=Enabled 4.15 Access Default 0x0 1588 IP Ingress Control and Status Registers This section provides information about the 1588 IP control and status registers. 4.15.1 IP 1588 Interrupt Status Short Name: INGR_INT_STATUS Address: 0x2D Status sticky conditions for the 1588 IP Table 157 • IP 1588 Interrupt Status Register Bit Name Description Access Default 6 INGR_ANALYZER_ERROR_STICK Y Indicates that more than one engine has produced a match 0: No error found 1: Duplicate match found Sticky 0x0 5 INGR_RW_PREAMBLE_ERR_STIC When set, indicates that a preamble that was too Sticky KY short to modify was detected in a PTP frame. Write to 0 to clear. This occurs when the Rewriter needs to shrink the preamble to append a timestamp but cannot because the preamble is too short. A short preamble is any preamble that is less than 8 characters long including the XGMII /S/ character and the ending SFD of 0xD5. Other preamble values are not checked, only the length. 0: No error 1: Preamble too short error 0x0 4 INGR_RW_FCS_ERR_STICKY When set, indicates that an FCS error was detected in a PTP frame. Write to 0 to clear. 0: No error 1: FCS error Sticky 0x0 3 INGR_TS_LEVEL_STICKY Reserved Sticky 0x0 2 INGR_TS_LOADED_STICKY When set, indicates a timestamp was captured in Sticky the Timestamp FIFO. The sticky bit should be reset by writing it to zero. 0: No overflow 1: Overflow 0x0 1 INGR_TS_UNDERFLOW_STICKY When set, indicates an underflow in the Timestamp FIFO. The sticky bit should be reset by writing it to zero. 0: No overflow 1: Overflow 0x0 VMDS-10509 VSC8572-02 Datasheet Revision 4.2 Sticky 152 Table 157 • IP 1588 Interrupt Status Register (continued) Bit Name Description Access Default 0 INGR_TS_OVERFLOW_STICKY When set, indicates an overflow in the Timestamp FIFO. The sticky bit should be reset by writing it to zero. 0: No overflow 1: Overflow Sticky 0x0 4.15.2 IP 1588 Interrupt Mask Short Name: INGR_INT_MASK Address: 0x2E Masks that enable and disable the interrupts Table 158 • IP 1588 Interrupt Mask Register Bit Name Description Access Default 6 INGR_ANALYZER_ERROR_MAS K Mask bit for ANALYZER_ERROR_STICKY bit. 0: Interrupt disabled 1: Interrupt enabled R/W 0x0 5 INGR_RW_PREAMBLE_ERR_MA Mask for the RW_PREAMBLE_ERR_STICKY SK bit. 0: Interrupt disabled 1: Interrupt enabled R/W 0x0 4 INGR_RW_FCS_ERR_MASK Mask for the RW_FCS_ERR_STICKY bit. 0: Interrupt disabled 1: Interrupt enabled R/W 0x0 3 INGR_TS_LEVEL_MASK Reserved. Do not modify setting. R/W 0x0 2 INGR_TS_LOADED_MASK Mask bit for TS_LOADED_STICKY. When 1, the R/W interrupt is enabled. 0: Interrupt disabled 1: Interrupt enabled 0x0 1 INGR_TS_UNDERFLOW_MASK Mask bit for TS_UNDERFLOW_STICKY. When 1, the interrupt is enabled. 0: Interrupt disabled 1: Interrupt enabled R/W 0x0 0 INGR_TS_OVERFLOW_MASK Mask bit for TS_OVERFLOW_STICKY. When 1, R/W the interrupt is enabled. 0: Interrupt disabled 1: Interrupt enabled 0x0 4.15.3 Spare Scratchpad Short Name: INGR_SPARE_REGISTER Address: 0x2F Table 159 • Spare Scratchpad Register Bit Name Description 31:0 INGR_SPARE_REGISTER Spare scratchpad register VMDS-10509 VSC8572-02 Datasheet Revision 4.2 Access Default R/W 0x00000000 153 4.16 1588 IP Ingress Timestamp Processor Registers This section provides information about the 1588 IP timestamp processor registers. 4.16.1 TSP Control Short Name: INGR_TSP_CTRL Address: 0x35 Table 160 • TSP Control Register Bit Name 2 INGR_FRACT_NS_MODE Selects a mode in which the fractional portion of R/W a second (in units of nanoseconds) is used for timestamping. Only the operation of the WRITE_NS, WRITE_NS_P2P, and SUB_ADD PTP commands are affected by the setting of this mode bit. 0: Select the total (summed) nanoseconds for timestamping. 1: Select the fractional portion in nanoseconds for timestamping. 0x0 1 INGR_SEL_EXT_SOF_IN D Select external pin start of frame indicator. 0: Select internal PCS as the source of SOF 1: Select external pin as the source of SOF. R/W 0x0 0 INGR_LOAD_DELAYS One-shot loads Local latency, Path delay, and DelayAsymmetry values into the Timestamp Processor One-shot 0x0 4.16.2 Description Access Default TSP Status Short Name: INGR_TSP_STAT Address: 0x36 Table 161 • TSP Status Register Bit Name 0 INGR_CF_TOO_BIG_STICK Timestamp processor marked a calculated Y correction field as too big. 0: A calculated correction field that was too big did occur. 1: A calculated correction field that was too big did not occur. 4.16.3 Description Access Default Sticky 0x0 Local Latency Short Name: INGR_LOCAL_LATENCY VMDS-10509 VSC8572-02 Datasheet Revision 4.2 154 Address: 0x37 Table 162 • Local Latency Register Bit Name 15:0 INGR_LOCAL_LATENC Local latency (nanoseconds) R/W Y The value programmed in this register is dependent upon the frequency of the clock driving the Local Time Counter (LTC) and upon LAN mode of operation. When in LAN mode and the LTC clock frequency is 250 MHz, set this register to 106. When in LAN mode and the LTC clock frequency is 125 MHz, set this register to 112. 4.16.4 Description Access Default 0x0000 Path Delay Short Name: INGR_PATH_DELAY Address: 0x38 Table 163 • Path Delay Register Bit Name Description Access Default 31:0 INGR_PATH_DELAY Path delay (nanoseconds) R/W 0x00000000 4.16.5 DelayAsymmetry Short Name: INGR_DELAY_ASYMMETRY Address: 0x39 Table 164 • DelayAsymmetry Register Bit Name 31:0 INGR_DELAY_ASYMMETRY DelayAsymmetry (scaled nanoseconds) 4.17 Description Access Default R/W 0x00000000 1588 IP Ingress Delay FIFO Registers This section provides information about the 1588 delay FIFO registers. The delay FIFO delays the data in a pipeline governed by these settings. 4.17.1 Configuration and Control for the Delay FIFO Short Name: INGR_DF_CTRL Address: 0x3A Table 165 • Configuration and Control Register for the Delay FIFO Bit Name Description 4:0 INGR_DF_DEPTH The index of the register stage in the Delay FIFO that is used for R/W output. The actual delay through the block is one more than the depth. If depth is set to 2, then the delay is 3 clocks as data is taken from stage 2. The depth MUST be greater than 0 (depth of 0 is not allowed). This bit group must be set to 0x0F in the device. VMDS-10509 VSC8572-02 Datasheet Revision 4.2 Access Default 0x00 155 4.18 1588 IP Ingress Rewriter Registers This section provides information about the 1588 IP rewriter registers. 4.18.1 Rewriter Configuration and Control Short Name: INGR_RW_CTRL Address: 0x44 Configuration for the Rewriter Table 166 • Rewriter Configuration and Control Register Bit Name 4 INGR_RW_REDUCE_PREAMBL When set, the 1588 IP will reduce the preamble E of ALL incoming frames by 4 bytes to allow a timestamp to be appended to the ingress data frames. This bit must be set along with proper configuration of the Analyzer to ensure proper operation. ** VALID IN INGRESS DIRECTION ONLY ** 0: No preamble modification 1: Reduce preamble by 4 bytes 3 2:0 4.18.2 Description Access Default R/W 0x0 INGR_RW_FLAG_VAL Value to write to the flag bit when it is overwritten. R/W 0: '0' will be written to the flag bit 1: '1' will be written to the flag bit 0x0 INGR_RW_FLAG_BIT Bit offset within a byte of the flag bit which indicates if the frame has been modified or not. Binary number 0x0 R/W Count of Modified Frames Short Name: INGR_RW_MODFRM_CNT Address: 0x45 Table 167 • Count of Modified Frames Register Bit Name 31:0 INGR_RW_MODFRM_CN Count of the number of frames modified by the T 1588 IP. The counter wraps. Binary number 4.18.3 Description Access Default R/W 0x00000000 Access Default R/W 0x00000000 Count of FCS Errors Short Name: INGR_RW_FCS_ERR_CNT Address: 0x46 Table 168 • Count of FCS Errors Register Bit Name Description 31:0 INGR_RW_FCS_ERR_CN Count of the number of FCS errored frames T detected by the Rewriter. Binary number VMDS-10509 VSC8572-02 Datasheet Revision 4.2 156 4.18.4 Count of the Number of Preamble Errors Short Name: INGR_RW_PREAMBLE_ERR_CNT Address: 0x47 Table 169 • Count of the Number of Preamble Errors Register Bit Name Description Access Default 31:0 INGR_RW_PREAMBLE_ERR_C NT Count of the number of errored preambles detected. The counter wraps. An errored preamble is a preamble that is too short to shrink that is encountered when RW_REDUCE_PREAMBLE is set. Binary number R/W 0x00000000 4.19 1588 IP Egress Control & Status Registers This section provides information about the 1588 IP control and status registers. 4.19.1 IP 1588 Interrupt Status Short Name: EGR_INT_STATUS Address: 0x4D Status sticky conditions for the 1588 IP Table 170 • IP 1588 Interrupt Status Register Bit Name 6 EGR_ANALYZER_ERROR_STICK Indicates that more than one engine has produced Sticky Y a match 0: No error found 1: Duplicate match found Description 0x0 5 EGR_RW_PREAMBLE_ERR_STIC When set, indicates that a preamble that was too Sticky KY short to modify was detected in a PTP frame. Write to 0 to clear. This occurs when the Rewriter needs to shrink the preamble to append a timestamp but cannot because the preamble is too short. A short preamble is any preamble that is less than 8 characters long including the XGMII /S/ character and the ending SFD of 0xD5. Other preamble values are not checked, only the length. 0: No error 1: Preamble too short error 0x0 4 EGR_RW_FCS_ERR_STICKY When set, indicates that an FCS error was detected in a PTP frame. Write to 0 to clear. 0: No error 1: FCS error Sticky 0x0 3 EGR_TS_LEVEL_STICKY When set, indicates that the level in the Timestamp Sticky FIFO has reached the threshold EGR_TS_THRESH. The sticky bit should be reset by writing it to zero. 0: Egress timestamp FIFO threshold not reached 1: Egress timestamp FIFO threshold reached 0x0 VMDS-10509 VSC8572-02 Datasheet Revision 4.2 Access Default 157 Table 170 • IP 1588 Interrupt Status Register (continued) Bit Name Description 2 EGR_TS_LOADED_STICKY When set, indicates a timestamp was captured in Sticky the Timestamp FIFO. The sticky bit should be reset by writing it to zero. 0: Egress timestamp FIFO not loaded 1: Egress timestamp FIFO loaded 0x0 1 EGR_TS_UNDERFLOW_STICKY When set, indicates an underflow in the Timestamp Sticky FIFO. The sticky bit should be reset by writing it to zero. 0: No underflow 1: Underflow 0x0 0 EGR_TS_OVERFLOW_STICKY When set, indicates an overflow in the Timestamp Sticky FIFO. The sticky bit should be reset by writing it to zero. 0: No overflow 1: Overflow 0x0 4.19.2 Access Default IP 1588 Interrupt Mask Short Name: EGR_INT_MASK Address: 0x4E Masks that enable and disable the interrupts Table 171 • IP 1588 Interrupt Mask Register Bit Name 6 Description Access Default EGR_ANALYZER_ERROR_MASK Mask bit for ANALYZER_ERROR_STICKY bit. 0: Interrupt disabled 1: Interrupt enabled R/W 0x0 5 EGR_RW_PREAMBLE_ERR_MA Mask for the RW_PREAMBLE_ERR_STICKY SK bit. 0: Interrupt disabled 1: Interrupt enabled R/W 0x0 4 EGR_RW_FCS_ERR_MASK Mask for the RW_FCS_ERR_STICKY bit. 0: Interrupt disabled 1: Interrupt enabled R/W 0x0 3 EGR_TS_LEVEL_MASK Mask bit for EGR_TS_LEVEL_STICKY. When 1, R/W the interrupt is enabled. 0: Interrupt disabled 1: Interrupt enabled 0x0 2 EGR_TS_LOADED_MASK Mask bit for TS_LOADED_STICKY. When 1, the R/W interrupt is enabled. 0: Interrupt disabled 1: Interrupt enabled 0x0 1 EGR_TS_UNDERFLOW_MASK Mask bit for TS_UNDERFLOW_STICKY. When 1, the interrupt is enabled. 0: Interrupt disabled 1: Interrupt enabled 0x0 VMDS-10509 VSC8572-02 Datasheet Revision 4.2 R/W 158 Table 171 • IP 1588 Interrupt Mask Register (continued) Bit Name Description 0 EGR_TS_OVERFLOW_MASK Mask bit for TS_OVERFLOW_STICKY. When 1, R/W the interrupt is enabled. 0: Interrupt disabled 1: Interrupt enabled 4.19.3 Access Default 0x0 Spare Scratchpad Short Name: EGR_SPARE_REGISTER Address: 0x4F Table 172 • Spare Scratchpad Register Bit Name 31:0 EGR_SPARE_REGISTER Spare scratchpad register 4.20 Description Access Default R/W 0x00000000 1588 IP Egress Timestamp Processor Registers This section provides information about the 1588 IP timestamp processor registers. 4.20.1 TSP Control Short Name: EGR_TSP_CTRL Address: 0x55 Table 173 • TSP Control Register Bit Name 2 EGR_FRACT_NS_MODE Selects a mode in which the fractional portion of a second (in R/W units of nanoseconds) is used for timestamping. Only the operation of the WRITE_NS, WRITE_NS_P2P, and SUB_ADD PTP commands are affected by the setting of this mode bit. 0: Select the total (summed) nanoseconds for timestamping. 1: Select the fractional portion in nanoseconds for timestamping. 0x0 1 EGR_SEL_EXT_SOF_IN D Select external pin start of frame indicator. 0: Select internal PCS as the source of SOF 1: Select external pin as the source of SOF. R/W 0x0 0 EGR_LOAD_DELAYS One-shot loads Local latency, Path delay, and DelayAsymmetry values into the Timestamp Processor One-shot 0x0 4.20.2 Description Access Default TSP Status Short Name: EGR_TSP_STAT VMDS-10509 VSC8572-02 Datasheet Revision 4.2 159 Address: 0x56 Table 174 • TSP Status Register Bit Name 0 EGR_CF_TOO_BIG_STICK Timestamp processor marked a calculated correction field Sticky Y as too big. 0: A calculated correction field that was too big did occur. 1: A calculated correction field that was too big did not occur. 4.20.3 Description Access Default 0x0 Local Latency Short Name: EGR_LOCAL_LATENCY Address: 0x57 Table 175 • Local Latency Register Bit Name 15:0 EGR_LOCAL_LATENC Local latency (nanoseconds) R/W Y The value programmed in this register is dependent upon the frequency of the clock driving the Local Time Counter (LTC) and upon LAN mode of operation. When in LAN mode and the LTC clock frequency is 250 MHz, set this register to 206. When in LAN mode and the LTC clock frequency is 125 MHz, set this register to 200. 4.20.4 Description Access Default 0x0000 Path Delay Short Name: EGR_PATH_DELAY Address: 0x58 Table 176 • Path Delay Register Bit Name Description Access Default 31:0 EGR_PATH_DELAY Path delay (nanoseconds) R/W 0x00000000 Access Default R/W 0x00000000 4.20.5 DelayAsymmetry Short Name: EGR_DELAY_ASYMMETRY Address: 0x59 Table 177 • DelayAsymmetry Register Bit Name 31:0 EGR_DELAY_ASYMMETR DelayAsymmetry (scaled nanoseconds) Y 4.21 Description 1588 IP Egress Delay FIFO Registers This section provides information about the 1588 IP delay FIFO registers. The delay FIFO delays the data in a pipeline governed by these settings. VMDS-10509 VSC8572-02 Datasheet Revision 4.2 160 4.21.1 Configuration and Control for the Delay FIFO Short Name: EGR_DF_CTRL Address: 0x5A Table 178 • Configuration and Control Register for the Delay FIFO Bit Name 4:0 EGR_DF_DEPTH The index of the register stage in the Delay FIFO that is used for R/W output. The actual delay through the block is one more than the depth. If depth is set to 2, then the delay is 3 clocks as data is taken from stage 2. The depth MUST be greater than 0 (depth of 0 is not allowed). This bit group must be set to 0x0F in the device. 4.22 Description Access Default 0x00 1588 IP Egress Timestamp FIFO Registers This section provides information about the egress timestamp FIFO. 4.22.1 Timestamp FIFO Configuration and Status Short Name: EGR_TSFIFO_CSR Address: 0x5B Configuration and status register for the Timestamp FIFO Table 179 • Timestamp FIFO Configuration and Status Register Bit Name Description Access Default 17 EGR_TS_4BYTES Selects a smaller timestamp size to be stored in the Timestamp FIFO (4 bytes vs. the default 10 bytes). 0: full 10 byte timestamps are stored 1: Only 4 bytes of each timestamp are stored. R/W 0x0 16 EGR_TS_FIFO_RESET Forces the Timestamp_FIFO into the reset state. R/W 0x0 15:12 EGR_TS_LEVEL The FIFO level associated with the last read of the EGR_TS_EMPTY status field of the EGR_TSFIFO_0 register. Binary number (0-8) R/O 0x0 11:8 EGR_TS_THRESH The threshold at which the Timestamp FIFO interrupt EGR_TS_LEVEL_STICKY will be set. If the FIFO level reaches the threshold, the sticky bit EGR TS_LEVEL_STICKY will be set. Binary number (1-8) R/W 0x3 4:0 EGR_TS_SIGNAT_BYTES Indicates the number of signature bytes used for timestamps R/W in the Timestamp FIFO (0-16). 4.22.2 0x00 Data Value from the Timestamp FIFO Short Name: EGR_TSFIFO_0 Address: 0x5C VMDS-10509 VSC8572-02 Datasheet Revision 4.2 161 Read the data from the timestamp FIFO along with the FIFO empty flag in the MSB Table 180 • Data Value from the Timestamp FIFO Register Bit Name 31 EGR_TS_EMPT The FIFO empty flag from the Timestamp FIFO. If this bit is set, there R/O Y is no FIFO data to be read from the FIFO. The data in the TSFIFO_x registers is not valid and should be discarded. When 0, the FIFO has data and the TSFIFO_x has a valid set of data. This register can be polled and when the bit is cleared, the other registers should be read to get a full timestamp. When 1, the last data has already been read out and the current read data should be discarded. Timestamp/Frame signature bytes are packed such that the 10 or 4 byte Timestamp resides in the LEAST significant bytes while the Frame signature (0 to 16 bytes) resides in the MOST significant bytes. The order of the bytes within each Timestamp/Frame signature field is also most significant to least significant. For example, a 26 byte timestamp/frame signature pairs are packed with the 10 byte timestamp field ([79:0]) corresponding to Bits 79:0 in the registers below, and a 16 byte frame signature field ([127:0]) corresponding to Bits 207:80 in the registers below. 0: FIFO not empty, data valid 1: FIFO empty, data invalid 0x1 30:28 EGR_TS_FLAG The FIFO flags from the Timestamp FIFO. These bits indicate how R/O S many timestamps are valid in the current (not empty) 26 byte FIFO entry. 000: Only the end of a partial timestamp is valid in the current FIFO entry (any remaining data is invalid) 001: 1 valid timestamp begins in the current FIFO entry (any remaining data is invalid) 010: 2 valid timestamps begin in the current FIFO entry (any remaining data is invalid) 011: 3 valid timestamps begin in the current FIFO entry (any remaining data is invalid) 100: 4 valid timestamps begin in the current FIFO entry (any remaining data is invalid) 101: 5 valid timestamps begin in the current FIFO entry (any remaining data is invalid) 110: 6 valid timestamps begin in the current FIFO entry (any remaining data is invalid) 111: The current FIFO entry is fully packed with timestamps (all data is valid) N/A 15:0 EGR_TSFIFO_0 16 bits from the Timestamp FIFO. Bits 15:0. N/A 4.22.3 Description Access Default R/O Data Value from the Timestamp FIFO Short Name: EGR_TSFIFO_1 Address: 0x5D Read the data from the timestamp FIFO Table 181 • Data Value from the Timestamp FIFO Register Bit Name Description Access Default 31:0 EGR_TSFIFO_1 32 bits from the Timestamp FIFO. Bits 47:16. R/O N/A VMDS-10509 VSC8572-02 Datasheet Revision 4.2 162 4.22.4 Data Value from the Timestamp FIFO Short Name: EGR_TSFIFO_2 Address: 0x5E Read the data from the timestamp FIFO Table 182 • Data Value from the Timestamp FIFO Register Bit Name Description Access Default 31:0 EGR_TSFIFO_2 32 bits from the Timestamp FIFO. Bits 79:48. R/O N/A 4.22.5 Data Value from the Timestamp FIFO Short Name: EGR_TSFIFO_3 Address: 0x5F Read the data from the timestamp FIFO Table 183 • Data Value from the Timestamp FIFO Register Bit Name Description Access Default 31:0 EGR_TSFIFO_3 32 bits from the Timestamp FIFO. Bits 111:80. R/O N/A 4.22.6 Data Value from the Timestamp FIFO Short Name: EGR_TSFIFO_4 Address: 0x60 Read the data from the timestamp FIFO Table 184 • Data Value from the Timestamp FIFO Register Bit Name Description Access Default 31:0 EGR_TSFIFO_4 32 bits from the Timestamp FIFO. Bits 143:112. R/O N/A 4.22.7 Data Value from the Timestamp FIFO Short Name: EGR_TSFIFO_5 Address: 0x61 Read the data from the timestamp FIFO Table 185 • Data Value from the Timestamp FIFO Register Bit Name Description Access Default 31:0 EGR_TSFIFO_5 32 bits from the Timestamp FIFO. Bits 175:144. R/O N/A 4.22.8 Data Value from the Timestamp FIFO Short Name: EGR_TSFIFO_6 Address: 0x62 VMDS-10509 VSC8572-02 Datasheet Revision 4.2 163 Read the data from the timestamp FIFO Table 186 • Data Value from the Timestamp FIFO Register Bit Name Description Access Default 31:0 EGR_TSFIFO_6 32 bits from the Timestamp FIFO. Bits 207:176. R/O N/A 4.22.9 Count of Dropped Timestamps Short Name: EGR_TSFIFO_DROP_CNT Address: 0x63 Count of dropped Timestamps not enqueued to the TS FIFO Table 187 • Count of Dropped Timestamps Register Bit Name Description Access Default 31:0 EGR_TS_FIFO_DROP_C NT Timestamps dropped count R/W 0x00000000 4.23 1588 IP Egress Rewriter Registers This section provides information about the 1588 IP rewriter configuration and status registers. 4.23.1 Rewriter Configuration and Control Short Name: EGR_RW_CTRL Address: 0x64 Configuration for the Rewriter Table 188 • Rewriter Configuration and Control Register Bit Name 4 EGR_RW_REDUCE_PREAMBL When set, the 1588 IP will reduce the preamble E of ALL incoming frames by 4 bytes to allow a timestamp to be appended to the ingress data frames. This bit must be set along with proper configuration of the Analyzer to ensure proper operation. ** VALID IN INGRESS DIRECTION ONLY ** 0: No preamble modification 1: Reduce preamble by 4 bytes 3 2:0 4.23.2 Description Access Default R/W 0x0 EGR_RW_FLAG_VAL Value to write to the flag bit when it is overwritten. R/W 0: 0 will be written to the flag bit 1: 1 will be written to the flag bit 0x0 EGR_RW_FLAG_BIT Bit offset within a byte of the flag bit which indicates if the frame has been modified or not. Binary number 0x0 R/W Count of Modified Frames Short Name: EGR_RW_MODFRM_CNT VMDS-10509 VSC8572-02 Datasheet Revision 4.2 164 Address: 0x65 Table 189 • Count of Modified Frames Register Bit Name 31:0 EGR_RW_MODFRM_CNT Count of the number of frames modified by the 1588 IP. The counter wraps. Binary number 4.23.3 Description Access Default R/W 0x00000000 Access Default R/W 0x00000000 Count of FCS Errors Short Name: EGR_RW_FCS_ERR_CNT Address: 0x66 Table 190 • Count of FCS Errors Register Bit Name 31:0 EGR_RW_FCS_ERR_CNT Count of the number of FCS errored frames detected by the Rewriter. Binary number 4.23.4 Description Count of the Number of Preamble Errors Short Name: EGR_RW_PREAMBLE_ERR_CNT Address: 0x67 Table 191 • Count of the Number of Preamble Errors Register Bit Name 31:0 EGR_RW_PREAMBLE_ERR_C Count of the number of errored preambles NT detected. The counter wraps. An errored preamble is a preamble that is too short to shrink that is encountered when RW_REDUCE_PREAMBLE is set. Binary number 4.24 Description Access Default R/W 0x00000000 1588 IP Ingress Debug Register This section provides information about reading the 1588 IP internal registers. 4.24.1 Software Pop FIFO Short Name: INGR_SW_POP_FIFO Address: 0x9F Table 192 • INGR_SW_POP_FIFO Field Name Bit Access Description INGR_SAFE_MODCHG_DIS 13 R/W When set low, the mode change is a controlled process 0x0 that first forces bypass mode, then takes effect after processing a single IDLE, then releases bypass mode. When asserted high, changes to PROTOCOL_MODE take immediate effect. 0= Follow controlled mode changes 1= Mode changes take immediate effect Reserved 12 R/W 0x0 VMDS-10509 VSC8572-02 Datasheet Revision 4.2 Default 165 Table 192 • INGR_SW_POP_FIFO (continued) Field Name Bit Access Description Default INGR_BYPASS_ON 11 R/W Sticky bit. Indicates 1588 bypass is ON. Always clears by writing 1. 0x01 INGR_BYPASS_IDLE 10 R/W Sticky bit. Indicates 1588 has encountered at least one 0x0 IDLE at input and in process of asserting bypass. Always clears by writing 1. INGR_FIFO_LVL_OFF 9 R/W Sticky bit. Indicates FIFO levels are non-zero in steady 0x0 state and were automatically emptied. Always clears by writing 1. INGR_AUTO_CLR_DONE 8 R/W Sticky bit. If 1, indicates auto-clear operation was completed. Always clears by writing 1. INGR_AUTO_CLR_CLKS 7:2 R/W Only valid when AUTO_CLR_EN is high. After 0x1A encountering AUTO_CLR_CLKS (‘n’ number of IDLEs), 1588 datapath FIFOs will empty. Only valid for number greater than or equal to 0x1A. 1G: needs ‘n+1’*8 clock cycles 100M: needs ‘n+1’*80 clock cycles 10M: needs ‘n+1’*800 clock cycles INGR_AUTO_CLR_EN 1 R/W If enabled, 1588 will detect when FIFOs contain stale entries. If contains entries in steady-state, then after encountering AUTO_CLR_CLKS number of IDLEs, all 1588 FIFOs will automatically empty. INGR_SW_POP_FIFO 0 R/W Self-clearing bit to manually drain all FIFOs within 1588. 0x0 Should only be asserted when 1588 is in the steadystate. 1. 0x0 0x1 Bit may not be valid until a clear-by-write has been performed after a device power-on. 4.25 1588 IP Egress Debug Registers This section provides information about reading the 1588 IP internal registers. 4.25.1 Software Pop FIFO Short Name: EGR_SW_POP_FIFO Address: 0xC0 Table 193 • EGR_SW_POP_FIFO Field Name Bit Access Description EGR_SAFE_MODCHG_DIS 13 R/W When set low, the mode change is a controlled process 0x0 that first forces bypass mode, then takes effect after processing a single IDLE, then releases bypass mode. When asserted high, changes to PROTOCOL_MODE take immediate effect. 0= Follow controlled mode changes 1= Mode changes take immediate effect Reserved 12 R/W 0x0 EGR_BYPASS_ON 11 R/W Sticky bit. Indicates 1588 bypass is ON. Always clears by writing 1. VMDS-10509 VSC8572-02 Datasheet Revision 4.2 Default 0x01 166 Table 193 • EGR_SW_POP_FIFO (continued) Field Name Bit Access Description EGR_BYPASS_IDLE 10 R/W Sticky bit. Indicates 1588 has encountered at least one 0x0 IDLE at input and in process of asserting bypass. Always clears by writing 1. EGR_FIFO_LVL_OFF 9 R/W Sticky bit. Indicates FIFO levels are non-zero in steady 0x0 state and were automatically emptied. Always clears by writing 1. EGR_AUTO_CLR_DONE 8 R/W Sticky bit. If 1, indicates auto-clear operation was completed. Always clears by writing 1. EGR_AUTO_CLR_CLKS 7:2 R/W Only valid when AUTO_CLR_EN is high. After 0x1A encountering AUTO_CLR_CLKS (‘n’ number of IDLEs), 1588 datapath FIFOs will empty. Only valid for number greater than or equal to 0x1A. 1G: needs ‘n+1’*8 clock cycles 100M: needs ‘n+1’*80 clock cycles 10M: needs ‘n+1’*800 clock cycles EGR_AUTO_CLR_EN 1 R/W If enabled, 1588 will detect when FIFOs contain stale entries. If contains entries in steady-state, then after encountering AUTO_CLR_CLKS number of IDLEs, all 1588 FIFOs will automatically empty. EGR_SW_POP_FIFO 0 R/W Self-clearing bit to manually drain all FIFOs within 1588. 0x0 Should only be asserted when 1588 is in the steadystate. 1. Default 0x0 0x1 Bit may not be valid until a clear-by-write has been performed after a device power-on. 4.26 Ingress0 Analyzer Engine Configuration Registers This section lists overviews for the ingress0 analyzer engine configuration registers.Ingress1 analyzer engine registers are identical to the ones defined for ingress0. Note: The analyzer engine configuration registers are not initialized to the default values during chip reset. Software must configure these registers to their default value. Note: For more information about accessing the 1588 IP registers, see Accessing 1588 IP Registers, page 72. Table 194 • INGR0_ETH1_NXT_PROTOCOL Address Name Details 0x00 INGR0_ETH1_NXT_PROTOCOL Ethernet Next Protocol, page 171 0x01 INGR0_ETH1_VLAN_TPID_CFG VLAN TPID Configuration, page 172 0x02 INGR0_ETH1_TAG_MODE Ethernet Tag Mode, page 172 0x03 INGR0_ETH1_ETYPE_MATCH Ethertype Match, page 172 Table 195 • INGR0_ETH1_FLOW_CFG (8 instances) Address Name Details 0x10 INGR0_ETH1_FLOW_ENABLE Ethernet Flow Enable, page 173 0x11 INGR0_ETH1_MATCH_MODE Ethernet Protocol Match Mode, page 173 0x12 INGR0_ETH1_ADDR_MATCH_1 Ethernet Address Match Part 1, page 174 VMDS-10509 VSC8572-02 Datasheet Revision 4.2 167 Table 195 • INGR0_ETH1_FLOW_CFG (8 instances) (continued) Address Name Details 0x13 INGR0_ETH1_ADDR_MATCH_2 Ethernet Address Match Part 2, page 175 0x14 INGR0_ETH1_VLAN_TAG_RANGE_I Ethernet VLAN Tag Range Match, page 175 _TAG 0x15 INGR0_ETH1_VLAN_TAG1 VLAN Tag 1 Match/Mask, page 176 0x16 INGR0_ETH1_VLAN_TAG2_I_TAG Match/Mask For VLAN Tag 2 or I-Tag Match, page 176 Table 196 • INGR0_ETH2_NXT_PROTOCOL Address Name Details 0x90 INGR0_ETH2_NXT_PROTOCOL Ethernet Next Protocol, page 177 0x91 INGR0_ETH2_VLAN_TPID_CFG VLAN TPID Configuration, page 177 0x92 INGR0_ETH2_ETYPE_MATCH Ethertype Match, page 177 Table 197 • INGR0_ETH2_FLOW_CFG (8 instances) Address Name Details 0xA0 INGR0_ETH2_FLOW_ENABLE Ethernet Flow Enable, page 178 0xA1 INGR0_ETH2_MATCH_MODE Ethernet Protocol Match Mode, page 178 0xA2 INGR0_ETH2_ADDR_MATCH_1 Ethernet Address Match Part 1, page 179 0xA3 INGR0_ETH2_ADDR_MATCH_2 Ethernet Address Match Part 2, page 180 0xA4 INGR0_ETH2_VLAN_TAG_RANGE_I_TA Ethernet VLAN Tag Range Match, page 180 G 0xA5 INGR0_ETH2_VLAN_TAG1 VLAN Tag 1 Match/Mask, page 181 0xA6 INGR0_ETH2_VLAN_TAG2_I_TAG Match/Mask for VLAN Tag 2 or I-Tag Match, page 181 Table 198 • INGR0_MPLS_NXT_COMPARATOR Address Name Details 0x120 INGR0_MPLS_NXT_COMPARAT OR MPLS Next Protocol Comparator, page 182 Table 199 • INGR0_MPLS_FLOW_CFG (8 instances) Address Name Details 0x130 INGR0_MPLS_FLOW_CONTROL MPLS Flow Control, page 182 0x132 INGR0_MPLS_LABEL_RANGE_LOWER MPLS Label 0 Match Range Lower Value, _0 page 183 VMDS-10509 VSC8572-02 Datasheet Revision 4.2 168 Table 199 • INGR0_MPLS_FLOW_CFG (8 instances) (continued) Address Name Details 0x133 INGR0_MPLS_LABEL_RANGE_UPPER MPLS Label 0 Match Range Upper Value, _0 page 183 0x134 INGR0_MPLS_LABEL_RANGE_LOWER MPLS Label 1 Match Range Lower Value, _1 page 184 0x135 INGR0_MPLS_LABEL_RANGE_UPPER MPLS Label 1 Match Range Lower Value, _1 page 184 0x136 INGR0_MPLS_LABEL_RANGE_LOWER MPLS Label 2 Match Range Lower Value, _2 page 185 0x137 INGR0_MPLS_LABEL_RANGE_UPPER MPLS Label 2 Match Range Lower Value, _2 page 185 0x138 INGR0_MPLS_LABEL_RANGE_LOWER MPLS Label 3 Match Range Lower Value, _3 page 185 0x139 INGR0_MPLS_LABEL_RANGE_UPPER MPLS Label 3 Match Range Lower Value, _3 page 186 Table 200 • INGR0_IP1_NXT_PROTOCOL Address Name Details 0x1B0 INGR0_IP1_NXT_COMPARATOR IP Next Comparator Control, page 186 0x1B1 INGR0_IP1_MODE IP Comparator Mode, page 187 0x1B2 INGR0_IP1_PROT_MATCH_1 IP Match Register Set 1, page 187 0x1B3 INGR0_IP1_PROT_MATCH_2_UPPE Upper Portion of Match 2, page 187 R 0x1B4 INGR0_IP1_PROT_MATCH_2_LOWE Lower Portion of Match 2, page 188 R 0x1B5 INGR0_IP1_PROT_MASK_2_UPPER Upper Portion of Match Mask 2, page 188 0x1B6 INGR0_IP1_PROT_MASK_2_LOWER Lower Portion of Match Mask 2, page 188 0x1B7 INGR0_IP1_PROT_OFFSET_2 Match Offset 2, page 188 0x1B8 INGR0_IP1_UDP_CHKSUM_CFG IP/UDP Checksum Control, page 188 Table 201 • INGR0_IP1_FLOW_CFG (8 instances) Address Name Details 0x1C0 INGR0_IP1_FLOW_ENA IP Flow Enable, page 189 0x1C1 INGR0_IP1_FLOW_MATCH_UPPER Upper Portion of the IP Flow Match, page 190 0x1C2 INGR0_IP1_FLOW_MATCH_UPPER_MI Upper Mid Portion of the IP Flow Match, D page 190 0x1C3 INGR0_IP1_FLOW_MATCH_LOWER_MI Lower Mid Portion of the IP Flow Match, D page 191 0x1C4 INGR0_IP1_FLOW_MATCH_LOWER Lower Portion of the IP Flow Match, page 191 VMDS-10509 VSC8572-02 Datasheet Revision 4.2 169 Table 201 • INGR0_IP1_FLOW_CFG (8 instances) (continued) Address Name Details 0x1C5 INGR0_IP1_FLOW_MASK_UPPER IP Flow Match Mask, page 191 0x1C6 INGR0_IP1_FLOW_MASK_UPPER_MID Upper Mid Portion of the IP Flow Mask, page 192 0x1C7 INGR0_IP1_FLOW_MASK_LOWER_MID Lower Mid Portion of the IP Flow Mask, page 192 0x1C8 INGR0_IP1_FLOW_MASK_LOWER Lower Portion of the IP Flow Mask, page 193 Table 202 • INGR0_IP2_NXT_PROTOCOL Address Name Details 0x240 INGR0_IP2_NXT_COMPARATOR IP Next Comparator Control, page 193 0x241 INGR0_IP2_MODE IP Comparator Mode, page 193 0x242 INGR0_IP2_PROT_MATCH_1 IP Match Set 1, page 194 0x243 INGR0_IP2_PROT_MATCH_2_UPPE Upper Portion of Match 2, page 194 R 0x244 INGR0_IP2_PROT_MATCH_2_LOWE Lower Portion of Match 2, page 194 R 0x245 INGR0_IP2_PROT_MASK_2_UPPER Upper Portion of Match Mask 2, page 194 0x246 INGR0_IP2_PROT_MASK_2_LOWE R Lower Portion of Match Mask 2, page 195 0x247 INGR0_IP2_PROT_OFFSET_2 Match Offset 2, page 195 0x248 INGR0_IP2_UDP_CHKSUM_CFG IP/UDP Checksum Control, page 195 Table 203 • INGR0_IP2_FLOW_CFG (8 instances) Address Name Details 0x250 INGR0_IP2_FLOW_ENA IP Flow Enable, page 196 0x251 INGR0_IP2_FLOW_MATCH_UPPER Upper Portion of the IP Flow Match, page 196 0x252 INGR0_IP2_FLOW_MATCH_UPPER_MI Upper Mid Portion of the IP Flow Match, D page 197 0x253 INGR0_IP2_FLOW_MATCH_LOWER_MI Lower Mid Portion of the IP Flow Match, D page 197 0x254 INGR0_IP2_FLOW_MATCH_LOWER Lower Portion of the IP Flow Match, page 198 0x255 INGR0_IP2_FLOW_MASK_UPPER IP Flow Match Mask, page 198 0x256 INGR0_IP2_FLOW_MASK_UPPER_MID Upper Mid Portion of the IP Flow Mask, page 198 0x257 INGR0_IP2_FLOW_MASK_LOWER_MID Lower Mid Portion of the IP Flow Mask, page 199 VMDS-10509 VSC8572-02 Datasheet Revision 4.2 170 Table 203 • INGR0_IP2_FLOW_CFG (8 instances) (continued) Address Name Details 0x258 INGR0_IP2_FLOW_MASK_LOWER Lower Portion of the IP Flow Mask, page 199 Table 204 • INGR0_PTP_FLOW (6 instances) Address Name Details 0x2D0 INGR0_PTP_FLOW_ENA PTP/OAM Flow Enable, page 200 0x2D1 INGR0_PTP_FLOW_MATCH_UPPE Upper Half of PTP/OAM Flow Match Field, R page 200 0x2D2 INGR0_PTP_FLOW_MATCH_LOW ER 0x2D3 INGR0_PTP_FLOW_MASK_UPPER Upper Half of PTP/OAM Flow Match Mask, page 201 0x2D4 INGR0_PTP_FLOW_MASK_LOWE R Lower Half of PTP/OAM Flow Match Mask, page 201 0x2D5 INGR0_PTP_DOMAIN_RANGE PTP/OAM Range Match, page 201 0x2D6 INGR0_PTP_ACTION PTP Action Control, page 202 0x2D7 INGR0_PTP_ACTION_2 PTP Action Control 2, page 203 0x2D8 INGR0_PTP_ZERO_FIELD_CTL Zero Field Control, page 203 Lower Half of PTP/OAM Flow Match Field, page 200 Table 205 • INGR0_PTP_IP_CHKSUM_CTL 4.27 Address Name Details 0x330 INGR0_PTP_IP_CKSUM_SEL IP Checksum Block Select, page 204 Ingress0 Ethernet Next Protocol Configuration Registers This section provides information about the Ethernet next protocol configuration registers. 4.27.1 Ethernet Next Protocol Short Name: INGR0_ETH1_NXT_PROTOCOL Address: 0x00 Table 206 • Ethernet Next Protocol Register Bit Name Description 20:16 INGR0_ETH1_FRAME_SIG_OFFS Frame signature offset. Points to the start of the R/W ET byte field in the Ethernet frame that will be used for the frame signature VMDS-10509 VSC8572-02 Datasheet Revision 4.2 Access Default 0x00 171 Table 206 • Ethernet Next Protocol Register (continued) Bit Name Description Access Default 2:0 INGR0_ETH1_NXT_COMPARATO R Points to the next comparator block after this Ethernet block 0: Reserved 1: Ethernet comparator 2 2: IP/UDP/ACH comparator 1 3: IP/UDP/ACH comparator 2 4: MPLS comparator 5: PTP/OAM comparator 6,7: Reserved R/W 0x0 4.27.2 VLAN TPID Configuration Short Name: INGR0_ETH1_VLAN_TPID_CFG Address: 0x01 Table 207 • VLAN TPID Configuration Register Bit Name Description Access Default 31:16 INGR0_ETH1_VLAN_TPID_CF G Configurable VLAN TPID (S or B-tag) R/W 0x88A8 Access Default 4.27.3 Ethernet Tag Mode Short Name: INGR0_ETH1_TAG_MODE Address: 0x02 Table 208 • Ethernet Tag Mode Register Bit Name Description 0 INGR0_ETH1_PBB_ENA This bit enables the presence of PBB. R/W The I-tag match bits are programmed in the ETH1_VLAN_TAG_RANGE registers. The mask bits are programmed in the ETH1_VLAN_TAG2 registers. A B-tag if present is configured in the ETH1_VLAN_TAG1 registers. 0: PBB not enabled 1: Always expect PBB, last tag is always an I-tag 4.27.4 0x0 Ethertype Match Short Name: INGR0_ETH1_ETYPE_MATCH Address: 0x03 Table 209 • Ethertype Match Register Bit Name Description Access 15:0 INGR0_ETH1_ETYPE_MATCH If the Ethertype/length field is an Ethertype, then R/W this register is compared against the value. If the field is a length, the length value is not checked. Default 0x0000 4.27.5 Instance offsets: 0x10 INGR0_ETH1_FLOW_CFG_0 VMDS-10509 VSC8572-02 Datasheet Revision 4.2 172 0x20 INGR0_ETH1_FLOW_CFG_1 0x30 INGR0_ETH1_FLOW_CFG_2 0x40 INGR0_ETH1_FLOW_CFG_3 0x50 INGR0_ETH1_FLOW_CFG_4 0x60 INGR0_ETH1_FLOW_CFG_5 0x70 INGR0_ETH1_FLOW_CFG_6 0x80 INGR0_ETH1_FLOW_CFG_7 4.27.6 Ethernet Flow Enable Short Name: INGR0_ETH1_FLOW_ENABLE Addresses: 0x10 INGR0_ETH1_FLOW_CFG_0 0x20 INGR0_ETH1_FLOW_CFG_1 0x30 INGR0_ETH1_FLOW_CFG_2 0x40 INGR0_ETH1_FLOW_CFG_3 0x50 INGR0_ETH1_FLOW_CFG_4 0x60 INGR0_ETH1_FLOW_CFG_5 0x70 INGR0_ETH1_FLOW_CFG_6 0x80 INGR0_ETH1_FLOW_CFG_7 Table 210 • Ethernet Flow Enable Register Bit Name Description Access Default 9:8 INGR0_ETH1_CHANNEL_MASK Channel mask bit 0: Flow valid for channel 0 bit 1: Flow valid for channel 1 R/W 0x3 0 INGR0_ETH1_FLOW_ENABLE Flow enable 0: Flow is disabled 1: Flow is enabled R/W 0x0 4.27.7 Ethernet Protocol Match Mode Short Name: INGR0_ETH1_MATCH_MODE Addresses: 0x11 INGR0_ETH1_FLOW_CFG_0 0x21 INGR0_ETH1_FLOW_CFG_1 0x31 INGR0_ETH1_FLOW_CFG_2 0x41 INGR0_ETH1_FLOW_CFG_3 0x51 INGR0_ETH1_FLOW_CFG_4 0x61 INGR0_ETH1_FLOW_CFG_5 0x71 INGR0_ETH1_FLOW_CFG_6 VMDS-10509 VSC8572-02 Datasheet Revision 4.2 173 0x81 INGR0_ETH1_FLOW_CFG_7 Table 211 • Ethernet Protocol Match Mode Register Bit Name Description 13:12 INGR0_ETH1_VLAN_TAG_MODE Access Default R/W 0x0 0: VLAN range checking disabled 1: VLAN range checking on tag 1 2: VLAN range checking on tag 2 (not supported with PBB) 3: reserved 9 INGR0_ETH1_VLAN_TAG2_TYPE This register is only used if ETH1_VLAN_VERIFY_ENA = 1 If PBB not enabled: 0: C tag (TPID of 0x8100) 1: S tag (match to CONF_VLAN_TPID) If PBB enabled: 0,1: I tag (use range registers) R/W 0x1 8 INGR0_ETH1_VLAN_TAG1_TYPE This register is only used if ETH1_VLAN_VERIFY_ENA = 1 0: C tag (TPID of 0x8100) 1: S or B tag (match to CONF_VLAN_TPID) R/W 0x0 7:6 INGR0_ETH1_VLAN_TAGS This register is only used if R/W ETH1_VLAN_VERIFY_ENA = 1 0: No VLAN tags (not valid for PBB) 1: 1 VLAN tag (for PBB this would be the I-tag) 2: 2 VLAN tags (for PBB expect a B-tag and an Itag) 3: Reserved 0x0 4 INGR0_ETH1_VLAN_VERIFY_EN R/W A 0: Parse for VLAN tags, do not check values. For PBB the I-tag is always checked. 1: Verify configured VLAN tag configuration. 0x0 0 INGR0_ETH1_ETHERTYPE_MOD When checking for presence of SNAP/LLC R/W E based upon ETH1_MATCH_MODE, this field indicates if SNAP & 3-byte LLC is expected to be present 0: Only Ethernet type II supported, no SNAP/LLC 1: Ethernet type II & Ethernet type I with SNAP/LLC, determine if SNAP/LLC is present or not. Type I always assumes that SNAP/LLC is present 0x0 4.27.8 Ethernet Address Match Part 1 Short Name: INGR0_ETH1_ADDR_MATCH_1 Addresses: 0x12 INGR0_ETH1_FLOW_CFG_0 0x22 INGR0_ETH1_FLOW_CFG_1 0x32 INGR0_ETH1_FLOW_CFG_2 0x42 INGR0_ETH1_FLOW_CFG_3 0x52 INGR0_ETH1_FLOW_CFG_4 0x62 INGR0_ETH1_FLOW_CFG_5 VMDS-10509 VSC8572-02 Datasheet Revision 4.2 174 0x72 INGR0_ETH1_FLOW_CFG_6 0x82 INGR0_ETH1_FLOW_CFG_7 Table 212 • Ethernet Address Match Part 1 Register Bit Name 31:0 INGR0_ETH1_ADDR_MATCH_1 First 32 bits of the address match value 4.27.9 Description Access Default R/W 0x00000000 Ethernet Address Match Part 2 Short Name: INGR0_ETH1_ADDR_MATCH_2 Addresses: 0x13 INGR0_ETH1_FLOW_CFG_0 0x23 INGR0_ETH1_FLOW_CFG_1 0x33 INGR0_ETH1_FLOW_CFG_2 0x43 INGR0_ETH1_FLOW_CFG_3 0x53 INGR0_ETH1_FLOW_CFG_4 0x63 INGR0_ETH1_FLOW_CFG_5 0x73 INGR0_ETH1_FLOW_CFG_6 0x83 INGR0_ETH1_FLOW_CFG_7 Table 213 • Ethernet Address Match Part 2 Register Bit Name 22:20 INGR0_ETH1_ADDR_MATCH_MODE Selects how the addresses are matched. Multiple R/W bits can be set at once bit 0: Full 48-bit address match bit 1: Match any unicast address bit 2: Match any multicast address Description Access Default 0x1 17:16 INGR0_ETH1_ADDR_MATCH_SELE CT Selects which address to match 0: Match the Destination Address 1: Match the Source Address 2: Match either the Source of Destination Address 3: Reserved R/W 0x0 15:0 INGR0_ETH1_ADDR_MATCH_2 Last 16 bits of the Ethernet address match field R/W 0x0000 4.27.10 Ethernet VLAN Tag Range Match Short Name: INGR0_ETH1_VLAN_TAG_RANGE_I_TAG Addresses: 0x14 INGR0_ETH1_FLOW_CFG_0 0x24 INGR0_ETH1_FLOW_CFG_1 0x34 INGR0_ETH1_FLOW_CFG_2 0x44 INGR0_ETH1_FLOW_CFG_3 0x54 INGR0_ETH1_FLOW_CFG_4 0x64 INGR0_ETH1_FLOW_CFG_5 0x74 INGR0_ETH1_FLOW_CFG_6 VMDS-10509 VSC8572-02 Datasheet Revision 4.2 175 0x84 INGR0_ETH1_FLOW_CFG_7 Table 214 • Ethernet VLAN Tag Range Match Register Bit Name Description Access 27:16 INGR0_ETH1_VLAN_TAG If PBB mode is not enabled, then this register R/W _RANGE_UPPER contains the upper range of the VLAN tag range match. If PBB mode is enabled, then this register contains the upper 12 bits of the I-tag 0xFFF 11:0 INGR0_ETH1_VLAN_TAG If PBB mode is not enabled, then this register _RANGE_LOWER contains the lower range of the VLAN tag range match. If PBB mode is enabled, then this register contains the lower 12 bits of the I-tag 0x000 R/W Default 4.27.11 VLAN Tag 1 Match/Mask Short Name: INGR0_ETH1_VLAN_TAG1 Addresses: 0x15 INGR0_ETH1_FLOW_CFG_0 0x25 INGR0_ETH1_FLOW_CFG_1 0x35 INGR0_ETH1_FLOW_CFG_2 0x45 INGR0_ETH1_FLOW_CFG_3 0x55 INGR0_ETH1_FLOW_CFG_4 0x65 INGR0_ETH1_FLOW_CFG_5 0x75 INGR0_ETH1_FLOW_CFG_6 0x85 INGR0_ETH1_FLOW_CFG_7 Table 215 • VLAN Tag 1 Match/Mask Register Bit Name Description Access Default 27:16 INGR0_ETH1_VLAN_TAG1_MASK Mask value for VLAN tag 1 R/W 0xFFF 11:0 INGR0_ETH1_VLAN_TAG1_MATCH Match value for the first VLAN tag R/W 0x000 4.27.12 Match/Mask For VLAN Tag 2 or I-Tag Match Short Name: INGR0_ETH1_VLAN_TAG2_I_TAG Addresses: 0x16 INGR0_ETH1_FLOW_CFG_0 0x26 INGR0_ETH1_FLOW_CFG_1 0x36 INGR0_ETH1_FLOW_CFG_2 0x46 INGR0_ETH1_FLOW_CFG_3 0x56 INGR0_ETH1_FLOW_CFG_4 0x66 INGR0_ETH1_FLOW_CFG_5 0x76 INGR0_ETH1_FLOW_CFG_6 VMDS-10509 VSC8572-02 Datasheet Revision 4.2 176 0x86 INGR0_ETH1_FLOW_CFG_7 Table 216 • Match/Mask For VLAN Tag 2 or I-Tag Match Register Bit Name Description Access Default 27:16 INGR0_ETH1_VLAN_TAG2_MASK When PBB is not enabled, the mask field for VLAN tag 2 When PBB is enabled, the upper 12 bits of the I-tag mask R/W 0xFFF 11:0 INGR0_ETH1_VLAN_TAG2_MATCH When PBB is not enabled, the match field for R/W VLAN Tag 2 When PBB is enabled, the lower 12 bits of the I-tag mask field 0x000 4.27.13 Ethernet Next Protocol Short Name: INGR0_ETH2_NXT_PROTOCOL Address: 0x90 Table 217 • Ethernet Next Protocol Register Bit Name Description Access 20:16 INGR0_ETH2_FRAME_SIG_OFFSE Frame signature offset. Points to the start of the R/W T byte field in the Ethernet frame that will be used for the frame signature 0x00 2:0 INGR0_ETH2_NXT_COMPARATOR Points to the next comparator block after this Ethernet block. If this comparator block is not used, this field must be set to 0. 0: Comparator block not used 1: Ethernet comparator 2 2: IP/UDP/ACH comparator 1 3: IP/UDP/ACH comparator 2 4: MPLS comparator 5: PTP/OAM comparator 6,7: Reserved 0x0 R/W Default 4.27.14 VLAN TPID Configuration Short Name: INGR0_ETH2_VLAN_TPID_CFG Address: 0x91 Table 218 • VLAN TPID Configuration Register Bit Name Description 31:16 INGR0_ETH2_VLAN_TPID_CFG Configurable S-tag TPID Access Default R/W 0x88A8 4.27.15 Ethertype Match Short Name: INGR0_ETH2_ETYPE_MATCH VMDS-10509 VSC8572-02 Datasheet Revision 4.2 177 Address: 0x92 Table 219 • Ethertype Match Register Bit Name Description Access 15:0 INGR0_ETH2_ETYPE_MATCH If the Ethertype/length field is an Ethertype, then R/W this register is compared against the value. If the field is a length, the length value is not checked. Default 0x0000 4.27.16 Instance offsets: 0xA0 INGR0_ETH2_FLOW_CFG_0 0xB0 INGR0_ETH2_FLOW_CFG_1 0xC0 INGR0_ETH2_FLOW_CFG_2 0xD0 INGR0_ETH2_FLOW_CFG_3 0xE0 INGR0_ETH2_FLOW_CFG_4 0xF0 INGR0_ETH2_FLOW_CFG_5 0x100 INGR0_ETH2_FLOW_CFG_6 0x110 INGR0_ETH2_FLOW_CFG_7 4.27.17 Ethernet Flow Enable Short Name: INGR0_ETH2_FLOW_ENABLE Addresses: 0xA0 INGR0_ETH2_FLOW_CFG_0 0xB0 INGR0_ETH2_FLOW_CFG_1 0xC0 INGR0_ETH2_FLOW_CFG_2 0xD0 INGR0_ETH2_FLOW_CFG_3 0xE0 INGR0_ETH2_FLOW_CFG_4 0xF0 INGR0_ETH2_FLOW_CFG_5 0x100 INGR0_ETH2_FLOW_CFG_6 0x110 INGR0_ETH2_FLOW_CFG_7 Table 220 • Ethernet Flow Enable Register Bit Name Description 9:8 INGR0_ETH2_CHANNEL_MASK Access Default R/W 0x3 Flow enable. If this comparator block is not used, R/W all flow enable bits must be set to 0. 0: Flow is disabled 1: Flow is enabled 0x0 bit 0: Flow valid for channel 0 bit 1: Flow valid for channel 1 0 INGR0_ETH2_FLOW_ENABLE 4.27.18 Ethernet Protocol Match Mode Short Name: INGR0_ETH2_MATCH_MODE Addresses: 0xA1 INGR0_ETH2_FLOW_CFG_0 0xB1 INGR0_ETH2_FLOW_CFG_1 VMDS-10509 VSC8572-02 Datasheet Revision 4.2 178 0xC1 INGR0_ETH2_FLOW_CFG_2 0xD1 INGR0_ETH2_FLOW_CFG_3 0xE1 INGR0_ETH2_FLOW_CFG_4 0xF1 INGR0_ETH2_FLOW_CFG_5 0x101 INGR0_ETH2_FLOW_CFG_6 0x111 INGR0_ETH2_FLOW_CFG_7 Table 221 • Ethernet Protocol Match Mode Register Bit Name Description 13:12 INGR0_ETH2_VLAN_TAG_MODE Access Default R/W 0x0 0: VLAN range checking disabled 1: VLAN range checking on tag 1 2: VLAN range checking on tag 2 (not supported with PBB) 3: reserved 9 INGR0_ETH2_VLAN_TAG2_TYPE This register is only used if ETH1_VLAN_VERIFY_ENA = 1 0: C tag (TPID of 0x8100) 1: S tag (match to CONF_VLAN_TPID) R/W 0x1 8 INGR0_ETH2_VLAN_TAG1_TYPE This register is only used if ETH1_VLAN_VERIFY_ENA = 1 0: C tag (TPID of 0x8100) 1: S or B tag (match to CONF_VLAN_TPID) R/W 0x0 7:6 INGR0_ETH2_VLAN_TAGS This register is only used if ETH2_VLAN_VERIFY_ENA = 1 0: No VLAN tags 1: 1 VLAN tag 2: 2 VLAN tags 3: Reserved R/W 0x0 4 INGR0_ETH2_VLAN_VERIFY_ENA R/W 0x0 When checking for presence of SNAP/LLC R/W based upon ETH1_MATCH_MODE, this field indicates if SNAP & 3-byte LLC is expected to be present 0: Only Ethernet type II supported, no SNAP/LLC 1: Ethernet type II & Ethernet type I with SNAP/LLC, determine if SNAP/LLC is present or not. Type I always assumes that SNAP/LLC is present 0x0 0: Parse for VLAN tags, do not check values. 1: Verify configured VLAN tag configuration. 0 INGR0_ETH2_ETHERTYPE_MOD E 4.27.19 Ethernet Address Match Part 1 Short Name: INGR0_ETH2_ADDR_MATCH_1 Addresses: 0xA2 INGR0_ETH2_FLOW_CFG_0 0xB2 INGR0_ETH2_FLOW_CFG_1 0xC2 INGR0_ETH2_FLOW_CFG_2 0xD2 INGR0_ETH2_FLOW_CFG_3 VMDS-10509 VSC8572-02 Datasheet Revision 4.2 179 0xE2 INGR0_ETH2_FLOW_CFG_4 0xF2 INGR0_ETH2_FLOW_CFG_5 0x102 INGR0_ETH2_FLOW_CFG_6 0x112 INGR0_ETH2_FLOW_CFG_7 Table 222 • Ethernet Address Match Part 1 Register Bit Name 31:0 INGR0_ETH2_ADDR_MATCH_1 First 32 bits of the address match value Description Access Default R/W 0x00000000 4.27.20 Ethernet Address Match Part 2 Short Name: INGR0_ETH2_ADDR_MATCH_2 Addresses: 0xA3 INGR0_ETH2_FLOW_CFG_0 0xB3 INGR0_ETH2_FLOW_CFG_1 0xC3 INGR0_ETH2_FLOW_CFG_2 0xD3 INGR0_ETH2_FLOW_CFG_3 0xE3 INGR0_ETH2_FLOW_CFG_4 0xF3 INGR0_ETH2_FLOW_CFG_5 0x103 INGR0_ETH2_FLOW_CFG_6 0x113 INGR0_ETH2_FLOW_CFG_7 Table 223 • Ethernet Address Match Part 2 Register Bit Name Description 22:20 INGR0_ETH2_ADDR_MATCH_MODE Selects how the addresses are matched. Multiple R/W bits can be set at once bit 0: Full 48-bit address match bit 1: Match any unicast address bit 2: Match any multicast address 0x1 17:16 INGR0_ETH2_ADDR_MATCH_SELE Selects which address to match CT 0: Match the Destination Address 1: Match the Source Address 2: Match either the Source of Destination Address 3: Reserved R/W 0x0 15:0 INGR0_ETH2_ADDR_MATCH_2 R/W 0x0000 Last 16 bits of the Ethernet address match field Access Default 4.27.21 Ethernet VLAN Tag Range Match Short Name: INGR0_ETH2_VLAN_TAG_RANGE_I_TAG Addresses: 0xA4 INGR0_ETH2_FLOW_CFG_0 0xB4 INGR0_ETH2_FLOW_CFG_1 0xC4 INGR0_ETH2_FLOW_CFG_2 0xD4 INGR0_ETH2_FLOW_CFG_3 0xE4 INGR0_ETH2_FLOW_CFG_4 VMDS-10509 VSC8572-02 Datasheet Revision 4.2 180 0xF4 INGR0_ETH2_FLOW_CFG_5 0x104 INGR0_ETH2_FLOW_CFG_6 0x114 INGR0_ETH2_FLOW_CFG_7 Table 224 • Ethernet VLAN Tag Range Match Register Bit Name 27:16 11:0 Description Access Default INGR0_ETH2_VLAN_TAG This register contains the upper range of the _RANGE_UPPER VLAN tag range match. R/W 0xFFF INGR0_ETH2_VLAN_TAG This register contains the lower range of the _RANGE_LOWER VLAN tag range match. R/W 0x000 4.27.22 VLAN Tag 1 Match/Mask Short Name: INGR0_ETH2_VLAN_TAG1 Addresses: 0xA5 INGR0_ETH2_FLOW_CFG_0 0xB5 INGR0_ETH2_FLOW_CFG_1 0xC5 INGR0_ETH2_FLOW_CFG_2 0xD5 INGR0_ETH2_FLOW_CFG_3 0xE5 INGR0_ETH2_FLOW_CFG_4 0xF5 INGR0_ETH2_FLOW_CFG_5 0x105 INGR0_ETH2_FLOW_CFG_6 0x115 INGR0_ETH2_FLOW_CFG_7 Table 225 • VLAN Tag 1 Match/Mask Register Bit Name Description Access Default 27:16 INGR0_ETH2_VLAN_TAG1_MASK Mask value for VLAN tag 1 R/W 0xFFF 11:0 INGR0_ETH2_VLAN_TAG1_MATCH Match value for the first VLAN tag R/W 0x000 4.27.23 Match/Mask for VLAN Tag 2 or I-Tag Match Short Name: INGR0_ETH2_VLAN_TAG2_I_TAG Addresses: 0xA6 INGR0_ETH2_FLOW_CFG_0 0xB6 INGR0_ETH2_FLOW_CFG_1 0xC6 INGR0_ETH2_FLOW_CFG_2 0xD6 INGR0_ETH2_FLOW_CFG_3 0xE6 INGR0_ETH2_FLOW_CFG_4 0xF6 INGR0_ETH2_FLOW_CFG_5 0x106 INGR0_ETH2_FLOW_CFG_6 0x116 INGR0_ETH2_FLOW_CFG_7 Table 226 • Match/Mask for VLAN Tag 2 or I-Tag Match Register Bit Name Description Access Default 27:16 INGR0_ETH2_VLAN_TAG2_MASK Mask field for VLAN tag 2 R/W 0xFFF VMDS-10509 VSC8572-02 Datasheet Revision 4.2 181 Table 226 • Match/Mask for VLAN Tag 2 or I-Tag Match Register (continued) Bit Name 11:0 INGR0_ETH2_VLAN_TAG2_MATCH Match field for VLAN Tag 2 4.28 Description Access Default R/W 0x000 Ingress0 MPLS Next Protocol Registers This section provides information about the MPLS next protocol registers. 4.28.1 MPLS Next Protocol Comparator Short Name: INGR0_MPLS_NXT_COMPARATOR Address: 0x120 Table 227 • MPLS Next Protocol Comparator Register Bit Name Description 16 INGR0_MPLS_CTL_WORD Indicates the presence of a control word after the R/W last label. The first 4 bits of the control word are always 0. 0: There is no control word after the last label 1: There is a control word after the last label Access 0x0 2:0 INGR0_MPLS_NXT_COMPARAT OR Points to the next comparator stage. If this comparator block is not used, this field must be set to 0. 0: Comparator block not used. 1: Ethernet comparator 2 2: IP/UDP/ACH comparator 1 3: IP/UDP/ACH comparator 2 4: Reserved 5: PTP/OAM comparator 6,7: Reserved 0x0 R/W Default 4.28.2 Instance offsets: 0x130 INGR0_MPLS_FLOW_CFG_0 0x140 INGR0_MPLS_FLOW_CFG_1 0x150 INGR0_MPLS_FLOW_CFG_2 0x160 INGR0_MPLS_FLOW_CFG_3 0x170 INGR0_MPLS_FLOW_CFG_4 0x180 INGR0_MPLS_FLOW_CFG_5 0x190 INGR0_MPLS_FLOW_CFG_6 0x1A0 INGR0_MPLS_FLOW_CFG_7 4.28.3 MPLS Flow Control Short Name: INGR0_MPLS_FLOW_CONTROL Addresses: 0x130 INGR0_MPLS_FLOW_CFG_0 0x140 INGR0_MPLS_FLOW_CFG_1 0x150 INGR0_MPLS_FLOW_CFG_2 0x160 INGR0_MPLS_FLOW_CFG_3 0x170 INGR0_MPLS_FLOW_CFG_4 VMDS-10509 VSC8572-02 Datasheet Revision 4.2 182 0x180 INGR0_MPLS_FLOW_CFG_5 0x190 INGR0_MPLS_FLOW_CFG_6 0x1A0 INGR0_MPLS_FLOW_CFG_7 Table 228 • MPLS Flow Control Register Bit Name Description 25:24 INGR0_MPLS_CHANNEL_MAS K Access Default R/W 0x3 bit 0: Flow valid for channel 0 bit 1: Flow valid for channel 1 19:16 INGR0_MPLS_STACK_DEPTH Defines the allowable stack depths for searches. R/W The direction that the stack is referenced is determined by the setting of MPLS_REF_PNT. For each bit set, The following table maps bits to stack depths: bit 0: stack allowed to be 1 label deep bit 1: stack allowed to be 2 labels deep bit 2: stack allowed to be 3 labels deep bit 3: stack allowed to be 4 labels deep 0x0 4 INGR0_MPLS_REF_PNT Defines the search direction for label matching R/W 0: All searching is performed starting from the top of the stack 1: All searching is performed from the end of the stack 0x0 0 INGR0_MPLS_FLOW_ENA Flow enable. If this comparator block is not used, R/W all flow enable bits must be set to 0. 0: Flow is disabled 1: Flow is enabled 0x0 4.28.4 MPLS Label 0 Match Range Lower Value Short Name: INGR0_MPLS_LABEL_RANGE_LOWER_0 Addresses: 0x132 INGR0_MPLS_FLOW_CFG_0 0x142 INGR0_MPLS_FLOW_CFG_1 0x152 INGR0_MPLS_FLOW_CFG_2 0x162 INGR0_MPLS_FLOW_CFG_3 0x172 INGR0_MPLS_FLOW_CFG_4 0x182 INGR0_MPLS_FLOW_CFG_5 0x192 INGR0_MPLS_FLOW_CFG_6 0x1A2 INGR0_MPLS_FLOW_CFG_7 Table 229 • MPLS Label 0 Match Range Lower Value Register Bit Name Description Access Default 19:0 INGR0_MPLS_LABEL_RANGE_LOWER_0 Lower value for label 0 match range R/W 4.28.5 0x00000 MPLS Label 0 Match Range Upper Value Short Name: INGR0_MPLS_LABEL_RANGE_UPPER_0 Addresses: 0x133 INGR0_MPLS_FLOW_CFG_0 VMDS-10509 VSC8572-02 Datasheet Revision 4.2 183 0x143 INGR0_MPLS_FLOW_CFG_1 0x153 INGR0_MPLS_FLOW_CFG_2 0x163 INGR0_MPLS_FLOW_CFG_3 0x173 INGR0_MPLS_FLOW_CFG_4 0x183 INGR0_MPLS_FLOW_CFG_5 0x193 INGR0_MPLS_FLOW_CFG_6 0x1A3 INGR0_MPLS_FLOW_CFG_7 Table 230 • MPLS Label 0 Match Range Upper Value Register Bit Name 19:0 INGR0_MPLS_LABEL_RANGE_UPPER_ Upper value for label 0 match range 0 4.28.6 Description Access Default R/W 0xFFFFF MPLS Label 1 Match Range Lower Value Short Name: INGR0_MPLS_LABEL_RANGE_LOWER_1 Addresses: 0x134 INGR0_MPLS_FLOW_CFG_0 0x144 INGR0_MPLS_FLOW_CFG_1 0x154 INGR0_MPLS_FLOW_CFG_2 0x164 INGR0_MPLS_FLOW_CFG_3 0x174 INGR0_MPLS_FLOW_CFG_4 0x184 INGR0_MPLS_FLOW_CFG_5 0x194 INGR0_MPLS_FLOW_CFG_6 0x1A4 INGR0_MPLS_FLOW_CFG_7 Table 231 • MPLS Label 1 Match Range Lower Value Register Bit Name 19:0 INGR0_MPLS_LABEL_RANGE_LOWER Lower value for label 1 match range _1 4.28.7 Description Access Default R/W 0x00000 MPLS Label 1 Match Range Lower Value Short Name: INGR0_MPLS_LABEL_RANGE_UPPER_1 Addresses: 0x135 INGR0_MPLS_FLOW_CFG_0 0x145 INGR0_MPLS_FLOW_CFG_1 0x155 INGR0_MPLS_FLOW_CFG_2 0x165 INGR0_MPLS_FLOW_CFG_3 0x175 INGR0_MPLS_FLOW_CFG_4 0x185 INGR0_MPLS_FLOW_CFG_5 0x195 INGR0_MPLS_FLOW_CFG_6 VMDS-10509 VSC8572-02 Datasheet Revision 4.2 184 0x1A5 INGR0_MPLS_FLOW_CFG_7 Table 232 • MPLS Label 1 Match Range Lower Value Register Bit Name 19:0 INGR0_MPLS_LABEL_RANGE_UPPER_ Upper value for label 1 match range 1 4.28.8 Description Access Default R/W 0xFFFFF MPLS Label 2 Match Range Lower Value Short Name: INGR0_MPLS_LABEL_RANGE_LOWER_2 Addresses: 0x136 INGR0_MPLS_FLOW_CFG_0 0x146 INGR0_MPLS_FLOW_CFG_1 0x156 INGR0_MPLS_FLOW_CFG_2 0x166 INGR0_MPLS_FLOW_CFG_3 0x176 INGR0_MPLS_FLOW_CFG_4 0x186 INGR0_MPLS_FLOW_CFG_5 0x196 INGR0_MPLS_FLOW_CFG_6 0x1A6 INGR0_MPLS_FLOW_CFG_7 Table 233 • MPLS Label 2 Match Range Lower Value Register Bit Name 19:0 INGR0_MPLS_LABEL_RANGE_LOWER Lower value for label 2 match range _2 4.28.9 Description Access Default R/W 0x00000 MPLS Label 2 Match Range Lower Value Short Name: INGR0_MPLS_LABEL_RANGE_UPPER_2 Addresses: 0x137 INGR0_MPLS_FLOW_CFG_0 0x147 INGR0_MPLS_FLOW_CFG_1 0x157 INGR0_MPLS_FLOW_CFG_2 0x167 INGR0_MPLS_FLOW_CFG_3 0x177 INGR0_MPLS_FLOW_CFG_4 0x187 INGR0_MPLS_FLOW_CFG_5 0x197 INGR0_MPLS_FLOW_CFG_6 0x1A7 INGR0_MPLS_FLOW_CFG_7 Table 234 • MPLS Label 2 Match Range Lower Value Register Bit Name Description 19:0 INGR0_MPLS_LABEL_RANGE_UPPER Upper value for label 2 match range _2 Access Default R/W 0xFFFFF 4.28.10 MPLS Label 3 Match Range Lower Value Short Name: INGR0_MPLS_LABEL_RANGE_LOWER_3 Addresses: 0x138 INGR0_MPLS_FLOW_CFG_0 VMDS-10509 VSC8572-02 Datasheet Revision 4.2 185 0x148 INGR0_MPLS_FLOW_CFG_1 0x158 INGR0_MPLS_FLOW_CFG_2 0x168 INGR0_MPLS_FLOW_CFG_3 0x178 INGR0_MPLS_FLOW_CFG_4 0x188 INGR0_MPLS_FLOW_CFG_5 0x198 INGR0_MPLS_FLOW_CFG_6 0x1A8 INGR0_MPLS_FLOW_CFG_7 Table 235 • MPLS Label 3 Match Range Lower Value Register Bit Name Description 19:0 INGR0_MPLS_LABEL_RANGE_LOWER_ Lower value for label 3 match range 3 Access Default R/W 0x00000 4.28.11 MPLS Label 3 Match Range Lower Value Short Name: INGR0_MPLS_LABEL_RANGE_UPPER_3 Addresses: 0x139 INGR0_MPLS_FLOW_CFG_0 0x149 INGR0_MPLS_FLOW_CFG_1 0x159 INGR0_MPLS_FLOW_CFG_2 0x169 INGR0_MPLS_FLOW_CFG_3 0x179 INGR0_MPLS_FLOW_CFG_4 0x189 INGR0_MPLS_FLOW_CFG_5 0x199 INGR0_MPLS_FLOW_CFG_6 0x1A9 INGR0_MPLS_FLOW_CFG_7 Table 236 • MPLS Label 3 Match Range Lower Value Register Bit Name 19:0 INGR0_MPLS_LABEL_RANGE_UPPER Upper value for label 3 match range _3 Description Access Default R/W 0xFFFFF 4.28.12 IP Next Comparator Control Short Name: INGR0_IP1_NXT_COMPARATOR Address: 0x1B0 Table 237 • IP Next Comparator Control Register Bit Name Description Access Default 15:8 INGR0_IP1_NXT_PROTOCOL Number of bytes in this header, points to the beginning of the next protocol R/W 0x00 VMDS-10509 VSC8572-02 Datasheet Revision 4.2 186 Table 237 • IP Next Comparator Control Register (continued) Bit Name Description 2:0 INGR0_IP1_NXT_COMPARATO Points to the next comparator stage. If this R comparator block is not used, this field must be set to 0. 0: Comparator block not used 1: Reserved 2: Reserved 3: IP/UDP/ACH comparator 2 4: Reserved 5: PTP/OAM comparator 6,7: Reserved Access Default R/W 0x0 4.28.13 IP Comparator Mode Short Name: INGR0_IP1_MODE Address: 0x1B1 Table 238 • IP Comparator Mode Register Bit Name 12:8 INGR0_IP1_FLOW_OFFSE Points to the source address field in the IP frame. R/W T Use 12 for IPv4 and 8 for IPv6 Description Access 0x0C 1:0 INGR0_IP1_MODE 0x0 R/W Default 0: IPv4 1: IPv6 2: Other protocol, 32-bit address match 3: Other protocol, 128-bit address match 4.28.14 IP Match Register Set 1 Short Name: INGR0_IP1_PROT_MATCH_1 Address: 0x1B2 Table 239 • IP Match Register Set 1 Register Bit Name 20:16 Description Access Default INGR0_IP1_PROT_OFFSET_ Points to the start of this match field relative to 1 the first byte of this protocol R/W 0x00 15:8 INGR0_IP1_PROT_MASK_1 R/W 0x00 7:0 INGR0_IP1_PROT_MATCH_1 8-bit match field R/W 0x00 Access Default R/W 0x00000000 Mask field for IP_PROT_MATCH_1 4.28.15 Upper Portion of Match 2 Short Name: INGR0_IP1_PROT_MATCH_2_UPPER Address: 0x1B3 Table 240 • Upper Portion of Match 2 Register Bit Name Description 31:0 INGR0_IP1_PROT_MATCH_2_UPPE 64-bit match register for advancing to R the next protocol, upper portion VMDS-10509 VSC8572-02 Datasheet Revision 4.2 187 4.28.16 Lower Portion of Match 2 Short Name: INGR0_IP1_PROT_MATCH_2_LOWER Address: 0x1B4 Table 241 • Lower Portion of Match 2 Register Bit Name Description 31:0 INGR0_IP1_PROT_MATCH_2_LOWE 64-bit match register for advancing to R the next protocol, lower portion Access Default R/W 0x00000000 4.28.17 Upper Portion of Match Mask 2 Short Name: INGR0_IP1_PROT_MASK_2_UPPER Address: 0x1B5 Table 242 • Upper Portion of Match Mask 2 Register Bit Name Description 31:0 INGR0_IP1_PROT_MASK_2_UPPE R Access Default R/W 0x00000000 4.28.18 Lower Portion of Match Mask 2 Short Name: INGR0_IP1_PROT_MASK_2_LOWER Address: 0x1B6 Table 243 • Lower Portion of Match Mask 2 Register Bit Name Description 31:0 INGR0_IP1_PROT_MASK_2_LOWE R Access Default R/W 0x00000000 4.28.19 Match Offset 2 Short Name: INGR0_IP1_PROT_OFFSET_2 Address: 0x1B7 Table 244 • Match Offset 2 Register Bit Name Description Access 6:0 INGR0_IP1_PROT_OFFSET_ Points to the start of match field 2 relative to the R/W 2 first byte of this protocol Default 0x00 4.28.20 IP/UDP Checksum Control Short Name: INGR0_IP1_UDP_CHKSUM_CFG VMDS-10509 VSC8572-02 Datasheet Revision 4.2 188 Address: 0x1B8 Table 245 • IP/UDP Checksum Control Register Bit Name Description Access Default 15:8 INGR0_IP1_UDP_CHKSUM_OFFSET Pointer to the IP/UDP checksum field FOR R/W IPv4 frames or to the pad bytes of a IPv6/UDP frame. For IPv4, it points to the bytes that will be cleared. For IPv6, it points to the bytes that will be updated to fix the CRC 0x00 5:4 INGR0_IP1_UDP_CHKSUM_WIDTH Specifies the length of the checksum field in bytes R/W 0x2 1 INGR0_IP1_UDP_CHKSUM_UPDATE_E This bit and NA IP_UDP_CHKSUM_CLEAR_ENA CANNOT be set together. 1: Update the pad bytes at the end of the frame 0: No pad byte field update R/W 0x0 0 R/W INGR0_IP1_UDP_CHKSUM_CLEAR_EN This bit and A IP_UDP_CHKSUM_UPDATE_ENA CANNOT be set together. 1: Clear the UDP checksum field in an IPv4 frame 0: Do not clear the checksum 0x0 4.28.21 Instance offsets: 0x1C0 INGR0_IP1_FLOW_CFG_0 0x1D0 INGR0_IP1_FLOW_CFG_1 0x1E0 INGR0_IP1_FLOW_CFG_2 0x1F0 INGR0_IP1_FLOW_CFG_3 0x200 INGR0_IP1_FLOW_CFG_4 0x210 INGR0_IP1_FLOW_CFG_5 0x220 INGR0_IP1_FLOW_CFG_6 0x230 INGR0_IP1_FLOW_CFG_7 4.28.22 IP Flow Enable Short Name: INGR0_IP1_FLOW_ENA Addresses: 0x1C0 INGR0_IP1_FLOW_CFG_0 0x1D0 INGR0_IP1_FLOW_CFG_1 0x1E0 INGR0_IP1_FLOW_CFG_2 0x1F0 INGR0_IP1_FLOW_CFG_3 0x200 INGR0_IP1_FLOW_CFG_4 0x210 INGR0_IP1_FLOW_CFG_5 0x220 INGR0_IP1_FLOW_CFG_6 VMDS-10509 VSC8572-02 Datasheet Revision 4.2 189 0x230 INGR0_IP1_FLOW_CFG_7 Table 246 • IP Flow Enable Register Bit Name 9:8 5:4 Description Access Default INGR0_IP1_FLOW_MATCH_MOD E 0: Match on source address 1: Match on destination address 2: Match on either source or destination address 3: reserved R/W 0x0 INGR0_IP1_CHANNEL_MASK R/W 0x3 R/W 0x0 Access Default R/W 0x00000000 bit 0: Flow valid for channel 0 bit 1: Flow valid for channel 1 0 INGR0_IP1_FLOW_ENA Flow enable. If this comparator block is not used, all flow enable bits must be set to 0. 1: This flow is enabled 0: This flow is not enabled 4.28.23 Upper Portion of the IP Flow Match Short Name: INGR0_IP1_FLOW_MATCH_UPPER Addresses: 0x1C1 INGR0_IP1_FLOW_CFG_0 0x1D1 INGR0_IP1_FLOW_CFG_1 0x1E1 INGR0_IP1_FLOW_CFG_2 0x1F1 INGR0_IP1_FLOW_CFG_3 0x201 INGR0_IP1_FLOW_CFG_4 0x211 INGR0_IP1_FLOW_CFG_5 0x221 INGR0_IP1_FLOW_CFG_6 0x231 INGR0_IP1_FLOW_CFG_7 Table 247 • Upper Portion of the IP Flow Match Register Bit Name Description 31:0 INGR0_IP1_FLOW_MATCH_UPPE Match field for either the entire 32-bit R selected address for IPv4 or the upper 32 bits of the selected address for IPv6 4.28.24 Upper Mid Portion of the IP Flow Match Short Name: INGR0_IP1_FLOW_MATCH_UPPER_MID Addresses: 0x1C2 INGR0_IP1_FLOW_CFG_0 0x1D2 INGR0_IP1_FLOW_CFG_1 0x1E2 INGR0_IP1_FLOW_CFG_2 0x1F2 INGR0_IP1_FLOW_CFG_3 0x202 INGR0_IP1_FLOW_CFG_4 0x212 INGR0_IP1_FLOW_CFG_5 0x222 INGR0_IP1_FLOW_CFG_6 VMDS-10509 VSC8572-02 Datasheet Revision 4.2 190 0x232 INGR0_IP1_FLOW_CFG_7 Table 248 • Upper Mid Portion of the IP Flow Match Register Bit Name Description 31:0 INGR0_IP1_FLOW_MATCH_UPPER_MI Match bits for the upper middle 32 D bits of the IPv6 address Access Default R/W 0x00000000 Access Default R/W 0x00000000 4.28.25 Lower Mid Portion of the IP Flow Match Short Name: INGR0_IP1_FLOW_MATCH_LOWER_MID Addresses: 0x1C3 INGR0_IP1_FLOW_CFG_0 0x1D3 INGR0_IP1_FLOW_CFG_1 0x1E3 INGR0_IP1_FLOW_CFG_2 0x1F3 INGR0_IP1_FLOW_CFG_3 0x203 INGR0_IP1_FLOW_CFG_4 0x213 INGR0_IP1_FLOW_CFG_5 0x223 INGR0_IP1_FLOW_CFG_6 0x233 INGR0_IP1_FLOW_CFG_7 Table 249 • Lower Mid Portion of the IP Flow Match Register Bit Name Description 31:0 INGR0_IP1_FLOW_MATCH_LOWER_MI Match bits for the lower middle 32 D bits of the IPv6 address 4.28.26 Lower Portion of the IP Flow Match Short Name: INGR0_IP1_FLOW_MATCH_LOWER Addresses: 0x1C4 INGR0_IP1_FLOW_CFG_0 0x1D4 INGR0_IP1_FLOW_CFG_1 0x1E4 INGR0_IP1_FLOW_CFG_2 0x1F4 INGR0_IP1_FLOW_CFG_3 0x204 INGR0_IP1_FLOW_CFG_4 0x214 INGR0_IP1_FLOW_CFG_5 0x224 INGR0_IP1_FLOW_CFG_6 0x234 INGR0_IP1_FLOW_CFG_7 Table 250 • Lower Portion of the IP Flow Match Register Bit Name Description 31:0 INGR0_IP1_FLOW_MATCH_LOWE Match bits for the lower 32 bits of the R IPv6 address Access Default R/W 0x00000000 4.28.27 IP Flow Match Mask Short Name: INGR0_IP1_FLOW_MASK_UPPER Addresses: 0x1C5 INGR0_IP1_FLOW_CFG_0 VMDS-10509 VSC8572-02 Datasheet Revision 4.2 191 0x1D5 INGR0_IP1_FLOW_CFG_1 0x1E5 INGR0_IP1_FLOW_CFG_2 0x1F5 INGR0_IP1_FLOW_CFG_3 0x205 INGR0_IP1_FLOW_CFG_4 0x215 INGR0_IP1_FLOW_CFG_5 0x225 INGR0_IP1_FLOW_CFG_6 0x235 INGR0_IP1_FLOW_CFG_7 Table 251 • IP Flow Match Mask Register Bit Name Description 31:0 INGR0_IP1_FLOW_MASK_UPPE This is the address mask for the IP address R Access Default R/W 0x00000000 Access Default R/W 0x00000000 4.28.28 Upper Mid Portion of the IP Flow Mask Short Name: INGR0_IP1_FLOW_MASK_UPPER_MID Addresses: 0x1C6 INGR0_IP1_FLOW_CFG_0 0x1D6 INGR0_IP1_FLOW_CFG_1 0x1E6 INGR0_IP1_FLOW_CFG_2 0x1F6 INGR0_IP1_FLOW_CFG_3 0x206 INGR0_IP1_FLOW_CFG_4 0x216 INGR0_IP1_FLOW_CFG_5 0x226 INGR0_IP1_FLOW_CFG_6 0x236 INGR0_IP1_FLOW_CFG_7 Table 252 • Upper Mid Portion of the IP Flow Mask Register Bit Name Description 31:0 INGR0_IP1_FLOW_MASK_UPPER_MI These bits must be all 0 for IPv4 and D any 32-bit address match mode 4.28.29 Lower Mid Portion of the IP Flow Mask Short Name: INGR0_IP1_FLOW_MASK_LOWER_MID Addresses: 0x1C7 INGR0_IP1_FLOW_CFG_0 0x1D7 INGR0_IP1_FLOW_CFG_1 0x1E7 INGR0_IP1_FLOW_CFG_2 0x1F7 INGR0_IP1_FLOW_CFG_3 0x207 INGR0_IP1_FLOW_CFG_4 0x217 INGR0_IP1_FLOW_CFG_5 0x227 INGR0_IP1_FLOW_CFG_6 VMDS-10509 VSC8572-02 Datasheet Revision 4.2 192 0x237 INGR0_IP1_FLOW_CFG_7 Table 253 • Lower Mid Portion of the IP Flow Mask Register Bit Name Description Access 31:0 INGR0_IP1_FLOW_MASK_LOWER_MI D These bits must be all 0 for IPv4 and R/W any 32-bit address match mode Default 0x00000000 4.28.30 Lower Portion of the IP Flow Mask Short Name: INGR0_IP1_FLOW_MASK_LOWER Addresses: 0x1C8 INGR0_IP1_FLOW_CFG_0 0x1D8 INGR0_IP1_FLOW_CFG_1 0x1E8 INGR0_IP1_FLOW_CFG_2 0x1F8 INGR0_IP1_FLOW_CFG_3 0x208 INGR0_IP1_FLOW_CFG_4 0x218 INGR0_IP1_FLOW_CFG_5 0x228 INGR0_IP1_FLOW_CFG_6 0x238 INGR0_IP1_FLOW_CFG_7 Table 254 • Lower Portion of the IP Flow Mask Register Bit Name Description Access 31:0 INGR0_IP1_FLOW_MASK_LOWE These bits must be all 0 for IPv4 and any R/W R 32-bit address match mode Default 0x00000000 4.28.31 IP Next Comparator Control Short Name: INGR0_IP2_NXT_COMPARATOR Address: 0x240 Table 255 • IP Next Comparator Control Register Bit Name Description Access Default 15:8 INGR0_IP2_NXT_PROTOCOL Number of bytes in this header, points to the beginning of the next protocol R/W 0x00 2:0 INGR0_IP2_NXT_COMPARATO Points to the next comparator stage. If this R comparator block is not used, this field must be set to 0. 0: Comparator block not used 1: Reserved 2: Reserved 3: Reserved 4: Reserved 5: PTP/OAM comparator 6,7: Reserved R/W 0x0 4.28.32 IP Comparator Mode Short Name: INGR0_IP2_MODE VMDS-10509 VSC8572-02 Datasheet Revision 4.2 193 Address: 0x241 Table 256 • IP Comparator Mode Register Bit Name Description Access 12:8 INGR0_IP2_FLOW_OFFSE T Points to the source address field in the IP frame. R/W Use 12 for IPv4 and 8 for IPv6 1:0 INGR0_IP2_MODE R/W Default 0x0C 0x0 0: IPv4 1: IPv6 2: Other protocol, 32-bit address match 3: Other protocol, 128-bit address match 4.28.33 IP Match Set 1 Short Name: INGR0_IP2_PROT_MATCH_1 Address: 0x242 Table 257 • IP Match Set 1 Register Bit Name 20:16 Description Access Default INGR0_IP2_PROT_OFFSET_ Points to the start of this match field relative to 1 the first byte of this protocol R/W 0x00 15:8 INGR0_IP2_PROT_MASK_1 R/W 0x00 7:0 INGR0_IP2_PROT_MATCH_1 8-bit match field R/W 0x00 Access Default R/W 0x00000000 Access Default R/W 0x00000000 Mask field for IP_PROT_MATCH_1 4.28.34 Upper Portion of Match 2 Short Name: INGR0_IP2_PROT_MATCH_2_UPPER Address: 0x243 Table 258 • Upper Portion of Match 2 Register Bit Name Description 31:0 INGR0_IP2_PROT_MATCH_2_UPPE 64-bit match register for advancing to R the next protocol, upper portion 4.28.35 Lower Portion of Match 2 Short Name: INGR0_IP2_PROT_MATCH_2_LOWER Address: 0x244 Table 259 • Lower Portion of Match 2 Register Bit Name Description 31:0 INGR0_IP2_PROT_MATCH_2_LOWE 64-bit match register for advancing to R the next protocol, lower portion 4.28.36 Upper Portion of Match Mask 2 Short Name: INGR0_IP2_PROT_MASK_2_UPPER VMDS-10509 VSC8572-02 Datasheet Revision 4.2 194 Address: 0x245 Table 260 • Upper Portion of Match Mask 2 Register Bit Name Description 31:0 INGR0_IP2_PROT_MASK_2_UPPE R Access Default R/W 0x00000000 Access Default R/W 0x00000000 4.28.37 Lower Portion of Match Mask 2 Short Name: INGR0_IP2_PROT_MASK_2_LOWER Address: 0x246 Table 261 • Lower Portion of Match Mask 2 Register Bit Name Description 31:0 INGR0_IP2_PROT_MASK_2_LOWE R 4.28.38 Match Offset 2 Short Name: INGR0_IP2_PROT_OFFSET_2 Address: 0x247 Table 262 • Match Offset 2 Register Bit Name Description Access 6:0 INGR0_IP2_PROT_OFFSET_ Points to the start of match field 2 relative to the R/W 2 first byte of this protocol Default 0x00 4.28.39 IP/UDP Checksum Control Short Name: INGR0_IP2_UDP_CHKSUM_CFG Address: 0x248 Table 263 • IP/UDP Checksum Control Register Bit Name Description 15:8 INGR0_IP2_UDP_CHKSUM_OFFSE Pointer to the IP/UDP checksum field FOR IPv4 R/W T frames or to the pad bytes of a IPv6/UDP frame. For IPv4, it points to the bytes that will be cleared. For IPv6, it points to the bytes that will be updated to fix the CRC 0x00 5:4 INGR0_IP2_UDP_CHKSUM_WIDTH Specifies the length of the checksum field in bytes R/W 0x2 1 INGR0_IP2_UDP_CHKSUM_UPDAT This bit and IP_UDP_CHKSUM_CLEAR_ENA R/W E_ENA CANNOT be set together. 1: Update the pad bytes at the end of the frame 0: No pad byte field update 0x0 0 INGR0_IP2_UDP_CHKSUM_CLEAR This bit and IP_UDP_CHKSUM_UPDATE_ENA R/W _ENA CANNOT be set together. 1: Clear the UDP checksum field in an IPv4 frame 0: Do not clear the checksum 0x0 VMDS-10509 VSC8572-02 Datasheet Revision 4.2 Access Default 195 4.28.40 Instance offsets: 0x250 INGR0_IP2_FLOW_CFG_0 0x260 INGR0_IP2_FLOW_CFG_1 0x270 INGR0_IP2_FLOW_CFG_2 0x280 INGR0_IP2_FLOW_CFG_3 0x290 INGR0_IP2_FLOW_CFG_4 0x2A0 INGR0_IP2_FLOW_CFG_5 0x2B0 INGR0_IP2_FLOW_CFG_6 0x2C0 INGR0_IP2_FLOW_CFG_7 4.28.41 IP Flow Enable Short Name: INGR0_IP2_FLOW_ENA Addresses: 0x250 INGR0_IP2_FLOW_CFG_0 0x260 INGR0_IP2_FLOW_CFG_1 0x270 INGR0_IP2_FLOW_CFG_2 0x280 INGR0_IP2_FLOW_CFG_3 0x290 INGR0_IP2_FLOW_CFG_4 0x2A0 INGR0_IP2_FLOW_CFG_5 0x2B0 INGR0_IP2_FLOW_CFG_6 0x2C0 INGR0_IP2_FLOW_CFG_7 Table 264 • IP Flow Enable Register Bit Name 9:8 5:4 Description Access Default INGR0_IP2_FLOW_MATCH_MOD E 0: Match on source address 1: Match on destination address 2: Match on either source or destination address 3: reserved R/W 0x0 INGR0_IP2_CHANNEL_MASK R/W 0x3 R/W 0x0 bit 0: Flow valid for channel 0 bit 1: Flow valid for channel 1 0 INGR0_IP2_FLOW_ENA Flow enable. If this comparator block is not used, all flow enable bits must be set to 0. 1: This flow is enabled 0: This flow is not enabled 4.28.42 Upper Portion of the IP Flow Match Short Name: INGR0_IP2_FLOW_MATCH_UPPER Addresses: 0x251 INGR0_IP2_FLOW_CFG_0 0x261 INGR0_IP2_FLOW_CFG_1 0x271 INGR0_IP2_FLOW_CFG_2 0x281 INGR0_IP2_FLOW_CFG_3 VMDS-10509 VSC8572-02 Datasheet Revision 4.2 196 0x291 INGR0_IP2_FLOW_CFG_4 0x2A1 INGR0_IP2_FLOW_CFG_5 0x2B1 INGR0_IP2_FLOW_CFG_6 0x2C1 INGR0_IP2_FLOW_CFG_7 Table 265 • Upper Portion of the IP Flow Match Register Bit Name 31:0 INGR0_IP2_FLOW_MATCH_UPPE Match field for either the entire 32-bit R selected address for IPv4 or the upper 32 bits of the selected address for IPv6 Description Access Default R/W 0x00000000 4.28.43 Upper Mid Portion of the IP Flow Match Short Name: INGR0_IP2_FLOW_MATCH_UPPER_MID Addresses: 0x252 INGR0_IP2_FLOW_CFG_0 0x262 INGR0_IP2_FLOW_CFG_1 0x272 INGR0_IP2_FLOW_CFG_2 0x282 INGR0_IP2_FLOW_CFG_3 0x292 INGR0_IP2_FLOW_CFG_4 0x2A2 INGR0_IP2_FLOW_CFG_5 0x2B2 INGR0_IP2_FLOW_CFG_6 0x2C2 INGR0_IP2_FLOW_CFG_7 Table 266 • Upper Mid Portion of the IP Flow Match Register Bit Name Description 31:0 INGR0_IP2_FLOW_MATCH_UPPER_M Match bits for the upper middle 32 ID bits of the IPv6 address Access Default R/W 0x00000000 4.28.44 Lower Mid Portion of the IP Flow Match Short Name: INGR0_IP2_FLOW_MATCH_LOWER_MID Addresses: 0x253 INGR0_IP2_FLOW_CFG_0 0x263 INGR0_IP2_FLOW_CFG_1 0x273 INGR0_IP2_FLOW_CFG_2 0x283 INGR0_IP2_FLOW_CFG_3 0x293 INGR0_IP2_FLOW_CFG_4 0x2A3 INGR0_IP2_FLOW_CFG_5 0x2B3 INGR0_IP2_FLOW_CFG_6 0x2C3 INGR0_IP2_FLOW_CFG_7 Table 267 • Lower Mid Portion of the IP Flow Match Register Bit Name Description 31:0 INGR0_IP2_FLOW_MATCH_LOWER_MI Match bits for the lower middle 32 D bits of the IPv6 address VMDS-10509 VSC8572-02 Datasheet Revision 4.2 Access Default R/W 0x00000000 197 4.28.45 Lower Portion of the IP Flow Match Short Name: INGR0_IP2_FLOW_MATCH_LOWER Addresses: 0x254 INGR0_IP2_FLOW_CFG_0 0x264 INGR0_IP2_FLOW_CFG_1 0x274 INGR0_IP2_FLOW_CFG_2 0x284 INGR0_IP2_FLOW_CFG_3 0x294 INGR0_IP2_FLOW_CFG_4 0x2A4 INGR0_IP2_FLOW_CFG_5 0x2B4 INGR0_IP2_FLOW_CFG_6 0x2C4 INGR0_IP2_FLOW_CFG_7 Table 268 • Lower Portion of the IP Flow Match Register Bit Name Description 31:0 INGR0_IP2_FLOW_MATCH_LOWE Match bits for the lower 32 bits of the R IPv6 address Access Default R/W 0x00000000 4.28.46 IP Flow Match Mask Short Name: INGR0_IP2_FLOW_MASK_UPPER Addresses: 0x255 INGR0_IP2_FLOW_CFG_0 0x265 INGR0_IP2_FLOW_CFG_1 0x275 INGR0_IP2_FLOW_CFG_2 0x285 INGR0_IP2_FLOW_CFG_3 0x295 INGR0_IP2_FLOW_CFG_4 0x2A5 INGR0_IP2_FLOW_CFG_5 0x2B5 INGR0_IP2_FLOW_CFG_6 0x2C5 INGR0_IP2_FLOW_CFG_7 Table 269 • IP Flow Match Mask Register Bit Name Description 31:0 INGR0_IP2_FLOW_MASK_UPPER This is the address mask for the IP address. Access Default R/W 0x00000000 4.28.47 Upper Mid Portion of the IP Flow Mask Short Name: INGR0_IP2_FLOW_MASK_UPPER_MID Addresses: 0x256 INGR0_IP2_FLOW_CFG_0 0x266 INGR0_IP2_FLOW_CFG_1 0x276 INGR0_IP2_FLOW_CFG_2 0x286 INGR0_IP2_FLOW_CFG_3 0x296 INGR0_IP2_FLOW_CFG_4 0x2A6 INGR0_IP2_FLOW_CFG_5 0x2B6 INGR0_IP2_FLOW_CFG_6 VMDS-10509 VSC8572-02 Datasheet Revision 4.2 198 0x2C6 INGR0_IP2_FLOW_CFG_7 Table 270 • Upper Mid Portion of the IP Flow Mask Register Bit Name Description 31:0 INGR0_IP2_FLOW_MASK_UPPER_MI These bits must be all 0 for IPv4 and D any 32-bit address match mode Access Default R/W 0x00000000 Access Default R/W 0x00000000 4.28.48 Lower Mid Portion of the IP Flow Mask Short Name: INGR0_IP2_FLOW_MASK_LOWER_MID Addresses: 0x257 INGR0_IP2_FLOW_CFG_0 0x267 INGR0_IP2_FLOW_CFG_1 0x277 INGR0_IP2_FLOW_CFG_2 0x287 INGR0_IP2_FLOW_CFG_3 0x297 INGR0_IP2_FLOW_CFG_4 0x2A7 INGR0_IP2_FLOW_CFG_5 0x2B7 INGR0_IP2_FLOW_CFG_6 0x2C7 INGR0_IP2_FLOW_CFG_7 Table 271 • Lower Mid Portion of the IP Flow Mask Register Bit Name Description 31:0 INGR0_IP2_FLOW_MASK_LOWER_MI These bits must be all 0 for IPv4 and D any 32-bit address match mode 4.28.49 Lower Portion of the IP Flow Mask Short Name: INGR0_IP2_FLOW_MASK_LOWER Addresses: 0x258 INGR0_IP2_FLOW_CFG_0 0x268 INGR0_IP2_FLOW_CFG_1 0x278 INGR0_IP2_FLOW_CFG_2 0x288 INGR0_IP2_FLOW_CFG_3 0x298 INGR0_IP2_FLOW_CFG_4 0x2A8 INGR0_IP2_FLOW_CFG_5 0x2B8 INGR0_IP2_FLOW_CFG_6 0x2C8 INGR0_IP2_FLOW_CFG_7 Table 272 • Lower Portion of the IP Flow Mask Register Bit Name Description 31:0 INGR0_IP2_FLOW_MASK_LOWE These bits must be all 0 for IPv4 and any R 32-bit address match mode Access Default R/W 0x00000000 4.28.50 Instance offsets: 0x2D0 INGR0_PTP_FLOW_0 0x2E0 INGR0_PTP_FLOW_1 VMDS-10509 VSC8572-02 Datasheet Revision 4.2 199 0x2F0 INGR0_PTP_FLOW_2 0x300 INGR0_PTP_FLOW_3 0x310 INGR0_PTP_FLOW_4 0x320 INGR0_PTP_FLOW_5 4.28.51 PTP/OAM Flow Enable Short Name: INGR0_PTP_FLOW_ENA Addresses: 0x2D0 INGR0_PTP_FLOW_0 0x2E0 INGR0_PTP_FLOW_1 0x2F0 INGR0_PTP_FLOW_2 0x300 INGR0_PTP_FLOW_3 0x310 INGR0_PTP_FLOW_4 0x320 INGR0_PTP_FLOW_5 Table 273 • PTP/OAM Flow Enable Register Bit Name 5:4 0 Description Access Default INGR0_PTP_CHANNEL_MAS K bit 0: Flow valid for channel 0 bit 1: Flow valid for channel 1 R/W 0x3 INGR0_PTP_FLOW_ENA R/W 0x0 Access Default R/W 0x00000000 4.28.52 Upper Half of PTP/OAM Flow Match Field Short Name: INGR0_PTP_FLOW_MATCH_UPPER Addresses: 0x2D1 INGR0_PTP_FLOW_0 0x2E1 INGR0_PTP_FLOW_1 0x2F1 INGR0_PTP_FLOW_2 0x301 INGR0_PTP_FLOW_3 0x311 INGR0_PTP_FLOW_4 0x321 INGR0_PTP_FLOW_5 Table 274 • Upper Half of PTP/OAM Flow Match Field Register Bit Name Description 31:0 INGR0_PTP_FLOW_MATCH_UPP ER 4.28.53 Lower Half of PTP/OAM Flow Match Field Short Name: INGR0_PTP_FLOW_MATCH_LOWER Addresses: 0x2D2 INGR0_PTP_FLOW_0 0x2E2 INGR0_PTP_FLOW_1 0x2F2 INGR0_PTP_FLOW_2 0x302 INGR0_PTP_FLOW_3 0x312 INGR0_PTP_FLOW_4 VMDS-10509 VSC8572-02 Datasheet Revision 4.2 200 0x322 INGR0_PTP_FLOW_5 Table 275 • Lower Half of PTP/OAM Flow Match Field Register Bit Name Description 31:0 INGR0_PTP_FLOW_MATCH_LOWE R Access Default R/W 0x00000000 4.28.54 Upper Half of PTP/OAM Flow Match Mask Short Name: INGR0_PTP_FLOW_MASK_UPPER Addresses: 0x2D3 INGR0_PTP_FLOW_0 0x2E3 INGR0_PTP_FLOW_1 0x2F3 INGR0_PTP_FLOW_2 0x303 INGR0_PTP_FLOW_3 0x313 INGR0_PTP_FLOW_4 0x323 INGR0_PTP_FLOW_5 Table 276 • Upper Half of PTP/OAM Flow Match Mask Register Bit Name Description 31:0 INGR0_PTP_FLOW_MASK_UPPE R Access Default R/W 0x00000000 4.28.55 Lower Half of PTP/OAM Flow Match Mask Short Name: INGR0_PTP_FLOW_MASK_LOWER Addresses: 0x2D4 INGR0_PTP_FLOW_0 0x2E4 INGR0_PTP_FLOW_1 0x2F4 INGR0_PTP_FLOW_2 0x304 INGR0_PTP_FLOW_3 0x314 INGR0_PTP_FLOW_4 0x324 INGR0_PTP_FLOW_5 Table 277 • Lower Half of PTP/OAM Flow Match Mask Register Bit Name Description 31:0 INGR0_PTP_FLOW_MASK_LOWE R Access Default R/W 0x00000000 4.28.56 PTP/OAM Range Match Short Name: INGR0_PTP_DOMAIN_RANGE Addresses: 0x2D5 INGR0_PTP_FLOW_0 0x2E5 INGR0_PTP_FLOW_1 0x2F5 INGR0_PTP_FLOW_2 0x305 INGR0_PTP_FLOW_3 0x315 INGR0_PTP_FLOW_4 VMDS-10509 VSC8572-02 Datasheet Revision 4.2 201 0x325 INGR0_PTP_FLOW_5 Table 278 • PTP/OAM Range Match Register Bit Name 28:24 Description Access Default INGR0_PTP_DOMAIN_RANGE_OFFSE T R/W 0x00 23:16 INGR0_PTP_DOMAIN_RANGE_UPPE R R/W 0xFF 15:8 INGR0_PTP_DOMAIN_RANGE_LOWE R R/W 0x00 0 INGR0_PTP_DOMAIN_RANGE_ENA R/W 0x0 4.28.57 PTP Action Control Short Name: INGR0_PTP_ACTION Addresses: 0x2D6 INGR0_PTP_FLOW_0 0x2E6 INGR0_PTP_FLOW_1 0x2F6 INGR0_PTP_FLOW_2 0x306 INGR0_PTP_FLOW_3 0x316 INGR0_PTP_FLOW_4 0x326 INGR0_PTP_FLOW_5 Table 279 • PTP Action Control Register Bit Name 28 Description Access Default INGR0_PTP_MOD_FRAM E_STAT_UPDATE 1: Tell the Rewriter to update the value of the Modified Frame Status bit 0: Do not update the bit R/W 0x0 26:24 INGR0_PTP_MOD_FRAM Indicates the position relative to the start of the E_BYTE_OFFSET PTP frame in bytes where the Modified_Frame_Status bit resides R/W 0x0 21 INGR0_PTP_SUB_DELAY R/W _ASYM_ENA 1: Signal the Timestamp block to subtract the asymmetry delay 0: Do not signal the Timestamp block to subtract the asymmetry delay 0x0 20 INGR0_PTP_ADD_DELAY R/W _ASYM_ENA 1: Signal the Timestamp block to add the asymmetry delay 0: Do not signal the Timestamp block to add the asymmetry delay 0x0 15:10 INGR0_PTP_TIME_STRG Points to the reserved 32-bit field where the Rx R/W _FIELD_OFFSET timestamp is saved. The location is relative to the first byte of the PTP/OAM header. 0x00 9:5 INGR0_PTP_CORR_FIEL Points to the location of the correction field for D_OFFSET updating the timestamp. Location is relative to the first byte of the PTP/OAM header. Note: If this flow is being used to match OAM frames, set this register to 4 0x00 VMDS-10509 VSC8572-02 Datasheet Revision 4.2 R/W 202 Table 279 • PTP Action Control Register (continued) Bit Name 4 3:0 Description Access Default INGR0_PTP_SAVE_LOCA L_TIME 1: Save the local time to the Timestamp FIFO 0: Do not save the time to the Timestamp FIFO R/W 0x0 INGR0_PTP_COMMAND R/W 0x0 0: NoP 1: SUB 2: SUB_P2P 3: ADD 4: SUB_ADD 5: WRITE_1588 6: WRITE_P2P (deprecated) 7: WRITE_NS 8: WRITE_NS_P2P 4.28.58 PTP Action Control 2 Short Name: INGR0_PTP_ACTION_2 Addresses: 0x2D7 INGR0_PTP_FLOW_0 0x2E7 INGR0_PTP_FLOW_1 0x2F7 INGR0_PTP_FLOW_2 0x307 INGR0_PTP_FLOW_3 0x317 INGR0_PTP_FLOW_4 0x327 INGR0_PTP_FLOW_5 Table 280 • PTP Action Control 2 Register Bit Name Description Access Default 23:16 INGR0_PTP_NEW_CF_LOC Location of the new correction field relative to the R/W PTP header start. Only even values are allowed. 15:8 INGR0_PTP_REWRITE_OFFSE Byte offset relative to the start of the PTP frame T where the ingress timestamp value can be stored. R/W 0x00 3:0 INGR0_PTP_REWRITE_BYTES Number of bytes in the PTP or OAM frame that must be modified by the Rewriter for the timestamp R/W 0x0 0x00 4.28.59 Zero Field Control Short Name: INGR0_PTP_ZERO_FIELD_CTL Addresses: 0x2D8 INGR0_PTP_FLOW_0 0x2E8 INGR0_PTP_FLOW_1 0x2F8 INGR0_PTP_FLOW_2 0x308 INGR0_PTP_FLOW_3 0x318 INGR0_PTP_FLOW_4 VMDS-10509 VSC8572-02 Datasheet Revision 4.2 203 0x328 INGR0_PTP_FLOW_5 Table 281 • Zero Field Control Register Bit Name 13:8 INGR0_PTP_ZERO_FIELD_OFFSET Points to a location in the PTP/OAM frame R/W relative to the start of the PTP header that will be zeroed if this function is enabled 0x00 3:0 INGR0_PTP_ZERO_FIELD_BYTE_C NT 0x0 4.29 Description Access Default The number of bytes to be zeroed. If this field R/W is 0, then this function is not enabled. Ingress0 IP Checksum Field Control Registers This section provides information about the IP checksum field control registers. 4.29.1 IP Checksum Block Select Short Name: INGR0_PTP_IP_CKSUM_SEL Address: 0x330 Table 282 • IP Checksum Block Select Register Bit Name 0 INGR0_PTP_IP_CHKSUM_S EL 4.30 Description Access Default R/W 0x0 0: Use the IP checksum controls from IP comparator 1 1: Use the IP checksum controls from IP comparator 2 Egress0 Analyzer Engine Configuration Registers This section lists overviews for the egress0 analyzer engine configuration registers.Egress1 analyzer engine registers are identical to the ones defined for egress0. Note: The analyzer engine configuration registers are not initialized to the default values during chip reset. Software must configure these registers to their default value. Note: For more information about accessing the 1588 IP registers, see Accessing 1588 IP Registers, page 72. Table 283 • EGR0_ETH1_NXT_PROTOCOL Address Name Details 0x00 EGR0_ETH1_NXT_PROTOCOL Ethernet Next Protocol, page 209 0x01 EGR0_ETH1_VLAN_TPID_CFG VLAN TPID Configuration, page 209 0x02 EGR0_ETH1_TAG_MODE Ethernet Tag Mode, page 209 0x03 EGR0_ETH1_ETYPE_MATCH Ethertype Match, page 210 Table 284 • EGR0_ETH1_FLOW_CFG (8 instances) Address Name Details 0x10 EGR0_ETH1_FLOW_ENABLE Ethernet Flow Enable, page 210 0x11 EGR0_ETH1_MATCH_MODE Ethernet Protocol Match Mode, page 211 VMDS-10509 VSC8572-02 Datasheet Revision 4.2 204 Table 284 • EGR0_ETH1_FLOW_CFG (8 instances) (continued) Address Name Details 0x12 EGR0_ETH1_ADDR_MATCH_1 Ethernet Address Match Part 1, page 212 0x13 EGR0_ETH1_ADDR_MATCH_2 Ethernet Address Match Part 2, page 212 0x14 EGR0_ETH1_VLAN_TAG_RANGE_I_TA Ethernet VLAN Tag Range Match, page 213 G 0x15 EGR0_ETH1_VLAN_TAG1 VLAN Tag 1 Match/Mask, page 213 0x16 EGR0_ETH1_VLAN_TAG2_I_TAG Match/Mask For VLAN Tag 2 or I-Tag Match, page 214 Table 285 • EGR0_ETH2_NXT_PROTOCOL Address Name Details 0x90 EGR0_ETH2_NXT_PROTOCOL Ethernet Next Protocol, page 214 0x91 EGR0_ETH2_VLAN_TPID_CFG VLAN TPID Configuration, page 215 0x92 EGR0_ETH2_ETYPE_MATCH Ethertype Match, page 215 Table 286 • EGR0_ETH2_FLOW_CFG (8 instances) Address Name Details 0xA0 EGR0_ETH2_FLOW_ENABLE Ethernet Flow Enable, page 215 0xA1 EGR0_ETH2_MATCH_MODE Ethernet Protocol Match Mode, page 216 0xA2 EGR0_ETH2_ADDR_MATCH_1 Ethernet Address Match Part 1, page 217 0xA3 EGR0_ETH2_ADDR_MATCH_2 Ethernet Address Match Part 2, page 217 0xA4 EGR0_ETH2_VLAN_TAG_RANGE_ Ethernet VLAN Tag Range Match, page 218 I_TAG 0xA5 EGR0_ETH2_VLAN_TAG1 VLAN Tag 1 Match/Mask, page 218 0xA6 EGR0_ETH2_VLAN_TAG2_I_TAG Match/Mask For VLAN Tag 2 or I-Tag Match, page 219 Table 287 • EGR0_MPLS_NXT_COMPARATOR Address Name 0x120 EGR0_MPLS_NXT_COMPARATO MPLS Next Protocol Comparator, page 219 R Details Table 288 • EGR0_MPLS_FLOW_CFG (8 instances) Address Name Details 0x130 EGR0_MPLS_FLOW_CONTROL MPLS Flow Control, page 220 VMDS-10509 VSC8572-02 Datasheet Revision 4.2 205 Table 288 • EGR0_MPLS_FLOW_CFG (8 instances) (continued) Address Name Details 0x132 EGR0_MPLS_LABEL_RANGE_LOWER MPLS Label 0 Match Range Lower Value, _0 page 221 0x133 EGR0_MPLS_LABEL_RANGE_UPPER MPLS Label 0 Match Range Upper Value, _0 page 221 0x134 EGR0_MPLS_LABEL_RANGE_LOWER MPLS Label 1 Match Range Lower Value, _1 page 222 0x135 EGR0_MPLS_LABEL_RANGE_UPPER MPLS Label 1 Match Range Lower Value, _1 page 222 0x136 EGR0_MPLS_LABEL_RANGE_LOWER MPLS Label 2 Match Range Lower Value, _2 page 222 0x137 EGR0_MPLS_LABEL_RANGE_UPPER MPLS Label 2 Match Range Lower Value, _2 page 223 0x138 EGR0_MPLS_LABEL_RANGE_LOWER MPLS Label 3 Match Range Lower Value, _3 page 223 0x139 EGR0_MPLS_LABEL_RANGE_UPPER MPLS Label 3 Match Range Lower Value, _3 page 224 Table 289 • EGR0_IP1_NXT_PROTOCOL Address Name Details 0x1B0 EGR0_IP1_NXT_COMPARATOR IP Next Comparator Control, page 224 0x1B1 EGR0_IP1_MODE IP Comparator Mode, page 224 0x1B2 EGR0_IP1_PROT_MATCH_1 IP Match Set 1, page 225 0x1B3 EGR0_IP1_PROT_MATCH_2_UPPE Upper Portion of Match 2, page 225 R 0x1B4 EGR0_IP1_PROT_MATCH_2_LOW ER 0x1B5 EGR0_IP1_PROT_MASK_2_UPPER Upper Portion of Match Mask 2, page 225 0x1B6 EGR0_IP1_PROT_MASK_2_LOWE Lower Portion of Match Mask 2, page 226 R 0x1B7 EGR0_IP1_PROT_OFFSET_2 Match Offset 2, page 226 0x1B8 EGR0_IP1_UDP_CHKSUM_CFG IP/UDP Checksum Control, page 226 0x1B9 EGR0_IP1_FRAME_SIG_CFG IP Frame Signature Control, page 227 Lower Portion of Match 2, page 225 Table 290 • EGR0_IP1_FLOW_CFG (8 instances) Address Name Details 0x1C0 EGR0_IP1_FLOW_ENA IP Flow Enable, page 227 0x1C1 EGR0_IP1_FLOW_MATCH_UPPE Upper Portion of the IP Flow Match, page 228 R 0x1C2 EGR0_IP1_FLOW_MATCH_UPPE Upper Mid Portion of the IP Flow Match, R_MID page 228 VMDS-10509 VSC8572-02 Datasheet Revision 4.2 206 Table 290 • EGR0_IP1_FLOW_CFG (8 instances) (continued) Address Name Details 0x1C3 EGR0_IP1_FLOW_MATCH_LOWE Lower Mid Portion of the IP Flow Match, R_MID page 229 0x1C4 EGR0_IP1_FLOW_MATCH_LOWE Lower Portion of the IP Flow Match, page 229 R 0x1C5 EGR0_IP1_FLOW_MASK_UPPER IP Flow Match Mask, page 229 0x1C6 EGR0_IP1_FLOW_MASK_UPPER Upper Mid Portion Of IP Flow Mask, page 230 _MID 0x1C7 EGR0_IP1_FLOW_MASK_LOWER Lower Mid Portion of IP Flow Mask, page 230 _MID 0x1C8 EGR0_IP1_FLOW_MASK_LOWER Lower Portion of IP Flow Mask, page 231 Table 291 • EGR0_IP2_NXT_PROTOCOL Address Name Details 0x240 EGR0_IP2_NXT_COMPARATOR IP Next Comparator Control, page 231 0x241 EGR0_IP2_MODE IP Comparator Mode, page 231 IP Match Register Set 1, page 232 0x242 EGR0_IP2_PROT_MATCH_1 0x243 EGR0_IP2_PROT_MATCH_2_UPPE Upper Portion of Match 2, page 232 R 0x244 EGR0_IP2_PROT_MATCH_2_LOW Lower Portion of Match 2, page 232 ER 0x245 EGR0_IP2_PROT_MASK_2_UPPE R 0x246 EGR0_IP2_PROT_MASK_2_LOWE Lower Portion of Match Mask 2, page 233 R 0x247 EGR0_IP2_PROT_OFFSET_2 Match Offset Register 2, page 233 0x248 EGR0_IP2_UDP_CHKSUM_CFG IP/UDP Checksum Control, page 233 0x249 EGR0_IP2_FRAME_SIG_CFG IP Frame Signature Control, page 234 Upper Portion of Match Mask 2, page 232 Table 292 • EGR0_IP2_FLOW_CFG (8 instances) Addres s Name Details 0x250 EGR0_IP2_FLOW_ENA IP Flow Enable, page 234 0x251 EGR0_IP2_FLOW_MATCH_UPPE Upper Portion of the IP Flow Match, page 235 R 0x252 EGR0_IP2_FLOW_MATCH_UPPE Upper Mid Portion of the IP Flow Match, page 235 R_MID 0x253 EGR0_IP2_FLOW_MATCH_LOWE Lower Mid Portion of the IP Flow Match, page 236 R_MID 0x254 EGR0_IP2_FLOW_MATCH_LOWE Lower Portion of the IP Flow Match, page 236 R VMDS-10509 VSC8572-02 Datasheet Revision 4.2 207 Table 292 • EGR0_IP2_FLOW_CFG (8 instances) (continued) Addres s Name Details 0x255 EGR0_IP2_FLOW_MASK_UPPER Upper Portion of the IP Flow Match Mask, page 236 0x256 EGR0_IP2_FLOW_MASK_UPPER Upper Mid Portion of the IP Flow Match Mask, _MID page 237 0x257 EGR0_IP2_FLOW_MASK_LOWER Lower Mid Portion of the IP Flow Match Mask, _MID page 237 0x258 EGR0_IP2_FLOW_MASK_LOWER Lower Portion of the IP Flow Match Mask, page 238 Table 293 • EGR0_PTP_FLOW (6 instances) Address Name Details 0x2D0 EGR0_PTP_FLOW_ENA PTP/OAM Flow Enable, page 238 0x2D1 EGR0_PTP_FLOW_MATCH_UPPE Upper Half of PTP/OAM Flow Match Field, R page 239 0x2D2 EGR0_PTP_FLOW_MATCH_LOW Lower Half of PTP/OAM Flow Match Field, ER page 239 0x2D3 EGR0_PTP_FLOW_MASK_UPPE R 0x2D4 EGR0_PTP_FLOW_MASK_LOWE Lower Half of PTP/OAM Flow Match Mask, R page 240 0x2D5 EGR0_PTP_DOMAIN_RANGE PTP/OAM Range Match, page 240 0x2D6 EGR0_PTP_ACTION PTP Action Control, page 240 0x2D7 EGR0_PTP_ACTION_2 PTP Action Control 2, page 242 0x2D8 EGR0_PTP_ZERO_FIELD_CTL Zero Field Control, page 242 Upper Half of PTP/OAM Flow Match Mask, page 239 Table 294 • EGR0_PTP_IP_CHKSUM_CTL Address Name Details 0x330 EGR0_PTP_IP_CKSUM_SEL IP Checksum Block Select, page 242 Table 295 • EGR0_FRAME_SIG_CFG Address Register Name Details 0x331 EGR0_FSB_CFG Frame Signature Builder Mode Configuration, page 243 0x332 EGR0_FSB_MAP_REG_ Frame Signature Builder Mapping 0, page 243 0 0x333 EGR0_FSB_MAP_REG_ Frame Signature Builder Mapping 1, page 244 1 0x334 EGR0_FSB_MAP_REG_ Frame Signature Builder Mapping 2, page 244 2 VMDS-10509 VSC8572-02 Datasheet Revision 4.2 208 Table 295 • EGR0_FRAME_SIG_CFG (continued) 4.31 Address Register Name Details 0x335 EGR0_FSB_MAP_REG_ Frame Signature Builder Mapping 3, page 244 3 Egress0 Ethernet Next Protocol Configuration Registers This section provides information about the Ethernet next protocol configuration registers. 4.31.1 Ethernet Next Protocol Short Name: EGR0_ETH1_NXT_PROTOCOL Address: 0x00 Table 296 • Ethernet Next Protocol Register Bit Name 20:16 2:0 Access Default EGR0_ETH1_FRAME_SIG_OFFSE Frame signature offset. Points to the start of the T byte field in the Ethernet frame that will be used for the frame signature R/W 0x00 EGR0_ETH1_NXT_COMPARATOR Points to the next comparator block after this Ethernet block 0: Reserved 1: Ethernet comparator 2 2: IP/UDP/ACH comparator 1 3: IP/UDP/ACH comparator 2 4: MPLS comparator 5: PTP/OAM comparator 6,7: Reserved R/W 0x0 4.31.2 Description VLAN TPID Configuration Short Name: EGR0_ETH1_VLAN_TPID_CFG Address: 0x01 Table 297 • VLAN TPID Configuration Register Bit Name 31:16 EGR0_ETH1_VLAN_TPID_CF Configurable VLAN TPID (S or B-tag) G 4.31.3 Description Access Default R/W 0x88A8 Ethernet Tag Mode Short Name: EGR0_ETH1_TAG_MODE VMDS-10509 VSC8572-02 Datasheet Revision 4.2 209 Address: 0x02 Table 298 • Ethernet Tag Mode Register Bit Name Description Access Default 0 EGR0_ETH1_PBB_ENA This bit enables the presence of PBB. The I-tag match bits are programmed in the ETH1_VLAN_TAG_RANGE registers. The mask bits are programmed in the ETH1_VLAN_TAG2 registers. A B-tag if present is configured in the ETH1_VLAN_TAG1 registers. 0: PBB not enabled 1: Always expect PBB, last tag is always an I-tag R/W 0x0 Access Default 4.31.4 Ethertype Match Short Name: EGR0_ETH1_ETYPE_MATCH Address: 0x03 Table 299 • Ethertype Match Register Bit Name Description 15:0 EGR0_ETH1_ETYPE_MATC If the Ethertype/length field is an Ethertype, then R/W H this register is compared against the value. If the field is a length, the length value is not checked. 0x0000 4.31.5 Instance offsets: 0x10 EGR0_ETH1_FLOW_CFG_0 0x20 EGR0_ETH1_FLOW_CFG_1 0x30 EGR0_ETH1_FLOW_CFG_2 0x40 EGR0_ETH1_FLOW_CFG_3 0x50 EGR0_ETH1_FLOW_CFG_4 0x60 EGR0_ETH1_FLOW_CFG_5 0x70 EGR0_ETH1_FLOW_CFG_6 0x80 EGR0_ETH1_FLOW_CFG_7 4.31.6 Ethernet Flow Enable Short Name: EGR0_ETH1_FLOW_ENABLE Addresses: 0x10 EGR0_ETH1_FLOW_CFG_0 0x20 EGR0_ETH1_FLOW_CFG_1 0x30 EGR0_ETH1_FLOW_CFG_2 0x40 EGR0_ETH1_FLOW_CFG_3 0x50 EGR0_ETH1_FLOW_CFG_4 0x60 EGR0_ETH1_FLOW_CFG_5 0x70 EGR0_ETH1_FLOW_CFG_6 VMDS-10509 VSC8572-02 Datasheet Revision 4.2 210 0x80 EGR0_ETH1_FLOW_CFG_7 Table 300 • Ethernet Flow Enable Register Bit Name 9:8 0 4.31.7 Description Access Default EGR0_ETH1_CHANNEL_MAS K 0: Flow valid for channel 0 1: Flow valid for channel 1 R/W 0x3 EGR0_ETH1_FLOW_ENABLE R/W 0x0 Flow enable 0: Flow is disabled 1: Flow is enabled Ethernet Protocol Match Mode Short Name: EGR0_ETH1_MATCH_MODE Addresses: 0x11 EGR0_ETH1_FLOW_CFG_0 0x21 EGR0_ETH1_FLOW_CFG_1 0x31 EGR0_ETH1_FLOW_CFG_2 0x41 EGR0_ETH1_FLOW_CFG_3 0x51 EGR0_ETH1_FLOW_CFG_4 0x61 EGR0_ETH1_FLOW_CFG_5 0x71 EGR0_ETH1_FLOW_CFG_6 0x81 EGR0_ETH1_FLOW_CFG_7 Table 301 • Ethernet Protocol Match Mode Register Bit Name Description 13:12 EGR0_ETH1_VLAN_TAG_MOD E Access Default R/W 0x0 0: VLAN range checking disabled 1: VLAN range checking on tag 1 2: VLAN range checking on tag 2 (not supported with PBB) 3: reserved 9 EGR0_ETH1_VLAN_TAG2_TYP This register is only used if E ETH1_VLAN_VERIFY_ENA = 1 If PBB not enabled: 0: C tag (TPID of 0x8100) 1: S tag (match to CONF_VLAN_TPID) If PBB enabled: 0,1: I tag (use range registers) R/W 0x1 8 EGR0_ETH1_VLAN_TAG1_TYP This register is only used if E ETH1_VLAN_VERIFY_ENA = 1 0: C tag (TPID of 0x8100) 1: S or B tag (match to CONF_VLAN_TPID) R/W 0x0 7:6 EGR0_ETH1_VLAN_TAGS This register is only used if R/W ETH1_VLAN_VERIFY_ENA = 1 0: No VLAN tags (not valid for PBB) 1: 1 VLAN tag (for PBB this would be the I-tag) 2: 2 VLAN tags (for PBB expect a B-tag and an Itag) 3: Reserved 0x0 VMDS-10509 VSC8572-02 Datasheet Revision 4.2 211 Table 301 • Ethernet Protocol Match Mode Register (continued) Bit Name 4 EGR0_ETH1_VLAN_VERIFY_E NA 0 4.31.8 Description Access Default R/W 0x0 EGR0_ETH1_ETHERTYPE_MO When checking for presence of SNAP/LLC R/W DE based upon ETH1_MATCH_MODE, this field indicates if SNAP & 3-byte LLC is expected to be present 0: Only Ethernet type II supported, no SNAP/LLC 1: Ethernet type II & Ethernet type I with SNAP/LLC, determine if SNAP/LLC is present or not. Type I always assumes that SNAP/LLC is present 0x0 0: Parse for VLAN tags, do not check values. For PBB the I-tag is always checked. 1: Verify configured VLAN tag configuration. Ethernet Address Match Part 1 Short Name: EGR0_ETH1_ADDR_MATCH_1 Addresses: 0x12 EGR0_ETH1_FLOW_CFG_0 0x22 EGR0_ETH1_FLOW_CFG_1 0x32 EGR0_ETH1_FLOW_CFG_2 0x42 EGR0_ETH1_FLOW_CFG_3 0x52 EGR0_ETH1_FLOW_CFG_4 0x62 EGR0_ETH1_FLOW_CFG_5 0x72 EGR0_ETH1_FLOW_CFG_6 0x82 EGR0_ETH1_FLOW_CFG_7 Table 302 • Ethernet Address Match Part 1 Register Bit Name 31:0 EGR0_ETH1_ADDR_MATCH First 32 bits of the address match value _1 4.31.9 Description Access Default R/W 0x00000000 Ethernet Address Match Part 2 Short Name: EGR0_ETH1_ADDR_MATCH_2 Addresses: 0x13 EGR0_ETH1_FLOW_CFG_0 0x23 EGR0_ETH1_FLOW_CFG_1 0x33 EGR0_ETH1_FLOW_CFG_2 0x43 EGR0_ETH1_FLOW_CFG_3 0x53 EGR0_ETH1_FLOW_CFG_4 0x63 EGR0_ETH1_FLOW_CFG_5 0x73 EGR0_ETH1_FLOW_CFG_6 VMDS-10509 VSC8572-02 Datasheet Revision 4.2 212 0x83 EGR0_ETH1_FLOW_CFG_7 Table 303 • Ethernet Address Match Part 2 Register Bit Name Description 22:20 EGR0_ETH1_ADDR_MATCH_MOD E Selects how the addresses are matched. Multiple R/W bits can be set at once bit 0: Full 48-bit address match bit 1: Match any unicast address bit 2: Match any multicast address 17:16 EGR0_ETH1_ADDR_MATCH_SELE Selects which address to match CT 0: Match the Destination Address 1: Match the Source Address 2: Match either the Source of Destination Address 3: Reserved R/W 0x0 15:0 EGR0_ETH1_ADDR_MATCH_2 R/W 0x0000 Last 16 bits of the Ethernet address match field Access Default 0x1 4.31.10 Ethernet VLAN Tag Range Match Short Name: EGR0_ETH1_VLAN_TAG_RANGE_I_TAG Addresses: 0x14 EGR0_ETH1_FLOW_CFG_0 0x24 EGR0_ETH1_FLOW_CFG_1 0x34 EGR0_ETH1_FLOW_CFG_2 0x44 EGR0_ETH1_FLOW_CFG_3 0x54 EGR0_ETH1_FLOW_CFG_4 0x64 EGR0_ETH1_FLOW_CFG_5 0x74 EGR0_ETH1_FLOW_CFG_6 0x84 EGR0_ETH1_FLOW_CFG_7 Table 304 • Ethernet VLAN Tag Range Match Register Bit Name Description Access Default 27:16 EGR0_ETH1_VLAN_TAG_RANGE_UPP If PBB mode is not enabled, then this ER register contains the upper range of the VLAN tag range match. If PBB mode is enabled, then this register contains the upper 12 bits of the I-tag R/W 0xFFF 11:0 EGR0_ETH1_VLAN_TAG_RANGE_LOW If PBB mode is not enabled, then this ER register contains the lower range of the VLAN tag range match. If PBB mode is enabled, then this register contains the lower 12 bits of the I-tag R/W 0x000 4.31.11 VLAN Tag 1 Match/Mask Short Name: EGR0_ETH1_VLAN_TAG1 Addresses: 0x15 EGR0_ETH1_FLOW_CFG_0 0x25 EGR0_ETH1_FLOW_CFG_1 0x35 EGR0_ETH1_FLOW_CFG_2 VMDS-10509 VSC8572-02 Datasheet Revision 4.2 213 0x45 EGR0_ETH1_FLOW_CFG_3 0x55 EGR0_ETH1_FLOW_CFG_4 0x65 EGR0_ETH1_FLOW_CFG_5 0x75 EGR0_ETH1_FLOW_CFG_6 0x85 EGR0_ETH1_FLOW_CFG_7 Table 305 • VLAN Tag 1 Match/Mask Register Bit Name Description Access Default 27:16 EGR0_ETH1_VLAN_TAG1_MAS K Mask value for VLAN tag 1 R/W 0xFFF 11:0 EGR0_ETH1_VLAN_TAG1_MAT CH Match value for the first VLAN tag R/W 0x000 Access Default 4.31.12 Match/Mask For VLAN Tag 2 or I-Tag Match Short Name: EGR0_ETH1_VLAN_TAG2_I_TAG Addresses: 0x16 EGR0_ETH1_FLOW_CFG_0 0x26 EGR0_ETH1_FLOW_CFG_1 0x36 EGR0_ETH1_FLOW_CFG_2 0x46 EGR0_ETH1_FLOW_CFG_3 0x56 EGR0_ETH1_FLOW_CFG_4 0x66 EGR0_ETH1_FLOW_CFG_5 0x76 EGR0_ETH1_FLOW_CFG_6 0x86 EGR0_ETH1_FLOW_CFG_7 Table 306 • Match/Mask For VLAN Tag 2 or I-Tag Match Register Bit Name Description 27:16 EGR0_ETH1_VLAN_TAG2_MASK When PBB is not enabled, the mask field for R/W VLAN tag 2 When PBB is enabled, the upper 12 bits of the Itag mask 0xFFF 11:0 EGR0_ETH1_VLAN_TAG2_MATC H 0x000 When PBB is not enabled, the match field for R/W VLAN Tag 2 When PBB is enabled, the lower 12 bits of the Itag mask field 4.31.13 Ethernet Next Protocol Short Name: EGR0_ETH2_NXT_PROTOCOL Address: 0x90 Table 307 • Ethernet Next Protocol Register Bit Name Description 20:16 EGR0_ETH2_FRAME_SIG_OFFS Frame signature offset. Points to the start of the R/W ET byte field in the Ethernet frame that will be used for the frame signature VMDS-10509 VSC8572-02 Datasheet Revision 4.2 Access Default 0x00 214 Table 307 • Ethernet Next Protocol Register (continued) Bit Name Description 2:0 EGR0_ETH2_NXT_COMPARATO Points to the next comparator block after this R Ethernet block. If this comparator block is not used, this field must be set to 0. 0: Comparator block not used 1: Ethernet comparator 2 2: IP/UDP/ACH comparator 1 3: IP/UDP/ACH comparator 2 4: MPLS comparator 5: PTP/OAM comparator 6,7: Reserved Access Default R/W 0x0 4.31.14 VLAN TPID Configuration Short Name: EGR0_ETH2_VLAN_TPID_CFG Address: 0x91 Table 308 • VLAN TPID Configuration Register Bit Name Description Access Default 31:16 EGR0_ETH2_VLAN_TPID_CF G Configurable S-tag TPID R/W 0x88A8 4.31.15 Ethertype Match Short Name: EGR0_ETH2_ETYPE_MATCH Address: 0x92 Table 309 • Ethertype Match Register Bit Name Description Access 15:0 EGR0_ETH2_ETYPE_MATC If the Ethertype/length field is an Ethertype, then R/W H this register is compared against the value. If the field is a length, the length value is not checked. Default 0x0000 4.31.16 Instance offsets: 0xA0 EGR0_ETH2_FLOW_CFG_0 0xB0 EGR0_ETH2_FLOW_CFG_1 0xC0 EGR0_ETH2_FLOW_CFG_2 0xD0 EGR0_ETH2_FLOW_CFG_3 0xE0 EGR0_ETH2_FLOW_CFG_4 0xF0 EGR0_ETH2_FLOW_CFG_5 0x100 EGR0_ETH2_FLOW_CFG_6 0x110 EGR0_ETH2_FLOW_CFG_7 4.31.17 Ethernet Flow Enable Short Name: EGR0_ETH2_FLOW_ENABLE Addresses: 0xA0 EGR0_ETH2_FLOW_CFG_0 0xB0 EGR0_ETH2_FLOW_CFG_1 VMDS-10509 VSC8572-02 Datasheet Revision 4.2 215 0xC0 EGR0_ETH2_FLOW_CFG_2 0xD0 EGR0_ETH2_FLOW_CFG_3 0xE0 EGR0_ETH2_FLOW_CFG_4 0xF0 EGR0_ETH2_FLOW_CFG_5 0x100 EGR0_ETH2_FLOW_CFG_6 0x110 EGR0_ETH2_FLOW_CFG_7 Table 310 • Ethernet Flow Enable Register Bit Name Description Access Default 9:8 EGR0_ETH2_CHANNEL_MAS K bit 0: Flow valid for channel 0 bit 1: Flow valid for channel 1 R/W 0x3 0 EGR0_ETH2_FLOW_ENABLE Flow enable. If this comparator block is not used, R/W all flow enable bits must be set to 0. 0: Flow is disabled 1: Flow is enabled 0x0 4.31.18 Ethernet Protocol Match Mode Short Name: EGR0_ETH2_MATCH_MODE Addresses: 0xA1 EGR0_ETH2_FLOW_CFG_0 0xB1 EGR0_ETH2_FLOW_CFG_1 0xC1 EGR0_ETH2_FLOW_CFG_2 0xD1 EGR0_ETH2_FLOW_CFG_3 0xE1 EGR0_ETH2_FLOW_CFG_4 0xF1 EGR0_ETH2_FLOW_CFG_5 0x101 EGR0_ETH2_FLOW_CFG_6 0x111 EGR0_ETH2_FLOW_CFG_7 Table 311 • Ethernet Protocol Match Mode Register Bit Name 13:12 Description Access Default EGR0_ETH2_VLAN_TAG_MOD E 0: VLAN range checking disabled 1: VLAN range checking on tag 1 2: VLAN range checking on tag 2 (not supported with PBB) 3: reserved R/W 0x0 9 EGR0_ETH2_VLAN_TAG2_TYP This register is only used if E ETH1_VLAN_VERIFY_ENA = 1 0: C tag (TPID of 0x8100) 1: S tag (match to CONF_VLAN_TPID) R/W 0x1 8 EGR0_ETH2_VLAN_TAG1_TYP This register is only used if E ETH1_VLAN_VERIFY_ENA = 1 0: C tag (TPID of 0x8100) 1: S or B tag (match to CONF_VLAN_TPID) R/W 0x0 VMDS-10509 VSC8572-02 Datasheet Revision 4.2 216 Table 311 • Ethernet Protocol Match Mode Register (continued) Bit Name Description Access Default 7:6 EGR0_ETH2_VLAN_TAGS This register is only used if ETH2_VLAN_VERIFY_ENA = 1 0: No VLAN tags 1: 1 VLAN tag 2: 2 VLAN tags 3: Reserved R/W 0x0 4 EGR0_ETH2_VLAN_VERIFY_E NA R/W 0x0 EGR0_ETH2_ETHERTYPE_MO When checking for presence of SNAP/LLC based R/W DE upon ETH1_MATCH_MODE, this field indicates if SNAP & 3-byte LLC is expected to be present 0: Only Ethernet type II supported, no SNAP/LLC 1: Ethernet type II & Ethernet type I with SNAP/LLC, determine if SNAP/LLC is present or not. Type I always assumes that SNAP/LLC is present 0x0 0 0: Parse for VLAN tags, do not check values. 1: Verify configured VLAN tag configuration. 4.31.19 Ethernet Address Match Part 1 Short Name: EGR0_ETH2_ADDR_MATCH_1 Addresses: 0xA2 EGR0_ETH2_FLOW_CFG_0 0xB2 EGR0_ETH2_FLOW_CFG_1 0xC2 EGR0_ETH2_FLOW_CFG_2 0xD2 EGR0_ETH2_FLOW_CFG_3 0xE2 EGR0_ETH2_FLOW_CFG_4 0xF2 EGR0_ETH2_FLOW_CFG_5 0x102 EGR0_ETH2_FLOW_CFG_6 0x112 EGR0_ETH2_FLOW_CFG_7 Table 312 • Ethernet Address Match Part 1 Register Bit Name Description 31:0 EGR0_ETH2_ADDR_MATCH_ First 32 bits of the address match value 1 Access Default R/W 0x00000000 4.31.20 Ethernet Address Match Part 2 Short Name: EGR0_ETH2_ADDR_MATCH_2 Addresses: 0xA3 EGR0_ETH2_FLOW_CFG_0 0xB3 EGR0_ETH2_FLOW_CFG_1 0xC3 EGR0_ETH2_FLOW_CFG_2 0xD3 EGR0_ETH2_FLOW_CFG_3 0xE3 EGR0_ETH2_FLOW_CFG_4 0xF3 EGR0_ETH2_FLOW_CFG_5 0x103 EGR0_ETH2_FLOW_CFG_6 VMDS-10509 VSC8572-02 Datasheet Revision 4.2 217 0x113 EGR0_ETH2_FLOW_CFG_7 Table 313 • Ethernet Address Match Part 2 Register Bit Name Description 22:20 EGR0_ETH2_ADDR_MATCH_MOD E Selects how the addresses are matched. Multiple R/W bits can be set at once bit 0: Full 48-bit address match bit 1: Match any unicast address bit 2: Match any multicast address 17:16 EGR0_ETH2_ADDR_MATCH_SELE Selects which address to match CT 0: Match the Destination Address 1: Match the Source Address 2: Match either the Source of Destination Address 3: Reserved R/W 0x0 15:0 EGR0_ETH2_ADDR_MATCH_2 R/W 0x0000 Last 16 bits of the Ethernet address match field Access Default 0x1 4.31.21 Ethernet VLAN Tag Range Match Short Name: EGR0_ETH2_VLAN_TAG_RANGE_I_TAG Addresses: 0xA4 EGR0_ETH2_FLOW_CFG_0 0xB4 EGR0_ETH2_FLOW_CFG_1 0xC4 EGR0_ETH2_FLOW_CFG_2 0xD4 EGR0_ETH2_FLOW_CFG_3 0xE4 EGR0_ETH2_FLOW_CFG_4 0xF4 EGR0_ETH2_FLOW_CFG_5 0x104 EGR0_ETH2_FLOW_CFG_6 0x114 EGR0_ETH2_FLOW_CFG_7 Table 314 • Ethernet VLAN Tag Range Match Register Bit Name Description Access Default 27:16 EGR0_ETH2_VLAN_TAG_RANGE_UPP This register contains the upper range of R/W ER the VLAN tag range match. 0xFFF 11:0 EGR0_ETH2_VLAN_TAG_RANGE_LOW This register contains the lower range of R/W ER the VLAN tag range match. 0x000 4.31.22 VLAN Tag 1 Match/Mask Short Name: EGR0_ETH2_VLAN_TAG1 Addresses: 0xA5 EGR0_ETH2_FLOW_CFG_0 0xB5 EGR0_ETH2_FLOW_CFG_1 0xC5 EGR0_ETH2_FLOW_CFG_2 0xD5 EGR0_ETH2_FLOW_CFG_3 0xE5 EGR0_ETH2_FLOW_CFG_4 0xF5 EGR0_ETH2_FLOW_CFG_5 0x105 EGR0_ETH2_FLOW_CFG_6 VMDS-10509 VSC8572-02 Datasheet Revision 4.2 218 0x115 EGR0_ETH2_FLOW_CFG_7 Table 315 • VLAN Tag 1 Match/Mask Register Bit Name Description Access Default 27:16 EGR0_ETH2_VLAN_TAG1_MAS K Mask value for VLAN tag 1 R/W 0xFFF 11:0 EGR0_ETH2_VLAN_TAG1_MAT CH Match value for the first VLAN tag R/W 0x000 4.31.23 Match/Mask For VLAN Tag 2 or I-Tag Match Short Name: EGR0_ETH2_VLAN_TAG2_I_TAG Addresses: 0xA6 EGR0_ETH2_FLOW_CFG_0 0xB6 EGR0_ETH2_FLOW_CFG_1 0xC6 EGR0_ETH2_FLOW_CFG_2 0xD6 EGR0_ETH2_FLOW_CFG_3 0xE6 EGR0_ETH2_FLOW_CFG_4 0xF6 EGR0_ETH2_FLOW_CFG_5 0x106 EGR0_ETH2_FLOW_CFG_6 0x116 EGR0_ETH2_FLOW_CFG_7 Table 316 • Match/Mask For VLAN Tag 2 or I-Tag Match Register Bit Name 27:16 11:0 4.32 Description Access Default EGR0_ETH2_VLAN_TAG2_MASK Mask field for VLAN tag 2 R/W 0xFFF EGR0_ETH2_VLAN_TAG2_MATC Match field for VLAN Tag 2 H R/W 0x000 Egress0 MPLS Next Protocol Registers This section provides information about the MPLS next protocol registers. 4.32.1 MPLS Next Protocol Comparator Short Name: EGR0_MPLS_NXT_COMPARATOR Address: 0x120 Table 317 • MPLS Next Protocol Comparator Register Bit Name Description 16 EGR0_MPLS_CTL_WORD Indicates the presence of a control word after the R/W last label. The first 4 bits of the control word are always 0. 0: There is no control word after the last label 1: There is a control word after the last label VMDS-10509 VSC8572-02 Datasheet Revision 4.2 Access Default 0x0 219 Table 317 • MPLS Next Protocol Comparator Register (continued) Bit Name Description Access Default 2:0 EGR0_MPLS_NXT_COMPARAT OR Points to the next comparator stage. If this comparator block is not used, this field must be set to 0. 0: Comparator block not used. 1: Ethernet comparator 2 2: IP/UDP/ACH comparator 1 3: IP/UDP/ACH comparator 2 4: Reserved 5: PTP/OAM comparator 6,7: Reserved R/W 0x0 4.32.2 Instance offsets: 0x130 EGR0_MPLS_FLOW_CFG_0 0x140 EGR0_MPLS_FLOW_CFG_1 0x150 EGR0_MPLS_FLOW_CFG_2 0x160 EGR0_MPLS_FLOW_CFG_3 0x170 EGR0_MPLS_FLOW_CFG_4 0x180 EGR0_MPLS_FLOW_CFG_5 0x190 EGR0_MPLS_FLOW_CFG_6 0x1A0 EGR0_MPLS_FLOW_CFG_7 4.32.3 MPLS Flow Control Short Name: EGR0_MPLS_FLOW_CONTROL Addresses: 0x130 EGR0_MPLS_FLOW_CFG_0 0x140 EGR0_MPLS_FLOW_CFG_1 0x150 EGR0_MPLS_FLOW_CFG_2 0x160 EGR0_MPLS_FLOW_CFG_3 0x170 EGR0_MPLS_FLOW_CFG_4 0x180 EGR0_MPLS_FLOW_CFG_5 0x190 EGR0_MPLS_FLOW_CFG_6 0x1A0 EGR0_MPLS_FLOW_CFG_7 Table 318 • MPLS Flow Control Register Bit Name Description 25:24 EGR0_MPLS_CHANNEL_MA SK 0: Flow valid for channel 0 1: Flow valid for channel 1 VMDS-10509 VSC8572-02 Datasheet Revision 4.2 Access Default R/W 0x3 220 Table 318 • MPLS Flow Control Register (continued) Bit Name 19:16 EGR0_MPLS_STACK_DEPTH Defines the allowable stack depths for searches. R/W The direction that the stack is referenced is determined by the setting of MPLS_REF_PNT. For each bit set, The following table maps bits to stack depths: 0: stack allowed to be 1 label deep 1: stack allowed to be 2 labels deep 2: stack allowed to be 3 labels deep 3: stack allowed to be 4 labels deep 0x0 4 EGR0_MPLS_REF_PNT Defines the search direction for label matching R/W 0: All searching is performed starting from the top of the stack 1: All searching is performed from the end of the stack 0x0 0 EGR0_MPLS_FLOW_ENA Flow enable. If this comparator block is not used, R/W all flow enable bits must be set to 0. 0: Flow is disabled 1: Flow is enabled 0x0 4.32.4 Description Access Default MPLS Label 0 Match Range Lower Value Short Name: EGR0_MPLS_LABEL_RANGE_LOWER_0 Addresses: 0x132 EGR0_MPLS_FLOW_CFG_0 0x142 EGR0_MPLS_FLOW_CFG_1 0x152 EGR0_MPLS_FLOW_CFG_2 0x162 EGR0_MPLS_FLOW_CFG_3 0x172 EGR0_MPLS_FLOW_CFG_4 0x182 EGR0_MPLS_FLOW_CFG_5 0x192 EGR0_MPLS_FLOW_CFG_6 0x1A2 EGR0_MPLS_FLOW_CFG_7 Table 319 • MPLS Label 0 Match Range Lower Value Register Bit Name Description Access Default 19:0 EGR0_MPLS_LABEL_RANGE_LOWE R_0 Lower value for label 0 match range R/W 0x00000 4.32.5 MPLS Label 0 Match Range Upper Value Short Name: EGR0_MPLS_LABEL_RANGE_UPPER_0 Addresses: 0x133 EGR0_MPLS_FLOW_CFG_0 0x143 EGR0_MPLS_FLOW_CFG_1 0x153 EGR0_MPLS_FLOW_CFG_2 0x163 EGR0_MPLS_FLOW_CFG_3 0x173 EGR0_MPLS_FLOW_CFG_4 0x183 EGR0_MPLS_FLOW_CFG_5 VMDS-10509 VSC8572-02 Datasheet Revision 4.2 221 0x193 EGR0_MPLS_FLOW_CFG_6 0x1A3 EGR0_MPLS_FLOW_CFG_7 Table 320 • MPLS Label 0 Match Range Upper Value Register Bit Name 19:0 EGR0_MPLS_LABEL_RANGE_UPPER Upper value for label 0 match range _0 4.32.6 Description Access Default R/W 0xFFFFF Access Default R/W 0x00000 MPLS Label 1 Match Range Lower Value Short Name: EGR0_MPLS_LABEL_RANGE_LOWER_1 Addresses: 0x134 EGR0_MPLS_FLOW_CFG_0 0x144 EGR0_MPLS_FLOW_CFG_1 0x154 EGR0_MPLS_FLOW_CFG_2 0x164 EGR0_MPLS_FLOW_CFG_3 0x174 EGR0_MPLS_FLOW_CFG_4 0x184 EGR0_MPLS_FLOW_CFG_5 0x194 EGR0_MPLS_FLOW_CFG_6 0x1A4 EGR0_MPLS_FLOW_CFG_7 Table 321 • MPLS Label 1 Match Range Lower Value Register Bit Name 19:0 EGR0_MPLS_LABEL_RANGE_LOWER Lower value for label 1 match range _1 4.32.7 Description MPLS Label 1 Match Range Lower Value Short Name: EGR0_MPLS_LABEL_RANGE_UPPER_1 Addresses: 0x135 EGR0_MPLS_FLOW_CFG_0 0x145 EGR0_MPLS_FLOW_CFG_1 0x155 EGR0_MPLS_FLOW_CFG_2 0x165 EGR0_MPLS_FLOW_CFG_3 0x175 EGR0_MPLS_FLOW_CFG_4 0x185 EGR0_MPLS_FLOW_CFG_5 0x195 EGR0_MPLS_FLOW_CFG_6 0x1A5 EGR0_MPLS_FLOW_CFG_7 Table 322 • MPLS Label 1 Match Range Lower Value Register Bit Name Description Access Default 19:0 EGR0_MPLS_LABEL_RANGE_UPPE R_1 Upper value for label 1 match range R/W 0xFFFFF 4.32.8 MPLS Label 2 Match Range Lower Value Short Name: EGR0_MPLS_LABEL_RANGE_LOWER_2 VMDS-10509 VSC8572-02 Datasheet Revision 4.2 222 Addresses: 0x136 EGR0_MPLS_FLOW_CFG_0 0x146 EGR0_MPLS_FLOW_CFG_1 0x156 EGR0_MPLS_FLOW_CFG_2 0x166 EGR0_MPLS_FLOW_CFG_3 0x176 EGR0_MPLS_FLOW_CFG_4 0x186 EGR0_MPLS_FLOW_CFG_5 0x196 EGR0_MPLS_FLOW_CFG_6 0x1A6 EGR0_MPLS_FLOW_CFG_7 Table 323 • MPLS Label 2 Match Range Lower Value Register Bit Name 19:0 EGR0_MPLS_LABEL_RANGE_LOWER Lower value for label 2 match range _2 4.32.9 Description Access Default R/W 0x00000 MPLS Label 2 Match Range Lower Value Short Name: EGR0_MPLS_LABEL_RANGE_UPPER_2 Addresses: 0x137 EGR0_MPLS_FLOW_CFG_0 0x147 EGR0_MPLS_FLOW_CFG_1 0x157 EGR0_MPLS_FLOW_CFG_2 0x167 EGR0_MPLS_FLOW_CFG_3 0x177 EGR0_MPLS_FLOW_CFG_4 0x187 EGR0_MPLS_FLOW_CFG_5 0x197 EGR0_MPLS_FLOW_CFG_6 0x1A7 EGR0_MPLS_FLOW_CFG_7 Table 324 • MPLS Label 2 Match Range Lower Value Register Bit Name Description Access Default 19:0 EGR0_MPLS_LABEL_RANGE_UPPE R_2 Upper value for label 2 match range R/W 0xFFFFF 4.32.10 MPLS Label 3 Match Range Lower Value Short Name: EGR0_MPLS_LABEL_RANGE_LOWER_3 Addresses: 0x138 EGR0_MPLS_FLOW_CFG_0 0x148 EGR0_MPLS_FLOW_CFG_1 0x158 EGR0_MPLS_FLOW_CFG_2 0x168 EGR0_MPLS_FLOW_CFG_3 0x178 EGR0_MPLS_FLOW_CFG_4 0x188 EGR0_MPLS_FLOW_CFG_5 0x198 EGR0_MPLS_FLOW_CFG_6 VMDS-10509 VSC8572-02 Datasheet Revision 4.2 223 0x1A8 EGR0_MPLS_FLOW_CFG_7 Table 325 • MPLS Label 3 Match Range Lower Value Register Bit Name Description 19:0 EGR0_MPLS_LABEL_RANGE_LOWER Lower value for label 3 match range _3 Access Default R/W 0x00000 4.32.11 MPLS Label 3 Match Range Lower Value Short Name: EGR0_MPLS_LABEL_RANGE_UPPER_3 Addresses: 0x139 EGR0_MPLS_FLOW_CFG_0 0x149 EGR0_MPLS_FLOW_CFG_1 0x159 EGR0_MPLS_FLOW_CFG_2 0x169 EGR0_MPLS_FLOW_CFG_3 0x179 EGR0_MPLS_FLOW_CFG_4 0x189 EGR0_MPLS_FLOW_CFG_5 0x199 EGR0_MPLS_FLOW_CFG_6 0x1A9 EGR0_MPLS_FLOW_CFG_7 Table 326 • MPLS Label 3 Match Range Lower Value Register Bit Name Description Access Default 19:0 EGR0_MPLS_LABEL_RANGE_UPPE R_3 Upper value for label 3 match range R/W 0xFFFFF 4.32.12 IP Next Comparator Control Short Name: EGR0_IP1_NXT_COMPARATOR Address: 0x1B0 Table 327 • IP Next Comparator Control Register Bit Name Description Access Default 15:8 EGR0_IP1_NXT_PROTOCOL Number of bytes in this header, points to the beginning of the next protocol R/W 0x00 2:0 EGR0_IP1_NXT_COMPARAT OR Points to the next comparator stage. If this comparator block is not used, this field must be set to 0. 0: Comparator block not used 1: Reserved 2: Reserved 3: IP/UDP/ACH comparator 2 4: Reserved 5: PTP/OAM comparator 6,7: Reserved R/W 0x0 4.32.13 IP Comparator Mode Short Name: EGR0_IP1_MODE VMDS-10509 VSC8572-02 Datasheet Revision 4.2 224 Address: 0x1B1 Table 328 • IP Comparator Mode Register Bit Name Description Access 12:8 EGR0_IP1_FLOW_OFFSE Points to the source address field in the IP frame. R/W T Use 12 for IPv4 and 8 for IPv6 0x0C 1:0 EGR0_IP1_MODE 0x0 R/W Default 0: IPv4 1: IPv6 2: Other protocol, 32-bit address match 3: Other protocol, 128-bit address match 4.32.14 IP Match Set 1 Short Name: EGR0_IP1_PROT_MATCH_1 Address: 0x1B2 Table 329 • IP Match Set 1 Register Bit Name 20:16 Description Access Default EGR0_IP1_PROT_OFFSET_ Points to the start of this match field relative to 1 the first byte of this protocol R/W 0x00 15:8 EGR0_IP1_PROT_MASK_1 R/W 0x00 7:0 EGR0_IP1_PROT_MATCH_1 8-bit match field R/W 0x00 Mask field for IP_PROT_MATCH_1 4.32.15 Upper Portion of Match 2 Short Name: EGR0_IP1_PROT_MATCH_2_UPPER Address: 0x1B3 Table 330 • Upper Portion of Match 2 Register Bit Name Description 31:0 EGR0_IP1_PROT_MATCH_2_UPP 64-bit match register for advancing to the ER next protocol, upper portion Access Default R/W 0x00000000 4.32.16 Lower Portion of Match 2 Short Name: EGR0_IP1_PROT_MATCH_2_LOWER Address: 0x1B4 Table 331 • Lower Portion of Match 2 Register Bit Name Description Access 31:0 EGR0_IP1_PROT_MATCH_2_LOW ER 64-bit match register for advancing to the R/W next protocol, lower portion Default 0x00000000 4.32.17 Upper Portion of Match Mask 2 Short Name: EGR0_IP1_PROT_MASK_2_UPPER VMDS-10509 VSC8572-02 Datasheet Revision 4.2 225 Address: 0x1B5 Table 332 • Upper Portion of Match Mask 2 Register Bit Name Description 31:0 EGR0_IP1_PROT_MASK_2_UPP ER Access Default R/W 0x00000000 4.32.18 Lower Portion of Match Mask 2 Short Name: EGR0_IP1_PROT_MASK_2_LOWER Address: 0x1B6 Table 333 • Lower Portion of Match Mask 2 Register Bit Name Description 31:0 EGR0_IP1_PROT_MASK_2_LOW ER Access Default R/W 0x00000000 4.32.19 Match Offset 2 Short Name: EGR0_IP1_PROT_OFFSET_2 Address: 0x1B7 Table 334 • Match Offset 2 Register Bit Name Description Access 6:0 EGR0_IP1_PROT_OFFSET Points to the start of match field 2 relative to the R/W _2 first byte of this protocol Default 0x00 4.32.20 IP/UDP Checksum Control Short Name: EGR0_IP1_UDP_CHKSUM_CFG Address: 0x1B8 Table 335 • IP/UDP Checksum Control Register Bit Name Description 15:8 EGR0_IP1_UDP_CHKSUM_OFFSET Pointer to the IP/UDP checksum field FOR R/W IPv4 frames or to the pad bytes of a IPv6/UDP frame. For IPv4, it points to the bytes that will be cleared. For IPv6, it points to the bytes that will be updated to fix the CRC 0x00 5:4 EGR0_IP1_UDP_CHKSUM_WIDTH Specifies the length of the checksum field in bytes R/W 0x2 1 EGR0_IP1_UDP_CHKSUM_UPDATE_E This bit and IP_UDP_CHKSUM_CLEAR_ENA R/W NA CANNOT be set together. 1: Update the pad bytes at the end of the frame 0: No pad byte field update 0x0 VMDS-10509 VSC8572-02 Datasheet Revision 4.2 Access Default 226 Table 335 • IP/UDP Checksum Control Register (continued) Bit Name Description Access Default 0 EGR0_IP1_UDP_CHKSUM_CLEAR_EN This bit and R/W A IP_UDP_CHKSUM_UPDATE_ENA CANNOT be set together. 1: Clear the UDP checksum field in an IPv4 frame 0: Do not clear the checksum 0x0 4.32.21 IP Frame Signature Control Short Name: EGR0_IP1_FRAME_SIG_CFG Address: 0x1B9 Table 336 • IP Frame Signature Control Register Bit Name Description Access 4:0 EGR0_IP1_FRAME_SIG_OFFSE Pointer to the start of the field that will be used for R/W T the frame signature. Position is relative to the first header byte of this IP protocol. Only even values are allowed. Default 0x00 4.32.22 Instance offsets: 0x1C0 EGR0_IP1_FLOW_CFG_0 0x1D0 EGR0_IP1_FLOW_CFG_1 0x1E0 EGR0_IP1_FLOW_CFG_2 0x1F0 EGR0_IP1_FLOW_CFG_3 0x200 EGR0_IP1_FLOW_CFG_4 0x210 EGR0_IP1_FLOW_CFG_5 0x220 EGR0_IP1_FLOW_CFG_6 0x230 EGR0_IP1_FLOW_CFG_7 4.32.23 IP Flow Enable Short Name: EGR0_IP1_FLOW_ENA Addresses: 0x1C0 EGR0_IP1_FLOW_CFG_0 0x1D0 EGR0_IP1_FLOW_CFG_1 0x1E0 EGR0_IP1_FLOW_CFG_2 0x1F0 EGR0_IP1_FLOW_CFG_3 0x200 EGR0_IP1_FLOW_CFG_4 0x210 EGR0_IP1_FLOW_CFG_5 0x220 EGR0_IP1_FLOW_CFG_6 VMDS-10509 VSC8572-02 Datasheet Revision 4.2 227 0x230 EGR0_IP1_FLOW_CFG_7 Table 337 • IP Flow Enabler Register Bit Name 9:8 5:4 Description Access Default EGR0_IP1_FLOW_MATCH_MOD E 0: Match on source address 1: Match on destination address 2: Match on either source or destination address 3: reserved R/W 0x0 EGR0_IP1_CHANNEL_MASK R/W 0x3 R/W 0x0 0: Flow valid for channel 0 1: Flow valid for channel 1 0 EGR0_IP1_FLOW_ENA Flow enable. If this comparator block is not used, all flow enable bits must be set to 0. 1: This flow is enabled 0: This flow is not enabled 4.32.24 Upper Portion of the IP Flow Match Short Name: EGR0_IP1_FLOW_MATCH_UPPER Addresses: 0x1C1 EGR0_IP1_FLOW_CFG_0 0x1D1 EGR0_IP1_FLOW_CFG_1 0x1E1 EGR0_IP1_FLOW_CFG_2 0x1F1 EGR0_IP1_FLOW_CFG_3 0x201 EGR0_IP1_FLOW_CFG_4 0x211 EGR0_IP1_FLOW_CFG_5 0x221 EGR0_IP1_FLOW_CFG_6 0x231 EGR0_IP1_FLOW_CFG_7 Table 338 • Upper Portion of the IP Flow Match Register Bit Name Description Access Default 31:0 EGR0_IP1_FLOW_MATCH_UPP ER Match field for either the entire 32-bit selected address for IPv4 or the upper 32 bits of the selected address for IPv6 R/W 0x00000000 4.32.25 Upper Mid Portion of the IP Flow Match Short Name: EGR0_IP1_FLOW_MATCH_UPPER_MID Addresses: 0x1C2 EGR0_IP1_FLOW_CFG_0 0x1D2 EGR0_IP1_FLOW_CFG_1 0x1E2 EGR0_IP1_FLOW_CFG_2 0x1F2 EGR0_IP1_FLOW_CFG_3 0x202 EGR0_IP1_FLOW_CFG_4 0x212 EGR0_IP1_FLOW_CFG_5 0x222 EGR0_IP1_FLOW_CFG_6 VMDS-10509 VSC8572-02 Datasheet Revision 4.2 228 0x232 EGR0_IP1_FLOW_CFG_7 Table 339 • Upper Mid Portion of the IP Flow Match Register Bit Name Description Access 31:0 EGR0_IP1_FLOW_MATCH_UPPER_M Match bits for the upper middle 32 bits of R/W ID the IPv6 address Default 0x00000000 4.32.26 Lower Mid Portion of the IP Flow Match Short Name: EGR0_IP1_FLOW_MATCH_LOWER_MID Addresses: 0x1C3 EGR0_IP1_FLOW_CFG_0 0x1D3 EGR0_IP1_FLOW_CFG_1 0x1E3 EGR0_IP1_FLOW_CFG_2 0x1F3 EGR0_IP1_FLOW_CFG_3 0x203 EGR0_IP1_FLOW_CFG_4 0x213 EGR0_IP1_FLOW_CFG_5 0x223 EGR0_IP1_FLOW_CFG_6 0x233 EGR0_IP1_FLOW_CFG_7 Table 340 • Lower Mid Portion of the IP Flow Match Register Bit Name Description Access 31:0 EGR0_IP1_FLOW_MATCH_LOWER_M Match bits for the lower middle 32 bits of R/W ID the IPv6 address Default 0x00000000 4.32.27 Lower Portion of the IP Flow Match Short Name: EGR0_IP1_FLOW_MATCH_LOWER Addresses: 0x1C4 EGR0_IP1_FLOW_CFG_0 0x1D4 EGR0_IP1_FLOW_CFG_1 0x1E4 EGR0_IP1_FLOW_CFG_2 0x1F4 EGR0_IP1_FLOW_CFG_3 0x204 EGR0_IP1_FLOW_CFG_4 0x214 EGR0_IP1_FLOW_CFG_5 0x224 EGR0_IP1_FLOW_CFG_6 0x234 EGR0_IP1_FLOW_CFG_7 Table 341 • Lower Portion of the IP Flow Match Register Bit Name Description 31:0 EGR0_IP1_FLOW_MATCH_LOW Match bits for the lower 32 bits of the IPv6 ER address Access Default R/W 0x00000000 4.32.28 IP Flow Match Mask Short Name: EGR0_IP1_FLOW_MASK_UPPER Addresses: 0x1C5 EGR0_IP1_FLOW_CFG_0 VMDS-10509 VSC8572-02 Datasheet Revision 4.2 229 0x1D5 EGR0_IP1_FLOW_CFG_1 0x1E5 EGR0_IP1_FLOW_CFG_2 0x1F5 EGR0_IP1_FLOW_CFG_3 0x205 EGR0_IP1_FLOW_CFG_4 0x215 EGR0_IP1_FLOW_CFG_5 0x225 EGR0_IP1_FLOW_CFG_6 0x235 EGR0_IP1_FLOW_CFG_7 Table 342 • IP Flow Match Mask Register Bit Name Description Access Default 31:0 EGR0_IP1_FLOW_MASK_UPP ER This is the address mask for the IP address. R/W 0x00000000 Access Default 4.32.29 Upper Mid Portion Of IP Flow Mask Short Name: EGR0_IP1_FLOW_MASK_UPPER_MID Addresses: 0x1C6 EGR0_IP1_FLOW_CFG_0 0x1D6 EGR0_IP1_FLOW_CFG_1 0x1E6 EGR0_IP1_FLOW_CFG_2 0x1F6 EGR0_IP1_FLOW_CFG_3 0x206 EGR0_IP1_FLOW_CFG_4 0x216 EGR0_IP1_FLOW_CFG_5 0x226 EGR0_IP1_FLOW_CFG_6 0x236 EGR0_IP1_FLOW_CFG_7 Table 343 • Upper Mid Portion of IP Flow Mask Register Bit Name 31:0 EGR0_IP1_FLOW_MASK_UPPER_MI These bits must be all 0 for IPv4 and any R/W D 32-bit address match mode Description 0x00000000 4.32.30 Lower Mid Portion of IP Flow Mask Short Name: EGR0_IP1_FLOW_MASK_LOWER_MID Addresses: 0x1C7 EGR0_IP1_FLOW_CFG_0 0x1D7 EGR0_IP1_FLOW_CFG_1 0x1E7 EGR0_IP1_FLOW_CFG_2 0x1F7 EGR0_IP1_FLOW_CFG_3 0x207 EGR0_IP1_FLOW_CFG_4 0x217 EGR0_IP1_FLOW_CFG_5 0x227 EGR0_IP1_FLOW_CFG_6 VMDS-10509 VSC8572-02 Datasheet Revision 4.2 230 0x237 EGR0_IP1_FLOW_CFG_7 Table 344 • Lower Mid Portion of IP Flow Mask Register Bit Name Description 31:0 EGR0_IP1_FLOW_MASK_LOWER_MI These bits must be all 0 for IPv4 and D any 32-bit address match mode Access Default R/W 0x00000000 4.32.31 Lower Portion of IP Flow Mask Short Name: EGR0_IP1_FLOW_MASK_LOWER Addresses: 0x1C8 EGR0_IP1_FLOW_CFG_0 0x1D8 EGR0_IP1_FLOW_CFG_1 0x1E8 EGR0_IP1_FLOW_CFG_2 0x1F8 EGR0_IP1_FLOW_CFG_3 0x208 EGR0_IP1_FLOW_CFG_4 0x218 EGR0_IP1_FLOW_CFG_5 0x228 EGR0_IP1_FLOW_CFG_6 0x238 EGR0_IP1_FLOW_CFG_7 Table 345 • Lower Portion of IP Flow Mask Register Bit Name Description Access Default 31:0 EGR0_IP1_FLOW_MASK_LOW ER These bits must be all 0 for IPv4 and any 32-bit address match mode R/W 0x00000000 4.32.32 IP Next Comparator Control Short Name: EGR0_IP2_NXT_COMPARATOR Address: 0x240 Table 346 • IP Next Comparator Control Register Bit Name Description Access Default 15:8 EGR0_IP2_NXT_PROTOCOL Number of bytes in this header, points to the beginning of the next protocol R/W 0x00 2:0 EGR0_IP2_NXT_COMPARATO Points to the next comparator stage. If this R comparator block is not used, this field must be set to 0. 0: Comparator block not used 1: Reserved 2: Reserved 3: Reserved 4: Reserved 5: PTP/OAM comparator 6,7: Reserved R/W 0x0 4.32.33 IP Comparator Mode Short Name: EGR0_IP2_MODE VMDS-10509 VSC8572-02 Datasheet Revision 4.2 231 Address: 0x241 Table 347 • IP Comparator Mode Register Bit Name Description Access Default 12:8 EGR0_IP2_FLOW_OFFSE Points to the source address field in the IP frame. R/W T Use 12 for IPv4 and 8 for IPv6 0x0C 1:0 EGR0_IP2_MODE 0x0 R/W 0: IPv4 1: IPv6 2: Other protocol, 32-bit address match 3: Other protocol, 128-bit address match 4.32.34 IP Match Register Set 1 Short Name: EGR0_IP2_PROT_MATCH_1 Address: 0x242 Table 348 • IP Match Register Set 1 Register Bit Name 20:16 Description Access Default EGR0_IP2_PROT_OFFSET_ Points to the start of this match field relative to 1 the first byte of this protocol R/W 0x00 15:8 EGR0_IP2_PROT_MASK_1 R/W 0x00 7:0 EGR0_IP2_PROT_MATCH_1 8-bit match field R/W 0x00 Mask field for IP_PROT_MATCH_1 4.32.35 Upper Portion of Match 2 Short Name: EGR0_IP2_PROT_MATCH_2_UPPER Address: 0x243 Table 349 • Upper Portion of Match 2 Register Bit Name Description 31:0 EGR0_IP2_PROT_MATCH_2_UPP 64-bit match register for advancing to the ER next protocol, upper portion Access Default R/W 0x00000000 Access Default 4.32.36 Lower Portion of Match 2 Short Name: EGR0_IP2_PROT_MATCH_2_LOWER Address: 0x244 Table 350 • Lower Portion of Match 2 Register Bit Name Description 31:0 EGR0_IP2_PROT_MATCH_2_LOW 64-bit match register for advancing to the R/W ER next protocol, lower portion 0x00000000 4.32.37 Upper Portion of Match Mask 2 Short Name: EGR0_IP2_PROT_MASK_2_UPPER VMDS-10509 VSC8572-02 Datasheet Revision 4.2 232 Address: 0x245 Table 351 • Upper Portion of Match Mask 2 Register Bit Name Description 31:0 EGR0_IP2_PROT_MASK_2_UPPE R Access Default R/W 0x00000000 Access Default R/W 0x00000000 4.32.38 Lower Portion of Match Mask 2 Short Name: EGR0_IP2_PROT_MASK_2_LOWER Address: 0x246 Table 352 • Lower Portion of Match Mask 2 Register Bit Name Description 31:0 EGR0_IP2_PROT_MASK_2_LOWE R 4.32.39 Match Offset Register 2 Short Name: EGR0_IP2_PROT_OFFSET_2 Address: 0x247 Table 353 • Match Offset 2 Register Bit Name Description Access 6:0 EGR0_IP2_PROT_OFFSET_ Points to the start of match field 2 relative to the R/W 2 first byte of this protocol Default 0x00 4.32.40 IP/UDP Checksum Control Short Name: EGR0_IP2_UDP_CHKSUM_CFG Address: 0x248 Table 354 • IP/UDP Checksum Control Register Bit Name Description Access Default 15:8 EGR0_IP2_UDP_CHKSUM_OFFSET Pointer to the IP/UDP checksum field FOR IPv4 frames or to the pad bytes of a IPv6/UDP frame. For IPv4, it points to the bytes that will be cleared. For IPv6, it points to the bytes that will be updated to fix the CRC R/W 5:4 EGR0_IP2_UDP_CHKSUM_WIDTH Specifies the length of the checksum field in R/W bytes 0x2 1 EGR0_IP2_UDP_CHKSUM_UPDATE_E NA This bit and R/W IP_UDP_CHKSUM_CLEAR_ENA CANNOT be set together. 1: Update the pad bytes at the end of the frame 0: No pad byte field update 0x0 VMDS-10509 VSC8572-02 Datasheet Revision 4.2 0x00 233 Table 354 • IP/UDP Checksum Control Register (continued) Bit Name Description Access Default 0 EGR0_IP2_UDP_CHKSUM_CLEAR_EN A This bit and IP_UDP_CHKSUM_UPDATE_ENA CANNOT be set together. 1: Clear the UDP checksum field in an IPv4 frame 0: Do not clear the checksum R/W 0x0 4.32.41 IP Frame Signature Control Short Name: EGR0_IP2_FRAME_SIG_CFG Address: 0x249 Table 355 • IP Frame Signature Control Register Bit Name Description Access 4:0 EGR0_IP2_FRAME_SIG_OFFS ET Pointer to the start of the field that will be used for R/W the frame signature. Position is relative to the first header byte of this IP protocol. Only even values are allowed. Default 0x00 4.32.42 Instance offsets: 0x250 EGR0_IP2_FLOW_CFG_0 0x260 EGR0_IP2_FLOW_CFG_1 0x270 EGR0_IP2_FLOW_CFG_2 0x280 EGR0_IP2_FLOW_CFG_3 0x290 EGR0_IP2_FLOW_CFG_4 0x2A0 EGR0_IP2_FLOW_CFG_5 0x2B0 EGR0_IP2_FLOW_CFG_6 0x2C0 EGR0_IP2_FLOW_CFG_7 4.32.43 IP Flow Enable Short Name: EGR0_IP2_FLOW_ENA Addresses: 0x250 EGR0_IP2_FLOW_CFG_0 0x260 EGR0_IP2_FLOW_CFG_1 0x270 EGR0_IP2_FLOW_CFG_2 0x280 EGR0_IP2_FLOW_CFG_3 0x290 EGR0_IP2_FLOW_CFG_4 0x2A0 EGR0_IP2_FLOW_CFG_5 0x2B0 EGR0_IP2_FLOW_CFG_6 VMDS-10509 VSC8572-02 Datasheet Revision 4.2 234 0x2C0 EGR0_IP2_FLOW_CFG_7 Table 356 • IP Flow Enable Register Bit Name 9:8 EGR0_IP2_FLOW_MATCH_MO DE 5:4 Description Access Default R/W 0x0 R/W 0x3 R/W 0x0 Access Default 0: Match on source address 1: Match on destination address 2: Match on either source or destination address 3: reserved EGR0_IP2_CHANNEL_MASK bit 0: Flow valid for channel 0 bit 1: Flow valid for channel 1 0 EGR0_IP2_FLOW_ENA Flow enable. If this comparator block is not used, all flow enable bits must be set to 0. 1: This flow is enabled 0: This flow is not enabled 4.32.44 Upper Portion of the IP Flow Match Short Name: EGR0_IP2_FLOW_MATCH_UPPER Addresses: 0x251 EGR0_IP2_FLOW_CFG_0 0x261 EGR0_IP2_FLOW_CFG_1 0x271 EGR0_IP2_FLOW_CFG_2 0x281 EGR0_IP2_FLOW_CFG_3 0x291 EGR0_IP2_FLOW_CFG_4 0x2A1 EGR0_IP2_FLOW_CFG_5 0x2B1 EGR0_IP2_FLOW_CFG_6 0x2C1 EGR0_IP2_FLOW_CFG_7 Table 357 • Upper Portion of the IP Flow Match Register Bit Name Description 31:0 EGR0_IP2_FLOW_MATCH_UPP ER Match field for either the entire 32-bit selected R/W address for IPv4 or the upper 32 bits of the selected address for IPv6 0x00000000 4.32.45 Upper Mid Portion of the IP Flow Match Short Name: EGR0_IP2_FLOW_MATCH_UPPER_MID Addresses: 0x252 EGR0_IP2_FLOW_CFG_0 0x262 EGR0_IP2_FLOW_CFG_1 0x272 EGR0_IP2_FLOW_CFG_2 0x282 EGR0_IP2_FLOW_CFG_3 0x292 EGR0_IP2_FLOW_CFG_4 0x2A2 EGR0_IP2_FLOW_CFG_5 0x2B2 EGR0_IP2_FLOW_CFG_6 VMDS-10509 VSC8572-02 Datasheet Revision 4.2 235 0x2C2 EGR0_IP2_FLOW_CFG_7 Table 358 • Upper Mid Portion of the IP Flow Match Register Bit Name Description Access 31:0 EGR0_IP2_FLOW_MATCH_UPPER_M Match bits for the upper middle 32 bits of R/W ID the IPv6 address Default 0x00000000 4.32.46 Lower Mid Portion of the IP Flow Match Short Name: EGR0_IP2_FLOW_MATCH_LOWER_MID Addresses: 0x253 EGR0_IP2_FLOW_CFG_0 0x263 EGR0_IP2_FLOW_CFG_1 0x273 EGR0_IP2_FLOW_CFG_2 0x283 EGR0_IP2_FLOW_CFG_3 0x293 EGR0_IP2_FLOW_CFG_4 0x2A3 EGR0_IP2_FLOW_CFG_5 0x2B3 EGR0_IP2_FLOW_CFG_6 0x2C3 EGR0_IP2_FLOW_CFG_7 Table 359 • Lower Mid Portion of the IP Flow Match Register Bit Name Description Access 31:0 EGR0_IP2_FLOW_MATCH_LOWER_M Match bits for the lower middle 32 bits R/W ID of the IPv6 address Default 0x00000000 4.32.47 Lower Portion of the IP Flow Match Short Name: EGR0_IP2_FLOW_MATCH_LOWER Addresses: 0x254 EGR0_IP2_FLOW_CFG_0 0x264 EGR0_IP2_FLOW_CFG_1 0x274 EGR0_IP2_FLOW_CFG_2 0x284 EGR0_IP2_FLOW_CFG_3 0x294 EGR0_IP2_FLOW_CFG_4 0x2A4 EGR0_IP2_FLOW_CFG_5 0x2B4 EGR0_IP2_FLOW_CFG_6 0x2C4 EGR0_IP2_FLOW_CFG_7 Table 360 • Lower Portion of the IP Flow Match Register Bit Name Description Access Default 31:0 EGR0_IP2_FLOW_MATCH_LOW ER Match bits for the lower 32 bits of the IPv6 address R/W 0x00000000 4.32.48 Upper Portion of the IP Flow Match Mask Short Name: EGR0_IP2_FLOW_MASK_UPPER Addresses: 0x255 EGR0_IP2_FLOW_CFG_0 VMDS-10509 VSC8572-02 Datasheet Revision 4.2 236 0x265 EGR0_IP2_FLOW_CFG_1 0x275 EGR0_IP2_FLOW_CFG_2 0x285 EGR0_IP2_FLOW_CFG_3 0x295 EGR0_IP2_FLOW_CFG_4 0x2A5 EGR0_IP2_FLOW_CFG_5 0x2B5 EGR0_IP2_FLOW_CFG_6 0x2C5 EGR0_IP2_FLOW_CFG_7 Table 361 • Upper Portion of the IP Flow Match Mask Register Bit Name Description 31:0 EGR0_IP2_FLOW_MASK_UPPE This is the address mask for the IP address. R Access Default R/W 0x00000000 4.32.49 Upper Mid Portion of the IP Flow Match Mask Short Name: EGR0_IP2_FLOW_MASK_UPPER_MID Addresses: 0x256 EGR0_IP2_FLOW_CFG_0 0x266 EGR0_IP2_FLOW_CFG_1 0x276 EGR0_IP2_FLOW_CFG_2 0x286 EGR0_IP2_FLOW_CFG_3 0x296 EGR0_IP2_FLOW_CFG_4 0x2A6 EGR0_IP2_FLOW_CFG_5 0x2B6 EGR0_IP2_FLOW_CFG_6 0x2C6 EGR0_IP2_FLOW_CFG_7 Table 362 • Upper Mid Portion of the IP Flow Match Mask Register Bit Name 31:0 EGR0_IP2_FLOW_MASK_UPPER_MI These bits must be all 0 for IPv4 and any R/W D 32-bit address match mode Description Access Default 0x00000000 4.32.50 Lower Mid Portion of the IP Flow Match Mask Short Name: EGR0_IP2_FLOW_MASK_LOWER_MID Addresses: 0x257 EGR0_IP2_FLOW_CFG_0 0x267 EGR0_IP2_FLOW_CFG_1 0x277 EGR0_IP2_FLOW_CFG_2 0x287 EGR0_IP2_FLOW_CFG_3 0x297 EGR0_IP2_FLOW_CFG_4 0x2A7 EGR0_IP2_FLOW_CFG_5 0x2B7 EGR0_IP2_FLOW_CFG_6 VMDS-10509 VSC8572-02 Datasheet Revision 4.2 237 0x2C7 EGR0_IP2_FLOW_CFG_7 Table 363 • Lower Mid Portion of the IP Flow Match Mask Register Bit Name Description 31:0 EGR0_IP2_FLOW_MASK_LOWER_MI These bits must be all 0 for IPv4 and any D 32-bit address match mode Access Default R/W 0x00000000 4.32.51 Lower Portion of the IP Flow Match Mask Short Name: EGR0_IP2_FLOW_MASK_LOWER Addresses: 0x258 EGR0_IP2_FLOW_CFG_0 0x268 EGR0_IP2_FLOW_CFG_1 0x278 EGR0_IP2_FLOW_CFG_2 0x288 EGR0_IP2_FLOW_CFG_3 0x298 EGR0_IP2_FLOW_CFG_4 0x2A8 EGR0_IP2_FLOW_CFG_5 0x2B8 EGR0_IP2_FLOW_CFG_6 0x2C8 EGR0_IP2_FLOW_CFG_7 Table 364 • Lower Portion of the IP Flow Match Mask Register Bit Name Description Access Default 31:0 EGR0_IP2_FLOW_MASK_LOW ER These bits must be all 0 for IPv4 and any 32-bit address match mode R/W 0x00000000 4.32.52 Instance offsets: 0x2D0 EGR0_PTP_FLOW_0 0x2E0 EGR0_PTP_FLOW_1 0x2F0 EGR0_PTP_FLOW_2 0x300 EGR0_PTP_FLOW_3 0x310 EGR0_PTP_FLOW_4 0x320 EGR0_PTP_FLOW_5 4.32.53 PTP/OAM Flow Enable Short Name: EGR0_PTP_FLOW_ENA Addresses: 0x2D0 EGR0_PTP_FLOW_0 0x2E0 EGR0_PTP_FLOW_1 0x2F0 EGR0_PTP_FLOW_2 0x300 EGR0_PTP_FLOW_3 0x310 EGR0_PTP_FLOW_4 VMDS-10509 VSC8572-02 Datasheet Revision 4.2 238 0x320 EGR0_PTP_FLOW_5 Table 365 • PTP/OAM Flow Enable Register Bit Name 5:4 0 Description Access Default EGR0_PTP_CHANNEL_MAS K 0: Flow valid for channel 0 1: Flow valid for channel 1 R/W 0x3 EGR0_PTP_FLOW_ENA R/W 0x0 Access Default R/W 0x00000000 Access Default R/W 0x00000000 4.32.54 Upper Half of PTP/OAM Flow Match Field Short Name: EGR0_PTP_FLOW_MATCH_UPPER Addresses: 0x2D1 EGR0_PTP_FLOW_0 0x2E1 EGR0_PTP_FLOW_1 0x2F1 EGR0_PTP_FLOW_2 0x301 EGR0_PTP_FLOW_3 0x311 EGR0_PTP_FLOW_4 0x321 EGR0_PTP_FLOW_5 Table 366 • Upper Half of PTP/OAM Flow Match Field Register Bit Name Description 31:0 EGR0_PTP_FLOW_MATCH_UPPE R 4.32.55 Lower Half of PTP/OAM Flow Match Field Short Name: EGR0_PTP_FLOW_MATCH_LOWER Addresses: 0x2D2 EGR0_PTP_FLOW_0 0x2E2 EGR0_PTP_FLOW_1 0x2F2 EGR0_PTP_FLOW_2 0x302 EGR0_PTP_FLOW_3 0x312 EGR0_PTP_FLOW_4 0x322 EGR0_PTP_FLOW_5 Table 367 • Lower Half of PTP/OAM Flow Match Field Register Bit Name Description 31:0 EGR0_PTP_FLOW_MATCH_LOWE R 4.32.56 Upper Half of PTP/OAM Flow Match Mask Short Name: EGR0_PTP_FLOW_MASK_UPPER Addresses: 0x2D3 EGR0_PTP_FLOW_0 0x2E3 EGR0_PTP_FLOW_1 0x2F3 EGR0_PTP_FLOW_2 0x303 EGR0_PTP_FLOW_3 VMDS-10509 VSC8572-02 Datasheet Revision 4.2 239 0x313 EGR0_PTP_FLOW_4 0x323 EGR0_PTP_FLOW_5 Table 368 • Upper Half of PTP/OAM Flow Match Mask Register Bit Name Description 31:0 EGR0_PTP_FLOW_MASK_UPP ER Access Default R/W 0x00000000 Access Default R/W 0x00000000 4.32.57 Lower Half of PTP/OAM Flow Match Mask Short Name: EGR0_PTP_FLOW_MASK_LOWER Addresses: 0x2D4 EGR0_PTP_FLOW_0 0x2E4 EGR0_PTP_FLOW_1 0x2F4 EGR0_PTP_FLOW_2 0x304 EGR0_PTP_FLOW_3 0x314 EGR0_PTP_FLOW_4 0x324 EGR0_PTP_FLOW_5 Table 369 • Lower Half of PTP/OAM Flow Match Mask Register Bit Name Description 31:0 EGR0_PTP_FLOW_MASK_LOWE R 4.32.58 PTP/OAM Range Match Short Name: EGR0_PTP_DOMAIN_RANGE Addresses: 0x2D5 EGR0_PTP_FLOW_0 0x2E5 EGR0_PTP_FLOW_1 0x2F5 EGR0_PTP_FLOW_2 0x305 EGR0_PTP_FLOW_3 0x315 EGR0_PTP_FLOW_4 0x325 EGR0_PTP_FLOW_5 Table 370 • PTP/OAM Range Match Register Bit Name Access Default 28:24 EGR0_PTP_DOMAIN_RANGE_OFFSE T Description R/W 0x00 23:16 EGR0_PTP_DOMAIN_RANGE_UPPE R R/W 0xFF 15:8 EGR0_PTP_DOMAIN_RANGE_LOWE R R/W 0x00 0 EGR0_PTP_DOMAIN_RANGE_ENA R/W 0x0 4.32.59 PTP Action Control Short Name: EGR0_PTP_ACTION VMDS-10509 VSC8572-02 Datasheet Revision 4.2 240 Addresses: 0x2D6 EGR0_PTP_FLOW_0 0x2E6 EGR0_PTP_FLOW_1 0x2F6 EGR0_PTP_FLOW_2 0x306 EGR0_PTP_FLOW_3 0x316 EGR0_PTP_FLOW_4 0x326 EGR0_PTP_FLOW_5 Table 371 • PTP Action Control Register Bit Name Description 28 EGR0_PTP_MOD_FRAME_STAT_UPD ATE Access Default R/W 0x0 1: Tell the Rewriter to update the value of the Modified Frame Status bit 0: Do not update the bit 26:24 EGR0_PTP_MOD_FRAME_BYTE_OFF Indicates the position relative to the start of SET the PTP frame in bytes where the Modified_Frame_Status bit resides R/W 0x0 21 EGR0_PTP_SUB_DELAY_ASYM_ENA R/W 0x0 R/W 0x0 1: Signal the Timestamp block to subtract the asymmetry delay 0: Do not signal the Timestamp block to subtract the asymmetry delay 20 EGR0_PTP_ADD_DELAY_ASYM_ENA 1: Signal the Timestamp block to add the asymmetry delay 0: Do not signal the Timestamp block to add the asymmetry delay 15:10 EGR0_PTP_TIME_STRG_FIELD_OFFS Points to the reserved 32-bit field where the ET Rx timestamp is saved. The location is relative to the first byte of the PTP/OAM header. R/W 0x00 9:5 EGR0_PTP_CORR_FIELD_OFFSET R/W 0x00 4 EGR0_PTP_SAVE_LOCAL_TIME R/W 0x0 R/W 0x0 Points to the location of the correction field for updating the timestamp. Location is relative to the first byte of the PTP/OAM header. Note: If this flow is being used to match OAM frames, set this register to 4 1: Save the local time to the Timestamp FIFO 0: Do not save the time to the Timestamp FIFO 3:0 EGR0_PTP_COMMAND 0: NoP 1: SUB 2: SUB_P2P 3: ADD 4: SUB_ADD 5: WRITE_1588 6: WRITE_P2P (deprecated) 7: WRITE_NS 8: WRITE_NS_P2P VMDS-10509 VSC8572-02 Datasheet Revision 4.2 241 4.32.60 PTP Action Control 2 Short Name: EGR0_PTP_ACTION_2 Addresses: 0x2D7 EGR0_PTP_FLOW_0 0x2E7 EGR0_PTP_FLOW_1 0x2F7 EGR0_PTP_FLOW_2 0x307 EGR0_PTP_FLOW_3 0x317 EGR0_PTP_FLOW_4 0x327 EGR0_PTP_FLOW_5 Table 372 • PTP Action Control 2 Register Bit Name Description Access 23:16 EGR0_PTP_NEW_CF_LOC Location of the new correction field relative to the R/W PTP header start. Only even values are allowed. 0x00 15:8 EGR0_PTP_REWRITE_OFFS Byte offset relative to the start of the PTP frame R/W ET where the ingress timestamp value can be read. 0x00 3:0 EGR0_PTP_REWRITE_BYTE Number of bytes in the PTP or OAM frame that S must be modified by the Rewriter for the timestamp 0x0 R/W Default 4.32.61 Zero Field Control Short Name: EGR0_PTP_ZERO_FIELD_CTL Addresses: 0x2D8 EGR0_PTP_FLOW_0 0x2E8 EGR0_PTP_FLOW_1 0x2F8 EGR0_PTP_FLOW_2 0x308 EGR0_PTP_FLOW_3 0x318 EGR0_PTP_FLOW_4 0x328 EGR0_PTP_FLOW_5 Table 373 • Zero Field Control Register Bit Name 13:8 EGR0_PTP_ZERO_FIELD_OFFSET Points to a location in the PTP/OAM frame R/W relative to the start of the PTP header that will be zeroed if this function is enabled 0x00 3:0 EGR0_PTP_ZERO_FIELD_BYTE_C The number of bytes to be zeroed. If this field is NT 0, then this function is not enabled. 0x0 4.33 Description Access R/W Default Egress0 IP Checksum Field Control Registers This section provides information about the IP checksum field control registers. 4.33.1 IP Checksum Block Select Short Name: EGR0_PTP_IP_CKSUM_SEL VMDS-10509 VSC8572-02 Datasheet Revision 4.2 242 Address: 0x330 Table 374 • IP Checksum Block Select Register Bit Name Description 0 EGR0_PTP_IP_CHKSUM_SE L 0: Use the IP checksum controls from IP comparator 1 1: Use the IP checksum controls from IP comparator 2 Access Default R/W 0x0 4.34 Egress0 Frame Signature Builder Configuration Registers 4.34.1 Frame Signature Builder Mode Configuration Short Name: EGR0_FSB_CFG Address: 0x331 Table 375 • Frame Signature Builder Mode Configuration Register Bit Name Description 1:0 EGR0_FSB_ADR_SEL Access Default R/W 0x0 0: Use the address from Ethernet block 1 1: Use the address from Ethernet block 2 2: Use the address from IP block 1 3: Use the address from IP block 2 4.34.2 Frame Signature Builder Mapping 0 Short Name: EGR0_FSB_MAP_REG_0 Address: 0x332 This register selects bytes to pack into the frame signature vector. The frame signature vector is 16 bytes long. The following table lists the source bytes; all other select values are reserved. Table 376 • Source Bytes Select Source Select Source Select Source Select Source 0 PTP hdr byte 31 1 PTP hdr byte 30 2 PTP hdr byte 29 3 PTP hdr byte 28 4 PTP hdr byte 27 5 PTP hdr byte 26 6 PTP hdr byte 25 7 PTP hdr byte 24 8 PTP hdr byte 23 9 PTP hdr byte 22 10 PTP hdr byte 21 11 PTP hdr byte 20 12 PTP hdr byte 19 13 PTP hdr byte 18 14 PTP hdr byte 17 15 PTP hdr byte 16 16 PTP hdr byte 15 17 PTP hdr byte 14 18 PTP hdr byte 13 19 PTP hdr byte 12 20 PTP hdr byte 11 21 PTP hdr byte 10 22 PTP hdr byte 9 23 PTP hdr byte 8 24 PTP hdr byte 6 25 PTP hdr byte 4 26 PTP hdr byte 0 27 reserved 28 address byte 0 29 address byte 1 30 address byte 2 31 address byte 3 32 address byte 4 33 address byte 5 34 address byte 6 35 address byte 7 VMDS-10509 VSC8572-02 Datasheet Revision 4.2 243 Table 377 • Frame Signature Builder Mapping 0 Register Bit Name Description Access Default 29:24 EGR0_FSB_MAP_4 Frame signature byte 4 select R/W 0x04 23:18 EGR0_FSB_MAP_3 Frame signature byte 3 select R/W 0x03 17:12 EGR0_FSB_MAP_2 Frame signature byte 2 select R/W 0x02 11:6 EGR0_FSB_MAP_1 Frame signature byte 1 select R/W 0x01 5:0 EGR0_FSB_MAP_0 Frame signature byte 0 select R/W 0x00 4.34.3 Frame Signature Builder Mapping 1 Short Name: EGR0_FSB_MAP_REG_1 Address: 0x333 Table 378 • Frame Signature Builder Mapping 1 Register Bit Name Description Access Default 29:24 EGR0_FSB_MAP_9 Frame signature byte 9 select R/W 0x09 23:18 EGR0_FSB_MAP_8 Frame signature byte 8 select R/W 0x08 17:12 EGR0_FSB_MAP_7 Frame signature byte 7 select R/W 0x07 11:6 EGR0_FSB_MAP_6 Frame signature byte 6 select R/W 0x06 5:0 EGR0_FSB_MAP_5 Frame signature byte 5 select R/W 0x05 4.34.4 Frame Signature Builder Mapping 2 Short Name: EGR0_FSB_MAP_REG_2 Address: 0x334 Table 379 • Frame Signature Builder Mapping 2 Register Bit Name Description Access Default 29:24 EGR0_FSB_MAP_14 Frame signature byte 14 select R/W 0x0E 23:18 EGR0_FSB_MAP_13 Frame signature byte 13 select R/W 0x0D 17:12 EGR0_FSB_MAP_12 Frame signature byte 12 select R/W 0x0C 11:6 EGR0_FSB_MAP_11 Frame signature byte 11 select R/W 0x0B 5:0 EGR0_FSB_MAP_10 Frame signature byte 10 select R/W 0x0A 4.34.5 Frame Signature Builder Mapping 3 Short Name: EGR0_FSB_MAP_REG_3 Address: 0x335 Table 380 • Frame Signature Builder Mapping 3 Register Bit Name Description Access Default 5:0 EGR0_FSB_MAP_15 Frame signature byte 15 select R/W 0x0F VMDS-10509 VSC8572-02 Datasheet Revision 4.2 244 4.35 Ingress2 Analyzer Engine Configuration Registers This section lists the register overviews for the analyzer engine configuration ingress2 registers. Note: The analyzer engine configuration registers are not initialized to the default values during chip reset. Software must configure these registers to their default value. Note: For more information about accessing the 1588 IP registers, see Accessing 1588 IP Registers, page 72. Table 381 • INGR2_ETH1_NXT_PROTOCOL_A Address Name Details 0x00 INGR2_ETH1_NXT_PROTOCOL_A Ethernet Next Protocol, page 247 0x01 INGR2_ETH1_VLAN_TPID_CFG_A VLAN TPID Configuration, page 247 0x02 INGR2_ETH1_TAG_MODE_A Ethernet Tag Mode, page 248 0x03 INGR2_ETH1_ETYPE_MATCH_A Ethertype Match, page 248 Table 382 • INGR2_ETH1_NXT_PROTOCOL_B Address Name Details 0x10 INGR2_ETH1_NXT_PROTOCOL_ Ethernet Next Protocol, page 248 B 0x11 INGR2_ETH1_VLAN_TPID_CFG_ VLAN TPID Configuration B, page 249 B 0x12 INGR2_ETH1_TAG_MODE_B 0x13 INGR2_ETH1_ETYPE_MATCH_B Ethertype Match, page 249 Ethernet Tag Mode, page 249 Table 383 • INGR2_ETH1_FLOW_CFG (8 instances) Address Name Details 0x20 INGR2_ETH1_FLOW_ENABLE Ethernet Flow Enable, page 250 0x21 INGR2_ETH1_MATCH_MODE Ethernet Protocol Match Mode, page 250 0x22 INGR2_ETH1_ADDR_MATCH_1 Ethernet Address Match Part 1, page 251 0x23 INGR2_ETH1_ADDR_MATCH_2 Ethernet Address Match Part 2, page 252 0x24 INGR2_ETH1_VLAN_TAG_RANGE_I_ Ethernet VLAN Tag Range Match, page 252 TAG 0x25 INGR2_ETH1_VLAN_TAG1 VLAN Tag 1 Match/Mask, page 253 0x26 INGR2_ETH1_VLAN_TAG2_I_TAG Match/Mask For VLAN Tag 2 or I-Tag Match, page 253 Table 384 • INGR2_ETH2_NXT_PROTOCOL_A Address Name Details 0xA0 INGR2_ETH2_NXT_PROTOCOL_A Ethernet Next Protocol, page 254 VMDS-10509 VSC8572-02 Datasheet Revision 4.2 245 Table 384 • INGR2_ETH2_NXT_PROTOCOL_A (continued) Address Name Details 0xA1 INGR2_ETH2_VLAN_TPID_CFG_A VLAN TPID Configuration, page 254 0xA2 INGR2_ETH2_ETYPE_MATCH_A Ethertype Match, page 254 Table 385 • INGR2_ETH2_FLOW_CFG (8 instances) Address Name Details 0xC0 INGR2_ETH2_FLOW_ENABLE Ethernet Flow Enable, page 255 0xC1 INGR2_ETH2_MATCH_MODE Ethernet Protocol Match Mode, page 255 0xC2 INGR2_ETH2_ADDR_MATCH_1 Ethernet Address Match Part 1, page 256 0xC3 INGR2_ETH2_ADDR_MATCH_2 Ethernet Address Match Part 2, page 257 0xC4 INGR2_ETH2_VLAN_TAG_RANGE_I_TA Ethernet VLAN Tag Range Match, page 257 G 0xC5 INGR2_ETH2_VLAN_TAG1 VLAN Tag 1 Match/Mask, page 258 0xC6 INGR2_ETH2_VLAN_TAG2_I_TAG Match/Mask For VLAN Tag 2 or I-Tag Match, page 258 Table 386 • INGR2_MPLS_NXT_COMPARATOR_A Address Name Details 0x140 INGR2_MPLS_NXT_COMPARATOR MPLS Next Protocol Comparator, page 259 _A Table 387 • INGR2_MPLS_FLOW_CFG (8 instances) Address Name Details 0x160 INGR2_MPLS_FLOW_CONTROL MPLS Flow Control, page 259 0x161 INGR2_MPLS_LABEL_RANGE_LOWER_ MPLS Label 0 Match Range Lower Value, 0 page 260 0x162 INGR2_MPLS_LABEL_RANGE_UPPER_ MPLS Label 0 Match Range Lower Value, 0 page 260 0x163 INGR2_MPLS_LABEL_RANGE_LOWER_ MPLS Label 1 Match Range Lower Value, 1 page 261 0x164 INGR2_MPLS_LABEL_RANGE_UPPER_ MPLS Label 1 Match Range Lower Value, 1 page 261 0x165 INGR2_MPLS_LABEL_RANGE_LOWER_ MPLS Label 2 Match Range Lower Value, 2 page 262 0x166 INGR2_MPLS_LABEL_RANGE_UPPER_ MPLS Label 2 Match Range Lower Value, 2 page 262 0x167 INGR2_MPLS_LABEL_RANGE_LOWER_ MPLS Label 3 Match Range Lower Value, 3 page 262 VMDS-10509 VSC8572-02 Datasheet Revision 4.2 246 Table 387 • INGR2_MPLS_FLOW_CFG (8 instances) (continued) Address Name Details 0x168 INGR2_MPLS_LABEL_RANGE_UPPER_ MPLS Label 3 Match Range Lower Value, 3 page 263 Table 388 • INGR2_PTP_FLOW (6 instances) 4.36 Address Register Name Details 0x1E0 INGR2_PTP_FLOW_ENA PTP/OAM Flow Enable, page 263 0x1E1 INGR2_PTP_FLOW_MATCH_UPPE Upper Half of PTP/OAM Flow Match Field, R page 264 0x1E2 INGR2_PTP_FLOW_MATCH_LOW ER 0x1E3 INGR2_PTP_FLOW_MASK_UPPER Upper Half of PTP/OAM Flow Match Mask, page 265 0x1E4 INGR2_PTP_FLOW_MASK_LOWE R Lower Half of PTP/OAM Flow Match Mask, page 265 0x1E5 INGR2_PTP_DOMAIN_RANGE PTP/OAM Range Match, page 265 0x1E6 INGR2_PTP_ACTION PTP Action Control, page 266 0x1E7 INGR2_PTP_ACTION_2 PTP Action Control 2, page 267 0x1E8 INGR2_PTP_ZERO_FIELD_CTL Zero Field Control, page 267 Lower Half of PTP/OAM Flow Match Field, page 264 Ingress2 Ethernet Next Protocol Configuration Registers This section provides information about the Ethernet next protocol configuration registers. 4.36.1 Ethernet Next Protocol Short Name: INGR2_ETH1_NXT_PROTOCOL_A Address: 0x00 Table 389 • Ethernet Next Protocol Register Bit Name 2:0 INGR2_ETH1_NXT_COMPARATOR_ Points to the next comparator block after this A Ethernet block 0: Reserved 1: Ethernet comparator 2 2: IP/UDP/ACH comparator 1 3: IP/UDP/ACH comparator 2 4: MPLS comparator 5: PTP/OAM comparator 6,7: Reserved 4.36.2 Description Access Default R/W 0x0 VLAN TPID Configuration Short Name: INGR2_ETH1_VLAN_TPID_CFG_A VMDS-10509 VSC8572-02 Datasheet Revision 4.2 247 Address: 0x01 Table 390 • VLAN TPID Configuration Register Bit Name 31:16 INGR2_ETH1_VLAN_TPID_CFG_ Configurable VLAN TPID (S or B-tag). A 4.36.3 Description Access Default R/W 0x88A8 Ethernet Tag Mode Short Name: INGR2_ETH1_TAG_MODE_A Address: 0x02 Table 391 • Ethernet Tag Mode Register Bit Name 0 INGR2_ETH1_PBB_ENA_ This bit enables the presence of PBB. A The I-tag match bits are programmed in the ETH1_VLAN_TAG_RANGE registers. The mask bits are programmed in the ETH1_VLAN_TAG2 registers. A B-tag if present is configured in the ETH1_VLAN_TAG1 registers. 0: PBB not enabled 1: Always expect PBB, last tag is always an I-tag 4.36.4 Description Access Default R/W 0x0 Ethertype Match Short Name: INGR2_ETH1_ETYPE_MATCH_A Address: 0x03 Table 392 • Ethertype Match Register Bit Name 15:0 INGR2_ETH1_ETYPE_MATCH_ If the Ethertype/length field is an Ethertype, then R/W A this register is compared against the value. If the field is a length, the length value is not checked. 4.36.5 Description Access Default 0x0000 Ethernet Next Protocol Short Name: INGR2_ETH1_NXT_PROTOCOL_B Address: 0x10 Table 393 • Ethernet Next Protocol Register Bit Name Description 2:0 INGR2_ETH1_NXT_COMPARATOR Points to the next comparator block after this _B Ethernet block 0: Reserved 1: Ethernet comparator 2 2: IP/UDP/ACH comparator 1 3: IP/UDP/ACH comparator 2 4: MPLS comparator 5: PTP/OAM comparator 6,7: Reserved VMDS-10509 VSC8572-02 Datasheet Revision 4.2 Access Default R/W 0x0 248 4.36.6 VLAN TPID Configuration B Short Name: INGR2_ETH1_VLAN_TPID_CFG_B Address: 0x11 Table 394 • VLAN TPID Configuration B Register Bit Name 15:0 INGR2_ETH1_VLAN_TPID_CFG_ Configurable VLAN TPID (S or B-tag). B 4.36.7 Description Access Default R/W 0x88A8 Ethernet Tag Mode Short Name: INGR2_ETH1_TAG_MODE_B Address: 0x12 Table 395 • Ethernet Tag Mode Register Bit Name 0 INGR2_ETH1_PBB_ENA_ This bit enables the presence of PBB. R/W B The I-tag match bits are programmed in the ETH1_VLAN_TAG_RANGE registers. The mask bits are programmed in the ETH1_VLAN_TAG2 registers. A B-tag if present is configured in the ETH1_VLAN_TAG1 registers. 0: PBB not enabled 1: Always expect PBB, last tag is always an I-tag 4.36.8 Description Access Default 0x0 Ethertype Match Short Name: INGR2_ETH1_ETYPE_MATCH_B Address: 0x13 Table 396 • Ethertype Match Register Bit Name 15:0 INGR2_ETH1_ETYPE_MATCH_ If the Ethertype/length field is an Ethertype, then R/W B this register is compared against the value. If the field is a length, the length value is not checked. Description Access Default 0x0000 4.36.9 Instance offsets: 0x20 INGR2_ETH1_FLOW_CFG_0 0x30 INGR2_ETH1_FLOW_CFG_1 0x40 INGR2_ETH1_FLOW_CFG_2 0x50 INGR2_ETH1_FLOW_CFG_3 0x60 INGR2_ETH1_FLOW_CFG_4 0x70 INGR2_ETH1_FLOW_CFG_5 0x80 INGR2_ETH1_FLOW_CFG_6 0x90 INGR2_ETH1_FLOW_CFG_7 VMDS-10509 VSC8572-02 Datasheet Revision 4.2 249 4.36.10 Ethernet Flow Enable Short Name: INGR2_ETH1_FLOW_ENABLE Addresses: 0x20 INGR2_ETH1_FLOW_CFG_0 0x30 INGR2_ETH1_FLOW_CFG_1 0x40 INGR2_ETH1_FLOW_CFG_2 0x50 INGR2_ETH1_FLOW_CFG_3 0x60 INGR2_ETH1_FLOW_CFG_4 0x70 INGR2_ETH1_FLOW_CFG_5 0x80 INGR2_ETH1_FLOW_CFG_6 0x90 INGR2_ETH1_FLOW_CFG_7 Table 397 • Ethernet Flow Enable Register Bit Name Description Access Default 16 INGR2_ETH1_NXT_PROT_GRP_S Indicates which next-protocol configuration group R/W EL is valid with this flow 0: Associate this flow with next-protocol group A 1: Associate this flow with next-protocol group B 0x0 9:8 INGR2_ETH1_CHANNEL_MASK R/W 0x3 R/W 0x0 0: Flow valid for channel 0 1: Flow valid for channel 1 0 INGR2_ETH1_FLOW_ENABLE Flow enable 0: Flow is disabled 1: Flow is enabled 4.36.11 Ethernet Protocol Match Mode Short Name: INGR2_ETH1_MATCH_MODE Addresses: 0x21 INGR2_ETH1_FLOW_CFG_0 0x31 INGR2_ETH1_FLOW_CFG_1 0x41 INGR2_ETH1_FLOW_CFG_2 0x51 INGR2_ETH1_FLOW_CFG_3 0x61 INGR2_ETH1_FLOW_CFG_4 0x71 INGR2_ETH1_FLOW_CFG_5 0x81 INGR2_ETH1_FLOW_CFG_6 0x91 INGR2_ETH1_FLOW_CFG_7 Table 398 • Ethernet Protocol Match Mode Register Bit Name Description 13:12 INGR2_ETH1_VLAN_TAG_MODE Access Default R/W 0x0 0: VLAN range checking disabled 1: VLAN range checking on tag 1 2: VLAN range checking on tag 2 (not supported with PBB) 3: reserved VMDS-10509 VSC8572-02 Datasheet Revision 4.2 250 Table 398 • Ethernet Protocol Match Mode Register (continued) Bit Name Description Access Default 9 INGR2_ETH1_VLAN_TAG2_TYPE This register is only used if ETH1_VLAN_VERIFY_ENA = 1 If PBB not enabled: 0: C tag (TPID of 0x8100) 1: S tag (match to CONF_VLAN_TPID) If PBB enabled: 0,1: I tag (use range registers) R/W 0x1 8 INGR2_ETH1_VLAN_TAG1_TYPE This register is only used if ETH1_VLAN_VERIFY_ENA = 1 0: C tag (TPID of 0x8100) 1: S or B tag (match to CONF_VLAN_TPID) R/W 0x0 7:6 INGR2_ETH1_VLAN_TAGS This register is only used if R/W ETH1_VLAN_VERIFY_ENA = 1 0: No VLAN tags (not valid for PBB) 1: 1 VLAN tag (for PBB this would be the I-tag) 2: 2 VLAN tags (for PBB expect a B-tag and an Itag) 3: Reserved 0x0 4 INGR2_ETH1_VLAN_VERIFY_EN R/W A 0: Parse for VLAN tags, do not check values. For PBB the I-tag is always checked. 1: Verify configured VLAN tag configuration. 0x0 0 INGR2_ETH1_ETHERTYPE_MOD When checking for presence of SNAP/LLC R/W E based upon ETH1_MATCH_MODE, this field indicates if SNAP & 3-byte LLC is expected to be present 0: Only Ethernet type II supported, no SNAP/LLC 1: Ethernet type II & Ethernet type I with SNAP/LLC, determine if SNAP/LLC is present or not. Type I always assumes that SNAP/LLC is present 0x0 4.36.12 Ethernet Address Match Part 1 Short Name: INGR2_ETH1_ADDR_MATCH_1 Addresses: 0x22 INGR2_ETH1_FLOW_CFG_0 0x32 INGR2_ETH1_FLOW_CFG_1 0x42 INGR2_ETH1_FLOW_CFG_2 0x52 INGR2_ETH1_FLOW_CFG_3 0x62 INGR2_ETH1_FLOW_CFG_4 0x72 INGR2_ETH1_FLOW_CFG_5 0x82 INGR2_ETH1_FLOW_CFG_6 0x92 INGR2_ETH1_FLOW_CFG_7 Table 399 • Ethernet Address Match Part 1 Register Bit Name Description 31:0 INGR2_ETH1_ADDR_MATCH_ First 32 bits of the address match value 1 VMDS-10509 VSC8572-02 Datasheet Revision 4.2 Access Default R/W 0x00000000 251 4.36.13 Ethernet Address Match Part 2 Short Name: INGR2_ETH1_ADDR_MATCH_2 Addresses: 0x23 INGR2_ETH1_FLOW_CFG_0 0x33 INGR2_ETH1_FLOW_CFG_1 0x43 INGR2_ETH1_FLOW_CFG_2 0x53 INGR2_ETH1_FLOW_CFG_3 0x63 INGR2_ETH1_FLOW_CFG_4 0x73 INGR2_ETH1_FLOW_CFG_5 0x83 INGR2_ETH1_FLOW_CFG_6 0x93 INGR2_ETH1_FLOW_CFG_7 Table 400 • Ethernet Address Match Part 2 Register Bit Name Description 22:20 INGR2_ETH1_ADDR_MATCH_MOD E Selects how the addresses are matched. Multiple R/W bits can be set at once bit 0: Full 48-bit address match bit 1: Match any unicast address bit 2: Match any multicast address 17:16 INGR2_ETH1_ADDR_MATCH_SELE Selects which address to match CT 0: Match the Destination Address 1: Match the Source Address 2: Match either the Source of Destination Address 3: Reserved R/W 0x0 15:0 INGR2_ETH1_ADDR_MATCH_2 R/W 0x0000 Last 16 bits of the Ethernet address match field Access Default 0x1 4.36.14 Ethernet VLAN Tag Range Match Short Name: INGR2_ETH1_VLAN_TAG_RANGE_I_TAG Addresses: 0x24 INGR2_ETH1_FLOW_CFG_0 0x34 INGR2_ETH1_FLOW_CFG_1 0x44 INGR2_ETH1_FLOW_CFG_2 0x54 INGR2_ETH1_FLOW_CFG_3 0x64 INGR2_ETH1_FLOW_CFG_4 0x74 INGR2_ETH1_FLOW_CFG_5 0x84 INGR2_ETH1_FLOW_CFG_6 0x94 INGR2_ETH1_FLOW_CFG_7 Table 401 • Ethernet VLAN Tag Range Match Register Bit Name Description Access Default 27:16 INGR2_ETH1_VLAN_TAG_RANGE_UPP ER If PBB mode is not enabled, then this register contains the upper range of the VLAN tag range match. If PBB mode is enabled, then this register contains the upper 12 bits of the I-tag R/W VMDS-10509 VSC8572-02 Datasheet Revision 4.2 0xFFF 252 Table 401 • Ethernet VLAN Tag Range Match Register (continued) Bit Name Description Access Default 11:0 INGR2_ETH1_VLAN_TAG_RANGE_LOW If PBB mode is not enabled, then this ER register contains the lower range of the VLAN tag range match. If PBB mode is enabled, then this register contains the lower 12 bits of the I-tag R/W 0x000 4.36.15 VLAN Tag 1 Match/Mask Short Name: INGR2_ETH1_VLAN_TAG1 Addresses: 0x25 INGR2_ETH1_FLOW_CFG_0 0x35 INGR2_ETH1_FLOW_CFG_1 0x45 INGR2_ETH1_FLOW_CFG_2 0x55 INGR2_ETH1_FLOW_CFG_3 0x65 INGR2_ETH1_FLOW_CFG_4 0x75 INGR2_ETH1_FLOW_CFG_5 0x85 INGR2_ETH1_FLOW_CFG_6 0x95 INGR2_ETH1_FLOW_CFG_7 Table 402 • VLAN Tag 1 Match/Mask Register Bit Name 27:16 11:0 Description Access Default INGR2_ETH1_VLAN_TAG1_MASK Mask value for VLAN tag 1 R/W 0xFFF INGR2_ETH1_VLAN_TAG1_MATC Match value for the first VLAN tag H R/W 0x000 4.36.16 Match/Mask For VLAN Tag 2 or I-Tag Match Short Name: INGR2_ETH1_VLAN_TAG2_I_TAG Addresses: 0x26 INGR2_ETH1_FLOW_CFG_0 0x36 INGR2_ETH1_FLOW_CFG_1 0x46 INGR2_ETH1_FLOW_CFG_2 0x56 INGR2_ETH1_FLOW_CFG_3 0x66 INGR2_ETH1_FLOW_CFG_4 0x76 INGR2_ETH1_FLOW_CFG_5 0x86 INGR2_ETH1_FLOW_CFG_6 0x96 INGR2_ETH1_FLOW_CFG_7 Table 403 • Match/Mask For VLAN Tag 2 or I-Tag Match Register Bit Name Description 27:16 INGR2_ETH1_VLAN_TAG2_MASK When PBB is not enabled, the mask field for R/W VLAN tag 2 When PBB is enabled, the upper 12 bits of the Itag mask VMDS-10509 VSC8572-02 Datasheet Revision 4.2 Access Default 0xFFF 253 Table 403 • Match/Mask For VLAN Tag 2 or I-Tag Match Register (continued) Bit Name Description Access 11:0 INGR2_ETH1_VLAN_TAG2_MATC When PBB is not enabled, the match field for R/W H VLAN Tag 2 When PBB is enabled, the lower 12 bits of the Itag mask field Default 0x000 4.36.17 Ethernet Next Protocol Short Name: INGR2_ETH2_NXT_PROTOCOL_A Address: 0xA0 Table 404 • Ethernet Next Protocol Register Bit Name Description 2:0 INGR2_ETH2_NXT_COMPARATOR Points to the next comparator block after this _A Ethernet block. If this comparator block is not used, this field must be set to 0. 0: Comparator block not used 1: Ethernet comparator 2 2: IP/UDP/ACH comparator 1 3: IP/UDP/ACH comparator 2 4: MPLS comparator 5: PTP/OAM comparator 6,7: Reserved Access Default R/W 0x0 Access Default R/W 0x88A8 4.36.18 VLAN TPID Configuration Short Name: INGR2_ETH2_VLAN_TPID_CFG_A Address: 0xA1 Table 405 • VLAN TPID Configuration Register Bit Name Description 31:16 INGR2_ETH2_VLAN_TPID_CFG_ Configurable S-tag TPID A 4.36.19 Ethertype Match Short Name: INGR2_ETH2_ETYPE_MATCH_A Address: 0xA2 Table 406 • Ethertype Match Register Bit Name Description Access 15:0 INGR2_ETH2_ETYPE_MATCH_ If the Ethertype/length field is an Ethertype, then R/W A this register is compared against the value. If the field is a length, the length value is not checked. Default 0x0000 4.36.20 Instance offsets: 0xC0 INGR2_ETH2_FLOW_CFG_0 0xD0 INGR2_ETH2_FLOW_CFG_1 0xE0 INGR2_ETH2_FLOW_CFG_2 VMDS-10509 VSC8572-02 Datasheet Revision 4.2 254 0xF0 INGR2_ETH2_FLOW_CFG_3 0x100 INGR2_ETH2_FLOW_CFG_4 0x110 INGR2_ETH2_FLOW_CFG_5 0x120 INGR2_ETH2_FLOW_CFG_6 0x130 INGR2_ETH2_FLOW_CFG_7 4.36.21 Ethernet Flow Enable Short Name: INGR2_ETH2_FLOW_ENABLE Addresses: 0xC0 INGR2_ETH2_FLOW_CFG_0 0xD0 INGR2_ETH2_FLOW_CFG_1 0xE0 INGR2_ETH2_FLOW_CFG_2 0xF0 INGR2_ETH2_FLOW_CFG_3 0x100 INGR2_ETH2_FLOW_CFG_4 0x110 INGR2_ETH2_FLOW_CFG_5 0x120 INGR2_ETH2_FLOW_CFG_6 0x130 INGR2_ETH2_FLOW_CFG_7 Table 407 • Ethernet Flow Enable Register Bit Name 9:8 0 Description Access Default INGR2_ETH2_CHANNEL_MAS K bit 0: Flow valid for channel 0 bit 1: Flow valid for channel 1 R/W 0x3 INGR2_ETH2_FLOW_ENABLE Flow enable. If this comparator block is not used, all flow enable bits must be set to 0. 0: Flow is disabled 1: Flow is enabled R/W 0x0 4.36.22 Ethernet Protocol Match Mode Short Name: INGR2_ETH2_MATCH_MODE Addresses: 0xC1 INGR2_ETH2_FLOW_CFG_0 0xD1 INGR2_ETH2_FLOW_CFG_1 0xE1 INGR2_ETH2_FLOW_CFG_2 0xF1 INGR2_ETH2_FLOW_CFG_3 0x101 INGR2_ETH2_FLOW_CFG_4 0x111 INGR2_ETH2_FLOW_CFG_5 0x121 INGR2_ETH2_FLOW_CFG_6 VMDS-10509 VSC8572-02 Datasheet Revision 4.2 255 0x131 INGR2_ETH2_FLOW_CFG_7 Table 408 • Ethernet Protocol Match Mode Register Bit Name Description 13:12 INGR2_ETH2_VLAN_TAG_MODE Access Default R/W 0x0 0: VLAN range checking disabled 1: VLAN range checking on tag 1 2: VLAN range checking on tag 2 (not supported with PBB) 3: reserved 9 INGR2_ETH2_VLAN_TAG2_TYP This register is only used if E ETH1_VLAN_VERIFY_ENA = 1 0: C tag (TPID of 0x8100) 1: S tag (match to CONF_VLAN_TPID) R/W 0x1 8 INGR2_ETH2_VLAN_TAG1_TYP This register is only used if E ETH1_VLAN_VERIFY_ENA = 1 0: C tag (TPID of 0x8100) 1: S or B tag (match to CONF_VLAN_TPID) R/W 0x0 7:6 INGR2_ETH2_VLAN_TAGS R/W 0x0 4 INGR2_ETH2_VLAN_VERIFY_EN A 0: Parse for VLAN tags, do not check values. 1: Verify configured VLAN tag configuration. R/W 0x0 0 INGR2_ETH2_ETHERTYPE_MO DE When checking for presence of SNAP/LLC R/W based upon ETH1_MATCH_MODE, this field indicates if SNAP & 3-byte LLC is expected to be present 0: Only Ethernet type II supported, no SNAP/LLC 1: Ethernet type II & Ethernet type I with SNAP/LLC, determine if SNAP/LLC is present or not. Type I always assumes that SNAP/LLC is present 0x0 This register is only used if ETH2_VLAN_VERIFY_ENA = 1 0: No VLAN tags 1: 1 VLAN tag 2: 2 VLAN tags 3: Reserved 4.36.23 Ethernet Address Match Part 1 Short Name: INGR2_ETH2_ADDR_MATCH_1 Addresses: 0xC2 INGR2_ETH2_FLOW_CFG_0 0xD2 INGR2_ETH2_FLOW_CFG_1 0xE2 INGR2_ETH2_FLOW_CFG_2 0xF2 INGR2_ETH2_FLOW_CFG_3 0x102 INGR2_ETH2_FLOW_CFG_4 0x112 INGR2_ETH2_FLOW_CFG_5 0x122 INGR2_ETH2_FLOW_CFG_6 VMDS-10509 VSC8572-02 Datasheet Revision 4.2 256 0x132 INGR2_ETH2_FLOW_CFG_7 Table 409 • Ethernet Address Match Part 1 Register Bit Name Description 31:0 INGR2_ETH2_ADDR_MATCH_ First 32 bits of the address match value 1 Access Default R/W 0x00000000 4.36.24 Ethernet Address Match Part 2 Short Name: INGR2_ETH2_ADDR_MATCH_2 Addresses: 0xC3 INGR2_ETH2_FLOW_CFG_0 0xD3 INGR2_ETH2_FLOW_CFG_1 0xE3 INGR2_ETH2_FLOW_CFG_2 0xF3 INGR2_ETH2_FLOW_CFG_3 0x103 INGR2_ETH2_FLOW_CFG_4 0x113 INGR2_ETH2_FLOW_CFG_5 0x123 INGR2_ETH2_FLOW_CFG_6 0x133 INGR2_ETH2_FLOW_CFG_7 Table 410 • Ethernet Address Match Part 2 Register Bit Name Description 22:20 INGR2_ETH2_ADDR_MATCH_MODE Selects how the addresses are matched. Multiple R/W bits can be set at once bit 0: Full 48-bit address match bit 1: Match any unicast address bit 2: Match any multicast address 0x1 17:16 INGR2_ETH2_ADDR_MATCH_SELE Selects which address to match CT 0: Match the Destination Address 1: Match the Source Address 2: Match either the Source of Destination Address 3: Reserved R/W 0x0 15:0 INGR2_ETH2_ADDR_MATCH_2 R/W 0x0000 Last 16 bits of the Ethernet address match field Access Default 4.36.25 Ethernet VLAN Tag Range Match Short Name: INGR2_ETH2_VLAN_TAG_RANGE_I_TAG Addresses: 0xC4 INGR2_ETH2_FLOW_CFG_0 0xD4 INGR2_ETH2_FLOW_CFG_1 0xE4 INGR2_ETH2_FLOW_CFG_2 0xF4 INGR2_ETH2_FLOW_CFG_3 0x104 INGR2_ETH2_FLOW_CFG_4 0x114 INGR2_ETH2_FLOW_CFG_5 0x124 INGR2_ETH2_FLOW_CFG_6 VMDS-10509 VSC8572-02 Datasheet Revision 4.2 257 0x134 INGR2_ETH2_FLOW_CFG_7 Table 411 • Ethernet VLAN Tag Range Match Register Bit Name Description Access Default 27:16 INGR2_ETH2_VLAN_TAG_RANGE_UPP ER This register contains the upper range of the VLAN tag range match. R/W 0xFFF 11:0 INGR2_ETH2_VLAN_TAG_RANGE_LOW This register contains the lower range of ER the VLAN tag range match. R/W 0x000 4.36.26 VLAN Tag 1 Match/Mask Short Name: INGR2_ETH2_VLAN_TAG1 Addresses: 0xC5 INGR2_ETH2_FLOW_CFG_0 0xD5 INGR2_ETH2_FLOW_CFG_1 0xE5 INGR2_ETH2_FLOW_CFG_2 0xF5 INGR2_ETH2_FLOW_CFG_3 0x105 INGR2_ETH2_FLOW_CFG_4 0x115 INGR2_ETH2_FLOW_CFG_5 0x125 INGR2_ETH2_FLOW_CFG_6 0x135 INGR2_ETH2_FLOW_CFG_7 Table 412 • VLAN Tag 1 Match/Mask Register Bit Name Description Access Default 27:16 INGR2_ETH2_VLAN_TAG1_MASK Mask value for VLAN tag 1 R/W 0xFFF 11:0 INGR2_ETH2_VLAN_TAG1_MATCH Match value for the first VLAN tag R/W 0x000 4.36.27 Match/Mask For VLAN Tag 2 or I-Tag Match Short Name: INGR2_ETH2_VLAN_TAG2_I_TAG Addresses: 0xC6 INGR2_ETH2_FLOW_CFG_0 0xD6 INGR2_ETH2_FLOW_CFG_1 0xE6 INGR2_ETH2_FLOW_CFG_2 0xF6 INGR2_ETH2_FLOW_CFG_3 0x106 INGR2_ETH2_FLOW_CFG_4 0x116 INGR2_ETH2_FLOW_CFG_5 0x126 INGR2_ETH2_FLOW_CFG_6 0x136 INGR2_ETH2_FLOW_CFG_7 Table 413 • Match/Mask For VLAN Tag 2 or I-Tag Match Register Bit Name Description Access Default 27:16 INGR2_ETH2_VLAN_TAG2_MASK Mask field for VLAN tag 2 R/W 0xFFF 11:0 INGR2_ETH2_VLAN_TAG2_MATCH Match field for VLAN Tag 2 R/W 0x000 VMDS-10509 VSC8572-02 Datasheet Revision 4.2 258 4.37 Ingress2 MPLS Next Protocol Registers This section provides information about the MPLS next protocol registers. 4.37.1 MPLS Next Protocol Comparator Short Name: INGR2_MPLS_NXT_COMPARATOR_A Address: 0x140 Table 414 • MPLS Next Protocol Comparator Register Bit Name Description Access 16 INGR2_MPLS_CTL_WORD_A Indicates the presence of a control word after the R/W last label 0: There is no control ward after the last label 1: There is a control word after the last label 2:0 INGR2_MPLS_NXT_COMPARATOR Points to the next comparator stage. If this _A comparator block is not used, this field must be set to 0. 0: Comparator block not used 1: Ethernet comparator 2 2: IP/UDP/ACH comparator 1 3: IP/UDP/ACH comparator 2 4: Reserved 5: PTP/OAM comparator 6,7: Reserved R/W Default 0x0 0x0 4.37.2 Instance offsets: 0x160 INGR2_MPLS_FLOW_CFG_0 0x170 INGR2_MPLS_FLOW_CFG_1 0x180 INGR2_MPLS_FLOW_CFG_2 0x190 INGR2_MPLS_FLOW_CFG_3 0x1A0 INGR2_MPLS_FLOW_CFG_4 0x1B0 INGR2_MPLS_FLOW_CFG_5 0x1C0 INGR2_MPLS_FLOW_CFG_6 0x1D0 INGR2_MPLS_FLOW_CFG_7 4.37.3 MPLS Flow Control Short Name: INGR2_MPLS_FLOW_CONTROL Addresses: 0x160 INGR2_MPLS_FLOW_CFG_0 0x170 INGR2_MPLS_FLOW_CFG_1 0x180 INGR2_MPLS_FLOW_CFG_2 0x190 INGR2_MPLS_FLOW_CFG_3 0x1A0 INGR2_MPLS_FLOW_CFG_4 0x1B0 INGR2_MPLS_FLOW_CFG_5 0x1C0 INGR2_MPLS_FLOW_CFG_6 VMDS-10509 VSC8572-02 Datasheet Revision 4.2 259 0x1D0 INGR2_MPLS_FLOW_CFG_7 Table 415 • MPLS Flow Control Register Bit Name Access Default 25:24 INGR2_MPLS_CHANNEL_MA SK R/W 0x3 19:16 INGR2_MPLS_STACK_DEPTH Defines the allowable stack depths for searches. R/W The direction that the stack is referenced is determined by the setting of MPLS_REF_PNT The following table maps bits to stack depths: bit 0: stack allowed to be 1 label deep bit 1: stack allowed to be 2 labels deep bit 2: stack allowed to be 3 labels deep bit 3: stack allowed to be 4 labels deep 0x0 4 INGR2_MPLS_REF_PNT Defines the search direction for label matching R/W 0: All searching is performed starting from the top of the stack 1: All searching is performed from the end of the stack 0x0 0 INGR2_MPLS_FLOW_ENA Flow enable. If this comparator block is not used, R/W all flow enable bits must be set to 0. 0: Flow is disabled 1: Flow is enabled 0x0 4.37.4 Description bit 0: Flow valid for channel 0 bit 1: Flow valid for channel 1 MPLS Label 0 Match Range Lower Value Short Name: INGR2_MPLS_LABEL_RANGE_LOWER_0 Addresses: 0x161 INGR2_MPLS_FLOW_CFG_0 0x171 INGR2_MPLS_FLOW_CFG_1 0x181 INGR2_MPLS_FLOW_CFG_2 0x191 INGR2_MPLS_FLOW_CFG_3 0x1A1 INGR2_MPLS_FLOW_CFG_4 0x1B1 INGR2_MPLS_FLOW_CFG_5 0x1C1 INGR2_MPLS_FLOW_CFG_6 0x1D1 INGR2_MPLS_FLOW_CFG_7 Table 416 • MPLS Label 0 Match Range Lower Value Register Bit Name 19:0 INGR2_MPLS_LABEL_RANGE_LOWER Lower value for label 0 match range _0 4.37.5 Description Access Default R/W 0x00000 MPLS Label 0 Match Range Lower Value Short Name: INGR2_MPLS_LABEL_RANGE_UPPER_0 Addresses: 0x162 INGR2_MPLS_FLOW_CFG_0 0x172 INGR2_MPLS_FLOW_CFG_1 0x182 INGR2_MPLS_FLOW_CFG_2 VMDS-10509 VSC8572-02 Datasheet Revision 4.2 260 0x192 INGR2_MPLS_FLOW_CFG_3 0x1A2 INGR2_MPLS_FLOW_CFG_4 0x1B2 INGR2_MPLS_FLOW_CFG_5 0x1C2 INGR2_MPLS_FLOW_CFG_6 0x1D2 INGR2_MPLS_FLOW_CFG_7 Table 417 • MPLS Label 0 Match Range Lower Value Register Bit Name Description Access Default 19:0 INGR2_MPLS_LABEL_RANGE_UPPE R_0 Upper value for label 0 match range R/W 0xFFFFF 4.37.6 MPLS Label 1 Match Range Lower Value Short Name: INGR2_MPLS_LABEL_RANGE_LOWER_1 Addresses: 0x163 INGR2_MPLS_FLOW_CFG_0 0x173 INGR2_MPLS_FLOW_CFG_1 0x183 INGR2_MPLS_FLOW_CFG_2 0x193 INGR2_MPLS_FLOW_CFG_3 0x1A3 INGR2_MPLS_FLOW_CFG_4 0x1B3 INGR2_MPLS_FLOW_CFG_5 0x1C3 INGR2_MPLS_FLOW_CFG_6 0x1D3 INGR2_MPLS_FLOW_CFG_7 Table 418 • MPLS Label 1 Match Range Lower Value Register Bit Name 19:0 INGR2_MPLS_LABEL_RANGE_LOWER Lower value for label 1 match range _1 4.37.7 Description Access Default R/W 0x00000 MPLS Label 1 Match Range Lower Value Short Name: INGR2_MPLS_LABEL_RANGE_UPPER_1 Addresses: 0x164 INGR2_MPLS_FLOW_CFG_0 0x174 INGR2_MPLS_FLOW_CFG_1 0x184 INGR2_MPLS_FLOW_CFG_2 0x194 INGR2_MPLS_FLOW_CFG_3 0x1A4 INGR2_MPLS_FLOW_CFG_4 0x1B4 INGR2_MPLS_FLOW_CFG_5 0x1C4 INGR2_MPLS_FLOW_CFG_6 0x1D4 INGR2_MPLS_FLOW_CFG_7 Table 419 • MPLS Label 1 Match Range Lower Value Register Bit Name Description Access Default 19:0 INGR2_MPLS_LABEL_RANGE_UPPE R_1 Upper value for label 1 match range R/W 0xFFFFF VMDS-10509 VSC8572-02 Datasheet Revision 4.2 261 4.37.8 MPLS Label 2 Match Range Lower Value Short Name: INGR2_MPLS_LABEL_RANGE_LOWER_2 Addresses: 0x165 INGR2_MPLS_FLOW_CFG_0 0x175 INGR2_MPLS_FLOW_CFG_1 0x185 INGR2_MPLS_FLOW_CFG_2 0x195 INGR2_MPLS_FLOW_CFG_3 0x1A5 INGR2_MPLS_FLOW_CFG_4 0x1B5 INGR2_MPLS_FLOW_CFG_5 0x1C5 INGR2_MPLS_FLOW_CFG_6 0x1D5 INGR2_MPLS_FLOW_CFG_7 Table 420 • MPLS Label 2 Match Range Lower Value Register Bit Name 19:0 INGR2_MPLS_LABEL_RANGE_LOWER_ Lower value for label 2 match range 2 4.37.9 Description Access Default R/W 0x00000 MPLS Label 2 Match Range Lower Value Short Name: INGR2_MPLS_LABEL_RANGE_UPPER_2 Addresses: 0x166 INGR2_MPLS_FLOW_CFG_0 0x176 INGR2_MPLS_FLOW_CFG_1 0x186 INGR2_MPLS_FLOW_CFG_2 0x196 INGR2_MPLS_FLOW_CFG_3 0x1A6 INGR2_MPLS_FLOW_CFG_4 0x1B6 INGR2_MPLS_FLOW_CFG_5 0x1C6 INGR2_MPLS_FLOW_CFG_6 0x1D6 INGR2_MPLS_FLOW_CFG_7 Table 421 • MPLS Label 2 Match Range Lower Value Register Bit Name Description Access Default 19:0 INGR2_MPLS_LABEL_RANGE_UPPE R_2 Upper value for label 2 match range R/W 0xFFFFF 4.37.10 MPLS Label 3 Match Range Lower Value Short Name: INGR2_MPLS_LABEL_RANGE_LOWER_3 Addresses: 0x167 INGR2_MPLS_FLOW_CFG_0 0x177 INGR2_MPLS_FLOW_CFG_1 0x187 INGR2_MPLS_FLOW_CFG_2 0x197 INGR2_MPLS_FLOW_CFG_3 0x1A7 INGR2_MPLS_FLOW_CFG_4 0x1B7 INGR2_MPLS_FLOW_CFG_5 0x1C7 INGR2_MPLS_FLOW_CFG_6 VMDS-10509 VSC8572-02 Datasheet Revision 4.2 262 0x1D7 INGR2_MPLS_FLOW_CFG_7 Table 422 • MPLS Label 3 Match Range Lower Value Register Bit Name Description 19:0 INGR2_MPLS_LABEL_RANGE_LOWER Lower value for label 3 match range _3 Access Default R/W 0x00000 4.37.11 MPLS Label 3 Match Range Lower Value Short Name: INGR2_MPLS_LABEL_RANGE_UPPER_3 Addresses: 0x168 INGR2_MPLS_FLOW_CFG_0 0x178 INGR2_MPLS_FLOW_CFG_1 0x188 INGR2_MPLS_FLOW_CFG_2 0x198 INGR2_MPLS_FLOW_CFG_3 0x1A8 INGR2_MPLS_FLOW_CFG_4 0x1B8 INGR2_MPLS_FLOW_CFG_5 0x1C8 INGR2_MPLS_FLOW_CFG_6 0x1D8 INGR2_MPLS_FLOW_CFG_7 Table 423 • MPLS Label 3 Match Range Lower Value Register Bit Name Description Access Default 19:0 INGR2_MPLS_LABEL_RANGE_UPPE R_3 Upper value for label 3 match range R/W 0xFFFFF 4.37.12 Instance offsets: 0x1E0 INGR2_PTP_FLOW_0 0x1F0 INGR2_PTP_FLOW_1 0x200 INGR2_PTP_FLOW_2 0x210 INGR2_PTP_FLOW_3 0x220 INGR2_PTP_FLOW_4 0x230 INGR2_PTP_FLOW_5 4.37.13 PTP/OAM Flow Enable Short Name: INGR2_PTP_FLOW_ENA Addresses: 0x1E0 INGR2_PTP_FLOW_0 0x1F0 INGR2_PTP_FLOW_1 0x200 INGR2_PTP_FLOW_2 0x210 INGR2_PTP_FLOW_3 0x220 INGR2_PTP_FLOW_4 VMDS-10509 VSC8572-02 Datasheet Revision 4.2 263 0x230 INGR2_PTP_FLOW_5 Table 424 • PTP/OAM Flow Enable Register Bit Name Description Access Default 17:16 INGR2_PTP_NXT_PROT_GRP_MA Indicates which next protocol groups that this R/W SK flow is valid for. For each next protocol group, if the bit is 1, then this flow is valid for that group. If it is 0, then it is not valid for the group. 0: Mask bit for next protocol group A 1: Mask bit for next protocol group B 0x3 5:4 INGR2_PTP_CHANNEL_MASK R/W 0x3 R/W 0x0 0: Flow valid for channel 0 1: Flow valid for channel 1 0 INGR2_PTP_FLOW_ENA 4.37.14 Upper Half of PTP/OAM Flow Match Field Short Name: INGR2_PTP_FLOW_MATCH_UPPER Addresses: 0x1E1 INGR2_PTP_FLOW_0 0x1F1 INGR2_PTP_FLOW_1 0x201 INGR2_PTP_FLOW_2 0x211 INGR2_PTP_FLOW_3 0x221 INGR2_PTP_FLOW_4 0x231 INGR2_PTP_FLOW_5 Table 425 • Upper Half of PTP/OAM Flow Match Field Register Bit Name Description 31:0 INGR2_PTP_FLOW_MATCH_UPP ER Access Default R/W 0x00000000 4.37.15 Lower Half of PTP/OAM Flow Match Field Short Name: INGR2_PTP_FLOW_MATCH_LOWER Addresses: 0x1E2 INGR2_PTP_FLOW_0 0x1F2 INGR2_PTP_FLOW_1 0x202 INGR2_PTP_FLOW_2 0x212 INGR2_PTP_FLOW_3 0x222 INGR2_PTP_FLOW_4 0x232 INGR2_PTP_FLOW_5 Table 426 • Lower Half of PTP/OAM Flow Match Field Register Bit Name Description 31:0 INGR2_PTP_FLOW_MATCH_LOW ER VMDS-10509 VSC8572-02 Datasheet Revision 4.2 Access Default R/W 0x00000000 264 4.37.16 Upper Half of PTP/OAM Flow Match Mask Short Name: INGR2_PTP_FLOW_MASK_UPPER Addresses: 0x1E3 INGR2_PTP_FLOW_0 0x1F3 INGR2_PTP_FLOW_1 0x203 INGR2_PTP_FLOW_2 0x213 INGR2_PTP_FLOW_3 0x223 INGR2_PTP_FLOW_4 0x233 INGR2_PTP_FLOW_5 Table 427 • Upper Half of PTP/OAM Flow Match Mask Register Bit Name Description 31:0 INGR2_PTP_FLOW_MASK_UPPE R Access Default R/W 0x00000000 4.37.17 Lower Half of PTP/OAM Flow Match Mask Short Name: INGR2_PTP_FLOW_MASK_LOWER Addresses: 0x1E4 INGR2_PTP_FLOW_0 0x1F4 INGR2_PTP_FLOW_1 0x204 INGR2_PTP_FLOW_2 0x214 INGR2_PTP_FLOW_3 0x224 INGR2_PTP_FLOW_4 0x234 INGR2_PTP_FLOW_5 Table 428 • Lower Half of PTP/OAM Flow Match Mask Register Bit Name Description 31:0 INGR2_PTP_FLOW_MASK_LOWE R Access Default R/W 0x00000000 4.37.18 PTP/OAM Range Match Short Name: INGR2_PTP_DOMAIN_RANGE Addresses: 0x1E5 INGR2_PTP_FLOW_0 0x1F5 INGR2_PTP_FLOW_1 0x205 INGR2_PTP_FLOW_2 0x215 INGR2_PTP_FLOW_3 0x225 INGR2_PTP_FLOW_4 0x235 INGR2_PTP_FLOW_5 Table 429 • PTP/OAM Range Match Register Bit Name Description 28:24 INGR2_PTP_DOMAIN_RANGE_OFFSE T VMDS-10509 VSC8572-02 Datasheet Revision 4.2 Access Default R/W 0x00 265 Table 429 • PTP/OAM Range Match Register (continued) Bit Name 23:16 Description Access Default INGR2_PTP_DOMAIN_RANGE_UPPE R R/W 0xFF 15:8 INGR2_PTP_DOMAIN_RANGE_LOWE R R/W 0x00 0 INGR2_PTP_DOMAIN_RANGE_ENA R/W 0x0 4.37.19 PTP Action Control Short Name: INGR2_PTP_ACTION Addresses: 0x1E6 INGR2_PTP_FLOW_0 0x1F6 INGR2_PTP_FLOW_1 0x206 INGR2_PTP_FLOW_2 0x216 INGR2_PTP_FLOW_3 0x226 INGR2_PTP_FLOW_4 0x236 INGR2_PTP_FLOW_5 Table 430 • PTP Action Control Register Bit Name Description Access Default 28 INGR2_PTP_MOD_FRAME_STAT_U PDATE 1: Tell the Rewriter to update the value of the Modified Frame Status bit 0: Do not update the bit R/W 0x0 26:24 INGR2_PTP_MOD_FRAME_BYTE_O Indicates the position relative to the start of the FFSET PTP frame in bytes where the Modified_Frame_Status bit resides R/W 0x0 21 INGR2_PTP_SUB_DELAY_ASYM_E NA R/W 0x0 R/W 0x0 1: Signal the Timestamp block to subtract the asymmetry delay 0: Do not signal the Timestamp block to subtract the asymmetry delay 20 INGR2_PTP_ADD_DELAY_ASYM_E NA 1: Signal the Timestamp block to add the asymmetry delay 0: Do not signal the Timestamp block to add the asymmetry delay 15:10 INGR2_PTP_TIME_STRG_FIELD_O FFSET 9:5 INGR2_PTP_CORR_FIELD_OFFSET Points to the location of the correction field for updating the timestamp. Location is relative to the first byte of the PTP/OAM header. Note: If this flow is being used to match OAM frames, set this register to 4 R/W 0x00 4 INGR2_PTP_SAVE_LOCAL_TIME R/W 0x0 Points to the reserved 32-bit field where the Rx R/W timestamp is saved. The location is relative to the first byte of the PTP/OAM header. 0x00 1: Save the local time to the Timestamp FIFO 0: Do not save the time to the Timestamp FIFO VMDS-10509 VSC8572-02 Datasheet Revision 4.2 266 Table 430 • PTP Action Control Register (continued) Bit Name Description 3:0 INGR2_PTP_COMMAND Access Default R/W 0x0 0: NoP 1: SUB 2: SUB_P2P 3: ADD 4: SUB_ADD 5: WRITE_1588 6: WRITE_P2P (deprecated) 7: WRITE_NS 8: WRITE_NS_P2P 4.37.20 PTP Action Control 2 Short Name: INGR2_PTP_ACTION_2 Addresses: 0x1E7 INGR2_PTP_FLOW_0 0x1F7 INGR2_PTP_FLOW_1 0x207 INGR2_PTP_FLOW_2 0x217 INGR2_PTP_FLOW_3 0x227 INGR2_PTP_FLOW_4 0x237 INGR2_PTP_FLOW_5 Table 431 • PTP Action Control 2 Register Bit Name Description Access Default 23:16 INGR2_PTP_NEW_CF_LOC Location of the new correction field relative to the R/W PTP header start. Only even values are allowed. 15:8 INGR2_PTP_REWRITE_OFFSE Byte offset relative to the start of the PTP frame T where the ingress timestamp value can be stored. R/W 0x00 3:0 INGR2_PTP_REWRITE_BYTES Number of bytes in the PTP or OAM frame that must be modified by the Rewriter for the timestamp R/W 0x0 0x00 4.37.21 Zero Field Control Short Name: INGR2_PTP_ZERO_FIELD_CTL Addresses: 0x1E8 INGR2_PTP_FLOW_0 0x1F8 INGR2_PTP_FLOW_1 0x208 INGR2_PTP_FLOW_2 0x218 INGR2_PTP_FLOW_3 0x228 INGR2_PTP_FLOW_4 VMDS-10509 VSC8572-02 Datasheet Revision 4.2 267 0x238 INGR2_PTP_FLOW_5 Table 432 • Zero Field Control Register Bit Name Description 13:8 INGR2_PTP_ZERO_FIELD_OFFSET Points to a location in the PTP/OAM frame R/W relative to the start of the PTP header that will be zeroed if this function is enabled 3:0 INGR2_PTP_ZERO_FIELD_BYTE_CN The number of bytes to be zeroed. If this field is R/W T 0, then this function is not enabled. 4.38 Access Default 0x00 0x0 Egress2 Analyzer Engine Configuration Registers This section lists the overviews for the analyzer engine configuration egress2 registers. Note: The analyzer engine configuration registers are not initialized to the default values during chip reset. Software must configure these registers to their default value. Note: For more information about accessing the 1588 IP registers, see Accessing 1588 IP Registers, page 72. Table 433 • EGR2_ETH1_NXT_PROTOCOL_A Address Name Details 0x00 EGR2_ETH1_NXT_PROTOCOL_A Ethernet Next Protocol, page 270 0x01 EGR2_ETH1_VLAN_TPID_CFG_A VLAN TPID Configuration, page 271 0x02 EGR2_ETH1_TAG_MODE_A Ethernet Tag Mode, page 271 0x03 EGR2_ETH1_ETYPE_MATCH_A Ethertype Match, page 271 Table 434 • EGR2_ETH1_NXT_PROTOCOL_B Address Name Details 0x10 EGR2_ETH1_NXT_PROTOCOL_ Ethernet Next Protocol, page 272 B 0x11 EGR2_ETH1_VLAN_TPID_CFG_ VLAN TPID Configuration, page 272 B 0x12 EGR2_ETH1_TAG_MODE_B Ethernet Tag Mode, page 272 0x13 EGR2_ETH1_ETYPE_MATCH_B Ethertype Match, page 272 Table 435 • EGR2_ETH1_FLOW_CFG (8 instances) Address Name Details 0x20 EGR2_ETH1_FLOW_ENABLE Ethernet Flow Enable, page 273 0x21 EGR2_ETH1_MATCH_MODE Ethernet Protocol Match Mode, page 273 0x22 EGR2_ETH1_ADDR_MATCH_1 Ethernet Address Match Part 1, page 275 0x23 EGR2_ETH1_ADDR_MATCH_2 Ethernet Address Match Part 2, page 275 0x24 EGR2_ETH1_VLAN_TAG_RANGE Ethernet VLAN Tag Range Match, page 275 _I_TAG VMDS-10509 VSC8572-02 Datasheet Revision 4.2 268 Table 435 • EGR2_ETH1_FLOW_CFG (8 instances) (continued) Address Name Details 0x25 EGR2_ETH1_VLAN_TAG1 VLAN Tag 1 Match/Mask, page 276 0x26 EGR2_ETH1_VLAN_TAG2_I_TAG Match/Mask For VLAN Tag 2 or I-Tag Match, page 276 Table 436 • EGR2_ETH2_NXT_PROTOCOL_A Address Name Details 0xA0 EGR2_ETH2_NXT_PROTOCOL_A Ethernet Next Protocol, page 277 0xA1 EGR2_ETH2_VLAN_TPID_CFG_A VLAN TPID Configuration, page 277 0xA2 EGR2_ETH2_ETYPE_MATCH_A Ethertype Match, page 277 Table 437 • EGR2_ETH2_FLOW_CFG (8 instances) Address Name Details 0xC0 EGR2_ETH2_FLOW_ENABLE Ethernet Flow Enable, page 278 0xC1 EGR2_ETH2_MATCH_MODE Ethernet Protocol Match Mode, page 278 0xC2 EGR2_ETH2_ADDR_MATCH_1 Ethernet Address Match Part 1, page 279 0xC3 EGR2_ETH2_ADDR_MATCH_2 Ethernet Address Match Part 2, page 280 0xC4 EGR2_ETH2_VLAN_TAG_RANGE_I_T Ethernet VLAN Tag Range Match, page 280 AG 0xC5 EGR2_ETH2_VLAN_TAG1 VLAN Tag 1 Match/Mask, page 281 0xC6 EGR2_ETH2_VLAN_TAG2_I_TAG Match/Mask For VLAN Tag 2 or I-Tag Match, page 281 Table 438 • EGR2_MPLS_NXT_COMPARATOR_A Address Name Details 0x140 EGR2_MPLS_NXT_COMPARATOR MPLS Next Protocol Comparator, page 282 _A Table 439 • EGR2_MPLS_FLOW_CFG (8 instances) Address Name Details 0x160 EGR2_MPLS_FLOW_CONTROL MPLS Flow Control, page 282 0x161 EGR2_MPLS_LABEL_RANGE_LOWER MPLS Label 0 Match Range Lower Value, _0 page 283 0x162 EGR2_MPLS_LABEL_RANGE_UPPER_ MPLS Label 0 Match Range Lower Value, 0 page 283 0x163 EGR2_MPLS_LABEL_RANGE_LOWER MPLS Label 1 Match Range Lower Value, _1 page 284 VMDS-10509 VSC8572-02 Datasheet Revision 4.2 269 Table 439 • EGR2_MPLS_FLOW_CFG (8 instances) (continued) Address Name Details 0x164 EGR2_MPLS_LABEL_RANGE_UPPER_ MPLS Label 1 Match Range Lower Value, 1 page 284 0x165 EGR2_MPLS_LABEL_RANGE_LOWER MPLS Label 2 Match Range Lower Value, _2 page 285 0x166 EGR2_MPLS_LABEL_RANGE_UPPER_ MPLS Label 2 Match Range Lower Value, 2 page 285 0x167 EGR2_MPLS_LABEL_RANGE_LOWER MPLS Label 3 Match Range Lower Value, _3 page 285 0x168 EGR2_MPLS_LABEL_RANGE_UPPER_ MPLS Label 3 Match Range Lower Value, 3 page 286 Table 440 • EGR2_PTP_FLOW (6 instances) 4.39 Address Register Name Details 0x1E0 EGR2_PTP_FLOW_ENA PTP/OAM Flow Enable, page 286 0x1E1 EGR2_PTP_FLOW_MATCH_UPPE Upper Half of PTP/OAM Flow Match Field, R page 287 0x1E2 EGR2_PTP_FLOW_MATCH_LOW Lower Half of PTP/OAM Flow Match Field, ER page 287 0x1E3 EGR2_PTP_FLOW_MASK_UPPE R 0x1E4 EGR2_PTP_FLOW_MASK_LOWE Lower Half of PTP/OAM Flow Match Mask, R page 288 0x1E5 EGR2_PTP_DOMAIN_RANGE PTP/OAM Range Match, page 288 0x1E6 EGR2_PTP_ACTION PTP Action Control, page 289 0x1E7 EGR2_PTP_ACTION_2 PTP Action Control 2, page 290 0x1E8 EGR2_PTP_ZERO_FIELD_CTL Zero Field Control, page 290 Upper Half of PTP/OAM Flow Match Mask, page 288 Egress2 Ethernet Next Protocol Configuration Registers This section provides information about the Ethernet next protocol configuration registers. 4.39.1 Ethernet Next Protocol Short Name: EGR2_ETH1_NXT_PROTOCOL_A VMDS-10509 VSC8572-02 Datasheet Revision 4.2 270 Address: 0x00 Table 441 • Ethernet Next Protocol Register Bit Name 2:0 EGR2_ETH1_NXT_COMPARATOR Points to the next comparator block after this _A Ethernet block 0: Reserved 1: Ethernet comparator 2 2: IP/UDP/ACH comparator 1 3: IP/UDP/ACH comparator 2 4: MPLS comparator 5: PTP/OAM comparator 6,7: Reserved 4.39.2 Description Access Default R/W 0x0 Access Default R/W 0x88A8 VLAN TPID Configuration Short Name: EGR2_ETH1_VLAN_TPID_CFG_A Address: 0x01 Table 442 • VLAN TPID Configuration Register Bit Name 31:16 EGR2_ETH1_VLAN_TPID_CFG_ Configurable VLAN TPID (S or B-tag). A 4.39.3 Description Ethernet Tag Mode Short Name: EGR2_ETH1_TAG_MODE_A Address: 0x02 Table 443 • Ethernet Tag Mode Register Bit Name Description 0 EGR2_ETH1_PBB_ENA_ A This bit enables the presence of PBB. R/W The I-tag match bits are programmed in the ETH1_VLAN_TAG_RANGE registers. The mask bits are programmed in the ETH1_VLAN_TAG2 registers. A B-tag if present is configured in the ETH1_VLAN_TAG1 registers. 0: PBB not enabled 1: Always expect PBB, last tag is always an I-tag 4.39.4 Access Default 0x0 Ethertype Match Short Name: EGR2_ETH1_ETYPE_MATCH_A Address: 0x03 Table 444 • Ethertype Match Register Bit Name Description 15:0 EGR2_ETH1_ETYPE_MATCH If the Ethertype/length field is an Ethertype, then R/W _A this register is compared against the value. If the field is a length, the length value is not checked. VMDS-10509 VSC8572-02 Datasheet Revision 4.2 Access Default 0x0000 271 4.39.5 Ethernet Next Protocol Short Name: EGR2_ETH1_NXT_PROTOCOL_B Address: 0x10 Table 445 • Ethernet Next Protocol Register Bit Name 2:0 EGR2_ETH1_NXT_COMPARATOR Points to the next comparator block after this _B Ethernet block 0: Reserved 1: Ethernet comparator 2 2: IP/UDP/ACH comparator 1 3: IP/UDP/ACH comparator 2 4: MPLS comparator 5: PTP/OAM comparator 6,7: Reserved 4.39.6 Description Access Default R/W 0x0 VLAN TPID Configuration Short Name: EGR2_ETH1_VLAN_TPID_CFG_B Address: 0x11 Table 446 • VLAN TPID Configuration Register Bit Name 15:0 EGR2_ETH1_VLAN_TPID_CFG_ Configurable VLAN TPID (S or B-tag). B 4.39.7 Description Access Default R/W 0x88A8 Access Default Ethernet Tag Mode Short Name: EGR2_ETH1_TAG_MODE_B Address: 0x12 Table 447 • Ethernet Tag Mode Register Bit Name Description 0 EGR2_ETH1_PBB_ENA_ B This bit enables the presence of PBB. R/W The I-tag match bits are programmed in the ETH1_VLAN_TAG_RANGE registers. The mask bits are programmed in the ETH1_VLAN_TAG2 registers. A B-tag if present is configured in the ETH1_VLAN_TAG1 registers. 0: PBB not enabled 1: Always expect PBB, last tag is always an I-tag 4.39.8 0x0 Ethertype Match Short Name: EGR2_ETH1_ETYPE_MATCH_B VMDS-10509 VSC8572-02 Datasheet Revision 4.2 272 Address: 0x13 Table 448 • Ethertype Match Register Bit Name Description Access 15:0 EGR2_ETH1_ETYPE_MATCH_B If the Ethertype/length field is an Ethertype, then R/W this register is compared against the value. If the field is a length, the length value is not checked. Default 0x0000 4.39.9 Instance offsets: 0x20 EGR2_ETH1_FLOW_CFG_0 0x30 EGR2_ETH1_FLOW_CFG_1 0x40 EGR2_ETH1_FLOW_CFG_2 0x50 EGR2_ETH1_FLOW_CFG_3 0x60 EGR2_ETH1_FLOW_CFG_4 0x70 EGR2_ETH1_FLOW_CFG_5 0x80 EGR2_ETH1_FLOW_CFG_6 0x90 EGR2_ETH1_FLOW_CFG_7 4.39.10 Ethernet Flow Enable Short Name: EGR2_ETH1_FLOW_ENABLE Addresses: 0x20 EGR2_ETH1_FLOW_CFG_0 0x30 EGR2_ETH1_FLOW_CFG_1 0x40 EGR2_ETH1_FLOW_CFG_2 0x50 EGR2_ETH1_FLOW_CFG_3 0x60 EGR2_ETH1_FLOW_CFG_4 0x70 EGR2_ETH1_FLOW_CFG_5 0x80 EGR2_ETH1_FLOW_CFG_6 0x90 EGR2_ETH1_FLOW_CFG_7 Table 449 • Ethernet Flow Enable Register Bit Name Description Access Default 16 EGR2_ETH1_NXT_PROT_GRP_S Indicates which next-protocol configuration group is R/W EL valid with this flow 0: Associate this flow with next-protocol group A 1: Associate this flow with next-protocol group B 0x0 9:8 EGR2_ETH1_CHANNEL_MASK R/W 0x3 R/W 0x0 0: Flow valid for channel 0 1: Flow valid for channel 1 0 EGR2_ETH1_FLOW_ENABLE Flow enable 0: Flow is disabled 1: Flow is enabled 4.39.11 Ethernet Protocol Match Mode Short Name: EGR2_ETH1_MATCH_MODE VMDS-10509 VSC8572-02 Datasheet Revision 4.2 273 Addresses: 0x21 EGR2_ETH1_FLOW_CFG_0 0x31 EGR2_ETH1_FLOW_CFG_1 0x41 EGR2_ETH1_FLOW_CFG_2 0x51 EGR2_ETH1_FLOW_CFG_3 0x61 EGR2_ETH1_FLOW_CFG_4 0x71 EGR2_ETH1_FLOW_CFG_5 0x81 EGR2_ETH1_FLOW_CFG_6 0x91 EGR2_ETH1_FLOW_CFG_7 Table 450 • Ethernet Protocol Match Mode Register Bit Name Description 13:12 EGR2_ETH1_VLAN_TAG_MODE Access Default R/W 0x0 0: VLAN range checking disabled 1: VLAN range checking on tag 1 2: VLAN range checking on tag 2 (not supported with PBB) 3: reserved 9 EGR2_ETH1_VLAN_TAG2_TYPE This register is only used if ETH1_VLAN_VERIFY_ENA = 1 If PBB not enabled: 0: C tag (TPID of 0x8100) 1: S tag (match to CONF_VLAN_TPID) If PBB enabled: 0,1: I tag (use range registers) R/W 0x1 8 EGR2_ETH1_VLAN_TAG1_TYPE This register is only used if ETH1_VLAN_VERIFY_ENA = 1 0: C tag (TPID of 0x8100) 1: S or B tag (match to CONF_VLAN_TPID) R/W 0x0 7:6 EGR2_ETH1_VLAN_TAGS This register is only used if R/W ETH1_VLAN_VERIFY_ENA = 1 0: No VLAN tags (not valid for PBB) 1: 1 VLAN tag (for PBB this would be the I-tag) 2: 2 VLAN tags (for PBB expect a B-tag and an Itag) 3: Reserved 0x0 4 EGR2_ETH1_VLAN_VERIFY_ENA R/W 0x0 EGR2_ETH1_ETHERTYPE_MODE When checking for presence of SNAP/LLC R/W based upon ETH1_MATCH_MODE, this field indicates if SNAP & 3-byte LLC is expected to be present 0: Only Ethernet type II supported, no SNAP/LLC 1: Ethernet type II & Ethernet type I with SNAP/LLC, determine if SNAP/LLC is present or not. Type I always assumes that SNAP/LLC is present 0x0 0: Parse for VLAN tags, do not check values. For PBB the I-tag is always checked. 1: Verify configured VLAN tag configuration. 0 VMDS-10509 VSC8572-02 Datasheet Revision 4.2 274 4.39.12 Ethernet Address Match Part 1 Short Name: EGR2_ETH1_ADDR_MATCH_1 Addresses: 0x22 EGR2_ETH1_FLOW_CFG_0 0x32 EGR2_ETH1_FLOW_CFG_1 0x42 EGR2_ETH1_FLOW_CFG_2 0x52 EGR2_ETH1_FLOW_CFG_3 0x62 EGR2_ETH1_FLOW_CFG_4 0x72 EGR2_ETH1_FLOW_CFG_5 0x82 EGR2_ETH1_FLOW_CFG_6 0x92 EGR2_ETH1_FLOW_CFG_7 Table 451 • Ethernet Address Match Part 1 Register Bit Name Description 31:0 EGR2_ETH1_ADDR_MATCH First 32 bits of the address match value _1 Access Default R/W 0x00000000 4.39.13 Ethernet Address Match Part 2 Short Name: EGR2_ETH1_ADDR_MATCH_2 Addresses: 0x23 EGR2_ETH1_FLOW_CFG_0 0x33 EGR2_ETH1_FLOW_CFG_1 0x43 EGR2_ETH1_FLOW_CFG_2 0x53 EGR2_ETH1_FLOW_CFG_3 0x63 EGR2_ETH1_FLOW_CFG_4 0x73 EGR2_ETH1_FLOW_CFG_5 0x83 EGR2_ETH1_FLOW_CFG_6 0x93 EGR2_ETH1_FLOW_CFG_7 Table 452 • Ethernet Address Match Part 2 Register Bit Name Description 22:20 EGR2_ETH1_ADDR_MATCH_MOD Selects how the addresses are matched. Multiple R/W E bits can be set at once bit 0: Full 48-bit address match bit 1: Match any unicast address bit 2: Match any multicast address 0x1 17:16 EGR2_ETH1_ADDR_MATCH_SELE Selects which address to match CT 0: Match the Destination Address 1: Match the Source Address 2: Match either the Source of Destination Address 3: Reserved R/W 0x0 15:0 EGR2_ETH1_ADDR_MATCH_2 R/W 0x0000 Last 16 bits of the Ethernet address match field Access Default 4.39.14 Ethernet VLAN Tag Range Match Short Name: EGR2_ETH1_VLAN_TAG_RANGE_I_TAG VMDS-10509 VSC8572-02 Datasheet Revision 4.2 275 Addresses: 0x24 EGR2_ETH1_FLOW_CFG_0 0x34 EGR2_ETH1_FLOW_CFG_1 0x44 EGR2_ETH1_FLOW_CFG_2 0x54 EGR2_ETH1_FLOW_CFG_3 0x64 EGR2_ETH1_FLOW_CFG_4 0x74 EGR2_ETH1_FLOW_CFG_5 0x84 EGR2_ETH1_FLOW_CFG_6 0x94 EGR2_ETH1_FLOW_CFG_7 Table 453 • Ethernet VLAN Tag Range Match Register Bit Name Description Access Default 27:16 EGR2_ETH1_VLAN_TAG_RANGE_UPP If PBB mode is not enabled, then this ER register contains the upper range of the VLAN tag range match. If PBB mode is enabled, then this register contains the upper 12 bits of the I-tag R/W 0xFFF 11:0 EGR2_ETH1_VLAN_TAG_RANGE_LOW If PBB mode is not enabled, then this ER register contains the lower range of the VLAN tag range match. If PBB mode is enabled, then this register contains the lower 12 bits of the I-tag R/W 0x000 Access Default 4.39.15 VLAN Tag 1 Match/Mask Short Name: EGR2_ETH1_VLAN_TAG1 Addresses: 0x25 EGR2_ETH1_FLOW_CFG_0 0x35 EGR2_ETH1_FLOW_CFG_1 0x45 EGR2_ETH1_FLOW_CFG_2 0x55 EGR2_ETH1_FLOW_CFG_3 0x65 EGR2_ETH1_FLOW_CFG_4 0x75 EGR2_ETH1_FLOW_CFG_5 0x85 EGR2_ETH1_FLOW_CFG_6 0x95 EGR2_ETH1_FLOW_CFG_7 Table 454 • VLAN Tag 1 Match/Mask Register Bit Name Description 27:16 EGR2_ETH1_VLAN_TAG1_MASK Mask value for VLAN tag 1 R/W 0xFFF 11:0 EGR2_ETH1_VLAN_TAG1_MATC Match value for the first VLAN tag H R/W 0x000 4.39.16 Match/Mask For VLAN Tag 2 or I-Tag Match Short Name: EGR2_ETH1_VLAN_TAG2_I_TAG Addresses: 0x26 EGR2_ETH1_FLOW_CFG_0 0x36 EGR2_ETH1_FLOW_CFG_1 VMDS-10509 VSC8572-02 Datasheet Revision 4.2 276 0x46 EGR2_ETH1_FLOW_CFG_2 0x56 EGR2_ETH1_FLOW_CFG_3 0x66 EGR2_ETH1_FLOW_CFG_4 0x76 EGR2_ETH1_FLOW_CFG_5 0x86 EGR2_ETH1_FLOW_CFG_6 0x96 EGR2_ETH1_FLOW_CFG_7 Table 455 • Match/Mask For VLAN Tag 2 or I-Tag Match Register Bit Name Description Access Default 27:16 EGR2_ETH1_VLAN_TAG2_MAS K When PBB is not enabled, the mask field for R/W VLAN tag 2 When PBB is enabled, the upper 12 bits of the Itag mask 0xFFF 11:0 EGR2_ETH1_VLAN_TAG2_MAT CH When PBB is not enabled, the match field for R/W VLAN Tag 2 When PBB is enabled, the lower 12 bits of the Itag mask field 0x000 4.39.17 Ethernet Next Protocol Short Name: EGR2_ETH2_NXT_PROTOCOL_A Address: 0xA0 Table 456 • Ethernet Next Protocol Register Bit Name Description 2:0 EGR2_ETH2_NXT_COMPARATOR Points to the next comparator block after this _A Ethernet block. If this comparator block is not used, this field must be set to 0. 0: Comparator block not used 1: Ethernet comparator 2 2: IP/UDP/ACH comparator 1 3: IP/UDP/ACH comparator 2 4: MPLS comparator 5: PTP/OAM comparator 6,7: Reserved Access Default R/W 0x0 4.39.18 VLAN TPID Configuration Short Name: EGR2_ETH2_VLAN_TPID_CFG_A Address: 0xA1 Table 457 • VLAN TPID Configuration Register Bit Name Description Access Default 31:16 EGR2_ETH2_VLAN_TPID_CFG_A Configurable S-tag TPID R/W 0x88A8 4.39.19 Ethertype Match Short Name: EGR2_ETH2_ETYPE_MATCH_A VMDS-10509 VSC8572-02 Datasheet Revision 4.2 277 Address: 0xA2 Table 458 • Ethertype Match Register Bit Name Description Access 15:0 EGR2_ETH2_ETYPE_MATCH_ If the Ethertype/length field is an Ethertype, then R/W A this register is compared against the value. If the field is a length, the length value is not checked. Default 0x0000 4.39.20 Instance offsets: 0xC0 EGR2_ETH2_FLOW_CFG_0 0xD0 EGR2_ETH2_FLOW_CFG_1 0xE0 EGR2_ETH2_FLOW_CFG_2 0xF0 EGR2_ETH2_FLOW_CFG_3 0x100 EGR2_ETH2_FLOW_CFG_4 0x110 EGR2_ETH2_FLOW_CFG_5 0x120 EGR2_ETH2_FLOW_CFG_6 0x130 EGR2_ETH2_FLOW_CFG_7 4.39.21 Ethernet Flow Enable Short Name: EGR2_ETH2_FLOW_ENABLE Addresses: 0xC0 EGR2_ETH2_FLOW_CFG_0 0xD0 EGR2_ETH2_FLOW_CFG_1 0xE0 EGR2_ETH2_FLOW_CFG_2 0xF0 EGR2_ETH2_FLOW_CFG_3 0x100 EGR2_ETH2_FLOW_CFG_4 0x110 EGR2_ETH2_FLOW_CFG_5 0x120 EGR2_ETH2_FLOW_CFG_6 0x130 EGR2_ETH2_FLOW_CFG_7 Table 459 • Ethernet Flow Enable Register Bit Name Description 9:8 EGR2_ETH2_CHANNEL_MASK Access Default R/W 0x3 Flow enable. If this comparator block is not used, R/W all flow enable bits must be set to 0. 0: Flow is disabled 1: Flow is enabled 0x0 bit 0: Flow valid for channel 0 bit 1: Flow valid for channel 1 0 EGR2_ETH2_FLOW_ENABLE 4.39.22 Ethernet Protocol Match Mode Short Name: EGR2_ETH2_MATCH_MODE Addresses: 0xC1 EGR2_ETH2_FLOW_CFG_0 0xD1 EGR2_ETH2_FLOW_CFG_1 VMDS-10509 VSC8572-02 Datasheet Revision 4.2 278 0xE1 EGR2_ETH2_FLOW_CFG_2 0xF1 EGR2_ETH2_FLOW_CFG_3 0x101 EGR2_ETH2_FLOW_CFG_4 0x111 EGR2_ETH2_FLOW_CFG_5 0x121 EGR2_ETH2_FLOW_CFG_6 0x131 EGR2_ETH2_FLOW_CFG_7 Table 460 • Ethernet Protocol Match Mode Register Bit Name Description 13:12 EGR2_ETH2_VLAN_TAG_MODE Access Default R/W 0x0 0: VLAN range checking disabled 1: VLAN range checking on tag 1 2: VLAN range checking on tag 2 (not supported with PBB) 3: reserved 9 EGR2_ETH2_VLAN_TAG2_TYPE This register is only used if ETH1_VLAN_VERIFY_ENA = 1 0: C tag (TPID of 0x8100) 1: S tag (match to CONF_VLAN_TPID) R/W 0x1 8 EGR2_ETH2_VLAN_TAG1_TYPE This register is only used if ETH1_VLAN_VERIFY_ENA = 1 0: C tag (TPID of 0x8100) 1: S or B tag (match to CONF_VLAN_TPID) R/W 0x0 7:6 EGR2_ETH2_VLAN_TAGS R/W 0x0 4 EGR2_ETH2_VLAN_VERIFY_EN A 0: Parse for VLAN tags, do not check values. 1: Verify configured VLAN tag configuration. R/W 0x0 0 EGR2_ETH2_ETHERTYPE_MOD When checking for presence of SNAP/LLC R/W E based upon ETH1_MATCH_MODE, this field indicates if SNAP & 3-byte LLC is expected to be present 0: Only Ethernet type II supported, no SNAP/LLC 1: Ethernet type II & Ethernet type I with SNAP/LLC, determine if SNAP/LLC is present or not. Type I always assumes that SNAP/LLC is present 0x0 This register is only used if ETH2_VLAN_VERIFY_ENA = 1 0: No VLAN tags 1: 1 VLAN tag 2: 2 VLAN tags 3: Reserved 4.39.23 Ethernet Address Match Part 1 Short Name: EGR2_ETH2_ADDR_MATCH_1 Addresses: 0xC2 EGR2_ETH2_FLOW_CFG_0 0xD2 EGR2_ETH2_FLOW_CFG_1 0xE2 EGR2_ETH2_FLOW_CFG_2 0xF2 EGR2_ETH2_FLOW_CFG_3 0x102 EGR2_ETH2_FLOW_CFG_4 VMDS-10509 VSC8572-02 Datasheet Revision 4.2 279 0x112 EGR2_ETH2_FLOW_CFG_5 0x122 EGR2_ETH2_FLOW_CFG_6 0x132 EGR2_ETH2_FLOW_CFG_7 Table 461 • Ethernet Address Match Part 1 Register Bit Name Description 31:0 EGR2_ETH2_ADDR_MATCH_1 First 32 bits of the address match value Access Default R/W 0x00000000 4.39.24 Ethernet Address Match Part 2 Short Name: EGR2_ETH2_ADDR_MATCH_2 Addresses: 0xC3 EGR2_ETH2_FLOW_CFG_0 0xD3 EGR2_ETH2_FLOW_CFG_1 0xE3 EGR2_ETH2_FLOW_CFG_2 0xF3 EGR2_ETH2_FLOW_CFG_3 0x103 EGR2_ETH2_FLOW_CFG_4 0x113 EGR2_ETH2_FLOW_CFG_5 0x123 EGR2_ETH2_FLOW_CFG_6 0x133 EGR2_ETH2_FLOW_CFG_7 Table 462 • Ethernet Address Match Part 2 Register Bit Name Description 22:20 EGR2_ETH2_ADDR_MATCH_MOD E Selects how the addresses are matched. Multiple R/W bits can be set at once bit 0: Full 48-bit address match bit 1: Match any unicast address bit 2: Match any multicast address 17:16 EGR2_ETH2_ADDR_MATCH_SELE Selects which address to match CT 0: Match the Destination Address 1: Match the Source Address 2: Match either the Source of Destination Address 3: Reserved R/W 0x0 15:0 EGR2_ETH2_ADDR_MATCH_2 R/W 0x0000 Last 16 bits of the Ethernet address match field Access Default 0x1 4.39.25 Ethernet VLAN Tag Range Match Short Name: EGR2_ETH2_VLAN_TAG_RANGE_I_TAG Addresses: 0xC4 EGR2_ETH2_FLOW_CFG_0 0xD4 EGR2_ETH2_FLOW_CFG_1 0xE4 EGR2_ETH2_FLOW_CFG_2 0xF4 EGR2_ETH2_FLOW_CFG_3 0x104 EGR2_ETH2_FLOW_CFG_4 0x114 EGR2_ETH2_FLOW_CFG_5 0x124 EGR2_ETH2_FLOW_CFG_6 VMDS-10509 VSC8572-02 Datasheet Revision 4.2 280 0x134 EGR2_ETH2_FLOW_CFG_7 Table 463 • Ethernet VLAN Tag Range Match Register Bit Name Description Access Default 27:16 EGR2_ETH2_VLAN_TAG_RANGE_UPP This register contains the upper range of R/W ER the VLAN tag range match. 0xFFF 11:0 EGR2_ETH2_VLAN_TAG_RANGE_LOW This register contains the lower range of R/W ER the VLAN tag range match. 0x000 4.39.26 VLAN Tag 1 Match/Mask Short Name: EGR2_ETH2_VLAN_TAG1 Addresses: 0xC5 EGR2_ETH2_FLOW_CFG_0 0xD5 EGR2_ETH2_FLOW_CFG_1 0xE5 EGR2_ETH2_FLOW_CFG_2 0xF5 EGR2_ETH2_FLOW_CFG_3 0x105 EGR2_ETH2_FLOW_CFG_4 0x115 EGR2_ETH2_FLOW_CFG_5 0x125 EGR2_ETH2_FLOW_CFG_6 0x135 EGR2_ETH2_FLOW_CFG_7 Table 464 • VLAN Tag 1 Match/Mask Register Bit Name 27:16 11:0 Description Access Default EGR2_ETH2_VLAN_TAG1_MASK Mask value for VLAN tag 1 R/W 0xFFF EGR2_ETH2_VLAN_TAG1_MATC Match value for the first VLAN tag H R/W 0x000 4.39.27 Match/Mask For VLAN Tag 2 or I-Tag Match Short Name: EGR2_ETH2_VLAN_TAG2_I_TAG Addresses: 0xC6 EGR2_ETH2_FLOW_CFG_0 0xD6 EGR2_ETH2_FLOW_CFG_1 0xE6 EGR2_ETH2_FLOW_CFG_2 0xF6 EGR2_ETH2_FLOW_CFG_3 0x106 EGR2_ETH2_FLOW_CFG_4 0x116 EGR2_ETH2_FLOW_CFG_5 0x126 EGR2_ETH2_FLOW_CFG_6 0x136 EGR2_ETH2_FLOW_CFG_7 Table 465 • Match/Mask For VLAN Tag 2 or I-Tag Match Register Bit Name Description Access Default 27:16 EGR2_ETH2_VLAN_TAG2_MASK Mask field for VLAN tag 2 R/W 0xFFF 11:0 EGR2_ETH2_VLAN_TAG2_MATCH Match field for VLAN Tag 2 R/W 0x000 VMDS-10509 VSC8572-02 Datasheet Revision 4.2 281 4.40 Egress2 MPLS Next Protocol Registers This section provides information about the MPLS next protocol registers. 4.40.1 MPLS Next Protocol Comparator Short Name: EGR2_MPLS_NXT_COMPARATOR_A Address: 0x140 Table 466 • MPLS Next Protocol Comparator Register Bit Name Description Access 16 EGR2_MPLS_CTL_WORD_A Indicates the presence of a control word after the R/W last label 0: There is no control ward after the last label 1: There is a control word after the last label 2:0 EGR2_MPLS_NXT_COMPARATOR Points to the next comparator stage. If this _A comparator block is not used, this field must be set to 0. 0: Comparator block not used 1: Ethernet comparator 2 2: IP/UDP/ACH comparator 1 3: IP/UDP/ACH comparator 2 4: Reserved 5: PTP/OAM comparator 6,7: Reserved R/W Default 0x0 0x0 4.40.2 Instance offsets: 0x160 EGR2_MPLS_FLOW_CFG_0 0x170 EGR2_MPLS_FLOW_CFG_1 0x180 EGR2_MPLS_FLOW_CFG_2 0x190 EGR2_MPLS_FLOW_CFG_3 0x1A0 EGR2_MPLS_FLOW_CFG_4 0x1B0 EGR2_MPLS_FLOW_CFG_5 0x1C0 EGR2_MPLS_FLOW_CFG_6 0x1D0 EGR2_MPLS_FLOW_CFG_7 4.40.3 MPLS Flow Control Short Name: EGR2_MPLS_FLOW_CONTROL Addresses: 0x160 EGR2_MPLS_FLOW_CFG_0 0x170 EGR2_MPLS_FLOW_CFG_1 0x180 EGR2_MPLS_FLOW_CFG_2 0x190 EGR2_MPLS_FLOW_CFG_3 0x1A0 EGR2_MPLS_FLOW_CFG_4 0x1B0 EGR2_MPLS_FLOW_CFG_5 0x1C0 EGR2_MPLS_FLOW_CFG_6 VMDS-10509 VSC8572-02 Datasheet Revision 4.2 282 0x1D0 EGR2_MPLS_FLOW_CFG_7 Table 467 • MPLS Flow Control Register Bit Name Description 25:24 EGR2_MPLS_CHANNEL_MAS K Access Default R/W 0x3 0: Flow valid for channel 0 1: Flow valid for channel 1 19:16 EGR2_MPLS_STACK_DEPTH Defines the allowable stack depths for searches. R/W The direction that the stack is referenced is determined by the setting of MPLS_REF_PNT The following table maps bits to stack depths: 0: stack allowed to be 1 label deep 1: stack allowed to be 2 labels deep 2: stack allowed to be 3 labels deep 3: stack allowed to be 4 labels deep 0x0 4 EGR2_MPLS_REF_PNT Defines the search direction for label matching R/W 0: All searching is performed starting from the top of the stack 1: All searching is performed from the end of the stack 0x0 0 EGR2_MPLS_FLOW_ENA Flow enable. If this comparator block is not used, R/W all flow enable bits must be set to 0. 0: Flow is disabled 1: Flow is enabled 0x0 4.40.4 MPLS Label 0 Match Range Lower Value Short Name: EGR2_MPLS_LABEL_RANGE_LOWER_0 Addresses: 0x161 EGR2_MPLS_FLOW_CFG_0 0x171 EGR2_MPLS_FLOW_CFG_1 0x181 EGR2_MPLS_FLOW_CFG_2 0x191 EGR2_MPLS_FLOW_CFG_3 0x1A1 EGR2_MPLS_FLOW_CFG_4 0x1B1 EGR2_MPLS_FLOW_CFG_5 0x1C1 EGR2_MPLS_FLOW_CFG_6 0x1D1 EGR2_MPLS_FLOW_CFG_7 Table 468 • MPLS Label 0 Match Range Lower Value Register Bit Name 19:0 EGR2_MPLS_LABEL_RANGE_LOWER Lower value for label 0 match range _0 4.40.5 Description Access Default R/W 0x00000 MPLS Label 0 Match Range Lower Value Short Name: EGR2_MPLS_LABEL_RANGE_UPPER_0 Addresses: 0x162 EGR2_MPLS_FLOW_CFG_0 0x172 EGR2_MPLS_FLOW_CFG_1 0x182 EGR2_MPLS_FLOW_CFG_2 VMDS-10509 VSC8572-02 Datasheet Revision 4.2 283 0x192 EGR2_MPLS_FLOW_CFG_3 0x1A2 EGR2_MPLS_FLOW_CFG_4 0x1B2 EGR2_MPLS_FLOW_CFG_5 0x1C2 EGR2_MPLS_FLOW_CFG_6 0x1D2 EGR2_MPLS_FLOW_CFG_7 Table 469 • MPLS Label 0 Match Range Lower Value Register Bit Name 19:0 EGR2_MPLS_LABEL_RANGE_UPPER Upper value for label 0 match range _0 4.40.6 Description Access Default R/W 0xFFFFF Access Default R/W 0x00000 Access Default R/W 0xFFFFF MPLS Label 1 Match Range Lower Value Short Name: EGR2_MPLS_LABEL_RANGE_LOWER_1 Addresses: 0x163 EGR2_MPLS_FLOW_CFG_0 0x173 EGR2_MPLS_FLOW_CFG_1 0x183 EGR2_MPLS_FLOW_CFG_2 0x193 EGR2_MPLS_FLOW_CFG_3 0x1A3 EGR2_MPLS_FLOW_CFG_4 0x1B3 EGR2_MPLS_FLOW_CFG_5 0x1C3 EGR2_MPLS_FLOW_CFG_6 0x1D3 EGR2_MPLS_FLOW_CFG_7 Table 470 • MPLS Label 1 Match Range Lower Value Register Bit Name 19:0 EGR2_MPLS_LABEL_RANGE_LOWER Lower value for label 1 match range _1 4.40.7 Description MPLS Label 1 Match Range Lower Value Short Name: EGR2_MPLS_LABEL_RANGE_UPPER_1 Addresses: 0x164 EGR2_MPLS_FLOW_CFG_0 0x174 EGR2_MPLS_FLOW_CFG_1 0x184 EGR2_MPLS_FLOW_CFG_2 0x194 EGR2_MPLS_FLOW_CFG_3 0x1A4 EGR2_MPLS_FLOW_CFG_4 0x1B4 EGR2_MPLS_FLOW_CFG_5 0x1C4 EGR2_MPLS_FLOW_CFG_6 0x1D4 EGR2_MPLS_FLOW_CFG_7 Table 471 • MPLS Label 1 Match Range Lower Value Register Bit Name Description 19:0 EGR2_MPLS_LABEL_RANGE_UPPER Upper value for label 1 match range _1 VMDS-10509 VSC8572-02 Datasheet Revision 4.2 284 4.40.8 MPLS Label 2 Match Range Lower Value Short Name: EGR2_MPLS_LABEL_RANGE_LOWER_2 Addresses: 0x165 EGR2_MPLS_FLOW_CFG_0 0x175 EGR2_MPLS_FLOW_CFG_1 0x185 EGR2_MPLS_FLOW_CFG_2 0x195 EGR2_MPLS_FLOW_CFG_3 0x1A5 EGR2_MPLS_FLOW_CFG_4 0x1B5 EGR2_MPLS_FLOW_CFG_5 0x1C5 EGR2_MPLS_FLOW_CFG_6 0x1D5 EGR2_MPLS_FLOW_CFG_7 Table 472 • MPLS Label 2 Match Range Lower Value Register Bit Name 19:0 EGR2_MPLS_LABEL_RANGE_LOWER Lower value for label 2 match range _2 4.40.9 Description Access Default R/W 0x00000 MPLS Label 2 Match Range Lower Value Short Name: EGR2_MPLS_LABEL_RANGE_UPPER_2 Addresses: 0x166 EGR2_MPLS_FLOW_CFG_0 0x176 EGR2_MPLS_FLOW_CFG_1 0x186 EGR2_MPLS_FLOW_CFG_2 0x196 EGR2_MPLS_FLOW_CFG_3 0x1A6 EGR2_MPLS_FLOW_CFG_4 0x1B6 EGR2_MPLS_FLOW_CFG_5 0x1C6 EGR2_MPLS_FLOW_CFG_6 0x1D6 EGR2_MPLS_FLOW_CFG_7 Table 473 • MPLS Label 2 Match Range Lower Value Register Bit Name Description 19:0 EGR2_MPLS_LABEL_RANGE_UPPER Upper value for label 2 match range _2 Access Default R/W 0xFFFFF 4.40.10 MPLS Label 3 Match Range Lower Value Short Name: EGR2_MPLS_LABEL_RANGE_LOWER_3 Addresses: 0x167 EGR2_MPLS_FLOW_CFG_0 0x177 EGR2_MPLS_FLOW_CFG_1 0x187 EGR2_MPLS_FLOW_CFG_2 0x197 EGR2_MPLS_FLOW_CFG_3 0x1A7 EGR2_MPLS_FLOW_CFG_4 0x1B7 EGR2_MPLS_FLOW_CFG_5 0x1C7 EGR2_MPLS_FLOW_CFG_6 VMDS-10509 VSC8572-02 Datasheet Revision 4.2 285 0x1D7 EGR2_MPLS_FLOW_CFG_7 Table 474 • MPLS Label 3 Match Range Lower Value Register Bit Name Description 19:0 EGR2_MPLS_LABEL_RANGE_LOWER Lower value for label 3 match range _3 Access Default R/W 0x00000 Access Default R/W 0xFFFFF 4.40.11 MPLS Label 3 Match Range Lower Value Short Name: EGR2_MPLS_LABEL_RANGE_UPPER_3 Addresses: 0x168 EGR2_MPLS_FLOW_CFG_0 0x178 EGR2_MPLS_FLOW_CFG_1 0x188 EGR2_MPLS_FLOW_CFG_2 0x198 EGR2_MPLS_FLOW_CFG_3 0x1A8 EGR2_MPLS_FLOW_CFG_4 0x1B8 EGR2_MPLS_FLOW_CFG_5 0x1C8 EGR2_MPLS_FLOW_CFG_6 0x1D8 EGR2_MPLS_FLOW_CFG_7 Table 475 • MPLS Label 3 Match Range Lower Value Register Bit Name Description 19:0 EGR2_MPLS_LABEL_RANGE_UPPER Upper value for label 3 match range _3 4.40.12 Instance offsets: 0x1E0 EGR2_PTP_FLOW_0 0x1F0 EGR2_PTP_FLOW_1 0x200 EGR2_PTP_FLOW_2 0x210 EGR2_PTP_FLOW_3 0x220 EGR2_PTP_FLOW_4 0x230 EGR2_PTP_FLOW_5 4.40.13 PTP/OAM Flow Enable Short Name: EGR2_PTP_FLOW_ENA Addresses: 0x1E0 EGR2_PTP_FLOW_0 0x1F0 EGR2_PTP_FLOW_1 0x200 EGR2_PTP_FLOW_2 0x210 EGR2_PTP_FLOW_3 0x220 EGR2_PTP_FLOW_4 VMDS-10509 VSC8572-02 Datasheet Revision 4.2 286 0x230 EGR2_PTP_FLOW_5 Table 476 • PTP/OAM Flow Enable Register Bit Name Description Access Default 17:16 EGR2_PTP_NXT_PROT_GRP_MA SK Indicates which next protocol groups that this R/W flow is valid for. For each next protocol group, if the bit is 1, then this flow is valid for that group. If it is 0, then it is not valid for the group. bit 0: Mask bit for next protocol group A bit 1: Mask bit for next protocol group B 0x3 5:4 EGR2_PTP_CHANNEL_MASK R/W 0x3 R/W 0x0 bit 0: Flow valid for channel 0 bit 1: Flow valid for channel 1 0 EGR2_PTP_FLOW_ENA 4.40.14 Upper Half of PTP/OAM Flow Match Field Short Name: EGR2_PTP_FLOW_MATCH_UPPER Addresses: 0x1E1 EGR2_PTP_FLOW_0 0x1F1 EGR2_PTP_FLOW_1 0x201 EGR2_PTP_FLOW_2 0x211 EGR2_PTP_FLOW_3 0x221 EGR2_PTP_FLOW_4 0x231 EGR2_PTP_FLOW_5 Table 477 • Upper Half of PTP/OAM Flow Match Field Register Bit Name Description 31:0 EGR2_PTP_FLOW_MATCH_UPP ER Access Default R/W 0x00000000 Access Default R/W 0x00000000 4.40.15 Lower Half of PTP/OAM Flow Match Field Short Name: EGR2_PTP_FLOW_MATCH_LOWER Addresses: 0x1E2 EGR2_PTP_FLOW_0 0x1F2 EGR2_PTP_FLOW_1 0x202 EGR2_PTP_FLOW_2 0x212 EGR2_PTP_FLOW_3 0x222 EGR2_PTP_FLOW_4 0x232 EGR2_PTP_FLOW_5 Table 478 • Lower Half of PTP/OAM Flow Match Field Register Bit Name Description 31:0 EGR2_PTP_FLOW_MATCH_LOWE R VMDS-10509 VSC8572-02 Datasheet Revision 4.2 287 4.40.16 Upper Half of PTP/OAM Flow Match Mask Short Name: EGR2_PTP_FLOW_MASK_UPPER Addresses: 0x1E3 EGR2_PTP_FLOW_0 0x1F3 EGR2_PTP_FLOW_1 0x203 EGR2_PTP_FLOW_2 0x213 EGR2_PTP_FLOW_3 0x223 EGR2_PTP_FLOW_4 0x233 EGR2_PTP_FLOW_5 Table 479 • Upper Half of PTP/OAM Flow Match Mask Register Bit Name Description 31:0 EGR2_PTP_FLOW_MASK_UPPE R Access Default R/W 0x00000000 Access Default R/W 0x00000000 Access Default R/W 0x00 4.40.17 Lower Half of PTP/OAM Flow Match Mask Short Name: EGR2_PTP_FLOW_MASK_LOWER Addresses: 0x1E4 EGR2_PTP_FLOW_0 0x1F4 EGR2_PTP_FLOW_1 0x204 EGR2_PTP_FLOW_2 0x214 EGR2_PTP_FLOW_3 0x224 EGR2_PTP_FLOW_4 0x234 EGR2_PTP_FLOW_5 Table 480 • Lower Half of PTP/OAM Flow Match Mask Register Bit Name Description 31:0 EGR2_PTP_FLOW_MASK_LOW ER 4.40.18 PTP/OAM Range Match Short Name: EGR2_PTP_DOMAIN_RANGE Addresses: 0x1E5 EGR2_PTP_FLOW_0 0x1F5 EGR2_PTP_FLOW_1 0x205 EGR2_PTP_FLOW_2 0x215 EGR2_PTP_FLOW_3 0x225 EGR2_PTP_FLOW_4 0x235 EGR2_PTP_FLOW_5 Table 481 • PTP/OAM Range Match Register Bit Name Description 28:24 EGR2_PTP_DOMAIN_RANGE_OFFSE T VMDS-10509 VSC8572-02 Datasheet Revision 4.2 288 Table 481 • PTP/OAM Range Match Register (continued) Bit Name 23:16 Description Access Default EGR2_PTP_DOMAIN_RANGE_UPPER R/W 0xFF 15:8 EGR2_PTP_DOMAIN_RANGE_LOWE R R/W 0x00 0 EGR2_PTP_DOMAIN_RANGE_ENA R/W 0x0 4.40.19 PTP Action Control Short Name: EGR2_PTP_ACTION Addresses: 0x1E6 EGR2_PTP_FLOW_0 0x1F6 EGR2_PTP_FLOW_1 0x206 EGR2_PTP_FLOW_2 0x216 EGR2_PTP_FLOW_3 0x226 EGR2_PTP_FLOW_4 0x236 EGR2_PTP_FLOW_5 Table 482 • PTP Action Control Register Bit Name Description 28 EGR2_PTP_MOD_FRAME_STAT_U PDATE Access Default R/W 0x0 1: Tell the Rewriter to update the value of the Modified Frame Status bit 0: Do not update the bit 26:24 EGR2_PTP_MOD_FRAME_BYTE_O Indicates the position relative to the start of the FFSET PTP frame in bytes where the Modified_Frame_Status bit resides R/W 0x0 21 EGR2_PTP_SUB_DELAY_ASYM_EN R/W A 1: Signal the Timestamp block to subtract the asymmetry delay 0: Do not signal the Timestamp block to subtract the asymmetry delay 0x0 20 EGR2_PTP_ADD_DELAY_ASYM_E NA 0x0 R/W 1: Signal the Timestamp block to add the asymmetry delay 0: Do not signal the Timestamp block to add the asymmetry delay 15:10 EGR2_PTP_TIME_STRG_FIELD_OF Points to the reserved 32-bit field where the Rx R/W FSET timestamp is saved. The location is relative to the first byte of the PTP/OAM header. 0x00 9:5 EGR2_PTP_CORR_FIELD_OFFSET Points to the location of the correction field for updating the timestamp. Location is relative to the first byte of the PTP/OAM header. Note: If this flow is being used to match OAM frames, set this register to 4 R/W 0x00 4 EGR2_PTP_SAVE_LOCAL_TIME R/W 0x0 1: Save the local time to the Timestamp FIFO 0: Do not save the time to the Timestamp FIFO VMDS-10509 VSC8572-02 Datasheet Revision 4.2 289 Table 482 • PTP Action Control Register (continued) Bit Name Description 3:0 EGR2_PTP_COMMAND Access Default R/W 0x0 0: NoP 1: SUB 2: SUB_P2P 3: ADD 4: SUB_ADD 5: WRITE_1588 6: WRITE_P2P (deprecated) 7: WRITE_NS 8: WRITE_NS_P2P 4.40.20 PTP Action Control 2 Short Name: EGR2_PTP_ACTION_2 Addresses: 0x1E7 EGR2_PTP_FLOW_0 0x1F7 EGR2_PTP_FLOW_1 0x207 EGR2_PTP_FLOW_2 0x217 EGR2_PTP_FLOW_3 0x227 EGR2_PTP_FLOW_4 0x237 EGR2_PTP_FLOW_5 Table 483 • PTP Action Control 2 Register Bit Name Description Access 23:16 EGR2_PTP_NEW_CF_LOC Location of the new correction field relative to the R/W PTP header start. Only even values are allowed. 0x00 15:8 EGR2_PTP_REWRITE_OFFSE Byte offset relative to the start of the PTP frame R/W T where the ingress timestamp value can be read. 0x00 3:0 EGR2_PTP_REWRITE_BYTES Number of bytes in the PTP or OAM frame that must be modified by the Rewriter for the timestamp 0x0 R/W Default 4.40.21 Zero Field Control Short Name: EGR2_PTP_ZERO_FIELD_CTL Addresses: 0x1E8 EGR2_PTP_FLOW_0 0x1F8 EGR2_PTP_FLOW_1 0x208 EGR2_PTP_FLOW_2 0x218 EGR2_PTP_FLOW_3 0x228 EGR2_PTP_FLOW_4 VMDS-10509 VSC8572-02 Datasheet Revision 4.2 290 0x238 EGR2_PTP_FLOW_5 Table 484 • Zero Field Control Register Bit Name Description 13:8 EGR2_PTP_ZERO_FIELD_OFFSET Points to a location in the PTP/OAM frame relative to the start of the PTP header that will be zeroed if this function is enabled 3:0 EGR2_PTP_ZERO_FIELD_BYTE_C NT Access Default R/W 0x00 The number of bytes to be zeroed. If this field R/W is 0, then this function is not enabled. VMDS-10509 VSC8572-02 Datasheet Revision 4.2 0x0 291 Electrical Specifications 5 Electrical Specifications This section provides the DC characteristics, AC characteristics, recommended operating conditions, and stress ratings for the VSC8572-02 device. 5.1 DC Characteristics This section contains the DC specifications for the VSC8572-02 device. 5.1.1 VDD25 The following table shows the DC specifications for the pins referenced to VDD25. The specifications listed in the following table are valid only when VDD1 = 1.0 V, VDD1A = 1.0 V, or VDD25A = 2.5 V. Table 485 • VDD25 DC Characteristics Parameter Symbol Minimum Output high voltage VOH 2.0 Output low voltage VOL Input high voltage VIH Input low voltage Unit Condition V IOH = –1.0 mA 0.4 V IOL = 1.0 mA 1.85 3.3 V VIL –0.3 0.7 V Input leakage current IILEAK –32 32 µA Internal resistor included Output leakage current IOLEAK –32 32 µA Internal resistor included 6 mA Output low current drive IOL strength Output high current drive IOH strength 5.1.2 Maximum –6 mA LED and GPIO The following table shows the DC specifications for the LED and GPIO pins. Table 486 • LED and GPIO Characteristics 5.1.3 Pin Symbol LED IOH LED IOL GPIO IOH GPIO IOL Minimum Maximum Unit 24 mA –24 mA 12 mA –12 mA Internal Pull-Up or Pull-Down Resistors Internal pull-up or pull-down resistors are specified in the following table. For more information about signals with internal pull-up or pull-down resistors, see Pins by Function, page 316. All internal pull-up resistors are connected to their respective I/O supply. Table 487 • Internal Pull-Up or Pull-Down Resistors Parameter Symbol Minimum Typical Maximum Unit Internal pull-up resistor, GPIO RPU_GPIO 33 53 90 kΩ VMDS-10509 VSC8572-02 Datasheet Revision 4.2 292 Electrical Specifications Table 487 • Internal Pull-Up or Pull-Down Resistors (continued) Parameter Symbol Minimum Typical Maximum Unit Internal pull-up resistor, all others RPU 96 120 144 kΩ Internal pull-down resistor RPD 96 120 144 kΩ 5.1.4 Reference Clock The following table shows the DC specifications for a differential reference clock input signal Table 488 • Reference Clock DC Characteristics Parameter Symbol Minimum Input voltage range VIP,VIN Input differential peak-to-peak voltage |VID| Input common-mode voltage VICM Differential input impedance RI 1. 2. 5.1.5 Typical Maximum Unit –25 1260 mV 1501 1200 mV 0 12002 mV Ω 100 To meet jitter specifications, the minimum |VID| must be 400 mV. When using a single-ended clock input, the REFCLK_P low voltage must be less than VDDA – 200 mV, and the high voltage level must be greater than VDDA + 200 mV The maximum common-mode voltage is provided without a differential signal. The common-mode voltage is only limited by the maximum and minimum input voltage range and by the differential amplitude of the input signal. 1588 Reference Clock The following table shows the DC specifications for a differential 1588 reference clock input signal. Table 489 • 1588 Reference Clock DC Characteristics Parameter Symbol Minimum Input voltage range VIP,VIN Input differential peak-to-peak voltage Maximum Unit –25 1260 mV |VID| 150 1200 mV Input common-mode voltage VICM 0 12001 mV Differential input impedance RI 1. 5.1.6 Typical Ω 100 The maximum common-mode voltage is provided without a differential signal. The common-mode voltage is only limited by the maximum and minimum input voltage range and by the differential amplitude of the input signal. SerDes Interface (SGMII) The SerDes output drivers are designed to operate in SGMII/LVDS mode. The SGMII/LVDS mode meets or exceeds the DC requirements of Serial-GMII Specification Revision 1.9 (ENG-46158), unless otherwise noted. The following table lists the DC specifications for the SGMII driver. The values are valid for all configurations, unless stated otherwise. Table 490 • SerDes Driver DC Specifications Parameter Symbol Output high voltage, VOA or VOB VOH Output low voltage, VOA or VOB VOL Minimum 0 Maximum Unit Condition 1050 mV RL = 100 Ω ±1% mV RL = 100 Ω ±1% VMDS-10509 VSC8572-02 Datasheet Revision 4.2 293 Electrical Specifications Table 490 • SerDes Driver DC Specifications (continued) Parameter Symbol Minimum Maximum Unit Condition Output differential peak voltage |VOD| 350 450 mV VDD_VS = 1.0 V RL = 100 Ω ±1% Output differential peak voltage, fiber media 1000BASE-X |VOD| 350 450 mV VDD_VS = 1.0 V RL = 100 Ω ±1% Output offset voltage(1) VOS 420 580 mV VDD_VS = 1.0 V RL = 100 Ω ±1% DC output impedance, single-ended, SGMII mode RO 40 140 Ω VC = 1.0 V See Figure 81, page 295 RO mismatch between A and B, SGMII mode(2) ΔRO 10 % VC = 1.0 V See Figure 81, page 295 25 mV RL = 100 Ω ±1% RL = 100 Ω ±1% Change in |VOD| between 0 and 1, Δ|VOD| SGMII mode Change in VOS between 0 and 1, SGMII mode ΔVOS 25 mV Output current, driver shorted to GND, SGMII mode |IOSA|, |IOSB| 40 mA Output current, drivers shorted together, SGMII mode |IOSAB| 12 mA 1. Requires AC-coupling for SGMII compliance. 2. Matching of reflection coefficients. For more information about test methods, see IEEE Std 1596.3-1996. Figure 79 • SGMII DC Transmit Test Circuit VOA 100 Ω ± 1% VOD = VOA – VOB VOS = ½ (VOA + VOB) VOB Figure 80 • SGMII DC Definitions VOA VOB GND VOD 0 V differential |VOD| |VOD| 0 V differential VOS GND VOS Δ|VOD| = | |VOAH – VOBL| – |VOBH – VOAL| | VMDS-10509 VSC8572-02 Datasheet Revision 4.2 294 Electrical Specifications ΔVOS = | ½(VOAH + VOBL) – ½(VOAL + VOBH) | Figure 81 • SGMII DC Driver Output Impedance Test Circuit VOA 50 Ω ± 0.1% +V – c 0 and 1 VOB 50 Ω ± 0.1% The following table lists the DC specifications for the SGMII receivers. Table 491 • SerDes Receiver DC Specifications Parameter Symbol Minimum Maximum Unit Input voltage range, VIA or VIB VI –25 1250 mV Input differential peak-to-peak voltage |VID| 100 1000 mV Input common-mode voltage(1) VICM 0 VDD_A(2) mV Receiver differential input impedance RI 80 120 Ω Input differential hysteresis, SGMII mode VHYST 25 1. 2. Condition Without any differential signal mV SGMII compliancy requires external AC-coupling. When interfacing with specific Microsemi devices, DCcoupling is possible. For more information, contact your local Microsemi sales representative. The common-mode voltage is only limited by the maximum and minimum input voltage range and the input signal’s differential amplitude. Figure 82 • SGMII DC Input Definitions VIA VID = VIA – VIB VIC = ½ (VIA + VIB) VIB 5.1.7 Enhanced SerDes Interface (QSGMII) All DC specifications for the enhanced SerDes interface are compliant with QSGMII Specification Revision 1.3 and meet or exceed the requirements in the standard. They are also compliant with OIFCEI-02.0 requirements where applicable. The enhanced SerDes interface supports the following operating modes: SGMII, QSGMII, and SFP. The values in the following table apply to the modes specified in the condition column. The following table shows the DC specifications for the enhanced SerDes driver. Table 492 • Enhanced SerDes Driver DC Specifications Parameter Symbol Minimum Maximum Unit Condition Output differential peak voltage, SFP and QSGMII modes |VODp| 250 400 mV VDD_VS = 1.0 V RL = 100 Ω ±1% maximum drive VMDS-10509 VSC8572-02 Datasheet Revision 4.2 295 Electrical Specifications Table 492 • Enhanced SerDes Driver DC Specifications (continued) Parameter Symbol Minimum Maximum Unit Condition Output differential peak voltage, SGMII mode(1) |VODp| 150 400 mV VDD_VS = 1.0 V RL = 100 Ω ±1% DC output impedance, single-ended, SGMII mode RO 40 140 Ω VC = 1.0 V See Figure 81, page 295 RO mismatch between A and B, SGMII mode(2) ΔRO 10 % VC = 1.0 V See Figure 81, page 295 25 mV RL = 100 Ω ±1% RL = 100 Ω ±1% Change in |VOD| between 0 and 1, Δ|VOD| SGMII mode Change in VOS between 0 and 1, SGMII mode ΔVOS 25 mV Output current, drivers shorted to ground, SGMII and QSGMII modes |IOSA|, |IOSB| 40 mA Output current, drivers shorted together, SGMII and QSGMII modes |IOSAB| 12 mA 1. Voltage is adjustable in 64 steps. 2. Matching of reflection coefficients. For more information about test methods, see IEEE Std 1596.3-1996. The following table lists the DC specifications for the enhanced SerDes receiver. Table 493 • Enhanced SerDes Receiver DC Specifications Parameter Symbol Minimum Maximum Unit VI –0.25 1.2 V Input differential peak-to-peak voltage |VID| 100 1600 mV Input common-mode voltage VICM 0 1200 mV Receiver differential input impedance RI 80 120 Ω Input voltage range, VIA or 1. 5.1.8 VIB(1) Typical 100 QSGMII DC input sensitivity is less than 400 mV. Current Consumption The following tables show the current consumption values for each mode. Add significant margin above the values for sizing power supplies. Table 494 • Current Consumption Mode Typical Maximum Unit Condition 1V Digital 1V 2.5 V Analog Digital 2.5 V 1V Analog Digital 1V 2.5 V Analog Digital 2.5 V Analog Reset 52 55 9 1 460 110 13 5 mA Power down 110 170 10 20 525 220 15 25 mA 1000BASE-T 250 180 15 250 755 245 15 265 mA 2-port SGMII 100BASE-TX 155 175 15 170 645 235 15 190 mA 2-port SGMII VMDS-10509 VSC8572-02 Datasheet Revision 4.2 296 Electrical Specifications Table 494 • Current Consumption (continued) Mode Typical Maximum Unit Condition 1V Digital 1V 2.5 V Analog Digital 2.5 V 1V Analog Digital 1V 2.5 V Analog Digital 2.5 V Analog 10BASE-T 130 170 15 145 615 230 15 150 mA 2-port SGMII 10BASE-Te 130 170 15 135 615 230 15 140 mA 2-port SGMII 1000BASE-X 145 205 15 35 685 265 15 40 mA 2-port SGMII 100BASE-FX 135 200 15 35 645 260 15 40 mA 2-port SGMII 1000BASE-T 300 180 15 250 800 245 15 265 mA 2-port SGMII + 1588 100BASE-TX 175 175 15 170 665 235 15 190 mA 2-port SGMII + 1588 10BASE-T 150 170 15 145 625 230 15 150 mA 2-port SGMII + 1588 10BASE-Te 150 170 15 135 625 230 15 140 mA 2-port SGMII + 1588 1000BASE-X 190 205 15 35 715 265 15 40 mA 2-port SGMII + 1588 100BASE-FX 155 200 15 35 665 260 15 40 mA 2-port SGMII + 1588 1000BASE-T 235 100 55 250 740 160 65 265 mA 2-port RGMII 100BASE-TX 140 95 20 170 630 150 20 190 mA 2-port RGMII 10BASE-T 115 90 15 145 600 145 15 150 mA 2-port RGMII 10BASE-Te 115 90 15 135 600 145 15 140 mA 2-port RGMII 1000BASE-X 130 120 55 35 670 180 65 40 mA 2-port RGMII 100BASE-FX 120 115 20 35 630 175 20 40 mA 2-port RGMII 1000BASE-T 290 100 60 250 795 160 65 265 mA 2-port RGMII + 1588 100BASE-TX 165 95 20 170 650 150 20 190 mA 2-port RGMII + 1588 10BASE-T 140 90 15 145 610 145 15 150 mA 2-port RGMII + 1588 10BASE-Te 140 90 15 135 610 145 15 140 mA 2-port RGMII + 1588 1000BASE-X 180 120 60 35 700 180 65 40 mA 2-port RGMII + 1588 100BASE-FX 145 115 20 35 650 175 20 40 mA 2-port RGMII + 1588 1000BASE-T 250 145 10 250 755 210 15 265 mA 2-port half QSGMII 100BASE-TX 155 140 10 170 645 200 15 190 mA 2-port half QSGMII 10BASE-T 130 135 10 145 615 195 15 150 mA 2-port half QSGMII 10BASE-Te 130 135 10 135 615 195 15 140 mA 2-port half QSGMII 1000BASE-X 145 170 10 35 685 230 15 40 mA 2-port half QSGMII 100BASE-FX 135 165 10 35 645 225 15 40 mA 2-port half QSGMII 1000BASE-T 300 145 10 250 800 210 15 265 mA 2-port half QSGMII + 1588 100BASE-TX 175 140 10 170 665 200 15 190 mA 2-port half QSGMII + 1588 10BASE-T 150 135 10 145 625 195 15 150 mA 2-port half QSGMII + 1588 10BASE-Te 150 135 10 135 625 195 15 140 mA 2-port half QSGMII + 1588 1000BASE-X 190 175 10 35 715 230 15 40 mA 2-port half QSGMII + 1588 VMDS-10509 VSC8572-02 Datasheet Revision 4.2 297 Electrical Specifications Table 494 • Current Consumption (continued) Mode Typical 100BASE-FX 5.1.9 Maximum 1V Digital 1V 2.5 V Analog Digital 2.5 V 1V Analog Digital 1V 2.5 V Analog Digital 2.5 V Analog 155 170 35 225 40 10 665 15 Unit Condition mA 2-port half QSGMII + 1588 Thermal Diode The VSC8572-02 device includes an on-die diode and internal circuitry for monitoring die temperature (junction temperature). The operation and accuracy of the diode is not guaranteed and should only be used as a reference. Care should be taken to find compatible grounded cathode temperature monitoring device. A thermal sensor, located on the board or in a stand-alone measurement kit, can monitor and display the die temperature of the switch for thermal management or instrumentation purposes. Temperature measurement using a thermal diode is very sensitive to noise. The following table provides the diode parameter and interface specifications. Note that the ThermDC pin is connected to VSS internally in the device. Table 495 • Thermal Diode Parameters Parameter Symbol Forward bias current IFW Diode ideality factor n Typical Maximum Unit 1 mA 1.008 Note: Microsemi does not support or recommend operation of the thermal diode under reverse bias. The ideality factor, n, represents the deviation from ideal diode behavior as exemplified by the diode equation: I FW = I S ×  e q V d × ---------nkT  – 1 where, Is = saturation current, q = electronic charge, Vd = voltage across the diode, k = Boltzmann Constant, and T = absolute temperature (Kelvin). 5.2 AC Characteristics This section provides the AC specifications for the VSC8572-02 device. 5.2.1 Reference Clock The following table shows the AC specifications for a 125 MHz differential reference clock source. Performance is guaranteed for 125 MHz differential clocks only; however, 125 MHz single-ended clocks are also supported for QSGMII interfaces. 25 MHz clock implementations are available but are limited to SGMII interfaces. For more information, contact your Microsemi representative. Table 496 • Reference Clock AC Characteristics for QSGMII 125 MHz Differential Clock Parameter Symbol Reference clock frequency, REFCLK_SEL2 = 1 ƒ Minimum Typical 125.00 Maximum Unit Condition MHz ±100 ppm VMDS-10509 VSC8572-02 Datasheet Revision 4.2 298 Electrical Specifications Table 496 • Reference Clock AC Characteristics for QSGMII 125 MHz Differential Clock (continued) Parameter Symbol Minimum Typical Maximum Unit Duty cycle DC 40 50 60 % Rise time and fall time tr, tf 1.5 ns 20% to 80% threshold RefClk input RMS jitter requirement, bandwidth between 12 kHz and 500 kHz(1) 20 ps To meet jitter generation of 1G output data per IEEE 802.3z RefClk input RMS jitter requirement, bandwidth between 500 kHz and 15 MHz(1) 4 ps To meet jitter generation of 1G output data per IEEE 802.3z RefClk input RMS jitter requirement, bandwidth between 15 MHz and 40 MHz(1) 20 ps To meet jitter generation of 1G output data per IEEE 802.3z RefClk input RMS jitter requirement, bandwidth between 40 MHz and 80 MHz(1) 100 ps To meet jitter generation of 1G output data per IEEE 802.3z Jitter gain from RefClk to SerDes output, bandwidth between 0 MHz and 0.1 MHz 0.3 dB 3 dB 3–20 × log (ƒ/7 MHz) dB Jitter gain from RefClk to SerDes output, bandwidth between 0.1 MHz and 7 MHz 1 Jitter gain from RefClk to SerDes output, bandwidth above 7 MHz 1. 5.2.2 1–20 × log (ƒ/7 MHz) Condition Maximum RMS jitter allowed at the RefClk input for the given bandwidth. Recovered Clock This section provides the AC characteristics for the recovered clock output signals. The following illustration shows the test circuit for the recovered clock output signals. Figure 83 • Test Circuit for Recovered Clock Output Signals 39 Ω 50 Ω 8 pF Device Under Test Signal Measurement Point VMDS-10509 VSC8572-02 Datasheet Revision 4.2 299 Electrical Specifications The following table shows the AC specifications for the RCVRDCLK1 and RCVRDCLK2 outputs. Table 497 • Recovered Clock AC Characteristics 5.2.3 Parameter Symbol Recovered clock frequency ƒ 125.00 MHz Recovered clock frequency ƒ 31.25 MHz Recovered clock frequency ƒ 25.00 MHz Recovered clock cycle tRCYC time 8.0 ns Recovered clock cycle tRCYC time 32.0 ns Recovered clock cycle tRCYC time 40.0 ns Frequency stability ƒSTABILITY Duty cycle, master mode DC Clock rise time and fall time tR, tF Minimum 40 Typical 50 Maximum Unit 50 ppm 60 % 600 Condition ps 20% to 80% Peak-to-peak jitter, JPPCLK_Cu copper media interface (1000BASET slave mode) 400 ps 10K samples Peak-to-peak jitter, fiber media interface, 100BASE-FX JPPCLK_FiFX 1.2 ns 10K samples Peak-to-peak jitter, fiber media interface, 1000BASE-X JPPCLK_FiX 250 ps 10K samples SerDes Outputs The values listed in the following table are valid for all configurations, unless otherwise noted. Table 498 • SerDes Outputs AC Specifications Parameter Symbol VOD ringing compared to VS, RGMII/SGMII mode VRING VOD rise time and fall time, tR, tF RGMII/SGMII mode Minimum 100 Maximum Unit Condition ±10 % RL = 100 Ω ±1% 200 ps 20% to 80% of VS RL = 100 Ω ±1% 30 mV Tx disabled Differential peak-to-peak output voltage VOD Differential output return loss, 50 MHz to 625 MHz RLO_DIFF ≥10 dB RL = 100 Ω ±1% Differential output return loss, 625 MHz to 1250 MHz RLO_DIFF 10–10 × log (ƒ/625 MHz) dB RL = 100 Ω ±1% VMDS-10509 VSC8572-02 Datasheet Revision 4.2 300 Electrical Specifications Table 498 • SerDes Outputs AC Specifications (continued) 5.2.4 Parameter Symbol Minimum Common-mode return loss, 50 MHz to 625 MHz RLOCM 6 Interpair skew, RGMII/SGMII mode tSKEW Maximum Unit Condition dB 20 ps SerDes Driver Jitter The following table lists the jitter characteristics for the SerDes output driver. Table 499 • SerDes Driver Jitter Characteristics 5.2.5 Parameter Symbol Maximum Unit Condition Total jitter TJO 192 ps Measured according to IEEE 802.3.38.5 Deterministic jitter DJO 80 ps Measured according to IEEE 802.3.38.5 SerDes Inputs The following table lists the AC specifications for the SerDes inputs. Table 500 • SerDes Input AC Specifications 5.2.6 Parameter Maximum Unit Condition Differential input return loss, 50 MHz to 625 MHz ≥10 dB RL = 100 Ω ±1% Differential input return loss, 625 MHz to 1250 MHz 10–10 × log (ƒ/625 MHz) dB RL = 100 Ω ±1% SerDes Receiver Jitter Tolerance The following table lists jitter tolerances for the SerDes receiver. Table 501 • SerDes Receiver Jitter Tolerance 5.2.7 Parameter Symbol Minimum Unit Condition Total jitter tolerance, greater than 637 kHz, SFP mode TJTI 600 ps Measured according to IEEE 802.3 38.6.8 Deterministic jitter tolerance, greater than 637 kHz, SFP mode DJTI 370 ps Measured according to IEEE 802.3 38.6.8 Cycle distortion jitter tolerance, 100BASE-FX mode JTCD 1.4 ns Measured according to ISO/IEC 9314-3:1990 Data-dependent jitter tolerance, 100BASE-FX mode DDJ 2.2 ns Measured according to ISO/IEC 9314-3:1990 Random peak-to-peak jitter tolerance, 100BASE-FX mode RJT 2.27 ns Measured according to ISO/IEC 9314-3:1990 Enhanced SerDes Interface All AC specifications for the enhanced SerDes interface are compliant with QSGMII Specification Revision 1.3 and meet or exceed the requirements in the standard. They are also compliant with the OIFCEI-02.0 requirements where applicable. VMDS-10509 VSC8572-02 Datasheet Revision 4.2 301 Electrical Specifications The enhanced SerDes interface supports the following modes of operation: SGMII, QSGMII, and SFP. The values in the tables in the following sections apply to the QSGMII modes listed in the condition column and are based on the test circuit shown in Figure 79, page 294. The transmit and receive eye specifications relate to the eye diagrams shown in the following illustration, with the compliance load as defined in the test circuit. Figure 84 • QSGMII Transient Parameters Transmitter Eye Mask Receiver Eye Mask R_Y2 Amplitude (mV) Amplitude (mV) T_Y2 T_Y1 0 –T_Y1 –T_Y2 R_Y1 0 –R_Y1 –R_Y2 0 T_X1 T_X2 1–T_X2 1–T_X1 1.0 0 R_X1 Time (UI) 5.2.7.1 0.5 1–R_X1 1.0 Time (UI) Enhanced SerDes Outputs The following table provides the AC specifications for the enhanced SerDes outputs in SGMII mode. Table 502 • Enhanced SerDes Outputs AC Specifications, SGMII Mode Parameter Symbol Unit interval, 1.25G mode UI VOD ringing compared to VS VRING VOD rise time and fall time t R, tF Minimum Maximum Unit Condition 800 ps 100 Differential peak-to-peak output VOD voltage ±10 % RL = 100 Ω ±1% 200 ps 20% to 80% of VS RL = 100 Ω ±1% 30 mV Tx disabled Differential output return loss, 50 MHz to 625 MHz RLO_DIFF ≥10 dB RL = 100 Ω ±1% Differential output return loss, 625 MHz to 1250 MHz RLO_DIFF 10–10 × log (ƒ/625 MHz) dB RL = 100 Ω ±1% Common-mode return loss, 50 MHz to 625 MHz RLOCM dB Intrapair skew tSKEW 6 20 ps The following table provides the AC specifications for the enhanced SerDes outputs in QSGMII mode. Table 503 • Enhanced SerDes Outputs AC Specifications, QSGMII Mode Parameter Symbol Unit interval, 5G UI VOD rise time and fall time tR, tF Differential peak-to-peak output voltage VOD Minimum Maximum Unit Condition 200 ps 30 96 ps 20% to 80% of VS RL = 100 Ω ±1% 30 mV Tx disabled VMDS-10509 VSC8572-02 Datasheet Revision 4.2 302 Electrical Specifications Table 503 • Enhanced SerDes Outputs AC Specifications, QSGMII Mode 5.2.7.2 Parameter Symbol Differential output return loss, 100 MHz to 2.5 GHz Minimum Maximum Unit Condition RLO_DIFF 8 dB RL = 100 Ω ±1% Differential output return loss, 2.5 GHz to 5 GHz RLO_DIFF 8 dB – 16.6 log (ƒ/2.5 GHz) dB RL = 100 Ω ±1% Eye mask X1 T_X1 0.15 UI Eye mask X2 T_X2 0.4 UI Eye mask Y1 T_Y1 Eye mask Y2 T_Y2 200 mV 450 mV Enhanced SerDes Driver Jitter Characteristics The following table lists the jitter characteristics for the enhanced SerDes driver in QSGMII mode. For information about jitter characteristics for the enhanced SerDes driver in SGMII mode, see Table 499, page 301. Table 504 • Enhanced SerDes Driver Jitter Characteristics, QSGMII Mode 5.2.7.3 Parameter Symbol Maximum Unit Condition Total output jitter TJO 60 ps Measured according to IEEE 802.3.38.5. Deterministic output jitter DJO 10 ps Measured according to IEEE 802.3.38.5. Enhanced SerDes Inputs The following table lists the AC specifications for the enhanced SerDes inputs in SGMII mode. Table 505 • Enhanced SerDes Input AC Specifications, SGMII Mode Parameter Symbol Unit interval, 1.25G Minimum Unit Condition UI ps 800 ps Differential input return loss, 50 MHz to 625 MHz RLI_DIFF 10 dB RL = 100 Ω ±1% Common-mode input return loss, 50 MHz to 625 MHz RLICM dB 6 The following table lists the AC specifications for the enhanced SerDes inputs in QSGMII mode. Table 506 • Enhanced SerDes Inputs AC Specifications, QSGMII Mode Parameter Symbol Minimum Maximum Unit Condition Unit interval, 5G UI Differential input return loss, 100 MHz to 2.5 GHz RLI_DIFF 8 dB RL = 100 Ω ±1% Differential input return loss, 2.5 GHz to 5 GHz RLI_DIFF 8 dB – 16.6 log (ƒ/2.5 GHz) dB RL = 100 Ω ±1% Common-mode input return loss, 100 MHz to 2.5 GHz RLICM dB Eye mask X1 R_X1 200 ps 6 0.3 UI VMDS-10509 VSC8572-02 Datasheet Revision 4.2 303 Electrical Specifications Table 506 • Enhanced SerDes Inputs AC Specifications, QSGMII Mode Parameter Symbol Eye mask Y1 Eye mask Y2 5.2.7.4 Minimum Maximum Unit R_Y1 50 mV R_Y2 450 mV Condition Enhanced SerDes Receiver Jitter Tolerance The following table lists the jitter tolerance for the enhanced SerDes receiver in QSGMII mode. For information about jitter tolerance for the enhanced SerDes receiver in SGMII mode, see Table 501, page 301. Table 507 • Enhanced SerDes Receiver Jitter Tolerance, QSGMII Mode Parameter Symbol Maximum Unit Condition BHPJ 90 ps 92 ps peak-to-peak random jitter and 38 ps sinusoidal jitter (SJHF). Sinusoidal jitter, maximum SJMAX 1000 ps Sinusoidal jitter, high frequency SJHF 10 ps Total jitter tolerance TJTI 120 ps Bounded high-probability 1. 5.2.8 jitter(1) 92 ps peak-to-peak random jitter and 38 ps sinusoidal jitter (SJHF). This is the sum of uncorrelated bounded high probability jitter (0.15 UI), and correlated bounded high probability jitter (0.30 UI). Uncorrelated bounded high probability jitter is distribution where the value of the jitter shows no correlation to any signal level being transmitted, formally defined as deterministic jitter (DJ). Correlated bounded high probability jitter is jitter distribution where the value of the jitter shows a strong correlation to the signal level being transmitted. Basic Serial LEDs This section contains the AC specifications for the basic serial LEDs. Table 508 • Basic Serial LEDs AC Characteristics Parameter Symbol Typical Unit LED_CLK cycle time tCYC 1024 ns Pause between LED port sequences tPAUSE_port 3072 ns Pause between LED bit sequences tPAUSE_bit 25.541632 ms LED_CLK to LED_DATA tCO 1 ns Figure 85 • Basic Serial LED Timing tcyc LED_CLK LED_DATA tPAUSE_port tco Bit 1 Bit 2 Bit X VMDS-10509 VSC8572-02 Datasheet Revision 4.2 Bit 1 304 Electrical Specifications 5.2.9 Enhanced Serial LEDs This section contains the AC specifications for the enhanced serial LEDs. The duty cycle of the LED_PULSE signal is programmable and can be varied between 0.5% and 99.5%. Table 509 • Enhanced Serial LEDs AC Characteristics Parameter Symbol LED_CLK cycle time tCYC Pause between LED_DATA bit sequences tPAUSE Minimum Typical Maximum 256 Unit ns 0.396 24.996 ms LED_CLK to LED_DATA tCO 127 ns LED_CLK to LED_LD tCL 256 ns LED_LD pulse width tLW LED_PULSE cycle time tPULSE 128 ns 199 201 µs Figure 86 • Enhanced Serial LED Timing tcyc tpause LED_CLK tcl tco LED_DATA Bit 1 Bit 2 Bit X Bit 1 Bit 2 tlw LED_LD tpulse LED_PULSE 5.2.10 JTAG Interface This section provides the AC specifications for the JTAG interface. The specifications meet or exceed the requirements of IEEE 1149.1-2001. The JTAG receive signal requirements are requested at the pin of the device. The JTAG_TRST signal is asynchronous to the clock, and does not have a setup or hold time requirement. Table 510 • JTAG Interface AC Specifications Parameter Symbol Minimum TCK frequency ƒ TCK cycle time tC 100 ns TCK high time tW(CH) 40 ns TCK low time tW(CL) 40 ns Setup time to TCK rising tSU 10 ns Hold time from TCK rising tH 10 ns TDO valid after TCK falling tV(C) TDO hold time from TCK falling tH(TDO) TDO disable time(1) tDIS Maximum Unit 10 MHz 28 0 30 Condition ns CL = 10 pF ns CL = 0 pF ns See Figure 88, page 306. VMDS-10509 VSC8572-02 Datasheet Revision 4.2 305 Electrical Specifications Table 510 • JTAG Interface AC Specifications (continued) Parameter Symbol Minimum TRST time low tW(TL) 30 1. Maximum Unit Condition ns The pin begins to float when a 300 mV change from the actual VOH/VOL level occurs. Figure 87 • JTAG Interface Timing Diagram tc TCK tW(CH) tW(CL) TDI TMS tSU tH t V(C) TDO tH(TDO) tDIS See definition nTRST tW(TL) Figure 88 • Test Circuit for TDO Disable Time 3.3 V 500 Ω F rom output under test 5 pF 500 Ω 5.2.11 RGMII, Uncompensated The following illustration shows the test circuit for the RGMII output signals. Figure 89 • Test Circuit for RGMII Output Signals 39 Ω 50 Ω 8 pF Device Under Test Signal Measurement Point VMDS-10509 VSC8572-02 Datasheet Revision 4.2 306 Electrical Specifications The following table lists the characteristics when using the device in RGMII uncompensated mode. For more information about the RGMII uncompensated timing, see Figure 90, page 308. Table 511 • AC Characteristics for RGMII Uncompensated Parameter Symbol Minimum Clock frequency 1000BASE-T duty cycle Typical Maximum 125 25 2.5 tDUTY1000 Unit Condition MHz 1000BASE-T operation 100BASE-TX operation 10BASE-T operation 40 50 60 % 10/100BASE-T tDUTY10/100 duty cycle 35 38 65 % 10BASE-T 10/100BASE-T tDUTY10/100 duty cycle 40 50 60 % 100BASE-TX Data to clock tSKEWT output skew1 (at transmitter) –500 0 500 ps 1.0 1.8 2.6 ns Data to clock output skew1 (at receiver) tSKEWR TX_CLK switching threshold VTHRESH 1.25 V VDD25 = 2.5 Clock/data tR and tF output rise and fall times 750 ps 20% to 80%, 1000BASE-T Clock/data tR and tF output rise and fall times 1000 ps 20% to 80%, 10BASE-T/ 100BASE-TX 1. When operating in uncompensated mode, the PC board design requires a clock to be routed so that an additional trace delay of greater than 1.5 ns is added to the associated clock signal. VMDS-10509 VSC8572-02 Datasheet Revision 4.2 307 Electrical Specifications Figure 90 • RGMII Uncompensated Timing t SKEW T R G M IIn_TXC LK (at Transm itter) TXD [3:0] R G M IIn_TXD [3:0] TXEN R G M IIn_TXC TL TXD [7:4] TXER R t SKEW R R G M IIn_TXC LK (at R eceiver) V T H R ESH tR , tF R G M IIn_R XC LK (at Transm itter) t SKEW T 80% 20% R XD [3:0] R G M IIn_R XD [3:0] R XD V R G M IIn_R XC TL R XD [7:4] R XER R t SKEW R t C YC R G M IIn_R XC LK (at R eceiver) n = 0 or 1, corresponding to PHY n . 5.2.12 RGMII, Compensated The following table lists the characteristics when using the device in RGMII compensated mode. Table 512 • PHY Input (RGMIIn_TXCLK Delay When Register 18E2.[6:4]=011’b) Parameter Symbol Minimum Typical Data to clock setup (TX_CLK delay = 011’b) tSETUP_R –1.0 ns Clock to data hold (TX_CLK delay = 011’b) tHOLD_R ns 2.8 VMDS-10509 VSC8572-02 Datasheet Revision 4.2 Maximum Unit 308 Electrical Specifications Figure 91 • Compensated Input RGMII Timing RGMIIn_TXCLK tSETUP_R TXD[3:0] RGMIIn_TXD[3:0] TXD[7:4] tHOLD_R TXEN RGMIIn_TXCTL TXERR n = 0 or 1, corresponding to PHY n . Table 513 • PHY Output (RGMIIn_RXCLK Delay When Register 18E2.[3:1]=100’b) Parameter Symbol Minimum Data to clock setup (RX_CLK delay = 100’b) tSETUP_T 1.3 2.0 ns Clock to data hold (RX_CLK delay = 100’b) tHOLD_T 2.0 ns 1.4 Typical Maximum Unit Figure 92 • Compensated Output RGMII Timing RX_CLK delay = 100'b RX_CLK with Internal Delay Added RGMIIn_RXCLK RXD[3:0] RGMIIn_RXD[3:0] tSETUP_T RXD[7:4] tHOLD_T RXEN RGMIIn_RXCTL RXERR n = 0 or 1, corresponding to PHY n . 5.2.13 Serial Management Interface This section contains the AC specifications for the serial management interface (SMI). Table 514 • Serial Management Interface AC Characteristics Parameter Symbol Minimum Typical Maximum Unit MDC frequency(1) fCLK 2.5 12.5 MHz MDC cycle time tCYC 80 400 ns MDC time high tWH 20 50 ns MDC time low tWL 20 50 ns Setup to MDC rising tSU 10 ns Hold from MDC rising tH 10 ns MDC rise time tR 100 tCYC × 10%(1) ns VMDS-10509 VSC8572-02 Datasheet Revision 4.2 Condition MDC = 0: 1 MHz MDC = 1: MHz – fCLK maximum 309 Electrical Specifications Table 514 • Serial Management Interface AC Characteristics (continued) Parameter Symbol Minimum MDC fall time tF MDC to MDIO valid tCO 1. Typical Maximum Unit Condition ns Time-dependant on the value of the external pull-up resistor on the MDIO pin 100 tCYC × 10%(1) 10 300 For fCLK above 1 MHz, the minimum rise time and fall time is in relation to the frequency of the MDC clock period. For example, if fCLK is 2 MHz, the minimum clock rise time and fall time is 50 ns. Figure 93 • Serial Management Interface Timing tW L tW H M DC t CYC t SU tH M D IO (w rite) D ata t CO M D IO (rea d) 5.2.14 D a ta Reset Timing This section contains the AC specifications that apply to device reset functionality. The signal applied to the NRESET input must comply with the specifications listed in the following table. Table 515 • Reset Timing Specifications Parameter Symbol Minimum NRESET assertion time after power supplies and clock stabilize tW 2 Recovery time from reset inactive to device fully active tREC NRESET pulse width tW(RL) Wait time between NRESET de-assert tWAIT and access of the SMI interface Maximum Unit ms 105 ms 100 ns 105 ms VMDS-10509 VSC8572-02 Datasheet Revision 4.2 310 Electrical Specifications 5.2.15 1588 Timing Specifications This section contains the AC specifications for the 1588 clock pins. Table 516 • 1588 Timing Specifications AC Characteristics Parameter Symbol Minimum 1588 reference clock frequency1 ƒ 125 Duty cycle DC 40 Rise time and fall time tR, tF 1. 5.2.16 Typical 50 Maximum Unit Condition 250 MHz ±100 ppm Jitter < 10 ps RMS 60 % 1.5 ns 20% to 80% threshold Supports a continuum of frequencies between 125 MHz and 250 MHz. Serial Timestamp Interface This section contains information about the AC specifications for the serial timestamp interface. Table 517 • Serial Timestamp Interface Parameter Symbol Minimum Typical 1588_SPI_CLK frequency Maximum Unit 62.51 MHz 1588_SPI_DO clock- tCLK-to-Q to-Q timing –5 0 ns 1588_SPI_CS clock- tCLK-to-Q to-Q timing –5 0 ns 1. Condition SPI clock low time programmed through SI_CLK_LO_CYCs must always equal 0x1 (8 nanoseconds) for correct bus operation. Duty cycle is dependent on SI_CLK_HI_CYCs configuration. The following illustration shows the serial timestamp interface timing diagram. Note: Data changes state on a falling 1588_SPI_CLK edge in the default configuration. 1588_SPI_CLK can be inverted by setting the 1588 register bit TS_FIFO_SI_CFG:SI_CLK_PHA. Figure 94 • Serial Timestamp Interface Timing Diagram SPI_CLK SPI_DO, SPI_CS tCLK-to-Q 5.2.17 Local Time Counter Load/Save Timing This section contains information about the AC specifications for the local time counter load/save signal. VMDS-10509 VSC8572-02 Datasheet Revision 4.2 311 Electrical Specifications Figure 95 • Local Time Counter Load/Save Timing Diagram tC 1588_DIFF_INPUT_CLK tSU(DI) tH(DI) 1588_LOAD_SAVE Table 518 • Local Time Counter Load/Save Timing Specifications 5.3 Parameter Symbol Minimum Maximum Unit Clock frequency ƒ 250 MHz Clock cycle time tC 4 ns DI setup time to clock tSU(DI) 2.8 ns DI hold time from clock tH(DI) 0.3 ns Operating Conditions The following table shows the recommended operating conditions for the VSC8572-02 device. Table 519 • Recommended Operating Conditions Parameter Symbol Minimum Typical Maximum Unit Power supply voltage for VDD1 VDD1 0.95 1.00 1.05 V Power supply voltage for VDD1A VDD1A 0.95 1.00 1.05 V Power supply voltage for VDD25 VDD25 2.38 2.50 2.62 V Power supply voltage for VDD25A 2.50 2.62 V VDD25A 2.38 VSC8572-02 operating temperature(1) T 0 125 °C VSC8572-05 operating temperature(1) T –40 125 °C 1. 5.4 Minimum specification is ambient temperature, and the maximum is junction temperature. For carrier class applications, the maximum operating temperature is 110 °C junction. Stress Ratings This section contains the stress ratings for the VSC8572-02 device. Warning Stresses listed in the following table may be applied to devices one at a time without causing permanent damage. Functionality at or exceeding the values listed is not implied. Exposure to these values for extended periods may affect device reliability. Table 520 • Stress Ratings Parameter Symbol Minimum Maximum Unit Power supply voltage for core supply VVDD1 –0.3 1.10 V Power supply voltage for analog circuits VVDD1A –0.3 1.10 V Power supply voltage for analog circuits VVDD25A –0.3 2.75 V Power supply voltage for digital I/O VVDD25 –0.3 2.75 V VMDS-10509 VSC8572-02 Datasheet Revision 4.2 312 Electrical Specifications Table 520 • Stress Ratings (continued) Parameter Symbol Minimum Input voltage for GPIO and logic input pins Maximum Unit 3.3 V Storage temperature TS –55 125 °C Electrostatic discharge voltage, charged device model VESD_CDM –250 250 V Electrostatic discharge voltage, human body model VESD_HBM See note(1) 1. V This device has completed all required testing as specified in the JEDEC standard JESD22-A114, Electrostatic Discharge (ESD) Sensitivity Testing Human Body Model (HBM), and complies with a Class 2 rating. The definition of Class 2 is any part that passes an ESD pulse of 2000 V, but fails an ESD pulse of 4000 V. Warning This device can be damaged by electrostatic discharge (ESD) voltage. Microsemi recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures may adversely affect reliability of the device. VMDS-10509 VSC8572-02 Datasheet Revision 4.2 313 Pin Descriptions 6 Pin Descriptions The VSC8572-02 device has 256 pins, which are described in this section. The pin information is also provided as an attached Microsoft Excel file so that you can copy it electronically. In Acrobat, double-click the attachment icon. 6.1 Pin Identifications This section contains the pin descriptions for the VSC8572-02 device. The following table provides notations for definitions of the various pin types. Table 521 • Pin Type Symbol Definitions Symbol Pin Type 3V 6.2 Description 3.3 V-tolerant pin. ABIAS Analog bias Analog bias pin. ADIFF Analog differential Analog differential signal pair. I Input Input without on-chip pull-up or pull-down resistor. I/O Bidirectional Bidirectional input or output signal. NC No connect No connect pins must be left floating. O Output Output signal. OD Open drain Open drain output. OS Open source Open source output. PD Pull-down On-chip pull-down resistor to VSS. PU Pull-up On-chip pull-up resistor to VDD_IO. ST Schmitt-trigger Input has Schmitt-trigger circuitry. Pin Diagram The following illustrations show the pin diagram for the VSC8572-02 device. For clarity, the device is shown in two halves, the top left and top right. VMDS-10509 VSC8572-02 Datasheet Revision 4.2 314 Pin Descriptions Figure 96 • Pin Diagram, Top Left 1 2 3 4 5 6 7 8 A NC_1 RESERVED_54 RESERVED_56 RESERVED_58 RESERVED_60 RESERVED_62 RESERVED_64 RESERVED_66 B VSS_1 RESERVED_55 RESERVED_57 RESERVED_59 RESERVED_61 RESERVED_63 RESERVED_65 RESERVED_67 C REFCLK_N VDD25A_1 THERMDA VDD25A_2 VSS_3 VDD25A_3 VDD1A_1 VDD1A_2 D REFCLK_P THERMDC_VSS VSS_6 VSS_7 VSS_8 VSS_9 E REFCLK_SEL2 TMS TRST VDD25A_6 VDD1_1 VSS_14 VSS_15 VSS_16 F TDO TDI TCK VSS_20 VDD1_3 VSS_21 VSS_22 VSS_23 G LED0_0 LED1_0 LED2_0 LED3_0 VDD1_5 VSS_27 VSS_28 VSS_29 H LED0_1 LED1_1 LED2_1 LED3_1 VDD1_7 VSS_33 VSS_34 VSS_35 REF_FILT_A REF_REXT_A J RGMII1_RXD0 RGMII1_RXD1 RGMII1_RXD2 RGMII1_RXD3 VDD1_9 VSS_39 VSS_40 VSS_41 K RGMII1_TXCLK RGMII1_TXCTL RGMII1_RXCTL RGMII1_RXCLK VDD1_11 VSS_45 VSS_46 VSS_47 L RGMII1_TXD0 RESERVED_73 COMA_MODE RESERVED_3 VDD1_13 VSS_51 VSS_52 VSS_53 M RGMII1_TXD1 MDINT VDD1_15 VSS_57 VSS_58 VSS_59 N RGMII1_TXD2 MDIO VDD1_17 VSS_63 VSS_64 VSS_65 P RGMII1_TXD3 MDC VDD25_4 RESERVED_4 VDD25A_8 VDD1A_5 VDD1A_6 VDD1A_7 R VSS_69 RESERVED_22 RESERVED_24 RESERVED_26 RESERVED_28 RESERVED_30 RESERVED_32 RESERVED_34 T NC_3 RESERVED_23 RESERVED_25 RESERVED_27 RESERVED_29 RESERVED_31 RESERVED_33 RESERVED_35 NRESET VDD25_2 RESERVED_9 RESERVED_72 VMDS-10509 VSC8572-02 Datasheet Revision 4.2 315 Pin Descriptions Figure 97 • Pin Diagram, Top Right 9 10 11 12 13 14 15 16 RESERVED_68 TXVPA_1 TXVPB_1 TXVPC_1 TXVPD_1 TXVPA_0 TXVPB_0 NC_2 A RESERVED_69 TXVNA_1 TXVNB_1 TXVNC_1 TXVND_1 TXVNA_0 TXVNB_0 VSS_2 B VDD1A_3 RESERVED_1 VDD25A_4 VSS_4 VDD1A_4 VDD25A_5 TXVNC_0 TXVPC_0 C VSS_10 VSS_11 VSS_12 VSS_13 RESERVED_2 RGMII0_TXD3 TXVND_0 TXVPD_0 D VSS_17 VSS_18 VSS_19 VDD1_2 VDD25A_7 RGMII0_TXD2 VSS_24 VSS_25 VSS_26 VDD1_4 RGMII0_TXD1 VSS_30 VSS_31 VSS_32 VDD1_6 VSS_36 VSS_37 VSS_38 VSS_42 VSS_43 VSS_48 CLK_SQUELCH_IN 1588_SPI_CLK E PHYADD4 RGMII0_TXD0 RCVRDCLK1 F PHYADD2 PHYADD3 RGMII0_TXCLK RCVRDCLK2 G VDD1_8 VDD25_1 GPIO13/1588_SPI_DO RGMII0_TXCTL RGMII0_RXCLK H VSS_44 VDD1_10 RGMII0_RXCTL GPIO12/1588_SPI_CS 1588_DIFF_INPUT_CLK_P 1588_DIFF_INPUT_CLK_N J VSS_49 VSS_50 VDD1_12 GPIO8/I2C_SDA GPIO9/FASTLINK-FAIL GPIO10/1588_LOAD_SAVE GPIO11 K VSS_54 VSS_55 VSS_56 VDD1_14 GPIO4/I2C_SCL_0 GPIO5/I2C_SCL_1 VSS_60 VSS_61 VSS_62 VDD1_16 VSS_66 VSS_67 VSS_68 VDD1_18 VDD1A_8 VDD1A_9 VDD1A_10 VDD25A_9 RESERVED_36 FIBROP_1 FIBRIP_1 RDP_1 TDP_1 RESERVED_37 FIBRON_1 FIBRIN_1 RDN_1 TDN_1 6.3 RGMII0_RXD0 RGMII0_RXD1 L GPIO1/SIGDET1 RGMII0_RXD2 RGMII0_RXD3 M SerDes_Rext_1 GPIO0/SIGDET0 TDP_0 TDN_0 N VDD25A_10 SerDes_Rext_0 RDP_0 RDN_0 P FIBROP_0 FIBRIP_0 VSS_70 R FIBRON_0 FIBRIN_0 NC_4 T VDD25_3 Pins by Function This section contains the functional pin descriptions for the VSC8572-02 device. 6.3.1 1588 Support The following table lists the 1588 support pins. Table 522 • 1588 Support Pins Name Pin Type Description 1588_DIFF_INPUT_CLK_ N 1588_DIFF_INPUT_CLK_ P J16 J15 ADIFF Differential reference clock input pair. RESERVED_9 N3 NC Leave pin unconnected (floating). VMDS-10509 VSC8572-02 Datasheet Revision 4.2 316 Pin Descriptions Table 522 • 1588 Support Pins (continued) 6.3.2 Name Pin Type Description 1588_SPI_CLK E16 O 1588 SPI clock. GPIO and 1588 Support The following table lists the GPIO and 1588 support pins. Table 523 • GPIO and 1588 Support Pins 6.3.3 Name Pin Type Description GPIO10/1588_LOAD_SAVE K15 I/O, PU, 3 V Sync signal to load the time to the 1588 engine. Rising edge triggered. GPIO12/1588_SPI_CS J14 I/O, PU, 3 V 1588 SPI chip select. GPIO13/1588_SPI_DO H14 I/O, PU, 3 V 1588 SPI data output. GPIO and SIGDET The following table lists the GPIO and SIGDET pins. Table 524 • GPIO and SIGDET Pins 6.3.4 Name Pin Type Description GPIO0/SIGDET0 GPIO1/SIGDET1 GPIO4/I2C_SCL_0 GPIO5/I2C_SCL_1 GPIO8/I2C_SDA GPIO9/FASTLINK-FAIL GPIO11 N14 M14 L13 L14 K13 K14 K16 I/O, PU, 3 V General purpose input/output (GPIO). The multipurpose SIGDET pins, two-wire serial controller pins, and fast link fail pin can be configured to serve as GPIOs. JTAG The following table lists the JTAG test pins. Table 525 • JTAG Pins Name Pin Type Description TCK F3 I, PU, ST, 3 V JTAG test clock input. TDI F2 I, PU, ST, 3 V JTAG test serial data input. TDO F1 O JTAG test serial data output. TMS E2 I, PU, ST, 3 V JTAG test mode select. TRST E3 I, PU, ST, 3 V JTAG reset. Important When JTAG is not in use, this pin must be tied to ground with a pull-down resistor for normal operation. VMDS-10509 VSC8572-02 Datasheet Revision 4.2 317 Pin Descriptions 6.3.5 Miscellaneous The following table lists the miscellaneous pins. Table 526 • Miscellaneous Pins Name Pin Type Description CLK_SQUELCH_IN E15 I, PU, 3V Input control to squelch recovered clock. COMA_MODE L3 I, PU, 3V When this pin is asserted high, all PHYs are held in a powered down state. When de-asserted low, all PHYs are powered up and resume normal operation. This signal is also used to synchronize the operation of multiple chips on the same PCB to provide visual synchronization for LEDs driven by separate chips.(1) LED0_[0:1] LED1_[0:1] LED2_[0:1] LED3_[0:1] G1, H1 G2, H2 G3, H3, G4, H4, O LED direct-drive outputs. All LEDs pins are active-low. A serial LED stream can also be implemented. See LED Mode Select, page 110. Note: LEDbit_port, where port = PHY port number and bit = the particular LED for the port. NC_1 NC_2 NC_3 NC_4 A1 A16 T1 T16 NC No connect. PHYADD2 PHYADD3 PHYADD4 G13 G14 F14 I, PD, 3V Device SMI address bits 4:2. RCVRDCLK1 RCVRDCLK2 F16 G16 O Clock output can be enabled or disabled and also output a clock frequency of 125 MHz or 25 MHz based on the selected active recovered media programmed for this pin. This pin is not active when NRESET is asserted. When disabled, the pin is held low. REF_FILT_A D3 ABIAS Reference filter connects to an external 1 µF capacitor to analog ground. REF_REXT_A D4 ABIAS Reference external connects to an external 2 kΩ (1%) resistor to analog ground. REFCLK_N REFCLK_P C1 D1 I, ADIFF 125 MHz or 25 MHz reference clock input pair. Must be capacitively coupled and LVDS compatible. REFCLK_SEL2 E1 I, PU, 3V Selects the reference clock speed: 0: 25 MHz (VSS) 1: 125 MHz (2.5 V) Use 125 MHz for typical applications. RESERVED_[1:4] C10, D13, L4, P4 NC Leave these pins unconnected (floating). RESERVED_[22:37] R2, T2, R3, T3, NC R4, T4, R5, T5, R6, T6, R7, T7, R8, T8, R9, T9 Leave these pins unconnected (floating). VMDS-10509 VSC8572-02 Datasheet Revision 4.2 318 Pin Descriptions Table 526 • Miscellaneous Pins (continued) Name Type Description RESERVED_[54:69] A2, B2, A3, B3, A4, B4, A5, B5, A6, B6, A7, B7, A8, B8, A9, B9 NC Leave these pins unconnected (floating). RESERVED_[72:73] N4, L2 NC Leave these pins unconnected (floating). THERMDA C3 A Thermal diode anode. THERMDC_VSS D2 A Thermal diode cathode connected to device ground. Temperature sensor must be chosen accordingly. 1. 6.3.6 Pin For more information, see Initialization, page 93. For a typical bring-up example, see Configuration, page 92. Power Supply The following table lists the power supply pins and associated functional pins. All power supply pins must be connected to their respective voltage input, even if certain functions are not used for a specific application. No power supply sequencing is required. However, clock and power must be stable before releasing Reset. Table 527 • Power Supply Pins 6.3.6.1 Name Pin Type Description VDD1_[1:18] E5, E12, F5, F12, G5, G12, H5, H12, J5, J12, K5, K12, L5, L12, M5, M12, N5, N12 1.0 V 1.0 V internal digital logic. VDD1A_[1:10] C7, C8, C9, C13, P6, P7, P8, 1.0 V P9, P10, P11 1.0 V analog power requiring additional PCB power supply filtering. Associated with the QSGMII/SGMII MAC receiver output pins. VDD25_[1:4] H13, M4, M13, P3 2.5 V 2.5 V general digital power supply. Associated with the LED, GPIO, JTAG, twisted pair interface, reference filter, reference external supply connect, and recovered clock pins. VDD25A_[1:10] C2, C4, C6, C11, C14, E4, E13, P5, P12, P13 2.5 V 2.5 V general analog power supply. VSS_[1:4] VSS_[6:70] B1, B16, C5, C12 0V D5, D6, D7, D8, D9, D10, D11, D12, E6, E7, E8, E9, E10, E11, F4, F6, F7, F8, F9, F10, F11, G6, G7, G8, G9, G10, G11, H6, H7, H8, H9, H10, H11, J6, J7, J8, J9, J10, J11, K6, K7, K8, K9, K10, K11, L6, L7, L8, L9, L10, L11, M6, M7, M8, M9, M10, M11, N6, N7, N8, N9, N10, N11, R1, R16 General device ground. RGMII Interface The following table lists the RGMII interface pins. VMDS-10509 VSC8572-02 Datasheet Revision 4.2 319 Pin Descriptions Note: Unused RGMII port pins cannot be used as GPIOs. Table 528 • RGMII Interface Pins Name Pin Type Description RGMII0_RXCLK H16 O Receive clock. Receive data is sourced from the PHY synchronously on the rising edge of RXCLK and is the recovered clock from the media. RGMII0_RXCTL J13 O Multiplexed receive data valid, receive error. This output is sampled by the MAC on opposite edges of RXCLK to indicate two receive conditions from the PHY: 1. On the rising edge of RXCLK, this output serves as RXDV and signals valid data is available on the RXD input data bus. 2. On the falling edge of RXCLK, this output signals a receive error from the PHY, based on a logical derivative of RXDV and RXER, as stated by the RGMII specification. RGMII0_RXD0 RGMII0_RXD1 RGMII0_RXD2 RGMII0_RXD3 L15 L16 M15 M16 O Multiplexed receive data. Bits 3:0 are synchronously output on the rising edge of RXCLK and bits 7:4 on the falling edge of RXCLK. RGMII0_TXCLK G15 I Transmit clock. This clock is 2.5 MHz for 10 Mbps mode, 25 MHz for 100 Mbps mode, and 125 MHz for 1000 Mbps mode. If left unconnected, these pins require a pull-down resistor to ground. RGMII0_TXCTL H15 I Multiplexed transmit enable, transmit error. This input is sampled by the PHY on opposite edges of TXCLK to indicate two transmit conditions of the MAC: 1. On the rising edge of TXCLK, this input serves as TXEN, indicating valid data is available on the TXD input data bus. 2. On the falling edge of TXCLK, this input signals a transmit error from the MAC, based on a logical derivative of TXEN and TXER, as stated by the RGMII specification. RGMII0_TXD0 RGMII0_TXD1 RGMII0_TXD2 RGMII0_TXD3 F15 F13 E14 D14 I Multiplexed transmit data. Bits 3:0 are synchronously output on the rising edge of TXCLK and bits 7:4 on the falling edge of TXCLK. RGMII1_RXCLK K4 O Receive clock. Receive data is sourced from the PHY synchronously on the rising edge of RXCLK and is the recovered clock from the media. RGMII1_RXCTL K3 O Multiplexed receive data valid, receive error. This output is sampled by the MAC on opposite edges of RXCLK to indicate two receive conditions from the PHY: 1. On the rising edge of RXCLK, this output serves as RXDV and signals valid data is available on the RXD input data bus. 2. On the falling edge of RXCLK, this output signals a receive error from the PHY, based on a logical derivative of RXDV and RXER, as stated by the RGMII specification. VMDS-10509 VSC8572-02 Datasheet Revision 4.2 320 Pin Descriptions Table 528 • RGMII Interface Pins (continued) Name Pin Type Description RGMII1_RXD0 RGMII1_RXD1 RGMII1_RXD2 RGMII1_RXD3 J1 J2 J3 J4 O Multiplexed receive data. Bits 3:0 are synchronously output on the rising edge of RXCLK and bits 7:4 on the falling edge of RXCLK. RGMII1_TXCLK K1 I Transmit clock. This clock is 2.5 MHz for 10 Mbps mode, 25 MHz for 100 Mbps mode, and 125 MHz for 1000 Mbps mode. If left unconnected, these pins require a pull-down resistor to ground. RGMII1_TXCTL K2 I Multiplexed transmit enable, transmit error. This input is sampled by the PHY on opposite edges of TXCLK to indicate two transmit conditions of the MAC: 1. On the rising edge of TXCLK, this input serves as TXEN, indicating valid data is available on the TXD input data bus. 2. On the falling edge of TXCLK, this input signals a transmit error from the MAC, based on a logical derivative of TXEN and TXER, as stated by the RGMII specification. RGMII1_TXD0 RGMII1_TXD1 RGMII1_TXD2 RGMII1_TXD3 6.3.7 L1 M1 N1 P1 I Multiplexed transmit data. Bits 3:0 are synchronously output on the rising edge of TXCLK and bits 7:4 on the falling edge of TXCLK. SGMII/SerDes/QSGMII MAC Interface The following table lists the SerDes MAC interface pins. Table 529 • SerDes MAC Interface Pins Name Pin Type Description RDN_0 RDP_0 P16 P15 O, ADIFF PHY0 QSGMII/SGMII/SerDes MAC receiver output pair. RDN_1 RDP_1 T12 R12 O, ADIFF SGMII/SerDes MAC receiver output pair. SerDes_Rext_0 P14 ABIAS SerDes bias pins. Connect to a 620 Ω 1% resistor between SerDes_Rext_0 and SerDes_Rext_1. SerDes_Rext_1 N13 ABIAS SerDes bias pins. Connect to a 620 Ω 1% resistor between SerDes_Rext_0 and SerDes_Rext_1. TDN_0 TDP_0 N16 N15 I, ADIFF PHY0 QSGMII/SGMII/SerDes MAC transmitter input pair. TDN_1 TDP_1 T13 R13 I, ADIFF SGMII/SerDes MAC transmitter input pair. VMDS-10509 VSC8572-02 Datasheet Revision 4.2 321 Pin Descriptions 6.3.8 SerDes Media Interface The following table lists the SerDes media interface pins. Table 530 • SerDes Media Interface Pins Name Pin Type Description FIBRIN_0 FIBRIN_1 T15 I, ADIFF T11 SerDes media receiver input pair. FIBRIP_0 FIBRIP_1 R15 I, ADIFF R11 SerDes media receiver input pair. FIBRON_0 T14 O, ADIFF SerDes media transmitter output pair. FIBRON_1 T10 FIBROP_0 R14 O, ADIFF SerDes media transmitter output pair. FIBROP_1 R10 6.3.9 Serial Management Interface The following table lists the serial management interface (SMI) pins. The SMI pins are referenced to VDD25 and can be set to a 2.5 V power supply. Table 531 • SMI Pins Name Pin Type Description MDC P2 I, PD, 3 V Management data clock. A 0 MHz to 12.5 MHz reference input is used to clock serial MDIO data into and out of the PHY. MDINT M2 I/O, OS, OD Management interrupt signal. Upon reset the device will configure these pins as active-low (open drain) or active-high (open source) based on the polarity of an external 10 kΩ resistor connection. These pins can be tied together in a wired-OR configuration with only a single pull-up or pull-down resistor. MDIO N2 I/O, OD Management data input/output pin. Serial data is written or read from this pin bidirectionally between the PHY and Station Manager, synchronously on the positive edge of MDC. One external pull-up resistor is required at the Station Manager, and its value depends on the MDC clock frequency and the total sum of the capacitive loads from the MDIO pins. NRESET M3 6.3.10 I, PD, ST, 3 V Device reset. Active low input that powers down the device and sets all register bits to their default state. Twisted Pair Interface The following table lists the twisted pair interface pins. Table 532 • Twisted Pair Interface Pins Name Pin Type Description TXVNA_0 TXVNA_1 B14 B10 ADIFF TX/RX channel A negative signal TXVNB_0 TXVNB_1 B15 B11 ADIFF TX/RX channel B negative signal TXVNC_0 TXVNC_1 C15 B12 ADIFF TX/RX channel C negative signal VMDS-10509 VSC8572-02 Datasheet Revision 4.2 322 Pin Descriptions Table 532 • Twisted Pair Interface Pins (continued) Name Pin Type Description TXVND_0 TXVND_1 D15 B13 ADIFF TX/RX channel D negative signal TXVPA_0 TXVPA_1 A14 A10 ADIFF TX/RX channel A positive signal TXVPB_0 TXVPB_1 A15 A11 ADIFF TX/RX channel B positive signal TXVPC_0 TXVPC_1 C16 A12 ADIFF TX/RX channel C positive signal TXVPD_0 TXVPD_1 D16 A13 ADIFF TX/RX channel D positive signal VMDS-10509 VSC8572-02 Datasheet Revision 4.2 323 Package Information 7 Package Information VSC8572XKS-02 and VSC8572XKS-05 are packaged in a lead(Pb)-free, 256-pin, plastic ball grid array (BGA) with a 17 mm × 17 mm body size, 1 mm pin pitch, and 1.8 mm maximum height. Lead(Pb)-free products from Microsemi comply with the temperatures and profiles defined in the joint IPC and JEDEC standard IPC/JEDEC J-STD-020. For more information, see the IPC and JEDEC standard. This section provides the package drawing, thermal specifications, and moisture sensitivity rating for the VSC8572-02 device. 7.1 Package Drawing The following illustration shows the package drawing for the VSC8572-02 device. The drawing contains the top view, bottom view, side view, dimensions, tolerances, and notes. VMDS-10509 VSC8572-02 Datasheet Revision 4.2 324 Package Information Figure 98 • Package Drawing Top View Bottom View 0.20 (4×) Pin A1 corner X 17.00 Pin A1 corner 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 A B C D E F G H J K L M N P R T 1.00 15.00 17.00 1.00 Y 15.00 0.31–0.43 Side View 0.25 Z 1.8 maximum 4 Z Seating plane 5 0.20 Z Ø 0.45–0.64 Ø 0.25 M Ø 0.10 M Z X Y Z Notes 1. All dimensions and tolerances are in millimeters (mm). 2. Ball diameter is 0.50 mm. 3. Radial true position is represented by typical values. 4. Primary datum Z and seating plane are defined by the spherical crowns of the solder balls. 5. Dimension is measured at the maximum solder ball diameter, parallel to primary datum Z. 7.2 Thermal Specifications Thermal specifications for this device are based on the JEDEC JESD51 family of documents. These documents are available on the JEDEC Web site at www.jedec.org. The thermal specifications are modeled using a four-layer test board with two signal layers, a power plane, and a ground plane (2s2p VMDS-10509 VSC8572-02 Datasheet Revision 4.2 325 Package Information PCB). For more information about the thermal measurement method used for this device, see the JESD51-1 standard. Table 533 • Thermal Resistances Symbol °C/W Parameter θJCtop 5.9 Die junction to package case top θJB 12.7 Die junction to printed circuit board θJA 22 Die junction to ambient θJMA at 1 m/s 18.5 Die junction to moving air measured at an air speed of 1 m/s θJMA at 2 m/s 16.3 Die junction to moving air measured at an air speed of 2 m/s To achieve results similar to the modeled thermal measurements, the guidelines for board design described in the JESD51 family of publications must be applied. For information about applications using BGA packages, see the following: • • • • 7.3 JESD51-2A, Integrated Circuits Thermal Test Method Environmental Conditions, Natural Convection (Still Air) JESD51-6, Integrated Circuit Thermal Test Method Environmental Conditions, Forced Convection (Moving Air) JESD51-8, Integrated Circuit Thermal Test Method Environmental Conditions, Junction-to-Board JESD51-9, Test Boards for Area Array Surface Mount Package Thermal Measurements Moisture Sensitivity This device is rated moisture sensitivity level 4 as specified in the joint IPC and JEDEC standard IPC/JEDEC J-STD-020. For more information, see the IPC and JEDEC standard. VMDS-10509 VSC8572-02 Datasheet Revision 4.2 326 Design Considerations 8 Design Considerations This section provides information about design considerations for the VSC8572-02 device. 8.1 Link status LED remains on while COMA_MODE pin is asserted high When the COMA_MODE is asserted high, the link status LED may not deactivate unless the media cable is disconnected from the device. While using COMA_MODE, link status should be verified using status registers rather than LED indicators. 8.2 LED pulse stretch enable turns off LED pins Enabling the pulse stretch function for LED0 or LED1 by setting register 30, bits 5:6 shuts off those LED pins. Use the default blink function setting of LED0 and LED1 rather than pulse stretching. For more information, see LED Behavior, page 111. 8.3 AMS and 100BASE-FX When the PHY operating mode (set in register 23) is AMS and the current active media is 100BASE-FX, register 0 bit 12 will be 0. This would normally indicate that auto-negotiation is disabled and the PHY is in forced mode. But in this mode, it has other meanings. The workaround is to ensure that bit 12 is always written as 1 when doing writes or updates to register 0 in AMS mode. 8.4 10BASE-T signal amplitude 10BASE-T signal amplitude can be lower than the minimum specified in IEEE 802.3 paragraph 14.3.1.2.1 (2.2 V) at low supply voltages. This issue is not estimated to present any system level impact. Performance is not impaired with cables up to 130 m with various link partners. 8.5 10BASE-T link recovery failures If the link disconnects when traffic is flowing while the device operates in a 10BASE-T mode, the PHY may not re-link. There is a software workaround for this issue in which the device's internal microcontroller monitors link transitions in 10BASE-T mode and forces a soft power-down/power-up procedure to prevent a re-link failure. A side effect of this software workaround is that the counts in registers 20 and 21 will be cleared (For more information, see Error Counter 2, page 105 and Error Counter 3, page 105). 8.6 SNR degradation and link drops The link may drop after approximately 100 master/slave relationship swaps with the ring resiliency feature when using Category 5 (Cat5) cables that are longer than 75 m. The workaround is to use a combination of an initialization script and a procedure change. Contact Microsemi for the workaround solution if the ring resiliency feature is being enabled. 8.7 Clause 45 register 3.22 The clause 45, register 3.22 is cleared upon read only when the extended page access register (register 31) is set to 0. VMDS-10509 VSC8572-02 Datasheet Revision 4.2 327 Design Considerations This register cannot be read when the page access register is set to a value other than 0. The workaround is to set extended page access register to 0 before accessing clause 45, register 3.22. 8.8 Clause 45 register 3.1 Clause 45, register 3.1, Rx and Tx LPI received bits are cleared upon read only when the extended page access register (register 31) is set to 0. This has a minor implication for software that needs to ensure that the extended page access register is set to 0 before reading clause 45, register 3.1. The workaround is to set extended page access register to 0 before accessing clause 45, register 3.1. 8.9 Clause 45 register address post-increment Clause 45 register address post-increment only works when reading registers and only when extended page access register (register 31) is set to 0. The workaround is to access the registers individually. 8.10 Fast link failure indication The fast link failure indication for all the ports is enabled using port 0, register 19E.4. The workaround is to set register 19E.4 = 1 in PHY 0 to enable Fast Link Fail indication. 8.11 Timestamp accuracy in 10BASE-T mode Timestamp accuracy in 10BASE-T mode is ±400 ns. Timing accuracy is reduced on networks running in 10BASE-T mode. There is currently no workaround for this issue. 8.12 Near-end loopback with AMS enabled Near-end loopback does not work when AMS is enabled. Near-end loopback is controlled by setting bit 14 of register 0. The workaround is to disable AMS when enabling loopback. This is a debug feature and does not have any real life implications. 8.13 Carrier detect assertion Carrier detect assertion is set to false incorrectly when 9 out of 10 bits in the K28.1 word are in error. No real life implication is expected, because the event that can trigger this error is extremely unlikely. If it does occur, the link may drop momentarily and come back up. 8.14 Link status not correct in register 24E3.2 for 100BASEFX operation The link status in register 24E3.2 only reflects the status of 1000BASE-X links. It does not reflect the status of 100BASE-FX links. The workaround is to check register 28.4:3 for media operating mode (10 for fiber), 28.4:3 for speed status (100 for 100 Mbps), and then check 16.12 for current link status. 8.15 Register 28.14 does not reflect autonegotiation disabled in 100BASE-FX mode Register 28.14 does not reflect autonegotiation status in 100BASE-FX mode. It works correctly in all copper and 1000BASE-X media modes. VMDS-10509 VSC8572-02 Datasheet Revision 4.2 328 Design Considerations The workaround is to use register 0.12 for autonegotiation status in 100BASE-FX mode when AMS is disabled. For more information about limitations when AMS is enabled, see AMS and 100BASE-FX, page 327. 8.16 Near-end loopback non-functional in protocol transfer mode Near-end loopback does not work correctly when the device is configured in protocol transfer mode. This is a debug feature and does not have any effect on the normal operation of the device. 8.17 Fiber-media CRC counters non-functional in protocol transfer mode at 10 Mbps and 100 Mbps Packets received on the media SerDes interface will not be counted correctly in registers 28E3 and 29E3 when the device is configured in protocol transfer mode and operating at 10 Mbps or 100 Mbps speeds. These counters are used for debugging and there is no effect on the normal operation of the device. 8.18 Fiber-media recovered clock does not squelch based on link status To squelch the clock in fiber media mode, code sync status is used instead of link status. This causes the clock to not be squelched if the device is configured in 1000BASE-X mode with autonegotiation enabled when the transmit fiber is unplugged. There is a software workaround for this issue where the device's internal microcontroller monitors link status and forces the clock off when no link is present. 8.19 1000BASE-X parallel detect mode with Clause 37 autonegotiation enabled When connected to a forced-mode link partner and attempting autonegotiation, the PHY in 1000BASEX parallel detect mode requires a minimum 250 ms IDLE stream in order to establish a link. If the PHY port is programmed with 1000BASE-X parallel detect-enabled (MAC-side register 16E3 bit 13, or media-side register 23E3 bit 13), then a forced-mode link partner sending traffic with an inter-packet gap less than 250 ms will not allow the local device’s PCS to transition from a link-down to link-up state. 8.20 Anomalous PCS error indications in Energy Efficient Ethernet mode When a port is processing traffic with Energy Efficient Ethernet enabled on the link, certain PCS errors (such as false carriers, spurious start-of-stream detection, and idle errors) and EEE wake errors may occur. There is no effect on traffic bit error rate for cable lengths up to 75 meters, and minor packet loss may occur on links longer than 75 meters. Regardless of cable length, some error indications should not be used while EEE is enabled. These error indications include false carrier interrupts (Interrupt Status register 26 bit 3), receive error interrupts (Interrupt Status register 26 bit 0), and EEE wake error interrupts. Contact Microsemi for a script that needs to be applied during system initialization if EEE will be enabled. 8.21 Long link-up times while in forced 100BASE-TX mode of operation While in forced 100BASE-TX operation and attempting to link up, the device may experience abnormally long link-up times. This issue can only occur if the Unified API is not used with the device. In those circumstances, the workaround for this issue is to clear all speed advertisements in the autonegotiation advertisement VMDS-10509 VSC8572-02 Datasheet Revision 4.2 329 Design Considerations registers (register 4, bits 9:5 and register 9, bits 9:8), then toggle the auto-negotiation enable bit of the mode control register (register 0, bit 12) for a port upon detecting its link is down. Any advertisements temporarily cleared can then be restored once register 0, bit 12 is cleared. Contact Microsemi for the latest code sequence included in the Unified API. 8.22 Timestamp errors due to IEEE 1588 Reference Clock interruption Interruption of the IEEE 1588 reference clock after release of device hardware reset will corrupt the local time counter (LTC) value. After clock interruption, an LTC reload is required using the Unified API. 8.23 1588 bypass shall be enabled during engine reconfiguration When the 1588 datapath is enabled, the 1588 bypass feature shall be enabled before reprogramming 1588 configuration registers. It is recommended to disable 1588 bypass before live traffic begins flowing through the re-provisioned port. 8.24 Missing clock pulses on serial timestamp output interface The serial timestamp output interface may not generate the final 1588_SPI_CLK cycle for certain timestamp push-out transactions. This issue can be worked around by programming the SI_CLK_LO_CYCS to value 0x1. Use the latest PHY API for a workaround to this issue. 8.25 Station managers cannot use MDIO address offsets 0x2 and 0x3 with the PHY In addition to responding to the two lowest MDIO addresses that can be resolved with device serial management interface address bits 4:2, the device will unexpectedly respond to offsets that have bit 1 set (for a detailed addressing diagram, see SMI Frames, page 74). However, PHY2 and PHY3 are unusable targets on this device, so their corresponding MDIO addresses must not be used by the SMI station manager that controls this device. It is essential to avoid assigning addresses to other devices on the bus that would overlap the 0x2 and 0x3 offsets. The workaround for this issue is to ensure the station manager connected to this device avoids using the two MDIO addresses immediately following the PHY1 target. VMDS-10509 VSC8572-02 Datasheet Revision 4.2 330 Ordering Information 9 Ordering Information The VSC8572 device is offered with two operating temperature ranges. The range for VSC8572-02 is 0 °C ambient to 125 °C junction, and the range for VSC8572-05 is -40 °C ambient to 125 °C junction. VSC8572XKS-02 and VSC8572XKS-05 are packaged in a lead(Pb)-free, 256-pin, plastic ball grid array (BGA) with a 17 mm × 17 mm body size, 1 mm pin pitch, and 1.8 mm maximum height. Lead(Pb)-free products from Microsemi comply with the temperatures and profiles defined in the joint IPC and JEDEC standard IPC/JEDEC J-STD-020. For more information, see the IPC and JEDEC standard. The following table lists the ordering information for the VSC8572-02 device. Table 534 • Ordering Information Part Order Number Description VSC8572XKS-02 Lead-free, 256-pin, plastic BGA with a 17 mm × 17 mm body size, 1 mm pin pitch, and 1.8 mm maximum height. The operating temperature is 0 °C ambient to 125 °C junction1. VSC8572XKS-05 Lead-free, 256-pin, plastic BGA with a 17 mm × 17 mm body size, 1 mm pin pitch, and 1.8 mm maximum height. The operating temperature is –40 °C ambient to 125 °C junction1. 1. For carrier class applications, the maximum operating temperature is 110 °C junction. VMDS-10509 VSC8572-02 Datasheet Revision 4.2 331