VSC8574-02 Datasheet
Quad-Port 10/100/1000BASE-T PHY with Synchronous
Ethernet, IEEE 1588, and QSGMII/SGMII MAC
Microsemi Headquarters
One Enterprise, Aliso Viejo,
CA 92656 USA
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subsidiary of Microchip Technology Inc. All
rights reserved. Microsemi and the
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Microsemi Corporation. All other trademarks
and service marks are the property of their
respective owners.
Microsemi makes no warranty, representation, or guarantee regarding the information contained herein or the suitability of
its products and services for any particular purpose, nor does Microsemi assume any liability whatsoever arising out of the
application or use of any product or circuit. The products sold hereunder and any other products sold by Microsemi have
been subject to limited testing and should not be used in conjunction with mission-critical equipment or applications. Any
performance specifications are believed to be reliable but are not verified, and Buyer must conduct and complete all
performance and other testing of the products, alone and together with, or installed in, any end-products. Buyer shall not
rely on any data and performance specifications or parameters provided by Microsemi. It is the Buyer’s responsibility to
independently determine suitability of any products and to test and verify the same. The information provided by Microsemi
hereunder is provided “as is, where is” and with all faults, and the entire risk associated with such information is entirely
with the Buyer. Microsemi does not grant, explicitly or implicitly, to any party any patent rights, licenses, or any other IP
rights, whether with regard to such information itself or anything described by such information. Information provided in this
document is proprietary to Microsemi, and Microsemi reserves the right to make any changes to the information in this
document or to any products and services at any time without notice.
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semiconductor and system solutions for aerospace & defense, communications, data center and industrial markets.
Products include high-performance and radiation-hardened analog mixed-signal integrated circuits, FPGAs, SoCs and
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solutions, security technologies and scalable anti-tamper products; Ethernet solutions; Power-over-Ethernet ICs and
midspans; as well as custom design capabilities and services. Learn more at www.microsemi.com.
VMDS-10510. 4.2 4/19
Contents
1 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1
1.2
1.3
1.4
Revision 4.2
Revision 4.1
Revision 4.0
Revision 2.0
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1
1
2
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2 Product Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2.1
2.2
Key Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.1.1
Low Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.1.2
Advanced Carrier Ethernet Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.1.3
Wide Range of Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.1.4
Flexibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4
4
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3 Functional Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3.1
3.2
3.3
3.4
3.5
3.6
3.7
3.8
3.9
Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3.1.1
QSGMII/SGMII MAC-to-1000BASE-X Link Partner . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3.1.2
QSGMII/SGMII MAC-to-100BASE-FX Link Partner . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.1.3
QSGMII/SGMII MAC-to-AMS and 1000BASE-X Media SerDes . . . . . . . . . . . . . . . . . . . . . . . . 8
3.1.4
QSGMII/SGMII MAC-to-AMS and 100BASE-FX Media SerDes . . . . . . . . . . . . . . . . . . . . . . . . 9
3.1.5
QSGMII/SGMII MAC-to-AMS and Protocol Transfer Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.1.6
QSGMII/SGMII MAC-to-Cat5 Link Partner . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.1.7
QSGMII/SGMII MAC-to-Protocol Transfer Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.1.8
1000BASE-X MAC-to-Cat5 Link Partner . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
SerDes MAC Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.2.1
SerDes MAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.2.2
SGMII MAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.2.3
QSGMII MAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
SerDes Media Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.3.1
QSGMII/SGMII to 1000BASE-X . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.3.2
QSGMII/SGMII to 100BASE-FX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.3.3
QSGMII to SGMII Protocol Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.3.4
Unidirectional Transport for Fiber Media . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
PHY Addressing and Port Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.4.1
PHY Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.4.2
SerDes Port Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Cat5 Twisted Pair Media Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.5.1
Voltage Mode Line Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.5.2
Cat5 Autonegotiation and Parallel Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.5.3
Automatic Crossover and Polarity Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.5.4
Manual HP Auto-MDIX Setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.5.5
Link Speed Downshift . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.5.6
Energy Efficient Ethernet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.5.7
Ring Resiliency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Automatic Media Sense Interface Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Reference Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.7.1
Configuring the Reference Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.7.2
Single-Ended REFCLK Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.7.3
Differential REFCLK Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
1588 Reference Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Ethernet Inline Powered Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
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3.19
IEEE 802.3af PoE Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ActiPHY Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.11.1 Low Power State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.11.2 Link Partner Wake-Up State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.11.3 Normal Operating State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IEEE 1588 Timestamping Engine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.12.1 IEEE 1588 Block Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.12.2 Supporting IEEE 1588 Timestamping Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.12.3 Application 1: IEEE 1588 One-Step E2E TC in Systems . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.12.4 Application 2: IEEE 1588 TC and BC in Systems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.12.5 Application 3: Enhancing IEEE 1588 Accuracy for CE Switches and MACs . . . . . . . . . . . . . .
3.12.6 Supporting One-Step Peer-to-Peer Transparent Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.12.7 Supporting One-Step Boundary Clock/Ordinary Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.12.8 Supporting Two- Step Boundary/Ordinary Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.12.9 Supporting Two-Step Transparent Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.12.10 Calculating Y.1731 OAM Delay Measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.12.11 One-Way Delay Measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.12.12 Two-Way Delay Measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.12.13 IEEE 1588 Device Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.12.14 Timestamp Update . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.12.15 Analyzer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.12.16 Timestamp Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.12.17 Timestamp FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.12.18 Serial Timestamp Output Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.12.19 Rewriter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.12.20 Local Time Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.12.21 Accuracy and Resolution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.12.22 Accessing 1588 IP Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.12.23 1588_DIFF_INPUT_CLK Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Media Recovered Clock Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.13.1 Clock Selection Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.13.2 Clock Output Squelch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Serial Management Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.14.1 SMI Frames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.14.2 SMI Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LED Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.15.1 LED Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.15.2 Extended LED Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.15.3 LED Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.15.4 Basic Serial LED Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.15.5 Enhanced Serial LED Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.15.6 LED Port Swapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Fast Link Failure Indication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Integrated Two-Wire Serial Multiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.17.1 Read/Write Access Using the Two-Wire Serial MUX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
GPIO Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Testing Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.19.1 Ethernet Packet Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.19.2 CRC Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.19.3 Far-End Loopback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.19.4 Near-End Loopback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.19.5 Connector Loopback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.19.6 SerDes Loopbacks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.19.7 VeriPHY Cable Diagnostics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.19.8 JTAG Boundary Scan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.19.9 JTAG Instruction Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.19.10 Boundary Scan Register Cell Order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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3.20
3.21
100BASE-FX Halt Code Transmission and Reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
3.21.1 Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
4 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
4.1
4.2
4.3
4.4
4.5
Register and Bit Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
IEEE 802.3 and Main Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
4.2.1
Mode Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
4.2.2
Mode Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
4.2.3
Device Identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
4.2.4
Autonegotiation Advertisement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
4.2.5
Link Partner Autonegotiation Capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
4.2.6
Autonegotiation Expansion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
4.2.7
Transmit Autonegotiation Next Page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
4.2.8
Autonegotiation Link Partner Next Page Receive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
4.2.9
1000BASE-T Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
4.2.10 1000BASE-T Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
4.2.11 MMD Access Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
4.2.12 MMD Address or Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
4.2.13 1000BASE-T Status Extension 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
4.2.14 100BASE-TX/FX Status Extension . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
4.2.15 1000BASE-T Status Extension 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
4.2.16 Bypass Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
4.2.17 Error Counter 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
4.2.18 Error Counter 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
4.2.19 Error Counter 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
4.2.20 Extended Control and Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
4.2.21 Extended PHY Control Set 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
4.2.22 Extended PHY Control Set 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
4.2.23 Interrupt Mask . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
4.2.24 Interrupt Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
4.2.25 Device Auxiliary Control and Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
4.2.26 LED Mode Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
4.2.27 LED Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
4.2.28 Extended Page Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Extended Page 1 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
4.3.1
SerDes Media Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
4.3.2
Cu Media CRC Good Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
4.3.3
Extended Mode Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
4.3.4
ActiPHY Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
4.3.5
PoE and Miscellaneous Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
4.3.6
VeriPHY Control 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
4.3.7
VeriPHY Control 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
4.3.8
VeriPHY Control 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
4.3.9
Ethernet Packet Generator Control 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
4.3.10 Ethernet Packet Generator Control 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Extended Page 2 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
4.4.1
Cu PMD Transmit Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
4.4.2
EEE Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
4.4.3
Ring Resiliency Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
Extended Page 3 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
4.5.1
MAC SerDes PCS Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
4.5.2
MAC SerDes PCS Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
4.5.3
MAC SerDes Clause 37 Advertised Ability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
4.5.4
MAC SerDes Clause 37 Link Partner Ability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
4.5.5
MAC SerDes Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
4.5.6
Media SerDes Transmit Good Packet Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
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4.5.7
Media SerDes Transmit CRC Error Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
4.5.8
Media SerDes PCS Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
4.5.9
Media SerDes PCS Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
4.5.10 Media SerDes Clause 37 Advertised Ability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
4.5.11 Media SerDes Clause 37 Link Partner Ability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
4.5.12 Media SerDes Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
4.5.13 Fiber Media CRC Good Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
4.5.14 Fiber Media CRC Error Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
General Purpose Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
4.6.1
Reserved General Purpose Address Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
4.6.2
SIGDET/GPIO Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
4.6.3
GPIO Control 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
4.6.4
GPIO Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
4.6.5
GPIO Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
4.6.6
GPIO Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
4.6.7
Microprocessor Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
4.6.8
MAC Configuration and Fast Link . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
4.6.9
Two-Wire Serial MUX Control 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
4.6.10 Two-Wire Serial MUX Control 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
4.6.11 Two-Wire Serial MUX Data Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
4.6.12 Recovered Clock 1 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
4.6.13 Recovered Clock 2 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
4.6.14 Enhanced LED Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
4.6.15 Global Interrupt Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
4.6.16 Extended Revision ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
Clause 45 Registers to Support Energy Efficient Ethernet and 802.3bf . . . . . . . . . . . . . . . . . . . . . . . 138
4.7.1
PCS Status 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
4.7.2
EEE Capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
4.7.3
EEE Wake Error Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
4.7.4
EEE Advertisement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
4.7.5
EEE Link Partner Advertisement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
1588 IP Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
4.8.1
IP_1588:IP_1588_TOP_CFG_STAT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
4.8.2
IP_1588:IP_1588_LTC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
4.8.3
IP_1588:TS_FIFO_SI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
4.8.4
IP_1588:INGR_PREDICTOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
4.8.5
IP_1588:EGR_PREDICTOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
4.8.6
IP_1588:INGR_IP_1588_CFG_STAT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
4.8.7
IP_1588:INGR_IP_1588_TSP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
4.8.8
IP_1588:INGR_IP_1588_DF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
4.8.9
IP_1588:INGR_IP_1588_TSFIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
4.8.10 IP_1588:INGR_IP_1588_RW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
4.8.11 IP_1588:EGR_IP_1588_CFG_STAT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
4.8.12 IP_1588:EGR_IP_1588_TSP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
4.8.13 IP_1588:EGR_IP_1588_DF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
4.8.14 IP_1588:EGR_IP_1588_TSFIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
4.8.15 IP_1588:EGR_IP_1588_RW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
4.8.16 IP_1588:INGR_IP_1588_DEBUG_REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
4.8.17 IP_1588:EGR_IP_1588_DEBUG_REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
Egress0 Ethernet Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
4.9.1
ETHERNET_COMPARATOR:EGR0_ETH1_NXT_PROTOCOL . . . . . . . . . . . . . . . . . . . . . 179
4.9.2
ETHERNET_COMPARATOR:EGR0_ETH1_FLOW_CFG . . . . . . . . . . . . . . . . . . . . . . . . . . 181
4.9.3
ETHERNET_COMPARATOR:EGR0_ETH2_NXT_PROTOCOL . . . . . . . . . . . . . . . . . . . . . 184
4.9.4
ETHERNET_COMPARATOR:EGR0_ETH2_FLOW_CFG . . . . . . . . . . . . . . . . . . . . . . . . . . 186
4.9.5
ETHERNET_COMPARATOR:EGR0_MPLS_NXT_COMPARATOR . . . . . . . . . . . . . . . . . . 189
4.9.6
ETHERNET_COMPARATOR:EGR0_MPLS_FLOW_CFG . . . . . . . . . . . . . . . . . . . . . . . . . . 190
4.9.7
ETHERNET_COMPARATOR:EGR0_IP1_NXT_PROTOCOL . . . . . . . . . . . . . . . . . . . . . . . 193
4.9.8
ETHERNET_COMPARATOR:EGR0_IP1_FLOW_CFG . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
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4.13
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4.9.9
ETHERNET_COMPARATOR:EGR0_IP2_NXT_PROTOCOL . . . . . . . . . . . . . . . . . . . . . . . 200
4.9.10 ETHERNET_COMPARATOR:EGR0_IP2_FLOW_CFG . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204
4.9.11 ETHERNET_COMPARATOR:EGR0_PTP_FLOW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
4.9.12 ETHERNET_COMPARATOR:EGR0_PTP_IP_CHKSUM_CTL . . . . . . . . . . . . . . . . . . . . . . 211
4.9.13 ETHERNET_COMPARATOR:EGR0_FRAME_SIG_CFG . . . . . . . . . . . . . . . . . . . . . . . . . . 212
Ingress0 Ethernet Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214
4.10.1 ETHERNET_COMPARATOR:INGR0_ETH1_NXT_PROTOCOL . . . . . . . . . . . . . . . . . . . . . 215
4.10.2 ETHERNET_COMPARATOR:INGR0_ETH1_FLOW_CFG . . . . . . . . . . . . . . . . . . . . . . . . . 217
4.10.3 ETHERNET_COMPARATOR:INGR0_ETH2_NXT_PROTOCOL . . . . . . . . . . . . . . . . . . . . . 220
4.10.4 ETHERNET_COMPARATOR:INGR0_ETH2_FLOW_CFG . . . . . . . . . . . . . . . . . . . . . . . . . 222
4.10.5 ETHERNET_COMPARATOR:INGR0_MPLS_NXT_COMPARATOR . . . . . . . . . . . . . . . . . . 225
4.10.6 ETHERNET_COMPARATOR:INGR0_MPLS_FLOW_CFG . . . . . . . . . . . . . . . . . . . . . . . . . 226
4.10.7 ETHERNET_COMPARATOR:INGR0_IP1_NXT_PROTOCOL . . . . . . . . . . . . . . . . . . . . . . . 229
4.10.8 ETHERNET_COMPARATOR:INGR0_IP1_FLOW_CFG . . . . . . . . . . . . . . . . . . . . . . . . . . . 233
4.10.9 ETHERNET_COMPARATOR:INGR0_IP2_NXT_PROTOCOL . . . . . . . . . . . . . . . . . . . . . . . 236
4.10.10 ETHERNET_COMPARATOR:INGR0_IP2_FLOW_CFG . . . . . . . . . . . . . . . . . . . . . . . . . . . 240
4.10.11 ETHERNET_COMPARATOR:INGR0_PTP_FLOW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244
4.10.12 ETHERNET_COMPARATOR:INGR0_PTP_IP_CHKSUM_CTL . . . . . . . . . . . . . . . . . . . . . . 248
Egress1 Ethernet Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248
4.11.1 ETHERNET_COMPARATOR:EGR1_ETH1_NXT_PROTOCOL . . . . . . . . . . . . . . . . . . . . . 249
4.11.2 ETHERNET_COMPARATOR:EGR1_ETH1_FLOW_CFG . . . . . . . . . . . . . . . . . . . . . . . . . . 251
4.11.3 ETHERNET_COMPARATOR:EGR1_ETH2_NXT_PROTOCOL . . . . . . . . . . . . . . . . . . . . . 254
4.11.4 ETHERNET_COMPARATOR:EGR1_ETH2_FLOW_CFG . . . . . . . . . . . . . . . . . . . . . . . . . . 256
4.11.5 ETHERNET_COMPARATOR:EGR1_MPLS_NXT_COMPARATOR . . . . . . . . . . . . . . . . . . 259
4.11.6 ETHERNET_COMPARATOR:EGR1_MPLS_FLOW_CFG . . . . . . . . . . . . . . . . . . . . . . . . . . 260
4.11.7 ETHERNET_COMPARATOR:EGR1_IP1_NXT_PROTOCOL . . . . . . . . . . . . . . . . . . . . . . . 263
4.11.8 ETHERNET_COMPARATOR:EGR1_IP1_FLOW_CFG . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267
4.11.9 ETHERNET_COMPARATOR:EGR1_IP2_NXT_PROTOCOL . . . . . . . . . . . . . . . . . . . . . . . 270
4.11.10 ETHERNET_COMPARATOR:EGR1_IP2_FLOW_CFG . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274
4.11.11 ETHERNET_COMPARATOR:EGR1_PTP_FLOW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277
4.11.12 ETHERNET_COMPARATOR:EGR1_PTP_IP_CHKSUM_CTL . . . . . . . . . . . . . . . . . . . . . . 281
4.11.13 ETHERNET_COMPARATOR:EGR1_FRAME_SIG_CFG . . . . . . . . . . . . . . . . . . . . . . . . . . 282
Ingress1 Ethernet Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284
4.12.1 ETHERNET_COMPARATOR:INGR1_ETH1_NXT_PROTOCOL . . . . . . . . . . . . . . . . . . . . . 285
4.12.2 ETHERNET_COMPARATOR:INGR1_ETH1_FLOW_CFG . . . . . . . . . . . . . . . . . . . . . . . . . 287
4.12.3 ETHERNET_COMPARATOR:INGR1_ETH2_NXT_PROTOCOL . . . . . . . . . . . . . . . . . . . . . 290
4.12.4 ETHERNET_COMPARATOR:INGR1_ETH2_FLOW_CFG . . . . . . . . . . . . . . . . . . . . . . . . . 292
4.12.5 ETHERNET_COMPARATOR:INGR1_MPLS_NXT_COMPARATOR . . . . . . . . . . . . . . . . . . 295
4.12.6 ETHERNET_COMPARATOR:INGR1_MPLS_FLOW_CFG . . . . . . . . . . . . . . . . . . . . . . . . . 296
4.12.7 ETHERNET_COMPARATOR:INGR1_IP1_NXT_PROTOCOL . . . . . . . . . . . . . . . . . . . . . . . 299
4.12.8 ETHERNET_COMPARATOR:INGR1_IP1_FLOW_CFG . . . . . . . . . . . . . . . . . . . . . . . . . . . 303
4.12.9 ETHERNET_COMPARATOR:INGR1_IP2_NXT_PROTOCOL . . . . . . . . . . . . . . . . . . . . . . . 306
4.12.10 ETHERNET_COMPARATOR:INGR1_IP2_FLOW_CFG . . . . . . . . . . . . . . . . . . . . . . . . . . . 310
4.12.11 ETHERNET_COMPARATOR:INGR1_PTP_FLOW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314
4.12.12 ETHERNET_COMPARATOR:INGR1_PTP_IP_CHKSUM_CTL . . . . . . . . . . . . . . . . . . . . . . 318
Egress2 Ethernet Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 318
4.13.1 ETHERNET_COMPARATOR:EGR2_ETH1_NXT_PROTOCOL_A . . . . . . . . . . . . . . . . . . . 319
4.13.2 ETHERNET_COMPARATOR:EGR2_ETH1_NXT_PROTOCOL_B . . . . . . . . . . . . . . . . . . . 321
4.13.3 ETHERNET_COMPARATOR:EGR2_ETH1_FLOW_CFG . . . . . . . . . . . . . . . . . . . . . . . . . . 322
4.13.4 ETHERNET_COMPARATOR:EGR2_ETH2_NXT_PROTOCOL_A . . . . . . . . . . . . . . . . . . . 326
4.13.5 ETHERNET_COMPARATOR:EGR2_ETH2_FLOW_CFG . . . . . . . . . . . . . . . . . . . . . . . . . . 327
4.13.6 ETHERNET_COMPARATOR:EGR2_MPLS_NXT_COMPARATOR_A . . . . . . . . . . . . . . . . 331
4.13.7 ETHERNET_COMPARATOR:EGR2_MPLS_FLOW_CFG . . . . . . . . . . . . . . . . . . . . . . . . . . 332
4.13.8 ETHERNET_COMPARATOR:EGR2_PTP_FLOW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 335
Ingress2 Ethernet Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 339
4.14.1 ETHERNET_COMPARATOR:INGR2_ETH1_NXT_PROTOCOL_A . . . . . . . . . . . . . . . . . . . 340
4.14.2 ETHERNET_COMPARATOR:INGR2_ETH1_NXT_PROTOCOL_B . . . . . . . . . . . . . . . . . . . 341
4.14.3 ETHERNET_COMPARATOR:INGR2_ETH1_FLOW_CFG . . . . . . . . . . . . . . . . . . . . . . . . . 343
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4.14.4
4.14.5
4.14.6
4.14.7
4.14.8
ETHERNET_COMPARATOR:INGR2_ETH2_NXT_PROTOCOL_A . . . . . . . . . . . . . . . . . . .
ETHERNET_COMPARATOR:INGR2_ETH2_FLOW_CFG . . . . . . . . . . . . . . . . . . . . . . . . .
ETHERNET_COMPARATOR:INGR2_MPLS_NXT_COMPARATOR_A . . . . . . . . . . . . . . .
ETHERNET_COMPARATOR:INGR2_MPLS_FLOW_CFG . . . . . . . . . . . . . . . . . . . . . . . . .
ETHERNET_COMPARATOR:INGR2_PTP_FLOW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
347
348
351
352
356
5 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 361
5.1
5.2
5.3
5.4
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 361
5.1.1
VDD25 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 361
5.1.2
LED and GPIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 361
5.1.3
Internal Pull-Up or Pull-Down Resistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 361
5.1.4
Reference Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 362
5.1.5
1588 Reference Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 362
5.1.6
SerDes Interface (SGMII) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 362
5.1.7
Enhanced SerDes Interface (QSGMII) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 364
5.1.8
Current Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 365
5.1.9
Thermal Diode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 366
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 367
5.2.1
Reference Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 367
5.2.2
Recovered Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 368
5.2.3
SerDes Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 369
5.2.4
SerDes Driver Jitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 369
5.2.5
SerDes Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 370
5.2.6
SerDes Receiver Jitter Tolerance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 370
5.2.7
Enhanced SerDes Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 370
5.2.8
Basic Serial LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 373
5.2.9
Enhanced Serial LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 373
5.2.10 JTAG Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 374
5.2.11 Serial Management Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 375
5.2.12 Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 376
5.2.13 1588 Timing Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 377
5.2.14 Serial Timestamp Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 377
5.2.15 Local Time Counter Load/Save Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 377
Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 378
Stress Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 378
6 Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 380
6.1
6.2
6.3
Pin Identifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pin Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pins by Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.3.1
1588 Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.3.2
GPIO and 1588 Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.3.3
GPIO and SIGDET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.3.4
JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.3.5
Miscellaneous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.3.6
Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.3.7
SGMII/SerDes/QSGMII MAC Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.3.8
SerDes Media Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.3.9
Serial Management Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.3.10 Twisted Pair Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
380
380
382
382
383
383
383
384
385
385
386
386
387
7 Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 389
7.1
7.2
7.3
Package Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 389
Thermal Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 390
Moisture Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 391
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8 Design Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 392
8.1
8.2
8.3
8.4
8.5
8.6
8.7
8.8
8.9
8.10
8.11
8.12
8.13
8.14
8.15
8.16
8.17
8.18
8.19
8.20
8.21
8.22
8.23
8.24
Link status LED remains on while COMA_MODE pin is asserted high . . . . . . . . . . . . . . . . . . . . . . . . 392
LED pulse stretch enable turns off LED pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 392
AMS and 100BASE-FX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 392
10BASE-T signal amplitude . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 392
10BASE-T link recovery failures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 392
SNR degradation and link drops . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 392
Clause 45 register 3.22 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 392
Clause 45 register 3.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 393
Clause 45 register address post-increment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 393
Fast link failure indication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 393
Timestamp accuracy in 10BASE-T mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 393
Near-end loopback with AMS enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 393
Carrier detect assertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 393
Link status not correct in register 24E3.2 for 100BASE-FX operation . . . . . . . . . . . . . . . . . . . . . . . . . 393
Register 28.14 does not reflect autonegotiation disabled in 100BASE-FX mode . . . . . . . . . . . . . . . . 393
Near-end loopback non-functional in protocol transfer mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 394
Fiber-media CRC counters non-functional in protocol transfer mode at 10 Mbps and 100 Mbps . . . . 394
Fiber-media recovered clock does not squelch based on link status . . . . . . . . . . . . . . . . . . . . . . . . . . 394
1000BASE-X parallel detect mode with Clause 37 autonegotiation enabled . . . . . . . . . . . . . . . . . . . . 394
Anomalous PCS error indications in Energy Efficient Ethernet mode . . . . . . . . . . . . . . . . . . . . . . . . . 394
Long link-up times while in forced 100BASE-TX mode of operation . . . . . . . . . . . . . . . . . . . . . . . . . . 394
Timestamp errors due to IEEE 1588 Reference Clock interruption . . . . . . . . . . . . . . . . . . . . . . . . . . . 395
1588 bypass shall be enabled during engine reconfiguration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 395
Missing clock pulses on serial timestamp output interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 395
9 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 396
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Figures
Figure 1
Figure 2
Figure 3
Figure 4
Figure 5
Figure 6
Figure 7
Figure 8
Figure 9
Figure 10
Figure 11
Figure 12
Figure 13
Figure 14
Figure 15
Figure 16
Figure 17
Figure 18
Figure 19
Figure 20
Figure 21
Figure 22
Figure 23
Figure 24
Figure 25
Figure 26
Figure 27
Figure 28
Figure 29
Figure 30
Figure 31
Figure 32
Figure 33
Figure 34
Figure 35
Figure 36
Figure 37
Figure 38
Figure 39
Figure 40
Figure 41
Figure 42
Figure 43
Figure 44
Figure 45
Figure 46
Figure 47
Figure 48
Figure 49
Figure 50
Figure 51
Figure 52
Figure 53
Figure 54
Dual Media Application Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Copper Transceiver Application Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Fiber Media Transceiver Application Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
SGMII MAC-to-1000BASE-X Link Partner . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
QSGMII MAC-to-1000BASE-X Link Partner . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
QSGMII/SGMII MAC-to-100BASE-FX Link Partner . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
QSGMII/SGMII MAC-to-AMS and 1000BASE-X Media SerDes . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
QSGMII/SGMII MAC-to-AMS and 100BASE-FX Media SerDes . . . . . . . . . . . . . . . . . . . . . . . . . . 10
QSGMII/SGMII MAC-to-AMS and Protocol Transfer Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
QSGMII/SGMII MAC-to-Cat5 Link Partner . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
QSGMII/SGMII MAC-to-Protocol Transfer Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
1000BASE-X MAC-to-Cat5 Link Partner . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
SerDes MAC Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
SGMII MAC Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
QSGMII MAC Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Cat5 Media Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Low Power Idle Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Automatic Media Sense Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.5 V CMOS Single-Ended REFCLK Input Resistor Network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.3 V CMOS Single-Ended REFCLK Input Resistor Network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
5 V CMOS Single-Ended REFCLK Input Resistor Network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
AC Coupling for REFCLK Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Inline Powered Ethernet Switch Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
ActiPHY State Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
IEEE 1588 Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
One-Step E2E TC Mode A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
One-Step E2E TC Mode B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Linecard E2E TC PHY application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
BC Linecard Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Delay Measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
One-Step P2P TC Standard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
One-Step E2E BC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Two-Step E2E BC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Two-Step E2E TC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Y.1731 1DM PDU Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Y.1731 One-Way Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Y.1731 DMM PDU Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Y.1731 Two-Way Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
PTP Packet Encapsulations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
OAM Packet Encapsulations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
TSU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Analyzer Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Type II Ethernet Basic Frame Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Ethernet Frame with SNAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Ethernet Frame with VLAN Tag and SNAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Ethernet Frame with VLAN Tags and SNAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
PBB Ethernet Frame Format (No B-Tag) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
PBB Ethernet Frame Format (1 B-Tag) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
MPLS Label Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
MPLS Label Stack within an Ethernet Frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
MPLS Labels and Control Word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
IPv4 with UDP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
IPv6 with UDP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
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Figure 55
Figure 56
Figure 57
Figure 58
Figure 59
Figure 60
Figure 61
Figure 62
Figure 63
Figure 64
Figure 65
Figure 66
Figure 67
Figure 68
Figure 69
Figure 70
Figure 71
Figure 72
Figure 73
Figure 74
Figure 75
Figure 76
Figure 77
Figure 78
Figure 79
Figure 80
Figure 81
Figure 82
Figure 83
Figure 84
Figure 85
Figure 86
Figure 87
Figure 88
Figure 89
Figure 90
Figure 91
Figure 92
Figure 93
ACH Header Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
ACH Header with Protocol ID Field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
IPSec Header Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
IPv6 with UDP and IPSec . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
PTP Frame Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
OAM 1DM Frame Header Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
OAM DMM Frame Header Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
OAM DMR Frame Header Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Serial Time Stamp/Frame Signature Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Preamble Reduction in Rewriter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Local Time Counter Load/Save Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
SMI Read Frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
SMI Write Frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
MDINT Configured as an Open-Drain (Active-Low) Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
MDINT Configured as an Open-Source (Active-High) Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Two-Wire Serial MUX with SFP Control and Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Two-Wire Serial MUX Read and Write Register Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Far-End Loopback Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Near-End Loopback Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Connector Loopback Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Data Loops of the SerDes Macro . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Test Access Port and Boundary Scan Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Register Space Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
SGMII DC Transmit Test Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 363
SGMII DC Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 363
SGMII DC Driver Output Impedance Test Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 364
SGMII DC Input Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 364
Test Circuit for Recovered Clock Output Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 368
QSGMII Transient Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 370
Basic Serial LED Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 373
Enhanced Serial LED Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 374
JTAG Interface Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 375
Test Circuit for TDO Disable Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 375
Serial Management Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 376
Serial Timestamp Interface Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 377
Local Time Counter Load/Save Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 378
Pin Diagram, Top Left . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 381
Pin Diagram, Top Right . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 382
Package Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 390
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Tables
Table 1
Table 2
Table 3
Table 4
Table 5
Table 6
Table 7
Table 8
Table 9
Table 10
Table 11
Table 12
Table 13
Table 14
Table 15
Table 16
Table 17
Table 18
Table 19
Table 20
Table 21
Table 22
Table 23
Table 24
Table 25
Table 26
Table 27
Table 28
Table 29
Table 30
Table 31
Table 32
Table 33
Table 34
Table 35
Table 36
Table 37
Table 38
Table 39
Table 40
Table 41
Table 42
Table 43
Table 44
Table 45
Table 46
Table 47
Table 48
Table 49
Table 50
Table 51
Table 52
Table 53
Table 54
Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
MAC Interface Mode Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Supported MDI Pair Combinations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
AMS Media Preferences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
REFCLK Frequency Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Flows Per Engine Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Ethernet Comparator: Next Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Comparator ID Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Ethernet Comparator (Next Protocol) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Ethernet Comparator (Flow) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
MPLS Comparator: Next Word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Next MPLS Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
MPLS Comparator: Per-Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
MPLS Range_Upper/Lower Label Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Next-Protocol Registers in OAM-Version of MPLS Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Comparator Field Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
IP/ACH Next-Protocol Comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
IP/ACH Comparator Flow Verification Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
PTP Comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
PTP Comparison: Common Controls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
PTP Comparison: Additions for OAM-Optimized Engine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Frame Signature Byte Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Frame Signature Address Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Register 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Register 17 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Register 18 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
LED Drive State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
LED Mode and Function Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Extended LED Mode and Function Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
LED Serial Bitstream Order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Register Bits for GPIO Control and Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
SerDes Macro Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
JTAG Instruction Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
IDCODE JTAG Device Identification Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
USERCODE JTAG Device Identification Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
JTAG Instruction Code IEEE Compliance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
IEEE 802.3 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Main Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Mode Control, Address 0 (0x00) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Mode Status, Address 1 (0x01) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Identifier 1, Address 2 (0x02) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Identifier 2, Address 3 (0x03) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Device Autonegotiation Advertisement, Address 4 (0x04) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Autonegotiation Link Partner Ability, Address 5 (0x05) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Autonegotiation Expansion, Address 6 (0x06) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Autonegotiation Next Page Transmit, Address 7 (0x07) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Autonegotiation LP Next Page Receive, Address 8 (0x08) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
1000BASE-T Control, Address 9 (0x09) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
1000BASE-T Status, Address 10 (0x0A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
MMD EEE Access, Address 13 (0x0D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
MMD Address or Data Register, Address 14 (0x0E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
1000BASE-T Status Extension 1, Address 15 (0x0F) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
100BASE-TX/FX Status Extension, Address 16 (0x10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
1000BASE-T Status Extension 2, Address 17 (0x11) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
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Table 56
Table 57
Table 58
Table 59
Table 60
Table 61
Table 62
Table 63
Table 64
Table 65
Table 66
Table 67
Table 68
Table 69
Table 70
Table 71
Table 72
Table 73
Table 74
Table 75
Table 76
Table 77
Table 78
Table 79
Table 80
Table 81
Table 82
Table 83
Table 84
Table 85
Table 86
Table 87
Table 88
Table 89
Table 90
Table 91
Table 92
Table 93
Table 94
Table 95
Table 96
Table 97
Table 98
Table 99
Table 100
Table 101
Table 102
Table 103
Table 104
Table 105
Table 106
Table 107
Table 108
Table 109
Table 110
Table 111
Table 112
Table 113
Bypass Control, Address 18 (0x12) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Error Counter 1, Address 19 (0x13) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Error Counter 2, Address 20 (0x14) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Error Counter 3, Address 21 (0x15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Extended Control and Status, Address 22 (0x16) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Extended PHY Control 1, Address 23 (0x17) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Extended PHY Control 2, Address 24 (0x18) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Interrupt Mask, Address 25 (0x19) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Interrupt Status, Address 26 (0x1A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Auxiliary Control and Status, Address 28 (0x1C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
LED Mode Select, Address 29 (0x1D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
LED Behavior, Address 30 (0x1E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Extended/GPIO Register Page Access, Address 31 (0x1F) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Extended Registers Page 1 Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
SerDes Media Control, Address 16E1 (0x10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Cu Media CRC Good Counter, Address 18E1 (0x12) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Extended Mode Control, Address 19E1 (0x13) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Extended PHY Control 3, Address 20E1 (0x14) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Extended PHY Control 4, Address 23E1 (0x17) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
VeriPHY Control Register 1, Address 24E1 (0x18) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
VeriPHY Control Register 2, Address 25E1 (0x19) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
VeriPHY Control Register 3, Address 26E1 (0x1A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
VeriPHY Control Register 3 Fault Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
EPG Control Register 1, Address 29E1 (0x1D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
EPG Control Register 2, Address 30E1 (0x1E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Extended Registers Page 2 Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
Cu PMD Transmit Control, Address 16E2 (0x10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
EEE Control, Address 17E2 (0x11) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
Ring Resiliency, Address 30E2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
Extended Registers Page 3 Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
MAC SerDes PCS Control, Address 16E3 (0x10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
MAC SerDes PCS Status, Address 17E3 (0x11) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
MAC SerDes Cl37 Advertised Ability, Address 18E3 (0x12) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
MAC SerDes Cl37 LP Ability, Address 19E3 (0x13) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
MAC SerDes Status, Address 20E3 (0x14) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
Media SerDes Tx Good Packet Counter, Address 21E3 (0x15) . . . . . . . . . . . . . . . . . . . . . . . . . . 124
Media SerDes Tx CRC Error Counter, Address 22E3 (0x16) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
Media SerDes PCS Control, Address 23E3 (0x17) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Media SerDes PCS Status, Address 24E3 (0x18) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Media SerDes Cl37 Advertised Ability, Address 25E3 (0x19) . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
MAC SerDes Cl37 LP Ability, Address 26E3 (0x1A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
Media SerDes Status, Address 27E3 (0x1B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
Fiber Media CRC Good Counter, Address 28E3 (0x1C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
Fiber Media CRC Error Counter, Address 29E3 (0x1D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
General Purpose Registers Page Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
SIGDET/GPIO Control, Address 13G (0x0D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
GPIO Control 2, Address 14G (0x0E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
GPIO Input, Address 15G (0x0F) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
GPIO Output, Address 16G (0x10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
GPIO Input/Output Configuration, Address 17G (0x11) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
Microprocessor Command Register, Address 18G . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
MAC Configuration and Fast Link Register, Address 19G (0x13) . . . . . . . . . . . . . . . . . . . . . . . . 132
Two-Wire Serial MUX Control 1, Address 20G (0x14) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
Two-Wire Serial MUX Interface Status and Control, Address 21G (0x15) . . . . . . . . . . . . . . . . . . 133
Two-Wire Serial MUX Data Read/Write, Address 22G (0x16) . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
Recovered Clock 1 Control, Address 23G (0x17) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
Recovered Clock 2 Control, Address 24G (0x18) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
Enhanced LED Control, Address 25G (0x19) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
Global Interrupt Status, Address 29G (0x1D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
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Table 116
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Table 118
Table 119
Table 120
Table 121
Table 122
Table 123
Table 124
Table 125
Table 126
Table 127
Table 128
Table 129
Table 130
Table 131
Table 132
Table 133
Table 134
Table 135
Table 136
Table 137
Table 138
Table 139
Table 140
Table 141
Table 142
Table 143
Table 144
Table 145
Table 146
Table 147
Table 148
Table 149
Table 150
Table 151
Table 152
Table 153
Table 154
Table 155
Table 156
Table 157
Table 158
Table 159
Table 160
Table 161
Table 162
Table 163
Table 164
Table 165
Table 166
Table 167
Table 168
Table 169
Table 170
Table 171
Table 172
Extended Revision ID, Address 30G (0x1E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Clause 45 Registers Page Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PCS Status 1, Address 3.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
EEE Capability, Address 3.20 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
EEE Wake Error Counter, Address 3.22 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
EEE Advertisement, Address 7.60 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
EEE Advertisement, Address 7.61 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
802.3bf Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Register Groups in IP_1588 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Registers in IP_1588_TOP_CFG_STAT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Fields in INTERFACE_CTL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Fields in ANALYZER_MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Fields in SPARE_REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Registers in IP_1588_LTC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Fields in LTC_CTRL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Fields in LTC_LOAD_SEC_H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Fields in LTC_LOAD_SEC_L . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Fields in LTC_LOAD_NS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Fields in LTC_SAVED_SEC_H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Fields in LTC_SAVED_SEC_L . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Fields in LTC_SAVED_NS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Fields in LTC_SEQUENCE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Fields in LTC_SEQ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Fields in LTC_AUTO_ADJUST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Registers in TS_FIFO_SI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Fields in TS_FIFO_SI_CFG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Fields in TS_FIFO_SI_TX_CNT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Registers in INGR_PREDICTOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Fields in IG_CFG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Fields in IG_PMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Fields in IG_XFI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Fields in IG_OTN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Registers in EGR_PREDICTOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Fields in EG_CFG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Fields in EG_WIS_FRAME . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Fields in EG_WIS_DELAYS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Fields in EG_PMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Fields in EG_XFI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Fields in EG_OTN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Registers in INGR_IP_1588_CFG_STAT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Fields in INGR_INT_STATUS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Fields in INGR_INT_MASK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Fields in INGR_SPARE_REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Registers in INGR_IP_1588_TSP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Fields in INGR_TSP_CTRL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Fields in INGR_TSP_STAT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Fields in INGR_LOCAL_LATENCY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Fields in INGR_PATH_DELAY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Fields in INGR_DELAY_ASYMMETRY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Registers in INGR_IP_1588_DF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Fields in INGR_DF_CTRL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Registers in INGR_IP_1588_TSFIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Fields in INGR_TSFIFO_CSR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Fields in INGR_TSFIFO_0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Fields in INGR_TSFIFO_1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Fields in INGR_TSFIFO_2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Fields in INGR_TSFIFO_3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Fields in INGR_TSFIFO_4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Fields in INGR_TSFIFO_5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Table 173
Table 174
Table 175
Table 176
Table 177
Table 178
Table 179
Table 180
Table 181
Table 182
Table 183
Table 184
Table 185
Table 186
Table 187
Table 188
Table 189
Table 190
Table 191
Table 192
Table 193
Table 194
Table 195
Table 196
Table 197
Table 198
Table 199
Table 200
Table 201
Table 202
Table 203
Table 204
Table 205
Table 206
Table 207
Table 208
Table 209
Table 210
Table 211
Table 212
Table 213
Table 214
Table 215
Table 216
Table 217
Table 218
Table 219
Table 220
Table 221
Table 222
Table 223
Table 224
Table 225
Table 226
Table 227
Table 228
Table 229
Table 230
Table 231
Fields in INGR_TSFIFO_6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
Fields in INGR_TSFIFO_DROP_CNT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
Registers in INGR_IP_1588_RW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
Fields in INGR_RW_CTRL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
Fields in INGR_RW_MODFRM_CNT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
Fields in INGR_RW_FCS_ERR_CNT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
Fields in INGR_RW_PREAMBLE_ERR_CNT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
Registers in EGR_IP_1588_CFG_STAT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
Fields in EGR_INT_STATUS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
Fields in EGR_INT_MASK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
Fields in EGR_SPARE_REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
Registers in EGR_IP_1588_TSP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
Fields in EGR_TSP_CTRL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
Fields in EGR_TSP_STAT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
Fields in EGR_LOCAL_LATENCY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
Fields in EGR_PATH_DELAY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
Fields in EGR_DELAY_ASYMMETRY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
Registers in EGR_IP_1588_DF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
Fields in EGR_DF_CTRL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
Registers in EGR_IP_1588_TSFIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
Fields in EGR_TSFIFO_CSR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
Fields in EGR_TSFIFO_0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
Fields in EGR_TSFIFO_1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
Fields in EGR_TSFIFO_2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
Fields in EGR_TSFIFO_3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
Fields in EGR_TSFIFO_4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
Fields in EGR_TSFIFO_5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
Fields in EGR_TSFIFO_6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
Fields in EGR_TSFIFO_DROP_CNT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
Registers in EGR_IP_1588_RW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
Fields in EGR_RW_CTRL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
Fields in EGR_RW_MODFRM_CNT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
Fields in EGR_RW_FCS_ERR_CNT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
Fields in EGR_RW_PREAMBLE_ERR_CNT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
INGR_IP_1588_DEBUG_REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
EGR_IP_1588_DEBUG_REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
Register Groups in Egress0 Ethernet Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
Registers in EGR0_ETH1_NXT_PROTOCOL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
Fields in EGR0_ETH1_NXT_PROTOCOL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
Fields in EGR0_ETH1_VLAN_TPID_CFG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
Fields in EGR0_ETH1_TAG_MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
Fields in EGR0_ETH1_ETYPE_MATCH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
Registers in EGR0_ETH1_FLOW_CFG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
Fields in EGR0_ETH1_FLOW_ENABLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
Fields in EGR0_ETH1_MATCH_MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
Fields in EGR0_ETH1_ADDR_MATCH_1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
Fields in EGR0_ETH1_ADDR_MATCH_2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
Fields in EGR0_ETH1_VLAN_TAG_RANGE_I_TAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
Fields in EGR0_ETH1_VLAN_TAG1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
Fields in EGR0_ETH1_VLAN_TAG2_I_TAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
Registers in EGR0_ETH2_NXT_PROTOCOL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
Fields in EGR0_ETH2_NXT_PROTOCOL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
Fields in EGR0_ETH2_VLAN_TPID_CFG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
Fields in EGR0_ETH2_ETYPE_MATCH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
Registers in EGR0_ETH2_FLOW_CFG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
Fields in EGR0_ETH2_FLOW_ENABLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
Fields in EGR0_ETH2_MATCH_MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
Fields in EGR0_ETH2_ADDR_MATCH_1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
Fields in EGR0_ETH2_ADDR_MATCH_2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
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Table 233
Table 234
Table 235
Table 236
Table 237
Table 238
Table 239
Table 240
Table 241
Table 242
Table 243
Table 244
Table 245
Table 246
Table 247
Table 248
Table 249
Table 250
Table 251
Table 252
Table 253
Table 254
Table 255
Table 256
Table 257
Table 258
Table 259
Table 260
Table 261
Table 262
Table 263
Table 264
Table 265
Table 266
Table 267
Table 268
Table 269
Table 270
Table 271
Table 272
Table 273
Table 274
Table 275
Table 276
Table 277
Table 278
Table 279
Table 280
Table 281
Table 282
Table 283
Table 284
Table 285
Table 286
Table 287
Table 288
Table 289
Table 290
Fields in EGR0_ETH2_VLAN_TAG_RANGE_I_TAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
Fields in EGR0_ETH2_VLAN_TAG1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
Fields in EGR0_ETH2_VLAN_TAG2_I_TAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
Registers in EGR0_MPLS_NXT_COMPARATOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
Fields in EGR0_MPLS_NXT_COMPARATOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
Registers in EGR0_MPLS_FLOW_CFG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
Fields in EGR0_MPLS_FLOW_CONTROL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
Fields in EGR0_MPLS_LABEL_RANGE_LOWER_0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
Fields in EGR0_MPLS_LABEL_RANGE_UPPER_0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
Fields in EGR0_MPLS_LABEL_RANGE_LOWER_1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
Fields in EGR0_MPLS_LABEL_RANGE_UPPER_1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
Fields in EGR0_MPLS_LABEL_RANGE_LOWER_2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
Fields in EGR0_MPLS_LABEL_RANGE_UPPER_2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
Fields in EGR0_MPLS_LABEL_RANGE_LOWER_3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
Fields in EGR0_MPLS_LABEL_RANGE_UPPER_3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
Registers in EGR0_IP1_NXT_PROTOCOL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
Fields in EGR0_IP1_NXT_COMPARATOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
Fields in EGR0_IP1_MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
Fields in EGR0_IP1_PROT_MATCH_1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
Fields in EGR0_IP1_PROT_MATCH_2_UPPER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
Fields in EGR0_IP1_PROT_MATCH_2_LOWER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
Fields in EGR0_IP1_PROT_MASK_2_UPPER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
Fields in EGR0_IP1_PROT_MASK_2_LOWER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
Fields in EGR0_IP1_PROT_OFFSET_2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
Fields in EGR0_IP1_UDP_CHKSUM_CFG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
Fields in EGR0_IP1_FRAME_SIG_CFG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
Registers in EGR0_IP1_FLOW_CFG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
Fields in EGR0_IP1_FLOW_ENA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198
Fields in EGR0_IP1_FLOW_MATCH_UPPER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
Fields in EGR0_IP1_FLOW_MATCH_UPPER_MID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
Fields in EGR0_IP1_FLOW_MATCH_LOWER_MID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
Fields in EGR0_IP1_FLOW_MATCH_LOWER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
Fields in EGR0_IP1_FLOW_MASK_UPPER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
Fields in EGR0_IP1_FLOW_MASK_UPPER_MID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
Fields in EGR0_IP1_FLOW_MASK_LOWER_MID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
Fields in EGR0_IP1_FLOW_MASK_LOWER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
Registers in EGR0_IP2_NXT_PROTOCOL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201
Fields in EGR0_IP2_NXT_COMPARATOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201
Fields in EGR0_IP2_MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
Fields in EGR0_IP2_PROT_MATCH_1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
Fields in EGR0_IP2_PROT_MATCH_2_UPPER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
Fields in EGR0_IP2_PROT_MATCH_2_LOWER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
Fields in EGR0_IP2_PROT_MASK_2_UPPER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
Fields in EGR0_IP2_PROT_MASK_2_LOWER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
Fields in EGR0_IP2_PROT_OFFSET_2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
Fields in EGR0_IP2_UDP_CHKSUM_CFG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204
Fields in EGR0_IP2_FRAME_SIG_CFG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204
Registers in EGR0_IP2_FLOW_CFG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204
Fields in EGR0_IP2_FLOW_ENA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205
Fields in EGR0_IP2_FLOW_MATCH_UPPER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206
Fields in EGR0_IP2_FLOW_MATCH_UPPER_MID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206
Fields in EGR0_IP2_FLOW_MATCH_LOWER_MID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206
Fields in EGR0_IP2_FLOW_MATCH_LOWER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206
Fields in EGR0_IP2_FLOW_MASK_UPPER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
Fields in EGR0_IP2_FLOW_MASK_UPPER_MID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
Fields in EGR0_IP2_FLOW_MASK_LOWER_MID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
Fields in EGR0_IP2_FLOW_MASK_LOWER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
Registers in EGR0_PTP_FLOW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208
Fields in EGR0_PTP_FLOW_ENA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208
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Table 293
Table 294
Table 295
Table 296
Table 297
Table 298
Table 299
Table 300
Table 301
Table 302
Table 303
Table 304
Table 305
Table 306
Table 307
Table 308
Table 309
Table 310
Table 311
Table 312
Table 313
Table 314
Table 315
Table 316
Table 317
Table 318
Table 319
Table 320
Table 321
Table 322
Table 323
Table 324
Table 325
Table 326
Table 327
Table 328
Table 329
Table 330
Table 331
Table 332
Table 333
Table 334
Table 335
Table 336
Table 337
Table 338
Table 339
Table 340
Table 341
Table 342
Table 343
Table 344
Table 345
Table 346
Table 347
Table 348
Table 349
Fields in EGR0_PTP_FLOW_MATCH_UPPER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208
Fields in EGR0_PTP_FLOW_MATCH_LOWER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
Fields in EGR0_PTP_FLOW_MASK_UPPER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
Fields in EGR0_PTP_FLOW_MASK_LOWER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
Fields in EGR0_PTP_DOMAIN_RANGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
Fields in EGR0_PTP_ACTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210
Fields in EGR0_PTP_ACTION_2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
Fields in EGR0_PTP_ZERO_FIELD_CTL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
Registers in EGR0_PTP_IP_CHKSUM_CTL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212
Fields in EGR0_PTP_IP_CKSUM_SEL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212
Registers in EGR0_FRAME_SIG_CFG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212
Fields in EGR0_FSB_CFG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213
Fields in EGR0_FSB_MAP_REG_0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213
Fields in EGR0_FSB_MAP_REG_1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214
Fields in EGR0_FSB_MAP_REG_2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214
Fields in EGR0_FSB_MAP_REG_3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214
Register Groups in Ingress0 Ethernet Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214
Registers in INGR0_ETH1_NXT_PROTOCOL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
Fields in INGR0_ETH1_NXT_PROTOCOL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216
Fields in INGR0_ETH1_VLAN_TPID_CFG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216
Fields in INGR0_ETH1_TAG_MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216
Fields in INGR0_ETH1_ETYPE_MATCH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217
Registers in INGR0_ETH1_FLOW_CFG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217
Fields in INGR0_ETH1_FLOW_ENABLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217
Fields in INGR0_ETH1_MATCH_MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218
Fields in INGR0_ETH1_ADDR_MATCH_1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219
Fields in INGR0_ETH1_ADDR_MATCH_2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219
Fields in INGR0_ETH1_VLAN_TAG_RANGE_I_TAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219
Fields in INGR0_ETH1_VLAN_TAG1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220
Fields in INGR0_ETH1_VLAN_TAG2_I_TAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220
Registers in INGR0_ETH2_NXT_PROTOCOL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221
Fields in INGR0_ETH2_NXT_PROTOCOL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221
Fields in INGR0_ETH2_VLAN_TPID_CFG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221
Fields in INGR0_ETH2_ETYPE_MATCH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222
Registers in INGR0_ETH2_FLOW_CFG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222
Fields in INGR0_ETH2_FLOW_ENABLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222
Fields in INGR0_ETH2_MATCH_MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223
Fields in INGR0_ETH2_ADDR_MATCH_1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224
Fields in INGR0_ETH2_ADDR_MATCH_2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224
Fields in INGR0_ETH2_VLAN_TAG_RANGE_I_TAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224
Fields in INGR0_ETH2_VLAN_TAG1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225
Fields in INGR0_ETH2_VLAN_TAG2_I_TAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225
Registers in INGR0_MPLS_NXT_COMPARATOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225
Fields in INGR0_MPLS_NXT_COMPARATOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226
Registers in INGR0_MPLS_FLOW_CFG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226
Fields in INGR0_MPLS_FLOW_CONTROL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227
Fields in INGR0_MPLS_LABEL_RANGE_LOWER_0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227
Fields in INGR0_MPLS_LABEL_RANGE_UPPER_0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228
Fields in INGR0_MPLS_LABEL_RANGE_LOWER_1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228
Fields in INGR0_MPLS_LABEL_RANGE_UPPER_1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228
Fields in INGR0_MPLS_LABEL_RANGE_LOWER_2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228
Fields in INGR0_MPLS_LABEL_RANGE_UPPER_2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229
Fields in INGR0_MPLS_LABEL_RANGE_LOWER_3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229
Fields in INGR0_MPLS_LABEL_RANGE_UPPER_3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229
Registers in INGR0_IP1_NXT_PROTOCOL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229
Fields in INGR0_IP1_NXT_COMPARATOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230
Fields in INGR0_IP1_MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230
Fields in INGR0_IP1_PROT_MATCH_1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231
Fields in INGR0_IP1_PROT_MATCH_2_UPPER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231
VMDS-10510 VSC8574-02 Datasheet Revision 4.2
xvii
Table 350
Table 351
Table 352
Table 353
Table 354
Table 355
Table 356
Table 357
Table 358
Table 359
Table 360
Table 361
Table 362
Table 363
Table 364
Table 365
Table 366
Table 367
Table 368
Table 369
Table 370
Table 371
Table 372
Table 373
Table 374
Table 375
Table 376
Table 377
Table 378
Table 379
Table 380
Table 381
Table 382
Table 383
Table 384
Table 385
Table 386
Table 387
Table 388
Table 389
Table 390
Table 391
Table 392
Table 393
Table 394
Table 395
Table 396
Table 397
Table 398
Table 399
Table 400
Table 401
Table 402
Table 403
Table 404
Table 405
Table 406
Table 407
Table 408
Fields in INGR0_IP1_PROT_MATCH_2_LOWER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231
Fields in INGR0_IP1_PROT_MASK_2_UPPER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232
Fields in INGR0_IP1_PROT_MASK_2_LOWER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232
Fields in INGR0_IP1_PROT_OFFSET_2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232
Fields in INGR0_IP1_UDP_CHKSUM_CFG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233
Registers in INGR0_IP1_FLOW_CFG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233
Fields in INGR0_IP1_FLOW_ENA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234
Fields in INGR0_IP1_FLOW_MATCH_UPPER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234
Fields in INGR0_IP1_FLOW_MATCH_UPPER_MID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235
Fields in INGR0_IP1_FLOW_MATCH_LOWER_MID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235
Fields in INGR0_IP1_FLOW_MATCH_LOWER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235
Fields in INGR0_IP1_FLOW_MASK_UPPER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235
Fields in INGR0_IP1_FLOW_MASK_UPPER_MID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236
Fields in INGR0_IP1_FLOW_MASK_LOWER_MID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236
Fields in INGR0_IP1_FLOW_MASK_LOWER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236
Registers in INGR0_IP2_NXT_PROTOCOL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236
Fields in INGR0_IP2_NXT_COMPARATOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237
Fields in INGR0_IP2_MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237
Fields in INGR0_IP2_PROT_MATCH_1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238
Fields in INGR0_IP2_PROT_MATCH_2_UPPER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238
Fields in INGR0_IP2_PROT_MATCH_2_LOWER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238
Fields in INGR0_IP2_PROT_MASK_2_UPPER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239
Fields in INGR0_IP2_PROT_MASK_2_LOWER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239
Fields in INGR0_IP2_PROT_OFFSET_2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239
Fields in INGR0_IP2_UDP_CHKSUM_CFG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240
Registers in INGR0_IP2_FLOW_CFG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240
Fields in INGR0_IP2_FLOW_ENA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241
Fields in INGR0_IP2_FLOW_MATCH_UPPER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241
Fields in INGR0_IP2_FLOW_MATCH_UPPER_MID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242
Fields in INGR0_IP2_FLOW_MATCH_LOWER_MID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242
Fields in INGR0_IP2_FLOW_MATCH_LOWER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242
Fields in INGR0_IP2_FLOW_MASK_UPPER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243
Fields in INGR0_IP2_FLOW_MASK_UPPER_MID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243
Fields in INGR0_IP2_FLOW_MASK_LOWER_MID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243
Fields in INGR0_IP2_FLOW_MASK_LOWER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244
Registers in INGR0_PTP_FLOW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244
Fields in INGR0_PTP_FLOW_ENA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244
Fields in INGR0_PTP_FLOW_MATCH_UPPER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245
Fields in INGR0_PTP_FLOW_MATCH_LOWER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245
Fields in INGR0_PTP_FLOW_MASK_UPPER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245
Fields in INGR0_PTP_FLOW_MASK_LOWER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245
Fields in INGR0_PTP_DOMAIN_RANGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246
Fields in INGR0_PTP_ACTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246
Fields in INGR0_PTP_ACTION_2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247
Fields in INGR0_PTP_ZERO_FIELD_CTL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248
Registers in INGR0_PTP_IP_CHKSUM_CTL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248
Fields in INGR0_PTP_IP_CKSUM_SEL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248
Register Groups in Egress1 Ethernet Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248
Registers in EGR1_ETH1_NXT_PROTOCOL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249
Fields in EGR1_ETH1_NXT_PROTOCOL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250
Fields in EGR1_ETH1_VLAN_TPID_CFG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250
Fields in EGR1_ETH1_TAG_MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250
Fields in EGR1_ETH1_ETYPE_MATCH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251
Registers in EGR1_ETH1_FLOW_CFG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251
Fields in EGR1_ETH1_FLOW_ENABLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251
Fields in EGR1_ETH1_MATCH_MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252
Fields in EGR1_ETH1_ADDR_MATCH_1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253
Fields in EGR1_ETH1_ADDR_MATCH_2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253
Fields in EGR1_ETH1_VLAN_TAG_RANGE_I_TAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253
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Table 409
Table 410
Table 411
Table 412
Table 413
Table 414
Table 415
Table 416
Table 417
Table 418
Table 419
Table 420
Table 421
Table 422
Table 423
Table 424
Table 425
Table 426
Table 427
Table 428
Table 429
Table 430
Table 431
Table 432
Table 433
Table 434
Table 435
Table 436
Table 437
Table 438
Table 439
Table 440
Table 441
Table 442
Table 443
Table 444
Table 445
Table 446
Table 447
Table 448
Table 449
Table 450
Table 451
Table 452
Table 453
Table 454
Table 455
Table 456
Table 457
Table 458
Table 459
Table 460
Table 461
Table 462
Table 463
Table 464
Table 465
Table 466
Table 467
Fields in EGR1_ETH1_VLAN_TAG1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254
Fields in EGR1_ETH1_VLAN_TAG2_I_TAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254
Registers in EGR1_ETH2_NXT_PROTOCOL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255
Fields in EGR1_ETH2_NXT_PROTOCOL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255
Fields in EGR1_ETH2_VLAN_TPID_CFG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255
Fields in EGR1_ETH2_ETYPE_MATCH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256
Registers in EGR1_ETH2_FLOW_CFG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256
Fields in EGR1_ETH2_FLOW_ENABLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256
Fields in EGR1_ETH2_MATCH_MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257
Fields in EGR1_ETH2_ADDR_MATCH_1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258
Fields in EGR1_ETH2_ADDR_MATCH_2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258
Fields in EGR1_ETH2_VLAN_TAG_RANGE_I_TAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258
Fields in EGR1_ETH2_VLAN_TAG1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259
Fields in EGR1_ETH2_VLAN_TAG2_I_TAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259
Registers in EGR1_MPLS_NXT_COMPARATOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259
Fields in EGR1_MPLS_NXT_COMPARATOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259
Registers in EGR1_MPLS_FLOW_CFG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260
Fields in EGR1_MPLS_FLOW_CONTROL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261
Fields in EGR1_MPLS_LABEL_RANGE_LOWER_0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261
Fields in EGR1_MPLS_LABEL_RANGE_UPPER_0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262
Fields in EGR1_MPLS_LABEL_RANGE_LOWER_1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262
Fields in EGR1_MPLS_LABEL_RANGE_UPPER_1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262
Fields in EGR1_MPLS_LABEL_RANGE_LOWER_2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262
Fields in EGR1_MPLS_LABEL_RANGE_UPPER_2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263
Fields in EGR1_MPLS_LABEL_RANGE_LOWER_3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263
Fields in EGR1_MPLS_LABEL_RANGE_UPPER_3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263
Registers in EGR1_IP1_NXT_PROTOCOL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263
Fields in EGR1_IP1_NXT_COMPARATOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264
Fields in EGR1_IP1_MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264
Fields in EGR1_IP1_PROT_MATCH_1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265
Fields in EGR1_IP1_PROT_MATCH_2_UPPER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265
Fields in EGR1_IP1_PROT_MATCH_2_LOWER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265
Fields in EGR1_IP1_PROT_MASK_2_UPPER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266
Fields in EGR1_IP1_PROT_MASK_2_LOWER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266
Fields in EGR1_IP1_PROT_OFFSET_2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266
Fields in EGR1_IP1_UDP_CHKSUM_CFG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267
Fields in EGR1_IP1_FRAME_SIG_CFG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267
Registers in EGR1_IP1_FLOW_CFG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267
Fields in EGR1_IP1_FLOW_ENA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268
Fields in EGR1_IP1_FLOW_MATCH_UPPER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269
Fields in EGR1_IP1_FLOW_MATCH_UPPER_MID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269
Fields in EGR1_IP1_FLOW_MATCH_LOWER_MID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269
Fields in EGR1_IP1_FLOW_MATCH_LOWER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269
Fields in EGR1_IP1_FLOW_MASK_UPPER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270
Fields in EGR1_IP1_FLOW_MASK_UPPER_MID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270
Fields in EGR1_IP1_FLOW_MASK_LOWER_MID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270
Fields in EGR1_IP1_FLOW_MASK_LOWER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270
Registers in EGR1_IP2_NXT_PROTOCOL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271
Fields in EGR1_IP2_NXT_COMPARATOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271
Fields in EGR1_IP2_MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272
Fields in EGR1_IP2_PROT_MATCH_1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272
Fields in EGR1_IP2_PROT_MATCH_2_UPPER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272
Fields in EGR1_IP2_PROT_MATCH_2_LOWER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272
Fields in EGR1_IP2_PROT_MASK_2_UPPER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273
Fields in EGR1_IP2_PROT_MASK_2_LOWER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273
Fields in EGR1_IP2_PROT_OFFSET_2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273
Fields in EGR1_IP2_UDP_CHKSUM_CFG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274
Fields in EGR1_IP2_FRAME_SIG_CFG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274
Registers in EGR1_IP2_FLOW_CFG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274
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Table 469
Table 470
Table 471
Table 472
Table 473
Table 474
Table 475
Table 476
Table 477
Table 478
Table 479
Table 480
Table 481
Table 482
Table 483
Table 484
Table 485
Table 486
Table 487
Table 488
Table 489
Table 490
Table 491
Table 492
Table 493
Table 494
Table 495
Table 496
Table 497
Table 498
Table 499
Table 500
Table 501
Table 502
Table 503
Table 504
Table 505
Table 506
Table 507
Table 508
Table 509
Table 510
Table 511
Table 512
Table 513
Table 514
Table 515
Table 516
Table 517
Table 518
Table 519
Table 520
Table 521
Table 522
Table 523
Table 524
Table 525
Table 526
Fields in EGR1_IP2_FLOW_ENA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275
Fields in EGR1_IP2_FLOW_MATCH_UPPER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276
Fields in EGR1_IP2_FLOW_MATCH_UPPER_MID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276
Fields in EGR1_IP2_FLOW_MATCH_LOWER_MID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276
Fields in EGR1_IP2_FLOW_MATCH_LOWER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276
Fields in EGR1_IP2_FLOW_MASK_UPPER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277
Fields in EGR1_IP2_FLOW_MASK_UPPER_MID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277
Fields in EGR1_IP2_FLOW_MASK_LOWER_MID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277
Fields in EGR1_IP2_FLOW_MASK_LOWER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277
Registers in EGR1_PTP_FLOW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278
Fields in EGR1_PTP_FLOW_ENA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278
Fields in EGR1_PTP_FLOW_MATCH_UPPER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278
Fields in EGR1_PTP_FLOW_MATCH_LOWER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279
Fields in EGR1_PTP_FLOW_MASK_UPPER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279
Fields in EGR1_PTP_FLOW_MASK_LOWER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279
Fields in EGR1_PTP_DOMAIN_RANGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279
Fields in EGR1_PTP_ACTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280
Fields in EGR1_PTP_ACTION_2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281
Fields in EGR1_PTP_ZERO_FIELD_CTL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281
Registers in EGR1_PTP_IP_CHKSUM_CTL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282
Fields in EGR1_PTP_IP_CKSUM_SEL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282
Registers in EGR1_FRAME_SIG_CFG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282
Fields in EGR1_FSB_CFG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283
Fields in EGR1_FSB_MAP_REG_0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283
Fields in EGR1_FSB_MAP_REG_1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284
Fields in EGR1_FSB_MAP_REG_2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284
Fields in EGR1_FSB_MAP_REG_3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284
Register Groups in Ingress1 Ethernet Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284
Registers in INGR1_ETH1_NXT_PROTOCOL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285
Fields in INGR1_ETH1_NXT_PROTOCOL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286
Fields in INGR1_ETH1_VLAN_TPID_CFG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286
Fields in INGR1_ETH1_TAG_MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286
Fields in INGR1_ETH1_ETYPE_MATCH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287
Registers in INGR1_ETH1_FLOW_CFG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287
Fields in INGR1_ETH1_FLOW_ENABLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287
Fields in INGR1_ETH1_MATCH_MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288
Fields in INGR1_ETH1_ADDR_MATCH_1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289
Fields in INGR1_ETH1_ADDR_MATCH_2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289
Fields in INGR1_ETH1_VLAN_TAG_RANGE_I_TAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289
Fields in INGR1_ETH1_VLAN_TAG1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290
Fields in INGR1_ETH1_VLAN_TAG2_I_TAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290
Registers in INGR1_ETH2_NXT_PROTOCOL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291
Fields in INGR1_ETH2_NXT_PROTOCOL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291
Fields in INGR1_ETH2_VLAN_TPID_CFG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291
Fields in INGR1_ETH2_ETYPE_MATCH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292
Registers in INGR1_ETH2_FLOW_CFG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292
Fields in INGR1_ETH2_FLOW_ENABLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292
Fields in INGR1_ETH2_MATCH_MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293
Fields in INGR1_ETH2_ADDR_MATCH_1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294
Fields in INGR1_ETH2_ADDR_MATCH_2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294
Fields in INGR1_ETH2_VLAN_TAG_RANGE_I_TAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294
Fields in INGR1_ETH2_VLAN_TAG1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295
Fields in INGR1_ETH2_VLAN_TAG2_I_TAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295
Registers in INGR1_MPLS_NXT_COMPARATOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295
Fields in INGR1_MPLS_NXT_COMPARATOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296
Registers in INGR1_MPLS_FLOW_CFG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296
Fields in INGR1_MPLS_FLOW_CONTROL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297
Fields in INGR1_MPLS_LABEL_RANGE_LOWER_0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297
Fields in INGR1_MPLS_LABEL_RANGE_UPPER_0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 298
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Table 531
Table 532
Table 533
Table 534
Table 535
Table 536
Table 537
Table 538
Table 539
Table 540
Table 541
Table 542
Table 543
Table 544
Table 545
Table 546
Table 547
Table 548
Table 549
Table 550
Table 551
Table 552
Table 553
Table 554
Table 555
Table 556
Table 557
Table 558
Table 559
Table 560
Table 561
Table 562
Table 563
Table 564
Table 565
Table 566
Table 567
Table 568
Table 569
Table 570
Table 571
Table 572
Table 573
Table 574
Table 575
Table 576
Table 577
Table 578
Table 579
Table 580
Table 581
Table 582
Table 583
Table 584
Table 585
Fields in INGR1_MPLS_LABEL_RANGE_LOWER_1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 298
Fields in INGR1_MPLS_LABEL_RANGE_UPPER_1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 298
Fields in INGR1_MPLS_LABEL_RANGE_LOWER_2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 298
Fields in INGR1_MPLS_LABEL_RANGE_UPPER_2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299
Fields in INGR1_MPLS_LABEL_RANGE_LOWER_3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299
Fields in INGR1_MPLS_LABEL_RANGE_UPPER_3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299
Registers in INGR1_IP1_NXT_PROTOCOL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299
Fields in INGR1_IP1_NXT_COMPARATOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300
Fields in INGR1_IP1_MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300
Fields in INGR1_IP1_PROT_MATCH_1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301
Fields in INGR1_IP1_PROT_MATCH_2_UPPER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301
Fields in INGR1_IP1_PROT_MATCH_2_LOWER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301
Fields in INGR1_IP1_PROT_MASK_2_UPPER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302
Fields in INGR1_IP1_PROT_MASK_2_LOWER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302
Fields in INGR1_IP1_PROT_OFFSET_2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302
Fields in INGR1_IP1_UDP_CHKSUM_CFG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303
Registers in INGR1_IP1_FLOW_CFG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303
Fields in INGR1_IP1_FLOW_ENA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 304
Fields in INGR1_IP1_FLOW_MATCH_UPPER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 304
Fields in INGR1_IP1_FLOW_MATCH_UPPER_MID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305
Fields in INGR1_IP1_FLOW_MATCH_LOWER_MID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305
Fields in INGR1_IP1_FLOW_MATCH_LOWER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305
Fields in INGR1_IP1_FLOW_MASK_UPPER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305
Fields in INGR1_IP1_FLOW_MASK_UPPER_MID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306
Fields in INGR1_IP1_FLOW_MASK_LOWER_MID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306
Fields in INGR1_IP1_FLOW_MASK_LOWER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306
Registers in INGR1_IP2_NXT_PROTOCOL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306
Fields in INGR1_IP2_NXT_COMPARATOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 307
Fields in INGR1_IP2_MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 307
Fields in INGR1_IP2_PROT_MATCH_1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308
Fields in INGR1_IP2_PROT_MATCH_2_UPPER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308
Fields in INGR1_IP2_PROT_MATCH_2_LOWER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308
Fields in INGR1_IP2_PROT_MASK_2_UPPER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 309
Fields in INGR1_IP2_PROT_MASK_2_LOWER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 309
Fields in INGR1_IP2_PROT_OFFSET_2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 309
Fields in INGR1_IP2_UDP_CHKSUM_CFG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 310
Registers in INGR1_IP2_FLOW_CFG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 310
Fields in INGR1_IP2_FLOW_ENA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 311
Fields in INGR1_IP2_FLOW_MATCH_UPPER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 311
Fields in INGR1_IP2_FLOW_MATCH_UPPER_MID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 312
Fields in INGR1_IP2_FLOW_MATCH_LOWER_MID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 312
Fields in INGR1_IP2_FLOW_MATCH_LOWER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 312
Fields in INGR1_IP2_FLOW_MASK_UPPER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313
Fields in INGR1_IP2_FLOW_MASK_UPPER_MID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313
Fields in INGR1_IP2_FLOW_MASK_LOWER_MID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313
Fields in INGR1_IP2_FLOW_MASK_LOWER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314
Registers in INGR1_PTP_FLOW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314
Fields in INGR1_PTP_FLOW_ENA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314
Fields in INGR1_PTP_FLOW_MATCH_UPPER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 315
Fields in INGR1_PTP_FLOW_MATCH_LOWER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 315
Fields in INGR1_PTP_FLOW_MASK_UPPER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 315
Fields in INGR1_PTP_FLOW_MASK_LOWER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 315
Fields in INGR1_PTP_DOMAIN_RANGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 316
Fields in INGR1_PTP_ACTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 316
Fields in INGR1_PTP_ACTION_2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 317
Fields in INGR1_PTP_ZERO_FIELD_CTL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 318
Registers in INGR1_PTP_IP_CHKSUM_CTL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 318
Fields in INGR1_PTP_IP_CKSUM_SEL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 318
Register Groups in Egress2 Ethernet Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 318
VMDS-10510 VSC8574-02 Datasheet Revision 4.2
xxi
Table 586
Table 587
Table 588
Table 589
Table 590
Table 591
Table 592
Table 593
Table 594
Table 595
Table 596
Table 597
Table 598
Table 599
Table 600
Table 601
Table 602
Table 603
Table 604
Table 605
Table 606
Table 607
Table 608
Table 609
Table 610
Table 611
Table 612
Table 613
Table 614
Table 615
Table 616
Table 617
Table 618
Table 619
Table 620
Table 621
Table 622
Table 623
Table 624
Table 625
Table 626
Table 627
Table 628
Table 629
Table 630
Table 631
Table 632
Table 633
Table 634
Table 635
Table 636
Table 637
Table 638
Table 639
Table 640
Table 641
Table 642
Table 643
Table 644
Registers in EGR2_ETH1_NXT_PROTOCOL_A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 319
Fields in EGR2_ETH1_NXT_PROTOCOL_A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 320
Fields in EGR2_ETH1_VLAN_TPID_CFG_A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 320
Fields in EGR2_ETH1_TAG_MODE_A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 320
Fields in EGR2_ETH1_ETYPE_MATCH_A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 321
Registers in EGR2_ETH1_NXT_PROTOCOL_B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 321
Fields in EGR2_ETH1_NXT_PROTOCOL_B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 321
Fields in EGR2_ETH1_VLAN_TPID_CFG_B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 322
Fields in EGR2_ETH1_TAG_MODE_B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 322
Fields in EGR2_ETH1_ETYPE_MATCH_B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 322
Registers in EGR2_ETH1_FLOW_CFG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 323
Fields in EGR2_ETH1_FLOW_ENABLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 323
Fields in EGR2_ETH1_MATCH_MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 324
Fields in EGR2_ETH1_ADDR_MATCH_1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 325
Fields in EGR2_ETH1_ADDR_MATCH_2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 325
Fields in EGR2_ETH1_VLAN_TAG_RANGE_I_TAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 325
Fields in EGR2_ETH1_VLAN_TAG1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 326
Fields in EGR2_ETH1_VLAN_TAG2_I_TAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 326
Registers in EGR2_ETH2_NXT_PROTOCOL_A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 326
Fields in EGR2_ETH2_NXT_PROTOCOL_A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 327
Fields in EGR2_ETH2_VLAN_TPID_CFG_A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 327
Fields in EGR2_ETH2_ETYPE_MATCH_A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 327
Registers in EGR2_ETH2_FLOW_CFG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 328
Fields in EGR2_ETH2_FLOW_ENABLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 328
Fields in EGR2_ETH2_MATCH_MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 329
Fields in EGR2_ETH2_ADDR_MATCH_1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 329
Fields in EGR2_ETH2_ADDR_MATCH_2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 330
Fields in EGR2_ETH2_VLAN_TAG_RANGE_I_TAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 330
Fields in EGR2_ETH2_VLAN_TAG1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 330
Fields in EGR2_ETH2_VLAN_TAG2_I_TAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 331
Registers in EGR2_MPLS_NXT_COMPARATOR_A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 331
Fields in EGR2_MPLS_NXT_COMPARATOR_A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 331
Registers in EGR2_MPLS_FLOW_CFG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 332
Fields in EGR2_MPLS_FLOW_CONTROL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 332
Fields in EGR2_MPLS_LABEL_RANGE_LOWER_0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 333
Fields in EGR2_MPLS_LABEL_RANGE_UPPER_0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 333
Fields in EGR2_MPLS_LABEL_RANGE_LOWER_1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 334
Fields in EGR2_MPLS_LABEL_RANGE_UPPER_1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 334
Fields in EGR2_MPLS_LABEL_RANGE_LOWER_2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 334
Fields in EGR2_MPLS_LABEL_RANGE_UPPER_2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 334
Fields in EGR2_MPLS_LABEL_RANGE_LOWER_3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 335
Fields in EGR2_MPLS_LABEL_RANGE_UPPER_3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 335
Registers in EGR2_PTP_FLOW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 335
Fields in EGR2_PTP_FLOW_ENA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 336
Fields in EGR2_PTP_FLOW_MATCH_UPPER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 336
Fields in EGR2_PTP_FLOW_MATCH_LOWER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 336
Fields in EGR2_PTP_FLOW_MASK_UPPER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 337
Fields in EGR2_PTP_FLOW_MASK_LOWER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 337
Fields in EGR2_PTP_DOMAIN_RANGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 337
Fields in EGR2_PTP_ACTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 337
Fields in EGR2_PTP_ACTION_2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 338
Fields in EGR2_PTP_ZERO_FIELD_CTL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 339
Register Groups in Ingress2 Ethernet Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 339
Registers in INGR2_ETH1_NXT_PROTOCOL_A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 340
Fields in INGR2_ETH1_NXT_PROTOCOL_A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 340
Fields in INGR2_ETH1_VLAN_TPID_CFG_A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 340
Fields in INGR2_ETH1_TAG_MODE_A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 341
Fields in INGR2_ETH1_ETYPE_MATCH_A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 341
Registers in INGR2_ETH1_NXT_PROTOCOL_B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 341
VMDS-10510 VSC8574-02 Datasheet Revision 4.2
xxii
Table 645
Table 646
Table 647
Table 648
Table 649
Table 650
Table 651
Table 652
Table 653
Table 654
Table 655
Table 656
Table 657
Table 658
Table 659
Table 660
Table 661
Table 662
Table 663
Table 664
Table 665
Table 666
Table 667
Table 668
Table 669
Table 670
Table 671
Table 672
Table 673
Table 674
Table 675
Table 676
Table 677
Table 678
Table 679
Table 680
Table 681
Table 682
Table 683
Table 684
Table 685
Table 686
Table 687
Table 688
Table 689
Table 690
Table 691
Table 692
Table 693
Table 694
Table 695
Table 696
Table 697
Table 698
Table 699
Table 700
Table 701
Table 702
Table 703
Fields in INGR2_ETH1_NXT_PROTOCOL_B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 342
Fields in INGR2_ETH1_VLAN_TPID_CFG_B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 342
Fields in INGR2_ETH1_TAG_MODE_B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 342
Fields in INGR2_ETH1_ETYPE_MATCH_B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 343
Registers in INGR2_ETH1_FLOW_CFG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 343
Fields in INGR2_ETH1_FLOW_ENABLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 344
Fields in INGR2_ETH1_MATCH_MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 344
Fields in INGR2_ETH1_ADDR_MATCH_1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 345
Fields in INGR2_ETH1_ADDR_MATCH_2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 345
Fields in INGR2_ETH1_VLAN_TAG_RANGE_I_TAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 346
Fields in INGR2_ETH1_VLAN_TAG1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 346
Fields in INGR2_ETH1_VLAN_TAG2_I_TAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 347
Registers in INGR2_ETH2_NXT_PROTOCOL_A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 347
Fields in INGR2_ETH2_NXT_PROTOCOL_A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 347
Fields in INGR2_ETH2_VLAN_TPID_CFG_A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 348
Fields in INGR2_ETH2_ETYPE_MATCH_A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 348
Registers in INGR2_ETH2_FLOW_CFG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 348
Fields in INGR2_ETH2_FLOW_ENABLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 349
Fields in INGR2_ETH2_MATCH_MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 349
Fields in INGR2_ETH2_ADDR_MATCH_1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 350
Fields in INGR2_ETH2_ADDR_MATCH_2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 350
Fields in INGR2_ETH2_VLAN_TAG_RANGE_I_TAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 351
Fields in INGR2_ETH2_VLAN_TAG1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 351
Fields in INGR2_ETH2_VLAN_TAG2_I_TAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 351
Registers in INGR2_MPLS_NXT_COMPARATOR_A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 352
Fields in INGR2_MPLS_NXT_COMPARATOR_A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 352
Registers in INGR2_MPLS_FLOW_CFG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 352
Fields in INGR2_MPLS_FLOW_CONTROL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 353
Fields in INGR2_MPLS_LABEL_RANGE_LOWER_0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 354
Fields in INGR2_MPLS_LABEL_RANGE_UPPER_0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 354
Fields in INGR2_MPLS_LABEL_RANGE_LOWER_1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 354
Fields in INGR2_MPLS_LABEL_RANGE_UPPER_1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 354
Fields in INGR2_MPLS_LABEL_RANGE_LOWER_2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 355
Fields in INGR2_MPLS_LABEL_RANGE_UPPER_2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 355
Fields in INGR2_MPLS_LABEL_RANGE_LOWER_3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 355
Fields in INGR2_MPLS_LABEL_RANGE_UPPER_3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 355
Registers in INGR2_PTP_FLOW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 356
Fields in INGR2_PTP_FLOW_ENA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 356
Fields in INGR2_PTP_FLOW_MATCH_UPPER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 357
Fields in INGR2_PTP_FLOW_MATCH_LOWER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 357
Fields in INGR2_PTP_FLOW_MASK_UPPER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 357
Fields in INGR2_PTP_FLOW_MASK_LOWER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 357
Fields in INGR2_PTP_DOMAIN_RANGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 358
Fields in INGR2_PTP_ACTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 358
Fields in INGR2_PTP_ACTION_2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 359
Fields in INGR2_PTP_ZERO_FIELD_CTL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 360
VDD25 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 361
LED and GPIO Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 361
Internal Pull-Up or Pull-Down Resistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 361
Reference Clock DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 362
1588 Reference Clock DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 362
SerDes Driver DC Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 362
SerDes Receiver DC Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 364
Enhanced SerDes Driver DC Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 364
Enhanced SerDes Receiver DC Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 365
Current Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 365
Thermal Diode Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 367
Reference Clock AC Characteristics for QSGMII 125 MHz Differential Clock . . . . . . . . . . . . . . . 367
Recovered Clock AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 368
VMDS-10510 VSC8574-02 Datasheet Revision 4.2
xxiii
Table 704
Table 705
Table 706
Table 707
Table 708
Table 709
Table 710
Table 711
Table 712
Table 713
Table 714
Table 715
Table 716
Table 717
Table 718
Table 719
Table 720
Table 721
Table 722
Table 723
Table 724
Table 725
Table 726
Table 727
Table 728
Table 729
Table 730
Table 731
Table 732
Table 733
Table 734
Table 735
Table 736
SerDes Outputs AC Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 369
SerDes Driver Jitter Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 369
SerDes Input AC Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 370
SerDes Receiver Jitter Tolerance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 370
Enhanced SerDes Outputs AC Specifications, SGMII Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 371
Enhanced SerDes Outputs AC Specifications, QSGMII Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 371
Enhanced SerDes Driver Jitter Characteristics, QSGMII Mode . . . . . . . . . . . . . . . . . . . . . . . . . . 371
Enhanced SerDes Input AC Specifications, SGMII Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 372
Enhanced SerDes Inputs AC Specifications, QSGMII Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 372
Enhanced SerDes Receiver Jitter Tolerance, QSGMII Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 372
Basic Serial LEDs AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 373
Enhanced Serial LEDs AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 373
JTAG Interface AC Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 374
Serial Management Interface AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 375
Reset Timing Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 376
1588 Timing Specifications AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 377
Serial Timestamp Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 377
Local Time Counter Load/Save Timing Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 378
Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 378
Stress Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 378
Pin Type Symbol Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 380
1588 Support Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 382
GPIO and 1588 Support Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 383
GPIO and SIGDET Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 383
JTAG Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 383
Miscellaneous Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 384
Power Supply Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 385
SerDes MAC Interface Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 385
SerDes Media Interface Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 386
SMI Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 386
Twisted Pair Interface Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 387
Thermal Resistances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 391
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 396
VMDS-10510 VSC8574-02 Datasheet Revision 4.2
xxiv
Revision History
1
Revision History
This section describes the changes that were implemented in this document. The changes are listed by
revision, starting with the most current publication.
1.1
Revision 4.2
Revision 4.2 was published in April 2019. The following is a summary of the changes in revision 4.2 of
this document.
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
1.2
The Block Diagram figure was updated. For more information, see Figure 4, page 5.
The IEEE 1588 Architecture figure was updated by removing reference to the pps functionality. For
more information, see Figure 26, page 25.
The IEEE 1588 Device Synchronization section was updated by removing reference to the pps
functionality. For more information, see IEEE 1588 Device Synchronization, page 42.
The Timestamp Update section was updated by removing reference to the pps functionality. For
more information, see Timestamp Update, page 42.
The Timestamp Update section was updated by removing reference to the pps functionality. For
more information, see Timestamp Update, page 42.
The Local Time Counter section was updated by removing reference to the PPS0 functionality and
the Local Time Counter Load/Save Timing figure. For more information, see Local Time Counter,
page 69.
The 1588_PPS_0/1 Mux Control section was deleted.
The Register Bits for GPIO Control and Status table was updated by removing reference to the pps
functionality. For more information, see Table 31, page 80.
The GPIO Control 2, Address 14G (0x0E) table was updated by removing reference to the pps
functionality. For more information, see Table 101, page 129.
The GPIO Input, Address 15G (0x0F) table was updated by removing reference to the pps
functionality. For more information, see Table 102, page 130.
The GPIO Output, Address 16G (0x10) table was updated by removing reference to the pps
functionality. For more information, see Table 103, page 131.
The GPIO Input/Output Configuration, Address 17G (0x11) table was updated by removing
reference to the pps functionality. For more information, see Table 104, page 131.
The Register Groups in IP_1588 table was updated by removing reference to the pps functionality.
For more information, see Table 122, page 142.
The Registers in IP_1588_LTC table was updated by removing reference to the pps functionality.
For more information, see Table 127, page 145.
The Fields in LTC_CTRL table was updated by removing reference to the pps functionality. For more
information, see Table 128, page 145.
The IP_1588:IP_1588_LTC:LTC_1PPS_WIDTH_ADJwas removed.
The IP_1588:MISC_CFG section was removed.
The diagrams have been updated by removing references to the pps functionality. For more
information, see Figure 91, page 381 and Figure 92, page 382.
The 1588 Support Pins table was updated by removing references to the pps functionality. For more
information, see Table 725, page 382.
The GPIO and 1588 Support Pins table was updated by removing references to the pps functionality.
For more information, see Table 726, page 383.
The GPIO and SIGDET Pins table was updated by removing references to the pps functionality. For
more information, see Table 727, page 383.
The 10BASE-T link recovery failures section was updated. For more information, see 10BASE-T link
recovery failures, page 392.
Revision 4.1
Revision 4.1 was published in May 2018. The following is a summary of the changes in revision 4.1 of
this document.
•
Configuration procedure steps were clarified. For more information, see Configuration, page 91.
VMDS-10510 VSC8574-02 Datasheet Revision 4.2
1
Revision History
•
•
•
1.3
The description of bit 10 was updated for register 0. For more information, see Table 39, page 95.
Serial timestamp interface characteristics were updated. For more information, see Table 720,
page 377.
Design considerations were updated. For more information, see Design Considerations, page 392.
Revision 4.0
Revision 4.0 was published in November 2017. The following is a summary of the changes in
revision 4.0 of this document.
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
1.4
A note was added about enhanced serial LED mode using the VDD LED drive state.
Details about LED pulsing were updated.
Information on enabling the serial clock was added.
Register bits were designated as “sticky” where appropriate.
A footnote was added about the fast link failure interrupt mask.
The default for the ring resiliency status bits 4:4 was updated from 00 to 11.
The default value for the MAC SerDes clause 37 advertised ability register was updated from
0x0000 to 0x01E0.
Footnotes regarding required register clears were added to the SIGDET/GPIO control register.
All GPIO input register bits marked as read-only and defaults updated.
Global interrupt status register defaults were added.
Register 30G changed from reserved to extended revision ID register.
Footnotes were added for INGR_BYPASS_ON and EGR_BYPASS_ON 1588 register bits.
Current consumption values were updated.
Some parameter names and conditions for recovered clock AC characteristics were updated.
Product SKUs in the package section were corrected to match the ordering information.
Design considerations were removed and new ones added to correctly reflect device functionality.
Revision 2.0
Revision 2.0 of this datasheet was published in September 2017. This was the first publication of the
document.
VMDS-10510 VSC8574-02 Datasheet Revision 4.2
2
Product Overview
2
Product Overview
The VSC8574-02 is a low-power, quad-port Gigabit Ethernet transceiver with four SerDes interfaces for
quad-port dual media capability. It also includes an integrated quad port two-wire serial multiplexer
(MUX) to control SFPs or PoE modules. It has a low electromagnetic interference (EMI) line driver, and
integrated line side termination resistors that conserve both power and printed circuit board (PCB) space.
The VSC8574-02 includes Microsemi’s IEEE 1588 timestamping solution with encapsulation support.
The device also includes dual recovered clock outputs to support Synchronous Ethernet applications.
Programmable clock squelch control is included to inhibit undesirable clocks from propagating and to
help prevent timing loops. The VSC8574-02 also supports a ring resiliency feature that allows a
1000BASE-T connected PHY port to switch between master and slave timing without having to interrupt
the 1000BASE-T link.
Using Microsemi’s EcoEthernet v2.0 PHY technology, the VSC8574-02 supports energy efficiency
features such as Energy Efficient Ethernet (EEE), ActiPHY link down power savings, and PerfectReach
that can adjust power based on the cable length. It also supports fully optimized power consumption in all
link speeds.
Microsemi's mixed signal and digital signal processing (DSP) architecture is a key operational feature of
the VSC8574-02, assuring robust performance even under less-than-favorable environmental
conditions. It supports both half-duplex and full-duplex 10BASE-T, 100BASE-TX, and 1000BASE-T
communication speeds over Category 5 (Cat5) unshielded twisted pair (UTP) cable at distances greater
than 100 m, displaying excellent tolerance to NEXT, FEXT, echo, and other types of ambient
environmental and system electronic noise. The device also supports four dual media ports that can
support up to four 100BASE-FX, 1000BASE-X fiber, and/or triple-speed copper SFPs.
The following illustrations show a high-level, general view of typical VSC8574-02 applications.
Figure 1 •
Dual Media Application Diagram
1x QSGMII,
4x SGMII, or
4x 1000BASE-X MAC
1x QSGMII,
4x SGMII MAC, or
4x 1000BASE-X MAC
Figure 2 •
1.0 V
2.5 V
4× RJ-45
and Magnetics
VSC8574-02
4 ports dual media
(fiber or copper)
QSGMII or SGMII
MAC interface
SerDes
SCL/SDA
4× SFPs
(fiber or copper)
Copper Transceiver Application Diagram
1x QSGMII,
4x SGMII, or
4x 1000BASE-X MAC
1x QSGMII,
4x SGMII MAC, or
4x 1000BASE-X MAC
1.0 V
2.5 V
VSC8574-02
4 ports copper media
QSGMII or SGMII
MAC interface
VMDS-10510 VSC8574-02 Datasheet Revision 4.2
4× RJ-45
and Magnetics
3
Product Overview
Figure 3 •
Fiber Media Transceiver Application Diagram
1x QSGMII,
4x SGMII, or
4x 1000BASE-X MAC
2.5 V
VSC8574-02
1x QSGMII,
4x SGMII MAC, or
4x 1000BASE-X MAC
2.1
1.0 V
4 ports fiber media
QSGMII or SGMII
MAC interface
4× 1000BASE-X SFP
or
4x 100BASE-FX SFP
Key Features
This section lists the main features and benefits of the VSC8574-02 device.
2.1.1
Low Power
•
•
•
•
2.1.2
Advanced Carrier Ethernet Support
•
•
•
•
•
•
2.1.3
Support for IEEE 1588-2008 timestamping with encapsulation support
Recovered clock outputs with programmable clock squelch control and fast link failure indication
( 12);
PhyWrite(, 31, 0);
The returned average absolute error is in units of 1/2,048 and can be found in the mse variable.
PhyWrite(, 31, 0x52b5);
PhyWrite(, 16, 0xa3c0);
PhyRead(, 16);
tmp17 = PhyRead(, 17);
tmp18 = PhyRead(, 18);
mseA = (tmp18 > 12);
mseB = tmp17 & 0x0fff;
PhyWrite(, 16, 0xa3c2);
PhyRead(, 16);
tmp17 = PhyRead(, 17);
tmp18 = PhyRead(, 18);
mseC = (tmp18 > 12);
mseD = tmp17 & 0x0fff;
PhyWrite(, 31, 0);
The returned average absolute error is in units of 1/2,048 and can be found in the mseA, mseB, mseC,
and mseD variables for each twisted pair.
3.19.8
JTAG Boundary Scan
The VSC8574-02 supports the test access port (TAP) and boundary scan architecture described in
IEEE 1149.1. The device includes an IEEE 1149.1-compliant test interface, referred to as a JTAG TAP
interface.
The JTAG boundary scan logic on the VSC8574-02, accessed using its TAP interface, consists of a
boundary scan register and other logic control blocks. The TAP controller includes all IEEE-required
signals (TMS, TCK, TDI, and TDO), in addition to the optional asynchronous reset signal TRST. The
following illustration shows the TAP and boundary scan architecture.
Important When JTAG is not in use, the TRST pin must be tied to ground with a pull-down resistor for
normal operation.
VMDS-10510 VSC8574-02 Datasheet Revision 4.2
87
Functional Descriptions
Figure 76 • Test Access Port and Boundary Scan Architecture
Boundary Scan
Register
Device Identification
Register
Bypass Register
Control
Instruction Register,
Instruction Decode
Control
TDI
TMS
NTRST
MUX,
DFF
TDO
Control
Test Access Port
Controller
Select
TDO Enable
TCK
After a TAP reset, the device identification register is serially connected between TDI and TDO by
default. The TAP instruction register is loaded either from a shift register when a new instruction is shifted
in, or, if there is no new instruction in the shift register, a default value of 6'b100000 (IDCODE) is loaded.
Using this method, there is always a valid code in the instruction register, and the problem of toggling
instruction bits during a shift is avoided. Unused codes are mapped to the BYPASS instruction.
3.19.9
JTAG Instruction Codes
The VSC8574-02 supports the following instruction codes:
Table 33 •
JTAG Instruction Codes
Instruction Code
Description
BYPASS
The bypass register contains a single shift-register stage and is
used to provide a minimum-length serial path (one TCK clock
period) between TDI and TDO to bypass the device when no test
operation is required.
CLAMP
Allows the state of the signals driven from the component pins to
be determined from the boundary scan register while the bypass
register is selected as the serial path between TDI and TDO.
While the CLAMP instruction is selected, the signals driven from
the component pins do not change.
EXTEST
Allows tests of the off-chip circuitry and board-level
interconnections by sampling input pins and loading data onto
output pins. Outputs are driven by the contents of the boundary
scan cells, which have to be updated with valid values, with the
PRELOAD instruction, prior to the EXTEST instruction.
VMDS-10510 VSC8574-02 Datasheet Revision 4.2
88
Functional Descriptions
JTAG Instruction Codes (continued)
Table 33 •
Instruction Code
Description
HIGHZ
Places the component in a state in which all of its system logic
outputs are placed in a high-impedance state. In this state, an incircuit test system can drive signals onto the connections normally
driven by a component output without incurring a risk of damage to
the component. This makes it possible to use a board where not
all of the components are compatible with the IEEE 1149.1
standard.
IDCODE
Provides the version number (bits 31:28), device family ID (bits
27:12), and the manufacturer identity (bits 11:1) to be serially read
from the device.
SAMPLE/PRELOA Allows a snapshot of inputs and outputs during normal system
D
operation to be taken and examined. It also allows data values to
be loaded into the boundary scan cells prior to the selection of
other boundary scan test instructions.
USERCODE
Provides the version number (bits 31:28), part number (bits 27:12),
and the manufacturer identity (bits 11:1) to be serially read from
the device.
The following tables provide information about the IDCODE and USERCODE binary values stored in the
device JTAG registers.
Table 34 •
IDCODE JTAG Device Identification Register Descriptions
Description
Device Version
Family ID
Manufacturing Identity
LSB
Bit field
31–28
27–12
11–1
0
Binary value
0000
1000 0101 0111 0100
000 0111 0100
1
Table 35 •
USERCODE JTAG Device Identification Register Descriptions
Description
Device Version
Model Number
Manufacturing Identity
LSB
Bit field
31–28
27–12
11–1
0
Binary value
0010
1000 0101 0000 0100
000 0111 0100
1
The following table provides information about the location and IEEE compliance of the JTAG instruction
codes used in the VSC8574-02. Instructions not explicitly listed in the table are reserved. For more
information about these IEEE specifications, visit the IEEE Web site at www.IEEE.org.
Table 36 •
JTAG Instruction Code IEEE Compliance
Instruction
Code
Selected Register
Register
Width
IEEE 1149.1
EXTEST
6'b000000
Boundary Scan
161
Mandatory
SAMPLE/PRELOA
D
6'b000001
Boundary Scan
161
Mandatory
IDCODE
6'b100000
Device Identification
32
Optional
USERCODE
6'b100101
Device Identification
32
Optional
CLAMP
6'b000010
Bypass Register
1
Optional
HIGHZ
6'b000101
Bypass Register
1
Optional
BYPASS
6'b111111
Bypass Register
1
Mandatory
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Functional Descriptions
3.19.10 Boundary Scan Register Cell Order
All inputs and outputs are observed in the boundary scan register cells. All outputs are additionally driven
by the contents of boundary scan register cells. Bidirectional pins have all three related boundary scan
register cells: input, output, and control.
The complete boundary scan cell order is available as a BSDL file format on the Microsemi Web site at
www.Microsemi.com.
3.20
100BASE-FX Halt Code Transmission and Reception
The VSC8574-02 device supports transmission and reception of halt code words in 100BASE-FX mode.
There are three separate scripts provided to initiate transmission of halt code words, stop transmission of
halt code words and detect reception of halt code words. Use the following scripts to implement each of
these functions:
Sending the HALT codeword:
PhyWrite(, 31, 0x52b5);
PhyWrite(, 16, 0xac82);
reg18 = PhyRead(, 18);
reg18 = (reg18 & 0xf0) | 0x0c;
PhyWrite(, 18, reg18);
PhyWrite(, 17, 0xe739);
PhyWrite(, 16, 0x8c82);
PhyWrite< , 16, 0xbe80);
reg17 = PhyRead(, 17);
reg18 = PhyRead(, 18);
reg17 = reg17 | 0x0040;
PhyWrite(, 18, reg18);
PhyWrite(, 17, reg17);
PhyWrite(, 16, 0x9e80);
PhyWrite(, 31, 0);
Stop sending the HALT codeword:
PhyWrite(, 31, 0x52b5);
PhyWrite< , 16, 0xbe80);
reg17 = PhyRead(, 17);
reg18 = PhyRead(, 18);
reg17 = reg17 & ~0x0040;
PhyWrite(, 18, reg18);
PhyWrite(, 17, reg17);
PhyWrite(, 16, 0x9e80);
PhyWrite(, 31, 0);
Detecting whether the HALT codeword is being sent by the link partner:
long patternset[5] = {
0xce739,
0xe739c,
0x739ce,
0x39ce7,
0x9ce73
};
Turning on the pattern checker:
PhyWrite(, 31, 0x52b5);
PhyWrite(, 16, 0xbe80);
reg18 = PhyRead(, 18);
reg17 = PhyRead(, 17);
reg17 = reg17 | 4;
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Functional Descriptions
PhyWrite(, 18, reg18);
PhyWrite(, 17, reg17);
PhyWrite(, 16, 0x9e80);
Sweeping through all five pattern shifts checking for a match:
for (i = 0, matchfailed = 1; i < 5 && matchfailed; ++i) {
PhyWrite(, 16, 0xac84);
reg18 = PhyRead(, 18);
reg18 = (reg18 & 0xf0) | (patternset[i] >> 16)
PhyWrite(, 18, reg18);
PhyWrite(, 17, patternset[i] & 0xffff);
PhyWrite(, 16, 0x8c84);
PhyWrite(, 16, 0xbe84); // Dummy read to clear latched mismatch
PhyWrite(, 16, 0xbe84); // Read pattern check failure status
matchfailed = PhyRead(, 17) & 1; // Extract pattern check failure status
}
Turning off the pattern checker:
PhyWrite(, 16, 0xbe80);
reg18 = PhyRead(, 18);
reg17 = PhyRead(, 17);
reg17 = reg17 & ~4;
PhyWrite(, 18, reg18);
PhyWrite(, 17, reg17);
PhyWrite(, 16, 0x9e80);
PhyWrite(, 31, 0);
HALT_codeword_detected =!matchfailed;
3.21
Configuration
The VSC8574-02 can be configured by setting internal memory registers using the management
interface. To configure the device, perform the following steps:
1.
2.
3.
4.
5.
6.
7.
COMA_MODE active, drive high (optional).
Apply power.
Apply RefCLK and IEEE 1588 reference clock.
Release reset, drive high. Power and clock must be stable before releasing reset.
Wait 120 ms minimum.
Apply patch from PHY_API (required for production released optional for board testing).
Configure register 19G for MAC mode (to access register 19G, register 31 must be 0x10). Read
register 19G. Set bits 15:14, MAC configuration as follows:
00: SGMII
01: QSGMII
10: Reserved
11: Reserved
Write new register 19G.
8. Configure register 18G for MAC on all 4 PHYs write:
SGMII: 0x80F0
QSGMII: 0x80E0
Read register 18G until bit 15 equals 0.
9. If Fiber Media on all 4 PHYs configure register 18G by writing:
Media 1000BASE-X: 0x8FC1
Media 100BASE-FX: 0x8FD1
10. If Fiber Media read register 18G till bit 15 equals 0.
11. Configure register 23 for MAC and Media mode (to access register 23, register 31 must be 0). Read
register 23. Set bits 10:8 as follows:
000: Copper
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Functional Descriptions
010: 1000BASE-X
011: 100BASE-FX
Write new register 23.
12. Software reset. Read register 0 (to access register 0, register 31 must be 0). Set bit 15 to 1.
Write new register 0.
13. Read register 0 until bit 15 equals 0.
14. Release the COMA_MODE pin, drive low (only necessary if COMA_MODE pin is driven high or
unconnected).
3.21.1
Initialization
The COMA_MODE pin provides an optional feature that may be used to control when the PHYs become
active. The typical usage is to keep the PHYs from becoming active before they have been fully
initialized. For more information, see Configuration, page 91. By not being active until after complete
initialization keeps links from going up and down. Alternatively the COMA_MODE pin may be connected
low (ground) and the PHYs will be fully active once out of reset.
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Registers
4
Registers
This section provides information about how to configure the VSC8574-02 using its internal memory
registers and the management interface. The registers marked reserved and factory test should not be
read or written to, because doing so may produce undesired effects.
The default value documented for registers is based on the value at reset; however, in some cases, that
value may change immediately after reset.
The access type for each register is shown using the following abbreviations:
•
•
•
•
•
•
RO: Read Only
ROCR: Read Only, Clear on Read
RO/LH: Read Only, Latch High
RO/LL: Read Only, Latch Low
R/W: Read and Write
RWSC: Read Write Self Clearing
The VSC8574-02 uses several different types of registers:
•
•
•
•
IEEE Clause 22 device registers with addresses from 0 to 31
Three pages of extended registers with addresses from 16E1–30E1, 16E2–30E2, and 16E3–30E3
General-purpose registers with addresses from 0G to 30G
IEEE Clause 45 devices registers accessible through the Clause 22 registers 13 and 14 to support
IEEE 802.3az-2010 energy efficient Ethernet registers
The following illustration shows the relationship between the device registers and their address spaces.
Figure 77 • Register Space Diagram
0
1
2
3
.
.
.
13
14
15
0G
1G
2G
3G
.
.
.
.
.
15G
Clause 45
Registers
IEEE 802.3
Standard
Registers
General Purpose
Registers
16
17
18
19
.
.
.
.
.
30
Main Registers
31
0x0000
16E1
17E1
18E1
19E1
.
.
.
.
.
30E1
Extended
Registers 1
0x0001
16E2
17E2
18E2
19E2
.
.
.
.
.
30E2
Extended
Registers 2
0x0002
16E3
17E3
18E3
19E3
.
.
.
.
.
30E3
Extended
Registers 3
0x0003
16G
17G
18G
19G
.
.
.
.
.
30G
16
17
18
0x0010
1588 Registers
0x1588
Reserved Registers—For main registers 16–31, extended registers 16E1–30E1, 16E2–30E2, 16E3–
30E3, and general purpose registers 0G–30G, any bits marked as Reserved should be processed as
read-only and their states as undefined.
Reserved Bits—In writing to registers with reserved bits, use a read-modify-then-write technique, where
the entire register is read but only the intended bits to be changed are modified. Reserved bits cannot be
changed and their read state cannot be considered static or unchanging.
4.1
Register and Bit Conventions
Registers are referred to by their address and bit number in decimal notation. A range of bits is indicated
with a colon. For example, a reference to address 26, bits 15 through 14 is shown as 26.15:14.
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Registers
A register with an E and a number attached (example 27E1) means it is a register contained within
extended register page number 1. A register with a G attached (example 13G) means it is a GPIO page
register.
Bit numbering follows the IEEE standard with bit 15 being the most significant bit and bit 0 being the least
significant bit.
4.2
IEEE 802.3 and Main Registers
In the VSC8574-02, the page space of the standard registers consists of the IEEE 802.3 standard
registers and the Microsemi standard registers. The following table lists the names of the registers
associated with the addresses as specified by IEEE 802.3.
Table 37 •
IEEE 802.3 Registers
Address
Name
0
Mode Control
1
Mode Status
2
PHY Identifier 1
3
PHY Identifier 2
4
Autonegotiation Advertisement
5
Autonegotiation Link Partner Ability
6
Autonegotiation Expansion
7
Autonegotiation Next-Page Transmit
8
Autonegotiation Link Partner Next-Page Receive
9
1000BASE-T Control
10
1000BASE-T Status
11–12
Reserved
13
Clause 45 Access Registers from IEEE 802.3
Table 22-6 and 22.24.3.11-12 and Annex 22D
14
Clause 45 Access Registers from IEEE 802.3
Table 22-6 and 22.24.3.11-12 and Annex 22D
15
1000BASE-T Status Extension 1
The following table lists the names of the registers in the main page space of the device. These registers
are accessible only when register address 31 is set to 0x0000.
Table 38 •
Main Registers
Address
Name
16
100BASE-TX status extension
17
1000BASE-T status extension 2
18
Bypass control
19
Error Counter 1
20
Error Counter 2
21
Error Counter 3
22
Extended control and status
23
Extended PHY control 1
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Registers
Table 38 •
4.2.1
Main Registers (continued)
Address
Name
24
Extended PHY control 2
25
Interrupt mask
26
Interrupt status
27
Reserved
28
Auxiliary control and status
29
LED mode select
30
LED behavior
31
Extended register page access
Mode Control
The device register at memory address 0 controls several aspects of VSC8574-02 functionality. The
following table shows the available bit settings in this register and what they control.
Table 39 •
Mode Control, Address 0 (0x00)
Bit
Name
Access Description
15
Software reset
R/W
Self-clearing. Restores all serial management 0
interface (SMI) registers to default state,
except for sticky and super-sticky bits.
1: Reset asserted.
0: Reset de-asserted. Wait [X] after setting this
bit to initiate another SMI register access.
14
Loopback
R/W
1: Loopback enabled.
0
0: Loopback disabled. When loop back is
enabled, the device functions at the current
speed setting and with the current duplex
mode setting (bits 6, 8, and 13 of this register).
13
Forced speed selection
LSB
R/W
Least significant bit. MSB is bit 6.
00: 10 Mbps.
01: 100 Mbps.
10: 1000 Mbps.
11: Reserved.
0
12
Autonegotiation enable
R/W
1: Autonegotiation enabled.
0: Autonegotiation disabled.
1
11
Power-down
R/W
1: Power-down enabled.
0
10
Isolate
R/W
1: Disconnect the MAC-side interface of the
device from the rest of the datapath. Traffic
entering the PHY from either the MAC-side or
media-side interface will terminate inside the
PHY.
0
9
Restart autonegotiation
R/W
Self-clearing bit.
0
1: Restart autonegotiation on media interface.
8
Duplex(1)
R/W
1: Full-duplex.
0: Half-duplex.
0
7
Collision test enable
R/W
1: Collision test enabled.
0
VMDS-10510 VSC8574-02 Datasheet Revision 4.2
Default
95
Registers
Table 39 •
Mode Control, Address 0 (0x00) (continued)
Bit
Name
Access Description
6
Forced speed selection
MSB
R/W
Most significant bit. LSB is bit 13.(2)
00: 10 Mbps.
01: 100 Mbps.
10: 1000 Mbps.
11: Reserved.
5
Unidirectional enable
R/W
When bit 0.12 = 1 or bit 0.8 = 0, this bit is
0
ignored. When bit 0.12 = 0 and bit 0.8 = 1, the
behavior is as follows:
1: Enable transmit from media independent
interface regardless of whether the PHY has
determined that a valid link has been
established.
0: Enable transmit from media independent
interface only when the PHY has determined
that a valid link has been established.
Note: This bit is only applicable in
100BASE-FX and 1000BASE-X
fiber media modes.
4:0
Reserved
1.
2.
4.2.2
Reserved.
Default
10
00000
Half-duplex is not supported when the 1588 unit is operating.
Before selecting the 1000 Mbps forced speed mode, manually configure the PHY as master or slave by
setting bit 11 in register 9 (1000BASE-T Control). Each time the link drops, the PHY needs to be powered
down manually to enable it to link up again using the master/slave setting specified in register 9.11.
Mode Status
The register at address 1 in the device main registers space allows you to read the currently enabled
mode setting. The following table shows possible readouts of this register.
Table 40 •
Mode Status, Address 1 (0x01)
Bit
Name
Access Description
Default
15
100BASE-T4 capability
RO
1: 100BASE-T4 capable.
0
14
100BASE-TX FDX capability RO
1: 100BASE-TX FDX capable.
1
13
100BASE-TX HDX capability RO
1: 100BASE-TX HDX capable.
1
12
10BASE-T FDX capability
RO
1: 10BASE-T FDX capable.
1
11
10BASE-T HDX capability
RO
1: 10BASE-T HDX capable.
1
10
100BASE-T2 FDX capability RO
1: 100BASE-T2 FDX capable.
0
9
100BASE-T2 HDX capability RO
1: 100BASE-T2 HDX capable.
0
8
Extended status enable
1: Extended status information present in
register 15.
1
RO
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Registers
Mode Status, Address 1 (0x01) (continued)
Table 40 •
Bit
Name
Access Description
Default
7
Unidirectional ability
RO
1: PHY able to transmit from media
independent interface regardless of
whether the PHY has determined that a
valid link has been established.
0: PHY able to transmit from media
independent interface only when the PHY
has determined that a valid link has been
established.
Note: This bit is only applicable to
100BASE-FX and
1000BASE-X fiber media
modes.
1
6
Preamble suppression
capability
RO
1: MF preamble can be suppressed.
0: MF required.
1
5
Autonegotiation complete
RO
1: Autonegotiation complete.
0
4
Remote fault
RO
Latches high.
1: Far-end fault detected.
0
3
Autonegotiation capability
RO
1: Autonegotiation capable.
1
2
Link status
RO
Latches low.
1: Link is up.
0
1
Jabber detect
RO
Latches high.
1: Jabber condition detected.
0
0
Extended capability
RO
1: Extended register capable.
1
4.2.3
Device Identification
All 16 bits in both register 2 and register 3 in the VSC8574-02 are used to provide information associated
with aspects of the device identification. The following tables list the expected readouts.
Identifier 1, Address 2 (0x02)
Table 41 •
Bit
Name
Access Description
Default
15:0
Organizationally unique identifier
(OUI)
RO
0×0007
Table 42 •
OUI most significant bits (3:18)
Identifier 2, Address 3 (0x03)
Bit
Name
Access Description
Default
15:10
OUI
RO
OUI least significant bits (19:24)
000001
9:4
Microsemi model
number
RO
VSC8574-02 (0xA)
001010
3:0
Device revision number
RO
See register 30G for the extended 0010
revision identification of this
device.
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Registers
4.2.4
Autonegotiation Advertisement
The bits in address 4 in the main registers space control the VSC8574-02 ability to notify other devices of
the status of its autonegotiation feature. The following table shows the available settings and readouts.
Device Autonegotiation Advertisement, Address 4 (0x04)
Table 43 •
Bit
Name
Access Description
Default
15
Next page transmission request
R/W
1: Request enabled
0
14
Reserved
RO
Reserved
0
13
Transmit remote fault
R/W
1: Enabled
0
12
Reserved
R/W
Reserved
0
11
Advertise asymmetric pause
R/W
1: Advertises asymmetric pause
0
10
Advertise symmetric pause
R/W
1: Advertises symmetric pause
0
9
Advertise100BASE-T4
R/W
1: Advertises 100BASE-T4
0
8
Advertise100BASE-TX FDX
R/W
1: Advertise 100BASE-TX FDX
1
7
Advertise100BASE-TX HDX
R/W
1: Advertises 100BASE-TX HDX
1
6
Advertise10BASE-T FDX
R/W
1: Advertises 10BASE-T FDX
1
5
Advertise10BASE-T HDX
R/W
1: Advertises 10BASE-T HDX
4:0
Advertise selector
R/W
4.2.5
1
00001
Link Partner Autonegotiation Capability
The bits in main register 5 can be used to determine if the Cat5 link partner (LP) used with the
VSC8574-02 is compatible with the autonegotiation functionality.
Table 44 •
Autonegotiation Link Partner Ability, Address 5 (0x05)
Bit
Name
Access Description
15
LP next page transmission request RO
1: Requested
0
14
LP acknowledge
RO
1: Acknowledge
0
13
LP remote fault
RO
1: Remote fault
0
12
Reserved
RO
Reserved
0
11
LP advertise asymmetric pause
RO
1: Capable of asymmetric pause
0
10
LP advertise symmetric pause
RO
1: Capable of symmetric pause
0
9
LP advertise 100BASE-T4
RO
1: Capable of 100BASE-T4
0
8
LP advertise 100BASE-TX FDX
RO
1: Capable of 100BASE-TX FDX
0
7
LP advertise 100BASE-TX HDX
RO
1: Capable of 100BASE-TX HDX 0
6
LP advertise 10BASE-T FDX
RO
1: Capable of 10BASE-T FDX
0
5
LP advertise 10BASE-T HDX
RO
1: Capable of 10BASE-T HDX
0
4:0
LP advertise selector
RO
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Default
00000
98
Registers
4.2.6
Autonegotiation Expansion
The bits in main register 6 work together with those in register 5 to indicate the status of the LP
autonegotiation functioning. The following table shows the available settings and readouts.
Autonegotiation Expansion, Address 6 (0x06)
Table 45 •
Bit
Name
Access Description
Default
15:5
Reserved
RO
Reserved.
All zeros
4
Parallel detection fault
RO
This bit latches high.
1: Parallel detection fault.
0
3
LP next page capable
RO
1: LP is next page capable.
0
2
Local PHY next page capable RO
1: Local PHY is next page capable.
1
1
Page received
This bit latches low.
1: New page is received.
0
0
LP is autonegotiation capable RO
1: LP is capable of autonegotiation.
0
4.2.7
RO
Transmit Autonegotiation Next Page
The settings in register 7 in the main registers space provide information about the number of pages in
an autonegotiation sequence. The following table shows the settings available.
Table 46 •
4.2.8
Autonegotiation Next Page Transmit, Address 7 (0x07)
Bit
Name
Access Description
Default
15
Next page
R/W
1: More pages follow
0
14
Reserved
RO
Reserved
0
13
Message page
R/W
1: Message page
0: Unformatted page
1
12
Acknowledge 2
R/W
1: Complies with request
0: Cannot comply with request
0
11
Toggle
RO
1: Previous transmitted LCW = 0 0: 0
Previous transmitted LCW = 1
10:0
Message/unformatted code
R/W
00000000001
Autonegotiation Link Partner Next Page Receive
The bits in register 8 of the main register space work together with register 7 to determine certain aspects
of the LP autonegotiation. The following table shows the possible readouts.
Table 47 •
Autonegotiation LP Next Page Receive, Address 8 (0x08)
Bit
Name
Access Description
Default
15
LP next page
RO
1: More pages follow
0
14
Acknowledge
RO
1: LP acknowledge
0
13
LP message page
RO
1: Message page
0: Unformatted page
0
12
LP acknowledge 2
RO
1: LP complies with request
0
11
LP toggle
RO
1: Previous transmitted LCW = 0
0: Previous transmitted LCW = 1
0
10:0
LP message/unformatted code RO
VMDS-10510 VSC8574-02 Datasheet Revision 4.2
All zeros
99
Registers
4.2.9
1000BASE-T Control
The VSC8574-02's 1000BASE-T functionality is controlled by the bits in register 9 of the main register
space. The following table shows the settings and readouts available.
Table 48 •
1000BASE-T Control, Address 9 (0x09)
Bit
Name
Access Description
Default
15:13
Transmitter test mode
R/W
000: Normal
001: Mode 1: Transmit waveform test
010: Mode 2: Transmit jitter test as master
011: Mode 3: Transmit jitter test as slave
100: Mode 4: Transmitter distortion test
101–111: Reserved
000
12
Master/slave manual
configuration
R/W
1: Master/slave manual configuration enabled 0
11
Master/slave value
R/W
This register is only valid when bit 9.12 is set
to 1.
1: Configure PHY as master during
negotiation
0: Configure PHY as slave during negotiation
0
10
Port type
R/W
1: Multi-port device
0: Single-port device
1
9
1000BASE-T FDX
capability
R/W
1: PHY is 1000BASE-T FDX capable
1
8
1000BASE-T HDX
capability
R/W
1: PHY is 1000BASE-T HDX capable
1
7:0
Reserved
R/W
Reserved
0x00
Note: Transmitter test mode (bits 15:13) operates in the manner described in IEEE 802.3 section 40.6.1.1.2.
When using any of the transmitter test modes, the automatic media sense feature must be disabled. For
more information, see Extended PHY Control Set 1, page 105.
4.2.10
1000BASE-T Status
The bits in register 10 of the main register space can be read to obtain the status of the 1000BASE-T
communications enabled in the device. The following table shows the readouts.
Table 49 •
1000BASE-T Status, Address 10 (0x0A)
Bit
Name
Access Description
15
Master/slave
configuration fault
RO
This bit latches high.
0
1: Master/slave configuration fault detected
0: No master/slave configuration fault detected
14
Master/slave
configuration resolution
RO
1: Local PHY configuration resolved to master 1
0: Local PHY configuration resolved to slave
13
Local receiver status
RO
1: Local receiver is operating normally
0
12
Remote receiver status
RO
1: Remote receiver OK
0
11
LP 1000BASE-T FDX
capability
RO
1: LP 1000BASE-T FDX capable
0
10
LP 1000BASE-T HDX
capability
RO
1: LP 1000BASE-T HDX capable
0
9:8
Reserved
RO
Reserved
00
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Default
100
Registers
Table 49 •
1000BASE-T Status, Address 10 (0x0A) (continued)
Bit
Name
Access Description
Default
7:0
Idle error count
RO
0x00
4.2.11
Self-clearing register
MMD Access Control Register
The bits in register 13 of the main register space are a window to the EEE registers as defined in
IEEE 802.3az-2010 Clause 45.
Table 50 •
4.2.12
MMD EEE Access, Address 13 (0x0D)
Bit
Name
Access Description
15:14
Function
R/W
13:5
Reserved R/W
Reserved
4:0
DVAD
Device address as defined in IEEE 802.3az-2010 table
45–1
R/W
00: Address
01: Data, no post increment
10: Data, post increment for read and write
11: Data, post increment for write only
MMD Address or Data Register
The bits in register 14 of the main register space are a window to the EEE registers as defined in
IEEE 802.3az-2010 Clause 45.
Table 51 •
4.2.13
MMD Address or Data Register, Address 14 (0x0E)
Bit
Name
Access Description
15:0
Register Address/Data
R/W
When register 13.15:14 = 2'b00, address of register of
the device that is specified by 13.4:0. Otherwise, the
data to be written to or read from the register.
1000BASE-T Status Extension 1
Register 15 provides additional information about the operation of the device 1000BASE-T
communications. The following table shows the readouts available.
Table 52 •
1000BASE-T Status Extension 1, Address 15 (0x0F)
Bit
Name
Access Description
15
1000BASE-X FDX capability RO
1: PHY is 1000BASE-X FDX capable 1
14
1000BASE-X HDX capability RO
1: PHY is 1000BASE-X HDX capable 1
13
1000BASE-T FDX capability RO
1: PHY is 1000BASE-T FDX capable 1
12
1000BASE-T HDX capability RO
1: PHY is 1000BASE-T HDX capable 1
11:0
Reserved
Reserved
RO
VMDS-10510 VSC8574-02 Datasheet Revision 4.2
Default
0x000
101
Registers
4.2.14
100BASE-TX/FX Status Extension
Register 16 in the main registers page space of the VSC8574-02 provides additional information about
the status of the device's 100BASE-TX/100BASE-FX operation.
Table 53 •
100BASE-TX/FX Status Extension, Address 16 (0x10)
Bit
Name
Access Description
Default
15
100BASE-TX/FX Descrambler
RO
1: Descrambler locked
0
14
100BASE-TX/FX lock error
RO
Self-clearing bit.
1: Lock error detected
0
13
100BASE-TX/FX disconnect
state
RO
Self-clearing bit.
1: PHY 100BASE-TX link disconnect
detected
0
12
100BASE-TX/FX current link
status
RO
1: PHY 100BASE-TX link active
0
11
100BASE-TX/FX receive error
RO
Self-clearing bit.
1: Receive error detected
0
10
100BASE-TX/FX transmit error
RO
Self-clearing bit.
1: Transmit error detected
0
9
100BASE-TX/FX SSD error
RO
Self-clearing bit.
1: Start-of-stream delimiter error
detected
0
8
100BASE-TX/FX ESD error
RO
Self-clearing bit.
1: End-of-stream delimiter error
detected
0
7:0
Reserved
RO
Reserved
4.2.15
1000BASE-T Status Extension 2
The second status extension register is at address 17 in the device main registers space. It provides
information about another set of parameters associated with 1000BASE-T communications. For
information about the first status extension register, see Table 52, page 101.
Table 54 •
1000BASE-T Status Extension 2, Address 17 (0x11)
Bit
Name
Access Description
Default
15
1000BASE-T descrambler
RO
1: Descrambler locked.
0
14
1000BASE-T lock error
RO
Self-clearing bit.
1: Lock error detected
0
13
1000BASE-T disconnect state RO
Self-clearing bit.
1: PHY 1000BASE-T link disconnect
detected
0
12
1000BASE-T current link
status
RO
1: PHY 1000BASE-T link active
0
11
1000BASE-T receive error
RO
Self-clearing bit.
1: Receive error detected
0
10
1000BASE-T transmit error
RO
Self-clearing bit.
1: Transmit error detected
0
9
1000BASE-T SSD error
RO
Self-clearing bit.
0
1: Start-of-stream delimiter error detected
VMDS-10510 VSC8574-02 Datasheet Revision 4.2
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Registers
Table 54 •
1000BASE-T Status Extension 2, Address 17 (0x11) (continued)
Bit
Name
Access Description
8
1000BASE-T ESD error
RO
7
1000BASE-T carrier extension RO
error
Self-clearing bit.
1: Carrier extension error detected
0
6
Non-compliant BCM5400
detected
RO
1: Non-compliant BCM5400 link partner
detected
0
5
MDI crossover error
RO
1: MDI crossover error was detected
0
4:0
Reserved
RO
Reserved
4.2.16
Default
Self-clearing bit.
0
1: End-of-stream delimiter error detected
Bypass Control
The bits in this register control aspects of functionality in effect when the device is disabled for the
purpose of traffic bypass. The following table shows the settings available.
Table 55 •
Bypass Control, Address 18 (0x12)
Bit
Name
Access Description
Default
15
Transmit disable
R/W
1: PHY transmitter disabled
0
14
4B5B encoder/decoder
R/W
1: Bypass 4B/5B encoder/decoder
0
13
Scrambler
R/W
1: Bypass scrambler
0
12
Descrambler
R/W
1: Bypass descrambler
0
11
PCS receive
R/W
1: Bypass PCS receiver
0
10
PCS transmit
R/W
1: Bypass PCS transmit
0
9
LFI timer
R/W
1: Bypass Link Fail Inhibit (LFI) timer
0
8
Reserved
RO
Reserved
7
HP Auto-MDIX at forced
10/100
R/W
Sticky bit.
1
1: Disable HP Auto-MDIX at forced 10/100
speeds
6
Non-compliant BCM5400
detect disable
R/W
Sticky bit.
1: Disable non-compliant BCM5400
detection
0
5
Disable pair swap correction
(HP Auto-MDIX when
autonegotiation enabled)
R/W
Sticky bit.
1: Disable the automatic pair swap
correction
0
4
Disable polarity correction
R/W
Sticky bit.
1: Disable polarity inversion correction on
each subchannel
0
3
Parallel detect control
R/W
Sticky bit.
1: Do not ignore advertised ability
0: Ignore advertised ability
1
2
Pulse shaping filter
R/W
1: Disable pulse shaping filter
0
1
Disable automatic
1000BASE-T next page
exchange
R/W
Sticky bit.
1: Disable automatic 1000BASE T next
page exchanges
0
0
Reserved
RO
Reserved
VMDS-10510 VSC8574-02 Datasheet Revision 4.2
103
Registers
Note: If bit 18.1 is set to 1 in this register, automatic exchange of next pages is disabled, and control is returned
to the user through the SMI after the base page is exchanged. The user then must send the correct
sequence of next pages to the link partner, determine the common capabilities, and force the device into
the correct configuration following the successful exchange of pages.
4.2.17
Error Counter 1
The bits in register 19 provide an error counter. The following table shows the settings available.
Error Counter 1, Address 19 (0x13)
Table 56 •
Bit
Name
Access Description
15:8
Reserved
RO
Reserved.
7:0
100/1000 receive
error counter
RO
8-bit counter that saturates when it reaches
255. These bits are self-clearing when read.
4.2.18
Default
0x00
Error Counter 2
The bits in register 20 provide an error counter. The following table shows the settings available.
Error Counter 2, Address 20 (0x14)
Table 57 •
Bit
Name
Access Description
15:8
Reserved
RO
Reserved.
7:0
100/1000 false carrier
counter
RO
8-bit counter that saturates when it reaches
255. These bits are self-clearing when read.
4.2.19
Default
0x00
Error Counter 3
The bits in register 21 provide an error counter. The following table shows the settings available.
Table 58 •
Error Counter 3, Address 21 (0x15)
Bit
Name
Access Description
15:8
Reserved
RO
Reserved.
7:0
Copper media link
disconnect counter
RO
8-bit counter that saturates when it reaches
255. These bits are self-clearing when read.
4.2.20
Default
0x00
Extended Control and Status
The bits in register 22 provide additional device control and readouts. The following table shows the
settings available.
Table 59 •
Extended Control and Status, Address 22 (0x16)
Bit
Name
Access Description
Default
15
Force 10BASE-T link high
R/W
Sticky bit.
1: Bypass link integrity test
0: Enable link integrity test
0
14
Jabber detect disable
R/W
Sticky bit.
1: Disable jabber detect
0
13
Disable 10BASE-T echo
R/W
Sticky bit.
1: Disable 10BASE-T echo
1
12
Disable SQE mode
R/W
Sticky bit.
1: Disable SQE mode
1
VMDS-10510 VSC8574-02 Datasheet Revision 4.2
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Registers
Table 59 •
Extended Control and Status, Address 22 (0x16) (continued)
Bit
Name
Access Description
Default
11:10
10BASE-T squelch control
R/W
Sticky bit.
00: Normal squelch
01: Low squelch
10: High squelch
11: Reserved
00
9
Sticky reset enable
R/W
Super-sticky bit.
1: Enabled
1
8
EOF Error
RO
This bit is self-clearing.
1: EOF error detected
0
7
10BASE-T disconnect state RO
This bit is self-clearing.
1: 10BASE-T link disconnect detected
0
6
10BASE-T link status
RO
1: 10BASE-T link active
0
5:1
Reserved
RO
Reserved
0
SMI broadcast write
R/W
Sticky bit.
1: Enabled
0
The following information applies to the extended control and status bits:
•
•
•
•
4.2.21
When bit 22.15 is set, the link integrity state machine is bypassed and the PHY is forced into a link
pass status.
When bits 22.11:10 are set to 00, the squelch threshold levels are based on the IEEE standard for
10BASE-T. When set to 01, the squelch level is decreased, which can improve the bit error rate
performance on long loops. When set to 10, the squelch level is increased and can improve the bit
error rate in high-noise environments.
When bit 22.9 is set, all sticky register bits retain their values during a software reset. Clearing this
bit causes all sticky register bits to change to their default values upon software reset. Super-sticky
bits retain their values upon software reset regardless of the setting of bit 22.9.
When bit 22.0 is set, if a write to any PHY register (registers 0–31, including extended registers), the
same write is broadcast to all PHYs. For example, if bit 22.0 is set to 1 and a write to PHY0 is
executed (register 0 is set to 0x1040), all PHYs' register 0s are set to 0x1040. Disabling this bit
restores normal PHY write operation. Reads are still possible when this bit is set, but the value that
is read corresponds only to the particular PHY being addressed.
Extended PHY Control Set 1
The following table shows the settings available.
Table 60 •
Extended PHY Control 1, Address 23 (0x17)
Bit
Name
Access Description
Default
15:13
Reserved
R/W
0
12
MAC interface mode R/W
Super-sticky bit.
0
0: SGMII
1: 1000BASE-X.
Note: Register 19G.15:14 must be = 00
for this selection to be valid.
11
AMS preference
Super-sticky bit.
1: Cat5 copper preferred.
0: SerDes fiber/SFP preferred.
R/W
Reserved
VMDS-10510 VSC8574-02 Datasheet Revision 4.2
0
105
Registers
Table 60 •
Extended PHY Control 1, Address 23 (0x17) (continued)
Bit
Name
Access Description
Default
10:8
Media operating
mode
R/W
Super-sticky bits.
000
000: Cat5 copper only.
001: SerDes fiber/SFP protocol transfer mode
only.
010: 1000BASE-X fiber/SFP media only with
autonegotiation performed by the PHY.
011: 100BASE-FX fiber/SFP on the fiber media
pins only.
101: Automatic media sense (AMS) with Cat5
media or SerDes fiber/SFP protocol transfer
mode.
110: AMS with Cat5 media or 1000BASE-X
fiber/SFP media with autonegotiation performed
by PHY.
111: AMS with Cat5 media or 100BASE-FX
fiber/SFP media.
100: AMS.
7:6
Force AMS override
R/W
Sticky bits.
00: Normal AMS selection
01: Force AMS to select SerDes media only
10: Force AMS to select copper media only
11: Reserved
5:4
Reserved
RO
Reserved.
3
Far-end loopback
mode
R/W
1: Enabled.
2:0
Reserved
RO
Reserved.
00
0
Note: After configuring bits 13:8 of the extended PHY control register set 1, a software reset (register 0, bit 15)
must be written to change the device operating mode. On read, these bits only indicate the actual
operating mode and not the pending operating mode setting before a software reset has taken place.
4.2.22
Extended PHY Control Set 2
The second set of extended controls is located in register 24 in the main register space for the device.
The following table shows the settings and readouts available.
Table 61 •
Extended PHY Control 2, Address 24 (0x18)
Bit
Name
Access Description
Default
15:13
100BASE-TX edge
rate control
R/W
Sticky bit.
011: +5 edge rate (slowest)
010: +4 edge rate
001: +3 edge rate
000: +2 edge rate
111: +1 edge rate
110: Default edge rate
101: –1 edge rate
100: –2 edge rate (fastest)
001
12
PICMG 2.16 reduced R/W
power mode
Sticky bit.
1: Enabled
0
11:6
Reserved
Reserved
RO
VMDS-10510 VSC8574-02 Datasheet Revision 4.2
106
Registers
Table 61 •
Extended PHY Control 2, Address 24 (0x18) (continued)
Bit
Name
Access Description
Default
5:4
Jumbo packet mode
R/W
Sticky bit.
00: Normal IEEE 1.5 kB packet length
01: 9 kB jumbo packet length (12 kB with
60 ppm or better reference clock)
10: 12 kB jumbo packet length (16 kB with
70 ppm or better reference clock)
11: Reserved
00
3:1
Reserved
RO
Reserved
0
1000BASE-T
connector loopback
R/W
1: Enabled
0
Note: When bits 5:4 are set to jumbo packet mode, the default maximum packet values are based on 100 ppm
driven reference clock to the device. Controlling the ppm offset between the MAC and the PHY as
specified in the bit description results in a higher jumbo packet length.
4.2.23
Interrupt Mask
These bits control the device interrupt mask. The following table shows the settings available.
Table 62 •
Interrupt Mask, Address 25 (0x19)
Bit
Name
Access Description
Default
15
MDINT interrupt status enable
R/W
Sticky bit. 1: Enabled.
0
14
Speed state change mask
R/W
Sticky bit. 1: Enabled.
0
13
Link state change mask
R/W
Sticky bit. 1: Enabled.
0
12
FDX state change mask
R/W
Sticky bit. 1: Enabled.
0
11
Autonegotiation error mask
R/W
Sticky bit. 1: Enabled.
0
10
Autonegotiation complete mask
R/W
Sticky bit. 1: Enabled.
0
9
Inline powered device (PoE) detect mask
R/W
Sticky bit. 1: Enabled.
0
8
Symbol error interrupt mask
R/W
Sticky bit. 1: Enabled.
0
7
Fast link failure interrupt mask(1)
R/W
Sticky bit. 1: Enabled.
0
6:5
Reserved
R/W
4
AMS media changed mask(2)
R/W
Sticky bit. 1: Enabled.
0
3
False carrier interrupt mask
R/W
Sticky bit. 1: Enabled.
0
2
Link speed downshift detect mask
R/W
Sticky bit. 1: Enabled.
0
1
Master/Slave resolution error mask
R/W
Sticky bit. 1: Enabled.
0
0
RX_ER interrupt mask
R/W
Sticky bit. 1: Enabled.
0
1.
2.
0
The interrupt is only valid for 100 Mbps and 1000 Mbps speeds. Notification at 10 Mbps speed requires
use of the FASTLINK-FAIL pin.
If hardware interrupts are not used, the mask can still be set and the status polled for changes.
Note: When bit 25.15 is set, the MDINT pin is enabled. When enabled, the state of this pin reflects the state of
bit 26.15. Clearing this bit only inhibits the MDINT pin from being asserted. Also, before enabling this bit,
read register 26 to clear any previously inactive interrupts pending that will cause bit 25.15 to be set.
VMDS-10510 VSC8574-02 Datasheet Revision 4.2
107
Registers
4.2.24
Interrupt Status
The status of interrupts already written to the device is available for reading from register 26 in the main
registers space. The following table shows the expected readouts.
Table 63 •
Interrupt Status, Address 26 (0x1A)
Bit
Name
Access Description
Default
15
Interrupt status
RO
Self-clearing bit. 1: Interrupt pending.
0
14
Speed state change status
RO
Self-clearing bit. 1: Interrupt pending.
0
13
Link state change status
RO
Self-clearing bit. 1: Interrupt pending.
0
12
FDX state change status
RO
Self-clearing bit. 1: Interrupt pending.
0
11
Autonegotiation error status
RO
Self-clearing bit. 1: Interrupt pending.
0
10
Autonegotiation complete status RO
Self-clearing bit. 1: Interrupt pending.
0
9
Inline powered device detect
status
RO
Self-clearing bit. 1: Interrupt pending.
0
8
Symbol error status
RO
Self-clearing bit. 1: Interrupt pending.
0
7
Fast link failure detect status
RO
Self-clearing bit. 1: Interrupt pending.
0
6:5
Reserved
RO
4
AMS media changed
3
mask(1)
0
RO
Self-clearing bit. 1: Interrupt pending.
0
False carrier interrupt status
RO
Self-clearing bit. 1: Interrupt pending.
0
2
Link speed downshift detect
status
RO
Self-clearing bit. 1: Interrupt pending.
0
1
Master/Slave resolution error
status
RO
Self-clearing bit. 1: Interrupt pending.
0
0
RX_ER interrupt status
RO
Self-clearing bit. 1: Interrupt pending.
0
1.
If hardware interrupts are not used, the mask can still be set and the status polled for changes.
The following information applies to the interrupt status bits:
•
•
•
•
4.2.25
All set bits in this register are cleared after being read (self-clearing). If bit 26.15 is set, the cause of
the interrupt can be read by reading bits 26.14:0.
For bits 26.14 and 26.12, bit 0.12 must be set for this interrupt to assert.
For bit 26.2, bits 4.8:5 must be set for this interrupt to assert.
For bit 26.0, this interrupt will not occur when RX_ER is used for carrier-extension decoding of a link
partner's data transmission.
Device Auxiliary Control and Status
Register 28 provides control and status information for several device functions not controlled or
monitored by other device registers. The following table shows the settings available and the expected
readouts.
Table 64 •
Auxiliary Control and Status, Address 28 (0x1C)
Bit
Name
Access Description
Default
15
Autonegotiation complete
RO
Duplicate of bit 1.5
0
14
Autonegotiation disabled
RO
Inverted duplicate of bit 0.12
0
131
HP Auto-MDIX crossover
indication
RO
1: HP Auto-MDIX crossover performed
internally
0
VMDS-10510 VSC8574-02 Datasheet Revision 4.2
108
Registers
Table 64 •
Bit
Name
Access Description
Default
12
CD pair swap
RO
1: CD pairs are swapped
0
11
A polarity inversion
RO
1: Polarity swap on pair A
0
10
B polarity inversion
RO
1: Polarity swap on pair B
0
9
C polarity inversion
RO
1: Polarity swap on pair C
0
8
D polarity inversion
RO
1: Polarity swap on pair D
0
7
ActiPHY link status time-out R/W
control [1]
Sticky bit. Bits 7 and 2 are part of the
0
ActiPHY Link Status time-out control. Bit 7
is the MSB.
00: 2.3 seconds
01: 3.3 seconds
10: 4.3 seconds
11: 5.3 seconds
6
ActiPHY mode enable
R/W
Sticky bit.
1: Enabled
0
5
FDX status
RO
1: Full-duplex
0: Half-duplex
00
4:3
Speed status
RO
00: Speed is 10BASE-T
0
01: Speed is 100BASE-TX or 100BASE-FX
10: Speed is 1000BASE-T or 1000BASE-X
11: Reserved
2
ActiPHY link status time-out R/W
control [0]
Sticky bit. Bits 7 and 2 are part of the
1
ActiPHY Link Status time-out control. Bit 7
is the MSB.
00: 2.3 seconds
01: 3.3 seconds
10: 4.3 seconds
11: 5.3 seconds
1:0
Media mode status
00: No media selected
01: Copper media selected
10: SerDes (Fiber) media selected
11: Reserved
1.
4.2.26
Auxiliary Control and Status, Address 28 (0x1C) (continued)
RO
00
In 1000BT mode, if Force MDI crossover is performed while link is up, the 1000BT link must be re-negotiated
in order for this bit to reflect the actual Auto-MDIX setting.
LED Mode Select
The device LED outputs are controlled using the bits in register 29 of the main register space. The
following table shows the information needed to access the functionality of each of the outputs. For more
information about LED modes, see Table 28, page 75. For information about enabling the extended LED
mode bits in Register 19E1 bits 13 to 12, see Table 29, page 76.
Table 65 •
LED Mode Select, Address 29 (0x1D)
Bit
Name
Access Description
15:12
LED3 mode select R/W
Sticky bit. Select from LED modes 0–15.
1000
11:8
LED2 mode select R/W
Sticky bit. Select from LED modes 0–15.
0000
7:4
LED1 mode select R/W
Sticky bit. Select from LED modes 0–15.
0010
3:0
LED0 mode select R/W
Sticky bit. Select from LED modes 0–15.
0001
VMDS-10510 VSC8574-02 Datasheet Revision 4.2
Default
109
Registers
4.2.27
LED Behavior
The bits in register 30 control and enable you to read the status of the pulse or blink rate of the device
LEDs. The following table shows the settings you can write to the register or read from the register.
Table 66 •
LED Behavior, Address 30 (0x1E)
Bit
Name
Access Description
15
Copper and fiber
R/W
LED combine disable
Sticky bit
0: Combine enabled (Copper/Fiber on
link/linkXXXX/activity LED)
1: Disable combination (link/linkXXXX/activity
LED; indicates copper only)
14
Activity output select R/W
0
Sticky bit
1: Activity LED becomes TX_Activity and fiber
activity LED becomes RX_Activity
0: TX and RX activity both displayed on activity
LEDs
13
Reserved
RO
Reserved
12
LED pulsing enable
R/W
Sticky bit
0
0: Normal operation
1: LEDs pulse with a 5 kHz, programmable duty
cycle when active
11:10
LED blink/pulsestretch rate
R/W
Sticky bit
00: 2.5 Hz blink rate/400 ms pulse-stretch
01: 5 Hz blink rate/200 ms pulse-stretch
10: 10 Hz blink rate/100 ms pulse-stretch
11: 20 Hz blink rate/50 ms pulse-stretch
The blink rate selection for PHY0 globally sets
the rate used for all LED pins on all PHY ports
9
Reserved
RO
Reserved
8
LED3 pulsestretch/blink select
R/W
Sticky bit
1: Pulse-stretch
0: Blink
0
7
LED2 pulsestretch/blink select
R/W
Sticky bit
1: Pulse-stretch
0: Blink
0
6
LED1 pulsestretch/blink select
R/W
Sticky bit
1: Pulse-stretch
0: Blink
0
5
LED0 pulsestretch/blink select
R/W
Sticky bit
1: Pulse-stretch
0: Blink
0
4
Reserved
RO
Reserved
3
LED3 combine
feature disable
R/W
Sticky bit
0: Combine enabled (link/activity,
duplex/collision)
1: Disable combination (link only, duplex only)
0
2
LED2 combine
feature disable
R/W
Sticky bit
0: Combine enabled (link/activity,
duplex/collision)
1: Disable combination (link only, duplex only)
0
VMDS-10510 VSC8574-02 Datasheet Revision 4.2
Default
0
01
110
Registers
Table 66 •
LED Behavior, Address 30 (0x1E) (continued)
Bit
Name
Access Description
Default
1
LED1 combine
feature disable
R/W
Sticky bit
0: Combine enabled (link/activity,
duplex/collision)
1: Disable combination (link only, duplex only)
0
0
LED0 combine
feature disable
R/W
Sticky bit
0: Combine enabled (link/activity,
duplex/collision)
1: Disable combination (link only, duplex only)
0
Note: Bits 30.11:10 are active only in port 0 and affect the behavior of LEDs for all the ports.
4.2.28
Extended Page Access
To provide functionality beyond the IEEE 802.3-specified registers and main device registers, the
VSC8574-02 includes an extended set of registers that provide an additional 15 register spaces.
The register at address 31 controls the access to the extended registers for the VSC8574-02. Accessing
the GPIO page register space is similar to accessing the extended page registers. The following table
shows the settings available.
Table 67 •
4.3
Extended/GPIO Register Page Access, Address 31 (0x1F)
Bit
Name
Access Description
15:0
Extended/GPIO page R/W
register access
Default
0x0000: Register 16–30 accesses main register 0x0000
space. Writing 0x0000 to register 31 restores the
main register access.
0x0001: Registers 16–30 access extended
register space 1
0x0002: Registers 16–30 access extended
register space 2
0x0003: Registers 16–30 access extended
register space 3
0x0010: Registers 0–30 access GPIO register
space
0x1588: Registers 16-18 1588 registers
Extended Page 1 Registers
To access the extended page 1 registers (16E1–30E1), enable extended register access by writing
0x0001 to register 31. Writing 0x0000 to register 31 restores the main register access.
When extended page 1 register access is enabled, reads and writes to registers 16–30 affect the
extended registers 16E1–30E1 instead of those same registers in the IEEE-specified register space.
Registers 0–15 are not affected by the state of the extended page register access.
Table 68 •
Extended Registers Page 1 Space
Address
Name
16E1
SerDes Media Control
17E1
Reserved
18E1
Cu Media CRC good counter
19E1
Extended mode and SIGDET control
20E1
Extended PHY control 3 (ActiPHY)
VMDS-10510 VSC8574-02 Datasheet Revision 4.2
111
Registers
Table 68 •
Extended Registers Page 1 Space (continued)
Address
Name
21E1–22E1 Reserved
23E1
Extended PHY control 4 (PoE and CRC error counter)
24E1
VeriPHY 1
25E1
VeriPHY 2
26E1
VeriPHY 3
27E1–28E1 Reserved
4.3.1
29E1
Ethernet packet generator (EPG) 1
30E1
EPG 2
SerDes Media Control
Register 16E1 controls some functions of the SerDes media interface on ports 0–3. These settings are
only valid for those ports. The following table shows the setting available in this register.
Table 69 •
SerDes Media Control, Address 16E1 (0x10)
Bit
Name
Access Description
Default
15:14
Transmit remote fault
R/W
Remote fault indication sent to link
partner (LP)
00
13:12
Link partner (LP) remote
fault
RO
Remote fault bits sent by LP during
autonegotiation
00
11:10
Reserved
RO
Reserved
9
Allow 1000BASE-X link-up
R/W
Sticky bit.
1
1: Allow 1000BASE-X fiber media link-up
capability
0: Suppress 1000BASE-X fiber media
link-up capability
8
Allow 100BASE-FX link-up
R/W
Sticky bit.
1
1: Allow 100BASE-FX fiber media link-up
capability
0: Suppress 100BASE-FX fiber media
link-up capability
7
Reserved
RO
Reserved
6
Far end fault detected in
100BASE-FX
RO
Self-clearing bit.
0
1: Far end fault in 100BASE-FX detected
5:0
Reserved
RO
Reserved
4.3.2
Cu Media CRC Good Counter
Register 18E1 makes it possible to read the contents of the CRC good counter for packets that are
received on the Cu media interface; the number of CRC routines that have executed successfully. The
following table shows the expected readouts.
Table 70 •
Cu Media CRC Good Counter, Address 18E1 (0x12)
Bit
Name
Access Description
Default
15
Packet since last read
RO
0
Self-clearing bit.
1: Packet received since last read.
VMDS-10510 VSC8574-02 Datasheet Revision 4.2
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Registers
Cu Media CRC Good Counter, Address 18E1 (0x12) (continued)
Table 70 •
Bit
Name
Access Description
14
Reserved
RO
Reserved.
13:0
Cu Media CRC good
counter contents
RO
Self-clearing bit. Counter containing the
number of packets with valid CRCs modulo
10,000; this counter does not saturate and
will roll over to zero on the next good packet
received after 9,999.
4.3.3
Default
0x000
Extended Mode Control
Register 19E1 controls the extended LED and other chip modes. The following table shows the settings
available.
Table 71 •
Extended Mode Control, Address 19E1 (0x13)
Bit
Name
Access Description
Default
15
LED3 Extended Mode
R/W
Sticky bit.
1: See Extended LED Modes, page 76
0
14
LED2 Extended Mode
R/W
Sticky bit.
1: See Extended LED Modes, page 76
0
13
LED1 Extended Mode
R/W
Sticky bit.
1: See Extended LED Modes, page 76
0
12
LED0 Extended Mode
R/W
Sticky bit.
1: See Extended LED Modes, page 76
0
11
LED Reset Blink Suppress R/W
Sticky bit.
0
1: Blink LEDs after COMA_MODE is
de-asserted
0: Suppress LED blink after COMA_MODE
is de-asserted
10:5
Reserved
RO
Reserved
0
4
Fast link failure
R/W
Sticky bit.
Enable fast link failure pin. This must be
done from PHY0 only.
1: Enabled
0: Disabled (GPIO9 pin becomes general
purpose I/O)
0
3:2
Force MDI crossover
R/W
Sticky bits.
00: Normal HP Auto-MDIX operation
01: Reserved
10: Copper media forced to MDI
11: Copper media forced MDI-X
00
1
Reserved
RO
Reserved
0
GPIO[3:0]/SIGDET[3:0] pin R/W
polarity
Sticky bit.
1: Active low
0: Active high
VMDS-10510 VSC8574-02 Datasheet Revision 4.2
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113
Registers
4.3.4
ActiPHY Control
Register 20E1 controls the device ActiPHY sleep timer, its wake-up timer, and its link speed downshifting
feature. The following table shows the settings available.
Table 72 •
Extended PHY Control 3, Address 20E1 (0x14)
Bit
Name
Access Description
15
Disable carrier extension
R/W
1: Disable carrier extension in 1000BASE-T 1
copper links
14:13
ActiPHY sleep timer
R/W
Sticky bit.
00: 1 second
01: 2 seconds
10: 3 seconds
11: 4 seconds
01
12:11
ActiPHY wake-up timer
R/W
Sticky bit.
00: 160 ms
01: 400 ms
10: 800 ms
11: 2 seconds
00
10
Reserved
RO
Reserved
9
PHY address reversal
R/W
Sticky bit.
Reverse PHY address
Enabling causes physical PHY 0 to have
address of 3, PHY 1 address of 2, PHY 2
address of 1, and PHY 3 address of 0.
Changing this bit to 1 should initially be
done from PHY 0 and changing to 0 from
PHY3
1: Enabled
0: Disabled
8
Reserved
RO
Valid only on PHY0
7:6
Media mode status
RO
00: No media selected
01: Copper media selected
10: SerDes media selected
11: Reserved
5
Enable 10BASE-T no
preamble mode
R/W
Sticky bit.
0
1: 10BASE-T will assert RX_DV indication
when data is presented to the receiver even
without a preamble preceding it
4
Enable link speed
autodownshift feature
R/W
Sticky bit.
1: Enable auto link speed downshift from
1000BASE-T
0
3:2
Link speed auto downshift R/W
control
Sticky bits.
00: Downshift after 2 failed 1000BASE-T
autonegotiation attempts
01: Downshift after 3 failed 1000BASE-T
autonegotiation attempts
10: Downshift after 4 failed 1000BASE-T
autonegotiation attempts
11: Downshift after 5 failed 1000BASE-T
autonegotiation attempts
01
1
Link speed auto downshift RO
status
0: No downshift
1: Downshift is required or has occurred
0
VMDS-10510 VSC8574-02 Datasheet Revision 4.2
Default
0
00
114
Registers
Table 72 •
Extended PHY Control 3, Address 20E1 (0x14) (continued)
Bit
Name
Access Description
0
Reserved
RO
4.3.5
Default
Reserved
PoE and Miscellaneous Functionality
The register at address 23E1 controls various aspects of inline powering and the CRC error counter in
the VSC8574-02.
Table 73 •
Extended PHY Control 4, Address 23E1 (0x17)
Bit
Name
Access Description
Default
15:11
PHY address
RO
PHY address; latched on reset
10
Inline powered device
detection
R/W
Sticky bit.
1: Enabled
0
9:8
Inline powered device
detection status
RO
Only valid when bit 10 is set.
00: Searching for devices
01: Device found; requires inline power
10: Device found; does not require inline
power
11: Reserved
00
7:0
Cu Media CRC error
counter
RO
Self-clearing bit
RC error counter for packets received on the Cu media interface. The value saturates at 0xFF and
subsequently clears when read and restarts count.0x00
4.3.6
VeriPHY Control 1
Register 24E1 in the extended register space provides control over the device VeriPHY diagnostics
features. There are three separate VeriPHY control registers. The following table shows the settings
available and describes the expected readouts.
Table 74 •
VeriPHY Control Register 1, Address 24E1 (0x18)
Bit
Name
Access Description
Default
15
VeriPHY trigger
R/W
Self-clearing bit.
1: Triggers the VeriPHY algorithm and clears
when VeriPHY has completed. Settings in
registers 24E–26E become valid after this bit
clears.
0
14
VeriPHY valid
RO
1: VeriPHY results in registers 24E–26E are
valid.
0
13:8
Pair A (1, 2) distance
RO
Loop length or distance to anomaly for pair A (1, 0x00
2).
7:6
Reserved
RO
Reserved.
5:0
Pair B (3, 6) distance
RO
Loop length or distance to anomaly for pair B (3, 0x00
6).
Note: The resolution of the 6-bit length field is 3 meters.
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Registers
4.3.7
VeriPHY Control 2
The register at address 25E1 consists of the second of the three device registers that provide control
over VeriPHY diagnostics features. The following table shows the expected readouts.
Table 75 •
VeriPHY Control Register 2, Address 25E1 (0x19)
Bit
Name
Access Description
15:14
Reserved
RO
Reserved
13:8
Pair C (4, 5) distance
RO
Loop length or distance to anomaly for pair C
(4, 5)
7:6
Reserved
RO
Reserved
5:0
Pair D (7, 8) distance
RO
Loop length or distance to anomaly for pair D
(7, 8)
Default
0x00
0x00
Note: The resolution of the 6-bit length field is 3 meters.
4.3.8
VeriPHY Control 3
The register at address 26E1 consists of the third of the three device registers that provide control over
VeriPHY diagnostics features. Specifically, this register provides information about the termination status
(fault condition) for all four link partner pairs. The following table shows the expected readouts.
Table 76 •
VeriPHY Control Register 3, Address 26E1 (0x1A)
Bit
Name
Access Description
Default
15:12
Pair A (1, 2) termination status
RO
Termination fault for pair A (1, 2)
0x00
11:8
Pair B (3, 6) termination status
RO
Termination fault for pair B (3, 4)
0x00
7:4
Pair C (4, 5) termination status
RO
Termination fault for pair C (4, 5)
0x00
3:0
Pair D (7, 8) termination status
RO
Termination fault for pair D (7, 8)
0x00
The following table shows the meanings for the various fault codes.
Table 77 •
VeriPHY Control Register 3 Fault Codes
Code Denotes
0000
Correctly terminated pair
0001
Open pair
0010
Shorted pair
0100
Abnormal termination
1000
Cross-pair short to pair A
1001
Cross-pair short to pair B
1010
Cross-pair short to pair C
1011
Cross-pair short to pair D
1100
Abnormal cross-pair coupling with pair A
1101
Abnormal cross-pair coupling with pair B
1110
Abnormal cross-pair coupling with pair C
1111
Abnormal cross-pair coupling with pair D
VMDS-10510 VSC8574-02 Datasheet Revision 4.2
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Registers
4.3.9
Ethernet Packet Generator Control 1
The EPG control register provides access to and control of various aspects of the EPG testing feature.
There are two separate EPG control registers. The following table shows the settings available in the first
register.
Table 78 •
EPG Control Register 1, Address 29E1 (0x1D)
Bit
Name
Access Description
Default
15
EPG enable
R/W
1: Enable EPG
0
14
EPG run or stop
R/W
1: Run EPG
0
13
Transmission duration R/W
1: Continuous (sends in 10,000-packet
increments)
0: Send 30,000,000 packets and stop
0
12:11
Packet length
R/W
00: 125 bytes
01: 64 bytes
10: 1518 bytes
11: 10,000 bytes (jumbo packet)
0
10
Interpacket gap
R/W
1: 8,192 ns
0: 96 ns
0
9:6
Destination address
R/W
Lowest nibble of the 6-byte destination
address
0001
5:2
Source address
R/W
Lowest nibble of the 6-byte destination
address
0000
1
Payload type
R/W
1: Randomly generated payload pattern
0: Fixed based on payload pattern
0
0
Bad frame check
sequence (FCS)
generation
R/W
1: Generate packets with bad FCS
0: Generate packets with good FCS
0
The following information applies to the EPG control number 1:
•
•
Do not run the EPG when the VSC8574-02 is connected to a live network.
bit 29E1.13 (continuous EPG mode control): When enabled, this mode causes the device to send
continuous packets. When disabled, the device continues to send packets only until it reaches the
next 10,000-packet increment mark. It then ceases to send packets.
The 6-byte destination address in bits 9:6 is assigned one of 16 addresses in the range of 0xFF FF
FF FF FF F0 through 0xFF FF FF FF FF FF.
The 6-byte source address in bits 5:2 is assigned one of 16 addresses in the range of 0xFF FF FF
FF FF F0 through 0xFF FF FF FF FF FF.
If any of bits 13:0 are changed while the EPG is running (bit 14 is set to 1), bit 14 must be cleared
and then set back to 1 for the change to take effect and to restart the EPG.
•
•
•
4.3.10
Ethernet Packet Generator Control 2
Register 30E1 consists of the second set of bits that provide access to and control over the various
aspects of the EPG testing feature. The following table shows the settings available.
Table 79 •
EPG Control Register 2, Address 30E1 (0x1E)
Bit
Name
Access Description
15:0
EPG packet payload R/W
Default
Data pattern repeated in the payload of 0x00
packets generated by the EPG
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Registers
Note: If any of bits 15:0 in this register are changed while the EPG is running (bit 14 of register 29E1 is set to
1), that bit (29E1.14) must first be cleared and then set back to 1 for the change to take effect and to
restart the EPG.
4.4
Extended Page 2 Registers
To access the extended page 2 registers (16E2–30E2), enable extended register access by writing
0x0002 to register 31. For more information, see Table 67, page 111.
When extended page 2 register access is enabled, reads and writes to registers 16–30 affect the
extended registers 16E2–30E2 instead of those same registers in the IEEE-specified register space.
Registers 0–15 are not affected by the state of the extended page register access.
Writing 0x0000 to register 31 restores the main register access.
The following table lists the addresses and register names in the extended register page 2 space. These
registers are accessible only when the device register 31 is set to 0x0002.
Table 80 •
4.4.1
Extended Registers Page 2 Space
Address
Name
16E2
Cu PMD Transmit Control
17E2
EEE Control
18E2-29E2
Reserved
30E2
Ring Resiliency Control
Cu PMD Transmit Control
The register at address 16E2 consists of the bits that provide control over the amplitude settings for the
transmit side Cu PMD interface. These bits provide the ability to make small adjustments in the signal
amplitude to compensate for minor variations in the magnetics from different vendors. Extreme caution
must be exercised when changing these settings from the default values as they have a direct impact on
the signal quality. Changing these settings also affects the linearity and harmonic distortion of the
transmitted signals. For help with changing these values, contact your Microsemi representative.
Table 81 •
Cu PMD Transmit Control, Address 16E2 (0x10)
Bit
Name
Access Description
15:12
1000BASE-T signal R/W
amplitude trim(1)
Sticky bits.
1000BASE-T signal amplitude
1111: -1.7%
1110: -2.6%
1101: -3.5%
1100: -4.4%
1011: -5.3%
1010: -7%
1001: -8.8%
1000: -10.6%
0111: 5.5%
0110: 4.6%
0101: 3.7%
0100: 2.8%
0011: 1.9%
0010: 1%
0001: 0.1%
0000: -0.8%
VMDS-10510 VSC8574-02 Datasheet Revision 4.2
Default
0000
118
Registers
Table 81 •
Cu PMD Transmit Control, Address 16E2 (0x10) (continued)
Bit
Name
Access Description
11:8
100BASE-TX signal R/W
amplitude trim(2)
7:4
10BASE-T signal
amplitude trim(3)
3:0
10BASE-Te signal
amplitude trim
Default
Sticky bits.
100BASE-TX signal amplitude
1111: -1.7%
1110: -2.6%
1101: -3.5%
1100: -4.4%
1011: -5.3%
1010: -7%
1001: -8.8%
1000: -10.6%
0111 5.5%
0110: 4.6%
0101: 3.7%
0100: 2.8%
0011: 1.9%
0010: 1%
0001: 0.1%
0000: -0.8%
0010
R/W
Sticky bits.
10BASE-T signal amplitude
1111: -7%
1110: -7.9%
1101: -8.8%
1100: -9.7%
1011: -10.6%
1010: -11.5%
1001: -12.4%
1000: -13.3%
0111: 0%
0110: -0.7%
0101: -1.6%
0100: -2.5%
0011: -3.4%
0010: -4.3%
0001: -5.2%
0000: -6.1%
1011
R/W
Sticky bits.
10BASE-Te signal amplitude
1111: -30.45%
1110: -31.1%
1101: -31.75%
1100: -32.4%
1011: -33.05%
1010: -33.7%
1001: -34.35%
1000: -35%
0111: -25.25%
0110: -25.9%
0101: -26.55%
0100: -27.2%
0011: -27.85%
0010: -28.5%
0001: -29.15%
0000: -29.8%
1110
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Registers
1.
2.
3.
4.4.2
Changes to 1000BASE-T amplitude may result in unpredictable side effects.
Adjust 100BASE-TX to specific magnetics.
Amplitude is limited by VCC (2.5 V).
EEE Control
The register at address 17E2 consists of the bits that provide additional control over the chip behavior in
energy efficient Ethernet (IEEE 802.3az-2010) mode.
Table 82 •
EEE Control, Address 17E2 (0x11)
Bit
Name
Access Description
Default
15
Enable 10BASE-Te
R/W
Sticky bit.
Enable energy efficient (IEEE 802.3az-2010)
10BASE-Te operating mode.
0
14
Enable LED in fiber
unidirectional mode
R/W
Sticky bit.
1: Enable LED functions in fiber unidirectional
mode.
0
13:10
Invert LED polarity
R/W
Sticky bits.
0000
Invert polarity of LED[3:0]_[3:0] signals. Default
is to drive an active low signal on the LED pins.
This also applies to enhanced serial LED mode.
For more information, see Enhanced Serial LED
Mode, page 78.
9:6
Reserved
RO
Reserved.
5
Enable 1000BASE-T R/W
force mode
0
Sticky bit.
1: Enable 1000BASE-T force mode to allow PHY
to link-up in 1000BASE-T mode without forcing
master/slave when register 0, bits 6 and 13 are
set to 2’b10.
41
Force transmit LPI
Sticky bit.
1: Enable the EPG to transmit LPI on the MDI,
ignore data from the MAC interface.
0: Transmit idles being received from the MAC.
3
Inhibit 100BASE-TX R/W
transmit EEE LPI
Sticky bit.
0
1: Disable transmission of EEE LPI on transmit
path MDI in 100BASE-TX mode when receiving
LPI from MAC.
2
Inhibit 100BASE-TX R/W
receive EEE LPI
Sticky bit.
0
1: Disable transmission of EEE LPI on receive
path MAC interface in 100BASE-TX mode when
receiving LPI from the MDI.
1
Inhibit 1000BASE-T R/W
transmit EEE LPI
Sticky bit.
1: Disable transmission of EEE LPI on transmit
path MDI in 1000BASE-T mode when receiving
LPI from MAC.
0
Inhibit 1000BASE-T R/W
receive EEE LPI
Sticky bit.
0
1: Disable transmission of EEE LPI on receive
path MAC interface in 1000BASE-T mode when
receiving LPI from the MDI.
1.
R/W
0
0
17E2 bits 4:0 are for debugging purposes only, not for operational use.
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4.4.3
Ring Resiliency Control
The following table shows the register settings for the ring resiliency controls at address 30E2.
Table 83 •
Bit
Name
Access
Description
Default
15
Ring resiliency
startup enable
(master TR enable)
R/W
Sticky
0
14
Advertise ring
resiliency
R/W
Sticky
0
13
LP ring resiliency
advertisement
RO
12
Force ring resiliency R/W
enable (override
autoneg)
Sticky
0
11:6
Reserved
RO
Reserved
000000
5:4
Ring resiliency
status
RO
Ring resiliency status (from r1000 DSP SM)
00: Timing slave(1)
10: Timing slave becoming master
11: Timing master(1)
01: Timing master becoming slave
11
3:1
Reserved
RO
Reserved
000
0
Start switchover
(only when not in
progress)
RWSC
1.
4.5
Ring Resiliency, Address 30E2
0
0
Reflects autoneg master/slave at initial link-up
Extended Page 3 Registers
To access the extended page 3 registers (16E3–30E3), enable extended register access by writing
0x0003 to register 31. For more information, see Table 67, page 111.
When extended page 3 register access is enabled, reads and writes to registers 16–30 affect the
extended registers 16E3–30E3 instead of those same registers in the IEEE-specified register space.
Registers 0–15 are not affected by the state of the extended page register access.
Writing 0x0000 to register 31 restores the main register access.
The following table lists the addresses and register names in the extended register page 3 space. These
registers are accessible only when the device register 31 is set to 0x0003.
Table 84 •
Extended Registers Page 3 Space
Address
Name
16E3
MAC SerDes PCS Control
17E3
MAC SerDes PCS Status
18E3
MAC SerDes Clause 37 Advertised Ability
19E3
MAC SerDes Clause 37 Link Partner Ability
20E3
MAC SerDes Status
21E3
Media SerDes Transmit Good Packet Counter
22E3
Media SerDes Transmit CRC Error Counter
VMDS-10510 VSC8574-02 Datasheet Revision 4.2
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Registers
Table 84 •
4.5.1
Extended Registers Page 3 Space (continued)
Address
Name
23E3
Media SerDes PCS Control
24E3
Media SerDes PCS Status
25E3
Media SerDes Clause 37 Advertised Ability
26E3
Media SerDes Clause 37 Link Partner Ability
27E3
Media SerDes status
28E3
Fiber Media CRC Good Counter
29E3
Fiber Media CRC Error Counter
30E3
Reserved
MAC SerDes PCS Control
The register at address 16E3 consists of the bits that provide access to and control over MAC SerDes
PCS block. The following table shows the settings available.
Table 85 •
MAC SerDes PCS Control, Address 16E3 (0x10)
Bit
Name
Access Description
15
MAC interface disable
R/W
Sticky bit.
0
1: 1000BASE-X MAC interface disable when
media link down.
14
MAC interface restart
R/W
Sticky bit.
1: 1000BASE-X MAC interface restart on
media link change.
0
13
MAC interface PD enable R/W
Sticky bit.
1: MAC interface autonegotiation parallel
detect enable.
0
12
MAC interface
autonegotiation restart
R/W
Self-clearing bit.
1: Restart MAC interface autonegotiation.
0
11
Force advertised ability
R/W
1: Force 16-bit advertised ability from register 0
18E3.
10:8
SGMII preamble control
R/W
000: No effect on the start of packet.
001
001: If both the first two nibbles of the 10/100
packet are not 0x5, a byte of 0x55 must be
prefixed to the output, otherwise there will be
no effect on the start of packet.
010: If both the first two nibbles of the 10/100
packet are not 0x5, a byte of 0x55 must be
prefixed to the output. An additional byte of
0x55 must be prefixed to the output if the
next two nibbles are also not 0x5.
011–111: Reserved.
7
MAC SerDes
autonegotiation enable
R/W
Sticky bit.
1: MAC SerDes ANEG enable.
6
SerDes polarity at input of R/W
MAC
1: Invert polarity of signal received at input of 0
MAC.
5
SerDes polarity at output R/W
of MAC
1: Invert polarity of signal at output of MAC.
VMDS-10510 VSC8574-02 Datasheet Revision 4.2
Default
0
122
Registers
Table 85 •
MAC SerDes PCS Control, Address 16E3 (0x10) (continued)
Bit
Name
Access Description
Default
4
Fast link status enable
R/W
1: Use fast link fail indication as link status
indication to MAC SerDes.
0: Use normal link status indication to MAC
SerDes.
0
3
Reserved
R/W
Reserved.
0
2:0
Reserved
RO
Reserved.
4.5.2
MAC SerDes PCS Status
The register at address 17E3 consists of the bits that provide status from the MAC SerDes PCS block.
The following table shows the settings available.
Table 86 •
4.5.3
MAC SerDes PCS Status, Address 17E3 (0x11)
Bit
Name
Access Description
15:13
Reserved
RO
Reserved
12
SGMII alignment error
RO
1: SGMII alignment error occurred
11
MAC interface LP autonegotiation
restart
RO
1: MAC interface link partner autonegotiation
restart request occurred
10
Reserved
RO
Reserved
9:8
MAC remote fault
RO
01, 10, and 11: Remote fault detected from
MAC
00: No remote fault detected from MAC
7
Asymmetric pause advertisement
RO
1: Asymmetric pause advertised by MAC
6
Symmetric pause advertisement
RO
1: Symmetric pause advertised by MAC
5
Full duplex advertisement
RO
1: Full duplex advertised by MAC
4
Half duplex advertisement
RO
1: Half duplex advertised by MAC
3
MAC interface LP autonegotiation
capable
RO
1: MAC interface link partner autonegotiation
capable
2
MAC interface link status
RO
1: MAC interface link status connected
1
MAC interface autonegotiation
complete
RO
1: MAC interface autonegotiation complete
0
MAC comma detect
RO
1: Comma currently detected
0: comma currently not detected
MAC SerDes Clause 37 Advertised Ability
The register at address 18E3 consists of the bits that provide access to and control over MAC SerDes
Clause 37 advertised ability. The following table shows the settings available.
Table 87 •
MAC SerDes Cl37 Advertised Ability, Address 18E3 (0x12)
Bit
Name
Access Description
15:0
MAC SerDes advertised R/W
ability
Current configuration code word being
advertised (this register is read/write if
16E3.11 = 1)
VMDS-10510 VSC8574-02 Datasheet Revision 4.2
Default
0x01E0
123
Registers
4.5.4
MAC SerDes Clause 37 Link Partner Ability
The register at address 19E3 consists of the bits that provide status of the MAC SerDes link partner's
Clause 37 advertised ability. The following table shows the settings available.
MAC SerDes Cl37 LP Ability, Address 19E3 (0x13)
Table 88 •
Bit
Name
15:0
MAC SerDes LP ability RO
4.5.5
Access Description
Last configuration code word received from link partner
MAC SerDes Status
The register at address 20E3 consists of the bits that provide access to MAC SerDes status. The
following table shows the settings available.
MAC SerDes Status, Address 20E3 (0x14)
Table 89 •
4.5.6
Bit
Name
Access Description
15
Reserved
RO
Reserved
14
MAC comma detect
RO
Super-sticky bit. Cleared upon SW reset.
1: Comma detected
0: Comma not detected
13
QSGMII sync status
RO
12:0
Reserved
RO
Reserved
Media SerDes Transmit Good Packet Counter
The register at address 21E3 consists of the bits that provide status of the media SerDes transmit good
packet counter. The following table shows the settings available.
Media SerDes Tx Good Packet Counter, Address 21E3 (0x15)
Table 90 •
4.5.7
Bit
Name
Access Description
15
Tx good packet counter active
RO
1: Transmit good packet counter active
14
Reserved
RO
Reserved
13:0
Tx good packet count
RO
Transmit good packet count modulo 10000
Media SerDes Transmit CRC Error Counter
The register at address 22E3 consists of the bits that provide status of the media SerDes transmit packet
count that had a CRC error. The following table shows the settings available.
Table 91 •
Media SerDes Tx CRC Error Counter, Address 22E3 (0x16)
Bit
Name
Access Description
15:8
Reserved
RO
7:0
Tx CRC packet count RO
Reserved
Transmit CRC packet count (saturates at 255)
VMDS-10510 VSC8574-02 Datasheet Revision 4.2
124
Registers
4.5.8
Media SerDes PCS Control
The register at address 23E3 consists of the bits that provide access to and control over Media SerDes
PCS control. The following table shows the settings available.
Table 92 •
4.5.9
Media SerDes PCS Control, Address 23E3 (0x17)
Bit
Name
Access Description
15:14
Reserved
RO
Reserved
13
Media interface autonegotiation
parallel-detection
R/W
Sticky bit.
1: SerDes media autonegotiation
parallel detect enabled
12
Reserved
RO
Reserved
11
Force advertised ability
R/W
1: Force 16-bit advertised ability
from register 25E3.15:0
10:7
Reserved
RO
Reserved
6
Polarity reversal input
Media SerDes polarity reversal
input
0: No polarity reversal (default)
1: Polarity reversed
0
5
Polarity reversal output
Media SerDes polarity reversal
output
0: No polarity reversal (default)
1: Polarity reversed
0
4:0
Reserved
RO
Default
0
0
Reserved
Media SerDes PCS Status
The register at address 24E3 consists of the bits that provide status of the Media SerDes PCS block. The
following table shows the settings available.
Table 93 •
Media SerDes PCS Status, Address 24E3 (0x18)
Bit
Name
Access Description
15:14
Reserved
RO
13
SerDes protocol transfer
RO
100 Mb or 100BASE-FX link status
12
SerDes protocol transfer
RO
10 Mb link status
11
Media interface link partner
autonegotiation restart
RO
1: Media interface link partner
autonegotiation restart request
occurred
10
Reserved
RO
Reserved
9:8
Remote fault detected
RO
01, 10, 11: Remote fault detected
from link partner
7
Link partner asymmetric pause
RO
1: Asymmetric pause advertised by
link partner
6
Link partner symmetric pause
RO
1: Symmetric pause advertised by
link partner
5
Link partner full duplex
advertisement
RO
1: Full duplex advertised by link
partner
4
Link partner half duplex
advertisement
RO
1: Half duplex advertised by link
partner
Reserved
VMDS-10510 VSC8574-02 Datasheet Revision 4.2
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Registers
Table 93 •
4.5.10
Media SerDes PCS Status, Address 24E3 (0x18) (continued)
Bit
Name
Access Description
3
Link partner autonegotiation
capable
RO
1: Media interface link partner
autonegotiation capable
2
Media interface link status
RO
1: Media interface link status
1
Media interface autonegotiation RO
complete
1: Media interface autonegotiation
complete
0
Reserved
Reserved
Media SerDes Clause 37 Advertised Ability
The register at address 25E3 consists of the bits that provide access to and control over Media SerDes
Clause 37 advertised ability. The following table shows the settings available.
Media SerDes Cl37 Advertised Ability, Address 25E3 (0x19)
Table 94 •
Bit
Name
Access Description
Default
15:0
Media SerDes
advertised ability
R/W
0x0000
4.5.11
Current configuration code word being advertised.
This register is read/write when 23E3.11 = 1.
Media SerDes Clause 37 Link Partner Ability
The register at address 26E3 consists of the bits that provide status of the media SerDes link partner's
Clause 37 advertised ability. The following table shows the settings available.
Table 95 •
MAC SerDes Cl37 LP Ability, Address 26E3 (0x1A)
Bit
Name
15:0
Media SerDes LP ability RO
4.5.12
Access Description
Last configuration code word received from link partner
Media SerDes Status
The register at address 27E3 consists of the bits that provide access to Media SerDes status. The
following table shows the settings available.
Table 96 •
Media SerDes Status, Address 27E3 (0x1B)
Bit
Name
Access Description
15
K28.5 comma realignment
RO
Self-clearing bit.
1: K28.5 comma re-alignment has occurred
14
Signal detect
RO
Self-clearing bit. Sticky bit.
1: SerDes media signal detect
13:0
Reserved
RO
Reserved
VMDS-10510 VSC8574-02 Datasheet Revision 4.2
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Registers
4.5.13
Fiber Media CRC Good Counter
Register 28E3 makes it possible to read the contents of the CRC good counter for packets that are
received on the Fiber media interface; the number of CRC routines that have executed successfully. The
following table shows the expected readouts.
Fiber Media CRC Good Counter, Address 28E3 (0x1C)
Table 97 •
Bit
Name
Access Description
Default
15
Packet since last read
RO
Self-clearing bit.
1: Packet received since last read.
0
14
Reserved
RO
Reserved.
13:0
Fiber media CRC good
counter contents
RO
Self-clearing bit. Counter containing the
number of packets with valid CRCs. This
counter does not saturate and will roll over.
4.5.14
0x000
Fiber Media CRC Error Counter
Register 29E3 makes it possible to read the contents of the CRC error counter for packets that are
received on the Fiber media interface. The following table shows the expected readouts.
Table 98 •
4.6
Fiber Media CRC Error Counter, Address 29E3 (0x1D)
Bit
Name
Access Description
15:8
Reserved
RO
7:0
Fiber Media CRC RO
error counter
Default
Reserved.
Self-clearing bit. CRC error counter for packets
received on the Fiber media interface. The value
saturates at 0xFF and subsequently clears when
read and restarts count.
0x00
General Purpose Registers
Accessing the general purpose register space is similar to accessing the extended page registers. Set
register 31 to 0x0010. This sets all 32 registers to the general purpose register space.
To restore main register page access, write 0x0000 to register 31.
The following table lists the addresses and register names in the general purpose register page space.
These registers are accessible only when the device register 31 is set to 0x0010. All general purpose
register bits are super-sticky. This register space is global in nature to all four PHY’s in the VSC8574-02
device.
Table 99 •
General Purpose Registers Page Space
Address
Name
0G–12G
Reserved
13G
LED/SIGDET/GPIO Control
14G
GPIO Control 2
15G
GPIO Input
16G
GPIO Output
17G
GPIO Output Enable
18G
Micro Command
19G
MAC Mode and Fast Link Configuration
VMDS-10510 VSC8574-02 Datasheet Revision 4.2
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Registers
Table 99 •
4.6.1
General Purpose Registers Page Space (continued)
Address
Name
20G
Two-Wire Serial MUX Control 1
21G
Two-Wire Serial MUX Control 2
22G
Two-Wire Serial MUX Data Read/Write
23G
Recovered Clock 0 Control
24G
Recovered Clock 1 Control
25G
Enhanced LED Control
26G
Reserved
27G
Reserved
28G
Reserved
29G
Global Interrupt Status
30G
Extended Revision ID
Reserved General Purpose Address Space
The bits in registers 0G to 12G of the general purpose register space are reserved.
4.6.2
SIGDET/GPIO Control
The SIGDET control bits configure the GPIO[3:0]/SIGDET[3:0] pins to function either as signal detect
pins for each fiber media port, or as GPIOs. The following table shows the values that can be written.
Table 100 • SIGDET/GPIO Control, Address 13G (0x0D)
Bit
Name
Access Description
15:14
GPIO7/I2C_SCL_3 R/W
00: SCL for PHY3
01: Reserved
10: Reserved
11: Controlled by MII registers 15G to 17G1
00
13:12
GPIO6/I2C_SCL_2 R/W
00: SCL for PHY2
01: Reserved
10: Reserved
11: Controlled by MII registers 15G to 17G2
00
11:10
GPIO5/I2C_SCL_1 R/W
00: SCL for PHY1
01: Reserved
10: Reserved
11: Controlled by MII registers 15G to 17G3
00
9:8
GPIO4/I2C_SCL_0 R/W
00: SCL for PHY0
01: Reserved
10: Reserved
11: Controlled by MII registers 15G to 17G4
00
7:6
GPIO3/SIGDET3
control
R/W
00: SIGDET operation
01: Reserved
10: Reserved
11: Controlled by MII registers 15G to 17G
00
5:4
GPIO2/SIGDET2
control
R/W
00: SIGDET operation
01: Reserved
10: Reserved
11: Controlled by MII registers 15G to 17G
00
VMDS-10510 VSC8574-02 Datasheet Revision 4.2
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128
Registers
Table 100 • SIGDET/GPIO Control, Address 13G (0x0D) (continued)
Bit
Name
Access Description
Default
3:2
GPIO1/SIGDET1
control
R/W
00: SIGDET operation
01: Reserved
10: Reserved
11: Controlled by MII registers 15G to 17G
00
1:0
GPIO0/SIGDET0
control
R/W
00: SIGDET operation
01: Reserved
10: Reserved
11: Controlled by MII registers 15G to 17G
00
1.
2.
3.
4.
4.6.3
Register 20G bit 3 must be clear in order for this setting to take effect.
Register 20G bit 2 must be clear in order for this setting to take effect.
Register 20G bit 1 must be clear in order for this setting to take effect.
Register 20G bit 0 must be clear in order for this setting to take effect.
GPIO Control 2
The GPIO control 2 register configures the functionality of the COMA_MODE and 1588 control input
pins, and provides control for possible GPIO pin options.
Table 101 • GPIO Control 2, Address 14G (0x0E)
Bit
Name
Access Description
15:14
GPIO12/1588_SPI_CS
and
GPIO13/1588_SPI_DO
R/W
GPIO12/1588_SPI_CS and
GPIO13/1588_SPI_DO control.
00: 1588_SPI_CS/1588_SPI_DO
operation.
01: Reserved.
10: Reserved.
11: GPIO12/GPIO13 operation. Controlled
by MII registers 15G to 17G.
13
COMA_MODE output
enable (active low)
R/W
1: COMA_MODE pin is an input.
0: COMA_MODE pin is an output.
1
12
COMA_MODE output
data
R/W
Value to output on the COMA_MODE pin
when it is configured as an output.
0
11
COMA_MODE input data RO
Data read from the COMA_MODE pin.
10
Tri-state enable for
two-wire serial bus
R/W
1: Tri-states two-wire serial bus output
signals instead of driving them high. This
allows those signals to be pulled above
VDD25 using an external pull-up resistor.
0: Drive two-wire serial bus output signals
to high and low values as appropriate.
9
Tri-state enable for LEDs
R/W
1
1: Tri-state LED output signals instead of
driving them high. This allows the signals
to be pulled above VDDIO using an external
pull-up resistor.
0: Drive LED bus output signals to high and
low values.
8
Reserved
RO
Reserved
VMDS-10510 VSC8574-02 Datasheet Revision 4.2
Default
1
0
129
Registers
Table 101 • GPIO Control 2, Address 14G (0x0E) (continued)
Bit
Name
Access Description
7:6
GPIO11
R/W
GPIO11 control.
00: Reserved
01: Reserved
10: Reserved
11: Controlled by MII registers 15G to 17G
5:4
GPIO10/1588_LOAD_SA R/W
VE
GPIO10/1588_LOAD_SAVE control.
00: 1588_LOAD_SAVE operation
01: Reserved
10: Reserved
11: Controlled by MII registers 15G to 17G
3:2
GPIO9/FASTLINK_FAIL
R/W
GPIO9/FASTLINK_FAIL control.
00: FASTLINK_FAIL operation
01: Reserved
10: Reserved
11: Controlled by MII registers 15G to 17G
1:0
GPIO8/I2C_SDA
R/W
GPIO8/I2C_SDA control.
00: I2C_SDA operation
01: Reserved
10: Reserved
11: Controlled by MII registers 15G to 17G
4.6.4
Default
GPIO Input
The input register contains information about the input to the device GPIO pins. Read from this register to
access the data on the device GPIO pins. The following table shows the readout you can expect.
Table 102 • GPIO Input, Address 15G (0x0F)
Bit
Name
Access Description
Default
15:14
Reserved
RO
Reserved
00
13
GPIO13/1588_SPI_DO
RO
GPIO13/1588_SPI_DO input
1
12
GPIO12/1588_SPI_CS
RO
GPIO12/1588_SPI_CS input
1
11
GPIO11
RO
GPIO11 input
0
10
GPIO10/1588_LOAD_SAVE RO
GPIO10/1588_LOAD_SAVE input
0
9
GPIO9/FASTLINK_FAIL
RO
GPIO9/FASTLINK_FAIL input
1
8
GPIO8/I2C_SDA
RO
GPIO8/I2C_SDA input
1
7
GPIO7/I2C_SCL_3
RO
GPIO7/I2C_SCL_3 input
1
6
GPIO6/I2C_SCL_2
RO
GPIO6/I2C_SCL_2 input
1
5
GPIO5/I2C_SCL_1
RO
GPIO5/I2C_SCL_1 input
1
4
GPIO4/I2C_SCL_0
RO
GPIO4/I2C_SCL_0 input
1
3
GPIO3/SIGDET3
RO
GPIO3/SIGDET3 input
1
2
GPIO2/SIGDET2
RO
GPIO2/SIGDET2 input
1
1
GPIO1/SIGDET1
RO
GPIO1/SIGDET1 input
1
0
GPIO0/SIGDET0
RO
GPIO0/SIGDET0 input
0
VMDS-10510 VSC8574-02 Datasheet Revision 4.2
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Registers
4.6.5
GPIO Output
The output register allows you to access and control the output from the device GPIO pins. The following
table shows the values you can write.
Table 103 • GPIO Output, Address 16G (0x10)
Bit
Name
Access Description
15:14
Reserved
RO
Reserved
Default
13
GPIO13/1588_SPI_DO
R/W
GPIO13/1588_SPI_DO output
0
12
GPIO12/1588_SPI_CS
R/W
GPIO12/1588_SPI_CS output
0
11
GPIO11
R/W
GPIO11 output
0
10
GPIO10/1588_LOAD_SAVE
R/W
GPIO10/1588_LOAD_SAVE output 0
9
GPIO9/FASTLINK_FAIL
R/W
GPIO9/FASTLINK_FAIL output
0
8
GPIO8/I2C_SDA
R/W
GPIO8/I2C_SDA output
0
7
GPIO7/I2C_SCL_3
R/W
GPIO7/I2C_SCL_3 output
0
6
GPIO6/I2C_SCL_2
R/W
GPIO6/I2C_SCL_2 output
0
5
GPIO5/I2C_SCL_1
R/W
GPIO5/I2C_SCL_1 output
0
4
GPIO4/I2C_SCL_0
R/W
GPIO4/I2C_SCL_0 output
0
3
GPIO3/SIGDET3
R/W
GPIO3/SIGDET3 output
0
2
GPIO2/SIGDET2
R/W
GPIO2/SIGDET2 output
0
1
GPIO1/SIGDET1
R/W
GPIO1/SIGDET1 output
0
0
GPIO0/SIGDET0
R/W
GPIO0/SIGDET0 output
0
4.6.6
GPIO Pin Configuration
Register 17G in the GPIO register space controls whether a particular GPIO pin functions as an input or
an output. The following table shows the settings available.
Table 104 • GPIO Input/Output Configuration, Address 17G (0x11)
Bit
Name
Access Description
15:14
Reserved
RO
Reserved
13
GPIO13/1588_SPI_DO
R/W
GPIO13/1588_SPI_DO output enable
0
12
GPIO12/1588_SPI_CS
R/W
GPIO12/1588_SPI_CS output enable
0
11
GPIO11
R/W
GPIO11 output enable
0
10
GPIO10/1588_LOAD_SAVE R/W
GPIO10/1588_LOAD_SAVE output
enable
0
9
GPIO9/FASTLINK_FAIL
R/W
GPIO9/FASTLINK_FAIL output enable
0
8
GPIO8/I2C_SDA
R/W
GPIO8/I2C_SDA output enable
0
7
GPIO7/I2C_SCL_3
R/W
GPIO7/I2C_SCL_3 output enable
0
6
GPIO6/I2C_SCL_2
R/W
GPIO6/I2C_SCL_2 output enable
0
5
GPIO5/I2C_SCL_1
R/W
GPIO5/I2C_SCL_1 output enable
0
4
GPIO4/I2C_SCL_0
R/W
GPIO4/I2C_SCL_0 output enable
0
3
GPIO3/SIGDET3
R/W
GPIO3/SIGDET3 output enable
0
2
GPIO2/SIGDET2
R/W
GPIO2/SIGDET2 output enable
0
VMDS-10510 VSC8574-02 Datasheet Revision 4.2
Default
131
Registers
Table 104 • GPIO Input/Output Configuration, Address 17G (0x11) (continued)
Bit
Name
Access Description
Default
1
GPIO1/SIGDET1
R/W
GPIO1/SIGDET1 output enable
0
0
GPIO0/SIGDET0
R/W
GPIO0/SIGDET0 output
0
4.6.7
Microprocessor Command
Register 18G is a command register. Bit 15 tells the internal processor to execute the command. When
bit 15 is cleared the command has completed. Software needs to wait until bit 15 = 0 before proceeding
with the next PHY register access. Bit 14 = 1 typically indicates an error condition where the squelch
patch was not loaded. Use the following steps to execute the command:
1. Write desired command
2. Check bit 15 (move existing text)
3. Check bit 14 (if set, then error)
Note: Commands may take up to 25 ms to complete before bit 15 changes to 0.
Table 105 • Microprocessor Command Register, Address 18G
Command
Setting
Enable 4 ports MAC SGMII
0x80F0
Enable 4 ports MAC QSGMII
0x80E0
QSGMII transmitter
1588 initialization(2)
0x801A
Enable 4 ports Media 1000BASE-X
0x8FC1(3)
Enable 4 ports Media 100BASE-FX
0x8FD1(3)
1.
Contact your Microsemi representative for an initialization script that greatly simplifies the programming
of QSGMII transmit controls.
Initializes six analyzers in both 1588 IP blocks A and B. This needs to be done after reset and before
the 1588 blocks are used.
The “F” in the command has a bit representing each of the four PHYs. To exclude a PHY from the
configuration, set its bit to 0. For example, the configuration of PHY 3 and PHY 2 to 1000BASE-X would
be 1100 or a “C” and the command would be 0x8CC1.
2.
3.
4.6.8
control(1)
MAC Configuration and Fast Link
Register 19G in the GPIO register space controls the MAC interface mode and the selection of the
source PHY for the fast link failure indication. The following table shows the settings available for the
GPIO9/FASTLINK-FAIL pin.
Table 106 • MAC Configuration and Fast Link Register, Address 19G (0x13)
Bit
Name
Access Description
Default
15:14
MAC configuration
R/W
Select MAC interface mode
00: SGMII
01: QSGMII
10: Reserved
11: Reserved
00
13:4
Reserved
RO
Reserved
VMDS-10510 VSC8574-02 Datasheet Revision 4.2
132
Registers
Table 106 • MAC Configuration and Fast Link Register, Address 19G (0x13) (continued)
Bit
Name
Access Description
Default
3:0
Fast link failure port setting
R/W
0xF
4.6.9
Select fast link failure PHY source
0000: Port0
0001: Port1
0010: Port2
0011: Port3
1100–1111: Output disabled
Two-Wire Serial MUX Control 1
The following table shows the settings available to control the integrated two-wire serial MUX.
Table 107 • Two-Wire Serial MUX Control 1, Address 20G (0x14)
Bit
Name
Access Description
15:9
Two-wire serial
device address
R/W
Top 7 bits of the 8-bit address sent out on the two 0xA0
wire serial stream. The bottom bit is the
read/write signal, which is controlled by register
21G, bit 8. SFPs use 0xA0.
8:6
Reserved
RO
Reserved.
5:4
Two-wire serial SCL
clock frequency
R/W
00: 50 kHz
01: 100 kHz
10: 400 kHz
11: 2 MHz
3
Two-wire serial MUX
port 3 enable
R/W
1: Enabled.
0
0: Two-wire serial disabled. Becomes GPIO pin.
2
Two-wire serial MUX
port 2 enable
R/W
1: Enabled.
0
0: Two-wire serial disabled. Becomes GPIO pin.
1
Two-wire serial MUX
port 1 enable
R/W
1: Enabled.
0
0: Two-wire serial disabled. Becomes GPIO pin.
0
Two-wire serial MUX
port 0 enable
R/W
1: Enabled.
0
0: Two-wire serial disabled. Two-wire serial MUX
port 0 becomes GPIO pin if serial LED function is
enabled, regardless of the settings of this bit.
4.6.10
Default
01
Two-Wire Serial MUX Control 2
Register 21G is used to control the two-wire serial MUX for status and control of two-wire serial slave
devices.
Table 108 • Two-Wire Serial MUX Interface Status and Control, Address 21G (0x15)
Bit
Name
Access Description
Default
15
Two-wire serial MUX
ready
RO
1: Two-wire serial MUX is ready for read or
write
1
14:12
Reserved
RO
Reserved
11:10
PHY port Address
R/W
Specific VSC8574-02 PHY port being
addressed.
VMDS-10510 VSC8574-02 Datasheet Revision 4.2
00
133
Registers
Table 108 • Two-Wire Serial MUX Interface Status and Control, Address 21G (0x15) (continued)
Bit
Name
Access Description
9
Enable two-wire serial
MUX access
R/W
Self-clearing bit.
0
1: Execute read or write through the two-wire
serial MUX based on the settings of register
bit 21G.8
8
Two-wire serial MUX
read or write
R/W
1: Read from two-wire serial MUX
0: Write to two-wire serial MUX
7:0
Two-wire serial MUX
address
R/W
Sets the address of the two-wire serial MUX 0x00
used to direct read or write operations.
4.6.11
Default
1
Two-Wire Serial MUX Data Read/Write
Register 22G in the extended register space enables access to the two-wire serial MUX.
Table 109 • Two-Wire Serial MUX Data Read/Write, Address 22G (0x16)
Bit
Name
15:8
Two-wire serial MUX RO
read data
Eight-bit data read from two-wire serial MUX;
requires setting both register 21G.9 and 21G.8 to
1.
7:0
Two-wire serial MUX R/W
write data
Eight-bit data to be written to two-wire serial MUX. 0x00
4.6.12
Access Description
Default
Recovered Clock 1 Control
Register 23G in the extended register space controls the functionality of the recovered clock 1 output
signal.
Table 110 • Recovered Clock 1 Control, Address 23G (0x17)
Bit
Name
Access Description
Default
15
Enable
RCVRDCLK1
R/W
1: Enable recovered clock 1 output
0: Disable recovered clock 1 output
0
14:11
Clock source select R/W
Select bits for source PHY for recovered clock:
0000: PHY0
0001: PHY1
0010: PHY2
0011: PHY3
0100–1111: Reserved
0000
10:8
Clock frequency
select
R/W
Select output clock frequency:
000: 25 MHz output clock
001: 125 MHz output clock
010: 31.25 MHz output clock
011–111: Reserved
000
7:6
Reserved
RO
Reserved.
VMDS-10510 VSC8574-02 Datasheet Revision 4.2
134
Registers
Table 110 • Recovered Clock 1 Control, Address 23G (0x17) (continued)
Bit
Name
Access Description
5:4
Clock squelch level R/W
Default
Select clock squelch level
00: Automatically squelch clock to low when the
link is not up, is unstable, is up in a mode that
does not support the generation of a recovered
clock (1000BASE-T master or 10BASE-T), or is
up in EEE mode (100BASE-TX or 1000BASE-T
slave).
01: Same as 00 except that the clock is also
generated in 1000BASE-T master and 10BASE-T
link-up modes. This mode also generates a
recovered clock output in EEE mode during
reception of LP_IDLE.
10: Squelch only when the link is not up.
11: Disable clock squelch.
Note: A clock from the SerDes or Cu PHY
will be output on the recovered
clock output in this mode when the
link is down.
When the CLK_SQUELCH_IN pin is set high, it
squelches the recovered clocks regardless of bit
settings.
3
Reserved
RO
Reserved.
2:0
Clock selection for
specified PHY
R/W
000: Serial media recovered clock
001: Copper PHY recovered clock
010: Copper PHY transmitter TCLK
011–111: Reserved
4.6.13
000
Recovered Clock 2 Control
Register 24G in the extended register space controls the functionality of the recovered clock 2 output
signal.
Table 111 • Recovered Clock 2 Control, Address 24G (0x18)
Bit
Name
Access Description
15
Enable RCVRDCLK2 R/W
Enable recovered clock 2 output
14:11
Clock source select
R/W
Select bits for source PHY for recovered clock: 0000
0000: PHY0
0001: PHY1
0010: PHY2
0011: PHY3
0100–1111: Reserved
10:8
Clock frequency
select
R/W
Select output clock frequency:
000: 25 MHz output clock
001: 125 MHz output clock
010: 31.25 MHz output clock
011–111: Reserved
7:6
Reserved
RO
Reserved
VMDS-10510 VSC8574-02 Datasheet Revision 4.2
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0
000
135
Registers
Table 111 • Recovered Clock 2 Control, Address 24G (0x18) (continued)
Bit
Name
Access Description
5:4
Clock squelch level
R/W
Default
Select clock squelch level:
00: Automatically squelch clock to low when the
link is not up, is unstable, is up in a mode that
does not support the generation of a recovered
clock (1000BASE-T master or 10BASE-T), or is
up in EEE mode (100BASE-TX or 1000BASE-T
slave).
01: Same as 00 except that the clock is also
generated in 1000BASE-T master and
10BASE-T link-up modes. This mode also
generates a recovered clock output in EEE
mode during reception of LP_IDLE
10: Squelch only when the link is not up
11: Disable clock squelch.
Note: A clock from the SerDes or Cu
PHY will be output on the
recovered clock output in this
mode when the link is down.
Note: A clock from the SerDes or Cu
PHY will be output on the
recovered clock output in this
mode when the link is down.
When the CLK_SQUELCH_IN pin is set high, it
squelches the recovered clocks regardless of
bit settings.
3
Reserved
RO
Reserved
2:0
Clock selection for
specified PHY
R/W
000: Serial media recovered clock
001: Copper PHY recovered clock
010–111: Reserved
4.6.14
000
Enhanced LED Control
The following table contains the bits to control advanced functionality of the parallel and serial LED
signals.
Table 112 • Enhanced LED Control, Address 25G (0x19)
Bit
Name
Access Description
15:8
LED pulsing duty cycle
control
R/W
7
Port 1 enhanced serial LED R/W
output enable
Default
Programmable control for LED pulsing
00
duty cycle when bit 30.12 is set to 1. Valid
settings are between 0 and 198. A setting
of 0 corresponds to a 0.5% duty cycle and
198 corresponds to a 99.5% duty cycle.
Intermediate values change the duty cycle
in 0.5% increments
Enable the enhanced serial LED output
functionality for port 1 LED pins.
1: Enhanced serial LED outputs
0: Normal function
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136
Registers
Table 112 • Enhanced LED Control, Address 25G (0x19) (continued)
Bit
Name
6
Port 0 enhanced serial LED R/W
output enable
Enable the enhanced serial LED output
functionality for port 0 LED pins.
1: Enhanced serial LED outputs
0: Normal function
5:3
Serial LED frame rate
selection
R/W
Select frame rate of serial LED stream
000: 2500 Hz frame rate
001: 1000 Hz frame rate
010: 500 Hz frame rate
011: 250 Hz frame rate
100: 200 Hz frame rate
101: 125 Hz frame rate
110: 40 Hz frame rate
111: Output basic serial LED stream
See Table 30, page 78.
2:1
Serial LED select
R/W
Select which LEDs from each PHY to
enable on the serial stream
00: Enable all four LEDs of each PHY
01: Enable LEDs 2, 1 and 0 of each PHY
10: Enable LEDs 1 and 0 of each PHY
11: Enable LED 0 of each PHY
0
LED port swapping
R/W
See LED Port Swapping, page 78.
4.6.15
Access Description
Default
0
00
Global Interrupt Status
The following table contains the interrupt status from the various sources to indicate which one caused
that last interrupt on the pin.
Table 113 • Global Interrupt Status, Address 29G (0x1D)
Bit
Name
Access Default Description
15:12
Reserved
RO
0001
Reserved
11
PHY3
1588(1)
RO
1
PHY3 1588 interrupt source indication
0: PHY3 1588 caused the interrupt
1: PHY3 1588 did not cause the interrupt
10
PHY2 1588(1)
RO
1
PHY 2 1588 interrupt source indication
0: PHY2 1588 caused the interrupt
1: PHY2 1588 did not cause the interrupt
9
PHY1 1588(1)
RO
1
PHY 1 1588 interrupt source indication
0: PHY1 1588 caused the interrupt
1: PHY1 1588 did not cause the interrupt
8
PHY0 1588(1)
RO
1
PHY 0 1588 interrupt source indication
0: PHY0 1588 caused the interrupt
1: PHY0 1588 did not cause the interrupt
7:4
Reserved
R
1111
Reserved
source(1)
3
PHY3 interrupt
RO
1
PHY3 interrupt source indication
0: PHY3 caused the interrupt
1: PHY3 did not cause the interrupt
2
PHY2 interrupt source(1) RO
1
PHY2 interrupt source indication
0: PHY2 caused the interrupt
1: PHY2 did not cause the interrupt
VMDS-10510 VSC8574-02 Datasheet Revision 4.2
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Registers
Table 113 • Global Interrupt Status, Address 29G (0x1D) (continued)
Bit
Name
1
PHY1 interrupt source(1) RO
1
PHY1 interrupt source indication
0: PHY1 caused the interrupt
1: PHY1 did not cause the interrupt
0
PHY0 interrupt source(1) RO
1
PHY0 interrupt source indication
0: PHY0 caused the interrupt
1: PHY0 did not cause the interrupt
1.
Access Default Description
This bit is set to 1 when the corresponding PHY’s Interrupt Status register 26 (0x1A) is read.
For information about 1588 IP register access, see Accessing 1588 IP Registers, page 71.
4.6.16
Extended Revision ID
The following table lists the extended revision ID information.
Table 114 • Extended Revision ID, Address 30G (0x1E)
4.7
Bit
Name
Access Default
Description
15:1
Reserved
RO
0x0000
Reserved
0
Ext Rev ID
RO
0x1
Revision E
Clause 45 Registers to Support Energy Efficient Ethernet
and 802.3bf
This section describes the Clause 45 registers that are required to support energy efficient Ethernet.
Access to these registers is through the IEEE standard registers 13 and 14 (MMD access control and
MMD data or address registers) as described in section 4.2.11 and 4.2.12.
The following table lists the addresses and register names in the Clause 45 register page space. When
the link is down, 0 is the value returned for the x.180x addresses.
Table 115 • Clause 45 Registers Page Space
Address
Name
1.1801
Tx maximum delay through PHY (PMA/PMD/PCS, until 1588 block)
1.1803
Tx minimum delay through PHY (PMA/PMD/PCS, until 1588 block)
1.1805
Rx maximum delay through PHY (PMA/PMD/PCS, until 1588 block)
1.1807
Rx minimum delay through PHY (PMA/PMD/PCS, until 1588 block)
3.1
PCS status 1
3.1801
Tx maximum delay through 1588
3.1803
Tx minimum delay through 1588
3.1805
Rx maximum delay through 1588
3.1807
Rx minimum delay through 1588
3.20
EEE capability
3.22
EEE wake error counter
4.1801
Tx maximum delay through xMII (SGMII, QSGMII, including FIFO variations)
4.1803
Tx minimum delay through xMII (SGMII, QSGMII, including FIFO variations)
4.1805
Rx maximum delay through xMII (SGMII, QSGMII, including FIFO variations)
VMDS-10510 VSC8574-02 Datasheet Revision 4.2
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Registers
Table 115 • Clause 45 Registers Page Space (continued)
Address
Name
4.1807
Rx minimum delay through xMII (SGMII, QSGMII, including FIFO variations)
7.60
EEE advertisement
7.61
EEE link partner advertisement
4.7.1
PCS Status 1
The bits in the PCS Status 1 register provide a status of the EEE operation from the PCS for the link that
is currently active.
Table 116 • PCS Status 1, Address 3.1
4.7.2
Bit
Name
Access Description
15:12
Reserved
RO
Reserved
11
Tx LPI received
RO/LH
1: Tx PCS has received LPI
0: LPI not received
10
Rx LPI received
RO/LH
1: Rx PCS has received LPI
0: LPI not received
9
Tx LPI indication
RO
1: Tx PCS is currently receiving LPI
0: PCS is not currently receiving LPI
8
Rx LPI indication
RO
1: Rx PCS is currently receiving LPI
0: PCS is not currently receiving LPI
7:3
Reserved
RO
Reserved
2
PCS receive link status RO
1: PCS receive link up
0: PCS receive link down
1:0
Reserved
Reserved
RO
EEE Capability
This register is used to indicate the capability of the PCS to support EEE functions for each PHY type.
The following table shows the bit assignments for the EEE capability register.
Table 117 • EEE Capability, Address 3.20
4.7.3
Bit
Name
Access Description
15:3
Reserved
RO
2
1000BASE-T EEE RO
1: EEE is supported for 1000BASE-T
0: EEE is not supported for 1000BASE-T
1
100BASE-TX
EEE
RO
1: EEE is supported for 100BASE-TX
0: EEE is not supported for 100BASE-TX
0
Reserved
RO
Reserved
Reserved
EEE Wake Error Counter
This register is used by PHY types that support EEE to count wake time faults where the PHY fails to
complete its normal wake sequence within the time required for the specific PHY type. The definition of
the fault event to be counted is defined for each PHY and can occur during a refresh or a wakeup as
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Registers
defined by the PHY. This 16-bit counter is reset to all zeros when the EEE wake error counter is read or
when the PHY undergoes hardware or software reset.
Table 118 • EEE Wake Error Counter, Address 3.22
4.7.4
Bit
Name
Access Description
15:0
Wake error counter
RO
Count of wake time faults for a PHY
EEE Advertisement
This register defines the EEE advertisement that is sent in the unformatted next page following a EEE
technology message code. The following table shows the bit assignments for the EEE advertisement
register.
Table 119 • EEE Advertisement, Address 7.60
Bit
Name
Access Description
15:3
Reserved
RO
2
1000BASE-T EEE R/W
1: Advertise that the 1000BASE-T has EEE
capability
0: Do not advertise that the 1000BASE-T has EEE
capability
0
1
100BASE-TX
EEE
R/W
1: Advertise that the 100BASE-TX has EEE
capability
0: Do not advertise that the 100BASE-TX has EEE
capability
0
0
Reserved
RO
Reserved
4.7.5
Default
Reserved
EEE Link Partner Advertisement
All the bits in the EEE LP Advertisement register are read only. A write to the EEE LP advertisement
register has no effect. When the AN process has been completed, this register will reflect the contents of
the link partner's EEE advertisement register. The following table shows the bit assignments for the EEE
advertisement register.
Table 120 • EEE Advertisement, Address 7.61
Bit
Name
Access Description
15:3
Reserved
RO
2
1000BASE-T EEE RO
1: Link partner is advertising EEE capability for 1000BASE-T
0: Link partner is not advertising EEE capability for
1000BASE-T
1
100BASE-TX
EEE
RO
1: Link partner is advertising EEE capability for 100BASE-TX
0: Link partner is not advertising EEE capability for
100BASE-TX
0
Reserved
RO
Reserved
Reserved
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Registers
The following table shows the bit assignments for the 802.3bf registers. When the link is down, 0 is the
value returned. cl45reg1_1801 would be device address of 1 and register address of 1801.
Table 121 • 802.3bf Registers
Register
Name
Function
1.1801
cl45reg1_1801_val[15:0]
Tx maximum delay through PHY (PMA/PMD/PCS,
until 1588 block)
1.1803
cl45reg1_1803_val[15:0]
Tx minimum delay through PHY (PMA/PMD/PCS,
until 1588 block)
1.1805
cl45reg1_1805_val[15:0]
Rx maximum delay through PHY (PMA/PMD/PCS,
until 1588 block)
1.1807
cl45reg1_1807_val[15:0]
Rx minimum delay through PHY (PMA/PMD/PCS,
until 1588 block)
3.1801
cl45reg3_1801_val[15:0]
Tx maximum delay through 1588
3.1803
cl45reg3_1803_val[15:0]
Tx minimum delay through 1588
3.1805
cl45reg3_1805_val[15:0]
Rx maximum delay through 1588
3.1807
cl45reg3_1807_val[15:0]
Rx minimum delay through 1588
4.1801
cl45reg4_1801_val[15:0]
Tx maximum delay through xMII (SGMII, QSGMII,
including FIFO variations)
4.1803
cl45reg4_1803_val[15:0]
Tx minimum delay through xMII (SGMII, QSGMII,
including FIFO variations)
4.1805
cl45reg4_1805_val[15:0]
Rx maximum delay through xMII (SGMII, QSGMII,
including FIFO variations)
4.1807
cl45reg4_1807_val[15:0]
Rx minimum delay through xMII (SGMII, QSGMII,
including FIFO variations)
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4.8
1588 IP Registers
This section provides information about the 1588 IP programming interface, register maps, register
descriptions, and register tables of the device.
In writing to registers with reserved bits, use a read-modify-write technique, where the entire register is
read, but with only the user bits to be chance are modified. Do not change the values of the register and
bits marked as reserved. Their read state should not be considered static or unchanging. Unspecified
registers and bits must be written to 0 and can be ignored when read.
The first-level table lists all register targets and associated base addresses. The second-level table lists
registers groups and offsets within targets, and the third-level tables list registers within the register
groups.
Both register groups and registers may be replicated (repeated) a number of times. The repeat-count
and the distance between two repetitions are listed in the Instances and Address Spacing column.
Spacing is omitted if there is only one instance. The Offset within Target and the Offset within Register
Group columns hold the offset of the first instance of the register group or register.
Use the following steps to calculate the absolute address of a given register.
1.
2.
3.
4.
5.
Multiply the register group's replication number by the register group's address spacing.
Add the result to the register group's offset within the target.
Multiply the register's replication number with the register's address spacing.
Add the result to the register's offset within the register group.
Add these two numbers to the absolute address of the target in question.
Table 122 • Register Groups in IP_1588
Register Group Name
Instances
Offset within and Address
Target
Spacing
Description
Details
IP_1588_TOP_CFG_STAT
0x00000000
1
1588 IP control and status
registers
Page 143
IP_1588_LTC
0x00000040
1
1588 IP local time counter
Page 144
TS_FIFO_SI
0x00000080
1
Timestamp FIFO serial
interface registers
Page 149
INGR_PREDICTOR
0x00000088
1
Ingress (Rx) registers
Page 150
EGR_PREDICTOR
0x00000098
1
Egress (Tx) registers
Page 152
INGR_IP_1588_CFG_STAT
0x000000B4
1
1588 IP control and status
registers
Page 155
INGR_IP_1588_TSP
0x000000D4
1
1588 IP timestamp processor
Page 157
INGR_IP_1588_DF
0x000000E8
1
1588 IP delay FIFO
Page 159
INGR_IP_1588_TSFIFO
0x000000EC
1
1588 IP timestamp FIFO
Page 160
INGR_IP_1588_RW
0x00000110
1
1588 IP rewriter
Page 164
EGR_IP_1588_CFG_STAT
0x00000134
1
1588 IP control and status
registers
Page 165
EGR_IP_1588_TSP
0x00000154
1
1588 IP timestamp processor
Page 168
EGR_IP_1588_DF
0x00000168
1
1588 IP delay FIFO
Page 170
EGR_IP_1588_TSFIFO
0x0000016C
1
1588 IP timestamp FIFO
Page 170
EGR_IP_1588_RW
0x00000190
1
1588 IP rewriter
Page 175
INGR_IP_1588_DEBUG_REGISTERS 0x0000027C
1
Software pop FIFO
Page 178
VMDS-10510 VSC8574-02 Datasheet Revision 4.2
142
Table 122 • Register Groups in IP_1588 (continued)
Register Group Name
Instances
Offset within and Address
Target
Spacing
Description
Details
EGR_IP_1588_DEBUG_REGISTERS
0x00000300
Software pop FIFO
Page 177
Register Name
Instances and
Offset within
Address
Register Group Spacing
Description
Details
INTERFACE_CTL
0x00000000
1
Interface control register
Page 143
ANALYZER_MODE
0x00000004
1
Analyzer mode register
Page 144
SPARE_REGISTER
0x00000008
1
Spare scratchpad register
Page 144
4.8.1
1
IP_1588:IP_1588_TOP_CFG_STAT
Parent:
Instances: 1
Table 123 • Registers in IP_1588_TOP_CFG_STAT
4.8.1.1
IP_1588:IP_1588_TOP_CFG_STAT:INTERFACE_CTL
Parent: IP_1588:IP_1588_TOP_CFG_STAT
Instances: 1
Table 124 • Fields in INTERFACE_CTL
Field Name
Bit
Access
Description
CLK_ENA
6
R/W
Clock enable for the 1588 IP block. This bit is 0x0
an output of the IP and can be used
externally to gate the clocks to the block off
when the block is disabled. This bit is not
used inside the IP block.
0: Clocks disabled
1: Clocks enabled
BYPASS
2
R/W
When 1, the 1588 IP block is bypassed. This 0x1
is the default state. Changing this bit to 0 will
allow 1588 processed data to flow out of the
block. This bit is internally registered so that it
only takes effect during an IDLE period in the
data stream. This allows for a more seamless
transition from bypass to data passing
modes.
0: Data mode
1: Bypass mode
VMDS-10510 VSC8574-02 Datasheet Revision 4.2
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143
Table 124 • Fields in INTERFACE_CTL (continued)
Field Name
Bit
Access
Description
Default
MII_PROTOCOL
1:0
R/W
Defines the operating mode in which the
attached PCS block operates
0: XGMII-64
1: Reserved
2: GMII
3: MII
0x0
4.8.1.2
IP_1588:IP_1588_TOP_CFG_STAT:ANALYZER_MODE
Parent: IP_1588:IP_1588_TOP_CFG_STAT
Instances: 1
Table 125 • Fields in ANALYZER_MODE
Field Name
Bit
Access
Description
Default
ENCAP_FLOW_MODE
18:16
R/W
Defines how flow matching is performed in
each encapsulation engine
0: Match any flow
1: Strict matching
0x0
EGR_ENCAP_ENGINE_ENA
6:4
R/W
Enables for the egress encapsulation
engines. Enable bit 0 and 1 are for the PTP
engines; bit 2 is for the OAM engine.
0: Disabled
1: Enabled
0x0
INGR_ENCAP_ENGINE_ENA
2:0
R/W
Enables for the ingress encapsulation
engines. Enable bit 0 & 1 are for the PTP
engines; bit 2 is for the OAM engine.
0: Disabled
1: Enabled
0x0
4.8.1.3
IP_1588:IP_1588_TOP_CFG_STAT:SPARE_REGISTER
Parent: IP_1588:IP_1588_TOP_CFG_STAT
Instances: 1
Table 126 • Fields in SPARE_REGISTER
Field Name
Bit
Access
Description
Default
SPARE_REGISTER
31:0
R/W
Spare scratchpad register
0x00000000
4.8.2
IP_1588:IP_1588_LTC
Parent:
Instances: 1
Configuration and status register set for the IEEE1588 local time counter
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Table 127 • Registers in IP_1588_LTC
Register Name
Instances and
Offset within
Address
Register Group Spacing
Description
Details
LTC_CTRL
0x00000000
1
LTC control
Page 145
LTC_LOAD_SEC_H
0x00000004
1
LTC load seconds (high)
Page 146
LTC_LOAD_SEC_L
0x00000008
1
LTC load seconds (low)
Page 146
LTC_LOAD_NS
0x0000000C
1
LTC load nanoseconds
Page 147
LTC_SAVED_SEC_H
0x00000010
1
LTC saved seconds (high)
Page 147
LTC_SAVED_SEC_L
0x00000014
1
LTC saved seconds (low)
Page 147
LTC_SAVED_NS
0x00000018
1
LTC saved nanoseconds
Page 147
LTC_SEQUENCE
0x0000001C
1
LTC sequence configuration
Page 148
LTC_SEQ
0x00000020
1
LTC sequence configuration
Page 148
LTC_AUTO_ADJUST
0x00000028
1
LTC auto adjustment
Page 148
4.8.2.1
IP_1588:IP_1588_LTC:LTC_CTRL
Parent: IP_1588:IP_1588_LTC
Instances: 1
LTC control
Table 128 • Fields in LTC_CTRL
Field Name
Bit
Access
Description
LTC_CLK_SEL
14:12
R/W
Select the clock source for the LTC block.
0x0
The actual clock mux is external to the IP
block, this field merely provides the select
lines to the clock mux. These three select
lines are outputs of the IP block and are not
used internally. The single clock signal is
then fed to the LTC input.The three bits allow
for one of up to eight possible clock sources
to be selected.
0: External Pin is source of clock
1: Client Rx Clock
2: Client Tx Clock
3: Line Rx Clock
4: Line Tx Clock
5-7: INVALID
Reserved
10:6
RO
Reserved
Reserved
5
RO
Reserved
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Table 128 • Fields in LTC_CTRL (continued)
Field Name
Bit
Access
LTC_AUTO_ADJUST_UPDATE
4
One-shot When written to a 1 causes the local time
0x0
counter to update the automatic adjustment
values from the LTC_AUTO_ADJUST
register. The current automatic adjustment is
reset to start with the new values.
Automatically cleared.
0: No change to any previous updates (write),
or update has completed (read)
1: Use new values from
LTC_AUTO_ADJUST register
LTC_ADD_SUB_1NS_REQ
3
One-shot When written to a 1 causes a request for 1 ns 0x0
to be added or subtracted (depending upon
the LTC_ADD_SUB_1NS field) from the
Local time.
Automatically cleared.
0: No Add/Subtract from local time (write), Bit
has auto cleared (read)
1: Add/Subtract 1ns from the local time
LTC_ADD_SUB_1NS
2
R/W
This bit selects whether a write to the
LTC_ADD_SUB_1NS_REQ register causes
an add or subtract
0: Subtract 1 ns
1: Add 1ns to the local time
0x0
LTC_SAVE_ENA
1
R/W
LTC save enable
Enables the load/save for channel 0 and 1
pin (GPIO 1) to save the LTC_SAVE
seconds/nanoseconds registers.
0x0
LTC_LOAD_ENA
0
R/W
LTC load enable
Enables load/save for channel 0 and 1 pin
(GPIO 1) to load the LTC_LOAD
seconds/nanoseconds registers.
0x0
4.8.2.2
Description
Default
IP_1588:IP_1588_LTC:LTC_LOAD_SEC_H
Parent: IP_1588:IP_1588_LTC
Instances: 1
LTC load seconds (high)
Table 129 • Fields in LTC_LOAD_SEC_H
Field Name
Bit
Access
Description
Default
LTC_LOAD_SEC_H
15:0
R/W
LTC load seconds (high)
0x0000
4.8.2.3
IP_1588:IP_1588_LTC:LTC_LOAD_SEC_L
Parent: IP_1588:IP_1588_LTC
Instances: 1
LTC load seconds (low)
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Table 130 • Fields in LTC_LOAD_SEC_L
Field Name
Bit
Access
Description
Default
LTC_LOAD_SEC_L
31:0
R/W
LTC load seconds (low)
0x00000000
4.8.2.4
IP_1588:IP_1588_LTC:LTC_LOAD_NS
Parent: IP_1588:IP_1588_LTC
Instances: 1
LTC load nanoseconds
Table 131 • Fields in LTC_LOAD_NS
Field Name
Bit
Access
Description
Default
LTC_LOAD_NS
31:0
R/W
LTC load nanoseconds
0x00000000
4.8.2.5
IP_1588:IP_1588_LTC:LTC_SAVED_SEC_H
Parent: IP_1588:IP_1588_LTC
Instances: 1
LTC saved seconds (high)
Table 132 • Fields in LTC_SAVED_SEC_H
Field Name
Bit
Access
Description
Default
LTC_SAVED_SEC_H
15:0
R/O
LTC saved seconds (high)
0x0000
4.8.2.6
IP_1588:IP_1588_LTC:LTC_SAVED_SEC_L
Parent: IP_1588:IP_1588_LTC
Instances: 1
LTC saved seconds (low)
Table 133 • Fields in LTC_SAVED_SEC_L
Field Name
Bit
Access
Description
Default
LTC_SAVED_SEC_L
31:0
R/O
LTC saved seconds (low)
0x00000000
4.8.2.7
IP_1588:IP_1588_LTC:LTC_SAVED_NS
Parent: IP_1588:IP_1588_LTC
Instances: 1
LTC saved nanoseconds
VMDS-10510 VSC8574-02 Datasheet Revision 4.2
147
Table 134 • Fields in LTC_SAVED_NS
Field Name
Bit
Access
Description
Default
LTC_SAVED_NS
31:0
R/O
LTC saved nanoseconds
0x00000000
4.8.2.8
IP_1588:IP_1588_LTC:LTC_SEQUENCE
Parent: IP_1588:IP_1588_LTC
Instances: 1
LTC sequence configuration
Table 135 • Fields in LTC_SEQUENCE
Field Name
Bit
Access
Description
Default
RESERVED
19:12
R/W
Must be set to its default.
0x01
RESERVED
11:8
R/W
Must be set to its default.
0x4
RESERVED
7:4
R/W
Must be set to its default.
0x4
LTC_SEQUENCE_A
3:0
R/W
LTC sequence of increments (nanoseconds) 0x4
4.8.2.9
IP_1588:IP_1588_LTC:LTC_SEQ
Parent: IP_1588:IP_1588_LTC
Instances: 1
LTC sequence configuration
Table 136 • Fields in LTC_SEQ
Field Name
Bit
Access
Description
Default
RESERVED
20
R/W
Must be set to its default.
0x1
LTC_SEQ_ADD_SUB
19
R/W
LTC sequence correction sign
0: Subtract 1 ns adjustment
1: Add 1 ns adjustment
0x1
LTC_SEQ_E
18:0
R/W
LTC sequence correction (nanoseconds * 1
million)
Example for 6.4 ns period (156.25 MHz):
LTC_SEQUENCE.LTC_SEQUENCE_A = 6
(6 ns)
LTC_SEQ.LTC_SEQ_ADD_SUB = 1 (add 1
ns)
LTC_SEQ.LTC_SEQ_E = 400000 (0.4 ns *
1,000,000)
0x00000
4.8.2.10
IP_1588:IP_1588_LTC:LTC_AUTO_ADJUST
Parent: IP_1588:IP_1588_LTC
Instances: 1
LTC auto adjustment
VMDS-10510 VSC8574-02 Datasheet Revision 4.2
148
Table 137 • Fields in LTC_AUTO_ADJUST
Field Name
Bit
Access
Description
Default
LTC_AUTO_ADD_SUB_1NS
31:30
R/W
LTC auto adjustment add/subtract 1 ns
0,3: No adjustment
1: Adjust by adding 1 ns upon rollover
2: Adjust by subtracting 1 ns upon rollover
0x0
LTC_AUTO_ADJUST_NS
29:0
R/W
LTC auto adjustment rollover (nanoseconds) 0x00000000
4.8.3
IP_1588:TS_FIFO_SI
Parent:
Instances: 1
Table 138 • Registers in TS_FIFO_SI
Register Name
Instances and
Offset within
Address
Register Group Spacing
TS_FIFO_SI_CFG
0x00000000
1
Timestamp FIFO serial
Page 149
interface configuration register
TS_FIFO_SI_TX_CNT
0x00000004
1
Transmitted timestamp count
4.8.3.1
Description
Details
Page 150
IP_1588:TS_FIFO_SI:TS_FIFO_SI_CFG
Parent: IP_1588:TS_FIFO_SI
Instances: 1
Polarity and cycle counts are configurable from port 0 only.
Table 139 • Fields in TS_FIFO_SI_CFG
Field Name
Bit
Access
Description
Default
SI_CLK_PHA
25
R/W
SI clock phase control
0: SI_CLK falling edge changes output data
1: SI_CLK rising edge changes output data
0x0
SI_CLK_POL
24
R/W
SI clock polarity control
0: SI_CLK starts and ends (idles) low
1: SI_CLK starts and ends (idles) high
0x0
SI_EN_DES_CYCS
23:20
R/W
Number of CSR clock periods SI_EN
negates between writes (deselected). The
CSR clock period is one-half the REFCLK
pin's period.
0x0
SI_CLK_HI_CYCS
10:6
R/W
Number of CSR clock periods that the
0x02
SI_CLK is high. The CSR clock period is onehalf the REFCLK pin's period.
SI_CLK_LO_CYCS
5:1
R/W
Number of CSR clock periods that the
0x02
SI_CLK is low. The CSR clock period is onehalf the REFCLK pin's period.
VMDS-10510 VSC8574-02 Datasheet Revision 4.2
149
Table 139 • Fields in TS_FIFO_SI_CFG (continued)
Field Name
Bit
Access
Description
TS_FIFO_SI_ENA
0
R/W
Timestamp FIFO serial interface block control 0x0
0: Disable Timestamp FIFO serial interface
block
1: Enable Timestamp FIFO serial interface
block
4.8.3.2
Default
IP_1588:TS_FIFO_SI:TS_FIFO_SI_TX_CNT
Parent: IP_1588:TS_FIFO_SI
Instances: 1
Counter for the number of timestamps transmitted to the interface.
Table 140 • Fields in TS_FIFO_SI_TX_CNT
Field Name
Bit
Access
Description
Default
TS_FIFO_SI_TX_CNT
31:0
R/W
Counter value
0x00000000
4.8.4
IP_1588:INGR_PREDICTOR
Parent:
Instances: 1
Table 141 • Registers in INGR_PREDICTOR
Register Name
Instances and
Offset within
Address
Register Group Spacing
Description
Details
IG_CFG
0x00000000
1
Ingress configuration register
Page 150
IG_PMA
0x00000004
1
Period of PMA clock in
fractional nanoseconds
Page 151
IG_XFI
0x00000008
1
XFI delays in nanoseconds
Page 151
IG_OTN
0x0000000C
1
OTN configuration
Page 152
4.8.4.1
IP_1588:INGR_PREDICTOR:IG_CFG
Parent: IP_1588:INGR_PREDICTOR
Instances: 1
VMDS-10510 VSC8574-02 Datasheet Revision 4.2
150
Table 142 • Fields in IG_CFG
Field Name
Bit
Access
Description
WAF
21:16
R/W
WIS advanced (fixed) value.
0x00
This is the number of register stages in the
pipeline from the SFD detection logic through
the 1588 IP, the PCS stages until the Rx
gearbox and after the gearbox through the
WIS until the frame overhead generation
logic.
PAF
13:8
R/W
PCS advanced (fixed) value.
0x00
This is the number of register stages in the
pipeline from the SFD detection logic through
the 1588 IP, the PCS stages until the Rx
gearbox.
IG_ENABLE
0
R/W
When 1, the Ingress prediction block is
enabled.
0: Disabled
1: Enabled
4.8.4.2
Default
0x0
IP_1588:INGR_PREDICTOR:IG_PMA
Parent: IP_1588:INGR_PREDICTOR
Instances: 1
Table 143 • Fields in IG_PMA
Field Name
Bit
Access
Description
TPMA
15:0
R/W
Period in fractional ns of the PMA clock.
0x0000
The binary number is in 9.7 format with 9
significant ns bits and 7 fractional ns bits.
9.7 format unsigned fractional binary number
4.8.4.3
Default
IP_1588:INGR_PREDICTOR:IG_XFI
Parent: IP_1588:INGR_PREDICTOR
Instances: 1
Table 144 • Fields in IG_XFI
Field Name
Bit
Access
Description
XFI_MSB
31:16
R/W
The time taken for the 32 most significant bits 0x0000
of a 64-bit transaction to pass through the
XFI logic. This is because the XFI processes
the LS and MS bits separately on a 2x clock.
9.7 format unsigned fractional binary number
VMDS-10510 VSC8574-02 Datasheet Revision 4.2
Default
151
Table 144 • Fields in IG_XFI (continued)
Field Name
Bit
Access
Description
Default
XFI_LSB
15:0
R/W
The time taken for the 32 least significant bits 0x0000
of a 64-bit transaction to pass through the
XFI logic. This is because the XFI processes
the LS and MS bits separately on a 2x clock.
9.7 format unsigned fractional binary number
4.8.4.4
IP_1588:INGR_PREDICTOR:IG_OTN
Parent: IP_1588:INGR_PREDICTOR
Instances: 1
Table 145 • Fields in IG_OTN
Field Name
Bit
Access
Description
Default
GAP_PERIOD
6:0
R/W
OTN clock gapping and virtual CBR pipe
width information
GAP_PERIOD[6:2]
0: Virtual CBR pipe, 64 bits wide
1: Virtual CBR pipe, 32 bits wide
2: Virtual CBR pipe, 1 bit wide
others: Undefined
GAP_PERIOD[1:0]
1: 1/15 OTN gapped clock.
2: 6/85 OTN gapped clock
others: No gapping
0x00
4.8.5
IP_1588:EGR_PREDICTOR
Parent:
Instances: 1
Table 146 • Registers in EGR_PREDICTOR
Register Name
Instances and
Offset within
Address
Register Group Spacing
Description
Details
EG_CFG
0x00000000
1
Egress configuration register
Page 152
EG_WIS_FRAME
0x00000004
1
Egress WIS frame
characteristics in clocks
Page 153
EG_WIS_DELAYS
0x00000008
1
Egress WIS delays in
nanoseconds
Page 153
EG_PMA
0x0000000C
1
Egress PMA clock delay
Page 154
EG_XFI
0x00000010
1
XFI delays in nanoseconds
Page 154
EG_OTN
0x00000014
1
OTN configuration
Page 154
4.8.5.1
IP_1588:EGR_PREDICTOR:EG_CFG
Parent: IP_1588:EGR_PREDICTOR
VMDS-10510 VSC8574-02 Datasheet Revision 4.2
152
Instances: 1
Table 147 • Fields in EG_CFG
Field Name
Bit
Access
Description
WAF
21:16
R/W
WIS advanced (fixed) value.
0x00
This is the number of register stages in the
pipeline from the SFD detection logic through
the 1588 IP, the PCS stages until the Tx
gearbox and after the gearbox through the
WIS until the frame overhead generation
logic.
PAF
13:8
R/W
PCS advanced (fixed) value.
0x00
This is the number of register stages in the
pipeline from the SFD detection logic through
the 1588 IP, the PCS stages until the Tx
gearbox.
EG_ENABLE
0
R/W
When 1, the Egress prediction block is
enabled.
0: Disabled
1: Enabled
4.8.5.2
Default
0x0
IP_1588:EGR_PREDICTOR:EG_WIS_FRAME
Parent: IP_1588:EGR_PREDICTOR
Instances: 1
Table 148 • Fields in EG_WIS_FRAME
Field Name
Bit
Access
Description
Default
W_OH
23:16
R/W
WIS overhead time in clock cycles.
This is the number of clocks in the Egress
WIS overhead time. Typically 80.
0x50
W_FSIZE
11:0
R/W
Size of the WIS frame in clocks. Typically
2160.
0x870
4.8.5.3
IP_1588:EGR_PREDICTOR:EG_WIS_DELAYS
Parent: IP_1588:EGR_PREDICTOR
Instances: 1
Table 149 • Fields in EG_WIS_DELAYS
Field Name
Bit
Access
Description
W_OH_NS
15:0
R/W
Duration of the WIS overhead in fractional
0x0000
nanoseconds.
The number is in 12.4 format with 12
nanosecond bits and 4 fractional nanosecond
bits.
12.4 format unsigned fractional binary
number
VMDS-10510 VSC8574-02 Datasheet Revision 4.2
Default
153
4.8.5.4
IP_1588:EGR_PREDICTOR:EG_PMA
Parent: IP_1588:EGR_PREDICTOR
Instances: 1
Table 150 • Fields in EG_PMA
Field Name
Bit
Access
Description
TPMA
15:0
R/W
PMA clock period in fractional nanoseconds. 0x0000
This period is for the clock that drives the
PMA, PCS, and WIS and is in 9.7 format with
9 significant ns bits and 7 fractional ns bits.
9.7 format unsigned fractional binary number
4.8.5.5
Default
IP_1588:EGR_PREDICTOR:EG_XFI
Parent: IP_1588:EGR_PREDICTOR
Instances: 1
Table 151 • Fields in EG_XFI
Field Name
Bit
Access
Description
Default
XFI_MSB
31:16
R/W
The time taken for the 32 most significant bits 0x0000
of a 64-bit transaction to pass through the
XFI logic. This is because the XFI processes
the LS and MS bits separately on a 2x clock.
9.7 format unsigned fractional binary number
XFI_LSB
15:0
R/W
The time taken for the 32 least significant bits 0x0000
of a 64-bit transaction to pass through the
XFI logic. This is because the XFI processes
the LS and MS bits separately on a 2x clock.
9.7 format unsigned fractional binary number
4.8.5.6
IP_1588:EGR_PREDICTOR:EG_OTN
Parent: IP_1588:EGR_PREDICTOR
Instances: 1
Table 152 • Fields in EG_OTN
Field Name
Bit
Access
Description
Default
GAP_PERIOD
6:0
R/W
OTN clock gapping and virtual CBR pipe
width information
GAP_PERIOD[6:2]
0: Virtual CBR pipe, 64 bits wide
1: Virtual CBR pipe, 32 bits wide
2: Virtual CBR pipe, 1 bit wide
others: Undefined
GAP_PERIOD[1:0]
1: 1/15 OTN gapped clock.
2: 6/85 OTN gapped clock
others: PMA clock not gapped
0x00
VMDS-10510 VSC8574-02 Datasheet Revision 4.2
154
4.8.6
IP_1588:INGR_IP_1588_CFG_STAT
Parent:
Instances: 1
Table 153 • Registers in INGR_IP_1588_CFG_STAT
Register Name
Instances and
Offset within
Address
Register Group Spacing
INGR_INT_STATUS
0x00000000
INGR_INT_MASK
INGR_SPARE_REGISTER
4.8.6.1
Description
Details
1
1588 IP interrupt status
register
Page 155
0x00000004
1
1588 IP interrupt mask register Page 156
0x00000008
1
Spare scratchpad register
Page 157
IP_1588:INGR_IP_1588_CFG_STAT:INGR_INT_STATUS
Parent: IP_1588:INGR_IP_1588_CFG_STAT
Instances: 1
Status sticky conditions for the 1588 IP
Table 154 • Fields in INGR_INT_STATUS
Field Name
Bit
Access
Description
Default
INGR_ANALYZER_ERROR_STIC 6
KY
Sticky
Indicates that more than one engine has
produced a match
0: No error found
1: Duplicate match found
0x0
INGR_RW_PREAMBLE_ERR_STI 5
CKY
Sticky
When set, indicates that a preamble that was 0x0
too short to modify was detected in a PTP
frame. Write to 1 to clear. This occurs when
the rewriter needs to shrink the preamble to
append a timestamp but cannot because the
preamble is too short. A short preamble is
any preamble that is less than eight
characters long including the XGMII /S/
character and the ending SFD of 0xD5. Other
preamble values are not checked, only the
GMII length.
0: No error
1: Preamble too short error
INGR_RW_FCS_ERR_STICKY
Sticky
When set, indicates that an FCS error was
detected in a PTP/OAM frame. Write to 1 to
clear.
0: No error
1: FCS error
4
VMDS-10510 VSC8574-02 Datasheet Revision 4.2
0x0
155
Table 154 • Fields in INGR_INT_STATUS (continued)
Field Name
Bit
Access
Description
INGR_TS_LEVEL_STICKY
3
Sticky
When set, indicates that the level in the
0x0
Timestamp FIFO has reached the threshold
TS_THRESH. The sticky bit should be reset
by writing it to 1.
0: No overflow
1: Overflow
INGR_TS_LOADED_STICKY
2
Sticky
When set, indicates a timestamp was
captured in the Timestamp FIFO. The sticky
bit should be reset by writing it to 1.
0: No overflow
1: Overflow
0x0
INGR_TS_UNDERFLOW_STICKY 1
Sticky
When set, indicates an underflow in the
Timestamp FIFO. The sticky bit should be
reset by writing it to 1.
0: No overflow
1: Overflow
0x0
INGR_TS_OVERFLOW_STICKY
Sticky
When set, indicates an overflow in the
Timestamp FIFO. The sticky bit should be
reset by writing it to 1.
0: No overflow
1: Overflow
0x0
4.8.6.2
0
Default
IP_1588:INGR_IP_1588_CFG_STAT:INGR_INT_MASK
Parent: IP_1588:INGR_IP_1588_CFG_STAT
Instances: 1
Masks that enable and disable the interrupts
Table 155 • Fields in INGR_INT_MASK
Field Name
Bit
Access
Description
Default
INGR_ANALYZER_ERROR_MAS 6
K
R/W
Mask bit for ANALYZER_ERROR_STICKY
bit
0: Interrupt disabled
1: Interrupt enabled
0x0
INGR_RW_PREAMBLE_ERR_MA 5
SK
R/W
Mask for the
RW_PREAMBLE_ERR_STICKY bit
0: Interrupt disabled
1: Interrupt enabled
0x0
INGR_RW_FCS_ERR_MASK
4
R/W
Mask for the RW_FCS_ERR_STICKY bit
0: Interrupt disabled
1: Interrupt enabled
0x0
INGR_TS_LEVEL_MASK
3
R/W
Mask bit for TS_LEVEL_STICKY. When 1,
the interrupt is enabled.
0: Interrupt disabled
1: Interrupt enabled
0x0
VMDS-10510 VSC8574-02 Datasheet Revision 4.2
156
Table 155 • Fields in INGR_INT_MASK (continued)
Field Name
Bit
Access
Description
INGR_TS_LOADED_MASK
2
R/W
Mask bit for TS_LOADED_STICKY. When 1, 0x0
the interrupt is enabled.
0: Interrupt disabled
1: Interrupt enabled
INGR_TS_UNDERFLOW_MASK
1
R/W
Mask bit for TS_UNDERFLOW_STICKY.
When 1, the interrupt is enabled.
0: Interrupt disabled
1: Interrupt enabled
0x0
INGR_TS_OVERFLOW_MASK
0
R/W
Mask bit for TS_OVERFLOW_STICKY.
When 1, the interrupt is enabled.
0: Interrupt disabled
1: Interrupt enabled
0x0
4.8.6.3
Default
IP_1588:INGR_IP_1588_CFG_STAT:INGR_SPARE_REGISTER
Parent: IP_1588:INGR_IP_1588_CFG_STAT
Instances: 1
Table 156 • Fields in INGR_SPARE_REGISTER
Field Name
Bit
Access
Description
Default
INGR_SPARE_REGISTER
31:0
R/W
Spare scratchpad register
0x00000000
4.8.7
IP_1588:INGR_IP_1588_TSP
Parent:
Instances: 1
Configuration and status register set for the IEEE1588 timestamp processor
Table 157 • Registers in INGR_IP_1588_TSP
Register Name
Instances and
Offset within
Address
Register Group Spacing
Description
Details
INGR_TSP_CTRL
0x00000000
1
TSP control
Page 157
INGR_TSP_STAT
0x00000004
1
TSP status
Page 158
INGR_LOCAL_LATENCY
0x00000008
1
Local latency
Page 158
INGR_PATH_DELAY
0x0000000C
1
Path delay
Page 158
INGR_DELAY_ASYMMETRY
0x00000010
1
Delay asymmetry
Page 159
4.8.7.1
IP_1588:INGR_IP_1588_TSP:INGR_TSP_CTRL
Parent: IP_1588:INGR_IP_1588_TSP
Instances: 1
VMDS-10510 VSC8574-02 Datasheet Revision 4.2
157
Table 158 • Fields in INGR_TSP_CTRL
Field Name
Bit
Access
Description
INGR_FRACT_NS_MODE
2
R/W
Selects a mode in which the fractional portion 0x0
of a second (in units of nanoseconds) is used
for timestamping. Only the operation of the
WRITE_NS, WRITE_NS_P2P, and
SUB_ADD PTP commands are affected by
the setting of this mode bit.
0: Select the total (summed) nanoseconds
for timestamping
1: Select the fractional portion in
nanoseconds for timestamping
INGR_SEL_EXT_SOF_IND
1
R/W
Select external pin start of frame indicator
0x0
0: Select internal PCS as the source of SOF
1: Select external pin as the source of SOF
INGR_LOAD_DELAYS
0
One-shot One-shot loads local latency, path delay, and 0x0
DelayAsymmetry values into the timestamp
processor
4.8.7.2
Default
IP_1588:INGR_IP_1588_TSP:INGR_TSP_STAT
Parent: IP_1588:INGR_IP_1588_TSP
Instances: 1
Table 159 • Fields in INGR_TSP_STAT
Field Name
Bit
Access
Description
Default
INGR_CF_TOO_BIG_STICKY
0
Sticky
Timestamp processor marked a calculated
correction field as too big
0: A calculated correction field that was too
big did occur
1: A calculated correction field that was too
big did not occur
0x0
4.8.7.3
IP_1588:INGR_IP_1588_TSP:INGR_LOCAL_LATENCY
Parent: IP_1588:INGR_IP_1588_TSP
Instances: 1
Table 160 • Fields in INGR_LOCAL_LATENCY
Field Name
Bit
Access
Description
Default
INGR_LOCAL_LATENCY
15:0
R/W
Local latency (nanoseconds)
0x0000
4.8.7.4
IP_1588:INGR_IP_1588_TSP:INGR_PATH_DELAY
Parent: IP_1588:INGR_IP_1588_TSP
Instances: 1
VMDS-10510 VSC8574-02 Datasheet Revision 4.2
158
Table 161 • Fields in INGR_PATH_DELAY
Field Name
Bit
Access
Description
Default
INGR_PATH_DELAY
31:0
R/W
Path delay (nanoseconds)
0x00000000
4.8.7.5
IP_1588:INGR_IP_1588_TSP:INGR_DELAY_ASYMMETRY
Parent: IP_1588:INGR_IP_1588_TSP
Instances: 1
Table 162 • Fields in INGR_DELAY_ASYMMETRY
Field Name
Bit
Access
Description
Default
INGR_DELAY_ASYMMETRY
31:0
R/W
Delay asymmetry (scaled nanoseconds)
0x00000000
4.8.8
IP_1588:INGR_IP_1588_DF
Parent:
Instances: 1
Configuration for the delay FIFO in the 1588 IP block. The delay FIFO will delay the data in a pipeline
governed by these settings.
Table 163 • Registers in INGR_IP_1588_DF
Register Name
Instances and
Offset within
Address
Register Group Spacing
INGR_DF_CTRL
0x00000000
4.8.8.1
1
Description
Details
Configuration and control
register for the delay FIFO
Page 159
IP_1588:INGR_IP_1588_DF:INGR_DF_CTRL
Parent: IP_1588:INGR_IP_1588_DF
Instances: 1
Table 164 • Fields in INGR_DF_CTRL
Field Name
Bit
Access
Description
INGR_DF_DEPTH
4:0
R/W
The index of the register stage in the delay
0x00
FIFO that is used for output. The actual delay
through the block is one more than the depth.
If depth is set to 2, then the delay is 3 clocks
as data is taken from stage 2. The depth
MUST be greater than 0 (depth of 0 is not
allowed).
Binary number >= 1
VMDS-10510 VSC8574-02 Datasheet Revision 4.2
Default
159
4.8.9
IP_1588:INGR_IP_1588_TSFIFO
Parent:
Instances: 1
Configuration and status for the timestamp FIFO. This register is only usable if a timestamp FIFO has
been instantiated in the given direction (ingress or egress).
Note: The ingress timestamp FIFO is NOT required and may not be present. In that case, the ingress registers
will be unconnected.
Table 165 • Registers in INGR_IP_1588_TSFIFO
Register Name
Instances and
Offset within
Address
Register Group Spacing
INGR_TSFIFO_CSR
0x00000000
1
Timestamp FIFO configuration Page 160
and status
INGR_TSFIFO_0
0x00000004
1
Data value from the timestamp Page 161
FIFO
INGR_TSFIFO_1
0x00000008
1
Data value from the timestamp Page 162
FIFO
INGR_TSFIFO_2
0x0000000C
1
Data value from the timestamp Page 162
FIFO
INGR_TSFIFO_3
0x00000010
1
Data value from the timestamp Page 162
FIFO
INGR_TSFIFO_4
0x00000014
1
Data value from the timestamp Page 163
FIFO
INGR_TSFIFO_5
0x00000018
1
Data value from the timestamp Page 163
FIFO
INGR_TSFIFO_6
0x0000001C
1
Data value from the timestamp Page 163
FIFO
INGR_TSFIFO_DROP_CNT
0x00000020
1
Count of dropped timestamps Page 163
4.8.9.1
Description
Details
IP_1588:INGR_IP_1588_TSFIFO:INGR_TSFIFO_CSR
Parent: IP_1588:INGR_IP_1588_TSFIFO
Instances: 1
Configuration and status register for the timestamp FIFO
Table 166 • Fields in INGR_TSFIFO_CSR
Field Name
Bit
Access
Description
INGR_TS_4BYTES
17
R/W
Selects a smaller timestamp size to be stored 0x0
in the timestamp FIFO (4 bytes vs. the
default 10 bytes)
0: Full 10 byte timestamps are stored
1: Only 4 bytes of each timestamp are stored
INGR_TS_FIFO_RESET
16
R/W
Forces the TS_FIFO into the reset state
VMDS-10510 VSC8574-02 Datasheet Revision 4.2
Default
0x0
160
Table 166 • Fields in INGR_TSFIFO_CSR (continued)
Field Name
Bit
Access
Description
INGR_TS_LEVEL
15:12
R/O
The FIFO level associated with the last read 0x0
of the TS_EMPTY status field of the
TSFIFO_0 register
Binary number (0-8)
INGR_TS_THRESH
11:8
R/W
The threshold at which the timestamp FIFO
interrupt TS_LEVEL_STICKY will be set. If
the FIFO level reaches the threshold, the
sticky bit TS_LEVEL_STICKY will be set.
Binary number (1-8)
INGR_TS_SIGNAT_BYTES
4:0
R/W
Indicates the number of signature bytes used 0x00
for timestamps in the timestamp FIFO (0-16).
4.8.9.2
Default
0x3
IP_1588:INGR_IP_1588_TSFIFO:INGR_TSFIFO_0
Parent: IP_1588:INGR_IP_1588_TSFIFO
Instances: 1
Read the data from the timestamp FIFO along with the FIFO empty flag in the MSB
Table 167 • Fields in INGR_TSFIFO_0
Field Name
Bit
Access
Description
INGR_TS_EMPTY
31
R/O
The FIFO empty flag from the Timestamp
0x1
FIFO. If this bit is set, there is no FIFO data to
be read from the FIFO. The data in the
TSFIFO_x registers is not valid and should
be discarded. When 0, the FIFO has data
and the TSFIFO_x has a valid set of data.
This register can be polled and when the bit
is cleared, the other registers should be read
to get a full timestamp. When 1, the last data
has already been read out and the current
read data should be discarded.
Timestamp/Frame signature bytes are
packed such that the 10 or 4 byte timestamp
resides in the LEAST significant bytes while
the frame signature (0 to 16 bytes) resides in
the MOST significant bytes. The order of the
bytes within each timestamp/frame signature
field is also most significant to least
significant.
For example, 26 byte timestamp/frame
signature pairs are packed with the 10 byte
timestamp field ([79:0]) corresponding to Bits
79:0 in the following registers, and a 16 byte
frame signature field ([127:0]) corresponding
to Bits 207:80 in the following registers.
0: FIFO not empty, data valid
1: FIFO empty, data invalid
VMDS-10510 VSC8574-02 Datasheet Revision 4.2
Default
161
Table 167 • Fields in INGR_TSFIFO_0 (continued)
Field Name
Bit
Access
Description
INGR_TS_FLAGS
30:28
R/O
FIFO flags from the timestamp FIFO. These N/A
bits indicate how many timestamps are valid
in the current (not empty) 26 byte FIFO entry.
000: Only the end of a partial timestamp is
valid in the current FIFO entry (any remaining
data is invalid)
001: 1 valid timestamp begins in the current
FIFO entry (any remaining data is invalid)
010: 2 valid timestamps begin in the current
FIFO entry (any remaining data is invalid)
011: 3 valid timestamps begin in the current
FIFO entry (any remaining data is invalid)
100: 4 valid timestamps begin in the current
FIFO entry (any remaining data is invalid)
101: 5 valid timestamps begin in the current
FIFO entry (any remaining data is invalid)
110: 6 valid timestamps begin in the current
FIFO entry (any remaining data is invalid)
111: The current FIFO entry is fully packed
with timestamps (all data is valid)
INGR_TSFIFO_0
15:0
R/O
16 bits from the timestamp FIFO. Bits 15:0
4.8.9.3
Default
N/A
IP_1588:INGR_IP_1588_TSFIFO:INGR_TSFIFO_1
Parent: IP_1588:INGR_IP_1588_TSFIFO
Instances: 1
Read the data from the timestamp FIFO
Table 168 • Fields in INGR_TSFIFO_1
Field Name
Bit
Access
Description
INGR_TSFIFO_1
31:0
R/O
32 bits from the timestamp FIFO. Bits 47:16. N/A
4.8.9.4
Default
IP_1588:INGR_IP_1588_TSFIFO:INGR_TSFIFO_2
Parent: IP_1588:INGR_IP_1588_TSFIFO
Instances: 1
Read the data from the timestamp FIFO
Table 169 • Fields in INGR_TSFIFO_2
Field Name
Bit
Access
Description
INGR_TSFIFO_2
31:0
R/O
32 bits from the timestamp FIFO. Bits 79:48. N/A
4.8.9.5
Default
IP_1588:INGR_IP_1588_TSFIFO:INGR_TSFIFO_3
Parent: IP_1588:INGR_IP_1588_TSFIFO
Instances: 1
Read the data from the timestamp FIFO
VMDS-10510 VSC8574-02 Datasheet Revision 4.2
162
Table 170 • Fields in INGR_TSFIFO_3
Field Name
Bit
Access
Description
INGR_TSFIFO_3
31:0
R/O
32 bits from the timestamp FIFO. Bits 111:80. N/A
4.8.9.6
Default
IP_1588:INGR_IP_1588_TSFIFO:INGR_TSFIFO_4
Parent: IP_1588:INGR_IP_1588_TSFIFO
Instances: 1
Read the data from the timestamp FIFO
Table 171 • Fields in INGR_TSFIFO_4
Field Name
Bit
Access
Description
Default
INGR_TSFIFO_4
31:0
R/O
32 bits from the timestamp FIFO. Bits
143:112.
N/A
4.8.9.7
IP_1588:INGR_IP_1588_TSFIFO:INGR_TSFIFO_5
Parent: IP_1588:INGR_IP_1588_TSFIFO
Instances: 1
Read the data from the timestamp FIFO
Table 172 • Fields in INGR_TSFIFO_5
Field Name
Bit
Access
Description
Default
INGR_TSFIFO_5
31:0
R/O
32 bits from the timestamp FIFO. Bits
175:144.
N/A
4.8.9.8
IP_1588:INGR_IP_1588_TSFIFO:INGR_TSFIFO_6
Parent: IP_1588:INGR_IP_1588_TSFIFO
Instances: 1
Read the data from the timestamp FIFO
Table 173 • Fields in INGR_TSFIFO_6
Field Name
Bit
Access
Description
Default
INGR_TSFIFO_6
31:0
R/O
32 bits from the timestamp FIFO. Bits
207:176.
N/A
4.8.9.9
IP_1588:INGR_IP_1588_TSFIFO:INGR_TSFIFO_DROP_CNT
Parent: IP_1588:INGR_IP_1588_TSFIFO
Instances: 1
Count of dropped timestamps not enqueued to the TS FIFO
VMDS-10510 VSC8574-02 Datasheet Revision 4.2
163
Table 174 • Fields in INGR_TSFIFO_DROP_CNT
Field Name
Bit
Access
Description
Default
INGR_TS_FIFO_DROP_CNT
31:0
R/W
Timestamps dropped count
0x00000000
4.8.10
IP_1588:INGR_IP_1588_RW
Parent:
Instances: 1
Configuration and status for the 1588 rewriter
Table 175 • Registers in INGR_IP_1588_RW
Register Name
Instances and
Offset within
Address
Register Group Spacing
INGR_RW_CTRL
0x00000000
INGR_RW_MODFRM_CNT
INGR_RW_FCS_ERR_CNT
Description
Details
1
Rewriter configuration and
control
Page 164
0x00000004
1
Count of modified frames
Page 165
0x00000008
1
Count of FCS errors
Page 165
INGR_RW_PREAMBLE_ERR_CN 0x0000000C
T
1
Count of the number of
preamble errors
Page 165
4.8.10.1
IP_1588:INGR_IP_1588_RW:INGR_RW_CTRL
Parent: IP_1588:INGR_IP_1588_RW
Instances: 1
Configuration for the rewriter
Table 176 • Fields in INGR_RW_CTRL
Field Name
Bit
INGR_RW_REDUCE_PREAMBLE 4
Access
Description
Default
R/W
When set, the 1588 IP will reduce the
0x0
preamble of ALL incoming frames by 4 bytes
to allow a timestamp to be appended to the
ingress data frames. This bit must be set
along with the proper configuration of the
Analyzer to ensure proper operation.
Note: Valid in ingress direction only
0: No preamble modification
1: Reduce preamble by 4 bytes
INGR_RW_FLAG_VAL
3
R/W
Value to write to the flag bit when it is
overwritten
0: 0 will be written to the flag bit
1: 1 will be written to the flag bit
0x0
INGR_RW_FLAG_BIT
2:0
R/W
Bit offset within a byte of the flag bit that
indicates if the frame has been modified
0x0
VMDS-10510 VSC8574-02 Datasheet Revision 4.2
164
4.8.10.2
IP_1588:INGR_IP_1588_RW:INGR_RW_MODFRM_CNT
Parent: IP_1588:INGR_IP_1588_RW
Instances: 1
Table 177 • Fields in INGR_RW_MODFRM_CNT
Field Name
Bit
Access
Description
Default
INGR_RW_MODFRM_CNT
31:0
R/W
Count of the number of frames modified by
the 1588 IP. The counter wraps.
0x00000000
4.8.10.3
IP_1588:INGR_IP_1588_RW:INGR_RW_FCS_ERR_CNT
Parent: IP_1588:INGR_IP_1588_RW
Instances: 1
Table 178 • Fields in INGR_RW_FCS_ERR_CNT
Field Name
Bit
Access
Description
INGR_RW_FCS_ERR_CNT
31:0
R/W
Count of the number of FCS errored frames 0x00000000
detected by the rewriter. Counts only the FCS
errored frames that are modified.
4.8.10.4
Default
IP_1588:INGR_IP_1588_RW:INGR_RW_PREAMBLE_ERR_CNT
Parent: IP_1588:INGR_IP_1588_RW
Instances: 1
Table 179 • Fields in INGR_RW_PREAMBLE_ERR_CNT
Field Name
Bit
INGR_RW_PREAMBLE_ERR_CN 31:0
T
4.8.11
Access
Description
Default
R/W
Count of the number of errored preambles
detected. The counter wraps. An errored
preamble is a preamble that is too short to
shrink that is encountered when
RW_REDUCE_PREAMBLE is set.
Binary number
0x00000000
IP_1588:EGR_IP_1588_CFG_STAT
Parent:
Instances: 1
Table 180 • Registers in EGR_IP_1588_CFG_STAT
Register Name
Instances and
Offset within
Address
Register Group Spacing
EGR_INT_STATUS
0x00000000
1
Description
Details
1588 IP interrupt status
register
Page 166
VMDS-10510 VSC8574-02 Datasheet Revision 4.2
165
Table 180 • Registers in EGR_IP_1588_CFG_STAT (continued)
Register Name
Instances and
Offset within
Address
Register Group Spacing
Description
EGR_INT_MASK
0x00000004
1
1588 IP interrupt mask register Page 167
EGR_SPARE_REGISTER
0x00000008
1
Spare scratchpad register
4.8.11.1
Details
Page 168
IP_1588:EGR_IP_1588_CFG_STAT:EGR_INT_STATUS
Parent: IP_1588:EGR_IP_1588_CFG_STAT
Instances: 1
Status sticky conditions for the 1588 IP
Table 181 • Fields in EGR_INT_STATUS
Field Name
Bit
Access
Description
Default
EGR_ANALYZER_ERROR_STIC
KY
6
Sticky
Indicates that more than one engine has
produced a match
0: No error found
1: Duplicate match found
0x0
EGR_RW_PREAMBLE_ERR_STI 5
CKY
Sticky
When set, indicates that a preamble that was 0x0
too short to modify was detected in a PTP
frame. Write to 1 to clear. This occurs when
the rewriter needs to shrink the preamble to
append a timestamp but cannot because the
preamble is too short. A short preamble is
any preamble that is less than eight
characters long including the XGMII /S/
character and the ending SFD of 0xD5. Other
preamble values are not checked, only the
GMII length.
0: No error
1: Preamble too short error
EGR_RW_FCS_ERR_STICKY
4
Sticky
When set, indicates that an FCS error was
detected in a PTP/OAM frame. Write to 1 to
clear.
0: No error
1: FCS error
EGR_TS_LEVEL_STICKY
3
Sticky
When set, indicates that the level in the
0x0
Timestamp FIFO has reached the threshold
TS_THRESH. The sticky bit should be reset
by writing it to 1.
0: No overflow
1: Overflow
EGR_TS_LOADED_STICKY
2
Sticky
When set, indicates a timestamp was
captured in the Timestamp FIFO. The sticky
bit should be reset by writing it to 1.
0: No overflow
1: Overflow
VMDS-10510 VSC8574-02 Datasheet Revision 4.2
0x0
0x0
166
Table 181 • Fields in EGR_INT_STATUS (continued)
Field Name
Access
Description
Default
EGR_TS_UNDERFLOW_STICKY 1
Sticky
When set, indicates an underflow in the
Timestamp FIFO. The sticky bit should be
reset by writing it to 1.
0: No overflow
1: Overflow
0x0
EGR_TS_OVERFLOW_STICKY
Sticky
When set, indicates an overflow in the
Timestamp FIFO. The sticky bit should be
reset by writing it to 1.
0: No overflow
1: Overflow
0x0
4.8.11.2
Bit
0
IP_1588:EGR_IP_1588_CFG_STAT:EGR_INT_MASK
Parent: IP_1588:EGR_IP_1588_CFG_STAT
Instances: 1
Masks that enable and disable the interrupts
Table 182 • Fields in EGR_INT_MASK
Field Name
Access
Description
Default
EGR_ANALYZER_ERROR_MASK 6
Bit
R/W
Mask bit for ANALYZER_ERROR_STICKY
bit
0: Interrupt disabled
1: Interrupt enabled
0x0
EGR_RW_PREAMBLE_ERR_MA 5
SK
R/W
Mask for the
RW_PREAMBLE_ERR_STICKY bit
0: Interrupt disabled
1: Interrupt enabled
0x0
EGR_RW_FCS_ERR_MASK
4
R/W
Mask for the RW_FCS_ERR_STICKY bit
0: Interrupt disabled
1: Interrupt enabled
0x0
EGR_TS_LEVEL_MASK
3
R/W
Mask bit for TS_LEVEL_STICKY. When 1,
the interrupt is enabled.
0: Interrupt disabled
1: Interrupt enabled
0x0
EGR_TS_LOADED_MASK
2
R/W
Mask bit for TS_LOADED_STICKY. When 1, 0x0
the interrupt is enabled.
0: Interrupt disabled
1: Interrupt enabled
EGR_TS_UNDERFLOW_MASK
1
R/W
Mask bit for TS_UNDERFLOW_STICKY.
When 1, the interrupt is enabled.
0: Interrupt disabled
1: Interrupt enabled
0x0
EGR_TS_OVERFLOW_MASK
0
R/W
Mask bit for TS_OVERFLOW_STICKY.
When 1, the interrupt is enabled.
0: Interrupt disabled
1: Interrupt enabled
0x0
VMDS-10510 VSC8574-02 Datasheet Revision 4.2
167
4.8.11.3
IP_1588:EGR_IP_1588_CFG_STAT:EGR_SPARE_REGISTER
Parent: IP_1588:EGR_IP_1588_CFG_STAT
Instances: 1
Table 183 • Fields in EGR_SPARE_REGISTER
Field Name
Bit
Access
Description
Default
EGR_SPARE_REGISTER
31:0
R/W
Spare scratchpad register
0x00000000
4.8.12
IP_1588:EGR_IP_1588_TSP
Parent:
Instances: 1
Configuration and status register set for the IEEE1588 timestamp processor
Table 184 • Registers in EGR_IP_1588_TSP
Register Name
Instances and
Offset within
Address
Register Group Spacing
Description
Details
EGR_TSP_CTRL
0x00000000
1
TSP control
Page 168
EGR_TSP_STAT
0x00000004
1
TSP status
Page 169
EGR_LOCAL_LATENCY
0x00000008
1
Local latency
Page 169
EGR_PATH_DELAY
0x0000000C
1
Path delay
Page 169
EGR_DELAY_ASYMMETRY
0x00000010
1
Delay asymmetry
Page 169
4.8.12.1
IP_1588:EGR_IP_1588_TSP:EGR_TSP_CTRL
Parent: IP_1588:EGR_IP_1588_TSP
Instances: 1
Table 185 • Fields in EGR_TSP_CTRL
Field Name
Bit
Access
Description
EGR_FRACT_NS_MODE
2
R/W
Selects a mode in which the fractional portion 0x0
of a second (in units of nanoseconds) is used
for timestamping. Only the operation of the
WRITE_NS, WRITE_NS_P2P, and
SUB_ADD PTP commands are affected by
the setting of this mode bit.
0: Select the total (summed) nanoseconds
for timestamping
1: Select the fractional portion in
nanoseconds for timestamping
EGR_SEL_EXT_SOF_IND
1
R/W
Select external pin start of frame indicator
0x0
0: Select internal PCS as the source of SOF
1: Select external pin as the source of SOF
VMDS-10510 VSC8574-02 Datasheet Revision 4.2
Default
168
Table 185 • Fields in EGR_TSP_CTRL (continued)
Field Name
Bit
Access
EGR_LOAD_DELAYS
0
One-shot One-shot loads local latency, path delay, and 0x0
DelayAsymmetry values into the timestamp
processor
4.8.12.2
Description
Default
IP_1588:EGR_IP_1588_TSP:EGR_TSP_STAT
Parent: IP_1588:EGR_IP_1588_TSP
Instances: 1
Table 186 • Fields in EGR_TSP_STAT
Field Name
Bit
Access
Description
Default
EGR_CF_TOO_BIG_STICKY
0
Sticky
Timestamp processor marked a calculated
correction field as too big
0: A calculated correction field that was too
big did occur
1: A calculated correction field that was too
big did not occur
0x0
4.8.12.3
IP_1588:EGR_IP_1588_TSP:EGR_LOCAL_LATENCY
Parent: IP_1588:EGR_IP_1588_TSP
Instances: 1
Table 187 • Fields in EGR_LOCAL_LATENCY
Field Name
Bit
Access
Description
Default
EGR_LOCAL_LATENCY
15:0
R/W
Local latency (nanoseconds)
0x0000
4.8.12.4
IP_1588:EGR_IP_1588_TSP:EGR_PATH_DELAY
Parent: IP_1588:EGR_IP_1588_TSP
Instances: 1
Table 188 • Fields in EGR_PATH_DELAY
Field Name
Bit
Access
Description
Default
EGR_PATH_DELAY
31:0
R/W
Path delay (nanoseconds)
0x00000000
4.8.12.5
IP_1588:EGR_IP_1588_TSP:EGR_DELAY_ASYMMETRY
Parent: IP_1588:EGR_IP_1588_TSP
Instances: 1
VMDS-10510 VSC8574-02 Datasheet Revision 4.2
169
Table 189 • Fields in EGR_DELAY_ASYMMETRY
Field Name
Bit
Access
Description
Default
EGR_DELAY_ASYMMETRY
31:0
R/W
Delay asymmetry (scaled nanoseconds)
0x00000000
4.8.13
IP_1588:EGR_IP_1588_DF
Parent:
Instances: 1
Configuration for the delay FIFO in the 1588 IP block. The delay FIFO will delay the data in a pipeline
governed by these settings.
Table 190 • Registers in EGR_IP_1588_DF
Register Name
Instances and
Offset within
Address
Register Group Spacing
EGR_DF_CTRL
0x00000000
4.8.13.1
1
Description
Details
Configuration and control
register for the delay FIFO
Page 170
IP_1588:EGR_IP_1588_DF:EGR_DF_CTRL
Parent: IP_1588:EGR_IP_1588_DF
Instances: 1
Table 191 • Fields in EGR_DF_CTRL
Field Name
Bit
Access
Description
EGR_DF_DEPTH
4:0
R/W
The index of the register stage in the delay
0x00
FIFO that is used for output. The actual delay
through the block is one more than the depth.
If depth is set to 2, then the delay is 3 clocks
as data is taken from stage 2. The depth
MUST be greater than 0 (depth of 0 is not
allowed).
Binary number >= 1
4.8.14
Default
IP_1588:EGR_IP_1588_TSFIFO
Parent:
Instances: 1
Configuration and status for the timestamp FIFO. This register is only usable if a timestamp FIFO has
been instantiated in the given direction (ingress or egress).
Note: The ingress timestamp FIFO is NOT required and may not be present. In that case, the ingress registers
will be unconnected.
VMDS-10510 VSC8574-02 Datasheet Revision 4.2
170
Table 192 • Registers in EGR_IP_1588_TSFIFO
Register Name
Instances and
Offset within
Address
Register Group Spacing
EGR_TSFIFO_CSR
0x00000000
1
Timestamp FIFO configuration Page 171
and status
EGR_TSFIFO_0
0x00000004
1
Data value from the timestamp Page 172
FIFO
EGR_TSFIFO_1
0x00000008
1
Data value from the timestamp Page 173
FIFO
EGR_TSFIFO_2
0x0000000C
1
Data value from the timestamp Page 173
FIFO
EGR_TSFIFO_3
0x00000010
1
Data value from the timestamp Page 173
FIFO
EGR_TSFIFO_4
0x00000014
1
Data value from the timestamp Page 174
FIFO
EGR_TSFIFO_5
0x00000018
1
Data value from the timestamp Page 174
FIFO
EGR_TSFIFO_6
0x0000001C
1
Data value from the timestamp Page 174
FIFO
EGR_TSFIFO_DROP_CNT
0x00000020
1
Count of dropped timestamps Page 174
4.8.14.1
Description
Details
IP_1588:EGR_IP_1588_TSFIFO:EGR_TSFIFO_CSR
Parent: IP_1588:EGR_IP_1588_TSFIFO
Instances: 1
Configuration and status register for the timestamp FIFO
Table 193 • Fields in EGR_TSFIFO_CSR
Field Name
Bit
Access
Description
EGR_TS_4BYTES
17
R/W
Selects a smaller timestamp size to be stored 0x0
in the timestamp FIFO (4 bytes vs. the
default 10 bytes)
0: Full 10 byte timestamps are stored
1: Only 4 bytes of each timestamp are stored
EGR_TS_FIFO_RESET
16
R/W
Forces the TS_FIFO into the reset state
EGR_TS_LEVEL
15:12
R/O
The FIFO level associated with the last read 0x0
of the TS_EMPTY status field of the
TSFIFO_0 register
Binary number (0-8)
EGR_TS_THRESH
11:8
R/W
The threshold at which the timestamp FIFO
interrupt TS_LEVEL_STICKY will be set. If
the FIFO level reaches the threshold, the
sticky bit TS_LEVEL_STICKY will be set.
Binary number (1-8)
VMDS-10510 VSC8574-02 Datasheet Revision 4.2
Default
0x0
0x3
171
Table 193 • Fields in EGR_TSFIFO_CSR (continued)
Field Name
Bit
Access
Description
EGR_TS_SIGNAT_BYTES
4:0
R/W
Indicates the number of signature bytes used 0x00
for timestamps in the timestamp FIFO (0-16).
4.8.14.2
Default
IP_1588:EGR_IP_1588_TSFIFO:EGR_TSFIFO_0
Parent: IP_1588:EGR_IP_1588_TSFIFO
Instances: 1
Read the data from the timestamp FIFO along with the FIFO empty flag in the MSB
Table 194 • Fields in EGR_TSFIFO_0
Field Name
Bit
Access
Description
EGR_TS_EMPTY
31
R/O
The FIFO empty flag from the Timestamp
0x1
FIFO. If this bit is set, there is no FIFO data to
be read from the FIFO. The data in the
TSFIFO_x registers is not valid and should
be discarded. When 0, the FIFO has data
and the TSFIFO_x has a valid set of data.
This register can be polled and when the bit
is cleared, the other registers should be read
to get a full timestamp. When 1, the last data
has already been read out and the current
read data should be discarded.
Timestamp/Frame signature bytes are
packed such that the 10 or 4 byte timestamp
resides in the LEAST significant bytes while
the frame signature (0 to 16 bytes) resides in
the MOST significant bytes. The order of the
bytes within each timestamp/frame signature
field is also most significant to least
significant.
For example, 26 byte timestamp/frame
signature pairs are packed with the 10 byte
timestamp field ([79:0]) corresponding to Bits
79:0 in the following registers, and a 16 byte
frame signature field ([127:0]) corresponding
to Bits 207:80 in the following registers.
0: FIFO not empty, data valid
1: FIFO empty, data invalid
VMDS-10510 VSC8574-02 Datasheet Revision 4.2
Default
172
Table 194 • Fields in EGR_TSFIFO_0 (continued)
Field Name
Bit
Access
Description
EGR_TS_FLAGS
30:28
R/O
FIFO flags from the timestamp FIFO. These N/A
bits indicate how many timestamps are valid
in the current (not empty) 26 byte FIFO entry.
000: Only the end of a partial timestamp is
valid in the current FIFO entry (any remaining
data is invalid)
001: 1 valid timestamp begins in the current
FIFO entry (any remaining data is invalid)
010: 2 valid timestamps begin in the current
FIFO entry (any remaining data is invalid)
011: 3 valid timestamps begin in the current
FIFO entry (any remaining data is invalid)
100: 4 valid timestamps begin in the current
FIFO entry (any remaining data is invalid)
101: 5 valid timestamps begin in the current
FIFO entry (any remaining data is invalid)
110: 6 valid timestamps begin in the current
FIFO entry (any remaining data is invalid)
111: The current FIFO entry is fully packed
with timestamps (all data is valid)
EGR_TSFIFO_0
15:0
R/O
16 bits from the timestamp FIFO. Bits 15:0
4.8.14.3
Default
N/A
IP_1588:EGR_IP_1588_TSFIFO:EGR_TSFIFO_1
Parent: IP_1588:EGR_IP_1588_TSFIFO
Instances: 1
Read the data from the timestamp FIFO
Table 195 • Fields in EGR_TSFIFO_1
Field Name
Bit
Access
Description
EGR_TSFIFO_1
31:0
R/O
32 bits from the timestamp FIFO. Bits 47:16. N/A
4.8.14.4
Default
IP_1588:EGR_IP_1588_TSFIFO:EGR_TSFIFO_2
Parent: IP_1588:EGR_IP_1588_TSFIFO
Instances: 1
Read the data from the timestamp FIFO
Table 196 • Fields in EGR_TSFIFO_2
Field Name
Bit
Access
Description
EGR_TSFIFO_2
31:0
R/O
32 bits from the timestamp FIFO. Bits 79:48. N/A
4.8.14.5
Default
IP_1588:EGR_IP_1588_TSFIFO:EGR_TSFIFO_3
Parent: IP_1588:EGR_IP_1588_TSFIFO
Instances: 1
Read the data from the timestamp FIFO
VMDS-10510 VSC8574-02 Datasheet Revision 4.2
173
Table 197 • Fields in EGR_TSFIFO_3
Field Name
Bit
Access
Description
EGR_TSFIFO_3
31:0
R/O
32 bits from the timestamp FIFO. Bits 111:80. N/A
4.8.14.6
Default
IP_1588:EGR_IP_1588_TSFIFO:EGR_TSFIFO_4
Parent: IP_1588:EGR_IP_1588_TSFIFO
Instances: 1
Read the data from the timestamp FIFO
Table 198 • Fields in EGR_TSFIFO_4
Field Name
Bit
Access
Description
Default
EGR_TSFIFO_4
31:0
R/O
32 bits from the timestamp FIFO. Bits
143:112.
N/A
4.8.14.7
IP_1588:EGR_IP_1588_TSFIFO:EGR_TSFIFO_5
Parent: IP_1588:EGR_IP_1588_TSFIFO
Instances: 1
Read the data from the timestamp FIFO
Table 199 • Fields in EGR_TSFIFO_5
Field Name
Bit
Access
Description
Default
EGR_TSFIFO_5
31:0
R/O
32 bits from the timestamp FIFO. Bits
175:144.
N/A
4.8.14.8
IP_1588:EGR_IP_1588_TSFIFO:EGR_TSFIFO_6
Parent: IP_1588:EGR_IP_1588_TSFIFO
Instances: 1
Read the data from the timestamp FIFO
Table 200 • Fields in EGR_TSFIFO_6
Field Name
Bit
Access
Description
Default
EGR_TSFIFO_6
31:0
R/O
32 bits from the timestamp FIFO. Bits
207:176.
N/A
4.8.14.9
IP_1588:EGR_IP_1588_TSFIFO:EGR_TSFIFO_DROP_CNT
Parent: IP_1588:EGR_IP_1588_TSFIFO
Instances: 1
Count of dropped timestamps not enqueued to the TS FIFO
VMDS-10510 VSC8574-02 Datasheet Revision 4.2
174
Table 201 • Fields in EGR_TSFIFO_DROP_CNT
Field Name
Bit
Access
Description
Default
EGR_TS_FIFO_DROP_CNT
31:0
R/W
Timestamps dropped count
0x00000000
4.8.15
IP_1588:EGR_IP_1588_RW
Parent:
Instances: 1
Configuration and status for the 1588 rewriter
Table 202 • Registers in EGR_IP_1588_RW
Register Name
Instances and
Offset within
Address
Register Group Spacing
EGR_RW_CTRL
0x00000000
EGR_RW_MODFRM_CNT
EGR_RW_FCS_ERR_CNT
Description
Details
1
Rewriter configuration and
control
Page 175
0x00000004
1
Count of modified frames
Page 176
0x00000008
1
Count of FCS errors
Page 176
EGR_RW_PREAMBLE_ERR_CN 0x0000000C
T
1
Count of the number of
preamble errors
Page 176
4.8.15.1
IP_1588:EGR_IP_1588_RW:EGR_RW_CTRL
Parent: IP_1588:EGR_IP_1588_RW
Instances: 1
Configuration for the rewriter
Table 203 • Fields in EGR_RW_CTRL
Field Name
Bit
EGR_RW_REDUCE_PREAMBLE 4
Access
Description
Default
R/W
When set, the 1588 IP will reduce the
0x0
preamble of ALL incoming frames by 4 bytes
to allow a timestamp to be appended to the
ingress data frames. This bit must be set
along with the proper configuration of the
Analyzer to ensure proper operation.
Note: Valid in ingress direction only
0: No preamble modification
1: Reduce preamble by 4 bytes
EGR_RW_FLAG_VAL
3
R/W
Value to write to the flag bit when it is
overwritten
0: 0 will be written to the flag bit
1: 1 will be written to the flag bit
0x0
EGR_RW_FLAG_BIT
2:0
R/W
Bit offset within a byte of the flag bit that
indicates if the frame has been modified
0x0
VMDS-10510 VSC8574-02 Datasheet Revision 4.2
175
4.8.15.2
IP_1588:EGR_IP_1588_RW:EGR_RW_MODFRM_CNT
Parent: IP_1588:EGR_IP_1588_RW
Instances: 1
Table 204 • Fields in EGR_RW_MODFRM_CNT
Field Name
Bit
Access
Description
Default
EGR_RW_MODFRM_CNT
31:0
R/W
Count of the number of frames modified by
the 1588 IP. The counter wraps.
0x00000000
4.8.15.3
IP_1588:EGR_IP_1588_RW:EGR_RW_FCS_ERR_CNT
Parent: IP_1588:EGR_IP_1588_RW
Instances: 1
Table 205 • Fields in EGR_RW_FCS_ERR_CNT
Field Name
Bit
Access
Description
EGR_RW_FCS_ERR_CNT
31:0
R/W
Count of the number of FCS errored frames 0x00000000
detected by the rewriter. Counts only the FCS
errored frames that are modified.
4.8.15.4
Default
IP_1588:EGR_IP_1588_RW:EGR_RW_PREAMBLE_ERR_CNT
Parent: IP_1588:EGR_IP_1588_RW
Instances: 1
Table 206 • Fields in EGR_RW_PREAMBLE_ERR_CNT
Field Name
Bit
EGR_RW_PREAMBLE_ERR_CN 31:0
T
4.8.16
Access
Description
Default
R/W
Count of the number of errored preambles
detected. The counter wraps. An errored
preamble is a preamble that is too short to
shrink that is encountered when
RW_REDUCE_PREAMBLE is set.
Binary number
0x00000000
IP_1588:INGR_IP_1588_DEBUG_REGISTERS
Parent:
Instances: 1
VMDS-10510 VSC8574-02 Datasheet Revision 4.2
176
1588 IP internal status
Table 207 • INGR_IP_1588_DEBUG_REGISTERS
Field Name
Bit Access Description
INGR_SAFE_MODCHG_DIS
13
R/W
When set low, the mode change is a controlled 0x0
process that first forces bypass mode, then takes
effect after processing a single IDLE, then
release bypass mode. When asserted high,
changes to PROTOCOL_MODE take immediate
effect.
0 = Follow controlled mode changes
1 = Mode changes take immediate effect
Reserved
12
R/W
0x0
INGR_BYPASS_ON
11
R/W
Sticky bit. Indicates 1588 bypass is ON. Always
clears by writing 1.
0x01
INGR_BYPASS_IDLE
10
R/W
Sticky bit. Indicates 1588 has encountered at
least one IDLE at input and in process of
asserting bypass. Always clears by writing 1.
0x0
INGR_FIFO_LVL_OFF
9
R/W
Sticky bit. Indicates FIFO levels are non-zero in
steady state and were automatically emptied.
Always clears by writing 1.
0x0
INGR_AUTO_CLR_DONE
8
R/W
Sticky bit. If 1, indicates auto- clear operation
was completed. Always clears by writing ‘1’.
0x0
INGR_AUTO_CLR_CLKS
7:2 R/W
Only valid when AUTO_CLR_EN is high. After
encountering AUTO_CLR_CLKS (‘n’ number of
IDLEs), 1588 datapath FIFOs will empty. Only
valid for number greater than or equal to 0x1A.
1G: needs ‘n+1’*8 clock cycles.
100M: needs ‘n+1’*80 clock cycles
10M: needs ‘n+1’*800 clock cycles
0x1A
INGR_AUTO_CLR_EN
1
R/W
If enabled, 1588 will detect when FIFOs contain
stale entries. If contains entries in steady-state,
then after encountering AUTO_CLR_CLKS
number of IDLEs all 1588 FIFOs will
automatically empty.
0x1
INGR_SW_POP_FIFO
0
R/W
Self-clearing bit to manually drain all FIFOs
0x0
within 1588. Should only be asserted when 1588
is in the steady-state.
1.
4.8.17
Default
Bit may not be valid until a clear-by-write has been performed after a device power-on.
IP_1588:EGR_IP_1588_DEBUG_REGISTERS
Parent:
Instances: 1
VMDS-10510 VSC8574-02 Datasheet Revision 4.2
177
1588 IP internal status
Table 208 • EGR_IP_1588_DEBUG_REGISTERS
Field Name
Bit Access Description
EGR_SAFE_MODCHG_DIS
13
R/W
When set low, the mode change is a controlled 0x0
process that first forces bypass mode, then takes
effect after processing a single IDLE, then
release bypass mode. When asserted high,
changes to PROTOCOL_MODE take immediate
effect.
0 = Follow controlled mode changes
1 = Mode changes take immediate effect
Reserved
12
R/W
0x0
EGR_BYPASS_ON
11
R/W
Sticky bit. Indicates 1588 bypass is ON. Always
clears by writing 1.
0x01
EGR_BYPASS_IDLE
10
R/W
Sticky bit. Indicates 1588 has encountered at
least one IDLE at input and in process of
asserting bypass. Always clears by writing 1.
0x0
EGR_FIFO_LVL_OFF
9
R/W
Sticky bit. Indicates FIFO levels are non-zero in
steady state and were automatically emptied.
Always clears by writing 1.
0x0
EGR_AUTO_CLR_DONE
8
R/W
Sticky bit. If 1, indicates auto- clear operation
was completed. Always clears by writing ‘1’.
0x0
EGR_AUTO_CLR_CLKS
7:2 R/W
Only valid when AUTO_CLR_EN is high. After
encountering AUTO_CLR_CLKS (‘n’ number of
IDLEs), 1588 datapath FIFOs will empty. Only
valid for number greater than or equal to 0x1A.
1G: needs ‘n+1’*8 clock cycles.
100M: needs ‘n+1’*80 clock cycles
10M: needs ‘n+1’*800 clock cycles
0x1A
EGR_AUTO_CLR_EN
1
R/W
If enabled, 1588 will detect when FIFOs contain
stale entries. If contains entries in steady-state,
then after encountering AUTO_CLR_CLKS
number of IDLEs all 1588 FIFOs will
automatically empty.
0x1
EGR_SW_POP_FIFO
0
R/W
Self-clearing bit to manually drain all FIFOs
0x0
within 1588. Should only be asserted when 1588
is in the steady-state.
1.
4.9
Default
Bit may not be valid until a clear-by-write has been performed after a device power-on.
Egress0 Ethernet Comparator
Table 209 • Register Groups in Egress0 Ethernet Comparator
Register Group Name
Offset within
Target
Instances and
Address
Spacing
EGR0_ETH1_NXT_PROTOCOL
0x00000000
1
Description
Details
Ethernet next protocol
configuration
Page 179
VMDS-10510 VSC8574-02 Datasheet Revision 4.2
178
Table 209 • Register Groups in Egress0 Ethernet Comparator (continued)
Register Group Name
Offset within
Target
EGR0_ETH1_FLOW_CFG
0x00000040
EGR0_ETH2_NXT_PROTOCOL
EGR0_ETH2_FLOW_CFG
Instances and
Address
Spacing
Description
Details
8
0x00000040
Ethernet flow configuration
Page 181
0x00000240
1
Ethernet next protocol
configuration
Page 184
0x00000280
8
0x00000040
Ethernet flow configuration
Page 186
EGR0_MPLS_NXT_COMPARATO 0x00000480
R
1
MPLS next protocol register
Page 189
EGR0_MPLS_FLOW_CFG
0x000004C0
8
0x00000040
MPLS flow configuration
Page 190
EGR0_IP1_NXT_PROTOCOL
0x000006C0
1
IP1 next protocol
Page 193
EGR0_IP1_FLOW_CFG
0x00000700
8
0x00000040
IP1 flow configuration
Page 197
EGR0_IP2_NXT_PROTOCOL
0x00000900
1
IP2 next protocol
Page 200
EGR0_IP2_FLOW_CFG
0x00000940
8
0x00000040
IP2 flow configuration
Page 204
EGR0_PTP_FLOW
0x00000B40
6
0x00000040
PTP flow configuration
Page 207
EGR0_PTP_IP_CHKSUM_CTL
0x00000CC0
1
IP checksum field control
Page 211
EGR0_FRAME_SIG_CFG
0x00000CC4
1
Frame signature builder
configuration
Page 212
4.9.1
ETHERNET_COMPARATOR:EGR0_ETH1_NXT_PROTOCOL
Parent: Egress0 Ethernet Comparator
Instances: 1
Table 210 • Registers in EGR0_ETH1_NXT_PROTOCOL
Register Name
Instances and
Offset within
Address
Register Group Spacing
Description
EGR0_ETH1_NXT_PROTOCOL
0x00000000
1
Ethernet next protocol register Page 179
EGR0_ETH1_VLAN_TPID_CFG
0x00000004
1
VLAN TPID configuration
Page 180
EGR0_ETH1_TAG_MODE
0x00000008
1
Ethernet tag mode
Page 180
EGR0_ETH1_ETYPE_MATCH
0x0000000C
1
Ethertype match register
Page 180
4.9.1.1
Details
ETHERNET_COMPARATOR:EGR0_ETH1_NXT_PROTOCOL:EGR0_ETH1_NXT
_PROTOCOL
Parent: ETHERNET_COMPARATOR:EGR0_ETH1_NXT_PROTOCOL
Instances: 1
VMDS-10510 VSC8574-02 Datasheet Revision 4.2
179
Table 211 • Fields in EGR0_ETH1_NXT_PROTOCOL
Field Name
Access
Description
EGR0_ETH1_FRAME_SIG_OFFS 20:16
ET
R/W
Frame signature offset. Points to the start of 0x00
the byte field in the Ethernet frame that will
be used for the frame signature.
EGR0_ETH1_NXT_COMPARATO 2:0
R
R/W
Points to the next comparator block after this 0x0
Ethernet block
0: Reserved
1: Ethernet comparator 2
2: IP/UDP/ACH comparator 1
3: IP/UDP/ACH comparator 2
4: MPLS comparator
5: PTP/OAM comparator
6,7: Reserved
4.9.1.2
Bit
Default
ETHERNET_COMPARATOR:EGR0_ETH1_NXT_PROTOCOL:EGR0_ETH1_VLA
N_TPID_CFG
Parent: ETHERNET_COMPARATOR:EGR0_ETH1_NXT_PROTOCOL
Instances: 1
Table 212 • Fields in EGR0_ETH1_VLAN_TPID_CFG
Field Name
Bit
Access
Description
Default
EGR0_ETH1_VLAN_TPID_CFG
31:16
R/W
Configurable VLAN TPID (S or B-tag)
0x88A8
4.9.1.3
ETHERNET_COMPARATOR:EGR0_ETH1_NXT_PROTOCOL:EGR0_ETH1_TAG
_MODE
Parent: ETHERNET_COMPARATOR:EGR0_ETH1_NXT_PROTOCOL
Instances: 1
Table 213 • Fields in EGR0_ETH1_TAG_MODE
Field Name
Bit
Access
Description
EGR0_ETH1_PBB_ENA
0
R/W
This bit enables the presence of PBB.
0x0
The I-tag match bits are programmed in the
ETH1_VLAN_TAG_RANGE registers. The
mask bits are programmed in the
ETH1_VLAN_TAG2 registers. A B-tag if
present is configured in the
ETH1_VLAN_TAG1 registers.
0: PBB not enabled
1: Always expect PBB, last tag is always an Itag
4.9.1.4
Default
ETHERNET_COMPARATOR:EGR0_ETH1_NXT_PROTOCOL:EGR0_ETH1_ETY
PE_MATCH
Parent: ETHERNET_COMPARATOR:EGR0_ETH1_NXT_PROTOCOL
VMDS-10510 VSC8574-02 Datasheet Revision 4.2
180
Instances: 1
Table 214 • Fields in EGR0_ETH1_ETYPE_MATCH
Field Name
Bit
Access
Description
EGR0_ETH1_ETYPE_MATCH
15:0
R/W
If the Ethertype/length field is an Ethertype, 0x0000
then this register is compared against the
value. If the field is a length, the length value
is not checked.
4.9.2
Default
ETHERNET_COMPARATOR:EGR0_ETH1_FLOW_CFG
Parent: Egress0 Ethernet Comparator
Instances: 8
Table 215 • Registers in EGR0_ETH1_FLOW_CFG
Register Name
Instances and
Address
Offset within
Register Group Spacing
Description
Details
EGR0_ETH1_FLOW_ENABLE
0x00000000
1
Ethernet flow enable
Page 181
EGR0_ETH1_MATCH_MODE
0x00000004
1
Ethernet protocol match mode Page 182
EGR0_ETH1_ADDR_MATCH_1
0x00000008
1
Ethernet address match part 1 Page 183
EGR0_ETH1_ADDR_MATCH_2
0x0000000C
1
Ethernet address match part 2 Page 183
EGR0_ETH1_VLAN_TAG_RANG
E_I_TAG
0x00000010
1
Ethernet VLAN tag range
match register
Page 183
EGR0_ETH1_VLAN_TAG1
0x00000014
1
VLAN tag 1 match/mask
Page 184
EGR0_ETH1_VLAN_TAG2_I_TAG 0x00000018
1
Match/mask for VLAN tag 2 or Page 184
I-tag match
4.9.2.1
ETHERNET_COMPARATOR:EGR0_ETH1_FLOW_CFG:EGR0_ETH1_FLOW_EN
ABLE
Parent: ETHERNET_COMPARATOR:EGR0_ETH1_FLOW_CFG
Instances: 1
Table 216 • Fields in EGR0_ETH1_FLOW_ENABLE
Field Name
Bit
Access
Description
Default
EGR0_ETH1_CHANNEL_MASK
9:8
R/W
Channel mask
0x0: Flow invalid
0x1: Flow valid for channel 0
0x2: Flow valid for channel 1
0x3: Flow valid for both channels
0x3
EGR0_ETH1_FLOW_ENABLE
0
R/W
Flow enable
0: Flow disabled
1: Flow enabled
0x0
VMDS-10510 VSC8574-02 Datasheet Revision 4.2
181
4.9.2.2
ETHERNET_COMPARATOR:EGR0_ETH1_FLOW_CFG:EGR0_ETH1_MATCH_M
ODE
Parent: ETHERNET_COMPARATOR:EGR0_ETH1_FLOW_CFG
Instances: 1
Table 217 • Fields in EGR0_ETH1_MATCH_MODE
Field Name
Bit
Access
Description
Default
EGR0_ETH1_VLAN_TAG_MODE 13:12
R/W
VLAN tag mode configuration
0: VLAN range checking disabled
1: VLAN range checking on tag 1
2: VLAN range checking on tag 2 (not
supported with PBB)
3: Reserved
0x0
EGR0_ETH1_VLAN_TAG2_TYPE 9
R/W
VLAN tag2 type
This register is only used if
ETH1_VLAN_VERIFY_ENA = 1
If PBB not enabled:
0: C tag (TPID of 0x8100)
1: S tag (match to CONF_VLAN_TPID)
If PBB enabled:
0,1: I tag (use range registers)
0x1
EGR0_ETH1_VLAN_TAG1_TYPE 8
R/W
VLAN tag1 type
0x0
This register is only used if
ETH1_VLAN_VERIFY_ENA = 1
0: C tag (TPID of 0x8100)
1: S or B tag (match to CONF_VLAN_TPID)
EGR0_ETH1_VLAN_TAGS
R/W
VLAN tags
0x0
This register is only used if
ETH1_VLAN_VERIFY_ENA = 1
0: No VLAN tags (not valid for PBB)
1: 1 VLAN tag (for PBB this would be the Itag)
2: 2 VLAN tags (for PBB expect a B-tag and
an I-tag)
3: Reserved
EGR0_ETH1_VLAN_VERIFY_EN 4
A
R/W
Verify VLAN tags
0x0
0: Parse for VLAN tags, do not check values.
For PBB the I-tag is always checked.
1: Verify configured VLAN tag configuration.
EGR0_ETH1_ETHERTYPE_MOD 0
E
R/W
VLAN tag verification configuration
0x0
When checking for presence of SNAP/LLC
based upon ETH1_MATCH_MODE, this field
indicates if SNAP and 3-byte LLC is expected
to be present.
0: Only Ethernet type II supported, no
SNAP/LLC
1: Ethernet type II and Ethernet type I with
SNAP/LLC, determine if SNAP/LLC is
present or not. Type I always assumes that
SNAP/LLC is present.
7:6
VMDS-10510 VSC8574-02 Datasheet Revision 4.2
182
4.9.2.3
ETHERNET_COMPARATOR:EGR0_ETH1_FLOW_CFG:EGR0_ETH1_ADDR_MA
TCH_1
Parent: ETHERNET_COMPARATOR:EGR0_ETH1_FLOW_CFG
Instances: 1
Table 218 • Fields in EGR0_ETH1_ADDR_MATCH_1
Field Name
Bit
Access
Description
Default
EGR0_ETH1_ADDR_MATCH_1
31:0
R/W
First 32 bits of the address match value
0x00000000
4.9.2.4
ETHERNET_COMPARATOR:EGR0_ETH1_FLOW_CFG:EGR0_ETH1_ADDR_MA
TCH_2
Parent: ETHERNET_COMPARATOR:EGR0_ETH1_FLOW_CFG
Instances: 1
Table 219 • Fields in EGR0_ETH1_ADDR_MATCH_2
Field Name
Access
Description
EGR0_ETH1_ADDR_MATCH_MO 22:20
DE
R/W
Selects how the addresses are matched.
0x1
One-hot encoded. Multiple bits can be set at
once.
0: Full 48-bit address match
1: Match any unicast address
2: Match any muliticast address
EGR0_ETH1_ADDR_MATCH_SE 17:16
LECT
R/W
Selects which address to match
0: Match the destination address
1: Match the source address
2: Match either the source of destination
address
3: Reserved
0x0
EGR0_ETH1_ADDR_MATCH_2
R/W
Last 16 bits of the Ethernet address match
field
0x0000
4.9.2.5
Bit
15:0
Default
ETHERNET_COMPARATOR:EGR0_ETH1_FLOW_CFG:EGR0_ETH1_VLAN_TA
G_RANGE_I_TAG
Parent: ETHERNET_COMPARATOR:EGR0_ETH1_FLOW_CFG
Instances: 1
Table 220 • Fields in EGR0_ETH1_VLAN_TAG_RANGE_I_TAG
Field Name
Bit
Access
Description
EGR0_ETH1_VLAN_TAG_RANG
E_UPPER
27:16
R/W
If PBB mode is not enabled, then this register 0xFFF
contains the upper range of the VLAN tag
range match.
If PBB mode is enabled, then this register
contains the upper 12 bits of the I-tag.
VMDS-10510 VSC8574-02 Datasheet Revision 4.2
Default
183
Table 220 • Fields in EGR0_ETH1_VLAN_TAG_RANGE_I_TAG (continued)
Field Name
Bit
Access
Description
EGR0_ETH1_VLAN_TAG_RANG
E_LOWER
11:0
R/W
If PBB mode is not enabled, then this register 0x000
contains the lower range of the VLAN tag
range match.
If PBB mode is enabled, then this register
contains the lower 12 bits of the I-tag.
4.9.2.6
Default
ETHERNET_COMPARATOR:EGR0_ETH1_FLOW_CFG:EGR0_ETH1_VLAN_TA
G1
Parent: ETHERNET_COMPARATOR:EGR0_ETH1_FLOW_CFG
Instances: 1
Table 221 • Fields in EGR0_ETH1_VLAN_TAG1
Field Name
Access
Description
Default
EGR0_ETH1_VLAN_TAG1_MASK 27:16
R/W
Mask value for VLAN tag 1
0xFFF
EGR0_ETH1_VLAN_TAG1_MATC 11:0
H
R/W
Match value for the first VLAN tag
0x000
4.9.2.7
Bit
ETHERNET_COMPARATOR:EGR0_ETH1_FLOW_CFG:EGR0_ETH1_VLAN_TA
G2_I_TAG
Parent: ETHERNET_COMPARATOR:EGR0_ETH1_FLOW_CFG
Instances: 1
Table 222 • Fields in EGR0_ETH1_VLAN_TAG2_I_TAG
Field Name
Access
Description
EGR0_ETH1_VLAN_TAG2_MASK 27:16
R/W
When PBB is not enabled, the mask field for 0xFFF
VLAN tag 2.
When PBB is enabled, the upper 12 bits of
the I-tag mask.
EGR0_ETH1_VLAN_TAG2_MATC 11:0
H
R/W
When PBB is not enabled, the match field for 0x000
VLAN Tag 2.
When PBB is enabled, the lower 12 bits of
the I-tag mask field.
4.9.3
Bit
Default
ETHERNET_COMPARATOR:EGR0_ETH2_NXT_PROTOCOL
Parent: Egress0 Ethernet Comparator
Instances: 1
VMDS-10510 VSC8574-02 Datasheet Revision 4.2
184
Table 223 • Registers in EGR0_ETH2_NXT_PROTOCOL
Register Name
Instances and
Offset within
Address
Register Group Spacing
Description
EGR0_ETH2_NXT_PROTOCOL
0x00000000
1
Ethernet next protocol register Page 185
EGR0_ETH2_VLAN_TPID_CFG
0x00000004
1
VLAN TPID configuration
Page 185
EGR0_ETH2_ETYPE_MATCH
0x00000008
1
Ethertype match register
Page 185
4.9.3.1
Details
ETHERNET_COMPARATOR:EGR0_ETH2_NXT_PROTOCOL:EGR0_ETH2_NXT
_PROTOCOL
Parent: ETHERNET_COMPARATOR:EGR0_ETH2_NXT_PROTOCOL
Instances: 1
Table 224 • Fields in EGR0_ETH2_NXT_PROTOCOL
Field Name
Access
Description
EGR0_ETH2_FRAME_SIG_OFFS 20:16
ET
R/W
Frame signature offset. Points to the start of 0x00
the byte field in the Ethernet frame that will
be used for the frame signature.
EGR0_ETH2_NXT_COMPARATO 2:0
R
R/W
Points to the next comparator block after this 0x0
Ethernet block. If this comparator block is not
used, this field must be set to 0.
0: Comparator block not used
1: Ethernet comparator 2
2: IP/UDP/ACH comparator 1
3: IP/UDP/ACH comparator 2
4: MPLS comparator
5: PTP/OAM comparator
6,7: Reserved
4.9.3.2
Bit
Default
ETHERNET_COMPARATOR:EGR0_ETH2_NXT_PROTOCOL:EGR0_ETH2_VLA
N_TPID_CFG
Parent: ETHERNET_COMPARATOR:EGR0_ETH2_NXT_PROTOCOL
Instances: 1
Table 225 • Fields in EGR0_ETH2_VLAN_TPID_CFG
Field Name
Bit
Access
Description
Default
EGR0_ETH2_VLAN_TPID_CFG
31:16
R/W
Configurable S-tag TPID
0x88A8
4.9.3.3
ETHERNET_COMPARATOR:EGR0_ETH2_NXT_PROTOCOL:EGR0_ETH2_ETY
PE_MATCH
Parent: ETHERNET_COMPARATOR:EGR0_ETH2_NXT_PROTOCOL
Instances: 1
VMDS-10510 VSC8574-02 Datasheet Revision 4.2
185
Table 226 • Fields in EGR0_ETH2_ETYPE_MATCH
Field Name
Bit
Access
Description
EGR0_ETH2_ETYPE_MATCH
15:0
R/W
If the Ethertype/length field is an Ethertype, 0x0000
then this register is compared against the
value. If the field is a length, the length value
is not checked.
4.9.4
Default
ETHERNET_COMPARATOR:EGR0_ETH2_FLOW_CFG
Parent: Egress0 Ethernet Comparator
Instances: 8
Table 227 • Registers in EGR0_ETH2_FLOW_CFG
Instances and
Offset within
Address
Register Group Spacing
Register Name
Description
Details
Page 186
EGR0_ETH2_FLOW_ENABLE
0x00000000
1
Ethernet flow enable
EGR0_ETH2_MATCH_MODE
0x00000004
1
Ethernet protocol match mode Page 187
EGR0_ETH2_ADDR_MATCH_1
0x00000008
1
Ethernet address match part 1 Page 187
EGR0_ETH2_ADDR_MATCH_2
0x0000000C
1
Ethernet address match part 2 Page 188
EGR0_ETH2_VLAN_TAG_RANG
E_I_TAG
0x00000010
1
Ethernet VLAN tag range
match register
Page 188
EGR0_ETH2_VLAN_TAG1
0x00000014
1
VLAN tag 1 match/mask
Page 188
EGR0_ETH2_VLAN_TAG2_I_TAG 0x00000018
1
Match/mask for VLAN tag 2 or Page 189
I-tag match
4.9.4.1
ETHERNET_COMPARATOR:EGR0_ETH2_FLOW_CFG:EGR0_ETH2_FLOW_EN
ABLE
Parent: ETHERNET_COMPARATOR:EGR0_ETH2_FLOW_CFG
Instances: 1
Table 228 • Fields in EGR0_ETH2_FLOW_ENABLE
Field Name
Bit
Access
Description
Default
EGR0_ETH2_CHANNEL_MASK
9:8
R/W
Channel mask
0x0: Flow invalid
0x1: Flow valid for channel 0
0x2: Flow valid for channel 1
0x3: Flow valid for both channels
0x3
EGR0_ETH2_FLOW_ENABLE
0
R/W
Flow enable.
If this comparator block is not used, all flow
enable bits must be set to 0.
0: Flow disabled
1: Flow enabled
0x0
VMDS-10510 VSC8574-02 Datasheet Revision 4.2
186
4.9.4.2
ETHERNET_COMPARATOR:EGR0_ETH2_FLOW_CFG:EGR0_ETH2_MATCH_M
ODE
Parent: ETHERNET_COMPARATOR:EGR0_ETH2_FLOW_CFG
Instances: 1
Table 229 • Fields in EGR0_ETH2_MATCH_MODE
Field Name
Access
Description
Default
EGR0_ETH2_VLAN_TAG_MODE 13:12
R/W
VLAN tag mode configuration
0: VLAN range checking disabled
1: VLAN range checking on tag 1
2: VLAN range checking on tag 2 (not
supported with PBB)
3: Reserved
0x0
EGR0_ETH2_VLAN_TAG2_TYPE 9
R/W
VLAN tag2 type
This register is only used if
ETH1_VLAN_VERIFY_ENA = 1
0: C tag (TPID of 0x8100)
1: S tag (match to CONF_VLAN_TPID)
0x1
EGR0_ETH2_VLAN_TAG1_TYPE 8
R/W
VLAN tag1 type
0x0
This register is only used if
ETH1_VLAN_VERIFY_ENA = 1
0: C tag (TPID of 0x8100)
1: S or B tag (match to CONF_VLAN_TPID)
EGR0_ETH2_VLAN_TAGS
R/W
VLAN tags
This register is only used if
ETH2_VLAN_VERIFY_ENA = 1
0: No VLAN tags
1: 1 VLAN tag
2: 2 VLAN tags
3: Reserved
EGR0_ETH2_VLAN_VERIFY_EN 4
A
R/W
0x0
Verify VLAN tags
0: Parse for VLAN tags, do not check values.
1: Verify configured VLAN tag configuration.
EGR0_ETH2_ETHERTYPE_MOD 0
E
R/W
VLAN tag verification configuration
0x0
When checking for presence of SNAP/LLC
based upon ETH1_MATCH_MODE, this field
indicates if SNAP and 3-byte LLC is expected
to be present.
0: Only Ethernet type II supported, no
SNAP/LLC
1: Ethernet type II and Ethernet type I with
SNAP/LLC, determine if SNAP/LLC is
present or not. Type I always assumes that
SNAP/LLC is present.
4.9.4.3
Bit
7:6
0x0
ETHERNET_COMPARATOR:EGR0_ETH2_FLOW_CFG:EGR0_ETH2_ADDR_MA
TCH_1
Parent: ETHERNET_COMPARATOR:EGR0_ETH2_FLOW_CFG
Instances: 1
VMDS-10510 VSC8574-02 Datasheet Revision 4.2
187
Table 230 • Fields in EGR0_ETH2_ADDR_MATCH_1
Field Name
Bit
Access
Description
Default
EGR0_ETH2_ADDR_MATCH_1
31:0
R/W
First 32 bits of the address match value
0x00000000
4.9.4.4
ETHERNET_COMPARATOR:EGR0_ETH2_FLOW_CFG:EGR0_ETH2_ADDR_MA
TCH_2
Parent: ETHERNET_COMPARATOR:EGR0_ETH2_FLOW_CFG
Instances: 1
Table 231 • Fields in EGR0_ETH2_ADDR_MATCH_2
Field Name
Access
Description
EGR0_ETH2_ADDR_MATCH_MO 22:20
DE
R/W
Selects how the addresses are matched.
0x1
One-hot encoded. Multiple bits can be set at
once.
0: Full 48-bit address match
1: Match any unicast address
2: Match any muliticast address
EGR0_ETH2_ADDR_MATCH_SE 17:16
LECT
R/W
Selects which address to match
0: Match the destination address
1: Match the source address
2: Match either the source of destination
address
3: Reserved
0x0
EGR0_ETH2_ADDR_MATCH_2
R/W
Last 16 bits of the Ethernet address match
field
0x0000
4.9.4.5
Bit
15:0
Default
ETHERNET_COMPARATOR:EGR0_ETH2_FLOW_CFG:EGR0_ETH2_VLAN_TA
G_RANGE_I_TAG
Parent: ETHERNET_COMPARATOR:EGR0_ETH2_FLOW_CFG
Instances: 1
Table 232 • Fields in EGR0_ETH2_VLAN_TAG_RANGE_I_TAG
Field Name
Bit
Access
Description
Default
EGR0_ETH2_VLAN_TAG_RANG
E_UPPER
27:16
R/W
Contains the upper range of the VLAN tag
range match
0xFFF
EGR0_ETH2_VLAN_TAG_RANG
E_LOWER
11:0
R/W
Contains the lower range of the VLAN tag
range match
0x000
4.9.4.6
ETHERNET_COMPARATOR:EGR0_ETH2_FLOW_CFG:EGR0_ETH2_VLAN_TA
G1
Parent: ETHERNET_COMPARATOR:EGR0_ETH2_FLOW_CFG
Instances: 1
VMDS-10510 VSC8574-02 Datasheet Revision 4.2
188
Table 233 • Fields in EGR0_ETH2_VLAN_TAG1
Field Name
Access
Description
Default
EGR0_ETH2_VLAN_TAG1_MASK 27:16
R/W
Mask value for VLAN tag 1
0xFFF
EGR0_ETH2_VLAN_TAG1_MATC 11:0
H
R/W
Match value for the first VLAN tag
0x000
4.9.4.7
Bit
ETHERNET_COMPARATOR:EGR0_ETH2_FLOW_CFG:EGR0_ETH2_VLAN_TA
G2_I_TAG
Parent: ETHERNET_COMPARATOR:EGR0_ETH2_FLOW_CFG
Instances: 1
Table 234 • Fields in EGR0_ETH2_VLAN_TAG2_I_TAG
Field Name
Access
Description
Default
EGR0_ETH2_VLAN_TAG2_MASK 27:16
R/W
Mask field for VLAN tag 2
0xFFF
EGR0_ETH2_VLAN_TAG2_MATC 11:0
H
R/W
Match field for VLAN Tag 2
0x000
4.9.5
Bit
ETHERNET_COMPARATOR:EGR0_MPLS_NXT_COMPARATOR
Parent: Egress0 Ethernet Comparator
Instances: 1
Table 235 • Registers in EGR0_MPLS_NXT_COMPARATOR
Register Name
Instances and
Offset within
Address
Register Group Spacing
EGR0_MPLS_NXT_COMPARATO 0x00000000
R
4.9.5.1
1
Description
Details
MPLS next protocol
comparator register
Page 189
ETHERNET_COMPARATOR:EGR0_MPLS_NXT_COMPARATOR:EGR0_MPLS_
NXT_COMPARATOR
Parent: ETHERNET_COMPARATOR:EGR0_MPLS_NXT_COMPARATOR
Instances: 1
Table 236 • Fields in EGR0_MPLS_NXT_COMPARATOR
Field Name
Bit
Access
Description
EGR0_MPLS_CTL_WORD
16
R/W
Indicates the presence of a control word after 0x0
the last label. The first 4 bits of the control
word are always 0.
0: No control word after the last label
1: Control word after the last label
VMDS-10510 VSC8574-02 Datasheet Revision 4.2
Default
189
Table 236 • Fields in EGR0_MPLS_NXT_COMPARATOR (continued)
Field Name
Bit
EGR0_MPLS_NXT_COMPARATO 2:0
R
4.9.6
Access
Description
Default
R/W
Points to the next comparator stage. If this
0x0
comparator block is not used, this field must
be set to 0.
0: Comparator block not used.
1: Ethernet comparator 2
2: IP/UDP/ACH comparator 1
3: IP/UDP/ACH comparator 2
4: Reserved
5: PTP/OAM comparator
6,7: Reserved
ETHERNET_COMPARATOR:EGR0_MPLS_FLOW_CFG
Parent: Egress0 Ethernet Comparator
Instances: 8
Table 237 • Registers in EGR0_MPLS_FLOW_CFG
Register Name
Instances and
Offset within
Address
Register Group Spacing
Description
Details
EGR0_MPLS_FLOW_CONTROL
0x00000000
1
MPLS flow control register
Page 190
EGR0_MPLS_LABEL_RANGE_L
OWER_0
0x00000008
1
MPLS label 0 match range
lower value
Page 191
EGR0_MPLS_LABEL_RANGE_U 0x0000000C
PPER_0
1
MPLS label 0 match range
upper value
Page 191
EGR0_MPLS_LABEL_RANGE_L
OWER_1
0x00000010
1
MPLS label 1 match range
lower value
Page 192
EGR0_MPLS_LABEL_RANGE_U 0x00000014
PPER_1
1
MPLS label 1 match range
upper value
Page 192
EGR0_MPLS_LABEL_RANGE_L
OWER_2
0x00000018
1
MPLS label 2 match range
lower value
Page 192
EGR0_MPLS_LABEL_RANGE_U 0x0000001C
PPER_2
1
MPLS label 2 match range
upper value
Page 192
EGR0_MPLS_LABEL_RANGE_L
OWER_3
0x00000020
1
MPLS label 3 match range
lower value
Page 193
EGR0_MPLS_LABEL_RANGE_U 0x00000024
PPER_3
1
MPLS label 3 match range
upper value
Page 193
4.9.6.1
ETHERNET_COMPARATOR:EGR0_MPLS_FLOW_CFG:EGR0_MPLS_FLOW_C
ONTROL
Parent: ETHERNET_COMPARATOR:EGR0_MPLS_FLOW_CFG
Instances: 1
VMDS-10510 VSC8574-02 Datasheet Revision 4.2
190
Table 238 • Fields in EGR0_MPLS_FLOW_CONTROL
Field Name
Bit
Access
Description
Default
EGR0_MPLS_CHANNEL_MASK
25:24
R/W
MPLS channel mask selector
0x0: Flow invalid
0x1: Flow valid for channel 0
0x2: Flow valid for channel 1
0x3: Flow valid for both channels
0x3
EGR0_MPLS_STACK_DEPTH
19:16
R/W
Stack depth configuration
Defines the allowable stack depths for
searches. The direction that the stack is
referenced is determined by the setting of
MPLS_REF_PNT. For each bit set, the
following table maps bits to stack depths:
0: Stack allowed to be 1 label deep
1: Stack allowed to be 2 labels deep
2: Stack allowed to be 3 labels deep
3: Stack allowed to be 4 labels deep
0x0
EGR0_MPLS_REF_PNT
4
R/W
Search direction for label matching
0x0
0: All searching is performed starting from the
top of the stack
1: All searching is performed from the end of
the stack
EGR0_MPLS_FLOW_ENA
0
R/W
Flow enable.
If this comparator block is not used, all flow
enable bits must be set to 0.
0: Flow is disabled
1: Flow is enabled
4.9.6.2
0x0
ETHERNET_COMPARATOR:EGR0_MPLS_FLOW_CFG:EGR0_MPLS_LABEL_R
ANGE_LOWER_0
Parent: ETHERNET_COMPARATOR:EGR0_MPLS_FLOW_CFG
Instances: 1
Table 239 • Fields in EGR0_MPLS_LABEL_RANGE_LOWER_0
Field Name
Bit
Access
Description
Default
EGR0_MPLS_LABEL_RANGE_L
OWER_0
19:0
R/W
Lower value for label 0 match range
0x00000
4.9.6.3
ETHERNET_COMPARATOR:EGR0_MPLS_FLOW_CFG:EGR0_MPLS_LABEL_R
ANGE_UPPER_0
Parent: ETHERNET_COMPARATOR:EGR0_MPLS_FLOW_CFG
Instances: 1
VMDS-10510 VSC8574-02 Datasheet Revision 4.2
191
Table 240 • Fields in EGR0_MPLS_LABEL_RANGE_UPPER_0
Field Name
Bit
EGR0_MPLS_LABEL_RANGE_U 19:0
PPER_0
4.9.6.4
Access
Description
Default
R/W
Upper value for label 0 match range
0xFFFFF
ETHERNET_COMPARATOR:EGR0_MPLS_FLOW_CFG:EGR0_MPLS_LABEL_R
ANGE_LOWER_1
Parent: ETHERNET_COMPARATOR:EGR0_MPLS_FLOW_CFG
Instances: 1
Table 241 • Fields in EGR0_MPLS_LABEL_RANGE_LOWER_1
Field Name
Bit
Access
Description
Default
EGR0_MPLS_LABEL_RANGE_L
OWER_1
19:0
R/W
Lower value for label 1 match range
0x00000
4.9.6.5
ETHERNET_COMPARATOR:EGR0_MPLS_FLOW_CFG:EGR0_MPLS_LABEL_R
ANGE_UPPER_1
Parent: ETHERNET_COMPARATOR:EGR0_MPLS_FLOW_CFG
Instances: 1
Table 242 • Fields in EGR0_MPLS_LABEL_RANGE_UPPER_1
Field Name
Bit
EGR0_MPLS_LABEL_RANGE_U 19:0
PPER_1
4.9.6.6
Access
Description
Default
R/W
Upper value for label 1 match range
0xFFFFF
ETHERNET_COMPARATOR:EGR0_MPLS_FLOW_CFG:EGR0_MPLS_LABEL_R
ANGE_LOWER_2
Parent: ETHERNET_COMPARATOR:EGR0_MPLS_FLOW_CFG
Instances: 1
Table 243 • Fields in EGR0_MPLS_LABEL_RANGE_LOWER_2
Field Name
Bit
Access
Description
Default
EGR0_MPLS_LABEL_RANGE_L
OWER_2
19:0
R/W
Lower value for label 2 match range
0x00000
4.9.6.7
ETHERNET_COMPARATOR:EGR0_MPLS_FLOW_CFG:EGR0_MPLS_LABEL_R
ANGE_UPPER_2
Parent: ETHERNET_COMPARATOR:EGR0_MPLS_FLOW_CFG
Instances: 1
VMDS-10510 VSC8574-02 Datasheet Revision 4.2
192
Table 244 • Fields in EGR0_MPLS_LABEL_RANGE_UPPER_2
Field Name
Bit
EGR0_MPLS_LABEL_RANGE_U 19:0
PPER_2
4.9.6.8
Access
Description
Default
R/W
Upper value for label 2 match range
0xFFFFF
ETHERNET_COMPARATOR:EGR0_MPLS_FLOW_CFG:EGR0_MPLS_LABEL_R
ANGE_LOWER_3
Parent: ETHERNET_COMPARATOR:EGR0_MPLS_FLOW_CFG
Instances: 1
Table 245 • Fields in EGR0_MPLS_LABEL_RANGE_LOWER_3
Field Name
Bit
Access
Description
Default
EGR0_MPLS_LABEL_RANGE_L
OWER_3
19:0
R/W
Lower value for label 3 match range
0x00000
4.9.6.9
ETHERNET_COMPARATOR:EGR0_MPLS_FLOW_CFG:EGR0_MPLS_LABEL_R
ANGE_UPPER_3
Parent: ETHERNET_COMPARATOR:EGR0_MPLS_FLOW_CFG
Instances: 1
Table 246 • Fields in EGR0_MPLS_LABEL_RANGE_UPPER_3
Field Name
Bit
EGR0_MPLS_LABEL_RANGE_U 19:0
PPER_3
4.9.7
Access
Description
Default
R/W
Upper value for label 3 match range
0xFFFFF
ETHERNET_COMPARATOR:EGR0_IP1_NXT_PROTOCOL
Parent: Egress0 Ethernet Comparator
Instances: 1
Table 247 • Registers in EGR0_IP1_NXT_PROTOCOL
Register Name
Instances and
Offset within
Address
Register Group Spacing
EGR0_IP1_NXT_COMPARATOR
0x00000000
EGR0_IP1_MODE
EGR0_IP1_PROT_MATCH_1
Description
Details
1
IP next comparator control
register
Page 194
0x00000004
1
IP comparator mode
Page 194
0x00000008
1
IP match register set 1
Page 195
EGR0_IP1_PROT_MATCH_2_UP 0x0000000C
PER
1
Upper portion of match
register 2
Page 195
VMDS-10510 VSC8574-02 Datasheet Revision 4.2
193
Table 247 • Registers in EGR0_IP1_NXT_PROTOCOL (continued)
Instances and
Offset within
Address
Register Group Spacing
Register Name
Description
Details
EGR0_IP1_PROT_MATCH_2_LO 0x00000010
WER
1
Lower portion of match
register 2
Page 195
EGR0_IP1_PROT_MASK_2_UPP 0x00000014
ER
1
Upper portion of match mask
register 2
Page 196
EGR0_IP1_PROT_MASK_2_LOW 0x00000018
ER
1
Lower portion of match mask
register 2
Page 196
EGR0_IP1_PROT_OFFSET_2
0x0000001C
1
IP match offset register set 2
Page 196
EGR0_IP1_UDP_CHKSUM_CFG
0x00000020
1
IP/UDP checksum control
register
Page 196
EGR0_IP1_FRAME_SIG_CFG
0x00000024
1
IP frame signature control
register
Page 197
4.9.7.1
ETHERNET_COMPARATOR:EGR0_IP1_NXT_PROTOCOL:EGR0_IP1_NXT_CO
MPARATOR
Parent: ETHERNET_COMPARATOR:EGR0_IP1_NXT_PROTOCOL
Instances: 1
Table 248 • Fields in EGR0_IP1_NXT_COMPARATOR
Field Name
Bit
Access
Description
EGR0_IP1_NXT_PROTOCOL
15:8
R/W
Number of bytes in this header, points to the 0x00
beginning of the next protocol.
EGR0_IP1_NXT_COMPARATOR
2:0
R/W
Points to the next comparator stage. If this
0x0
comparator block is not used, this field must
be set to 0.
0: Comparator block not used
1: Reserved
2: Reserved
3: IP/UDP/ACH comparator 2
4: Reserved
5: PTP/OAM comparator
6,7: Reserved
4.9.7.2
Default
ETHERNET_COMPARATOR:EGR0_IP1_NXT_PROTOCOL:EGR0_IP1_MODE
Parent: ETHERNET_COMPARATOR:EGR0_IP1_NXT_PROTOCOL
Instances: 1
Table 249 • Fields in EGR0_IP1_MODE
Field Name
Bit
Access
Description
Default
EGR0_IP1_FLOW_OFFSET
12:8
R/W
Points to the source address field in the IP
frame. Use 12 for IPv4 and 8 for IPv6.
0x0C
VMDS-10510 VSC8574-02 Datasheet Revision 4.2
194
Table 249 • Fields in EGR0_IP1_MODE (continued)
Field Name
Bit
Access
Description
Default
EGR0_IP1_MODE
1:0
R/W
IP mode
0: IPv4
1: IPv6
2: Other protocol, 32-bit address match
3: Other protocol, 128-bit address match
0x0
4.9.7.3
ETHERNET_COMPARATOR:EGR0_IP1_NXT_PROTOCOL:EGR0_IP1_PROT_M
ATCH_1
Parent: ETHERNET_COMPARATOR:EGR0_IP1_NXT_PROTOCOL
Instances: 1
Table 250 • Fields in EGR0_IP1_PROT_MATCH_1
Field Name
Bit
Access
Description
Default
EGR0_IP1_PROT_OFFSET_1
20:16
R/W
Points to the start of this match field relative
to the first byte of this protocol
0x00
EGR0_IP1_PROT_MASK_1
15:8
R/W
Mask field for IP_PROT_MATCH_1
0x00
EGR0_IP1_PROT_MATCH_1
7:0
R/W
8-bit match field
0x00
4.9.7.4
ETHERNET_COMPARATOR:EGR0_IP1_NXT_PROTOCOL:EGR0_IP1_PROT_M
ATCH_2_UPPER
Parent: ETHERNET_COMPARATOR:EGR0_IP1_NXT_PROTOCOL
Instances: 1
Table 251 • Fields in EGR0_IP1_PROT_MATCH_2_UPPER
Field Name
Bit
EGR0_IP1_PROT_MATCH_2_UP 31:0
PER
4.9.7.5
Access
Description
Default
R/W
64-bit match register for advancing to the
next protocol, upper portion.
0x00000000
ETHERNET_COMPARATOR:EGR0_IP1_NXT_PROTOCOL:EGR0_IP1_PROT_M
ATCH_2_LOWER
Parent: ETHERNET_COMPARATOR:EGR0_IP1_NXT_PROTOCOL
Instances: 1
Table 252 • Fields in EGR0_IP1_PROT_MATCH_2_LOWER
Field Name
Bit
EGR0_IP1_PROT_MATCH_2_LO 31:0
WER
Access
Description
Default
R/W
64-bit match register for advancing to the
next protocol, lower portion.
0x00000000
VMDS-10510 VSC8574-02 Datasheet Revision 4.2
195
4.9.7.6
ETHERNET_COMPARATOR:EGR0_IP1_NXT_PROTOCOL:EGR0_IP1_PROT_M
ASK_2_UPPER
Parent: ETHERNET_COMPARATOR:EGR0_IP1_NXT_PROTOCOL
Instances: 1
Table 253 • Fields in EGR0_IP1_PROT_MASK_2_UPPER
Field Name
Bit
EGR0_IP1_PROT_MASK_2_UPP 31:0
ER
4.9.7.7
Access
Description
Default
R/W
64-bit match register for advancing to the
next protocol, upper portion.
0x00000000
ETHERNET_COMPARATOR:EGR0_IP1_NXT_PROTOCOL:EGR0_IP1_PROT_M
ASK_2_LOWER
Parent: ETHERNET_COMPARATOR:EGR0_IP1_NXT_PROTOCOL
Instances: 1
Table 254 • Fields in EGR0_IP1_PROT_MASK_2_LOWER
Field Name
Bit
EGR0_IP1_PROT_MASK_2_LOW 31:0
ER
4.9.7.8
Access
Description
Default
R/W
64-bit match register for advancing to the
next protocol, lower portion.
0x00000000
ETHERNET_COMPARATOR:EGR0_IP1_NXT_PROTOCOL:EGR0_IP1_PROT_O
FFSET_2
Parent: ETHERNET_COMPARATOR:EGR0_IP1_NXT_PROTOCOL
Instances: 1
Table 255 • Fields in EGR0_IP1_PROT_OFFSET_2
Field Name
Bit
Access
Description
EGR0_IP1_PROT_OFFSET_2
6:0
R/W
Points to the start of match field 2 relative to 0x00
the first byte of this protocol
4.9.7.9
Default
ETHERNET_COMPARATOR:EGR0_IP1_NXT_PROTOCOL:EGR0_IP1_UDP_CH
KSUM_CFG
Parent: ETHERNET_COMPARATOR:EGR0_IP1_NXT_PROTOCOL
Instances: 1
VMDS-10510 VSC8574-02 Datasheet Revision 4.2
196
Table 256 • Fields in EGR0_IP1_UDP_CHKSUM_CFG
Field Name
Access
Description
Default
EGR0_IP1_UDP_CHKSUM_OFFS 15:8
ET
R/W
Pointer to the IP/UDP checksum field FOR
IPv4 frames or to the pad bytes of a
IPv6/UDP frame. For IPv4, it points to the
bytes that will be cleared. For IPv6, it points
to the bytes that will be updated to fix the
CRC.
0x00
EGR0_IP1_UDP_CHKSUM_WIDT 5:4
H
R/W
Specifies the length of the checksum field in 0x2
bytes
EGR0_IP1_UDP_CHKSUM_UPD
ATE_ENA
1
R/W
This bit and
0x0
IP_UDP_CHKSUM_CLEAR_ENA CANNOT
be set together
0: No pad byte field update
1: Update the pad bytes at the end of the
frame
EGR0_IP1_UDP_CHKSUM_CLEA 0
R_ENA
R/W
This bit and
IP_UDP_CHKSUM_UPDATE_ENA
CANNOT be set together
0: Do not clear the checksum
1: Clear the UDP checksum field in an IPv4
frame
4.9.7.10
Bit
0x0
ETHERNET_COMPARATOR:EGR0_IP1_NXT_PROTOCOL:EGR0_IP1_FRAME
_SIG_CFG
Parent: ETHERNET_COMPARATOR:EGR0_IP1_NXT_PROTOCOL
Instances: 1
Table 257 • Fields in EGR0_IP1_FRAME_SIG_CFG
Field Name
Bit
Access
Description
Default
EGR0_IP1_FRAME_SIG_OFFSE
T
4:0
R/W
Pointer to the start of the field that will be
used for the frame signature. Position is
relative to the first header byte of this IP
protocol. Only even values are allowed.
0x00
4.9.8
ETHERNET_COMPARATOR:EGR0_IP1_FLOW_CFG
Parent: Egress0 Ethernet Comparator
Instances: 8
Table 258 • Registers in EGR0_IP1_FLOW_CFG
Register Name
Instances and
Offset within
Address
Register Group Spacing
Description
Details
EGR0_IP1_FLOW_ENA
0x00000000
IP flow enable register
Page 198
1
VMDS-10510 VSC8574-02 Datasheet Revision 4.2
197
Table 258 • Registers in EGR0_IP1_FLOW_CFG (continued)
Instances and
Address
Offset within
Register Group Spacing
Register Name
Description
Details
EGR0_IP1_FLOW_MATCH_UPPE 0x00000004
R
1
Upper portion of the IP flow
match register
Page 198
EGR0_IP1_FLOW_MATCH_UPPE 0x00000008
R_MID
1
Upper mid portion of the IP
flow match register
Page 199
EGR0_IP1_FLOW_MATCH_LOW 0x0000000C
ER_MID
1
Lower mid portion of the IP
flow match register
Page 199
EGR0_IP1_FLOW_MATCH_LOW 0x00000010
ER
1
Lower portion of the IP flow
match register
Page 199
EGR0_IP1_FLOW_MASK_UPPE
R
0x00000014
1
IP flow match mask register,
bytes 12-15
Page 199
EGR0_IP1_FLOW_MASK_UPPE
R_MID
0x00000018
1
IP flow match mask register,
bytes 8-11
Page 200
EGR0_IP1_FLOW_MASK_LOWE 0x0000001C
R_MID
1
IP flow match mask register,
bytes 4-7
Page 200
EGR0_IP1_FLOW_MASK_LOWE 0x00000020
R
1
IP flow match mask register,
bytes 0-3
Page 200
4.9.8.1
ETHERNET_COMPARATOR:EGR0_IP1_FLOW_CFG:EGR0_IP1_FLOW_ENA
Parent: ETHERNET_COMPARATOR:EGR0_IP1_FLOW_CFG
Instances: 1
Table 259 • Fields in EGR0_IP1_FLOW_ENA
Field Name
Access
Description
Default
EGR0_IP1_FLOW_MATCH_MOD 9:8
E
R/W
Match mode
0: Match on source address
1: Match on destination address
2: Match on either source or destination
address
3: Reserved
0x0
EGR0_IP1_CHANNEL_MASK
5:4
R/W
Channel mask
0x0: Flow invalid
0x1: Flow valid for channel 0
0x2: Flow valid for channel 1
0x3: Flow valid for both channels
0x3
EGR0_IP1_FLOW_ENA
0
R/W
Flow enable.
If this comparator block is not used, all flow
enable bits must be set to 0.
0: Flow disabled
1: Flow enabled
0x0
4.9.8.2
Bit
ETHERNET_COMPARATOR:EGR0_IP1_FLOW_CFG:EGR0_IP1_FLOW_MATCH
_UPPER
Parent: ETHERNET_COMPARATOR:EGR0_IP1_FLOW_CFG
VMDS-10510 VSC8574-02 Datasheet Revision 4.2
198
Instances: 1
Table 260 • Fields in EGR0_IP1_FLOW_MATCH_UPPER
Field Name
Bit
EGR0_IP1_FLOW_MATCH_UPPE 31:0
R
4.9.8.3
Access
Description
Default
R/W
Match field for either the entire 32-bit
0x00000000
selected address for IPv4 or the upper 32 bits
of the selected address for IPv6
ETHERNET_COMPARATOR:EGR0_IP1_FLOW_CFG:EGR0_IP1_FLOW_MATCH
_UPPER_MID
Parent: ETHERNET_COMPARATOR:EGR0_IP1_FLOW_CFG
Instances: 1
Table 261 • Fields in EGR0_IP1_FLOW_MATCH_UPPER_MID
Field Name
Bit
EGR0_IP1_FLOW_MATCH_UPPE 31:0
R_MID
4.9.8.4
Access
Description
Default
R/W
Match bits for the upper middle 32 bits of the 0x00000000
IPv6 address
ETHERNET_COMPARATOR:EGR0_IP1_FLOW_CFG:EGR0_IP1_FLOW_MATCH
_LOWER_MID
Parent: ETHERNET_COMPARATOR:EGR0_IP1_FLOW_CFG
Instances: 1
Table 262 • Fields in EGR0_IP1_FLOW_MATCH_LOWER_MID
Field Name
Bit
EGR0_IP1_FLOW_MATCH_LOW 31:0
ER_MID
4.9.8.5
Access
Description
Default
R/W
Match bits for the lower middle 32 bits of the 0x00000000
IPv6 address
ETHERNET_COMPARATOR:EGR0_IP1_FLOW_CFG:EGR0_IP1_FLOW_MATCH
_LOWER
Parent: ETHERNET_COMPARATOR:EGR0_IP1_FLOW_CFG
Instances: 1
Table 263 • Fields in EGR0_IP1_FLOW_MATCH_LOWER
Field Name
Bit
EGR0_IP1_FLOW_MATCH_LOW 31:0
ER
4.9.8.6
Access
Description
Default
R/W
Match bits for the lower 32 bits of the IPv6
address
0x00000000
ETHERNET_COMPARATOR:EGR0_IP1_FLOW_CFG:EGR0_IP1_FLOW_MASK_
UPPER
Parent: ETHERNET_COMPARATOR:EGR0_IP1_FLOW_CFG
VMDS-10510 VSC8574-02 Datasheet Revision 4.2
199
Instances: 1
Table 264 • Fields in EGR0_IP1_FLOW_MASK_UPPER
Field Name
Bit
Access
Description
Default
EGR0_IP1_FLOW_MASK_UPPE
R
31:0
R/W
Address mask for the IP address
0x00000000
4.9.8.7
ETHERNET_COMPARATOR:EGR0_IP1_FLOW_CFG:EGR0_IP1_FLOW_MASK_
UPPER_MID
Parent: ETHERNET_COMPARATOR:EGR0_IP1_FLOW_CFG
Instances: 1
Table 265 • Fields in EGR0_IP1_FLOW_MASK_UPPER_MID
Field Name
Bit
Access
Description
EGR0_IP1_FLOW_MASK_UPPE
R_MID
31:0
R/W
These bits must be all 0 for IPv4 and any 32- 0x00000000
bit address match mode
4.9.8.8
Default
ETHERNET_COMPARATOR:EGR0_IP1_FLOW_CFG:EGR0_IP1_FLOW_MASK_
LOWER_MID
Parent: ETHERNET_COMPARATOR:EGR0_IP1_FLOW_CFG
Instances: 1
Table 266 • Fields in EGR0_IP1_FLOW_MASK_LOWER_MID
Field Name
Bit
EGR0_IP1_FLOW_MASK_LOWE 31:0
R_MID
4.9.8.9
Access
Description
Default
R/W
These bits must be all 0 for IPv4 and any 32- 0x00000000
bit address match mode
ETHERNET_COMPARATOR:EGR0_IP1_FLOW_CFG:EGR0_IP1_FLOW_MASK_
LOWER
Parent: ETHERNET_COMPARATOR:EGR0_IP1_FLOW_CFG
Instances: 1
Table 267 • Fields in EGR0_IP1_FLOW_MASK_LOWER
Field Name
Bit
EGR0_IP1_FLOW_MASK_LOWE 31:0
R
4.9.9
Access
Description
Default
R/W
These bits must be all 0 for IPv4 and any 32- 0x00000000
bit address match mode
ETHERNET_COMPARATOR:EGR0_IP2_NXT_PROTOCOL
Parent: Egress0 Ethernet Comparator
Instances: 1
VMDS-10510 VSC8574-02 Datasheet Revision 4.2
200
Table 268 • Registers in EGR0_IP2_NXT_PROTOCOL
Register Name
Instances and
Offset within
Address
Register Group Spacing
EGR0_IP2_NXT_COMPARATOR
0x00000000
EGR0_IP2_MODE
EGR0_IP2_PROT_MATCH_1
Description
Details
1
IP next comparator control
register
Page 201
0x00000004
1
IP comparator mode
Page 201
0x00000008
1
IP match register set 1
Page 202
EGR0_IP2_PROT_MATCH_2_UP 0x0000000C
PER
1
Upper portion of match
register 2
Page 202
EGR0_IP2_PROT_MATCH_2_LO 0x00000010
WER
1
Lower portion of match
register 2
Page 202
EGR0_IP2_PROT_MASK_2_UPP 0x00000014
ER
1
Upper portion of match mask
register 2
Page 203
EGR0_IP2_PROT_MASK_2_LOW 0x00000018
ER
1
Lower portion of match mask
register 2
Page 203
EGR0_IP2_PROT_OFFSET_2
0x0000001C
1
IP match offset register set 2
Page 203
EGR0_IP2_UDP_CHKSUM_CFG
0x00000020
1
IP/UDP checksum control
register
Page 203
EGR0_IP2_FRAME_SIG_CFG
0x00000024
1
IP frame signature control
register
Page 204
4.9.9.1
ETHERNET_COMPARATOR:EGR0_IP2_NXT_PROTOCOL:EGR0_IP2_NXT_CO
MPARATOR
Parent: ETHERNET_COMPARATOR:EGR0_IP2_NXT_PROTOCOL
Instances: 1
Table 269 • Fields in EGR0_IP2_NXT_COMPARATOR
Field Name
Bit
Access
Description
EGR0_IP2_NXT_PROTOCOL
15:8
R/W
Number of bytes in this header, points to the 0x00
beginning of the next protocol.
EGR0_IP2_NXT_COMPARATOR
2:0
R/W
Points to the next comparator stage. If this
0x0
comparator block is not used, this field must
be set to 0.
0: Comparator block not used
1: Reserved
2: Reserved
3: Reserved
4: Reserved
5: PTP/OAM comparator
6,7: Reserved
4.9.9.2
Default
ETHERNET_COMPARATOR:EGR0_IP2_NXT_PROTOCOL:EGR0_IP2_MODE
Parent: ETHERNET_COMPARATOR:EGR0_IP2_NXT_PROTOCOL
Instances: 1
VMDS-10510 VSC8574-02 Datasheet Revision 4.2
201
Table 270 • Fields in EGR0_IP2_MODE
Field Name
Bit
Access
Description
Default
EGR0_IP2_FLOW_OFFSET
12:8
R/W
Points to the source address field in the IP
frame. Use 12 for IPv4 and 8 for IPv6
0x0C
EGR0_IP2_MODE
1:0
R/W
IP mode
0: IPv4
1: IPv6
2: Other protocol, 32-bit address match
3: Other protocol, 128-bit address match
0x0
4.9.9.3
ETHERNET_COMPARATOR:EGR0_IP2_NXT_PROTOCOL:EGR0_IP2_PROT_M
ATCH_1
Parent: ETHERNET_COMPARATOR:EGR0_IP2_NXT_PROTOCOL
Instances: 1
Table 271 • Fields in EGR0_IP2_PROT_MATCH_1
Field Name
Bit
Access
Description
Default
EGR0_IP2_PROT_OFFSET_1
20:16
R/W
Points to the start of this match field relative
to the first byte of this protocol
0x00
EGR0_IP2_PROT_MASK_1
15:8
R/W
Mask field for IP_PROT_MATCH_1
0x00
EGR0_IP2_PROT_MATCH_1
7:0
R/W
8-bit match field
0x00
4.9.9.4
ETHERNET_COMPARATOR:EGR0_IP2_NXT_PROTOCOL:EGR0_IP2_PROT_M
ATCH_2_UPPER
Parent: ETHERNET_COMPARATOR:EGR0_IP2_NXT_PROTOCOL
Instances: 1
Table 272 • Fields in EGR0_IP2_PROT_MATCH_2_UPPER
Field Name
Bit
EGR0_IP2_PROT_MATCH_2_UP 31:0
PER
4.9.9.5
Access
Description
Default
R/W
64-bit match register for advancing to the
next protocol, upper portion
0x00000000
ETHERNET_COMPARATOR:EGR0_IP2_NXT_PROTOCOL:EGR0_IP2_PROT_M
ATCH_2_LOWER
Parent: ETHERNET_COMPARATOR:EGR0_IP2_NXT_PROTOCOL
Instances: 1
Table 273 • Fields in EGR0_IP2_PROT_MATCH_2_LOWER
Field Name
Bit
EGR0_IP2_PROT_MATCH_2_LO 31:0
WER
Access
Description
Default
R/W
64-bit match register for advancing to the
next protocol, lower portion
0x00000000
VMDS-10510 VSC8574-02 Datasheet Revision 4.2
202
4.9.9.6
ETHERNET_COMPARATOR:EGR0_IP2_NXT_PROTOCOL:EGR0_IP2_PROT_M
ASK_2_UPPER
Parent: ETHERNET_COMPARATOR:EGR0_IP2_NXT_PROTOCOL
Instances: 1
Table 274 • Fields in EGR0_IP2_PROT_MASK_2_UPPER
Field Name
Bit
EGR0_IP2_PROT_MASK_2_UPP 31:0
ER
4.9.9.7
Access
Description
Default
R/W
64-bit match register for advancing to the
next protocol, upper portion.
0x00000000
ETHERNET_COMPARATOR:EGR0_IP2_NXT_PROTOCOL:EGR0_IP2_PROT_M
ASK_2_LOWER
Parent: ETHERNET_COMPARATOR:EGR0_IP2_NXT_PROTOCOL
Instances: 1
Table 275 • Fields in EGR0_IP2_PROT_MASK_2_LOWER
Field Name
Bit
EGR0_IP2_PROT_MASK_2_LOW 31:0
ER
4.9.9.8
Access
Description
Default
R/W
64-bit match register for advancing to the
next protocol, lower portion.
0x00000000
ETHERNET_COMPARATOR:EGR0_IP2_NXT_PROTOCOL:EGR0_IP2_PROT_O
FFSET_2
Parent: ETHERNET_COMPARATOR:EGR0_IP2_NXT_PROTOCOL
Instances: 1
Table 276 • Fields in EGR0_IP2_PROT_OFFSET_2
Field Name
Bit
Access
Description
EGR0_IP2_PROT_OFFSET_2
6:0
R/W
Points to the start of match field 2 relative to 0x00
the first byte of this protocol
4.9.9.9
Default
ETHERNET_COMPARATOR:EGR0_IP2_NXT_PROTOCOL:EGR0_IP2_UDP_CH
KSUM_CFG
Parent: ETHERNET_COMPARATOR:EGR0_IP2_NXT_PROTOCOL
Instances: 1
VMDS-10510 VSC8574-02 Datasheet Revision 4.2
203
Table 277 • Fields in EGR0_IP2_UDP_CHKSUM_CFG
Field Name
Access
Description
Default
EGR0_IP2_UDP_CHKSUM_OFFS 15:8
ET
R/W
Pointer to the IP/UDP checksum field FOR
IPv4 frames or to the pad bytes of a
IPv6/UDP frame. For IPv4, it points to the
bytes that will be cleared. For IPv6, it points
to the bytes that will be updated to fix the
CRC.
0x00
EGR0_IP2_UDP_CHKSUM_WIDT 5:4
H
R/W
Specifies the length of the checksum field in 0x2
bytes
EGR0_IP2_UDP_CHKSUM_UPD
ATE_ENA
1
R/W
This bit and
0x0
IP_UDP_CHKSUM_CLEAR_ENA CANNOT
be set together
0: No pad byte field update
1: Update the pad bytes at the end of the
frame
EGR0_IP2_UDP_CHKSUM_CLEA 0
R_ENA
R/W
This bit and
IP_UDP_CHKSUM_UPDATE_ENA
CANNOT be set together
0: Do not clear the checksum
1: Clear the UDP checksum field in an IPv4
frame
4.9.9.10
Bit
0x0
ETHERNET_COMPARATOR:EGR0_IP2_NXT_PROTOCOL:EGR0_IP2_FRAME
_SIG_CFG
Parent: ETHERNET_COMPARATOR:EGR0_IP2_NXT_PROTOCOL
Instances: 1
Table 278 • Fields in EGR0_IP2_FRAME_SIG_CFG
Field Name
Bit
Access
Description
Default
EGR0_IP2_FRAME_SIG_OFFSE
T
4:0
R/W
Pointer to the start of the field that will be
used for the frame signature. Position is
relative to the first header byte of this IP
protocol. Only even values are allowed.
0x00
4.9.10
ETHERNET_COMPARATOR:EGR0_IP2_FLOW_CFG
Parent: Egress0 Ethernet Comparator
Instances: 8
Table 279 • Registers in EGR0_IP2_FLOW_CFG
Register Name
Instances and
Offset within
Address
Register Group Spacing
Description
Details
EGR0_IP2_FLOW_ENA
0x00000000
IP flow enable register
Page 205
1
VMDS-10510 VSC8574-02 Datasheet Revision 4.2
204
Table 279 • Registers in EGR0_IP2_FLOW_CFG (continued)
Instances and
Address
Offset within
Register Group Spacing
Register Name
Description
Details
EGR0_IP2_FLOW_MATCH_UPPE 0x00000004
R
1
Upper portion of the IP flow
match register
Page 205
EGR0_IP2_FLOW_MATCH_UPPE 0x00000008
R_MID
1
Upper mid portion of the IP
flow match register
Page 206
EGR0_IP2_FLOW_MATCH_LOW 0x0000000C
ER_MID
1
Lower mid portion of the IP
flow match register
Page 206
EGR0_IP2_FLOW_MATCH_LOW 0x00000010
ER
1
Lower portion of the IP flow
match register
Page 206
EGR0_IP2_FLOW_MASK_UPPE
R
0x00000014
1
IP flow match mask register,
bytes 12-15
Page 206
EGR0_IP2_FLOW_MASK_UPPE
R_MID
0x00000018
1
IP flow match mask register,
bytes 8-11
Page 207
EGR0_IP2_FLOW_MASK_LOWE 0x0000001C
R_MID
1
IP flow match mask register,
bytes 4-7
Page 207
EGR0_IP2_FLOW_MASK_LOWE 0x00000020
R
1
IP flow match mask register,
bytes 0-3
Page 207
4.9.10.1
ETHERNET_COMPARATOR:EGR0_IP2_FLOW_CFG:EGR0_IP2_FLOW_ENA
Parent: ETHERNET_COMPARATOR:EGR0_IP2_FLOW_CFG
Instances: 1
Table 280 • Fields in EGR0_IP2_FLOW_ENA
Field Name
Access
Description
Default
EGR0_IP2_FLOW_MATCH_MOD 9:8
E
R/W
Match mode
0: Match on source address
1: Match on destination address
2: Match on either source or destination
address
3: Reserved
0x0
EGR0_IP2_CHANNEL_MASK
5:4
R/W
Channel mask
0x0: Flow invalid
0x1: Flow valid for channel 0
0x2: Flow valid for channel 1
0x3: Flow valid for both channels
0x3
EGR0_IP2_FLOW_ENA
0
R/W
Flow enable.
If this comparator block is not used, all flow
enable bits must be set to 0.
0: Flow disabled
1: Flow enabled
0x0
4.9.10.2
Bit
ETHERNET_COMPARATOR:EGR0_IP2_FLOW_CFG:EGR0_IP2_FLOW_MATC
H_UPPER
Parent: ETHERNET_COMPARATOR:EGR0_IP2_FLOW_CFG
VMDS-10510 VSC8574-02 Datasheet Revision 4.2
205
Instances: 1
Table 281 • Fields in EGR0_IP2_FLOW_MATCH_UPPER
Field Name
Bit
EGR0_IP2_FLOW_MATCH_UPPE 31:0
R
4.9.10.3
Access
Description
Default
R/W
Match field for either the entire 32-bit
0x00000000
selected address for IPv4 or the upper 32 bits
of the selected address for IPv6
ETHERNET_COMPARATOR:EGR0_IP2_FLOW_CFG:EGR0_IP2_FLOW_MATC
H_UPPER_MID
Parent: ETHERNET_COMPARATOR:EGR0_IP2_FLOW_CFG
Instances: 1
Table 282 • Fields in EGR0_IP2_FLOW_MATCH_UPPER_MID
Field Name
Bit
EGR0_IP2_FLOW_MATCH_UPPE 31:0
R_MID
4.9.10.4
Access
Description
Default
R/W
Match bits for the upper middle 32 bits of the 0x00000000
IPv6 address
ETHERNET_COMPARATOR:EGR0_IP2_FLOW_CFG:EGR0_IP2_FLOW_MATC
H_LOWER_MID
Parent: ETHERNET_COMPARATOR:EGR0_IP2_FLOW_CFG
Instances: 1
Table 283 • Fields in EGR0_IP2_FLOW_MATCH_LOWER_MID
Field Name
Bit
EGR0_IP2_FLOW_MATCH_LOW 31:0
ER_MID
4.9.10.5
Access
Description
Default
R/W
Match bits for the lower middle 32 bits of the 0x00000000
IPv6 address
ETHERNET_COMPARATOR:EGR0_IP2_FLOW_CFG:EGR0_IP2_FLOW_MATC
H_LOWER
Parent: ETHERNET_COMPARATOR:EGR0_IP2_FLOW_CFG
Instances: 1
Table 284 • Fields in EGR0_IP2_FLOW_MATCH_LOWER
Field Name
Bit
EGR0_IP2_FLOW_MATCH_LOW 31:0
ER
4.9.10.6
Access
Description
Default
R/W
Match bits for the lower 32 bits of the IPv6
address
0x00000000
ETHERNET_COMPARATOR:EGR0_IP2_FLOW_CFG:EGR0_IP2_FLOW_MASK
_UPPER
Parent: ETHERNET_COMPARATOR:EGR0_IP2_FLOW_CFG
VMDS-10510 VSC8574-02 Datasheet Revision 4.2
206
Instances: 1
Table 285 • Fields in EGR0_IP2_FLOW_MASK_UPPER
Field Name
Bit
Access
Description
Default
EGR0_IP2_FLOW_MASK_UPPE
R
31:0
R/W
Address mask for the IP address
0x00000000
4.9.10.7
ETHERNET_COMPARATOR:EGR0_IP2_FLOW_CFG:EGR0_IP2_FLOW_MASK
_UPPER_MID
Parent: ETHERNET_COMPARATOR:EGR0_IP2_FLOW_CFG
Instances: 1
Table 286 • Fields in EGR0_IP2_FLOW_MASK_UPPER_MID
Field Name
Bit
Access
Description
EGR0_IP2_FLOW_MASK_UPPE
R_MID
31:0
R/W
These bits must be all 0 for IPv4 and any 32- 0x00000000
bit address match mode
4.9.10.8
Default
ETHERNET_COMPARATOR:EGR0_IP2_FLOW_CFG:EGR0_IP2_FLOW_MASK
_LOWER_MID
Parent: ETHERNET_COMPARATOR:EGR0_IP2_FLOW_CFG
Instances: 1
Table 287 • Fields in EGR0_IP2_FLOW_MASK_LOWER_MID
Field Name
Bit
EGR0_IP2_FLOW_MASK_LOWE 31:0
R_MID
4.9.10.9
Access
Description
Default
R/W
These bits must be all 0 for IPv4 and any 32- 0x00000000
bit address match mode
ETHERNET_COMPARATOR:EGR0_IP2_FLOW_CFG:EGR0_IP2_FLOW_MASK
_LOWER
Parent: ETHERNET_COMPARATOR:EGR0_IP2_FLOW_CFG
Instances: 1
Table 288 • Fields in EGR0_IP2_FLOW_MASK_LOWER
Field Name
Bit
EGR0_IP2_FLOW_MASK_LOWE 31:0
R
4.9.11
Access
Description
Default
R/W
These bits must be all 0 for IPv4 and any 32- 0x00000000
bit address match mode
ETHERNET_COMPARATOR:EGR0_PTP_FLOW
Parent: Egress0 Ethernet Comparator
Instances: 6
VMDS-10510 VSC8574-02 Datasheet Revision 4.2
207
Table 289 • Registers in EGR0_PTP_FLOW
Register Name
Instances and
Offset within
Address
Register Group Spacing
Description
Details
EGR0_PTP_FLOW_ENA
0x00000000
1
PTP/OAM flow enable
Page 208
EGR0_PTP_FLOW_MATCH_UPP 0x00000004
ER
1
Upper half of PTP/OAM flow
match field
Page 208
EGR0_PTP_FLOW_MATCH_LOW 0x00000008
ER
1
Lower half of PTP/OAM flow
match field
Page 209
EGR0_PTP_FLOW_MASK_UPPE 0x0000000C
R
1
Upper half of PTP/OAM flow
match mask
Page 209
EGR0_PTP_FLOW_MASK_LOWE 0x00000010
R
1
Lower half of PTP/OAM flow
match mask
Page 209
EGR0_PTP_DOMAIN_RANGE
0x00000014
1
PTP/OAM range match
register
Page 209
EGR0_PTP_ACTION
0x00000018
1
PTP action control register
Page 210
EGR0_PTP_ACTION_2
0x0000001C
1
PTP action control register 2
Page 211
EGR0_PTP_ZERO_FIELD_CTL
0x00000020
1
Zero field control register
Page 211
4.9.11.1
ETHERNET_COMPARATOR:EGR0_PTP_FLOW:EGR0_PTP_FLOW_ENA
Parent: ETHERNET_COMPARATOR:EGR0_PTP_FLOW
Instances: 1
Table 290 • Fields in EGR0_PTP_FLOW_ENA
Field Name
Bit
Access
Description
Default
EGR0_PTP_CHANNEL_MASK
5:4
R/W
Channel mask
0x0: Flow invalid
0x1: Flow valid for channel 0
0x2: Flow valid for channel 1
0x3: Flow valid for both channels
0x3
EGR0_PTP_FLOW_ENA
0
R/W
Flow enable
0x0
4.9.11.2
ETHERNET_COMPARATOR:EGR0_PTP_FLOW:EGR0_PTP_FLOW_MATCH_U
PPER
Parent: ETHERNET_COMPARATOR:EGR0_PTP_FLOW
Instances: 1
Table 291 • Fields in EGR0_PTP_FLOW_MATCH_UPPER
Field Name
Bit
EGR0_PTP_FLOW_MATCH_UPP 31:0
ER
Access
Description
Default
R/W
PTP flow match, upper 32 bit
0x00000000
VMDS-10510 VSC8574-02 Datasheet Revision 4.2
208
4.9.11.3
ETHERNET_COMPARATOR:EGR0_PTP_FLOW:EGR0_PTP_FLOW_MATCH_L
OWER
Parent: ETHERNET_COMPARATOR:EGR0_PTP_FLOW
Instances: 1
Table 292 • Fields in EGR0_PTP_FLOW_MATCH_LOWER
Field Name
Bit
EGR0_PTP_FLOW_MATCH_LOW 31:0
ER
4.9.11.4
Access
Description
Default
R/W
PTP flow match, lower 32 bit
0x00000000
ETHERNET_COMPARATOR:EGR0_PTP_FLOW:EGR0_PTP_FLOW_MASK_UP
PER
Parent: ETHERNET_COMPARATOR:EGR0_PTP_FLOW
Instances: 1
Table 293 • Fields in EGR0_PTP_FLOW_MASK_UPPER
Field Name
Bit
EGR0_PTP_FLOW_MASK_UPPE 31:0
R
4.9.11.5
Access
Description
Default
R/W
PTP flow mask, upper 32 bit
0x00000000
ETHERNET_COMPARATOR:EGR0_PTP_FLOW:EGR0_PTP_FLOW_MASK_LO
WER
Parent: ETHERNET_COMPARATOR:EGR0_PTP_FLOW
Instances: 1
Table 294 • Fields in EGR0_PTP_FLOW_MASK_LOWER
Field Name
Bit
EGR0_PTP_FLOW_MASK_LOWE 31:0
R
4.9.11.6
Access
Description
Default
R/W
PTP flow mask, lower 32 bit
0x00000000
ETHERNET_COMPARATOR:EGR0_PTP_FLOW:EGR0_PTP_DOMAIN_RANGE
Parent: ETHERNET_COMPARATOR:EGR0_PTP_FLOW
Instances: 1
Table 295 • Fields in EGR0_PTP_DOMAIN_RANGE
Field Name
Bit
Access
Description
Default
EGR0_PTP_DOMAIN_RANGE_O 28:24
FFSET
R/W
PTP domain range offset
0x00
EGR0_PTP_DOMAIN_RANGE_U 23:16
PPER
R/W
Upper range of PTP domain field to match
0xFF
VMDS-10510 VSC8574-02 Datasheet Revision 4.2
209
Table 295 • Fields in EGR0_PTP_DOMAIN_RANGE (continued)
Field Name
Bit
Access
Description
Default
EGR0_PTP_DOMAIN_RANGE_L
OWER
15:8
R/W
Lower range of PTP domain field to match
0x00
R/W
Enable PTP domain range checking
0x0
EGR0_PTP_DOMAIN_RANGE_E 0
NA
4.9.11.7
ETHERNET_COMPARATOR:EGR0_PTP_FLOW:EGR0_PTP_ACTION
Parent: ETHERNET_COMPARATOR:EGR0_PTP_FLOW
Instances: 1
Table 296 • Fields in EGR0_PTP_ACTION
Field Name
Bit
Access
Description
Default
EGR0_PTP_MOD_FRAME_STAT 28
_UPDATE
R/W
Modified frame status update
0: Do not signal the rewriter to update value
of the Modified Frame Status bit
1: Signal the rewriter to update value of the
Modified Frame Status bit
0x0
EGR0_PTP_MOD_FRAME_BYTE 26:24
_OFFSET
R/W
Indicates the position relative to the start of
the PTP frame in bytes where the Modified
Frame Status bit resides
0x0
EGR0_PTP_SUB_DELAY_ASYM_ 21
ENA
R/W
Enable subtract delay asymmetry signal
0x0
0: Do not signal the timestamp block to
subtract the asymmetry delay
1: Signal the timestamp block to subtract the
asymmetry delay
EGR0_PTP_ADD_DELAY_ASYM 20
_ENA
R/W
Enable add delay asymmetry signal
0: Do not signal the timestamp block to add
the asymmetry delay
1: Signal the timestamp block to add the
asymmetry delay
0x0
EGR0_PTP_TIME_STRG_FIELD_ 15:10
OFFSET
R/W
Time storage field offset
The location in a PTP frame where a time
value can be stored or read
0x00
EGR0_PTP_CORR_FIELD_OFFS 9:5
ET
R/W
Points to the location of the correction field
for updating the timestamp. Location is
relative to the first byte of the PTP/OAM
header.
Note: If this flow is being used to
match OAM frames, set this
register to 4
0x00
EGR0_PTP_SAVE_LOCAL_TIME 4
R/W
Enable saving time
0x0
0: Do not save the time to the timestamp
FIFO
1: Save the local time to the timestamp FIFO
VMDS-10510 VSC8574-02 Datasheet Revision 4.2
210
Table 296 • Fields in EGR0_PTP_ACTION (continued)
Field Name
Bit
Access
Description
Default
EGR0_PTP_COMMAND
3:0
R/W
PTP action command
0: NOP
1: SUB
2: SUB_P2P
3: ADD
4: SUB_ADD
5: WRITE_1588
6: WRITE_P2P (deprecated)
7: WRITE_NS
8: WRITE_NS_P2P
0x0
4.9.11.8
ETHERNET_COMPARATOR:EGR0_PTP_FLOW:EGR0_PTP_ACTION_2
Parent: ETHERNET_COMPARATOR:EGR0_PTP_FLOW
Instances: 1
Table 297 • Fields in EGR0_PTP_ACTION_2
Field Name
Bit
Access
Description
EGR0_PTP_NEW_CF_LOC
23:16
R/W
Location of the new correction field relative to 0x00
the PTP header start. Only even values are
allowed.
EGR0_PTP_REWRITE_OFFSET
15:8
R/W
Points to where in the frame relative to the
SFD that the timestamp should be updated
0x00
EGR0_PTP_REWRITE_BYTES
3:0
R/W
Number of bytes in the PTP or OAM frame
that must be modified by the rewriter for the
timestamp
0x0
4.9.11.9
Default
ETHERNET_COMPARATOR:EGR0_PTP_FLOW:EGR0_PTP_ZERO_FIELD_CT
L
Parent: ETHERNET_COMPARATOR:EGR0_PTP_FLOW
Instances: 1
Table 298 • Fields in EGR0_PTP_ZERO_FIELD_CTL
Field Name
Access
Description
EGR0_PTP_ZERO_FIELD_OFFS 13:8
ET
R/W
Points to a location in the PTP/OAM frame
0x00
relative to the start of the PTP header that will
be zeroed if this function is enabled
EGR0_PTP_ZERO_FIELD_BYTE 3:0
_CNT
R/W
The number of bytes to be zeroed. If this field 0x0
is 0, then this function is not enabled.
4.9.12
Bit
Default
ETHERNET_COMPARATOR:EGR0_PTP_IP_CHKSUM_CTL
Parent: Egress0 Ethernet Comparator
Instances: 1
VMDS-10510 VSC8574-02 Datasheet Revision 4.2
211
Table 299 • Registers in EGR0_PTP_IP_CHKSUM_CTL
Register Name
Instances and
Offset within
Address
Register Group Spacing
Description
Details
EGR0_PTP_IP_CKSUM_SEL
0x00000000
IP checksum block select
Page 212
4.9.12.1
1
ETHERNET_COMPARATOR:EGR0_PTP_IP_CHKSUM_CTL:EGR0_PTP_IP_CK
SUM_SEL
Parent: ETHERNET_COMPARATOR:EGR0_PTP_IP_CHKSUM_CTL
Instances: 1
Table 300 • Fields in EGR0_PTP_IP_CKSUM_SEL
Field Name
Bit
Access
Description
Default
EGR0_PTP_IP_CHKSUM_SEL
0
R/W
IP checksum controls selection
0: Use the IP checksum controls from IP
comparator 1
1: Use the IP checksum controls from IP
comparator 2
0x0
4.9.13
ETHERNET_COMPARATOR:EGR0_FRAME_SIG_CFG
Parent: Egress0 Ethernet Comparator
Instances: 1
Table 301 • Registers in EGR0_FRAME_SIG_CFG
Register Name
Instances and
Offset within
Address
Register Group Spacing
EGR0_FSB_CFG
0x00000000
1
Frame signature builder mode Page 212
configuration
EGR0_FSB_MAP_REG_0
0x00000004
1
Frame signature builder
mapping register 0
Page 213
EGR0_FSB_MAP_REG_1
0x00000008
1
Frame signature builder
mapping register 1
Page 213
EGR0_FSB_MAP_REG_2
0x0000000C
1
Frame signature builder
mapping register 2
Page 214
EGR0_FSB_MAP_REG_3
0x00000010
1
Frame signature builder
mapping register 3
Page 214
4.9.13.1
Description
Details
ETHERNET_COMPARATOR:EGR0_FRAME_SIG_CFG:EGR0_FSB_CFG
Parent: ETHERNET_COMPARATOR:EGR0_FRAME_SIG_CFG
Instances: 1
VMDS-10510 VSC8574-02 Datasheet Revision 4.2
212
Table 302 • Fields in EGR0_FSB_CFG
Field Name
Bit
Access
EGR0_FSB_ADR_SEL
1:0
R/W
Description
Default
0x0
0: Use the address from Ethernet block 1
1: Use the address from Ethernet block 2
2: Use the address from IP block 1
3: Use the address from IP block 2
4.9.13.2
ETHERNET_COMPARATOR:EGR0_FRAME_SIG_CFG:EGR0_FSB_MAP_REG
_0
Parent: ETHERNET_COMPARATOR:EGR0_FRAME_SIG_CFG
Instances: 1
This register selects bytes to pack into the frame signature vector. The frame signature vector is 16 bytes
long. The source bytes are as follows:
select
source
select
source
select source
select source
----------------------------------------------------------------------------------------------------------------------------------0
PTP hdr byte 31
1
PTP hdr byte 30 2
PTP hdr byte 29
3
PTP hdr byte 28
4
PTP hdr byte 27
5
PTP hdr byte 26 6
PTP hdr byte 25
7
PTP hdr byte 24
8
PTP hdr byte 23
9
PTP hdr byte 22 10 PTP hdr byte 21
11 PTP hdr byte 20
12
PTP hdr byte 19
13 PTP hdr byte 18 14 PTP hdr byte 17
15 PTP hdr byte 16
16
PTP hdr byte 15
17 PTP hdr byte 14 18 PTP hdr byte 13
19 PTP hdr byte 12
20
PTP hdr byte 11
21 PTP hdr byte 10 22 PTP hdr byte 9
23 PTP hdr byte 8
24
PTP hdr byte 6
25 PTP hdr byte 4
26 PTP hdr byte 0
27 reserved
28
address byte 0
29 address byte 1
30 addess byte 2
31 address byte 3
32
address byte 4
33 address byte 5
34 addess byte 6
35 address byte 7
all other select values reserved
Table 303 • Fields in EGR0_FSB_MAP_REG_0
Field Name
Bit
Access
Description
Default
EGR0_FSB_MAP_4
29:24
R/W
Frame signature byte 4 select
0x04
EGR0_FSB_MAP_3
23:18
R/W
Frame signature byte 3 select
0x03
EGR0_FSB_MAP_2
17:12
R/W
Frame signature byte 2 select
0x02
EGR0_FSB_MAP_1
11:6
R/W
Frame signature byte 1 select
0x01
EGR0_FSB_MAP_0
5:0
R/W
Frame signature byte 0 select
0x00
4.9.13.3
ETHERNET_COMPARATOR:EGR0_FRAME_SIG_CFG:EGR0_FSB_MAP_REG
_1
Parent: ETHERNET_COMPARATOR:EGR0_FRAME_SIG_CFG
VMDS-10510 VSC8574-02 Datasheet Revision 4.2
213
Instances: 1
Table 304 • Fields in EGR0_FSB_MAP_REG_1
Field Name
Bit
Access
Description
Default
EGR0_FSB_MAP_9
29:24
R/W
Frame signature byte 9 select
0x09
EGR0_FSB_MAP_8
23:18
R/W
Frame signature byte 8 select
0x08
EGR0_FSB_MAP_7
17:12
R/W
Frame signature byte 7 select
0x07
EGR0_FSB_MAP_6
11:6
R/W
Frame signature byte 6 select
0x06
EGR0_FSB_MAP_5
5:0
R/W
Frame signature byte 5 select
0x05
4.9.13.4
ETHERNET_COMPARATOR:EGR0_FRAME_SIG_CFG:EGR0_FSB_MAP_REG
_2
Parent: ETHERNET_COMPARATOR:EGR0_FRAME_SIG_CFG
Instances: 1
Table 305 • Fields in EGR0_FSB_MAP_REG_2
Field Name
Bit
Access
Description
Default
EGR0_FSB_MAP_14
29:24
R/W
Frame signature byte 14 select
0x0E
EGR0_FSB_MAP_13
23:18
R/W
Frame signature byte 13 select
0x0D
EGR0_FSB_MAP_12
17:12
R/W
Frame signature byte 12 select
0x0C
EGR0_FSB_MAP_11
11:6
R/W
Frame signature byte 11 select
0x0B
EGR0_FSB_MAP_10
5:0
R/W
Frame signature byte 10 select
0x0A
4.9.13.5
ETHERNET_COMPARATOR:EGR0_FRAME_SIG_CFG:EGR0_FSB_MAP_REG
_3
Parent: ETHERNET_COMPARATOR:EGR0_FRAME_SIG_CFG
Instances: 1
Table 306 • Fields in EGR0_FSB_MAP_REG_3
Field Name
Bit
Access
Description
Default
EGR0_FSB_MAP_15
5:0
R/W
Frame signature byte 15 select
0x0F
4.10
Ingress0 Ethernet Comparator
Table 307 • Register Groups in Ingress0 Ethernet Comparator
Register Group Name
Offset within
Target
Instances and
Address
Spacing
INGR0_ETH1_NXT_PROTOCOL
0x00000000
1
Description
Details
Ethernet next protocol
configuration
Page 215
VMDS-10510 VSC8574-02 Datasheet Revision 4.2
214
Table 307 • Register Groups in Ingress0 Ethernet Comparator (continued)
Register Group Name
Offset within
Target
INGR0_ETH1_FLOW_CFG
0x00000040
INGR0_ETH2_NXT_PROTOCOL
Instances and
Address
Spacing
Description
Details
8
0x00000040
Ethernet flow configuration
Page 217
0x00000240
1
Ethernet next protocol
configuration
Page 220
INGR0_ETH2_FLOW_CFG
0x00000280
8
0x00000040
Ethernet flow configuration
Page 222
INGR0_MPLS_NXT_COMPARAT
OR
0x00000480
1
MPLS next protocol register
Page 225
INGR0_MPLS_FLOW_CFG
0x000004C0
8
0x00000040
MPLS flow configuration
Page 226
INGR0_IP1_NXT_PROTOCOL
0x000006C0
1
IP1 next protocol
Page 229
INGR0_IP1_FLOW_CFG
0x00000700
8
0x00000040
IP1 flow configuration
Page 233
INGR0_IP2_NXT_PROTOCOL
0x00000900
1
IP2 next protocol
Page 236
INGR0_IP2_FLOW_CFG
0x00000940
8
0x00000040
IP2 flow configuration
Page 240
INGR0_PTP_FLOW
0x00000B40
6
0x00000040
PTP flow configuration
Page 244
INGR0_PTP_IP_CHKSUM_CTL
0x00000CC0
1
IP checksum field control
Page 248
4.10.1
ETHERNET_COMPARATOR:INGR0_ETH1_NXT_PROTOCOL
Parent: Egress0 Ethernet Comparator
Instances: 1
Table 308 • Registers in INGR0_ETH1_NXT_PROTOCOL
Register Name
Instances and
Offset within
Address
Register Group Spacing
Description
INGR0_ETH1_NXT_PROTOCOL
0x00000000
1
Ethernet next protocol register Page 215
INGR0_ETH1_VLAN_TPID_CFG
0x00000004
1
VLAN TPID configuration
Page 216
INGR0_ETH1_TAG_MODE
0x00000008
1
Ethernet tag mode
Page 216
INGR0_ETH1_ETYPE_MATCH
0x0000000C
1
Ethertype match register
Page 216
4.10.1.1
Details
ETHERNET_COMPARATOR:INGR0_ETH1_NXT_PROTOCOL:INGR0_ETH1_N
XT_PROTOCOL
Parent: ETHERNET_COMPARATOR:INGR0_ETH1_NXT_PROTOCOL
Instances: 1
VMDS-10510 VSC8574-02 Datasheet Revision 4.2
215
Table 309 • Fields in INGR0_ETH1_NXT_PROTOCOL
Field Name
Access
Description
INGR0_ETH1_FRAME_SIG_OFF 20:16
SET
R/W
Frame signature offset. Points to the start of 0x00
the byte field in the Ethernet frame that will
be used for the frame signature.
INGR0_ETH1_NXT_COMPARATO 2:0
R
R/W
Points to the next comparator block after this 0x0
Ethernet block
0: Reserved
1: Ethernet comparator 2
2: IP/UDP/ACH comparator 1
3: IP/UDP/ACH comparator 2
4: MPLS comparator
5: PTP/OAM comparator
6,7: Reserved
4.10.1.2
Bit
Default
ETHERNET_COMPARATOR:INGR0_ETH1_NXT_PROTOCOL:INGR0_ETH1_VL
AN_TPID_CFG
Parent: ETHERNET_COMPARATOR:INGR0_ETH1_NXT_PROTOCOL
Instances: 1
Table 310 • Fields in INGR0_ETH1_VLAN_TPID_CFG
Field Name
Bit
Access
Description
Default
INGR0_ETH1_VLAN_TPID_CFG
31:16
R/W
Configurable VLAN TPID (S or B-tag)
0x88A8
4.10.1.3
ETHERNET_COMPARATOR:INGR0_ETH1_NXT_PROTOCOL:INGR0_ETH1_TA
G_MODE
Parent: ETHERNET_COMPARATOR:INGR0_ETH1_NXT_PROTOCOL
Instances: 1
Table 311 • Fields in INGR0_ETH1_TAG_MODE
Field Name
Bit
Access
Description
INGR0_ETH1_PBB_ENA
0
R/W
This bit enables the presence of PBB.
0x0
The I-tag match bits are programmed in the
ETH1_VLAN_TAG_RANGE registers. The
mask bits are programmed in the
ETH1_VLAN_TAG2 registers. A B-tag if
present is configured in the
ETH1_VLAN_TAG1 registers.
0: PBB not enabled
1: Always expect PBB, last tag is always an Itag
4.10.1.4
Default
ETHERNET_COMPARATOR:INGR0_ETH1_NXT_PROTOCOL:INGR0_ETH1_ET
YPE_MATCH
Parent: ETHERNET_COMPARATOR:INGR0_ETH1_NXT_PROTOCOL
VMDS-10510 VSC8574-02 Datasheet Revision 4.2
216
Instances: 1
Table 312 • Fields in INGR0_ETH1_ETYPE_MATCH
Field Name
Bit
Access
Description
INGR0_ETH1_ETYPE_MATCH
15:0
R/W
If the Ethertype/length field is an Ethertype, 0x0000
then this register is compared against the
value. If the field is a length, the length value
is not checked.
4.10.2
Default
ETHERNET_COMPARATOR:INGR0_ETH1_FLOW_CFG
Parent: Egress0 Ethernet Comparator
Instances: 8
Table 313 • Registers in INGR0_ETH1_FLOW_CFG
Register Name
Instances and
Address
Offset within
Register Group Spacing
Description
Details
INGR0_ETH1_FLOW_ENABLE
0x00000000
1
Ethernet flow enable
Page 217
INGR0_ETH1_MATCH_MODE
0x00000004
1
Ethernet protocol match mode Page 218
INGR0_ETH1_ADDR_MATCH_1
0x00000008
1
Ethernet address match part 1 Page 219
INGR0_ETH1_ADDR_MATCH_2
0x0000000C
1
Ethernet address match part 2 Page 219
INGR0_ETH1_VLAN_TAG_RANG 0x00000010
E_I_TAG
1
Ethernet VLAN tag range
match register
Page 219
INGR0_ETH1_VLAN_TAG1
0x00000014
1
VLAN tag 1 match/mask
Page 220
INGR0_ETH1_VLAN_TAG2_I_TA 0x00000018
G
1
Match/mask for VLAN tag 2 or Page 220
I-tag match
4.10.2.1
ETHERNET_COMPARATOR:INGR0_ETH1_FLOW_CFG:INGR0_ETH1_FLOW_
ENABLE
Parent: ETHERNET_COMPARATOR:INGR0_ETH1_FLOW_CFG
Instances: 1
Table 314 • Fields in INGR0_ETH1_FLOW_ENABLE
Field Name
Bit
Access
Description
Default
INGR0_ETH1_CHANNEL_MASK
9:8
R/W
Channel mask
0x0: Flow invalid
0x1: Flow valid for channel 0
0x2: Flow valid for channel 1
0x3: Flow valid for both channels
0x3
INGR0_ETH1_FLOW_ENABLE
0
R/W
Flow enable
0: Flow disabled
1: Flow enabled
0x0
VMDS-10510 VSC8574-02 Datasheet Revision 4.2
217
4.10.2.2
ETHERNET_COMPARATOR:INGR0_ETH1_FLOW_CFG:INGR0_ETH1_MATCH
_MODE
Parent: ETHERNET_COMPARATOR:INGR0_ETH1_FLOW_CFG
Instances: 1
Table 315 • Fields in INGR0_ETH1_MATCH_MODE
Field Name
Bit
Access
Description
Default
INGR0_ETH1_VLAN_TAG_MODE 13:12
R/W
VLAN tag mode configuration
0: VLAN range checking disabled
1: VLAN range checking on tag 1
2: VLAN range checking on tag 2 (not
supported with PBB)
3: Reserved
0x0
INGR0_ETH1_VLAN_TAG2_TYP
E
9
R/W
VLAN tag2 type
This register is only used if
ETH1_VLAN_VERIFY_ENA = 1
If PBB not enabled:
0: C tag (TPID of 0x8100)
1: S tag (match to CONF_VLAN_TPID)
If PBB enabled:
0,1: I tag (use range registers)
0x1
INGR0_ETH1_VLAN_TAG1_TYP
E
8
R/W
VLAN tag1 type
0x0
This register is only used if
ETH1_VLAN_VERIFY_ENA = 1
0: C tag (TPID of 0x8100)
1: S or B tag (match to CONF_VLAN_TPID)
INGR0_ETH1_VLAN_TAGS
7:6
R/W
VLAN tags
0x0
This register is only used if
ETH1_VLAN_VERIFY_ENA = 1
0: No VLAN tags (not valid for PBB)
1: 1 VLAN tag (for PBB this would be the Itag)
2: 2 VLAN tags (for PBB expect a B-tag and
an I-tag)
3: Reserved
INGR0_ETH1_VLAN_VERIFY_EN 4
A
R/W
Verify VLAN tags
0x0
0: Parse for VLAN tags, do not check values.
For PBB the I-tag is always checked.
1: Verify configured VLAN tag configuration.
INGR0_ETH1_ETHERTYPE_MO
DE
R/W
VLAN tag verification configuration
0x0
When checking for presence of SNAP/LLC
based upon ETH1_MATCH_MODE, this field
indicates if SNAP and 3-byte LLC is expected
to be present.
0: Only Ethernet type II supported, no
SNAP/LLC
1: Ethernet type II and Ethernet type I with
SNAP/LLC, determine if SNAP/LLC is
present or not. Type I always assumes that
SNAP/LLC is present.
0
VMDS-10510 VSC8574-02 Datasheet Revision 4.2
218
4.10.2.3
ETHERNET_COMPARATOR:INGR0_ETH1_FLOW_CFG:INGR0_ETH1_ADDR_
MATCH_1
Parent: ETHERNET_COMPARATOR:INGR0_ETH1_FLOW_CFG
Instances: 1
Table 316 • Fields in INGR0_ETH1_ADDR_MATCH_1
Field Name
Bit
Access
Description
Default
INGR0_ETH1_ADDR_MATCH_1
31:0
R/W
First 32 bits of the address match value
0x00000000
4.10.2.4
ETHERNET_COMPARATOR:INGR0_ETH1_FLOW_CFG:INGR0_ETH1_ADDR_
MATCH_2
Parent: ETHERNET_COMPARATOR:INGR0_ETH1_FLOW_CFG
Instances: 1
Table 317 • Fields in INGR0_ETH1_ADDR_MATCH_2
Field Name
Bit
Access
Description
INGR0_ETH1_ADDR_MATCH_M
ODE
22:20
R/W
Selects how the addresses are matched.
0x1
One-hot encoded. Multiple bits can be set at
once.
0: Full 48-bit address match
1: Match any unicast address
2: Match any muliticast address
INGR0_ETH1_ADDR_MATCH_SE 17:16
LECT
R/W
Selects which address to match
0: Match the destination address
1: Match the source address
2: Match either the source of destination
address
3: Reserved
0x0
INGR0_ETH1_ADDR_MATCH_2
R/W
Last 16 bits of the Ethernet address match
field
0x0000
4.10.2.5
15:0
Default
ETHERNET_COMPARATOR:INGR0_ETH1_FLOW_CFG:INGR0_ETH1_VLAN_T
AG_RANGE_I_TAG
Parent: ETHERNET_COMPARATOR:INGR0_ETH1_FLOW_CFG
Instances: 1
Table 318 • Fields in INGR0_ETH1_VLAN_TAG_RANGE_I_TAG
Field Name
Bit
INGR0_ETH1_VLAN_TAG_RANG 27:16
E_UPPER
Access
Description
R/W
If PBB mode is not enabled, then this register 0xFFF
contains the upper range of the VLAN tag
range match.
If PBB mode is enabled, then this register
contains the upper 12 bits of the I-tag.
VMDS-10510 VSC8574-02 Datasheet Revision 4.2
Default
219
Table 318 • Fields in INGR0_ETH1_VLAN_TAG_RANGE_I_TAG (continued)
Field Name
Bit
INGR0_ETH1_VLAN_TAG_RANG 11:0
E_LOWER
4.10.2.6
Access
Description
Default
R/W
If PBB mode is not enabled, then this register 0x000
contains the lower range of the VLAN tag
range match.
If PBB mode is enabled, then this register
contains the lower 12 bits of the I-tag.
ETHERNET_COMPARATOR:INGR0_ETH1_FLOW_CFG:INGR0_ETH1_VLAN_T
AG1
Parent: ETHERNET_COMPARATOR:INGR0_ETH1_FLOW_CFG
Instances: 1
Table 319 • Fields in INGR0_ETH1_VLAN_TAG1
Field Name
Access
Description
Default
INGR0_ETH1_VLAN_TAG1_MAS 27:16
K
R/W
Mask value for VLAN tag 1
0xFFF
INGR0_ETH1_VLAN_TAG1_MAT 11:0
CH
R/W
Match value for the first VLAN tag
0x000
4.10.2.7
Bit
ETHERNET_COMPARATOR:INGR0_ETH1_FLOW_CFG:INGR0_ETH1_VLAN_T
AG2_I_TAG
Parent: ETHERNET_COMPARATOR:INGR0_ETH1_FLOW_CFG
Instances: 1
Table 320 • Fields in INGR0_ETH1_VLAN_TAG2_I_TAG
Field Name
Access
Description
INGR0_ETH1_VLAN_TAG2_MAS 27:16
K
R/W
When PBB is not enabled, the mask field for 0xFFF
VLAN tag 2.
When PBB is enabled, the upper 12 bits of
the I-tag mask.
INGR0_ETH1_VLAN_TAG2_MAT 11:0
CH
R/W
When PBB is not enabled, the match field for 0x000
VLAN Tag 2.
When PBB is enabled, the lower 12 bits of
the I-tag mask field.
4.10.3
Bit
Default
ETHERNET_COMPARATOR:INGR0_ETH2_NXT_PROTOCOL
Parent: Egress0 Ethernet Comparator
Instances: 1
VMDS-10510 VSC8574-02 Datasheet Revision 4.2
220
Table 321 • Registers in INGR0_ETH2_NXT_PROTOCOL
Register Name
Instances and
Offset within
Address
Register Group Spacing
Description
INGR0_ETH2_NXT_PROTOCOL
0x00000000
1
Ethernet next protocol register Page 221
INGR0_ETH2_VLAN_TPID_CFG
0x00000004
1
VLAN TPID configuration
Page 221
INGR0_ETH2_ETYPE_MATCH
0x00000008
1
Ethertype match register
Page 221
4.10.3.1
Details
ETHERNET_COMPARATOR:INGR0_ETH2_NXT_PROTOCOL:INGR0_ETH2_N
XT_PROTOCOL
Parent: ETHERNET_COMPARATOR:INGR0_ETH2_NXT_PROTOCOL
Instances: 1
Table 322 • Fields in INGR0_ETH2_NXT_PROTOCOL
Field Name
Access
Description
INGR0_ETH2_FRAME_SIG_OFF 20:16
SET
R/W
Frame signature offset. Points to the start of 0x00
the byte field in the Ethernet frame that will
be used for the frame signature.
INGR0_ETH2_NXT_COMPARATO 2:0
R
R/W
Points to the next comparator block after this 0x0
Ethernet block. If this comparator block is not
used, this field must be set to 0.
0: Comparator block not used
1: Ethernet comparator 2
2: IP/UDP/ACH comparator 1
3: IP/UDP/ACH comparator 2
4: MPLS comparator
5: PTP/OAM comparator
6,7: Reserved
4.10.3.2
Bit
Default
ETHERNET_COMPARATOR:INGR0_ETH2_NXT_PROTOCOL:INGR0_ETH2_VL
AN_TPID_CFG
Parent: ETHERNET_COMPARATOR:INGR0_ETH2_NXT_PROTOCOL
Instances: 1
Table 323 • Fields in INGR0_ETH2_VLAN_TPID_CFG
Field Name
Bit
Access
Description
Default
INGR0_ETH2_VLAN_TPID_CFG
31:16
R/W
Configurable S-tag TPID
0x88A8
4.10.3.3
ETHERNET_COMPARATOR:INGR0_ETH2_NXT_PROTOCOL:INGR0_ETH2_ET
YPE_MATCH
Parent: ETHERNET_COMPARATOR:INGR0_ETH2_NXT_PROTOCOL
Instances: 1
VMDS-10510 VSC8574-02 Datasheet Revision 4.2
221
Table 324 • Fields in INGR0_ETH2_ETYPE_MATCH
Field Name
Bit
Access
Description
INGR0_ETH2_ETYPE_MATCH
15:0
R/W
If the Ethertype/length field is an Ethertype, 0x0000
then this register is compared against the
value. If the field is a length, the length value
is not checked.
4.10.4
Default
ETHERNET_COMPARATOR:INGR0_ETH2_FLOW_CFG
Parent: Egress0 Ethernet Comparator
Instances: 8
Table 325 • Registers in INGR0_ETH2_FLOW_CFG
Register Name
Instances and
Offset within
Address
Register Group Spacing
Description
Details
INGR0_ETH2_FLOW_ENABLE
0x00000000
1
Ethernet flow enable
Page 222
INGR0_ETH2_MATCH_MODE
0x00000004
1
Ethernet protocol match mode Page 223
INGR0_ETH2_ADDR_MATCH_1
0x00000008
1
Ethernet address match part 1 Page 223
INGR0_ETH2_ADDR_MATCH_2
0x0000000C
1
Ethernet address match part 2 Page 224
INGR0_ETH2_VLAN_TAG_RANG 0x00000010
E_I_TAG
1
Ethernet VLAN tag range
match register
Page 224
INGR0_ETH2_VLAN_TAG1
0x00000014
1
VLAN tag 1 match/mask
Page 224
INGR0_ETH2_VLAN_TAG2_I_TA 0x00000018
G
1
Match/mask for VLAN tag 2 or Page 225
I-tag match
4.10.4.1
ETHERNET_COMPARATOR:INGR0_ETH2_FLOW_CFG:INGR0_ETH2_FLOW_
ENABLE
Parent: ETHERNET_COMPARATOR:INGR0_ETH2_FLOW_CFG
Instances: 1
Table 326 • Fields in INGR0_ETH2_FLOW_ENABLE
Field Name
Bit
Access
Description
Default
INGR0_ETH2_CHANNEL_MASK
9:8
R/W
Channel mask
0x0: Flow invalid
0x1: Flow valid for channel 0
0x2: Flow valid for channel 1
0x3: Flow valid for both channels
0x3
INGR0_ETH2_FLOW_ENABLE
0
R/W
Flow enable.
If this comparator block is not used, all flow
enable bits must be set to 0.
0: Flow disabled
1: Flow enabled
0x0
VMDS-10510 VSC8574-02 Datasheet Revision 4.2
222
4.10.4.2
ETHERNET_COMPARATOR:INGR0_ETH2_FLOW_CFG:INGR0_ETH2_MATCH
_MODE
Parent: ETHERNET_COMPARATOR:INGR0_ETH2_FLOW_CFG
Instances: 1
Table 327 • Fields in INGR0_ETH2_MATCH_MODE
Field Name
Access
Description
Default
INGR0_ETH2_VLAN_TAG_MODE 13:12
R/W
VLAN tag mode configuration
0: VLAN range checking disabled
1: VLAN range checking on tag 1
2: VLAN range checking on tag 2 (not
supported with PBB)
3: Reserved
0x0
INGR0_ETH2_VLAN_TAG2_TYP
E
9
R/W
VLAN tag2 type
This register is only used if
ETH1_VLAN_VERIFY_ENA = 1
0: C tag (TPID of 0x8100)
1: S tag (match to CONF_VLAN_TPID)
0x1
INGR0_ETH2_VLAN_TAG1_TYP
E
8
R/W
VLAN tag1 type
0x0
This register is only used if
ETH1_VLAN_VERIFY_ENA = 1
0: C tag (TPID of 0x8100)
1: S or B tag (match to CONF_VLAN_TPID)
INGR0_ETH2_VLAN_TAGS
7:6
R/W
VLAN tags
This register is only used if
ETH2_VLAN_VERIFY_ENA = 1
0: No VLAN tags
1: 1 VLAN tag
2: 2 VLAN tags
3: Reserved
INGR0_ETH2_VLAN_VERIFY_EN 4
A
R/W
0x0
Verify VLAN tags
0: Parse for VLAN tags, do not check values.
1: Verify configured VLAN tag configuration.
INGR0_ETH2_ETHERTYPE_MO
DE
R/W
VLAN tag verification configuration
0x0
When checking for presence of SNAP/LLC
based upon ETH1_MATCH_MODE, this field
indicates if SNAP and 3-byte LLC is expected
to be present.
0: Only Ethernet type II supported, no
SNAP/LLC
1: Ethernet type II and Ethernet type I with
SNAP/LLC, determine if SNAP/LLC is
present or not. Type I always assumes that
SNAP/LLC is present.
4.10.4.3
Bit
0
0x0
ETHERNET_COMPARATOR:INGR0_ETH2_FLOW_CFG:INGR0_ETH2_ADDR_
MATCH_1
Parent: ETHERNET_COMPARATOR:INGR0_ETH2_FLOW_CFG
Instances: 1
VMDS-10510 VSC8574-02 Datasheet Revision 4.2
223
Table 328 • Fields in INGR0_ETH2_ADDR_MATCH_1
Field Name
Bit
Access
Description
Default
INGR0_ETH2_ADDR_MATCH_1
31:0
R/W
First 32 bits of the address match value
0x00000000
4.10.4.4
ETHERNET_COMPARATOR:INGR0_ETH2_FLOW_CFG:INGR0_ETH2_ADDR_
MATCH_2
Parent: ETHERNET_COMPARATOR:INGR0_ETH2_FLOW_CFG
Instances: 1
Table 329 • Fields in INGR0_ETH2_ADDR_MATCH_2
Field Name
Bit
Access
Description
INGR0_ETH2_ADDR_MATCH_M
ODE
22:20
R/W
Selects how the addresses are matched.
0x1
One-hot encoded. Multiple bits can be set at
once.
0: Full 48-bit address match
1: Match any unicast address
2: Match any muliticast address
INGR0_ETH2_ADDR_MATCH_SE 17:16
LECT
R/W
Selects which address to match
0: Match the destination address
1: Match the source address
2: Match either the source of destination
address
3: Reserved
0x0
INGR0_ETH2_ADDR_MATCH_2
R/W
Last 16 bits of the Ethernet address match
field
0x0000
4.10.4.5
15:0
Default
ETHERNET_COMPARATOR:INGR0_ETH2_FLOW_CFG:INGR0_ETH2_VLAN_T
AG_RANGE_I_TAG
Parent: ETHERNET_COMPARATOR:INGR0_ETH2_FLOW_CFG
Instances: 1
Table 330 • Fields in INGR0_ETH2_VLAN_TAG_RANGE_I_TAG
Field Name
Access
Description
Default
INGR0_ETH2_VLAN_TAG_RANG 27:16
E_UPPER
R/W
Contains the upper range of the VLAN tag
range match
0xFFF
INGR0_ETH2_VLAN_TAG_RANG 11:0
E_LOWER
R/W
Contains the lower range of the VLAN tag
range match
0x000
4.10.4.6
Bit
ETHERNET_COMPARATOR:INGR0_ETH2_FLOW_CFG:INGR0_ETH2_VLAN_T
AG1
Parent: ETHERNET_COMPARATOR:INGR0_ETH2_FLOW_CFG
Instances: 1
VMDS-10510 VSC8574-02 Datasheet Revision 4.2
224
Table 331 • Fields in INGR0_ETH2_VLAN_TAG1
Field Name
Access
Description
Default
INGR0_ETH2_VLAN_TAG1_MAS 27:16
K
R/W
Mask value for VLAN tag 1
0xFFF
INGR0_ETH2_VLAN_TAG1_MAT 11:0
CH
R/W
Match value for the first VLAN tag
0x000
4.10.4.7
Bit
ETHERNET_COMPARATOR:INGR0_ETH2_FLOW_CFG:INGR0_ETH2_VLAN_T
AG2_I_TAG
Parent: ETHERNET_COMPARATOR:INGR0_ETH2_FLOW_CFG
Instances: 1
Table 332 • Fields in INGR0_ETH2_VLAN_TAG2_I_TAG
Field Name
Access
Description
Default
INGR0_ETH2_VLAN_TAG2_MAS 27:16
K
R/W
Mask field for VLAN tag 2
0xFFF
INGR0_ETH2_VLAN_TAG2_MAT 11:0
CH
R/W
Match field for VLAN Tag 2
0x000
4.10.5
Bit
ETHERNET_COMPARATOR:INGR0_MPLS_NXT_COMPARATOR
Parent: Egress0 Ethernet Comparator
Instances: 1
Table 333 • Registers in INGR0_MPLS_NXT_COMPARATOR
Instances and
Offset within
Address
Register Group Spacing
Register Name
INGR0_MPLS_NXT_COMPARAT
OR
4.10.5.1
0x00000000
1
Description
Details
MPLS next protocol
comparator register
Page 225
ETHERNET_COMPARATOR:INGR0_MPLS_NXT_COMPARATOR:INGR0_MPL
S_NXT_COMPARATOR
Parent: ETHERNET_COMPARATOR:INGR0_MPLS_NXT_COMPARATOR
Instances: 1
VMDS-10510 VSC8574-02 Datasheet Revision 4.2
225
Table 334 • Fields in INGR0_MPLS_NXT_COMPARATOR
Field Name
Bit
Access
Description
INGR0_MPLS_CTL_WORD
16
R/W
Indicates the presence of a control word after 0x0
the last label. The first 4 bits of the control
word are always 0.
0: No control word after the last label
1: Control word after the last label
INGR0_MPLS_NXT_COMPARAT
OR
2:0
R/W
Points to the next comparator stage. If this
0x0
comparator block is not used, this field must
be set to 0.
0: Comparator block not used.
1: Ethernet comparator 2
2: IP/UDP/ACH comparator 1
3: IP/UDP/ACH comparator 2
4: Reserved
5: PTP/OAM comparator
6,7: Reserved
4.10.6
Default
ETHERNET_COMPARATOR:INGR0_MPLS_FLOW_CFG
Parent: Egress0 Ethernet Comparator
Instances: 8
Table 335 • Registers in INGR0_MPLS_FLOW_CFG
Register Name
Instances and
Offset within
Address
Register Group Spacing
Description
Details
INGR0_MPLS_FLOW_CONTROL 0x00000000
1
MPLS flow control register
Page 227
INGR0_MPLS_LABEL_RANGE_L 0x00000008
OWER_0
1
MPLS label 0 match range
lower value
Page 227
INGR0_MPLS_LABEL_RANGE_U 0x0000000C
PPER_0
1
MPLS label 0 match range
upper value
Page 227
INGR0_MPLS_LABEL_RANGE_L 0x00000010
OWER_1
1
MPLS label 1 match range
lower value
Page 228
INGR0_MPLS_LABEL_RANGE_U 0x00000014
PPER_1
1
MPLS label 1 match range
upper value
Page 228
INGR0_MPLS_LABEL_RANGE_L 0x00000018
OWER_2
1
MPLS label 2 match range
lower value
Page 228
INGR0_MPLS_LABEL_RANGE_U 0x0000001C
PPER_2
1
MPLS label 2 match range
upper value
Page 228
INGR0_MPLS_LABEL_RANGE_L 0x00000020
OWER_3
1
MPLS label 3 match range
lower value
Page 229
INGR0_MPLS_LABEL_RANGE_U 0x00000024
PPER_3
1
MPLS label 3 match range
upper value
Page 229
VMDS-10510 VSC8574-02 Datasheet Revision 4.2
226
4.10.6.1
ETHERNET_COMPARATOR:INGR0_MPLS_FLOW_CFG:INGR0_MPLS_FLOW
_CONTROL
Parent: ETHERNET_COMPARATOR:INGR0_MPLS_FLOW_CFG
Instances: 1
Table 336 • Fields in INGR0_MPLS_FLOW_CONTROL
Field Name
Access
Description
Default
INGR0_MPLS_CHANNEL_MASK 25:24
R/W
MPLS channel mask selector
0x0: Flow invalid
0x1: Flow valid for channel 0
0x2: Flow valid for channel 1
0x3: Flow valid for both channels
0x3
INGR0_MPLS_STACK_DEPTH
19:16
R/W
Stack depth configuration
Defines the allowable stack depths for
searches. The direction that the stack is
referenced is determined by the setting of
MPLS_REF_PNT. For each bit set, the
following table maps bits to stack depths:
0: Stack allowed to be 1 label deep
1: Stack allowed to be 2 labels deep
2: Stack allowed to be 3 labels deep
3: Stack allowed to be 4 labels deep
0x0
INGR0_MPLS_REF_PNT
4
R/W
Search direction for label matching
0x0
0: All searching is performed starting from the
top of the stack
1: All searching is performed from the end of
the stack
INGR0_MPLS_FLOW_ENA
0
R/W
Flow enable.
If this comparator block is not used, all flow
enable bits must be set to 0.
0: Flow is disabled
1: Flow is enabled
4.10.6.2
Bit
0x0
ETHERNET_COMPARATOR:INGR0_MPLS_FLOW_CFG:INGR0_MPLS_LABEL
_RANGE_LOWER_0
Parent: ETHERNET_COMPARATOR:INGR0_MPLS_FLOW_CFG
Instances: 1
Table 337 • Fields in INGR0_MPLS_LABEL_RANGE_LOWER_0
Field Name
Bit
INGR0_MPLS_LABEL_RANGE_L 19:0
OWER_0
4.10.6.3
Access
Description
Default
R/W
Lower value for label 0 match range
0x00000
ETHERNET_COMPARATOR:INGR0_MPLS_FLOW_CFG:INGR0_MPLS_LABEL
_RANGE_UPPER_0
Parent: ETHERNET_COMPARATOR:INGR0_MPLS_FLOW_CFG
Instances: 1
VMDS-10510 VSC8574-02 Datasheet Revision 4.2
227
Table 338 • Fields in INGR0_MPLS_LABEL_RANGE_UPPER_0
Field Name
Bit
INGR0_MPLS_LABEL_RANGE_U 19:0
PPER_0
4.10.6.4
Access
Description
Default
R/W
Upper value for label 0 match range
0xFFFFF
ETHERNET_COMPARATOR:INGR0_MPLS_FLOW_CFG:INGR0_MPLS_LABEL
_RANGE_LOWER_1
Parent: ETHERNET_COMPARATOR:INGR0_MPLS_FLOW_CFG
Instances: 1
Table 339 • Fields in INGR0_MPLS_LABEL_RANGE_LOWER_1
Field Name
Bit
INGR0_MPLS_LABEL_RANGE_L 19:0
OWER_1
4.10.6.5
Access
Description
Default
R/W
Lower value for label 1 match range
0x00000
ETHERNET_COMPARATOR:INGR0_MPLS_FLOW_CFG:INGR0_MPLS_LABEL
_RANGE_UPPER_1
Parent: ETHERNET_COMPARATOR:INGR0_MPLS_FLOW_CFG
Instances: 1
Table 340 • Fields in INGR0_MPLS_LABEL_RANGE_UPPER_1
Field Name
Bit
INGR0_MPLS_LABEL_RANGE_U 19:0
PPER_1
4.10.6.6
Access
Description
Default
R/W
Upper value for label 1 match range
0xFFFFF
ETHERNET_COMPARATOR:INGR0_MPLS_FLOW_CFG:INGR0_MPLS_LABEL
_RANGE_LOWER_2
Parent: ETHERNET_COMPARATOR:INGR0_MPLS_FLOW_CFG
Instances: 1
Table 341 • Fields in INGR0_MPLS_LABEL_RANGE_LOWER_2
Field Name
Bit
INGR0_MPLS_LABEL_RANGE_L 19:0
OWER_2
4.10.6.7
Access
Description
Default
R/W
Lower value for label 2 match range
0x00000
ETHERNET_COMPARATOR:INGR0_MPLS_FLOW_CFG:INGR0_MPLS_LABEL
_RANGE_UPPER_2
Parent: ETHERNET_COMPARATOR:INGR0_MPLS_FLOW_CFG
Instances: 1
VMDS-10510 VSC8574-02 Datasheet Revision 4.2
228
Table 342 • Fields in INGR0_MPLS_LABEL_RANGE_UPPER_2
Field Name
Bit
INGR0_MPLS_LABEL_RANGE_U 19:0
PPER_2
4.10.6.8
Access
Description
Default
R/W
Upper value for label 2 match range
0xFFFFF
ETHERNET_COMPARATOR:INGR0_MPLS_FLOW_CFG:INGR0_MPLS_LABEL
_RANGE_LOWER_3
Parent: ETHERNET_COMPARATOR:INGR0_MPLS_FLOW_CFG
Instances: 1
Table 343 • Fields in INGR0_MPLS_LABEL_RANGE_LOWER_3
Field Name
Bit
INGR0_MPLS_LABEL_RANGE_L 19:0
OWER_3
4.10.6.9
Access
Description
Default
R/W
Lower value for label 3 match range
0x00000
ETHERNET_COMPARATOR:INGR0_MPLS_FLOW_CFG:INGR0_MPLS_LABEL
_RANGE_UPPER_3
Parent: ETHERNET_COMPARATOR:INGR0_MPLS_FLOW_CFG
Instances: 1
Table 344 • Fields in INGR0_MPLS_LABEL_RANGE_UPPER_3
Field Name
Bit
INGR0_MPLS_LABEL_RANGE_U 19:0
PPER_3
4.10.7
Access
Description
Default
R/W
Upper value for label 3 match range
0xFFFFF
ETHERNET_COMPARATOR:INGR0_IP1_NXT_PROTOCOL
Parent: Egress0 Ethernet Comparator
Instances: 1
Table 345 • Registers in INGR0_IP1_NXT_PROTOCOL
Register Name
Instances and
Offset within
Address
Register Group Spacing
Description
Details
INGR0_IP1_NXT_COMPARATOR 0x00000000
1
IP next comparator control
register
Page 230
INGR0_IP1_MODE
0x00000004
1
IP comparator mode
Page 230
INGR0_IP1_PROT_MATCH_1
0x00000008
1
IP match register set 1
Page 231
INGR0_IP1_PROT_MATCH_2_UP 0x0000000C
PER
1
Upper portion of match
register 2
Page 231
VMDS-10510 VSC8574-02 Datasheet Revision 4.2
229
Table 345 • Registers in INGR0_IP1_NXT_PROTOCOL (continued)
Instances and
Offset within
Address
Register Group Spacing
Register Name
Description
Details
INGR0_IP1_PROT_MATCH_2_LO 0x00000010
WER
1
Lower portion of match
register 2
Page 231
INGR0_IP1_PROT_MASK_2_UPP 0x00000014
ER
1
Upper portion of match mask
register 2
Page 232
INGR0_IP1_PROT_MASK_2_LO
WER
0x00000018
1
Lower portion of match mask
register 2
Page 232
INGR0_IP1_PROT_OFFSET_2
0x0000001C
1
IP match offset register set 2
Page 232
INGR0_IP1_UDP_CHKSUM_CFG 0x00000020
1
IP/UDP checksum control
register
Page 232
4.10.7.1
ETHERNET_COMPARATOR:INGR0_IP1_NXT_PROTOCOL:INGR0_IP1_NXT_C
OMPARATOR
Parent: ETHERNET_COMPARATOR:INGR0_IP1_NXT_PROTOCOL
Instances: 1
Table 346 • Fields in INGR0_IP1_NXT_COMPARATOR
Field Name
Bit
Access
Description
INGR0_IP1_NXT_PROTOCOL
15:8
R/W
Number of bytes in this header, points to the 0x00
beginning of the next protocol.
R/W
Points to the next comparator stage. If this
0x0
comparator block is not used, this field must
be set to 0.
0: Comparator block not used
1: Reserved
2: Reserved
3: IP/UDP/ACH comparator 2
4: Reserved
5: PTP/OAM comparator
6,7: Reserved
INGR0_IP1_NXT_COMPARATOR 2:0
4.10.7.2
Default
ETHERNET_COMPARATOR:INGR0_IP1_NXT_PROTOCOL:INGR0_IP1_MODE
Parent: ETHERNET_COMPARATOR:INGR0_IP1_NXT_PROTOCOL
Instances: 1
Table 347 • Fields in INGR0_IP1_MODE
Field Name
Bit
Access
Description
Default
INGR0_IP1_FLOW_OFFSET
12:8
R/W
Points to the source address field in the IP
frame. Use 12 for IPv4 and 8 for IPv6.
0x0C
VMDS-10510 VSC8574-02 Datasheet Revision 4.2
230
Table 347 • Fields in INGR0_IP1_MODE (continued)
Field Name
Bit
Access
Description
Default
INGR0_IP1_MODE
1:0
R/W
IP mode
0: IPv4
1: IPv6
2: Other protocol, 32-bit address match
3: Other protocol, 128-bit address match
0x0
4.10.7.3
ETHERNET_COMPARATOR:INGR0_IP1_NXT_PROTOCOL:INGR0_IP1_PROT_
MATCH_1
Parent: ETHERNET_COMPARATOR:INGR0_IP1_NXT_PROTOCOL
Instances: 1
Table 348 • Fields in INGR0_IP1_PROT_MATCH_1
Field Name
Bit
Access
Description
Default
INGR0_IP1_PROT_OFFSET_1
20:16
R/W
Points to the start of this match field relative
to the first byte of this protocol
0x00
INGR0_IP1_PROT_MASK_1
15:8
R/W
Mask field for IP_PROT_MATCH_1
0x00
INGR0_IP1_PROT_MATCH_1
7:0
R/W
8-bit match field
0x00
4.10.7.4
ETHERNET_COMPARATOR:INGR0_IP1_NXT_PROTOCOL:INGR0_IP1_PROT_
MATCH_2_UPPER
Parent: ETHERNET_COMPARATOR:INGR0_IP1_NXT_PROTOCOL
Instances: 1
Table 349 • Fields in INGR0_IP1_PROT_MATCH_2_UPPER
Field Name
Bit
INGR0_IP1_PROT_MATCH_2_UP 31:0
PER
4.10.7.5
Access
Description
Default
R/W
64-bit match register for advancing to the
next protocol, upper portion
0x00000000
ETHERNET_COMPARATOR:INGR0_IP1_NXT_PROTOCOL:INGR0_IP1_PROT_
MATCH_2_LOWER
Parent: ETHERNET_COMPARATOR:INGR0_IP1_NXT_PROTOCOL
Instances: 1
Table 350 • Fields in INGR0_IP1_PROT_MATCH_2_LOWER
Field Name
Bit
INGR0_IP1_PROT_MATCH_2_LO 31:0
WER
Access
Description
Default
R/W
64-bit match register for advancing to the
next protocol, lower portion
0x00000000
VMDS-10510 VSC8574-02 Datasheet Revision 4.2
231
4.10.7.6
ETHERNET_COMPARATOR:INGR0_IP1_NXT_PROTOCOL:INGR0_IP1_PROT_
MASK_2_UPPER
Parent: ETHERNET_COMPARATOR:INGR0_IP1_NXT_PROTOCOL
Instances: 1
Table 351 • Fields in INGR0_IP1_PROT_MASK_2_UPPER
Field Name
Bit
INGR0_IP1_PROT_MASK_2_UPP 31:0
ER
4.10.7.7
Access
Description
R/W
Default
0x00000000
ETHERNET_COMPARATOR:INGR0_IP1_NXT_PROTOCOL:INGR0_IP1_PROT_
MASK_2_LOWER
Parent: ETHERNET_COMPARATOR:INGR0_IP1_NXT_PROTOCOL
Instances: 1
Table 352 • Fields in INGR0_IP1_PROT_MASK_2_LOWER
Field Name
Bit
Access
INGR0_IP1_PROT_MASK_2_LO
WER
31:0
R/W
4.10.7.8
Description
Default
0x00000000
ETHERNET_COMPARATOR:INGR0_IP1_NXT_PROTOCOL:INGR0_IP1_PROT_
OFFSET_2
Parent: ETHERNET_COMPARATOR:INGR0_IP1_NXT_PROTOCOL
Instances: 1
Table 353 • Fields in INGR0_IP1_PROT_OFFSET_2
Field Name
Bit
Access
Description
INGR0_IP1_PROT_OFFSET_2
6:0
R/W
Points to the start of match field 2 relative to 0x00
the first byte of this protocol
4.10.7.9
Default
ETHERNET_COMPARATOR:INGR0_IP1_NXT_PROTOCOL:INGR0_IP1_UDP_C
HKSUM_CFG
Parent: ETHERNET_COMPARATOR:INGR0_IP1_NXT_PROTOCOL
Instances: 1
VMDS-10510 VSC8574-02 Datasheet Revision 4.2
232
Table 354 • Fields in INGR0_IP1_UDP_CHKSUM_CFG
Field Name
Access
Description
Default
INGR0_IP1_UDP_CHKSUM_OFF 15:8
SET
R/W
Pointer to the IP/UDP checksum field FOR
IPv4 frames or to the pad bytes of a
IPv6/UDP frame. For IPv4, it points to the
bytes that will be cleared. For IPv6, it points
to the bytes that will be updated to fix the
CRC.
0x00
INGR0_IP1_UDP_CHKSUM_WID 5:4
TH
R/W
Specifies the length of the checksum field in 0x2
bytes
INGR0_IP1_UDP_CHKSUM_UPD 1
ATE_ENA
R/W
0x0
This bit and
IP_UDP_CHKSUM_CLEAR_ENA CANNOT
be set together
0: No pad byte field update
1: Update the pad bytes at the end of the
frame
INGR0_IP1_UDP_CHKSUM_CLE 0
AR_ENA
R/W
This bit and
IP_UDP_CHKSUM_UPDATE_ENA
CANNOT be set together
0: Do not clear the checksum
1: Clear the UDP checksum field in an IPv4
frame
4.10.8
Bit
0x0
ETHERNET_COMPARATOR:INGR0_IP1_FLOW_CFG
Parent: Egress0 Ethernet Comparator
Instances: 8
Table 355 • Registers in INGR0_IP1_FLOW_CFG
Register Name
Instances and
Offset within
Address
Register Group Spacing
Description
Details
INGR0_IP1_FLOW_ENA
0x00000000
1
IP flow enable register
Page 234
INGR0_IP1_FLOW_MATCH_UPP 0x00000004
ER
1
Upper portion of the IP flow
match register
Page 234
INGR0_IP1_FLOW_MATCH_UPP 0x00000008
ER_MID
1
Upper mid portion of the IP
flow match register
Page 234
INGR0_IP1_FLOW_MATCH_LOW 0x0000000C
ER_MID
1
Lower mid portion of the IP
flow match register
Page 235
INGR0_IP1_FLOW_MATCH_LOW 0x00000010
ER
1
Lower portion of the IP flow
match register
Page 235
INGR0_IP1_FLOW_MASK_UPPE 0x00000014
R
1
Upper portion of the IP flow
match mask register
Page 235
INGR0_IP1_FLOW_MASK_UPPE 0x00000018
R_MID
1
Upper mid portion of the IP
flow match mask register
Page 235
INGR0_IP1_FLOW_MASK_LOWE 0x0000001C
R_MID
1
Lower mid portion of the IP
flow match mask register
Page 236
VMDS-10510 VSC8574-02 Datasheet Revision 4.2
233
Table 355 • Registers in INGR0_IP1_FLOW_CFG (continued)
Register Name
Instances and
Offset within
Address
Register Group Spacing
INGR0_IP1_FLOW_MASK_LOWE 0x00000020
R
4.10.8.1
1
Description
Details
Lower portion of the IP flow
match mask register
Page 236
ETHERNET_COMPARATOR:INGR0_IP1_FLOW_CFG:INGR0_IP1_FLOW_ENA
Parent: ETHERNET_COMPARATOR:INGR0_IP1_FLOW_CFG
Instances: 1
Table 356 • Fields in INGR0_IP1_FLOW_ENA
Field Name
Access
Description
Default
INGR0_IP1_FLOW_MATCH_MOD 9:8
E
R/W
Match mode
0: Match on source address
1: Match on destination address
2: Match on either source or destination
address
3: Reserved
0x0
INGR0_IP1_CHANNEL_MASK
5:4
R/W
Channel mask
0x0: Flow invalid
0x1: Flow valid for channel 0
0x2: Flow valid for channel 1
0x3: Flow valid for both channels
0x3
INGR0_IP1_FLOW_ENA
0
R/W
Flow enable. If this comparator block is not
used, all flow enable bits must be set to 0.
0: Flow disabled
1: Flow enabled
0x0
4.10.8.2
Bit
ETHERNET_COMPARATOR:INGR0_IP1_FLOW_CFG:INGR0_IP1_FLOW_MAT
CH_UPPER
Parent: ETHERNET_COMPARATOR:INGR0_IP1_FLOW_CFG
Instances: 1
Table 357 • Fields in INGR0_IP1_FLOW_MATCH_UPPER
Field Name
Bit
INGR0_IP1_FLOW_MATCH_UPP 31:0
ER
4.10.8.3
Access
Description
Default
R/W
Match field for either the entire 32-bit
0x00000000
selected address for IPv4 or the upper 32 bits
of the selected address for IPv6
ETHERNET_COMPARATOR:INGR0_IP1_FLOW_CFG:INGR0_IP1_FLOW_MAT
CH_UPPER_MID
Parent: ETHERNET_COMPARATOR:INGR0_IP1_FLOW_CFG
Instances: 1
VMDS-10510 VSC8574-02 Datasheet Revision 4.2
234
Table 358 • Fields in INGR0_IP1_FLOW_MATCH_UPPER_MID
Field Name
Bit
INGR0_IP1_FLOW_MATCH_UPP 31:0
ER_MID
4.10.8.4
Access
Description
Default
R/W
Match bits for the upper middle 32 bits of the 0x00000000
IPv6 address
ETHERNET_COMPARATOR:INGR0_IP1_FLOW_CFG:INGR0_IP1_FLOW_MAT
CH_LOWER_MID
Parent: ETHERNET_COMPARATOR:INGR0_IP1_FLOW_CFG
Instances: 1
Table 359 • Fields in INGR0_IP1_FLOW_MATCH_LOWER_MID
Field Name
Bit
INGR0_IP1_FLOW_MATCH_LOW 31:0
ER_MID
4.10.8.5
Access
Description
Default
R/W
Match bits for the lower middle 32 bits of the 0x00000000
IPv6 address
ETHERNET_COMPARATOR:INGR0_IP1_FLOW_CFG:INGR0_IP1_FLOW_MAT
CH_LOWER
Parent: ETHERNET_COMPARATOR:INGR0_IP1_FLOW_CFG
Instances: 1
Table 360 • Fields in INGR0_IP1_FLOW_MATCH_LOWER
Field Name
Bit
INGR0_IP1_FLOW_MATCH_LOW 31:0
ER
4.10.8.6
Access
Description
Default
R/W
Match bits for the lower 32 bits of the IPv6
address
0x00000000
ETHERNET_COMPARATOR:INGR0_IP1_FLOW_CFG:INGR0_IP1_FLOW_MAS
K_UPPER
Parent: ETHERNET_COMPARATOR:INGR0_IP1_FLOW_CFG
Instances: 1
Table 361 • Fields in INGR0_IP1_FLOW_MASK_UPPER
Field Name
Bit
INGR0_IP1_FLOW_MASK_UPPE 31:0
R
4.10.8.7
Access
Description
Default
R/W
Address mask for the IP address
0x00000000
ETHERNET_COMPARATOR:INGR0_IP1_FLOW_CFG:INGR0_IP1_FLOW_MAS
K_UPPER_MID
Parent: ETHERNET_COMPARATOR:INGR0_IP1_FLOW_CFG
Instances: 1
VMDS-10510 VSC8574-02 Datasheet Revision 4.2
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Table 362 • Fields in INGR0_IP1_FLOW_MASK_UPPER_MID
Field Name
Bit
INGR0_IP1_FLOW_MASK_UPPE 31:0
R_MID
4.10.8.8
Access
Description
Default
R/W
These bits must be all 0 for IPv4 and any 32- 0x00000000
bit address match mode
ETHERNET_COMPARATOR:INGR0_IP1_FLOW_CFG:INGR0_IP1_FLOW_MAS
K_LOWER_MID
Parent: ETHERNET_COMPARATOR:INGR0_IP1_FLOW_CFG
Instances: 1
Table 363 • Fields in INGR0_IP1_FLOW_MASK_LOWER_MID
Field Name
Bit
INGR0_IP1_FLOW_MASK_LOWE 31:0
R_MID
4.10.8.9
Access
Description
Default
R/W
These bits must be all 0 for IPv4 and any 32- 0x00000000
bit address match mode
ETHERNET_COMPARATOR:INGR0_IP1_FLOW_CFG:INGR0_IP1_FLOW_MAS
K_LOWER
Parent: ETHERNET_COMPARATOR:INGR0_IP1_FLOW_CFG
Instances: 1
Table 364 • Fields in INGR0_IP1_FLOW_MASK_LOWER
Field Name
Bit
INGR0_IP1_FLOW_MASK_LOWE 31:0
R
4.10.9
Access
Description
Default
R/W
These bits must be all 0 for IPv4 and any 32- 0x00000000
bit address match mode
ETHERNET_COMPARATOR:INGR0_IP2_NXT_PROTOCOL
Parent: Egress0 Ethernet Comparator
Instances: 1
Table 365 • Registers in INGR0_IP2_NXT_PROTOCOL
Register Name
Instances and
Offset within
Address
Register Group Spacing
Description
Details
INGR0_IP2_NXT_COMPARATOR 0x00000000
1
IP next comparator control
register
Page 237
INGR0_IP2_MODE
0x00000004
1
IP comparator mode
Page 237
INGR0_IP2_PROT_MATCH_1
0x00000008
1
IP match register set 1
Page 238
INGR0_IP2_PROT_MATCH_2_UP 0x0000000C
PER
1
Upper portion of match
register 2
Page 238
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Table 365 • Registers in INGR0_IP2_NXT_PROTOCOL (continued)
Instances and
Offset within
Address
Register Group Spacing
Register Name
Description
Details
INGR0_IP2_PROT_MATCH_2_LO 0x00000010
WER
1
Lower portion of match
register 2
Page 238
INGR0_IP2_PROT_MASK_2_UPP 0x00000014
ER
1
Upper portion of match mask
register 2
Page 239
INGR0_IP2_PROT_MASK_2_LO
WER
0x00000018
1
Lower portion of match mask
register 2
Page 239
INGR0_IP2_PROT_OFFSET_2
0x0000001C
1
IP match offset register set 2
Page 239
INGR0_IP2_UDP_CHKSUM_CFG 0x00000020
1
IP/UDP checksum control
register
Page 239
4.10.9.1
ETHERNET_COMPARATOR:INGR0_IP2_NXT_PROTOCOL:INGR0_IP2_NXT_C
OMPARATOR
Parent: ETHERNET_COMPARATOR:INGR0_IP2_NXT_PROTOCOL
Instances: 1
Table 366 • Fields in INGR0_IP2_NXT_COMPARATOR
Field Name
Bit
Access
Description
INGR0_IP2_NXT_PROTOCOL
15:8
R/W
Number of bytes in this header, points to the 0x00
beginning of the next protocol.
R/W
Points to the next comparator stage. If this
0x0
comparator block is not used, this field must
be set to 0.
0: Comparator block not used
1: Reserved
2: Reserved
3: Reserved
4: Reserved
5: PTP/OAM comparator
6,7: Reserved
INGR0_IP2_NXT_COMPARATOR 2:0
4.10.9.2
Default
ETHERNET_COMPARATOR:INGR0_IP2_NXT_PROTOCOL:INGR0_IP2_MODE
Parent: ETHERNET_COMPARATOR:INGR0_IP2_NXT_PROTOCOL
Instances: 1
Table 367 • Fields in INGR0_IP2_MODE
Field Name
Bit
Access
Description
Default
INGR0_IP2_FLOW_OFFSET
12:8
R/W
Points to the source address field in the IP
frame. Use 12 for IPv4 and 8 for IPv6.
0x0C
VMDS-10510 VSC8574-02 Datasheet Revision 4.2
237
Table 367 • Fields in INGR0_IP2_MODE (continued)
Field Name
Bit
Access
Description
Default
INGR0_IP2_MODE
1:0
R/W
IP mode
0: IPv4
1: IPv6
2: Other protocol, 32-bit address match
3: Other protocol, 128-bit address match
0x0
4.10.9.3
ETHERNET_COMPARATOR:INGR0_IP2_NXT_PROTOCOL:INGR0_IP2_PROT_
MATCH_1
Parent: ETHERNET_COMPARATOR:INGR0_IP2_NXT_PROTOCOL
Instances: 1
Table 368 • Fields in INGR0_IP2_PROT_MATCH_1
Field Name
Bit
Access
Description
Default
INGR0_IP2_PROT_OFFSET_1
20:16
R/W
Points to the start of this match field relative
to the first byte of this protocol
0x00
INGR0_IP2_PROT_MASK_1
15:8
R/W
Mask field for IP_PROT_MATCH_1
0x00
INGR0_IP2_PROT_MATCH_1
7:0
R/W
8-bit match field
0x00
4.10.9.4
ETHERNET_COMPARATOR:INGR0_IP2_NXT_PROTOCOL:INGR0_IP2_PROT_
MATCH_2_UPPER
Parent: ETHERNET_COMPARATOR:INGR0_IP2_NXT_PROTOCOL
Instances: 1
Table 369 • Fields in INGR0_IP2_PROT_MATCH_2_UPPER
Field Name
Bit
INGR0_IP2_PROT_MATCH_2_UP 31:0
PER
4.10.9.5
Access
Description
Default
R/W
64-bit match register for advancing to the
next protocol, upper portion
0x00000000
ETHERNET_COMPARATOR:INGR0_IP2_NXT_PROTOCOL:INGR0_IP2_PROT_
MATCH_2_LOWER
Parent: ETHERNET_COMPARATOR:INGR0_IP2_NXT_PROTOCOL
Instances: 1
Table 370 • Fields in INGR0_IP2_PROT_MATCH_2_LOWER
Field Name
Bit
INGR0_IP2_PROT_MATCH_2_LO 31:0
WER
Access
Description
Default
R/W
64-bit match register for advancing to the
next protocol, lower portion
0x00000000
VMDS-10510 VSC8574-02 Datasheet Revision 4.2
238
4.10.9.6
ETHERNET_COMPARATOR:INGR0_IP2_NXT_PROTOCOL:INGR0_IP2_PROT_
MASK_2_UPPER
Parent: ETHERNET_COMPARATOR:INGR0_IP2_NXT_PROTOCOL
Instances: 1
Table 371 • Fields in INGR0_IP2_PROT_MASK_2_UPPER
Field Name
Bit
INGR0_IP2_PROT_MASK_2_UPP 31:0
ER
4.10.9.7
Access
Description
R/W
Default
0x00000000
ETHERNET_COMPARATOR:INGR0_IP2_NXT_PROTOCOL:INGR0_IP2_PROT_
MASK_2_LOWER
Parent: ETHERNET_COMPARATOR:INGR0_IP2_NXT_PROTOCOL
Instances: 1
Table 372 • Fields in INGR0_IP2_PROT_MASK_2_LOWER
Field Name
Bit
Access
INGR0_IP2_PROT_MASK_2_LO
WER
31:0
R/W
4.10.9.8
Description
Default
0x00000000
ETHERNET_COMPARATOR:INGR0_IP2_NXT_PROTOCOL:INGR0_IP2_PROT_
OFFSET_2
Parent: ETHERNET_COMPARATOR:INGR0_IP2_NXT_PROTOCOL
Instances: 1
Table 373 • Fields in INGR0_IP2_PROT_OFFSET_2
Field Name
Bit
Access
Description
INGR0_IP2_PROT_OFFSET_2
6:0
R/W
Points to the start of match field 2 relative to 0x00
the first byte of this protocol
4.10.9.9
Default
ETHERNET_COMPARATOR:INGR0_IP2_NXT_PROTOCOL:INGR0_IP2_UDP_C
HKSUM_CFG
Parent: ETHERNET_COMPARATOR:INGR0_IP2_NXT_PROTOCOL
Instances: 1
VMDS-10510 VSC8574-02 Datasheet Revision 4.2
239
Table 374 • Fields in INGR0_IP2_UDP_CHKSUM_CFG
Field Name
Bit
Access
Description
Default
INGR0_IP2_UDP_CHKSUM_OFF 15:8
SET
R/W
Pointer to the IP/UDP checksum field FOR
IPv4 frames or to the pad bytes of a
IPv6/UDP frame. For IPv4, it points to the
bytes that will be cleared. For IPv6, it points
to the bytes that will be updated to fix the
CRC.
0x00
INGR0_IP2_UDP_CHKSUM_WID 5:4
TH
R/W
Specifies the length of the checksum field in 0x2
bytes
INGR0_IP2_UDP_CHKSUM_UPD 1
ATE_ENA
R/W
0x0
This bit and
IP_UDP_CHKSUM_CLEAR_ENA CANNOT
be set together
1: Update the pad bytes at the end of the
frame
0: No pad byte field update
INGR0_IP2_UDP_CHKSUM_CLE 0
AR_ENA
R/W
This bit and
IP_UDP_CHKSUM_UPDATE_ENA
CANNOT be set together
1: Clear the UDP checksum field in an IPv4
frame
0: Do not clear the checksum
0x0
4.10.10 ETHERNET_COMPARATOR:INGR0_IP2_FLOW_CFG
Parent: Egress0 Ethernet Comparator
Instances: 8
Table 375 • Registers in INGR0_IP2_FLOW_CFG
Register Name
Instances and
Offset within
Address
Register Group Spacing
Description
Details
INGR0_IP2_FLOW_ENA
0x00000000
1
IP flow enable register
Page 241
INGR0_IP2_FLOW_MATCH_UPP 0x00000004
ER
1
Upper portion of the IP flow
match register
Page 241
INGR0_IP2_FLOW_MATCH_UPP 0x00000008
ER_MID
1
Upper mid portion of the IP
flow match register
Page 241
INGR0_IP2_FLOW_MATCH_LOW 0x0000000C
ER_MID
1
Lower mid portion of the IP
flow match register
Page 242
INGR0_IP2_FLOW_MATCH_LOW 0x00000010
ER
1
Lower portion of the IP flow
match register
Page 242
INGR0_IP2_FLOW_MASK_UPPE 0x00000014
R
1
Upper portion of the IP flow
match mask register
Page 242
INGR0_IP2_FLOW_MASK_UPPE 0x00000018
R_MID
1
Upper mid portion of the IP
flow match mask register
Page 243
INGR0_IP2_FLOW_MASK_LOWE 0x0000001C
R_MID
1
Lower mid portion of the IP
flow match mask register
Page 243
VMDS-10510 VSC8574-02 Datasheet Revision 4.2
240
Table 375 • Registers in INGR0_IP2_FLOW_CFG (continued)
Register Name
Instances and
Offset within
Address
Register Group Spacing
INGR0_IP2_FLOW_MASK_LOWE 0x00000020
R
1
Description
Details
Lower portion of the IP flow
match mask register
Page 243
4.10.10.1 ETHERNET_COMPARATOR:INGR0_IP2_FLOW_CFG:INGR0_IP2_FLOW_EN
A
Parent: ETHERNET_COMPARATOR:INGR0_IP2_FLOW_CFG
Instances: 1
Table 376 • Fields in INGR0_IP2_FLOW_ENA
Field Name
Bit
Access
Description
Default
INGR0_IP2_FLOW_MATCH_MOD 9:8
E
R/W
Match mode
0: Match on source address
1: Match on destination address
2: Match on either source or destination
address
3: Reserved
0x0
INGR0_IP2_CHANNEL_MASK
5:4
R/W
Channel mask
0x0: Flow invalid
0x1: Flow valid for channel 0
0x2: Flow valid for channel 1
0x3: Flow valid for both channels
0x3
INGR0_IP2_FLOW_ENA
0
R/W
Flow enable. If this comparator block is not
used, all flow enable bits must be set to 0.
0: Flow disabled
1: Flow enabled
0x0
4.10.10.2 ETHERNET_COMPARATOR:INGR0_IP2_FLOW_CFG:INGR0_IP2_FLOW_MA
TCH_UPPER
Parent: ETHERNET_COMPARATOR:INGR0_IP2_FLOW_CFG
Instances: 1
Table 377 • Fields in INGR0_IP2_FLOW_MATCH_UPPER
Field Name
Bit
INGR0_IP2_FLOW_MATCH_UPP 31:0
ER
Access
Description
R/W
Match field for either the entire 32-bit
0x00000000
selected address for IPv4 or the upper 32 bits
of the selected address for IPv6
Default
4.10.10.3 ETHERNET_COMPARATOR:INGR0_IP2_FLOW_CFG:INGR0_IP2_FLOW_MA
TCH_UPPER_MID
Parent: ETHERNET_COMPARATOR:INGR0_IP2_FLOW_CFG
Instances: 1
VMDS-10510 VSC8574-02 Datasheet Revision 4.2
241
Table 378 • Fields in INGR0_IP2_FLOW_MATCH_UPPER_MID
Field Name
Bit
INGR0_IP2_FLOW_MATCH_UPP 31:0
ER_MID
Access
Description
Default
R/W
Match bits for the upper middle 32 bits of the 0x00000000
IPv6 address
4.10.10.4 ETHERNET_COMPARATOR:INGR0_IP2_FLOW_CFG:INGR0_IP2_FLOW_MA
TCH_LOWER_MID
Parent: ETHERNET_COMPARATOR:INGR0_IP2_FLOW_CFG
Instances: 1
Table 379 • Fields in INGR0_IP2_FLOW_MATCH_LOWER_MID
Field Name
Bit
INGR0_IP2_FLOW_MATCH_LOW 31:0
ER_MID
Access
Description
Default
R/W
Match bits for the lower middle 32 bits of the 0x00000000
IPv6 address
4.10.10.5 ETHERNET_COMPARATOR:INGR0_IP2_FLOW_CFG:INGR0_IP2_FLOW_MA
TCH_LOWER
Parent: ETHERNET_COMPARATOR:INGR0_IP2_FLOW_CFG
Instances: 1
Table 380 • Fields in INGR0_IP2_FLOW_MATCH_LOWER
Field Name
Bit
INGR0_IP2_FLOW_MATCH_LOW 31:0
ER
Access
Description
Default
R/W
Match bits for the lower 32 bits of the IPv6
address
0x00000000
4.10.10.6 ETHERNET_COMPARATOR:INGR0_IP2_FLOW_CFG:INGR0_IP2_FLOW_MA
SK_UPPER
Parent: ETHERNET_COMPARATOR:INGR0_IP2_FLOW_CFG
Instances: 1
VMDS-10510 VSC8574-02 Datasheet Revision 4.2
242
Table 381 • Fields in INGR0_IP2_FLOW_MASK_UPPER
Field Name
Bit
INGR0_IP2_FLOW_MASK_UPPE 31:0
R
Access
Description
Default
R/W
Address mask for the IP address. It uses
0x00000000
CIDR format and specifies a number of
sequential bits to be used for matching, and a
number of sequential bits that are not
checked.
IP addresses specified in CIDR format look
like the following example:
192.0.0.5/24
In this example, the upper 24 bits are
significant and the lower 8 bits are not
checked.
This can be swapped by setting the
CIDR_DIRECTION register to 1 (normally it
is 0) so that in the above example, the upper
8 bits would not be checked and the lower 24
bits would be checked.
For IPv4 the allowable range is 1 - 32
For IPv6 the allowable range is 1 - 128
All other values are not defined
4.10.10.7 ETHERNET_COMPARATOR:INGR0_IP2_FLOW_CFG:INGR0_IP2_FLOW_MA
SK_UPPER_MID
Parent: ETHERNET_COMPARATOR:INGR0_IP2_FLOW_CFG
Instances: 1
Table 382 • Fields in INGR0_IP2_FLOW_MASK_UPPER_MID
Field Name
Bit
INGR0_IP2_FLOW_MASK_UPPE 31:0
R_MID
Access
Description
Default
R/W
These bits must be all 0 for IPv4 and any 32- 0x00000000
bit address match mode
4.10.10.8 ETHERNET_COMPARATOR:INGR0_IP2_FLOW_CFG:INGR0_IP2_FLOW_MA
SK_LOWER_MID
Parent: ETHERNET_COMPARATOR:INGR0_IP2_FLOW_CFG
Instances: 1
Table 383 • Fields in INGR0_IP2_FLOW_MASK_LOWER_MID
Field Name
Bit
INGR0_IP2_FLOW_MASK_LOWE 31:0
R_MID
Access
Description
Default
R/W
These bits must be all 0 for IPv4 and any 32- 0x00000000
bit address match mode
4.10.10.9 ETHERNET_COMPARATOR:INGR0_IP2_FLOW_CFG:INGR0_IP2_FLOW_MA
SK_LOWER
Parent: ETHERNET_COMPARATOR:INGR0_IP2_FLOW_CFG
VMDS-10510 VSC8574-02 Datasheet Revision 4.2
243
Instances: 1
Table 384 • Fields in INGR0_IP2_FLOW_MASK_LOWER
Field Name
Bit
INGR0_IP2_FLOW_MASK_LOWE 31:0
R
Access
Description
Default
R/W
These bits must be all 0 for IPv4 and any 32- 0x00000000
bit address match mode
4.10.11 ETHERNET_COMPARATOR:INGR0_PTP_FLOW
Parent: Egress0 Ethernet Comparator
Instances: 6
Table 385 • Registers in INGR0_PTP_FLOW
Register Name
Instances and
Offset within
Address
Register Group Spacing
Description
Details
INGR0_PTP_FLOW_ENA
0x00000000
1
PTP/OAM flow enable
Page 244
INGR0_PTP_FLOW_MATCH_UP
PER
0x00000004
1
Upper half of PTP/OAM flow
match field
Page 245
INGR0_PTP_FLOW_MATCH_LO
WER
0x00000008
1
Lower half of PTP/OAM flow
match field
Page 245
INGR0_PTP_FLOW_MASK_UPP
ER
0x0000000C
1
Upper half of PTP/OAM flow
match mask
Page 245
INGR0_PTP_FLOW_MASK_LOW 0x00000010
ER
1
Lower half of PTP/OAM flow
match mask
Page 245
INGR0_PTP_DOMAIN_RANGE
0x00000014
1
PTP/OAM range match
register
Page 246
INGR0_PTP_ACTION
0x00000018
1
PTP action control register
Page 246
INGR0_PTP_ACTION_2
0x0000001C
1
PTP action control register 2
Page 247
INGR0_PTP_ZERO_FIELD_CTL
0x00000020
1
Zero field control register
Page 247
4.10.11.1 ETHERNET_COMPARATOR:INGR0_PTP_FLOW:INGR0_PTP_FLOW_ENA
Parent: ETHERNET_COMPARATOR:INGR0_PTP_FLOW
Instances: 1
Table 386 • Fields in INGR0_PTP_FLOW_ENA
Field Name
Bit
Access
Description
Default
INGR0_PTP_CHANNEL_MASK
5:4
R/W
Channel mask
0x0: Flow invalid
0x1: Flow valid for channel 0
0x2: Flow valid for channel 1
0x3: Flow valid for both channels
0x3
INGR0_PTP_FLOW_ENA
0
R/W
Flow enable
0x0
VMDS-10510 VSC8574-02 Datasheet Revision 4.2
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4.10.11.2 ETHERNET_COMPARATOR:INGR0_PTP_FLOW:INGR0_PTP_FLOW_MATCH
_UPPER
Parent: ETHERNET_COMPARATOR:INGR0_PTP_FLOW
Instances: 1
Table 387 • Fields in INGR0_PTP_FLOW_MATCH_UPPER
Field Name
Bit
Access
Description
Default
INGR0_PTP_FLOW_MATCH_UP
PER
31:0
R/W
PTP flow match, upper 32 bit
0x00000000
4.10.11.3 ETHERNET_COMPARATOR:INGR0_PTP_FLOW:INGR0_PTP_FLOW_MATCH
_LOWER
Parent: ETHERNET_COMPARATOR:INGR0_PTP_FLOW
Instances: 1
Table 388 • Fields in INGR0_PTP_FLOW_MATCH_LOWER
Field Name
Bit
Access
Description
Default
INGR0_PTP_FLOW_MATCH_LO
WER
31:0
R/W
PTP flow match, lower 32 bit
0x00000000
4.10.11.4 ETHERNET_COMPARATOR:INGR0_PTP_FLOW:INGR0_PTP_FLOW_MASK_
UPPER
Parent: ETHERNET_COMPARATOR:INGR0_PTP_FLOW
Instances: 1
Table 389 • Fields in INGR0_PTP_FLOW_MASK_UPPER
Field Name
Bit
Access
Description
Default
INGR0_PTP_FLOW_MASK_UPP
ER
31:0
R/W
PTP flow mask, upper 32 bit
0x00000000
4.10.11.5 ETHERNET_COMPARATOR:INGR0_PTP_FLOW:INGR0_PTP_FLOW_MASK_
LOWER
Parent: ETHERNET_COMPARATOR:INGR0_PTP_FLOW
Instances: 1
Table 390 • Fields in INGR0_PTP_FLOW_MASK_LOWER
Field Name
Bit
INGR0_PTP_FLOW_MASK_LOW 31:0
ER
Access
Description
Default
R/W
PTP flow mask, lower 32 bit
0x00000000
VMDS-10510 VSC8574-02 Datasheet Revision 4.2
245
4.10.11.6 ETHERNET_COMPARATOR:INGR0_PTP_FLOW:INGR0_PTP_DOMAIN_RAN
GE
Parent: ETHERNET_COMPARATOR:INGR0_PTP_FLOW
Instances: 1
Table 391 • Fields in INGR0_PTP_DOMAIN_RANGE
Field Name
Bit
Access
Description
Default
INGR0_PTP_DOMAIN_RANGE_O 28:24
FFSET
R/W
PTP domain range offset
0x00
INGR0_PTP_DOMAIN_RANGE_U 23:16
PPER
R/W
Upper range of PTP domain field to match
0xFF
INGR0_PTP_DOMAIN_RANGE_L 15:8
OWER
R/W
Lower range of PTP domain field to match
0x00
INGR0_PTP_DOMAIN_RANGE_E 0
NA
R/W
Enable PTP domain range checking
0x0
4.10.11.7 ETHERNET_COMPARATOR:INGR0_PTP_FLOW:INGR0_PTP_ACTION
Parent: ETHERNET_COMPARATOR:INGR0_PTP_FLOW
Instances: 1
Table 392 • Fields in INGR0_PTP_ACTION
Field Name
Bit
Access
Description
Default
INGR0_PTP_MOD_FRAME_STAT 28
_UPDATE
R/W
Modified frame status update
0: Do not signal the rewriter to update the
value of the Modified Frame Status bit
1: Signal the rewriter to update the value of
the Modified Frame Status bit
0x0
INGR0_PTP_MOD_FRAME_BYT
E_OFFSET
R/W
Indicates the position relative to the start of
the PTP frame in bytes where the Modified
Frame Status bit resides
0x0
INGR0_PTP_SUB_DELAY_ASYM 21
_ENA
R/W
Enable subtract delay asymmetry signal
0x0
0: Do not signal the timestamp block to
subtract the asymmetry delay
1: Signal the timestamp block to subtract the
asymmetry delay
INGR0_PTP_ADD_DELAY_ASYM 20
_ENA
R/W
Enable add delay asymmetry signal
0: Do not signal the timestamp block to add
the asymmetry delay
1: Signal the timestamp block to add the
asymmetry delay
0x0
INGR0_PTP_TIME_STRG_FIELD 15:10
_OFFSET
R/W
Time storage field offset
The location in a PTP frame where a time
value can be stored or read
0x00
26:24
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Table 392 • Fields in INGR0_PTP_ACTION (continued)
Field Name
Bit
Access
Description
Default
INGR0_PTP_CORR_FIELD_OFF
SET
9:5
R/W
Points to the location of the correction field
for updating the timestamp. Location is
relative to the first byte of the PTP/OAM
header.
Note: If this flow is being used to
match OAM frames, set this
register to 4.
0x00
INGR0_PTP_SAVE_LOCAL_TIME 4
R/W
Enable saving time
0x0
0: Do not save the time to the timestamp
FIFO
1: Save the local time to the timestamp FIFO
INGR0_PTP_COMMAND
R/W
PTP action command
0: NOP
1: SUB
2: SUB_P2P
3: ADD
4: SUB_ADD
5: WRITE_1588
6: WRITE_P2P (deprecated)
7: WRITE_NS
8: WRITE_NS_P2P
3:0
0x0
4.10.11.8 ETHERNET_COMPARATOR:INGR0_PTP_FLOW:INGR0_PTP_ACTION_2
Parent: ETHERNET_COMPARATOR:INGR0_PTP_FLOW
Instances: 1
Table 393 • Fields in INGR0_PTP_ACTION_2
Field Name
Bit
Access
Description
INGR0_PTP_NEW_CF_LOC
23:16
R/W
Location of the new correction field relative to 0x00
the PTP header start. Only even values are
allowed.
INGR0_PTP_REWRITE_OFFSET 15:8
R/W
Points to where in the frame relative to the
SFD that the timestamp should be updated
0x00
INGR0_PTP_REWRITE_BYTES
R/W
Number of bytes in the PTP or OAM frame
that must be modified by the rewriter for the
timestamp
0x0
3:0
Default
4.10.11.9 ETHERNET_COMPARATOR:INGR0_PTP_FLOW:INGR0_PTP_ZERO_FIELD_
CTL
Parent: ETHERNET_COMPARATOR:INGR0_PTP_FLOW
Instances: 1
VMDS-10510 VSC8574-02 Datasheet Revision 4.2
247
Table 394 • Fields in INGR0_PTP_ZERO_FIELD_CTL
Field Name
Bit
Access
Description
Default
INGR0_PTP_ZERO_FIELD_OFFS 13:8
ET
R/W
Points to a location in the PTP/OAM frame
0x00
relative to the start of the PTP header that will
be zeroed if this function is enabled
INGR0_PTP_ZERO_FIELD_BYTE 3:0
_CNT
R/W
The number of bytes to be zeroed. If this field 0x0
is 0, then this function is not enabled.
4.10.12 ETHERNET_COMPARATOR:INGR0_PTP_IP_CHKSUM_CTL
Parent: Egress0 Ethernet Comparator
Instances: 1
Table 395 • Registers in INGR0_PTP_IP_CHKSUM_CTL
Register Name
Instances and
Offset within
Address
Register Group Spacing
Description
Details
INGR0_PTP_IP_CKSUM_SEL
0x00000000
IP checksum block select
Page 248
1
4.10.12.1 ETHERNET_COMPARATOR:INGR0_PTP_IP_CHKSUM_CTL:INGR0_PTP_IP_
CKSUM_SEL
Parent: ETHERNET_COMPARATOR:INGR0_PTP_IP_CHKSUM_CTL
Instances: 1
Table 396 • Fields in INGR0_PTP_IP_CKSUM_SEL
Field Name
Bit
Access
Description
Default
INGR0_PTP_IP_CHKSUM_SEL
0
R/W
IP checksum controls selection
0: Use the IP checksum controls from IP
comparator 1
1: Use the IP checksum controls from IP
comparator 2
0x0
4.11
Egress1 Ethernet Comparator
Table 397 • Register Groups in Egress1 Ethernet Comparator
Register Group Name
Offset within
Target
Instances and
Address
Spacing
EGR1_ETH1_NXT_PROTOCOL
0x00000000
EGR1_ETH1_FLOW_CFG
0x00000040
Description
Details
1
Ethernet next protocol
configuration
Page 249
8
0x00000040
Ethernet flow configuration
Page 251
VMDS-10510 VSC8574-02 Datasheet Revision 4.2
248
Table 397 • Register Groups in Egress1 Ethernet Comparator (continued)
Register Group Name
Offset within
Target
Instances and
Address
Spacing
EGR1_ETH2_NXT_PROTOCOL
0x00000240
EGR1_ETH2_FLOW_CFG
0x00000280
Description
Details
1
Ethernet next protocol
configuration
Page 254
8
0x00000040
Ethernet flow configuration
Page 256
EGR1_MPLS_NXT_COMPARATO 0x00000480
R
1
MPLS next protocol register
Page 259
EGR1_MPLS_FLOW_CFG
0x000004C0
8
0x00000040
MPLS flow configuration
Page 260
EGR1_IP1_NXT_PROTOCOL
0x000006C0
1
IP1 next protocol
Page 263
EGR1_IP1_FLOW_CFG
0x00000700
8
0x00000040
IP1 flow configuration
Page 267
EGR1_IP2_NXT_PROTOCOL
0x00000900
1
IP2 next protocol
Page 270
EGR1_IP2_FLOW_CFG
0x00000940
8
0x00000040
IP2 flow configuration
Page 274
EGR1_PTP_FLOW
0x00000B40
6
0x00000040
PTP flow configuration
Page 277
EGR1_PTP_IP_CHKSUM_CTL
0x00000CC0
1
IP checksum field control
Page 281
EGR1_FRAME_SIG_CFG
0x00000CC4
1
Frame signature builder
configuration
Page 282
4.11.1
ETHERNET_COMPARATOR:EGR1_ETH1_NXT_PROTOCOL
Parent: Egress0 Ethernet Comparator
Instances: 1
Table 398 • Registers in EGR1_ETH1_NXT_PROTOCOL
Register Name
Instances and
Offset within
Address
Register Group Spacing
Description
EGR1_ETH1_NXT_PROTOCOL
0x00000000
1
Ethernet next protocol register Page 249
EGR1_ETH1_VLAN_TPID_CFG
0x00000004
1
VLAN TPID configuration
Page 250
EGR1_ETH1_TAG_MODE
0x00000008
1
Ethernet tag mode
Page 250
EGR1_ETH1_ETYPE_MATCH
0x0000000C
1
Ethertype match register
Page 250
4.11.1.1
Details
ETHERNET_COMPARATOR:EGR1_ETH1_NXT_PROTOCOL:EGR1_ETH1_NXT
_PROTOCOL
Parent: ETHERNET_COMPARATOR:EGR1_ETH1_NXT_PROTOCOL
Instances: 1
VMDS-10510 VSC8574-02 Datasheet Revision 4.2
249
Table 399 • Fields in EGR1_ETH1_NXT_PROTOCOL
Field Name
Access
Description
EGR1_ETH1_FRAME_SIG_OFFS 20:16
ET
R/W
Frame signature offset. Points to the start of 0x00
the byte field in the Ethernet frame that will
be used for the frame signature.
EGR1_ETH1_NXT_COMPARATO 2:0
R
R/W
Points to the next comparator block after this 0x0
Ethernet block
0: Reserved
1: Ethernet comparator 2
2: IP/UDP/ACH comparator 1
3: IP/UDP/ACH comparator 2
4: MPLS comparator
5: PTP/OAM comparator
6,7: Reserved
4.11.1.2
Bit
Default
ETHERNET_COMPARATOR:EGR1_ETH1_NXT_PROTOCOL:EGR1_ETH1_VLA
N_TPID_CFG
Parent: ETHERNET_COMPARATOR:EGR1_ETH1_NXT_PROTOCOL
Instances: 1
Table 400 • Fields in EGR1_ETH1_VLAN_TPID_CFG
Field Name
Bit
Access
Description
Default
EGR1_ETH1_VLAN_TPID_CFG
31:16
R/W
Configurable VLAN TPID (S or B-tag)
0x88A8
4.11.1.3
ETHERNET_COMPARATOR:EGR1_ETH1_NXT_PROTOCOL:EGR1_ETH1_TA
G_MODE
Parent: ETHERNET_COMPARATOR:EGR1_ETH1_NXT_PROTOCOL
Instances: 1
Table 401 • Fields in EGR1_ETH1_TAG_MODE
Field Name
Bit
Access
Description
EGR1_ETH1_PBB_ENA
0
R/W
This bit enables the presence of PBB.
0x0
The I-tag match bits are programmed in the
ETH1_VLAN_TAG_RANGE registers. The
mask bits are programmed in the
ETH1_VLAN_TAG2 registers. A B-tag if
present is configured in the
ETH1_VLAN_TAG1 registers.
0: PBB not enabled
1: Always expect PBB, last tag is always an Itag
4.11.1.4
Default
ETHERNET_COMPARATOR:EGR1_ETH1_NXT_PROTOCOL:EGR1_ETH1_ETY
PE_MATCH
Parent: ETHERNET_COMPARATOR:EGR1_ETH1_NXT_PROTOCOL
VMDS-10510 VSC8574-02 Datasheet Revision 4.2
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Instances: 1
Table 402 • Fields in EGR1_ETH1_ETYPE_MATCH
Field Name
Bit
Access
Description
EGR1_ETH1_ETYPE_MATCH
15:0
R/W
If the Ethertype/length field is an Ethertype, 0x0000
then this register is compared against the
value. If the field is a length, the length value
is not checked.
4.11.2
Default
ETHERNET_COMPARATOR:EGR1_ETH1_FLOW_CFG
Parent: Egress0 Ethernet Comparator
Instances: 8
Table 403 • Registers in EGR1_ETH1_FLOW_CFG
Register Name
Instances and
Address
Offset within
Register Group Spacing
Description
Details
EGR1_ETH1_FLOW_ENABLE
0x00000000
1
Ethernet flow enable
Page 251
EGR1_ETH1_MATCH_MODE
0x00000004
1
Ethernet protocol match mode Page 252
EGR1_ETH1_ADDR_MATCH_1
0x00000008
1
Ethernet address match part 1 Page 253
EGR1_ETH1_ADDR_MATCH_2
0x0000000C
1
Ethernet address match part 2 Page 253
EGR1_ETH1_VLAN_TAG_RANG
E_I_TAG
0x00000010
1
Ethernet VLAN tag range
match register
Page 253
EGR1_ETH1_VLAN_TAG1
0x00000014
1
VLAN tag 1 match/mask
Page 254
EGR1_ETH1_VLAN_TAG2_I_TAG 0x00000018
1
Match/mask for VLAN tag 2 or Page 254
I-tag match
4.11.2.1
ETHERNET_COMPARATOR:EGR1_ETH1_FLOW_CFG:EGR1_ETH1_FLOW_E
NABLE
Parent: ETHERNET_COMPARATOR:EGR1_ETH1_FLOW_CFG
Instances: 1
Table 404 • Fields in EGR1_ETH1_FLOW_ENABLE
Field Name
Bit
Access
Description
Default
EGR1_ETH1_CHANNEL_MASK
9:8
R/W
Channel mask
0x0: Flow invalid
0x1: Flow valid for channel 0
0x2: Flow valid for channel 1
0x3: Flow valid for both channels
0x3
EGR1_ETH1_FLOW_ENABLE
0
R/W
Flow enable
0: Flow disabled
1: Flow enabled
0x0
VMDS-10510 VSC8574-02 Datasheet Revision 4.2
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4.11.2.2
ETHERNET_COMPARATOR:EGR1_ETH1_FLOW_CFG:EGR1_ETH1_MATCH_
MODE
Parent: ETHERNET_COMPARATOR:EGR1_ETH1_FLOW_CFG
Instances: 1
Table 405 • Fields in EGR1_ETH1_MATCH_MODE
Field Name
Bit
Access
Description
Default
EGR1_ETH1_VLAN_TAG_MODE 13:12
R/W
VLAN tag mode configuration
0: VLAN range checking disabled
1: VLAN range checking on tag 1
2: VLAN range checking on tag 2 (not
supported with PBB)
3: Reserved
0x0
EGR1_ETH1_VLAN_TAG2_TYPE 9
R/W
VLAN tag2 type
This register is only used if
ETH1_VLAN_VERIFY_ENA = 1
If PBB not enabled:
0: C tag (TPID of 0x8100)
1: S tag (match to CONF_VLAN_TPID)
If PBB enabled:
0,1: I tag (use range registers)
0x1
EGR1_ETH1_VLAN_TAG1_TYPE 8
R/W
VLAN tag1 type
0x0
This register is only used if
ETH1_VLAN_VERIFY_ENA = 1
0: C tag (TPID of 0x8100)
1: S or B tag (match to CONF_VLAN_TPID)
EGR1_ETH1_VLAN_TAGS
R/W
VLAN tags
0x0
This register is only used if
ETH1_VLAN_VERIFY_ENA = 1
0: No VLAN tags (not valid for PBB)
1: 1 VLAN tag (for PBB this would be the Itag)
2: 2 VLAN tags (for PBB expect a B-tag and
an I-tag)
3: Reserved
EGR1_ETH1_VLAN_VERIFY_EN 4
A
R/W
Verify VLAN tags
0x0
0: Parse for VLAN tags, do not check values.
For PBB the I-tag is always checked.
1: Verify configured VLAN tag configuration.
EGR1_ETH1_ETHERTYPE_MOD 0
E
R/W
VLAN tag verification configuration
0x0
When checking for presence of SNAP/LLC
based upon ETH1_MATCH_MODE, this field
indicates if SNAP and 3-byte LLC is expected
to be present.
0: Only Ethernet type II supported, no
SNAP/LLC
1: Ethernet type II and Ethernet type I with
SNAP/LLC, determine if SNAP/LLC is
present or not. Type I always assumes that
SNAP/LLC is present.
7:6
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4.11.2.3
ETHERNET_COMPARATOR:EGR1_ETH1_FLOW_CFG:EGR1_ETH1_ADDR_M
ATCH_1
Parent: ETHERNET_COMPARATOR:EGR1_ETH1_FLOW_CFG
Instances: 1
Table 406 • Fields in EGR1_ETH1_ADDR_MATCH_1
Field Name
Bit
Access
Description
Default
EGR1_ETH1_ADDR_MATCH_1
31:0
R/W
First 32 bits of the address match value
0x00000000
4.11.2.4
ETHERNET_COMPARATOR:EGR1_ETH1_FLOW_CFG:EGR1_ETH1_ADDR_M
ATCH_2
Parent: ETHERNET_COMPARATOR:EGR1_ETH1_FLOW_CFG
Instances: 1
Table 407 • Fields in EGR1_ETH1_ADDR_MATCH_2
Field Name
Access
Description
EGR1_ETH1_ADDR_MATCH_MO 22:20
DE
R/W
Selects how the addresses are matched.
0x1
One-hot encoded. Multiple bits can be set at
once
0: Full 48-bit address match
1: Match any unicast address
2: Match any muliticast address
EGR1_ETH1_ADDR_MATCH_SE 17:16
LECT
R/W
Selects which address to match
0: Match the destination address
1: Match the source address
2: Match either the source of destination
address
3: Reserved
0x0
EGR1_ETH1_ADDR_MATCH_2
R/W
Last 16 bits of the Ethernet address match
field
0x0000
4.11.2.5
Bit
15:0
Default
ETHERNET_COMPARATOR:EGR1_ETH1_FLOW_CFG:EGR1_ETH1_VLAN_TA
G_RANGE_I_TAG
Parent: ETHERNET_COMPARATOR:EGR1_ETH1_FLOW_CFG
Instances: 1
Table 408 • Fields in EGR1_ETH1_VLAN_TAG_RANGE_I_TAG
Field Name
Bit
Access
Description
EGR1_ETH1_VLAN_TAG_RANG
E_UPPER
27:16
R/W
If PBB mode is not enabled, then this register 0xFFF
contains the upper range of the VLAN tag
range match.
If PBB mode is enabled, then this register
contains the upper 12 bits of the I-tag.
VMDS-10510 VSC8574-02 Datasheet Revision 4.2
Default
253
Table 408 • Fields in EGR1_ETH1_VLAN_TAG_RANGE_I_TAG (continued)
Field Name
Bit
Access
Description
EGR1_ETH1_VLAN_TAG_RANG
E_LOWER
11:0
R/W
If PBB mode is not enabled, then this register 0x000
contains the lower range of the VLAN tag
range match.
If PBB mode is enabled, then this register
contains the lower 12 bits of the I-tag.
4.11.2.6
Default
ETHERNET_COMPARATOR:EGR1_ETH1_FLOW_CFG:EGR1_ETH1_VLAN_TA
G1
Parent: ETHERNET_COMPARATOR:EGR1_ETH1_FLOW_CFG
Instances: 1
Table 409 • Fields in EGR1_ETH1_VLAN_TAG1
Field Name
Access
Description
Default
EGR1_ETH1_VLAN_TAG1_MASK 27:16
R/W
Mask value for VLAN tag 1
0xFFF
EGR1_ETH1_VLAN_TAG1_MATC 11:0
H
R/W
Match value for the first VLAN tag
0x000
4.11.2.7
Bit
ETHERNET_COMPARATOR:EGR1_ETH1_FLOW_CFG:EGR1_ETH1_VLAN_TA
G2_I_TAG
Parent: ETHERNET_COMPARATOR:EGR1_ETH1_FLOW_CFG
Instances: 1
Table 410 • Fields in EGR1_ETH1_VLAN_TAG2_I_TAG
Field Name
Access
Description
EGR1_ETH1_VLAN_TAG2_MASK 27:16
R/W
When PBB is not enabled, the mask field for 0xFFF
VLAN tag 2.
When PBB is enabled, the upper 12 bits of
the I-tag mask.
EGR1_ETH1_VLAN_TAG2_MATC 11:0
H
R/W
When PBB is not enabled, the match field for 0x000
VLAN Tag 2.
When PBB is enabled, the lower 12 bits of
the I-tag mask field.
4.11.3
Bit
Default
ETHERNET_COMPARATOR:EGR1_ETH2_NXT_PROTOCOL
Parent: Egress0 Ethernet Comparator
Instances: 1
VMDS-10510 VSC8574-02 Datasheet Revision 4.2
254
Table 411 • Registers in EGR1_ETH2_NXT_PROTOCOL
Register Name
Instances and
Offset within
Address
Register Group Spacing
Description
EGR1_ETH2_NXT_PROTOCOL
0x00000000
1
Ethernet next protocol register Page 255
EGR1_ETH2_VLAN_TPID_CFG
0x00000004
1
VLAN TPID configuration
Page 255
EGR1_ETH2_ETYPE_MATCH
0x00000008
1
Ethertype match register
Page 255
4.11.3.1
Details
ETHERNET_COMPARATOR:EGR1_ETH2_NXT_PROTOCOL:EGR1_ETH2_NXT
_PROTOCOL
Parent: ETHERNET_COMPARATOR:EGR1_ETH2_NXT_PROTOCOL
Instances: 1
Table 412 • Fields in EGR1_ETH2_NXT_PROTOCOL
Field Name
Access
Description
EGR1_ETH2_FRAME_SIG_OFFS 20:16
ET
R/W
Frame signature offset. Points to the start of 0x00
the byte field in the Ethernet frame that will
be used for the frame signature.
EGR1_ETH2_NXT_COMPARATO 2:0
R
R/W
Points to the next comparator block after this 0x0
Ethernet block. If this comparator block is not
used, this field must be set to 0.
0: Comparator block not used
1: Ethernet comparator 2
2: IP/UDP/ACH comparator 1
3: IP/UDP/ACH comparator 2
4: MPLS comparator
5: PTP/OAM comparator
6,7: Reserved
4.11.3.2
Bit
Default
ETHERNET_COMPARATOR:EGR1_ETH2_NXT_PROTOCOL:EGR1_ETH2_VLA
N_TPID_CFG
Parent: ETHERNET_COMPARATOR:EGR1_ETH2_NXT_PROTOCOL
Instances: 1
Table 413 • Fields in EGR1_ETH2_VLAN_TPID_CFG
Field Name
Bit
Access
Description
Default
EGR1_ETH2_VLAN_TPID_CFG
31:16
R/W
Configurable S-tag TPID
0x88A8
4.11.3.3
ETHERNET_COMPARATOR:EGR1_ETH2_NXT_PROTOCOL:EGR1_ETH2_ETY
PE_MATCH
Parent: ETHERNET_COMPARATOR:EGR1_ETH2_NXT_PROTOCOL
Instances: 1
VMDS-10510 VSC8574-02 Datasheet Revision 4.2
255
Table 414 • Fields in EGR1_ETH2_ETYPE_MATCH
Field Name
Bit
Access
Description
EGR1_ETH2_ETYPE_MATCH
15:0
R/W
If the Ethertype/length field is an Ethertype, 0x0000
then this register is compared against the
value. If the field is a length, the length value
is not checked.
4.11.4
Default
ETHERNET_COMPARATOR:EGR1_ETH2_FLOW_CFG
Parent: Egress0 Ethernet Comparator
Instances: 8
Table 415 • Registers in EGR1_ETH2_FLOW_CFG
Instances and
Offset within
Address
Register Group Spacing
Register Name
Description
Details
Page 256
EGR1_ETH2_FLOW_ENABLE
0x00000000
1
Ethernet flow enable
EGR1_ETH2_MATCH_MODE
0x00000004
1
Ethernet protocol match mode Page 257
EGR1_ETH2_ADDR_MATCH_1
0x00000008
1
Ethernet address match part 1 Page 257
EGR1_ETH2_ADDR_MATCH_2
0x0000000C
1
Ethernet address match part 2 Page 258
EGR1_ETH2_VLAN_TAG_RANG
E_I_TAG
0x00000010
1
Ethernet VLAN tag range
match register
Page 258
EGR1_ETH2_VLAN_TAG1
0x00000014
1
VLAN tag 1 match/mask
Page 258
EGR1_ETH2_VLAN_TAG2_I_TAG 0x00000018
1
Match/mask for VLAN tag 2 or Page 259
I-tag match
4.11.4.1
ETHERNET_COMPARATOR:EGR1_ETH2_FLOW_CFG:EGR1_ETH2_FLOW_E
NABLE
Parent: ETHERNET_COMPARATOR:EGR1_ETH2_FLOW_CFG
Instances: 1
Table 416 • Fields in EGR1_ETH2_FLOW_ENABLE
Field Name
Bit
Access
Description
Default
EGR1_ETH2_CHANNEL_MASK
9:8
R/W
Channel mask
0x0: Flow invalid
0x1: Flow valid for channel 0
0x2: Flow valid for channel 1
0x3: Flow valid for both channels
0x3
EGR1_ETH2_FLOW_ENABLE
0
R/W
Flow enable.
If this comparator block is not used, all flow
enable bits must be set to 0.
0: Flow disabled
1: Flow enabled
0x0
VMDS-10510 VSC8574-02 Datasheet Revision 4.2
256
4.11.4.2
ETHERNET_COMPARATOR:EGR1_ETH2_FLOW_CFG:EGR1_ETH2_MATCH_
MODE
Parent: ETHERNET_COMPARATOR:EGR1_ETH2_FLOW_CFG
Instances: 1
Table 417 • Fields in EGR1_ETH2_MATCH_MODE
Field Name
Access
Description
Default
EGR1_ETH2_VLAN_TAG_MODE 13:12
R/W
VLAN tag mode configuration
0: VLAN range checking disabled
1: VLAN range checking on tag 1
2: VLAN range checking on tag 2 (not
supported with PBB)
3: Reserved
0x0
EGR1_ETH2_VLAN_TAG2_TYPE 9
R/W
VLAN tag2 type
This register is only used if
ETH1_VLAN_VERIFY_ENA = 1
0: C tag (TPID of 0x8100)
1: S tag (match to CONF_VLAN_TPID)
0x1
EGR1_ETH2_VLAN_TAG1_TYPE 8
R/W
VLAN tag1 type
0x0
This register is only used if
ETH1_VLAN_VERIFY_ENA = 1
0: C tag (TPID of 0x8100)
1: S or B tag (match to CONF_VLAN_TPID)
EGR1_ETH2_VLAN_TAGS
R/W
VLAN tags
This register is only used if
ETH2_VLAN_VERIFY_ENA = 1
0: No VLAN tags
1: 1 VLAN tag
2: 2 VLAN tags
3: Reserved
EGR1_ETH2_VLAN_VERIFY_EN 4
A
R/W
0x0
Verify VLAN tags
0: Parse for VLAN tags, do not check values.
1: Verify configured VLAN tag configuration.
EGR1_ETH2_ETHERTYPE_MOD 0
E
R/W
VLAN tag verification configuration
0x0
When checking for presence of SNAP/LLC
based upon ETH1_MATCH_MODE, this field
indicates if SNAP and 3-byte LLC is expected
to be present.
0: Only Ethernet type II supported, no
SNAP/LLC
1: Ethernet type II and Ethernet type I with
SNAP/LLC, determine if SNAP/LLC is
present or not. Type I always assumes that
SNAP/LLC is present.
4.11.4.3
Bit
7:6
0x0
ETHERNET_COMPARATOR:EGR1_ETH2_FLOW_CFG:EGR1_ETH2_ADDR_M
ATCH_1
Parent: ETHERNET_COMPARATOR:EGR1_ETH2_FLOW_CFG
Instances: 1
VMDS-10510 VSC8574-02 Datasheet Revision 4.2
257
Table 418 • Fields in EGR1_ETH2_ADDR_MATCH_1
Field Name
Bit
Access
Description
Default
EGR1_ETH2_ADDR_MATCH_1
31:0
R/W
First 32 bits of the address match value
0x00000000
4.11.4.4
ETHERNET_COMPARATOR:EGR1_ETH2_FLOW_CFG:EGR1_ETH2_ADDR_M
ATCH_2
Parent: ETHERNET_COMPARATOR:EGR1_ETH2_FLOW_CFG
Instances: 1
Table 419 • Fields in EGR1_ETH2_ADDR_MATCH_2
Field Name
Access
Description
EGR1_ETH2_ADDR_MATCH_MO 22:20
DE
R/W
Selects how the addresses are matched.
0x1
One-hot encoded. Multiple bits can be set at
once.
0: Full 48-bit address match
1: Match any unicast address
2: Match any muliticast address
EGR1_ETH2_ADDR_MATCH_SE 17:16
LECT
R/W
Selects which address to match
0: Match the destination address
1: Match the source address
2: Match either the source of destination
address
3: Reserved
0x0
EGR1_ETH2_ADDR_MATCH_2
R/W
Last 16 bits of the Ethernet address match
field
0x0000
4.11.4.5
Bit
15:0
Default
ETHERNET_COMPARATOR:EGR1_ETH2_FLOW_CFG:EGR1_ETH2_VLAN_TA
G_RANGE_I_TAG
Parent: ETHERNET_COMPARATOR:EGR1_ETH2_FLOW_CFG
Instances: 1
Table 420 • Fields in EGR1_ETH2_VLAN_TAG_RANGE_I_TAG
Field Name
Bit
Access
Description
Default
EGR1_ETH2_VLAN_TAG_RANG
E_UPPER
27:16
R/W
Contains the upper range of the VLAN tag
range match
0xFFF
EGR1_ETH2_VLAN_TAG_RANG
E_LOWER
11:0
R/W
Contains the lower range of the VLAN tag
range match
0x000
4.11.4.6
ETHERNET_COMPARATOR:EGR1_ETH2_FLOW_CFG:EGR1_ETH2_VLAN_TA
G1
Parent: ETHERNET_COMPARATOR:EGR1_ETH2_FLOW_CFG
Instances: 1
VMDS-10510 VSC8574-02 Datasheet Revision 4.2
258
Table 421 • Fields in EGR1_ETH2_VLAN_TAG1
Field Name
Access
Description
Default
EGR1_ETH2_VLAN_TAG1_MASK 27:16
R/W
Mask value for VLAN tag 1
0xFFF
EGR1_ETH2_VLAN_TAG1_MATC 11:0
H
R/W
Match value for the first VLAN tag
0x000
4.11.4.7
Bit
ETHERNET_COMPARATOR:EGR1_ETH2_FLOW_CFG:EGR1_ETH2_VLAN_TA
G2_I_TAG
Parent: ETHERNET_COMPARATOR:EGR1_ETH2_FLOW_CFG
Instances: 1
Table 422 • Fields in EGR1_ETH2_VLAN_TAG2_I_TAG
Field Name
Access
Description
Default
EGR1_ETH2_VLAN_TAG2_MASK 27:16
R/W
Mask field for VLAN tag 2
0xFFF
EGR1_ETH2_VLAN_TAG2_MATC 11:0
H
R/W
Match field for VLAN Tag 2
0x000
4.11.5
Bit
ETHERNET_COMPARATOR:EGR1_MPLS_NXT_COMPARATOR
Parent: Egress0 Ethernet Comparator
Instances: 1
Table 423 • Registers in EGR1_MPLS_NXT_COMPARATOR
Register Name
Instances and
Offset within
Address
Register Group Spacing
EGR1_MPLS_NXT_COMPARATO 0x00000000
R
4.11.5.1
1
Description
Details
MPLS next protocol
comparator register
Page 259
ETHERNET_COMPARATOR:EGR1_MPLS_NXT_COMPARATOR:EGR1_MPLS_
NXT_COMPARATOR
Parent: ETHERNET_COMPARATOR:EGR1_MPLS_NXT_COMPARATOR
Instances: 1
Table 424 • Fields in EGR1_MPLS_NXT_COMPARATOR
Field Name
Bit
Access
Description
EGR1_MPLS_CTL_WORD
16
R/W
Indicates the presence of a control word after 0x0
the last label. The first 4 bits of the control
word are always 0.
0: No control word after the last label
1: Control word after the last label
VMDS-10510 VSC8574-02 Datasheet Revision 4.2
Default
259
Table 424 • Fields in EGR1_MPLS_NXT_COMPARATOR (continued)
Field Name
Bit
EGR1_MPLS_NXT_COMPARATO 2:0
R
4.11.6
Access
Description
Default
R/W
Points to the next comparator stage. If this
0x0
comparator block is not used, this field must
be set to 0.
0: Comparator block not used.
1: Ethernet comparator 2
2: IP/UDP/ACH comparator 1
3: IP/UDP/ACH comparator 2
4: Reserved
5: PTP/OAM comparator
6,7: Reserved
ETHERNET_COMPARATOR:EGR1_MPLS_FLOW_CFG
Parent: Egress0 Ethernet Comparator
Instances: 8
Table 425 • Registers in EGR1_MPLS_FLOW_CFG
Register Name
Instances and
Offset within
Address
Register Group Spacing
Description
Details
EGR1_MPLS_FLOW_CONTROL
0x00000000
1
MPLS flow control register
Page 260
EGR1_MPLS_LABEL_RANGE_L
OWER_0
0x00000008
1
MPLS label 0 match range
lower value
Page 261
EGR1_MPLS_LABEL_RANGE_U 0x0000000C
PPER_0
1
MPLS label 0 match range
upper value
Page 261
EGR1_MPLS_LABEL_RANGE_L
OWER_1
0x00000010
1
MPLS label 1 match range
lower value
Page 262
EGR1_MPLS_LABEL_RANGE_U 0x00000014
PPER_1
1
MPLS label 1 match range
upper value
Page 262
EGR1_MPLS_LABEL_RANGE_L
OWER_2
0x00000018
1
MPLS label 2 match range
lower value
Page 262
EGR1_MPLS_LABEL_RANGE_U 0x0000001C
PPER_2
1
MPLS label 2 match range
upper value
Page 262
EGR1_MPLS_LABEL_RANGE_L
OWER_3
0x00000020
1
MPLS label 3 match range
lower value
Page 263
EGR1_MPLS_LABEL_RANGE_U 0x00000024
PPER_3
1
MPLS label 3 match range
upper value
Page 263
4.11.6.1
ETHERNET_COMPARATOR:EGR1_MPLS_FLOW_CFG:EGR1_MPLS_FLOW_
CONTROL
Parent: ETHERNET_COMPARATOR:EGR1_MPLS_FLOW_CFG
Instances: 1
VMDS-10510 VSC8574-02 Datasheet Revision 4.2
260
Table 426 • Fields in EGR1_MPLS_FLOW_CONTROL
Field Name
Bit
Access
Description
Default
EGR1_MPLS_CHANNEL_MASK
25:24
R/W
MPLS channel mask selector
0x0: Flow invalid
0x1: Flow valid for channel 0
0x2: Flow valid for channel 1
0x3: Flow valid for both channels
0x3
EGR1_MPLS_STACK_DEPTH
19:16
R/W
Stack depth configuration
Defines the allowable stack depths for
searches. The direction that the stack is
referenced is determined by the setting of
MPLS_REF_PNT. For each bit set, the
following table maps bits to stack depths:
0: Stack allowed to be 1 label deep
1: Stack allowed to be 2 labels deep
2: Stack allowed to be 3 labels deep
3: Stack allowed to be 4 labels deep
0x0
EGR1_MPLS_REF_PNT
4
R/W
Search direction for label matching
0x0
0: All searching is performed starting from the
top of the stack
1: All searching is performed from the end of
the stack
EGR1_MPLS_FLOW_ENA
0
R/W
Flow enable.
If this comparator block is not used, all flow
enable bits must be set to 0.
0: Flow is disabled
1: Flow is enabled
4.11.6.2
0x0
ETHERNET_COMPARATOR:EGR1_MPLS_FLOW_CFG:EGR1_MPLS_LABEL_
RANGE_LOWER_0
Parent: ETHERNET_COMPARATOR:EGR1_MPLS_FLOW_CFG
Instances: 1
Table 427 • Fields in EGR1_MPLS_LABEL_RANGE_LOWER_0
Field Name
Bit
Access
Description
Default
EGR1_MPLS_LABEL_RANGE_L
OWER_0
19:0
R/W
Lower value for label 0 match range
0x00000
4.11.6.3
ETHERNET_COMPARATOR:EGR1_MPLS_FLOW_CFG:EGR1_MPLS_LABEL_
RANGE_UPPER_0
Parent: ETHERNET_COMPARATOR:EGR1_MPLS_FLOW_CFG
Instances: 1
VMDS-10510 VSC8574-02 Datasheet Revision 4.2
261
Table 428 • Fields in EGR1_MPLS_LABEL_RANGE_UPPER_0
Field Name
Bit
EGR1_MPLS_LABEL_RANGE_U 19:0
PPER_0
4.11.6.4
Access
Description
Default
R/W
Upper value for label 0 match range
0xFFFFF
ETHERNET_COMPARATOR:EGR1_MPLS_FLOW_CFG:EGR1_MPLS_LABEL_
RANGE_LOWER_1
Parent: ETHERNET_COMPARATOR:EGR1_MPLS_FLOW_CFG
Instances: 1
Table 429 • Fields in EGR1_MPLS_LABEL_RANGE_LOWER_1
Field Name
Bit
Access
Description
Default
EGR1_MPLS_LABEL_RANGE_L
OWER_1
19:0
R/W
Lower value for label 1 match range
0x00000
4.11.6.5
ETHERNET_COMPARATOR:EGR1_MPLS_FLOW_CFG:EGR1_MPLS_LABEL_
RANGE_UPPER_1
Parent: ETHERNET_COMPARATOR:EGR1_MPLS_FLOW_CFG
Instances: 1
Table 430 • Fields in EGR1_MPLS_LABEL_RANGE_UPPER_1
Field Name
Bit
EGR1_MPLS_LABEL_RANGE_U 19:0
PPER_1
4.11.6.6
Access
Description
Default
R/W
Upper value for label 1 match range
0xFFFFF
ETHERNET_COMPARATOR:EGR1_MPLS_FLOW_CFG:EGR1_MPLS_LABEL_
RANGE_LOWER_2
Parent: ETHERNET_COMPARATOR:EGR1_MPLS_FLOW_CFG
Instances: 1
Table 431 • Fields in EGR1_MPLS_LABEL_RANGE_LOWER_2
Field Name
Bit
Access
Description
Default
EGR1_MPLS_LABEL_RANGE_L
OWER_2
19:0
R/W
Lower value for label 2 match range
0x00000
4.11.6.7
ETHERNET_COMPARATOR:EGR1_MPLS_FLOW_CFG:EGR1_MPLS_LABEL_
RANGE_UPPER_2
Parent: ETHERNET_COMPARATOR:EGR1_MPLS_FLOW_CFG
Instances: 1
VMDS-10510 VSC8574-02 Datasheet Revision 4.2
262
Table 432 • Fields in EGR1_MPLS_LABEL_RANGE_UPPER_2
Field Name
Bit
EGR1_MPLS_LABEL_RANGE_U 19:0
PPER_2
4.11.6.8
Access
Description
Default
R/W
Upper value for label 2 match range
0xFFFFF
ETHERNET_COMPARATOR:EGR1_MPLS_FLOW_CFG:EGR1_MPLS_LABEL_
RANGE_LOWER_3
Parent: ETHERNET_COMPARATOR:EGR1_MPLS_FLOW_CFG
Instances: 1
Table 433 • Fields in EGR1_MPLS_LABEL_RANGE_LOWER_3
Field Name
Bit
Access
Description
Default
EGR1_MPLS_LABEL_RANGE_L
OWER_3
19:0
R/W
Lower value for label 3 match range
0x00000
4.11.6.9
ETHERNET_COMPARATOR:EGR1_MPLS_FLOW_CFG:EGR1_MPLS_LABEL_
RANGE_UPPER_3
Parent: ETHERNET_COMPARATOR:EGR1_MPLS_FLOW_CFG
Instances: 1
Table 434 • Fields in EGR1_MPLS_LABEL_RANGE_UPPER_3
Field Name
Bit
EGR1_MPLS_LABEL_RANGE_U 19:0
PPER_3
4.11.7
Access
Description
Default
R/W
Upper value for label 3 match range
0xFFFFF
ETHERNET_COMPARATOR:EGR1_IP1_NXT_PROTOCOL
Parent: Egress0 Ethernet Comparator
Instances: 1
Table 435 • Registers in EGR1_IP1_NXT_PROTOCOL
Register Name
Instances and
Offset within
Address
Register Group Spacing
EGR1_IP1_NXT_COMPARATOR
0x00000000
EGR1_IP1_MODE
EGR1_IP1_PROT_MATCH_1
Description
Details
1
IP next comparator control
register
Page 264
0x00000004
1
IP comparator mode
Page 264
0x00000008
1
IP match register set 1
Page 265
EGR1_IP1_PROT_MATCH_2_UP 0x0000000C
PER
1
Upper portion of match
register 2
Page 265
VMDS-10510 VSC8574-02 Datasheet Revision 4.2
263
Table 435 • Registers in EGR1_IP1_NXT_PROTOCOL (continued)
Instances and
Offset within
Address
Register Group Spacing
Register Name
Description
Details
EGR1_IP1_PROT_MATCH_2_LO 0x00000010
WER
1
Lower portion of match
register 2
Page 265
EGR1_IP1_PROT_MASK_2_UPP 0x00000014
ER
1
Upper portion of match mask
register 2
Page 266
EGR1_IP1_PROT_MASK_2_LOW 0x00000018
ER
1
Lower portion of match mask
register 2
Page 266
EGR1_IP1_PROT_OFFSET_2
0x0000001C
1
IP match offset register set 2
Page 266
EGR1_IP1_UDP_CHKSUM_CFG
0x00000020
1
IP/UDP checksum control
register
Page 266
EGR1_IP1_FRAME_SIG_CFG
0x00000024
1
IP frame signature control
register
Page 267
4.11.7.1
ETHERNET_COMPARATOR:EGR1_IP1_NXT_PROTOCOL:EGR1_IP1_NXT_CO
MPARATOR
Parent: ETHERNET_COMPARATOR:EGR1_IP1_NXT_PROTOCOL
Instances: 1
Table 436 • Fields in EGR1_IP1_NXT_COMPARATOR
Field Name
Bit
Access
Description
EGR1_IP1_NXT_PROTOCOL
15:8
R/W
Number of bytes in this header, points to the 0x00
beginning of the next protocol.
EGR1_IP1_NXT_COMPARATOR
2:0
R/W
Points to the next comparator stage. If this
0x0
comparator block is not used, this field must
be set to 0.
0: Comparator block not used
1: Reserved
2: Reserved
3: IP/UDP/ACH comparator 2
4: Reserved
5: PTP/OAM comparator
6,7: Reserved
4.11.7.2
Default
ETHERNET_COMPARATOR:EGR1_IP1_NXT_PROTOCOL:EGR1_IP1_MODE
Parent: ETHERNET_COMPARATOR:EGR1_IP1_NXT_PROTOCOL
Instances: 1
Table 437 • Fields in EGR1_IP1_MODE
Field Name
Bit
Access
Description
Default
EGR1_IP1_FLOW_OFFSET
12:8
R/W
Points to the source address field in the IP
frame. Use 12 for IPv4 and 8 for IPv6.
0x0C
VMDS-10510 VSC8574-02 Datasheet Revision 4.2
264
Table 437 • Fields in EGR1_IP1_MODE (continued)
Field Name
Bit
Access
Description
Default
EGR1_IP1_MODE
1:0
R/W
IP mode
0: IPv4
1: IPv6
2: Other protocol, 32-bit address match
3: Other protocol, 128-bit address match
0x0
4.11.7.3
ETHERNET_COMPARATOR:EGR1_IP1_NXT_PROTOCOL:EGR1_IP1_PROT_
MATCH_1
Parent: ETHERNET_COMPARATOR:EGR1_IP1_NXT_PROTOCOL
Instances: 1
Table 438 • Fields in EGR1_IP1_PROT_MATCH_1
Field Name
Bit
Access
Description
Default
EGR1_IP1_PROT_OFFSET_1
20:16
R/W
Points to the start of this match field relative
to the first byte of this protocol
0x00
EGR1_IP1_PROT_MASK_1
15:8
R/W
Mask field for IP_PROT_MATCH_1
0x00
EGR1_IP1_PROT_MATCH_1
7:0
R/W
8-bit match field
0x00
4.11.7.4
ETHERNET_COMPARATOR:EGR1_IP1_NXT_PROTOCOL:EGR1_IP1_PROT_
MATCH_2_UPPER
Parent: ETHERNET_COMPARATOR:EGR1_IP1_NXT_PROTOCOL
Instances: 1
Table 439 • Fields in EGR1_IP1_PROT_MATCH_2_UPPER
Field Name
Bit
EGR1_IP1_PROT_MATCH_2_UP 31:0
PER
4.11.7.5
Access
Description
Default
R/W
64-bit match register for advancing to the
next protocol, upper portion.
0x00000000
ETHERNET_COMPARATOR:EGR1_IP1_NXT_PROTOCOL:EGR1_IP1_PROT_
MATCH_2_LOWER
Parent: ETHERNET_COMPARATOR:EGR1_IP1_NXT_PROTOCOL
Instances: 1
Table 440 • Fields in EGR1_IP1_PROT_MATCH_2_LOWER
Field Name
Bit
EGR1_IP1_PROT_MATCH_2_LO 31:0
WER
Access
Description
Default
R/W
64-bit match register for advancing to the
next protocol, lower portion.
0x00000000
VMDS-10510 VSC8574-02 Datasheet Revision 4.2
265
4.11.7.6
ETHERNET_COMPARATOR:EGR1_IP1_NXT_PROTOCOL:EGR1_IP1_PROT_
MASK_2_UPPER
Parent: ETHERNET_COMPARATOR:EGR1_IP1_NXT_PROTOCOL
Instances: 1
Table 441 • Fields in EGR1_IP1_PROT_MASK_2_UPPER
Field Name
Bit
EGR1_IP1_PROT_MASK_2_UPP 31:0
ER
4.11.7.7
Access
Description
Default
R/W
64-bit match register for advancing to the
next protocol, upper portion.
0x00000000
ETHERNET_COMPARATOR:EGR1_IP1_NXT_PROTOCOL:EGR1_IP1_PROT_
MASK_2_LOWER
Parent: ETHERNET_COMPARATOR:EGR1_IP1_NXT_PROTOCOL
Instances: 1
Table 442 • Fields in EGR1_IP1_PROT_MASK_2_LOWER
Field Name
Bit
EGR1_IP1_PROT_MASK_2_LOW 31:0
ER
4.11.7.8
Access
Description
Default
R/W
64-bit match register for advancing to the
next protocol, lower portion.
0x00000000
ETHERNET_COMPARATOR:EGR1_IP1_NXT_PROTOCOL:EGR1_IP1_PROT_O
FFSET_2
Parent: ETHERNET_COMPARATOR:EGR1_IP1_NXT_PROTOCOL
Instances: 1
Table 443 • Fields in EGR1_IP1_PROT_OFFSET_2
Field Name
Bit
Access
Description
EGR1_IP1_PROT_OFFSET_2
6:0
R/W
Points to the start of match field 2 relative to 0x00
the first byte of this protocol
4.11.7.9
Default
ETHERNET_COMPARATOR:EGR1_IP1_NXT_PROTOCOL:EGR1_IP1_UDP_CH
KSUM_CFG
Parent: ETHERNET_COMPARATOR:EGR1_IP1_NXT_PROTOCOL
Instances: 1
VMDS-10510 VSC8574-02 Datasheet Revision 4.2
266
Table 444 • Fields in EGR1_IP1_UDP_CHKSUM_CFG
Field Name
Bit
Access
Description
Default
EGR1_IP1_UDP_CHKSUM_OFFS 15:8
ET
R/W
Pointer to the IP/UDP checksum field FOR
IPv4 frames or to the pad bytes of a
IPv6/UDP frame. For IPv4, it points to the
bytes that will be cleared. For IPv6, it points
to the bytes that will be updated to fix the
CRC.
0x00
EGR1_IP1_UDP_CHKSUM_WIDT 5:4
H
R/W
Specifies the length of the checksum field in 0x2
bytes
EGR1_IP1_UDP_CHKSUM_UPD
ATE_ENA
1
R/W
This bit and
0x0
IP_UDP_CHKSUM_CLEAR_ENA CANNOT
be set together
0: No pad byte field update
1: Update the pad bytes at the end of the
frame
EGR1_IP1_UDP_CHKSUM_CLEA 0
R_ENA
R/W
This bit and
IP_UDP_CHKSUM_UPDATE_ENA
CANNOT be set together
0: Do not clear the checksum
1: Clear the UDP checksum field in an IPv4
frame
0x0
4.11.7.10 ETHERNET_COMPARATOR:EGR1_IP1_NXT_PROTOCOL:EGR1_IP1_FRAME
_SIG_CFG
Parent: ETHERNET_COMPARATOR:EGR1_IP1_NXT_PROTOCOL
Instances: 1
Table 445 • Fields in EGR1_IP1_FRAME_SIG_CFG
Field Name
Bit
Access
Description
Default
EGR1_IP1_FRAME_SIG_OFFSE
T
4:0
R/W
Pointer to the start of the field that will be
used for the frame signature. Position is
relative to the first header byte of this IP
protocol. Only even values are allowed.
0x00
4.11.8
ETHERNET_COMPARATOR:EGR1_IP1_FLOW_CFG
Parent: Egress0 Ethernet Comparator
Instances: 8
Table 446 • Registers in EGR1_IP1_FLOW_CFG
Register Name
Instances and
Offset within
Address
Register Group Spacing
Description
Details
EGR1_IP1_FLOW_ENA
0x00000000
IP flow enable register
Page 268
1
VMDS-10510 VSC8574-02 Datasheet Revision 4.2
267
Table 446 • Registers in EGR1_IP1_FLOW_CFG (continued)
Instances and
Address
Offset within
Register Group Spacing
Register Name
Description
Details
EGR1_IP1_FLOW_MATCH_UPPE 0x00000004
R
1
Upper portion of the IP flow
match register
Page 268
EGR1_IP1_FLOW_MATCH_UPPE 0x00000008
R_MID
1
Upper mid portion of the IP
flow match register
Page 269
EGR1_IP1_FLOW_MATCH_LOW 0x0000000C
ER_MID
1
Lower mid portion of the IP
flow match register
Page 269
EGR1_IP1_FLOW_MATCH_LOW 0x00000010
ER
1
Lower portion of the IP flow
match register
Page 269
EGR1_IP1_FLOW_MASK_UPPE
R
0x00000014
1
IP flow match mask register,
bytes 12-15
Page 269
EGR1_IP1_FLOW_MASK_UPPE
R_MID
0x00000018
1
IP flow match mask register,
bytes 8-11
Page 270
EGR1_IP1_FLOW_MASK_LOWE 0x0000001C
R_MID
1
IP flow match mask register,
bytes 4-7
Page 270
EGR1_IP1_FLOW_MASK_LOWE 0x00000020
R
1
IP flow match mask register,
bytes 0-3
Page 270
4.11.8.1
ETHERNET_COMPARATOR:EGR1_IP1_FLOW_CFG:EGR1_IP1_FLOW_ENA
Parent: ETHERNET_COMPARATOR:EGR1_IP1_FLOW_CFG
Instances: 1
Table 447 • Fields in EGR1_IP1_FLOW_ENA
Field Name
Access
Description
Default
EGR1_IP1_FLOW_MATCH_MOD 9:8
E
R/W
Match mode
0: Match on source address
1: Match on destination address
2: Match on either source or destination
address
3: Reserved
0x0
EGR1_IP1_CHANNEL_MASK
5:4
R/W
Channel mask
0x0: Flow invalid
0x1: Flow valid for channel 0
0x2: Flow valid for channel 1
0x3: Flow valid for both channels
0x3
EGR1_IP1_FLOW_ENA
0
R/W
Flow enable.
If this comparator block is not used, all flow
enable bits must be set to 0.
0: Flow disabled
1: Flow enabled
0x0
4.11.8.2
Bit
ETHERNET_COMPARATOR:EGR1_IP1_FLOW_CFG:EGR1_IP1_FLOW_MATC
H_UPPER
Parent: ETHERNET_COMPARATOR:EGR1_IP1_FLOW_CFG
VMDS-10510 VSC8574-02 Datasheet Revision 4.2
268
Instances: 1
Table 448 • Fields in EGR1_IP1_FLOW_MATCH_UPPER
Field Name
Bit
EGR1_IP1_FLOW_MATCH_UPPE 31:0
R
4.11.8.3
Access
Description
Default
R/W
Match field for either the entire 32-bit
0x00000000
selected address for IPv4 or the upper 32 bits
of the selected address for IPv6
ETHERNET_COMPARATOR:EGR1_IP1_FLOW_CFG:EGR1_IP1_FLOW_MATC
H_UPPER_MID
Parent: ETHERNET_COMPARATOR:EGR1_IP1_FLOW_CFG
Instances: 1
Table 449 • Fields in EGR1_IP1_FLOW_MATCH_UPPER_MID
Field Name
Bit
EGR1_IP1_FLOW_MATCH_UPPE 31:0
R_MID
4.11.8.4
Access
Description
Default
R/W
Match bits for the upper middle 32 bits of the 0x00000000
IPv6 address
ETHERNET_COMPARATOR:EGR1_IP1_FLOW_CFG:EGR1_IP1_FLOW_MATC
H_LOWER_MID
Parent: ETHERNET_COMPARATOR:EGR1_IP1_FLOW_CFG
Instances: 1
Table 450 • Fields in EGR1_IP1_FLOW_MATCH_LOWER_MID
Field Name
Bit
EGR1_IP1_FLOW_MATCH_LOW 31:0
ER_MID
4.11.8.5
Access
Description
Default
R/W
Match bits for the lower middle 32 bits of the 0x00000000
IPv6 address
ETHERNET_COMPARATOR:EGR1_IP1_FLOW_CFG:EGR1_IP1_FLOW_MATC
H_LOWER
Parent: ETHERNET_COMPARATOR:EGR1_IP1_FLOW_CFG
Instances: 1
Table 451 • Fields in EGR1_IP1_FLOW_MATCH_LOWER
Field Name
Bit
EGR1_IP1_FLOW_MATCH_LOW 31:0
ER
4.11.8.6
Access
Description
Default
R/W
Match bits for the lower 32 bits of the IPv6
address
0x00000000
ETHERNET_COMPARATOR:EGR1_IP1_FLOW_CFG:EGR1_IP1_FLOW_MASK
_UPPER
Parent: ETHERNET_COMPARATOR:EGR1_IP1_FLOW_CFG
VMDS-10510 VSC8574-02 Datasheet Revision 4.2
269
Instances: 1
Table 452 • Fields in EGR1_IP1_FLOW_MASK_UPPER
Field Name
Bit
Access
Description
Default
EGR1_IP1_FLOW_MASK_UPPE
R
31:0
R/W
Address mask for the IP address
0x00000000
4.11.8.7
ETHERNET_COMPARATOR:EGR1_IP1_FLOW_CFG:EGR1_IP1_FLOW_MASK
_UPPER_MID
Parent: ETHERNET_COMPARATOR:EGR1_IP1_FLOW_CFG
Instances: 1
Table 453 • Fields in EGR1_IP1_FLOW_MASK_UPPER_MID
Field Name
Bit
Access
Description
EGR1_IP1_FLOW_MASK_UPPE
R_MID
31:0
R/W
These bits must be all 0 for IPv4 and any 32- 0x00000000
bit address match mode
4.11.8.8
Default
ETHERNET_COMPARATOR:EGR1_IP1_FLOW_CFG:EGR1_IP1_FLOW_MASK
_LOWER_MID
Parent: ETHERNET_COMPARATOR:EGR1_IP1_FLOW_CFG
Instances: 1
Table 454 • Fields in EGR1_IP1_FLOW_MASK_LOWER_MID
Field Name
Bit
EGR1_IP1_FLOW_MASK_LOWE 31:0
R_MID
4.11.8.9
Access
Description
Default
R/W
These bits must be all 0 for IPv4 and any 32- 0x00000000
bit address match mode
ETHERNET_COMPARATOR:EGR1_IP1_FLOW_CFG:EGR1_IP1_FLOW_MASK
_LOWER
Parent: ETHERNET_COMPARATOR:EGR1_IP1_FLOW_CFG
Instances: 1
Table 455 • Fields in EGR1_IP1_FLOW_MASK_LOWER
Field Name
Bit
EGR1_IP1_FLOW_MASK_LOWE 31:0
R
4.11.9
Access
Description
Default
R/W
These bits must be all 0 for IPv4 and any 32- 0x00000000
bit address match mode
ETHERNET_COMPARATOR:EGR1_IP2_NXT_PROTOCOL
Parent: Egress0 Ethernet Comparator
Instances: 1
VMDS-10510 VSC8574-02 Datasheet Revision 4.2
270
Table 456 • Registers in EGR1_IP2_NXT_PROTOCOL
Register Name
Instances and
Offset within
Address
Register Group Spacing
EGR1_IP2_NXT_COMPARATOR
0x00000000
EGR1_IP2_MODE
EGR1_IP2_PROT_MATCH_1
Description
Details
1
IP next comparator control
register
Page 271
0x00000004
1
IP comparator mode
Page 271
0x00000008
1
IP match register set 1
Page 272
EGR1_IP2_PROT_MATCH_2_UP 0x0000000C
PER
1
Upper portion of match
register 2
Page 272
EGR1_IP2_PROT_MATCH_2_LO 0x00000010
WER
1
Lower portion of match
register 2
Page 272
EGR1_IP2_PROT_MASK_2_UPP 0x00000014
ER
1
Upper portion of match mask
register 2
Page 273
EGR1_IP2_PROT_MASK_2_LOW 0x00000018
ER
1
Lower portion of match mask
register 2
Page 273
EGR1_IP2_PROT_OFFSET_2
0x0000001C
1
IP match offset register set 2
Page 273
EGR1_IP2_UDP_CHKSUM_CFG
0x00000020
1
IP/UDP checksum control
register
Page 273
EGR1_IP2_FRAME_SIG_CFG
0x00000024
1
IP frame signature control
register
Page 274
4.11.9.1
ETHERNET_COMPARATOR:EGR1_IP2_NXT_PROTOCOL:EGR1_IP2_NXT_CO
MPARATOR
Parent: ETHERNET_COMPARATOR:EGR1_IP2_NXT_PROTOCOL
Instances: 1
Table 457 • Fields in EGR1_IP2_NXT_COMPARATOR
Field Name
Bit
Access
Description
EGR1_IP2_NXT_PROTOCOL
15:8
R/W
Number of bytes in this header, points to the 0x00
beginning of the next protocol.
EGR1_IP2_NXT_COMPARATOR
2:0
R/W
Points to the next comparator stage. If this
0x0
comparator block is not used, this field must
be set to 0.
0: Comparator block not used
1: Reserved
2: Reserved
3: Reserved
4: Reserved
5: PTP/OAM comparator
6,7: Reserved
4.11.9.2
Default
ETHERNET_COMPARATOR:EGR1_IP2_NXT_PROTOCOL:EGR1_IP2_MODE
Parent: ETHERNET_COMPARATOR:EGR1_IP2_NXT_PROTOCOL
Instances: 1
VMDS-10510 VSC8574-02 Datasheet Revision 4.2
271
Table 458 • Fields in EGR1_IP2_MODE
Field Name
Bit
Access
Description
Default
EGR1_IP2_FLOW_OFFSET
12:8
R/W
Points to the source address field in the IP
frame. Use 12 for IPv4 and 8 for IPv6
0x0C
EGR1_IP2_MODE
1:0
R/W
IP mode
0: IPv4
1: IPv6
2: Other protocol, 32-bit address match
3: Other protocol, 128-bit address match
0x0
4.11.9.3
ETHERNET_COMPARATOR:EGR1_IP2_NXT_PROTOCOL:EGR1_IP2_PROT_
MATCH_1
Parent: ETHERNET_COMPARATOR:EGR1_IP2_NXT_PROTOCOL
Instances: 1
Table 459 • Fields in EGR1_IP2_PROT_MATCH_1
Field Name
Bit
Access
Description
Default
EGR1_IP2_PROT_OFFSET_1
20:16
R/W
Points to the start of this match field relative
to the first byte of this protocol
0x00
EGR1_IP2_PROT_MASK_1
15:8
R/W
Mask field for IP_PROT_MATCH_1
0x00
EGR1_IP2_PROT_MATCH_1
7:0
R/W
8-bit match field
0x00
4.11.9.4
ETHERNET_COMPARATOR:EGR1_IP2_NXT_PROTOCOL:EGR1_IP2_PROT_
MATCH_2_UPPER
Parent: ETHERNET_COMPARATOR:EGR1_IP2_NXT_PROTOCOL
Instances: 1
Table 460 • Fields in EGR1_IP2_PROT_MATCH_2_UPPER
Field Name
Bit
EGR1_IP2_PROT_MATCH_2_UP 31:0
PER
4.11.9.5
Access
Description
Default
R/W
64-bit match register for advancing to the
next protocol, upper portion
0x00000000
ETHERNET_COMPARATOR:EGR1_IP2_NXT_PROTOCOL:EGR1_IP2_PROT_
MATCH_2_LOWER
Parent: ETHERNET_COMPARATOR:EGR1_IP2_NXT_PROTOCOL
Instances: 1
Table 461 • Fields in EGR1_IP2_PROT_MATCH_2_LOWER
Field Name
Bit
EGR1_IP2_PROT_MATCH_2_LO 31:0
WER
Access
Description
Default
R/W
64-bit match register for advancing to the
next protocol, lower portion
0x00000000
VMDS-10510 VSC8574-02 Datasheet Revision 4.2
272
4.11.9.6
ETHERNET_COMPARATOR:EGR1_IP2_NXT_PROTOCOL:EGR1_IP2_PROT_
MASK_2_UPPER
Parent: ETHERNET_COMPARATOR:EGR1_IP2_NXT_PROTOCOL
Instances: 1
Table 462 • Fields in EGR1_IP2_PROT_MASK_2_UPPER
Field Name
Bit
EGR1_IP2_PROT_MASK_2_UPP 31:0
ER
4.11.9.7
Access
Description
Default
R/W
64-bit match register for advancing to the
next protocol, upper portion.
0x00000000
ETHERNET_COMPARATOR:EGR1_IP2_NXT_PROTOCOL:EGR1_IP2_PROT_
MASK_2_LOWER
Parent: ETHERNET_COMPARATOR:EGR1_IP2_NXT_PROTOCOL
Instances: 1
Table 463 • Fields in EGR1_IP2_PROT_MASK_2_LOWER
Field Name
Bit
EGR1_IP2_PROT_MASK_2_LOW 31:0
ER
4.11.9.8
Access
Description
Default
R/W
64-bit match register for advancing to the
next protocol, lower portion.
0x00000000
ETHERNET_COMPARATOR:EGR1_IP2_NXT_PROTOCOL:EGR1_IP2_PROT_O
FFSET_2
Parent: ETHERNET_COMPARATOR:EGR1_IP2_NXT_PROTOCOL
Instances: 1
Table 464 • Fields in EGR1_IP2_PROT_OFFSET_2
Field Name
Bit
Access
Description
EGR1_IP2_PROT_OFFSET_2
6:0
R/W
Points to the start of match field 2 relative to 0x00
the first byte of this protocol
4.11.9.9
Default
ETHERNET_COMPARATOR:EGR1_IP2_NXT_PROTOCOL:EGR1_IP2_UDP_CH
KSUM_CFG
Parent: ETHERNET_COMPARATOR:EGR1_IP2_NXT_PROTOCOL
Instances: 1
VMDS-10510 VSC8574-02 Datasheet Revision 4.2
273
Table 465 • Fields in EGR1_IP2_UDP_CHKSUM_CFG
Field Name
Bit
Access
Description
Default
EGR1_IP2_UDP_CHKSUM_OFFS 15:8
ET
R/W
Pointer to the IP/UDP checksum field FOR
IPv4 frames or to the pad bytes of a
IPv6/UDP frame. For IPv4, it points to the
bytes that will be cleared. For IPv6, it points
to the bytes that will be updated to fix the
CRC.
0x00
EGR1_IP2_UDP_CHKSUM_WIDT 5:4
H
R/W
Specifies the length of the checksum field in 0x2
bytes
EGR1_IP2_UDP_CHKSUM_UPD
ATE_ENA
1
R/W
This bit and
0x0
IP_UDP_CHKSUM_CLEAR_ENA CANNOT
be set together
0: No pad byte field update
1: Update the pad bytes at the end of the
frame
EGR1_IP2_UDP_CHKSUM_CLEA 0
R_ENA
R/W
This bit and
IP_UDP_CHKSUM_UPDATE_ENA
CANNOT be set together
0: Do not clear the checksum
1: Clear the UDP checksum field in an IPv4
frame
0x0
4.11.9.10 ETHERNET_COMPARATOR:EGR1_IP2_NXT_PROTOCOL:EGR1_IP2_FRAME
_SIG_CFG
Parent: ETHERNET_COMPARATOR:EGR1_IP2_NXT_PROTOCOL
Instances: 1
Table 466 • Fields in EGR1_IP2_FRAME_SIG_CFG
Field Name
Bit
Access
Description
Default
EGR1_IP2_FRAME_SIG_OFFSE
T
4:0
R/W
Pointer to the start of the field that will be
used for the frame signature. Position is
relative to the first header byte of this IP
protocol. Only even values are allowed.
0x00
4.11.10 ETHERNET_COMPARATOR:EGR1_IP2_FLOW_CFG
Parent: Egress0 Ethernet Comparator
Instances: 8
Table 467 • Registers in EGR1_IP2_FLOW_CFG
Register Name
Instances and
Offset within
Address
Register Group Spacing
Description
Details
EGR1_IP2_FLOW_ENA
0x00000000
IP flow enable register
Page 275
1
VMDS-10510 VSC8574-02 Datasheet Revision 4.2
274
Table 467 • Registers in EGR1_IP2_FLOW_CFG (continued)
Instances and
Address
Offset within
Register Group Spacing
Register Name
Description
Details
EGR1_IP2_FLOW_MATCH_UPPE 0x00000004
R
1
Upper portion of the IP flow
match register
Page 275
EGR1_IP2_FLOW_MATCH_UPPE 0x00000008
R_MID
1
Upper mid portion of the IP
flow match register
Page 276
EGR1_IP2_FLOW_MATCH_LOW 0x0000000C
ER_MID
1
Lower mid portion of the IP
flow match register
Page 276
EGR1_IP2_FLOW_MATCH_LOW 0x00000010
ER
1
Lower portion of the IP flow
match register
Page 276
EGR1_IP2_FLOW_MASK_UPPE
R
0x00000014
1
IP flow match mask register,
bytes 12-15
Page 276
EGR1_IP2_FLOW_MASK_UPPE
R_MID
0x00000018
1
IP flow match mask register,
bytes 8-11
Page 277
EGR1_IP2_FLOW_MASK_LOWE 0x0000001C
R_MID
1
IP flow match mask register,
bytes 4-7
Page 277
EGR1_IP2_FLOW_MASK_LOWE 0x00000020
R
1
IP flow match mask register,
bytes 0-3
Page 277
4.11.10.1 ETHERNET_COMPARATOR:EGR1_IP2_FLOW_CFG:EGR1_IP2_FLOW_ENA
Parent: ETHERNET_COMPARATOR:EGR1_IP2_FLOW_CFG
Instances: 1
Table 468 • Fields in EGR1_IP2_FLOW_ENA
Field Name
Bit
Access
Description
Default
EGR1_IP2_FLOW_MATCH_MOD 9:8
E
R/W
Match mode
0: Match on source address
1: Match on destination address
2: Match on either source or destination
address
3: Reserved
0x0
EGR1_IP2_CHANNEL_MASK
5:4
R/W
Channel mask
0x0: Flow invalid
0x1: Flow valid for channel 0
0x2: Flow valid for channel 1
0x3: Flow valid for both channels
0x3
EGR1_IP2_FLOW_ENA
0
R/W
Flow enable.
If this comparator block is not used, all flow
enable bits must be set to 0.
0: Flow disabled
1: Flow enabled
0x0
4.11.10.2 ETHERNET_COMPARATOR:EGR1_IP2_FLOW_CFG:EGR1_IP2_FLOW_MAT
CH_UPPER
Parent: ETHERNET_COMPARATOR:EGR1_IP2_FLOW_CFG
VMDS-10510 VSC8574-02 Datasheet Revision 4.2
275
Instances: 1
Table 469 • Fields in EGR1_IP2_FLOW_MATCH_UPPER
Field Name
Bit
EGR1_IP2_FLOW_MATCH_UPPE 31:0
R
Access
Description
Default
R/W
Match field for either the entire 32-bit
0x00000000
selected address for IPv4 or the upper 32 bits
of the selected address for IPv6
4.11.10.3 ETHERNET_COMPARATOR:EGR1_IP2_FLOW_CFG:EGR1_IP2_FLOW_MAT
CH_UPPER_MID
Parent: ETHERNET_COMPARATOR:EGR1_IP2_FLOW_CFG
Instances: 1
Table 470 • Fields in EGR1_IP2_FLOW_MATCH_UPPER_MID
Field Name
Bit
EGR1_IP2_FLOW_MATCH_UPPE 31:0
R_MID
Access
Description
Default
R/W
Match bits for the upper middle 32 bits of the 0x00000000
IPv6 address
4.11.10.4 ETHERNET_COMPARATOR:EGR1_IP2_FLOW_CFG:EGR1_IP2_FLOW_MAT
CH_LOWER_MID
Parent: ETHERNET_COMPARATOR:EGR1_IP2_FLOW_CFG
Instances: 1
Table 471 • Fields in EGR1_IP2_FLOW_MATCH_LOWER_MID
Field Name
Bit
EGR1_IP2_FLOW_MATCH_LOW 31:0
ER_MID
Access
Description
Default
R/W
Match bits for the lower middle 32 bits of the 0x00000000
IPv6 address
4.11.10.5 ETHERNET_COMPARATOR:EGR1_IP2_FLOW_CFG:EGR1_IP2_FLOW_MAT
CH_LOWER
Parent: ETHERNET_COMPARATOR:EGR1_IP2_FLOW_CFG
Instances: 1
Table 472 • Fields in EGR1_IP2_FLOW_MATCH_LOWER
Field Name
Bit
EGR1_IP2_FLOW_MATCH_LOW 31:0
ER
Access
Description
Default
R/W
Match bits for the lower 32 bits of the IPv6
address
0x00000000
4.11.10.6 ETHERNET_COMPARATOR:EGR1_IP2_FLOW_CFG:EGR1_IP2_FLOW_MAS
K_UPPER
Parent: ETHERNET_COMPARATOR:EGR1_IP2_FLOW_CFG
VMDS-10510 VSC8574-02 Datasheet Revision 4.2
276
Instances: 1
Table 473 • Fields in EGR1_IP2_FLOW_MASK_UPPER
Field Name
Bit
Access
Description
Default
EGR1_IP2_FLOW_MASK_UPPE
R
31:0
R/W
Address mask for the IP address
0x00000000
4.11.10.7 ETHERNET_COMPARATOR:EGR1_IP2_FLOW_CFG:EGR1_IP2_FLOW_MAS
K_UPPER_MID
Parent: ETHERNET_COMPARATOR:EGR1_IP2_FLOW_CFG
Instances: 1
Table 474 • Fields in EGR1_IP2_FLOW_MASK_UPPER_MID
Field Name
Bit
Access
Description
Default
EGR1_IP2_FLOW_MASK_UPPE
R_MID
31:0
R/W
These bits must be all 0 for IPv4 and any 32- 0x00000000
bit address match mode
4.11.10.8 ETHERNET_COMPARATOR:EGR1_IP2_FLOW_CFG:EGR1_IP2_FLOW_MAS
K_LOWER_MID
Parent: ETHERNET_COMPARATOR:EGR1_IP2_FLOW_CFG
Instances: 1
Table 475 • Fields in EGR1_IP2_FLOW_MASK_LOWER_MID
Field Name
Bit
EGR1_IP2_FLOW_MASK_LOWE 31:0
R_MID
Access
Description
Default
R/W
These bits must be all 0 for IPv4 and any 32- 0x00000000
bit address match mode
4.11.10.9 ETHERNET_COMPARATOR:EGR1_IP2_FLOW_CFG:EGR1_IP2_FLOW_MAS
K_LOWER
Parent: ETHERNET_COMPARATOR:EGR1_IP2_FLOW_CFG
Instances: 1
Table 476 • Fields in EGR1_IP2_FLOW_MASK_LOWER
Field Name
Bit
EGR1_IP2_FLOW_MASK_LOWE 31:0
R
Access
Description
Default
R/W
These bits must be all 0 for IPv4 and any 32- 0x00000000
bit address match mode
4.11.11 ETHERNET_COMPARATOR:EGR1_PTP_FLOW
Parent: Egress0 Ethernet Comparator
Instances: 6
VMDS-10510 VSC8574-02 Datasheet Revision 4.2
277
Table 477 • Registers in EGR1_PTP_FLOW
Register Name
Instances and
Offset within
Address
Register Group Spacing
Description
Details
EGR1_PTP_FLOW_ENA
0x00000000
1
PTP/OAM flow enable
Page 278
EGR1_PTP_FLOW_MATCH_UPP 0x00000004
ER
1
Upper half of PTP/OAM flow
match field
Page 278
EGR1_PTP_FLOW_MATCH_LOW 0x00000008
ER
1
Lower half of PTP/OAM flow
match field
Page 279
EGR1_PTP_FLOW_MASK_UPPE 0x0000000C
R
1
Upper half of PTP/OAM flow
match mask
Page 279
EGR1_PTP_FLOW_MASK_LOWE 0x00000010
R
1
Lower half of PTP/OAM flow
match mask
Page 279
EGR1_PTP_DOMAIN_RANGE
0x00000014
1
PTP/OAM range match
register
Page 279
EGR1_PTP_ACTION
0x00000018
1
PTP action control register
Page 280
EGR1_PTP_ACTION_2
0x0000001C
1
PTP action control register 2
Page 281
EGR1_PTP_ZERO_FIELD_CTL
0x00000020
1
Zero field control register
Page 281
4.11.11.1 ETHERNET_COMPARATOR:EGR1_PTP_FLOW:EGR1_PTP_FLOW_ENA
Parent: ETHERNET_COMPARATOR:EGR1_PTP_FLOW
Instances: 1
Table 478 • Fields in EGR1_PTP_FLOW_ENA
Field Name
Bit
Access
Description
Default
EGR1_PTP_CHANNEL_MASK
5:4
R/W
Channel mask
0x0: Flow invalid
0x1: Flow valid for channel 0
0x2: Flow valid for channel 1
0x3: Flow valid for both channels
0x3
EGR1_PTP_FLOW_ENA
0
R/W
Flow enable
0x0
4.11.11.2 ETHERNET_COMPARATOR:EGR1_PTP_FLOW:EGR1_PTP_FLOW_MATCH_
UPPER
Parent: ETHERNET_COMPARATOR:EGR1_PTP_FLOW
Instances: 1
Table 479 • Fields in EGR1_PTP_FLOW_MATCH_UPPER
Field Name
Bit
EGR1_PTP_FLOW_MATCH_UPP 31:0
ER
Access
Description
Default
R/W
PTP flow match, upper 32 bit
0x00000000
VMDS-10510 VSC8574-02 Datasheet Revision 4.2
278
4.11.11.3 ETHERNET_COMPARATOR:EGR1_PTP_FLOW:EGR1_PTP_FLOW_MATCH_
LOWER
Parent: ETHERNET_COMPARATOR:EGR1_PTP_FLOW
Instances: 1
Table 480 • Fields in EGR1_PTP_FLOW_MATCH_LOWER
Field Name
Bit
EGR1_PTP_FLOW_MATCH_LOW 31:0
ER
Access
Description
Default
R/W
PTP flow match, lower 32 bit
0x00000000
4.11.11.4 ETHERNET_COMPARATOR:EGR1_PTP_FLOW:EGR1_PTP_FLOW_MASK_U
PPER
Parent: ETHERNET_COMPARATOR:EGR1_PTP_FLOW
Instances: 1
Table 481 • Fields in EGR1_PTP_FLOW_MASK_UPPER
Field Name
Bit
EGR1_PTP_FLOW_MASK_UPPE 31:0
R
Access
Description
Default
R/W
PTP flow mask, upper 32 bit
0x00000000
4.11.11.5 ETHERNET_COMPARATOR:EGR1_PTP_FLOW:EGR1_PTP_FLOW_MASK_L
OWER
Parent: ETHERNET_COMPARATOR:EGR1_PTP_FLOW
Instances: 1
Table 482 • Fields in EGR1_PTP_FLOW_MASK_LOWER
Field Name
Bit
EGR1_PTP_FLOW_MASK_LOWE 31:0
R
Access
Description
Default
R/W
PTP flow mask, lower 32 bit
0x00000000
4.11.11.6 ETHERNET_COMPARATOR:EGR1_PTP_FLOW:EGR1_PTP_DOMAIN_RANG
E
Parent: ETHERNET_COMPARATOR:EGR1_PTP_FLOW
Instances: 1
Table 483 • Fields in EGR1_PTP_DOMAIN_RANGE
Field Name
Bit
Access
Description
Default
EGR1_PTP_DOMAIN_RANGE_O 28:24
FFSET
R/W
PTP domain range offset
0x00
EGR1_PTP_DOMAIN_RANGE_U 23:16
PPER
R/W
Upper range of PTP domain field to match
0xFF
VMDS-10510 VSC8574-02 Datasheet Revision 4.2
279
Table 483 • Fields in EGR1_PTP_DOMAIN_RANGE (continued)
Field Name
Bit
Access
Description
Default
EGR1_PTP_DOMAIN_RANGE_L
OWER
15:8
R/W
Lower range of PTP domain field to match
0x00
R/W
Enable PTP domain range checking
0x0
EGR1_PTP_DOMAIN_RANGE_E 0
NA
4.11.11.7 ETHERNET_COMPARATOR:EGR1_PTP_FLOW:EGR1_PTP_ACTION
Parent: ETHERNET_COMPARATOR:EGR1_PTP_FLOW
Instances: 1
Table 484 • Fields in EGR1_PTP_ACTION
Field Name
Bit
Access
Description
Default
EGR1_PTP_MOD_FRAME_STAT 28
_UPDATE
R/W
Modified frame status update
0: Do not signal the rewriter to update value
of the Modified Frame Status bit
1: Signal the rewriter to update value of the
Modified Frame Status bit
0x0
EGR1_PTP_MOD_FRAME_BYTE 26:24
_OFFSET
R/W
Indicates the position relative to the start of
the PTP frame in bytes where the Modified
Frame Status bit resides
0x0
EGR1_PTP_SUB_DELAY_ASYM_ 21
ENA
R/W
Enable subtract delay asymmetry signal
0x0
0: Do not signal the timestamp block to
subtract the asymmetry delay
1: Signal the timestamp block to subtract the
asymmetry delay
EGR1_PTP_ADD_DELAY_ASYM 20
_ENA
R/W
Enable add delay asymmetry signal
0: Do not signal the timestamp block to add
the asymmetry delay
1: Signal the timestamp block to add the
asymmetry delay
0x0
EGR1_PTP_TIME_STRG_FIELD_ 15:10
OFFSET
R/W
Time storage field offset
The location in a PTP frame where a time
value can be stored or read
0x00
EGR1_PTP_CORR_FIELD_OFFS 9:5
ET
R/W
Points to the location of the correction field
for updating the timestamp. Location is
relative to the first byte of the PTP/OAM
header.
Note: If this flow is being used to
match OAM frames, set this
register to 4
0x00
EGR1_PTP_SAVE_LOCAL_TIME 4
R/W
Enable saving time
0x0
0: Do not save the time to the timestamp
FIFO
1: Save the local time to the timestamp FIFO
VMDS-10510 VSC8574-02 Datasheet Revision 4.2
280
Table 484 • Fields in EGR1_PTP_ACTION (continued)
Field Name
Bit
Access
Description
Default
EGR1_PTP_COMMAND
3:0
R/W
PTP action command
0: NOP
1: SUB
2: SUB_P2P
3: ADD
4: SUB_ADD
5: WRITE_1588
6: WRITE_P2P (deprecated)
7: WRITE_NS
8: WRITE_NS_P2P
0x0
4.11.11.8 ETHERNET_COMPARATOR:EGR1_PTP_FLOW:EGR1_PTP_ACTION_2
Parent: ETHERNET_COMPARATOR:EGR1_PTP_FLOW
Instances: 1
Table 485 • Fields in EGR1_PTP_ACTION_2
Field Name
Bit
Access
Description
Default
EGR1_PTP_NEW_CF_LOC
23:16
R/W
Location of the new correction field relative to 0x00
the PTP header start. Only even values are
allowed.
EGR1_PTP_REWRITE_OFFSET
15:8
R/W
Points to where in the frame relative to the
SFD that the timestamp should be updated
0x00
EGR1_PTP_REWRITE_BYTES
3:0
R/W
Number of bytes in the PTP or OAM frame
that must be modified by the rewriter for the
timestamp
0x0
4.11.11.9 ETHERNET_COMPARATOR:EGR1_PTP_FLOW:EGR1_PTP_ZERO_FIELD_C
TL
Parent: ETHERNET_COMPARATOR:EGR1_PTP_FLOW
Instances: 1
Table 486 • Fields in EGR1_PTP_ZERO_FIELD_CTL
Field Name
Bit
Access
Description
Default
EGR1_PTP_ZERO_FIELD_OFFS 13:8
ET
R/W
Points to a location in the PTP/OAM frame
0x00
relative to the start of the PTP header that will
be zeroed if this function is enabled
EGR1_PTP_ZERO_FIELD_BYTE 3:0
_CNT
R/W
The number of bytes to be zeroed. If this field 0x0
is 0, then this function is not enabled.
4.11.12 ETHERNET_COMPARATOR:EGR1_PTP_IP_CHKSUM_CTL
Parent: Egress0 Ethernet Comparator
Instances: 1
VMDS-10510 VSC8574-02 Datasheet Revision 4.2
281
Table 487 • Registers in EGR1_PTP_IP_CHKSUM_CTL
Register Name
Instances and
Offset within
Address
Register Group Spacing
Description
Details
EGR1_PTP_IP_CKSUM_SEL
0x00000000
IP checksum block select
Page 282
1
4.11.12.1 ETHERNET_COMPARATOR:EGR1_PTP_IP_CHKSUM_CTL:EGR1_PTP_IP_C
KSUM_SEL
Parent: ETHERNET_COMPARATOR:EGR1_PTP_IP_CHKSUM_CTL
Instances: 1
Table 488 • Fields in EGR1_PTP_IP_CKSUM_SEL
Field Name
Bit
Access
Description
Default
EGR1_PTP_IP_CHKSUM_SEL
0
R/W
IP checksum controls selection
0: Use the IP checksum controls from IP
comparator 1
1: Use the IP checksum controls from IP
comparator 2
0x0
4.11.13 ETHERNET_COMPARATOR:EGR1_FRAME_SIG_CFG
Parent: Egress0 Ethernet Comparator
Instances: 1
Table 489 • Registers in EGR1_FRAME_SIG_CFG
Register Name
Instances and
Offset within
Address
Register Group Spacing
EGR1_FSB_CFG
0x00000000
1
Frame signature builder mode Page 282
configuration
EGR1_FSB_MAP_REG_0
0x00000004
1
Frame signature builder
mapping register 0
Page 283
EGR1_FSB_MAP_REG_1
0x00000008
1
Frame signature builder
mapping register 1
Page 283
EGR1_FSB_MAP_REG_2
0x0000000C
1
Frame signature builder
mapping register 2
Page 284
EGR1_FSB_MAP_REG_3
0x00000010
1
Frame signature builder
mapping register 3
Page 284
Description
Details
4.11.13.1 ETHERNET_COMPARATOR:EGR1_FRAME_SIG_CFG:EGR1_FSB_CFG
Parent: ETHERNET_COMPARATOR:EGR1_FRAME_SIG_CFG
Instances: 1
VMDS-10510 VSC8574-02 Datasheet Revision 4.2
282
Table 490 • Fields in EGR1_FSB_CFG
Field Name
Bit
Access
EGR1_FSB_ADR_SEL
1:0
R/W
Description
Default
0x0
0: Use the address from Ethernet block 1
1: Use the address from Ethernet block 2
2: Use the address from IP block 1
3: Use the address from IP block 2
4.11.13.2 ETHERNET_COMPARATOR:EGR1_FRAME_SIG_CFG:EGR1_FSB_MAP_RE
G_0
Parent: ETHERNET_COMPARATOR:EGR1_FRAME_SIG_CFG
Instances: 1
This register selects bytes to pack into the frame signature vector. The frame signature vector is 16 bytes
long. The source bytes are as follows:
select
source
select
source
select source
select source
----------------------------------------------------------------------------------------------------------------------------------0
PTP hdr byte 31
1
PTP hdr byte 30 2
PTP hdr byte 29
3
PTP hdr byte 28
4
PTP hdr byte 27
5
PTP hdr byte 26 6
PTP hdr byte 25
7
PTP hdr byte 24
8
PTP hdr byte 23
9
PTP hdr byte 22 10 PTP hdr byte 21
11 PTP hdr byte 20
12
PTP hdr byte 19
13 PTP hdr byte 18 14 PTP hdr byte 17
15 PTP hdr byte 16
16
PTP hdr byte 15
17 PTP hdr byte 14 18 PTP hdr byte 13
19 PTP hdr byte 12
20
PTP hdr byte 11
21 PTP hdr byte 10 22 PTP hdr byte 9
23 PTP hdr byte 8
24
PTP hdr byte 6
25 PTP hdr byte 4
26 PTP hdr byte 0
27 reserved
28
address byte 0
29 address byte 1
30 addess byte 2
31 address byte 3
32
address byte 4
33 address byte 5
34 addess byte 6
35 address byte 7
all other select values reserved
Table 491 • Fields in EGR1_FSB_MAP_REG_0
Field Name
Bit
Access
Description
Default
EGR1_FSB_MAP_4
29:24
R/W
Frame signature byte 4 select
0x04
EGR1_FSB_MAP_3
23:18
R/W
Frame signature byte 3 select
0x03
EGR1_FSB_MAP_2
17:12
R/W
Frame signature byte 2 select
0x02
EGR1_FSB_MAP_1
11:6
R/W
Frame signature byte 1 select
0x01
EGR1_FSB_MAP_0
5:0
R/W
Frame signature byte 0 select
0x00
4.11.13.3 ETHERNET_COMPARATOR:EGR1_FRAME_SIG_CFG:EGR1_FSB_MAP_RE
G_1
Parent: ETHERNET_COMPARATOR:EGR1_FRAME_SIG_CFG
VMDS-10510 VSC8574-02 Datasheet Revision 4.2
283
Instances: 1
Table 492 • Fields in EGR1_FSB_MAP_REG_1
Field Name
Bit
Access
Description
Default
EGR1_FSB_MAP_9
29:24
R/W
Frame signature byte 9 select
0x09
EGR1_FSB_MAP_8
23:18
R/W
Frame signature byte 8 select
0x08
EGR1_FSB_MAP_7
17:12
R/W
Frame signature byte 7 select
0x07
EGR1_FSB_MAP_6
11:6
R/W
Frame signature byte 6 select
0x06
EGR1_FSB_MAP_5
5:0
R/W
Frame signature byte 5 select
0x05
4.11.13.4 ETHERNET_COMPARATOR:EGR1_FRAME_SIG_CFG:EGR1_FSB_MAP_RE
G_2
Parent: ETHERNET_COMPARATOR:EGR1_FRAME_SIG_CFG
Instances: 1
Table 493 • Fields in EGR1_FSB_MAP_REG_2
Field Name
Bit
Access
Description
Default
EGR1_FSB_MAP_14
29:24
R/W
Frame signature byte 14 select
0x0E
EGR1_FSB_MAP_13
23:18
R/W
Frame signature byte 13 select
0x0D
EGR1_FSB_MAP_12
17:12
R/W
Frame signature byte 12 select
0x0C
EGR1_FSB_MAP_11
11:6
R/W
Frame signature byte 11 select
0x0B
EGR1_FSB_MAP_10
5:0
R/W
Frame signature byte 10 select
0x0A
4.11.13.5 ETHERNET_COMPARATOR:EGR1_FRAME_SIG_CFG:EGR1_FSB_MAP_RE
G_3
Parent: ETHERNET_COMPARATOR:EGR1_FRAME_SIG_CFG
Instances: 1
Table 494 • Fields in EGR1_FSB_MAP_REG_3
Field Name
Bit
Access
Description
Default
EGR1_FSB_MAP_15
5:0
R/W
Frame signature byte 15 select
0x0F
4.12
Ingress1 Ethernet Comparator
Table 495 • Register Groups in Ingress1 Ethernet Comparator
Register Group Name
Offset within
Target
Instances and
Address
Spacing
INGR1_ETH1_NXT_PROTOCOL
0x00000000
1
Description
Details
Ethernet next protocol
configuration
Page 285
VMDS-10510 VSC8574-02 Datasheet Revision 4.2
284
Table 495 • Register Groups in Ingress1 Ethernet Comparator (continued)
Register Group Name
Offset within
Target
INGR1_ETH1_FLOW_CFG
0x00000040
INGR1_ETH2_NXT_PROTOCOL
Instances and
Address
Spacing
Description
Details
8
0x00000040
Ethernet flow configuration
Page 287
0x00000240
1
Ethernet next protocol
configuration
Page 290
INGR1_ETH2_FLOW_CFG
0x00000280
8
0x00000040
Ethernet flow configuration
Page 292
INGR1_MPLS_NXT_COMPARAT
OR
0x00000480
1
MPLS next protocol register
Page 295
INGR1_MPLS_FLOW_CFG
0x000004C0
8
0x00000040
MPLS flow configuration
Page 296
INGR1_IP1_NXT_PROTOCOL
0x000006C0
1
IP1 next protocol
Page 299
INGR1_IP1_FLOW_CFG
0x00000700
8
0x00000040
IP1 flow configuration
Page 303
INGR1_IP2_NXT_PROTOCOL
0x00000900
1
IP2 next protocol
Page 306
INGR1_IP2_FLOW_CFG
0x00000940
8
0x00000040
IP2 flow configuration
Page 310
INGR1_PTP_FLOW
0x00000B40
6
0x00000040
PTP flow configuration
Page 314
INGR1_PTP_IP_CHKSUM_CTL
0x00000CC0
1
IP checksum field control
Page 318
4.12.1
ETHERNET_COMPARATOR:INGR1_ETH1_NXT_PROTOCOL
Parent: Egress0 Ethernet Comparator
Instances: 1
Table 496 • Registers in INGR1_ETH1_NXT_PROTOCOL
Register Name
Instances and
Offset within
Address
Register Group Spacing
Description
INGR1_ETH1_NXT_PROTOCOL
0x00000000
1
Ethernet next protocol register Page 285
INGR1_ETH1_VLAN_TPID_CFG
0x00000004
1
VLAN TPID configuration
Page 286
INGR1_ETH1_TAG_MODE
0x00000008
1
Ethernet tag mode
Page 286
INGR1_ETH1_ETYPE_MATCH
0x0000000C
1
Ethertype match register
Page 286
4.12.1.1
Details
ETHERNET_COMPARATOR:INGR1_ETH1_NXT_PROTOCOL:INGR1_ETH1_N
XT_PROTOCOL
Parent: ETHERNET_COMPARATOR:INGR1_ETH1_NXT_PROTOCOL
Instances: 1
VMDS-10510 VSC8574-02 Datasheet Revision 4.2
285
Table 497 • Fields in INGR1_ETH1_NXT_PROTOCOL
Field Name
Access
Description
INGR1_ETH1_FRAME_SIG_OFF 20:16
SET
R/W
Frame signature offset. Points to the start of 0x00
the byte field in the Ethernet frame that will
be used for the frame signature.
INGR1_ETH1_NXT_COMPARATO 2:0
R
R/W
Points to the next comparator block after this 0x0
Ethernet block
0: Reserved
1: Ethernet comparator 2
2: IP/UDP/ACH comparator 1
3: IP/UDP/ACH comparator 2
4: MPLS comparator
5: PTP/OAM comparator
6,7: Reserved
4.12.1.2
Bit
Default
ETHERNET_COMPARATOR:INGR1_ETH1_NXT_PROTOCOL:INGR1_ETH1_VL
AN_TPID_CFG
Parent: ETHERNET_COMPARATOR:INGR1_ETH1_NXT_PROTOCOL
Instances: 1
Table 498 • Fields in INGR1_ETH1_VLAN_TPID_CFG
Field Name
Bit
Access
Description
Default
INGR1_ETH1_VLAN_TPID_CFG
31:16
R/W
Configurable VLAN TPID (S or B-tag)
0x88A8
4.12.1.3
ETHERNET_COMPARATOR:INGR1_ETH1_NXT_PROTOCOL:INGR1_ETH1_TA
G_MODE
Parent: ETHERNET_COMPARATOR:INGR1_ETH1_NXT_PROTOCOL
Instances: 1
Table 499 • Fields in INGR1_ETH1_TAG_MODE
Field Name
Bit
Access
Description
INGR1_ETH1_PBB_ENA
0
R/W
This bit enables the presence of PBB.
0x0
The I-tag match bits are programmed in the
ETH1_VLAN_TAG_RANGE registers. The
mask bits are programmed in the
ETH1_VLAN_TAG2 registers. A B-tag if
present is configured in the
ETH1_VLAN_TAG1 registers.
0: PBB not enabled
1: Always expect PBB, last tag is always an Itag
4.12.1.4
Default
ETHERNET_COMPARATOR:INGR1_ETH1_NXT_PROTOCOL:INGR1_ETH1_ET
YPE_MATCH
Parent: ETHERNET_COMPARATOR:INGR1_ETH1_NXT_PROTOCOL
VMDS-10510 VSC8574-02 Datasheet Revision 4.2
286
Instances: 1
Table 500 • Fields in INGR1_ETH1_ETYPE_MATCH
Field Name
Bit
Access
Description
INGR1_ETH1_ETYPE_MATCH
15:0
R/W
If the Ethertype/length field is an Ethertype, 0x0000
then this register is compared against the
value. If the field is a length, the length value
is not checked.
4.12.2
Default
ETHERNET_COMPARATOR:INGR1_ETH1_FLOW_CFG
Parent: Egress0 Ethernet Comparator
Instances: 8
Table 501 • Registers in INGR1_ETH1_FLOW_CFG
Register Name
Instances and
Address
Offset within
Register Group Spacing
Description
Details
INGR1_ETH1_FLOW_ENABLE
0x00000000
1
Ethernet flow enable
Page 287
INGR1_ETH1_MATCH_MODE
0x00000004
1
Ethernet protocol match mode Page 288
INGR1_ETH1_ADDR_MATCH_1
0x00000008
1
Ethernet address match part 1 Page 289
INGR1_ETH1_ADDR_MATCH_2
0x0000000C
1
Ethernet address match part 2 Page 289
INGR1_ETH1_VLAN_TAG_RANG 0x00000010
E_I_TAG
1
Ethernet VLAN tag range
match register
Page 289
INGR1_ETH1_VLAN_TAG1
0x00000014
1
VLAN tag 1 match/mask
Page 290
INGR1_ETH1_VLAN_TAG2_I_TA 0x00000018
G
1
Match/mask for VLAN tag 2 or Page 290
I-tag match
4.12.2.1
ETHERNET_COMPARATOR:INGR1_ETH1_FLOW_CFG:INGR1_ETH1_FLOW_
ENABLE
Parent: ETHERNET_COMPARATOR:INGR1_ETH1_FLOW_CFG
Instances: 1
Table 502 • Fields in INGR1_ETH1_FLOW_ENABLE
Field Name
Bit
Access
Description
Default
INGR1_ETH1_CHANNEL_MASK
9:8
R/W
Channel mask
0x0: Flow invalid
0x1: Flow valid for channel 0
0x2: Flow valid for channel 1
0x3: Flow valid for both channels
0x3
INGR1_ETH1_FLOW_ENABLE
0
R/W
Flow enable
0: Flow disabled
1: Flow enabled
0x0
VMDS-10510 VSC8574-02 Datasheet Revision 4.2
287
4.12.2.2
ETHERNET_COMPARATOR:INGR1_ETH1_FLOW_CFG:INGR1_ETH1_MATCH
_MODE
Parent: ETHERNET_COMPARATOR:INGR1_ETH1_FLOW_CFG
Instances: 1
Table 503 • Fields in INGR1_ETH1_MATCH_MODE
Field Name
Bit
Access
Description
Default
INGR1_ETH1_VLAN_TAG_MODE 13:12
R/W
VLAN tag mode configuration
0: VLAN range checking disabled
1: VLAN range checking on tag 1
2: VLAN range checking on tag 2 (not
supported with PBB)
3: Reserved
0x0
INGR1_ETH1_VLAN_TAG2_TYP
E
9
R/W
VLAN tag2 type
This register is only used if
ETH1_VLAN_VERIFY_ENA = 1
If PBB not enabled:
0: C tag (TPID of 0x8100)
1: S tag (match to CONF_VLAN_TPID)
If PBB enabled:
0,1: I tag (use range registers)
0x1
INGR1_ETH1_VLAN_TAG1_TYP
E
8
R/W
VLAN tag1 type
0x0
This register is only used if
ETH1_VLAN_VERIFY_ENA = 1
0: C tag (TPID of 0x8100)
1: S or B tag (match to CONF_VLAN_TPID)
INGR1_ETH1_VLAN_TAGS
7:6
R/W
VLAN tags
0x0
This register is only used if
ETH1_VLAN_VERIFY_ENA = 1
0: No VLAN tags (not valid for PBB)
1: 1 VLAN tag (for PBB this would be the Itag)
2: 2 VLAN tags (for PBB expect a B-tag and
an I-tag)
3: Reserved
INGR1_ETH1_VLAN_VERIFY_EN 4
A
R/W
Verify VLAN tags
0x0
0: Parse for VLAN tags, do not check values.
For PBB the I-tag is always checked.
1: Verify configured VLAN tag configuration.
INGR1_ETH1_ETHERTYPE_MO
DE
R/W
VLAN tag verification configuration
0x0
When checking for presence of SNAP/LLC
based upon ETH1_MATCH_MODE, this field
indicates if SNAP and 3-byte LLC is expected
to be present.
0: Only Ethernet type II supported, no
SNAP/LLC
1: Ethernet type II and Ethernet type I with
SNAP/LLC, determine if SNAP/LLC is
present or not. Type I always assumes that
SNAP/LLC is present.
0
VMDS-10510 VSC8574-02 Datasheet Revision 4.2
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4.12.2.3
ETHERNET_COMPARATOR:INGR1_ETH1_FLOW_CFG:INGR1_ETH1_ADDR_
MATCH_1
Parent: ETHERNET_COMPARATOR:INGR1_ETH1_FLOW_CFG
Instances: 1
Table 504 • Fields in INGR1_ETH1_ADDR_MATCH_1
Field Name
Bit
Access
Description
Default
INGR1_ETH1_ADDR_MATCH_1
31:0
R/W
First 32 bits of the address match value
0x00000000
4.12.2.4
ETHERNET_COMPARATOR:INGR1_ETH1_FLOW_CFG:INGR1_ETH1_ADDR_
MATCH_2
Parent: ETHERNET_COMPARATOR:INGR1_ETH1_FLOW_CFG
Instances: 1
Table 505 • Fields in INGR1_ETH1_ADDR_MATCH_2
Field Name
Bit
Access
Description
INGR1_ETH1_ADDR_MATCH_M
ODE
22:20
R/W
Selects how the addresses are matched.
0x1
One-hot encoded. Multiple bits can be set at
once.
0: Full 48-bit address match
1: Match any unicast address
2: Match any muliticast address
INGR1_ETH1_ADDR_MATCH_SE 17:16
LECT
R/W
Selects which address to match
0: Match the destination address
1: Match the source address
2: Match either the source of destination
address
3: Reserved
0x0
INGR1_ETH1_ADDR_MATCH_2
R/W
Last 16 bits of the Ethernet address match
field
0x0000
4.12.2.5
15:0
Default
ETHERNET_COMPARATOR:INGR1_ETH1_FLOW_CFG:INGR1_ETH1_VLAN_T
AG_RANGE_I_TAG
Parent: ETHERNET_COMPARATOR:INGR1_ETH1_FLOW_CFG
Instances: 1
Table 506 • Fields in INGR1_ETH1_VLAN_TAG_RANGE_I_TAG
Field Name
Bit
INGR1_ETH1_VLAN_TAG_RANG 27:16
E_UPPER
Access
Description
R/W
If PBB mode is not enabled, then this register 0xFFF
contains the upper range of the VLAN tag
range match.
If PBB mode is enabled, then this register
contains the upper 12 bits of the I-tag.
VMDS-10510 VSC8574-02 Datasheet Revision 4.2
Default
289
Table 506 • Fields in INGR1_ETH1_VLAN_TAG_RANGE_I_TAG (continued)
Field Name
Bit
INGR1_ETH1_VLAN_TAG_RANG 11:0
E_LOWER
4.12.2.6
Access
Description
Default
R/W
If PBB mode is not enabled, then this register 0x000
contains the lower range of the VLAN tag
range match.
If PBB mode is enabled, then this register
contains the lower 12 bits of the I-tag.
ETHERNET_COMPARATOR:INGR1_ETH1_FLOW_CFG:INGR1_ETH1_VLAN_T
AG1
Parent: ETHERNET_COMPARATOR:INGR1_ETH1_FLOW_CFG
Instances: 1
Table 507 • Fields in INGR1_ETH1_VLAN_TAG1
Field Name
Access
Description
Default
INGR1_ETH1_VLAN_TAG1_MAS 27:16
K
R/W
Mask value for VLAN tag 1
0xFFF
INGR1_ETH1_VLAN_TAG1_MAT 11:0
CH
R/W
Match value for the first VLAN tag
0x000
4.12.2.7
Bit
ETHERNET_COMPARATOR:INGR1_ETH1_FLOW_CFG:INGR1_ETH1_VLAN_T
AG2_I_TAG
Parent: ETHERNET_COMPARATOR:INGR1_ETH1_FLOW_CFG
Instances: 1
Table 508 • Fields in INGR1_ETH1_VLAN_TAG2_I_TAG
Field Name
Access
Description
INGR1_ETH1_VLAN_TAG2_MAS 27:16
K
R/W
When PBB is not enabled, the mask field for 0xFFF
VLAN tag 2.
When PBB is enabled, the upper 12 bits of
the I-tag mask.
INGR1_ETH1_VLAN_TAG2_MAT 11:0
CH
R/W
When PBB is not enabled, the match field for 0x000
VLAN Tag 2.
When PBB is enabled, the lower 12 bits of
the I-tag mask field.
4.12.3
Bit
Default
ETHERNET_COMPARATOR:INGR1_ETH2_NXT_PROTOCOL
Parent: Egress0 Ethernet Comparator
Instances: 1
VMDS-10510 VSC8574-02 Datasheet Revision 4.2
290
Table 509 • Registers in INGR1_ETH2_NXT_PROTOCOL
Register Name
Instances and
Offset within
Address
Register Group Spacing
Description
INGR1_ETH2_NXT_PROTOCOL
0x00000000
1
Ethernet next protocol register Page 291
INGR1_ETH2_VLAN_TPID_CFG
0x00000004
1
VLAN TPID configuration
Page 291
INGR1_ETH2_ETYPE_MATCH
0x00000008
1
Ethertype match register
Page 291
4.12.3.1
Details
ETHERNET_COMPARATOR:INGR1_ETH2_NXT_PROTOCOL:INGR1_ETH2_N
XT_PROTOCOL
Parent: ETHERNET_COMPARATOR:INGR1_ETH2_NXT_PROTOCOL
Instances: 1
Table 510 • Fields in INGR1_ETH2_NXT_PROTOCOL
Field Name
Access
Description
INGR1_ETH2_FRAME_SIG_OFF 20:16
SET
R/W
Frame signature offset. Points to the start of 0x00
the byte field in the Ethernet frame that will
be used for the frame signature.
INGR1_ETH2_NXT_COMPARATO 2:0
R
R/W
Points to the next comparator block after this 0x0
Ethernet block. If this comparator block is not
used, this field must be set to 0.
0: Comparator block not used
1: Ethernet comparator 2
2: IP/UDP/ACH comparator 1
3: IP/UDP/ACH comparator 2
4: MPLS comparator
5: PTP/OAM comparator
6,7: Reserved
4.12.3.2
Bit
Default
ETHERNET_COMPARATOR:INGR1_ETH2_NXT_PROTOCOL:INGR1_ETH2_VL
AN_TPID_CFG
Parent: ETHERNET_COMPARATOR:INGR1_ETH2_NXT_PROTOCOL
Instances: 1
Table 511 • Fields in INGR1_ETH2_VLAN_TPID_CFG
Field Name
Bit
Access
Description
Default
INGR1_ETH2_VLAN_TPID_CFG
31:16
R/W
Configurable S-tag TPID
0x88A8
4.12.3.3
ETHERNET_COMPARATOR:INGR1_ETH2_NXT_PROTOCOL:INGR1_ETH2_ET
YPE_MATCH
Parent: ETHERNET_COMPARATOR:INGR1_ETH2_NXT_PROTOCOL
Instances: 1
VMDS-10510 VSC8574-02 Datasheet Revision 4.2
291
Table 512 • Fields in INGR1_ETH2_ETYPE_MATCH
Field Name
Bit
Access
Description
INGR1_ETH2_ETYPE_MATCH
15:0
R/W
If the Ethertype/length field is an Ethertype, 0x0000
then this register is compared against the
value. If the field is a length, the length value
is not checked.
4.12.4
Default
ETHERNET_COMPARATOR:INGR1_ETH2_FLOW_CFG
Parent: Egress0 Ethernet Comparator
Instances: 8
Table 513 • Registers in INGR1_ETH2_FLOW_CFG
Register Name
Instances and
Offset within
Address
Register Group Spacing
Description
Details
INGR1_ETH2_FLOW_ENABLE
0x00000000
1
Ethernet flow enable
Page 292
INGR1_ETH2_MATCH_MODE
0x00000004
1
Ethernet protocol match mode Page 293
INGR1_ETH2_ADDR_MATCH_1
0x00000008
1
Ethernet address match part 1 Page 293
INGR1_ETH2_ADDR_MATCH_2
0x0000000C
1
Ethernet address match part 2 Page 294
INGR1_ETH2_VLAN_TAG_RANG 0x00000010
E_I_TAG
1
Ethernet VLAN tag range
match register
Page 294
INGR1_ETH2_VLAN_TAG1
0x00000014
1
VLAN tag 1 match/mask
Page 294
INGR1_ETH2_VLAN_TAG2_I_TA 0x00000018
G
1
Match/mask for VLAN tag 2 or Page 295
I-tag match
4.12.4.1
ETHERNET_COMPARATOR:INGR1_ETH2_FLOW_CFG:INGR1_ETH2_FLOW_
ENABLE
Parent: ETHERNET_COMPARATOR:INGR1_ETH2_FLOW_CFG
Instances: 1
Table 514 • Fields in INGR1_ETH2_FLOW_ENABLE
Field Name
Bit
Access
Description
Default
INGR1_ETH2_CHANNEL_MASK
9:8
R/W
Channel mask
0x0: Flow invalid
0x1: Flow valid for channel 0
0x2: Flow valid for channel 1
0x3: Flow valid for both channels
0x3
INGR1_ETH2_FLOW_ENABLE
0
R/W
Flow enable.
If this comparator block is not used, all flow
enable bits must be set to 0.
0: Flow disabled
1: Flow enabled
0x0
VMDS-10510 VSC8574-02 Datasheet Revision 4.2
292
4.12.4.2
ETHERNET_COMPARATOR:INGR1_ETH2_FLOW_CFG:INGR1_ETH2_MATCH
_MODE
Parent: ETHERNET_COMPARATOR:INGR1_ETH2_FLOW_CFG
Instances: 1
Table 515 • Fields in INGR1_ETH2_MATCH_MODE
Field Name
Access
Description
Default
INGR1_ETH2_VLAN_TAG_MODE 13:12
R/W
VLAN tag mode configuration
0: VLAN range checking disabled
1: VLAN range checking on tag 1
2: VLAN range checking on tag 2 (not
supported with PBB)
3: Reserved
0x0
INGR1_ETH2_VLAN_TAG2_TYP
E
9
R/W
VLAN tag2 type
This register is only used if
ETH1_VLAN_VERIFY_ENA = 1
0: C tag (TPID of 0x8100)
1: S tag (match to CONF_VLAN_TPID)
0x1
INGR1_ETH2_VLAN_TAG1_TYP
E
8
R/W
VLAN tag1 type
0x0
This register is only used if
ETH1_VLAN_VERIFY_ENA = 1
0: C tag (TPID of 0x8100)
1: S or B tag (match to CONF_VLAN_TPID)
INGR1_ETH2_VLAN_TAGS
7:6
R/W
VLAN tags
This register is only used if
ETH2_VLAN_VERIFY_ENA = 1
0: No VLAN tags
1: 1 VLAN tag
2: 2 VLAN tags
3: Reserved
INGR1_ETH2_VLAN_VERIFY_EN 4
A
R/W
0x0
Verify VLAN tags
0: Parse for VLAN tags, do not check values.
1: Verify configured VLAN tag configuration.
INGR1_ETH2_ETHERTYPE_MO
DE
R/W
VLAN tag verification configuration
0x0
When checking for presence of SNAP/LLC
based upon ETH1_MATCH_MODE, this field
indicates if SNAP and 3-byte LLC is expected
to be present.
0: Only Ethernet type II supported, no
SNAP/LLC
1: Ethernet type II and Ethernet type I with
SNAP/LLC, determine if SNAP/LLC is
present or not. Type I always assumes that
SNAP/LLC is present.
4.12.4.3
Bit
0
0x0
ETHERNET_COMPARATOR:INGR1_ETH2_FLOW_CFG:INGR1_ETH2_ADDR_
MATCH_1
Parent: ETHERNET_COMPARATOR:INGR1_ETH2_FLOW_CFG
Instances: 1
VMDS-10510 VSC8574-02 Datasheet Revision 4.2
293
Table 516 • Fields in INGR1_ETH2_ADDR_MATCH_1
Field Name
Bit
Access
Description
Default
INGR1_ETH2_ADDR_MATCH_1
31:0
R/W
First 32 bits of the address match value
0x00000000
4.12.4.4
ETHERNET_COMPARATOR:INGR1_ETH2_FLOW_CFG:INGR1_ETH2_ADDR_
MATCH_2
Parent: ETHERNET_COMPARATOR:INGR1_ETH2_FLOW_CFG
Instances: 1
Table 517 • Fields in INGR1_ETH2_ADDR_MATCH_2
Field Name
Bit
Access
Description
INGR1_ETH2_ADDR_MATCH_M
ODE
22:20
R/W
Selects how the addresses are matched.
0x1
One-hot encoded. Multiple bits can be set at
once.
0: Full 48-bit address match
1: Match any unicast address
2: Match any muliticast address
INGR1_ETH2_ADDR_MATCH_SE 17:16
LECT
R/W
Selects which address to match
0: Match the destination address
1: Match the source address
2: Match either the source of destination
address
3: Reserved
0x0
INGR1_ETH2_ADDR_MATCH_2
R/W
Last 16 bits of the Ethernet address match
field
0x0000
4.12.4.5
15:0
Default
ETHERNET_COMPARATOR:INGR1_ETH2_FLOW_CFG:INGR1_ETH2_VLAN_T
AG_RANGE_I_TAG
Parent: ETHERNET_COMPARATOR:INGR1_ETH2_FLOW_CFG
Instances: 1
Table 518 • Fields in INGR1_ETH2_VLAN_TAG_RANGE_I_TAG
Field Name
Access
Description
Default
INGR1_ETH2_VLAN_TAG_RANG 27:16
E_UPPER
R/W
Contains the upper range of the VLAN tag
range match
0xFFF
INGR1_ETH2_VLAN_TAG_RANG 11:0
E_LOWER
R/W
Contains the lower range of the VLAN tag
range match
0x000
4.12.4.6
Bit
ETHERNET_COMPARATOR:INGR1_ETH2_FLOW_CFG:INGR1_ETH2_VLAN_T
AG1
Parent: ETHERNET_COMPARATOR:INGR1_ETH2_FLOW_CFG
Instances: 1
VMDS-10510 VSC8574-02 Datasheet Revision 4.2
294
Table 519 • Fields in INGR1_ETH2_VLAN_TAG1
Field Name
Access
Description
Default
INGR1_ETH2_VLAN_TAG1_MAS 27:16
K
R/W
Mask value for VLAN tag 1
0xFFF
INGR1_ETH2_VLAN_TAG1_MAT 11:0
CH
R/W
Match value for the first VLAN tag
0x000
4.12.4.7
Bit
ETHERNET_COMPARATOR:INGR1_ETH2_FLOW_CFG:INGR1_ETH2_VLAN_T
AG2_I_TAG
Parent: ETHERNET_COMPARATOR:INGR1_ETH2_FLOW_CFG
Instances: 1
Table 520 • Fields in INGR1_ETH2_VLAN_TAG2_I_TAG
Field Name
Access
Description
Default
INGR1_ETH2_VLAN_TAG2_MAS 27:16
K
R/W
Mask field for VLAN tag 2
0xFFF
INGR1_ETH2_VLAN_TAG2_MAT 11:0
CH
R/W
Match field for VLAN Tag 2
0x000
4.12.5
Bit
ETHERNET_COMPARATOR:INGR1_MPLS_NXT_COMPARATOR
Parent: Egress0 Ethernet Comparator
Instances: 1
Table 521 • Registers in INGR1_MPLS_NXT_COMPARATOR
Instances and
Offset within
Address
Register Group Spacing
Register Name
INGR1_MPLS_NXT_COMPARAT
OR
4.12.5.1
0x00000000
1
Description
Details
MPLS next protocol
comparator register
Page 295
ETHERNET_COMPARATOR:INGR1_MPLS_NXT_COMPARATOR:INGR1_MPL
S_NXT_COMPARATOR
Parent: ETHERNET_COMPARATOR:INGR1_MPLS_NXT_COMPARATOR
Instances: 1
VMDS-10510 VSC8574-02 Datasheet Revision 4.2
295
Table 522 • Fields in INGR1_MPLS_NXT_COMPARATOR
Field Name
Bit
Access
Description
INGR1_MPLS_CTL_WORD
16
R/W
Indicates the presence of a control word after 0x0
the last label. The first 4 bits of the control
word are always 0.
0: No control word after the last label
1: Control word after the last label
INGR1_MPLS_NXT_COMPARAT
OR
2:0
R/W
Points to the next comparator stage. If this
0x0
comparator block is not used, this field must
be set to 0.
0: Comparator block not used.
1: Ethernet comparator 2
2: IP/UDP/ACH comparator 1
3: IP/UDP/ACH comparator 2
4: Reserved
5: PTP/OAM comparator
6,7: Reserved
4.12.6
Default
ETHERNET_COMPARATOR:INGR1_MPLS_FLOW_CFG
Parent: Egress0 Ethernet Comparator
Instances: 8
Table 523 • Registers in INGR1_MPLS_FLOW_CFG
Register Name
Instances and
Offset within
Address
Register Group Spacing
Description
Details
INGR1_MPLS_FLOW_CONTROL 0x00000000
1
MPLS flow control register
Page 297
INGR1_MPLS_LABEL_RANGE_L 0x00000008
OWER_0
1
MPLS label 0 match range
lower value
Page 297
INGR1_MPLS_LABEL_RANGE_U 0x0000000C
PPER_0
1
MPLS label 0 match range
upper value
Page 297
INGR1_MPLS_LABEL_RANGE_L 0x00000010
OWER_1
1
MPLS label 1 match range
lower value
Page 298
INGR1_MPLS_LABEL_RANGE_U 0x00000014
PPER_1
1
MPLS label 1 match range
upper value
Page 298
INGR1_MPLS_LABEL_RANGE_L 0x00000018
OWER_2
1
MPLS label 2 match range
lower value
Page 298
INGR1_MPLS_LABEL_RANGE_U 0x0000001C
PPER_2
1
MPLS label 2 match range
upper value
Page 298
INGR1_MPLS_LABEL_RANGE_L 0x00000020
OWER_3
1
MPLS label 3 match range
lower value
Page 299
INGR1_MPLS_LABEL_RANGE_U 0x00000024
PPER_3
1
MPLS label 3 match range
upper value
Page 299
VMDS-10510 VSC8574-02 Datasheet Revision 4.2
296
4.12.6.1
ETHERNET_COMPARATOR:INGR1_MPLS_FLOW_CFG:INGR1_MPLS_FLOW
_CONTROL
Parent: ETHERNET_COMPARATOR:INGR1_MPLS_FLOW_CFG
Instances: 1
Table 524 • Fields in INGR1_MPLS_FLOW_CONTROL
Field Name
Access
Description
Default
INGR1_MPLS_CHANNEL_MASK 25:24
R/W
MPLS channel mask selector
0x0: Flow invalid
0x1: Flow valid for channel 0
0x2: Flow valid for channel 1
0x3: Flow valid for both channels
0x3
INGR1_MPLS_STACK_DEPTH
19:16
R/W
Stack depth configuration
Defines the allowable stack depths for
searches. The direction that the stack is
referenced is determined by the setting of
MPLS_REF_PNT. For each bit set, the
following table maps bits to stack depths:
0: Stack allowed to be 1 label deep
1: Stack allowed to be 2 labels deep
2: Stack allowed to be 3 labels deep
3: Stack allowed to be 4 labels deep
0x0
INGR1_MPLS_REF_PNT
4
R/W
Search direction for label matching
0x0
0: All searching is performed starting from the
top of the stack
1: All searching is performed from the end of
the stack
INGR1_MPLS_FLOW_ENA
0
R/W
Flow enable.
If this comparator block is not used, all flow
enable bits must be set to 0.
0: Flow is disabled
1: Flow is enabled
4.12.6.2
Bit
0x0
ETHERNET_COMPARATOR:INGR1_MPLS_FLOW_CFG:INGR1_MPLS_LABEL
_RANGE_LOWER_0
Parent: ETHERNET_COMPARATOR:INGR1_MPLS_FLOW_CFG
Instances: 1
Table 525 • Fields in INGR1_MPLS_LABEL_RANGE_LOWER_0
Field Name
Bit
INGR1_MPLS_LABEL_RANGE_L 19:0
OWER_0
4.12.6.3
Access
Description
Default
R/W
Lower value for label 0 match range
0x00000
ETHERNET_COMPARATOR:INGR1_MPLS_FLOW_CFG:INGR1_MPLS_LABEL
_RANGE_UPPER_0
Parent: ETHERNET_COMPARATOR:INGR1_MPLS_FLOW_CFG
Instances: 1
VMDS-10510 VSC8574-02 Datasheet Revision 4.2
297
Table 526 • Fields in INGR1_MPLS_LABEL_RANGE_UPPER_0
Field Name
Bit
INGR1_MPLS_LABEL_RANGE_U 19:0
PPER_0
4.12.6.4
Access
Description
Default
R/W
Upper value for label 0 match range
0xFFFFF
ETHERNET_COMPARATOR:INGR1_MPLS_FLOW_CFG:INGR1_MPLS_LABEL
_RANGE_LOWER_1
Parent: ETHERNET_COMPARATOR:INGR1_MPLS_FLOW_CFG
Instances: 1
Table 527 • Fields in INGR1_MPLS_LABEL_RANGE_LOWER_1
Field Name
Bit
INGR1_MPLS_LABEL_RANGE_L 19:0
OWER_1
4.12.6.5
Access
Description
Default
R/W
Lower value for label 1 match range
0x00000
ETHERNET_COMPARATOR:INGR1_MPLS_FLOW_CFG:INGR1_MPLS_LABEL
_RANGE_UPPER_1
Parent: ETHERNET_COMPARATOR:INGR1_MPLS_FLOW_CFG
Instances: 1
Table 528 • Fields in INGR1_MPLS_LABEL_RANGE_UPPER_1
Field Name
Bit
INGR1_MPLS_LABEL_RANGE_U 19:0
PPER_1
4.12.6.6
Access
Description
Default
R/W
Upper value for label 1 match range
0xFFFFF
ETHERNET_COMPARATOR:INGR1_MPLS_FLOW_CFG:INGR1_MPLS_LABEL
_RANGE_LOWER_2
Parent: ETHERNET_COMPARATOR:INGR1_MPLS_FLOW_CFG
Instances: 1
Table 529 • Fields in INGR1_MPLS_LABEL_RANGE_LOWER_2
Field Name
Bit
INGR1_MPLS_LABEL_RANGE_L 19:0
OWER_2
4.12.6.7
Access
Description
Default
R/W
Lower value for label 2 match range
0x00000
ETHERNET_COMPARATOR:INGR1_MPLS_FLOW_CFG:INGR1_MPLS_LABEL
_RANGE_UPPER_2
Parent: ETHERNET_COMPARATOR:INGR1_MPLS_FLOW_CFG
Instances: 1
VMDS-10510 VSC8574-02 Datasheet Revision 4.2
298
Table 530 • Fields in INGR1_MPLS_LABEL_RANGE_UPPER_2
Field Name
Bit
INGR1_MPLS_LABEL_RANGE_U 19:0
PPER_2
4.12.6.8
Access
Description
Default
R/W
Upper value for label 2 match range
0xFFFFF
ETHERNET_COMPARATOR:INGR1_MPLS_FLOW_CFG:INGR1_MPLS_LABEL
_RANGE_LOWER_3
Parent: ETHERNET_COMPARATOR:INGR1_MPLS_FLOW_CFG
Instances: 1
Table 531 • Fields in INGR1_MPLS_LABEL_RANGE_LOWER_3
Field Name
Bit
INGR1_MPLS_LABEL_RANGE_L 19:0
OWER_3
4.12.6.9
Access
Description
Default
R/W
Lower value for label 3 match range
0x00000
ETHERNET_COMPARATOR:INGR1_MPLS_FLOW_CFG:INGR1_MPLS_LABEL
_RANGE_UPPER_3
Parent: ETHERNET_COMPARATOR:INGR1_MPLS_FLOW_CFG
Instances: 1
Table 532 • Fields in INGR1_MPLS_LABEL_RANGE_UPPER_3
Field Name
Bit
INGR1_MPLS_LABEL_RANGE_U 19:0
PPER_3
4.12.7
Access
Description
Default
R/W
Upper value for label 3 match range
0xFFFFF
ETHERNET_COMPARATOR:INGR1_IP1_NXT_PROTOCOL
Parent: Egress0 Ethernet Comparator
Instances: 1
Table 533 • Registers in INGR1_IP1_NXT_PROTOCOL
Register Name
Instances and
Offset within
Address
Register Group Spacing
Description
Details
INGR1_IP1_NXT_COMPARATOR 0x00000000
1
IP next comparator control
register
Page 300
INGR1_IP1_MODE
0x00000004
1
IP comparator mode
Page 300
INGR1_IP1_PROT_MATCH_1
0x00000008
1
IP match register set 1
Page 301
INGR1_IP1_PROT_MATCH_2_UP 0x0000000C
PER
1
Upper portion of match
register 2
Page 301
VMDS-10510 VSC8574-02 Datasheet Revision 4.2
299
Table 533 • Registers in INGR1_IP1_NXT_PROTOCOL (continued)
Instances and
Offset within
Address
Register Group Spacing
Register Name
Description
Details
INGR1_IP1_PROT_MATCH_2_LO 0x00000010
WER
1
Lower portion of match
register 2
Page 301
INGR1_IP1_PROT_MASK_2_UPP 0x00000014
ER
1
Upper portion of match mask
register 2
Page 302
INGR1_IP1_PROT_MASK_2_LO
WER
0x00000018
1
Lower portion of match mask
register 2
Page 302
INGR1_IP1_PROT_OFFSET_2
0x0000001C
1
IP match offset register set 2
Page 302
INGR1_IP1_UDP_CHKSUM_CFG 0x00000020
1
IP/UDP checksum control
register
Page 302
4.12.7.1
ETHERNET_COMPARATOR:INGR1_IP1_NXT_PROTOCOL:INGR1_IP1_NXT_C
OMPARATOR
Parent: ETHERNET_COMPARATOR:INGR1_IP1_NXT_PROTOCOL
Instances: 1
Table 534 • Fields in INGR1_IP1_NXT_COMPARATOR
Field Name
Bit
Access
Description
INGR1_IP1_NXT_PROTOCOL
15:8
R/W
Number of bytes in this header, points to the 0x00
beginning of the next protocol.
R/W
Points to the next comparator stage. If this
0x0
comparator block is not used, this field must
be set to 0.
0: Comparator block not used
1: Reserved
2: Reserved
3: IP/UDP/ACH comparator 2
4: Reserved
5: PTP/OAM comparator
6,7: Reserved
INGR1_IP1_NXT_COMPARATOR 2:0
4.12.7.2
Default
ETHERNET_COMPARATOR:INGR1_IP1_NXT_PROTOCOL:INGR1_IP1_MODE
Parent: ETHERNET_COMPARATOR:INGR1_IP1_NXT_PROTOCOL
Instances: 1
Table 535 • Fields in INGR1_IP1_MODE
Field Name
Bit
Access
Description
Default
INGR1_IP1_FLOW_OFFSET
12:8
R/W
Points to the source address field in the IP
frame. Use 12 for IPv4 and 8 for IPv6.
0x0C
VMDS-10510 VSC8574-02 Datasheet Revision 4.2
300
Table 535 • Fields in INGR1_IP1_MODE (continued)
Field Name
Bit
Access
Description
Default
INGR1_IP1_MODE
1:0
R/W
IP mode
0: IPv4
1: IPv6
2: Other protocol, 32-bit address match
3: Other protocol, 128-bit address match
0x0
4.12.7.3
ETHERNET_COMPARATOR:INGR1_IP1_NXT_PROTOCOL:INGR1_IP1_PROT_
MATCH_1
Parent: ETHERNET_COMPARATOR:INGR1_IP1_NXT_PROTOCOL
Instances: 1
Table 536 • Fields in INGR1_IP1_PROT_MATCH_1
Field Name
Bit
Access
Description
Default
INGR1_IP1_PROT_OFFSET_1
20:16
R/W
Points to the start of this match field relative
to the first byte of this protocol
0x00
INGR1_IP1_PROT_MASK_1
15:8
R/W
Mask field for IP_PROT_MATCH_1
0x00
INGR1_IP1_PROT_MATCH_1
7:0
R/W
8-bit match field
0x00
4.12.7.4
ETHERNET_COMPARATOR:INGR1_IP1_NXT_PROTOCOL:INGR1_IP1_PROT_
MATCH_2_UPPER
Parent: ETHERNET_COMPARATOR:INGR1_IP1_NXT_PROTOCOL
Instances: 1
Table 537 • Fields in INGR1_IP1_PROT_MATCH_2_UPPER
Field Name
Bit
INGR1_IP1_PROT_MATCH_2_UP 31:0
PER
4.12.7.5
Access
Description
Default
R/W
64-bit match register for advancing to the
next protocol, upper portion
0x00000000
ETHERNET_COMPARATOR:INGR1_IP1_NXT_PROTOCOL:INGR1_IP1_PROT_
MATCH_2_LOWER
Parent: ETHERNET_COMPARATOR:INGR1_IP1_NXT_PROTOCOL
Instances: 1
Table 538 • Fields in INGR1_IP1_PROT_MATCH_2_LOWER
Field Name
Bit
INGR1_IP1_PROT_MATCH_2_LO 31:0
WER
Access
Description
Default
R/W
64-bit match register for advancing to the
next protocol, lower portion
0x00000000
VMDS-10510 VSC8574-02 Datasheet Revision 4.2
301
4.12.7.6
ETHERNET_COMPARATOR:INGR1_IP1_NXT_PROTOCOL:INGR1_IP1_PROT_
MASK_2_UPPER
Parent: ETHERNET_COMPARATOR:INGR1_IP1_NXT_PROTOCOL
Instances: 1
Table 539 • Fields in INGR1_IP1_PROT_MASK_2_UPPER
Field Name
Bit
INGR1_IP1_PROT_MASK_2_UPP 31:0
ER
4.12.7.7
Access
Description
R/W
Default
0x00000000
ETHERNET_COMPARATOR:INGR1_IP1_NXT_PROTOCOL:INGR1_IP1_PROT_
MASK_2_LOWER
Parent: ETHERNET_COMPARATOR:INGR1_IP1_NXT_PROTOCOL
Instances: 1
Table 540 • Fields in INGR1_IP1_PROT_MASK_2_LOWER
Field Name
Bit
Access
INGR1_IP1_PROT_MASK_2_LO
WER
31:0
R/W
4.12.7.8
Description
Default
0x00000000
ETHERNET_COMPARATOR:INGR1_IP1_NXT_PROTOCOL:INGR1_IP1_PROT_
OFFSET_2
Parent: ETHERNET_COMPARATOR:INGR1_IP1_NXT_PROTOCOL
Instances: 1
Table 541 • Fields in INGR1_IP1_PROT_OFFSET_2
Field Name
Bit
Access
Description
INGR1_IP1_PROT_OFFSET_2
6:0
R/W
Points to the start of match field 2 relative to 0x00
the first byte of this protocol
4.12.7.9
Default
ETHERNET_COMPARATOR:INGR1_IP1_NXT_PROTOCOL:INGR1_IP1_UDP_C
HKSUM_CFG
Parent: ETHERNET_COMPARATOR:INGR1_IP1_NXT_PROTOCOL
Instances: 1
VMDS-10510 VSC8574-02 Datasheet Revision 4.2
302
Table 542 • Fields in INGR1_IP1_UDP_CHKSUM_CFG
Field Name
Access
Description
Default
INGR1_IP1_UDP_CHKSUM_OFF 15:8
SET
R/W
Pointer to the IP/UDP checksum field FOR
IPv4 frames or to the pad bytes of a
IPv6/UDP frame. For IPv4, it points to the
bytes that will be cleared. For IPv6, it points
to the bytes that will be updated to fix the
CRC.
0x00
INGR1_IP1_UDP_CHKSUM_WID 5:4
TH
R/W
Specifies the length of the checksum field in 0x2
bytes
INGR1_IP1_UDP_CHKSUM_UPD 1
ATE_ENA
R/W
0x0
This bit and
IP_UDP_CHKSUM_CLEAR_ENA CANNOT
be set together
0: No pad byte field update
1: Update the pad bytes at the end of the
frame
INGR1_IP1_UDP_CHKSUM_CLE 0
AR_ENA
R/W
This bit and
IP_UDP_CHKSUM_UPDATE_ENA
CANNOT be set together
0: Do not clear the checksum
1: Clear the UDP checksum field in an IPv4
frame
4.12.8
Bit
0x0
ETHERNET_COMPARATOR:INGR1_IP1_FLOW_CFG
Parent: Egress0 Ethernet Comparator
Instances: 8
Table 543 • Registers in INGR1_IP1_FLOW_CFG
Register Name
Instances and
Offset within
Address
Register Group Spacing
Description
Details
INGR1_IP1_FLOW_ENA
0x00000000
1
IP flow enable register
Page 304
INGR1_IP1_FLOW_MATCH_UPP 0x00000004
ER
1
Upper portion of the IP flow
match register
Page 304
INGR1_IP1_FLOW_MATCH_UPP 0x00000008
ER_MID
1
Upper mid portion of the IP
flow match register
Page 304
INGR1_IP1_FLOW_MATCH_LOW 0x0000000C
ER_MID
1
Lower mid portion of the IP
flow match register
Page 305
INGR1_IP1_FLOW_MATCH_LOW 0x00000010
ER
1
Lower portion of the IP flow
match register
Page 305
INGR1_IP1_FLOW_MASK_UPPE 0x00000014
R
1
Upper portion of the IP flow
match mask register
Page 305
INGR1_IP1_FLOW_MASK_UPPE 0x00000018
R_MID
1
Upper mid portion of the IP
flow match mask register
Page 305
INGR1_IP1_FLOW_MASK_LOWE 0x0000001C
R_MID
1
Lower mid portion of the IP
flow match mask register
Page 306
VMDS-10510 VSC8574-02 Datasheet Revision 4.2
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Table 543 • Registers in INGR1_IP1_FLOW_CFG (continued)
Register Name
Instances and
Offset within
Address
Register Group Spacing
INGR1_IP1_FLOW_MASK_LOWE 0x00000020
R
4.12.8.1
1
Description
Details
Lower portion of the IP flow
match mask register
Page 306
ETHERNET_COMPARATOR:INGR1_IP1_FLOW_CFG:INGR1_IP1_FLOW_ENA
Parent: ETHERNET_COMPARATOR:INGR1_IP1_FLOW_CFG
Instances: 1
Table 544 • Fields in INGR1_IP1_FLOW_ENA
Field Name
Access
Description
Default
INGR1_IP1_FLOW_MATCH_MOD 9:8
E
R/W
Match mode
0: Match on source address
1: Match on destination address
2: Match on either source or destination
address
3: Reserved
0x0
INGR1_IP1_CHANNEL_MASK
5:4
R/W
Channel mask
0x0: Flow invalid
0x1: Flow valid for channel 0
0x2: Flow valid for channel 1
0x3: Flow valid for both channels
0x3
INGR1_IP1_FLOW_ENA
0
R/W
Flow enable. If this comparator block is not
used, all flow enable bits must be set to 0.
0: Flow disabled
1: Flow enabled
0x0
4.12.8.2
Bit
ETHERNET_COMPARATOR:INGR1_IP1_FLOW_CFG:INGR1_IP1_FLOW_MAT
CH_UPPER
Parent: ETHERNET_COMPARATOR:INGR1_IP1_FLOW_CFG
Instances: 1
Table 545 • Fields in INGR1_IP1_FLOW_MATCH_UPPER
Field Name
Bit
INGR1_IP1_FLOW_MATCH_UPP 31:0
ER
4.12.8.3
Access
Description
Default
R/W
Match field for either the entire 32-bit
0x00000000
selected address for IPv4 or the upper 32 bits
of the selected address for IPv6
ETHERNET_COMPARATOR:INGR1_IP1_FLOW_CFG:INGR1_IP1_FLOW_MAT
CH_UPPER_MID
Parent: ETHERNET_COMPARATOR:INGR1_IP1_FLOW_CFG
Instances: 1
VMDS-10510 VSC8574-02 Datasheet Revision 4.2
304
Table 546 • Fields in INGR1_IP1_FLOW_MATCH_UPPER_MID
Field Name
Bit
INGR1_IP1_FLOW_MATCH_UPP 31:0
ER_MID
4.12.8.4
Access
Description
Default
R/W
Match bits for the upper middle 32 bits of the 0x00000000
IPv6 address
ETHERNET_COMPARATOR:INGR1_IP1_FLOW_CFG:INGR1_IP1_FLOW_MAT
CH_LOWER_MID
Parent: ETHERNET_COMPARATOR:INGR1_IP1_FLOW_CFG
Instances: 1
Table 547 • Fields in INGR1_IP1_FLOW_MATCH_LOWER_MID
Field Name
Bit
INGR1_IP1_FLOW_MATCH_LOW 31:0
ER_MID
4.12.8.5
Access
Description
Default
R/W
Match bits for the lower middle 32 bits of the 0x00000000
IPv6 address
ETHERNET_COMPARATOR:INGR1_IP1_FLOW_CFG:INGR1_IP1_FLOW_MAT
CH_LOWER
Parent: ETHERNET_COMPARATOR:INGR1_IP1_FLOW_CFG
Instances: 1
Table 548 • Fields in INGR1_IP1_FLOW_MATCH_LOWER
Field Name
Bit
INGR1_IP1_FLOW_MATCH_LOW 31:0
ER
4.12.8.6
Access
Description
Default
R/W
Match bits for the lower 32 bits of the IPv6
address
0x00000000
ETHERNET_COMPARATOR:INGR1_IP1_FLOW_CFG:INGR1_IP1_FLOW_MAS
K_UPPER
Parent: ETHERNET_COMPARATOR:INGR1_IP1_FLOW_CFG
Instances: 1
Table 549 • Fields in INGR1_IP1_FLOW_MASK_UPPER
Field Name
Bit
INGR1_IP1_FLOW_MASK_UPPE 31:0
R
4.12.8.7
Access
Description
Default
R/W
Address mask for the IP address
0x00000000
ETHERNET_COMPARATOR:INGR1_IP1_FLOW_CFG:INGR1_IP1_FLOW_MAS
K_UPPER_MID
Parent: ETHERNET_COMPARATOR:INGR1_IP1_FLOW_CFG
Instances: 1
VMDS-10510 VSC8574-02 Datasheet Revision 4.2
305
Table 550 • Fields in INGR1_IP1_FLOW_MASK_UPPER_MID
Field Name
Bit
INGR1_IP1_FLOW_MASK_UPPE 31:0
R_MID
4.12.8.8
Access
Description
Default
R/W
These bits must be all 0 for IPv4 and any 32- 0x00000000
bit address match mode
ETHERNET_COMPARATOR:INGR1_IP1_FLOW_CFG:INGR1_IP1_FLOW_MAS
K_LOWER_MID
Parent: ETHERNET_COMPARATOR:INGR1_IP1_FLOW_CFG
Instances: 1
Table 551 • Fields in INGR1_IP1_FLOW_MASK_LOWER_MID
Field Name
Bit
INGR1_IP1_FLOW_MASK_LOWE 31:0
R_MID
4.12.8.9
Access
Description
Default
R/W
These bits must be all 0 for IPv4 and any 32- 0x00000000
bit address match mode
ETHERNET_COMPARATOR:INGR1_IP1_FLOW_CFG:INGR1_IP1_FLOW_MAS
K_LOWER
Parent: ETHERNET_COMPARATOR:INGR1_IP1_FLOW_CFG
Instances: 1
Table 552 • Fields in INGR1_IP1_FLOW_MASK_LOWER
Field Name
Bit
INGR1_IP1_FLOW_MASK_LOWE 31:0
R
4.12.9
Access
Description
Default
R/W
These bits must be all 0 for IPv4 and any 32- 0x00000000
bit address match mode
ETHERNET_COMPARATOR:INGR1_IP2_NXT_PROTOCOL
Parent: Egress0 Ethernet Comparator
Instances: 1
Table 553 • Registers in INGR1_IP2_NXT_PROTOCOL
Register Name
Instances and
Offset within
Address
Register Group Spacing
Description
Details
INGR1_IP2_NXT_COMPARATOR 0x00000000
1
IP next comparator control
register
Page 307
INGR1_IP2_MODE
0x00000004
1
IP comparator mode
Page 307
INGR1_IP2_PROT_MATCH_1
0x00000008
1
IP match register set 1
Page 308
INGR1_IP2_PROT_MATCH_2_UP 0x0000000C
PER
1
Upper portion of match
register 2
Page 308
VMDS-10510 VSC8574-02 Datasheet Revision 4.2
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Table 553 • Registers in INGR1_IP2_NXT_PROTOCOL (continued)
Instances and
Offset within
Address
Register Group Spacing
Register Name
Description
Details
INGR1_IP2_PROT_MATCH_2_LO 0x00000010
WER
1
Lower portion of match
register 2
Page 308
INGR1_IP2_PROT_MASK_2_UPP 0x00000014
ER
1
Upper portion of match mask
register 2
Page 309
INGR1_IP2_PROT_MASK_2_LO
WER
0x00000018
1
Lower portion of match mask
register 2
Page 309
INGR1_IP2_PROT_OFFSET_2
0x0000001C
1
IP match offset register set 2
Page 309
INGR1_IP2_UDP_CHKSUM_CFG 0x00000020
1
IP/UDP checksum control
register
Page 309
4.12.9.1
ETHERNET_COMPARATOR:INGR1_IP2_NXT_PROTOCOL:INGR1_IP2_NXT_C
OMPARATOR
Parent: ETHERNET_COMPARATOR:INGR1_IP2_NXT_PROTOCOL
Instances: 1
Table 554 • Fields in INGR1_IP2_NXT_COMPARATOR
Field Name
Bit
Access
Description
INGR1_IP2_NXT_PROTOCOL
15:8
R/W
Number of bytes in this header, points to the 0x00
beginning of the next protocol.
R/W
Points to the next comparator stage. If this
0x0
comparator block is not used, this field must
be set to 0.
0: Comparator block not used
1: Reserved
2: Reserved
3: Reserved
4: Reserved
5: PTP/OAM comparator
6,7: Reserved
INGR1_IP2_NXT_COMPARATOR 2:0
4.12.9.2
Default
ETHERNET_COMPARATOR:INGR1_IP2_NXT_PROTOCOL:INGR1_IP2_MODE
Parent: ETHERNET_COMPARATOR:INGR1_IP2_NXT_PROTOCOL
Instances: 1
Table 555 • Fields in INGR1_IP2_MODE
Field Name
Bit
Access
Description
Default
INGR1_IP2_FLOW_OFFSET
12:8
R/W
Points to the source address field in the IP
frame. Use 12 for IPv4 and 8 for IPv6.
0x0C
VMDS-10510 VSC8574-02 Datasheet Revision 4.2
307
Table 555 • Fields in INGR1_IP2_MODE (continued)
Field Name
Bit
Access
Description
Default
INGR1_IP2_MODE
1:0
R/W
IP mode
0: IPv4
1: IPv6
2: Other protocol, 32-bit address match
3: Other protocol, 128-bit address match
0x0
4.12.9.3
ETHERNET_COMPARATOR:INGR1_IP2_NXT_PROTOCOL:INGR1_IP2_PROT_
MATCH_1
Parent: ETHERNET_COMPARATOR:INGR1_IP2_NXT_PROTOCOL
Instances: 1
Table 556 • Fields in INGR1_IP2_PROT_MATCH_1
Field Name
Bit
Access
Description
Default
INGR1_IP2_PROT_OFFSET_1
20:16
R/W
Points to the start of this match field relative
to the first byte of this protocol
0x00
INGR1_IP2_PROT_MASK_1
15:8
R/W
Mask field for IP_PROT_MATCH_1
0x00
INGR1_IP2_PROT_MATCH_1
7:0
R/W
8-bit match field
0x00
4.12.9.4
ETHERNET_COMPARATOR:INGR1_IP2_NXT_PROTOCOL:INGR1_IP2_PROT_
MATCH_2_UPPER
Parent: ETHERNET_COMPARATOR:INGR1_IP2_NXT_PROTOCOL
Instances: 1
Table 557 • Fields in INGR1_IP2_PROT_MATCH_2_UPPER
Field Name
Bit
INGR1_IP2_PROT_MATCH_2_UP 31:0
PER
4.12.9.5
Access
Description
Default
R/W
64-bit match register for advancing to the
next protocol, upper portion
0x00000000
ETHERNET_COMPARATOR:INGR1_IP2_NXT_PROTOCOL:INGR1_IP2_PROT_
MATCH_2_LOWER
Parent: ETHERNET_COMPARATOR:INGR1_IP2_NXT_PROTOCOL
Instances: 1
Table 558 • Fields in INGR1_IP2_PROT_MATCH_2_LOWER
Field Name
Bit
INGR1_IP2_PROT_MATCH_2_LO 31:0
WER
Access
Description
Default
R/W
64-bit match register for advancing to the
next protocol, lower portion
0x00000000
VMDS-10510 VSC8574-02 Datasheet Revision 4.2
308
4.12.9.6
ETHERNET_COMPARATOR:INGR1_IP2_NXT_PROTOCOL:INGR1_IP2_PROT_
MASK_2_UPPER
Parent: ETHERNET_COMPARATOR:INGR1_IP2_NXT_PROTOCOL
Instances: 1
Table 559 • Fields in INGR1_IP2_PROT_MASK_2_UPPER
Field Name
Bit
INGR1_IP2_PROT_MASK_2_UPP 31:0
ER
4.12.9.7
Access
Description
R/W
Default
0x00000000
ETHERNET_COMPARATOR:INGR1_IP2_NXT_PROTOCOL:INGR1_IP2_PROT_
MASK_2_LOWER
Parent: ETHERNET_COMPARATOR:INGR1_IP2_NXT_PROTOCOL
Instances: 1
Table 560 • Fields in INGR1_IP2_PROT_MASK_2_LOWER
Field Name
Bit
Access
INGR1_IP2_PROT_MASK_2_LO
WER
31:0
R/W
4.12.9.8
Description
Default
0x00000000
ETHERNET_COMPARATOR:INGR1_IP2_NXT_PROTOCOL:INGR1_IP2_PROT_
OFFSET_2
Parent: ETHERNET_COMPARATOR:INGR1_IP2_NXT_PROTOCOL
Instances: 1
Table 561 • Fields in INGR1_IP2_PROT_OFFSET_2
Field Name
Bit
Access
Description
INGR1_IP2_PROT_OFFSET_2
6:0
R/W
Points to the start of match field 2 relative to 0x00
the first byte of this protocol
4.12.9.9
Default
ETHERNET_COMPARATOR:INGR1_IP2_NXT_PROTOCOL:INGR1_IP2_UDP_C
HKSUM_CFG
Parent: ETHERNET_COMPARATOR:INGR1_IP2_NXT_PROTOCOL
Instances: 1
VMDS-10510 VSC8574-02 Datasheet Revision 4.2
309
Table 562 • Fields in INGR1_IP2_UDP_CHKSUM_CFG
Field Name
Bit
Access
Description
Default
INGR1_IP2_UDP_CHKSUM_OFF 15:8
SET
R/W
Pointer to the IP/UDP checksum field FOR
IPv4 frames or to the pad bytes of a
IPv6/UDP frame. For IPv4, it points to the
bytes that will be cleared. For IPv6, it points
to the bytes that will be updated to fix the
CRC.
0x00
INGR1_IP2_UDP_CHKSUM_WID 5:4
TH
R/W
Specifies the length of the checksum field in 0x2
bytes
INGR1_IP2_UDP_CHKSUM_UPD 1
ATE_ENA
R/W
0x0
This bit and
IP_UDP_CHKSUM_CLEAR_ENA CANNOT
be set together
1: Update the pad bytes at the end of the
frame
0: No pad byte field update
INGR1_IP2_UDP_CHKSUM_CLE 0
AR_ENA
R/W
This bit and
IP_UDP_CHKSUM_UPDATE_ENA
CANNOT be set together
1: Clear the UDP checksum field in an IPv4
frame
0: Do not clear the checksum
0x0
4.12.10 ETHERNET_COMPARATOR:INGR1_IP2_FLOW_CFG
Parent: Egress0 Ethernet Comparator
Instances: 8
Table 563 • Registers in INGR1_IP2_FLOW_CFG
Register Name
Instances and
Offset within
Address
Register Group Spacing
Description
Details
INGR1_IP2_FLOW_ENA
0x00000000
1
IP flow enable register
Page 311
INGR1_IP2_FLOW_MATCH_UPP 0x00000004
ER
1
Upper portion of the IP flow
match register
Page 311
INGR1_IP2_FLOW_MATCH_UPP 0x00000008
ER_MID
1
Upper mid portion of the IP
flow match register
Page 311
INGR1_IP2_FLOW_MATCH_LOW 0x0000000C
ER_MID
1
Lower mid portion of the IP
flow match register
Page 312
INGR1_IP2_FLOW_MATCH_LOW 0x00000010
ER
1
Lower portion of the IP flow
match register
Page 312
INGR1_IP2_FLOW_MASK_UPPE 0x00000014
R
1
Upper portion of the IP flow
match mask register
Page 312
INGR1_IP2_FLOW_MASK_UPPE 0x00000018
R_MID
1
Upper mid portion of the IP
flow match mask register
Page 313
INGR1_IP2_FLOW_MASK_LOWE 0x0000001C
R_MID
1
Lower mid portion of the IP
flow match mask register
Page 313
VMDS-10510 VSC8574-02 Datasheet Revision 4.2
310
Table 563 • Registers in INGR1_IP2_FLOW_CFG (continued)
Register Name
Instances and
Offset within
Address
Register Group Spacing
INGR1_IP2_FLOW_MASK_LOWE 0x00000020
R
1
Description
Details
Lower portion of the IP flow
match mask register
Page 313
4.12.10.1 ETHERNET_COMPARATOR:INGR1_IP2_FLOW_CFG:INGR1_IP2_FLOW_EN
A
Parent: ETHERNET_COMPARATOR:INGR1_IP2_FLOW_CFG
Instances: 1
Table 564 • Fields in INGR1_IP2_FLOW_ENA
Field Name
Bit
Access
Description
Default
INGR1_IP2_FLOW_MATCH_MOD 9:8
E
R/W
Match mode
0: Match on source address
1: Match on destination address
2: Match on either source or destination
address
3: Reserved
0x0
INGR1_IP2_CHANNEL_MASK
5:4
R/W
Channel mask
0x0: Flow invalid
0x1: Flow valid for channel 0
0x2: Flow valid for channel 1
0x3: Flow valid for both channels
0x3
INGR1_IP2_FLOW_ENA
0
R/W
Flow enable. If this comparator block is not
used, all flow enable bits must be set to 0.
0: Flow disabled
1: Flow enabled
0x0
4.12.10.2 ETHERNET_COMPARATOR:INGR1_IP2_FLOW_CFG:INGR1_IP2_FLOW_MA
TCH_UPPER
Parent: ETHERNET_COMPARATOR:INGR1_IP2_FLOW_CFG
Instances: 1
Table 565 • Fields in INGR1_IP2_FLOW_MATCH_UPPER
Field Name
Bit
INGR1_IP2_FLOW_MATCH_UPP 31:0
ER
Access
Description
R/W
Match field for either the entire 32-bit
0x00000000
selected address for IPv4 or the upper 32 bits
of the selected address for IPv6
Default
4.12.10.3 ETHERNET_COMPARATOR:INGR1_IP2_FLOW_CFG:INGR1_IP2_FLOW_MA
TCH_UPPER_MID
Parent: ETHERNET_COMPARATOR:INGR1_IP2_FLOW_CFG
Instances: 1
VMDS-10510 VSC8574-02 Datasheet Revision 4.2
311
Table 566 • Fields in INGR1_IP2_FLOW_MATCH_UPPER_MID
Field Name
Bit
INGR1_IP2_FLOW_MATCH_UPP 31:0
ER_MID
Access
Description
Default
R/W
Match bits for the upper middle 32 bits of the 0x00000000
IPv6 address
4.12.10.4 ETHERNET_COMPARATOR:INGR1_IP2_FLOW_CFG:INGR1_IP2_FLOW_MA
TCH_LOWER_MID
Parent: ETHERNET_COMPARATOR:INGR1_IP2_FLOW_CFG
Instances: 1
Table 567 • Fields in INGR1_IP2_FLOW_MATCH_LOWER_MID
Field Name
Bit
INGR1_IP2_FLOW_MATCH_LOW 31:0
ER_MID
Access
Description
Default
R/W
Match bits for the lower middle 32 bits of the 0x00000000
IPv6 address
4.12.10.5 ETHERNET_COMPARATOR:INGR1_IP2_FLOW_CFG:INGR1_IP2_FLOW_MA
TCH_LOWER
Parent: ETHERNET_COMPARATOR:INGR1_IP2_FLOW_CFG
Instances: 1
Table 568 • Fields in INGR1_IP2_FLOW_MATCH_LOWER
Field Name
Bit
INGR1_IP2_FLOW_MATCH_LOW 31:0
ER
Access
Description
Default
R/W
Match bits for the lower 32 bits of the IPv6
address
0x00000000
4.12.10.6 ETHERNET_COMPARATOR:INGR1_IP2_FLOW_CFG:INGR1_IP2_FLOW_MA
SK_UPPER
Parent: ETHERNET_COMPARATOR:INGR1_IP2_FLOW_CFG
Instances: 1
VMDS-10510 VSC8574-02 Datasheet Revision 4.2
312
Table 569 • Fields in INGR1_IP2_FLOW_MASK_UPPER
Field Name
Bit
INGR1_IP2_FLOW_MASK_UPPE 31:0
R
Access
Description
Default
R/W
Address mask for the IP address. It uses
0x00000000
CIDR format and specifies a number of
sequential bits to be used for matching, and a
number of sequential bits that are not
checked.
IP addresses specified in CIDR format look
like the following example:
192.0.0.5/24
In this example, the upper 24 bits are
significant and the lower 8 bits are not
checked.
This can be swapped by setting the
CIDR_DIRECTION register to 1 (normally it
is 0) so that in the above example, the upper
8 bits would not be checked and the lower 24
bits would be checked.
For IPv4 the allowable range is 1 - 32
For IPv6 the allowable range is 1 - 128
All other values are not defined
4.12.10.7 ETHERNET_COMPARATOR:INGR1_IP2_FLOW_CFG:INGR1_IP2_FLOW_MA
SK_UPPER_MID
Parent: ETHERNET_COMPARATOR:INGR1_IP2_FLOW_CFG
Instances: 1
Table 570 • Fields in INGR1_IP2_FLOW_MASK_UPPER_MID
Field Name
Bit
INGR1_IP2_FLOW_MASK_UPPE 31:0
R_MID
Access
Description
Default
R/W
These bits must be all 0 for IPv4 and any 32- 0x00000000
bit address match mode
4.12.10.8 ETHERNET_COMPARATOR:INGR1_IP2_FLOW_CFG:INGR1_IP2_FLOW_MA
SK_LOWER_MID
Parent: ETHERNET_COMPARATOR:INGR1_IP2_FLOW_CFG
Instances: 1
Table 571 • Fields in INGR1_IP2_FLOW_MASK_LOWER_MID
Field Name
Bit
INGR1_IP2_FLOW_MASK_LOWE 31:0
R_MID
Access
Description
Default
R/W
These bits must be all 0 for IPv4 and any 32- 0x00000000
bit address match mode
4.12.10.9 ETHERNET_COMPARATOR:INGR1_IP2_FLOW_CFG:INGR1_IP2_FLOW_MA
SK_LOWER
Parent: ETHERNET_COMPARATOR:INGR1_IP2_FLOW_CFG
VMDS-10510 VSC8574-02 Datasheet Revision 4.2
313
Instances: 1
Table 572 • Fields in INGR1_IP2_FLOW_MASK_LOWER
Field Name
Bit
INGR1_IP2_FLOW_MASK_LOWE 31:0
R
Access
Description
Default
R/W
These bits must be all 0 for IPv4 and any 32- 0x00000000
bit address match mode
4.12.11 ETHERNET_COMPARATOR:INGR1_PTP_FLOW
Parent: Egress0 Ethernet Comparator
Instances: 6
Table 573 • Registers in INGR1_PTP_FLOW
Register Name
Instances and
Offset within
Address
Register Group Spacing
Description
Details
INGR1_PTP_FLOW_ENA
0x00000000
1
PTP/OAM flow enable
Page 314
INGR1_PTP_FLOW_MATCH_UP
PER
0x00000004
1
Upper half of PTP/OAM flow
match field
Page 315
INGR1_PTP_FLOW_MATCH_LO
WER
0x00000008
1
Lower half of PTP/OAM flow
match field
Page 315
INGR1_PTP_FLOW_MASK_UPP
ER
0x0000000C
1
Upper half of PTP/OAM flow
match mask
Page 315
INGR1_PTP_FLOW_MASK_LOW 0x00000010
ER
1
Lower half of PTP/OAM flow
match mask
Page 315
INGR1_PTP_DOMAIN_RANGE
0x00000014
1
PTP/OAM range match
register
Page 316
INGR1_PTP_ACTION
0x00000018
1
PTP action control register
Page 316
INGR1_PTP_ACTION_2
0x0000001C
1
PTP action control register 2
Page 317
INGR1_PTP_ZERO_FIELD_CTL
0x00000020
1
Zero field control register
Page 317
4.12.11.1 ETHERNET_COMPARATOR:INGR1_PTP_FLOW:INGR1_PTP_FLOW_ENA
Parent: ETHERNET_COMPARATOR:INGR1_PTP_FLOW
Instances: 1
Table 574 • Fields in INGR1_PTP_FLOW_ENA
Field Name
Bit
Access
Description
Default
INGR1_PTP_CHANNEL_MASK
5:4
R/W
Channel mask
0x0: Flow invalid
0x1: Flow valid for channel 0
0x2: Flow valid for channel 1
0x3: Flow valid for both channels
0x3
INGR1_PTP_FLOW_ENA
0
R/W
Flow enable
0x0
VMDS-10510 VSC8574-02 Datasheet Revision 4.2
314
4.12.11.2 ETHERNET_COMPARATOR:INGR1_PTP_FLOW:INGR1_PTP_FLOW_MATCH
_UPPER
Parent: ETHERNET_COMPARATOR:INGR1_PTP_FLOW
Instances: 1
Table 575 • Fields in INGR1_PTP_FLOW_MATCH_UPPER
Field Name
Bit
Access
Description
Default
INGR1_PTP_FLOW_MATCH_UP
PER
31:0
R/W
PTP flow match, upper 32 bit
0x00000000
4.12.11.3 ETHERNET_COMPARATOR:INGR1_PTP_FLOW:INGR1_PTP_FLOW_MATCH
_LOWER
Parent: ETHERNET_COMPARATOR:INGR1_PTP_FLOW
Instances: 1
Table 576 • Fields in INGR1_PTP_FLOW_MATCH_LOWER
Field Name
Bit
Access
Description
Default
INGR1_PTP_FLOW_MATCH_LO
WER
31:0
R/W
PTP flow match, lower 32 bit
0x00000000
4.12.11.4 ETHERNET_COMPARATOR:INGR1_PTP_FLOW:INGR1_PTP_FLOW_MASK_
UPPER
Parent: ETHERNET_COMPARATOR:INGR1_PTP_FLOW
Instances: 1
Table 577 • Fields in INGR1_PTP_FLOW_MASK_UPPER
Field Name
Bit
Access
Description
Default
INGR1_PTP_FLOW_MASK_UPP
ER
31:0
R/W
PTP flow mask, upper 32 bit
0x00000000
4.12.11.5 ETHERNET_COMPARATOR:INGR1_PTP_FLOW:INGR1_PTP_FLOW_MASK_
LOWER
Parent: ETHERNET_COMPARATOR:INGR1_PTP_FLOW
Instances: 1
Table 578 • Fields in INGR1_PTP_FLOW_MASK_LOWER
Field Name
Bit
INGR1_PTP_FLOW_MASK_LOW 31:0
ER
Access
Description
Default
R/W
PTP flow mask, lower 32 bit
0x00000000
VMDS-10510 VSC8574-02 Datasheet Revision 4.2
315
4.12.11.6 ETHERNET_COMPARATOR:INGR1_PTP_FLOW:INGR1_PTP_DOMAIN_RAN
GE
Parent: ETHERNET_COMPARATOR:INGR1_PTP_FLOW
Instances: 1
Table 579 • Fields in INGR1_PTP_DOMAIN_RANGE
Field Name
Bit
Access
Description
Default
INGR1_PTP_DOMAIN_RANGE_O 28:24
FFSET
R/W
PTP domain range offset
0x00
INGR1_PTP_DOMAIN_RANGE_U 23:16
PPER
R/W
Upper range of PTP domain field to match
0xFF
INGR1_PTP_DOMAIN_RANGE_L 15:8
OWER
R/W
Lower range of PTP domain field to match
0x00
INGR1_PTP_DOMAIN_RANGE_E 0
NA
R/W
Enable PTP domain range checking
0x0
4.12.11.7 ETHERNET_COMPARATOR:INGR1_PTP_FLOW:INGR1_PTP_ACTION
Parent: ETHERNET_COMPARATOR:INGR1_PTP_FLOW
Instances: 1
Table 580 • Fields in INGR1_PTP_ACTION
Field Name
Bit
Access
Description
Default
INGR1_PTP_MOD_FRAME_STAT 28
_UPDATE
R/W
Modified frame status update
0: Do not signal the rewriter to update the
value of the Modified Frame Status bit
1: Signal the rewriter to update the value of
the Modified Frame Status bit
0x0
INGR1_PTP_MOD_FRAME_BYT
E_OFFSET
R/W
Indicates the position relative to the start of
the PTP frame in bytes where the Modified
Frame Status bit resides
0x0
INGR1_PTP_SUB_DELAY_ASYM 21
_ENA
R/W
Enable subtract delay asymmetry signal
0x0
0: Do not signal the timestamp block to
subtract the asymmetry delay
1: Signal the timestamp block to subtract the
asymmetry delay
INGR1_PTP_ADD_DELAY_ASYM 20
_ENA
R/W
Enable add delay asymmetry signal
0: Do not signal the timestamp block to add
the asymmetry delay
1: Signal the timestamp block to add the
asymmetry delay
0x0
INGR1_PTP_TIME_STRG_FIELD 15:10
_OFFSET
R/W
Time storage field offset
The location in a PTP frame where a time
value can be stored or read
0x00
26:24
VMDS-10510 VSC8574-02 Datasheet Revision 4.2
316
Table 580 • Fields in INGR1_PTP_ACTION (continued)
Field Name
Bit
Access
Description
Default
INGR1_PTP_CORR_FIELD_OFF
SET
9:5
R/W
Points to the location of the correction field
for updating the timestamp. Location is
relative to the first byte of the PTP/OAM
header.
Note: If this flow is being used to
match OAM frames, set this
register to 4.
0x00
INGR1_PTP_SAVE_LOCAL_TIME 4
R/W
Enable saving time
0x0
0: Do not save the time to the timestamp
FIFO
1: Save the local time to the timestamp FIFO
INGR1_PTP_COMMAND
R/W
PTP action command
0: NOP
1: SUB
2: SUB_P2P
3: ADD
4: SUB_ADD
5: WRITE_1588
6: WRITE_P2P (deprecated)
7: WRITE_NS
8: WRITE_NS_P2P
3:0
0x0
4.12.11.8 ETHERNET_COMPARATOR:INGR1_PTP_FLOW:INGR1_PTP_ACTION_2
Parent: ETHERNET_COMPARATOR:INGR1_PTP_FLOW
Instances: 1
Table 581 • Fields in INGR1_PTP_ACTION_2
Field Name
Bit
Access
Description
INGR1_PTP_NEW_CF_LOC
23:16
R/W
Location of the new correction field relative to 0x00
the PTP header start. Only even values are
allowed.
INGR1_PTP_REWRITE_OFFSET 15:8
R/W
Points to where in the frame relative to the
SFD that the timestamp should be updated
0x00
INGR1_PTP_REWRITE_BYTES
R/W
Number of bytes in the PTP or OAM frame
that must be modified by the rewriter for the
timestamp
0x0
3:0
Default
4.12.11.9 ETHERNET_COMPARATOR:INGR1_PTP_FLOW:INGR1_PTP_ZERO_FIELD_
CTL
Parent: ETHERNET_COMPARATOR:INGR1_PTP_FLOW
Instances: 1
VMDS-10510 VSC8574-02 Datasheet Revision 4.2
317
Table 582 • Fields in INGR1_PTP_ZERO_FIELD_CTL
Field Name
Bit
Access
Description
Default
INGR1_PTP_ZERO_FIELD_OFFS 13:8
ET
R/W
Points to a location in the PTP/OAM frame
0x00
relative to the start of the PTP header that will
be zeroed if this function is enabled
INGR1_PTP_ZERO_FIELD_BYTE 3:0
_CNT
R/W
The number of bytes to be zeroed. If this field 0x0
is 0, then this function is not enabled.
4.12.12 ETHERNET_COMPARATOR:INGR1_PTP_IP_CHKSUM_CTL
Parent: Egress0 Ethernet Comparator
Instances: 1
Table 583 • Registers in INGR1_PTP_IP_CHKSUM_CTL
Register Name
Instances and
Offset within
Address
Register Group Spacing
Description
Details
INGR1_PTP_IP_CKSUM_SEL
0x00000000
IP checksum block select
Page 318
1
4.12.12.1 ETHERNET_COMPARATOR:INGR1_PTP_IP_CHKSUM_CTL:INGR1_PTP_IP_
CKSUM_SEL
Parent: ETHERNET_COMPARATOR:INGR1_PTP_IP_CHKSUM_CTL
Instances: 1
Table 584 • Fields in INGR1_PTP_IP_CKSUM_SEL
Field Name
Bit
Access
Description
Default
INGR1_PTP_IP_CHKSUM_SEL
0
R/W
IP checksum controls selection
0: Use the IP checksum controls from IP
comparator 1
1: Use the IP checksum controls from IP
comparator 2
0x0
4.13
Egress2 Ethernet Comparator
Table 585 • Register Groups in Egress2 Ethernet Comparator
Register Group Name
Offset within
Target
Instances and
Address
Spacing
Description
Details
EGR2_ETH1_NXT_PROTOCOL_ 0x00000000
A
1
Ethernet next protocol
configuration
Page 319
EGR2_ETH1_NXT_PROTOCOL_ 0x00000040
B
1
Ethernet next protocol
configuration
Page 321
VMDS-10510 VSC8574-02 Datasheet Revision 4.2
318
Table 585 • Register Groups in Egress2 Ethernet Comparator (continued)
Register Group Name
Offset within
Target
EGR2_ETH1_FLOW_CFG
0x00000080
Instances and
Address
Spacing
Description
Details
8
0x00000040
Ethernet flow configuration
Page 322
EGR2_ETH2_NXT_PROTOCOL_ 0x00000280
A
1
Ethernet next protocol
configuration
Page 326
EGR2_ETH2_FLOW_CFG
8
0x00000040
Ethernet flow configuration
Page 327
EGR2_MPLS_NXT_COMPARATO 0x00000500
R_A
1
MPLS next protocol register
Page 331
EGR2_MPLS_FLOW_CFG
0x00000580
8
0x00000040
MPLS flow configuration
Page 332
EGR2_PTP_FLOW
0x00000780
6
0x00000040
PTP flow configuration
Page 335
4.13.1
0x00000300
ETHERNET_COMPARATOR:EGR2_ETH1_NXT_PROTOCOL_A
Parent: Egress0 Ethernet Comparator
Instances: 1
Table 586 • Registers in EGR2_ETH1_NXT_PROTOCOL_A
Instances and
Offset within
Address
Register Group Spacing
Register Name
Description
Details
EGR2_ETH1_NXT_PROTOCOL_ 0x00000000
A
1
Ethernet next protocol register Page 319
EGR2_ETH1_VLAN_TPID_CFG_ 0x00000004
A
1
VLAN TPID configuration
Page 320
EGR2_ETH1_TAG_MODE_A
0x00000008
1
Ethernet tag mode
Page 320
EGR2_ETH1_ETYPE_MATCH_A
0x0000000C
1
Ethertype match register
Page 320
4.13.1.1
ETHERNET_COMPARATOR:EGR2_ETH1_NXT_PROTOCOL_A:EGR2_ETH1_
NXT_PROTOCOL_A
Parent: ETHERNET_COMPARATOR:EGR2_ETH1_NXT_PROTOCOL_A
Instances: 1
VMDS-10510 VSC8574-02 Datasheet Revision 4.2
319
Table 587 • Fields in EGR2_ETH1_NXT_PROTOCOL_A
Field Name
Bit
EGR2_ETH1_NXT_COMPARATO 2:0
R_A
4.13.1.2
Access
Description
Default
R/W
Points to the next comparator block after this 0x0
Ethernet block
0: Reserved
1: Ethernet comparator 2
2: IP/UDP/ACH comparator 1
3: IP/UDP/ACH comparator 2
4: MPLS comparator
5: PTP/OAM comparator
6,7: Reserved
ETHERNET_COMPARATOR:EGR2_ETH1_NXT_PROTOCOL_A:EGR2_ETH1_V
LAN_TPID_CFG_A
Parent: ETHERNET_COMPARATOR:EGR2_ETH1_NXT_PROTOCOL_A
Instances: 1
Table 588 • Fields in EGR2_ETH1_VLAN_TPID_CFG_A
Field Name
Bit
EGR2_ETH1_VLAN_TPID_CFG_ 31:16
A
4.13.1.3
Access
Description
Default
R/W
Configurable VLAN TPID (S or B-tag)
0x88A8
ETHERNET_COMPARATOR:EGR2_ETH1_NXT_PROTOCOL_A:EGR2_ETH1_T
AG_MODE_A
Parent: ETHERNET_COMPARATOR:EGR2_ETH1_NXT_PROTOCOL_A
Instances: 1
Table 589 • Fields in EGR2_ETH1_TAG_MODE_A
Field Name
Bit
Access
Description
EGR2_ETH1_PBB_ENA_A
0
R/W
This bit enables the presence of PBB.
0x0
The I-tag match bits are programmed in the
ETH1_VLAN_TAG_RANGE registers. The
mask bits are programmed in the
ETH1_VLAN_TAG2 registers. A B-tag if
present is configured in the
ETH1_VLAN_TAG1 registers.
0: PBB not enabled
1: Always expect PBB, last tag is always an Itag
4.13.1.4
Default
ETHERNET_COMPARATOR:EGR2_ETH1_NXT_PROTOCOL_A:EGR2_ETH1_E
TYPE_MATCH_A
Parent: ETHERNET_COMPARATOR:EGR2_ETH1_NXT_PROTOCOL_A
Instances: 1
VMDS-10510 VSC8574-02 Datasheet Revision 4.2
320
Table 590 • Fields in EGR2_ETH1_ETYPE_MATCH_A
Field Name
Bit
Access
Description
EGR2_ETH1_ETYPE_MATCH_A
15:0
R/W
If the Ethertype/length field is an Ethertype, 0x0000
then this register is compared against the
value. If the field is a length, the length value
is not checked.
4.13.2
Default
ETHERNET_COMPARATOR:EGR2_ETH1_NXT_PROTOCOL_B
Parent: Egress0 Ethernet Comparator
Instances: 1
Table 591 • Registers in EGR2_ETH1_NXT_PROTOCOL_B
Instances and
Offset within
Address
Register Group Spacing
Register Name
Description
Details
EGR2_ETH1_NXT_PROTOCOL_ 0x00000000
B
1
Ethernet next protocol register Page 321
EGR2_ETH1_VLAN_TPID_CFG_ 0x00000004
B
1
VLAN TPID configuration
Page 321
EGR2_ETH1_TAG_MODE_B
0x00000008
1
Ethernet tag mode
Page 322
EGR2_ETH1_ETYPE_MATCH_B
0x0000000C
1
Ethertype match register
Page 322
4.13.2.1
ETHERNET_COMPARATOR:EGR2_ETH1_NXT_PROTOCOL_B:EGR2_ETH1_
NXT_PROTOCOL_B
Parent: ETHERNET_COMPARATOR:EGR2_ETH1_NXT_PROTOCOL_B
Instances: 1
Table 592 • Fields in EGR2_ETH1_NXT_PROTOCOL_B
Field Name
Bit
EGR2_ETH1_NXT_COMPARATO 2:0
R_B
4.13.2.2
Access
Description
R/W
Points to the next comparator block after this 0x0
Ethernet block
0: Reserved
1: Ethernet comparator 2
2: IP/UDP/ACH comparator 1
3: IP/UDP/ACH comparator 2
4: MPLS comparator
5: PTP/OAM comparator
6,7: Reserved
Default
ETHERNET_COMPARATOR:EGR2_ETH1_NXT_PROTOCOL_B:EGR2_ETH1_V
LAN_TPID_CFG_B
Parent: ETHERNET_COMPARATOR:EGR2_ETH1_NXT_PROTOCOL_B
Instances: 1
VMDS-10510 VSC8574-02 Datasheet Revision 4.2
321
Table 593 • Fields in EGR2_ETH1_VLAN_TPID_CFG_B
Field Name
Bit
EGR2_ETH1_VLAN_TPID_CFG_ 15:0
B
4.13.2.3
Access
Description
Default
R/W
Configurable VLAN TPID (S or B-tag)
0x88A8
ETHERNET_COMPARATOR:EGR2_ETH1_NXT_PROTOCOL_B:EGR2_ETH1_T
AG_MODE_B
Parent: ETHERNET_COMPARATOR:EGR2_ETH1_NXT_PROTOCOL_B
Instances: 1
Table 594 • Fields in EGR2_ETH1_TAG_MODE_B
Field Name
Bit
Access
Description
EGR2_ETH1_PBB_ENA_B
0
R/W
This bit enables the presence of PBB.
0x0
The I-tag match bits are programmed in the
ETH1_VLAN_TAG_RANGE registers. The
mask bits are programmed in the
ETH1_VLAN_TAG2 registers. A B-tag if
present is configured in the
ETH1_VLAN_TAG1 registers.
0: PBB not enabled
1: Always expect PBB, last tag is always an Itag
4.13.2.4
Default
ETHERNET_COMPARATOR:EGR2_ETH1_NXT_PROTOCOL_B:EGR2_ETH1_E
TYPE_MATCH_B
Parent: ETHERNET_COMPARATOR:EGR2_ETH1_NXT_PROTOCOL_B
Instances: 1
Table 595 • Fields in EGR2_ETH1_ETYPE_MATCH_B
Field Name
Bit
Access
Description
EGR2_ETH1_ETYPE_MATCH_B
15:0
R/W
If the Ethertype/length field is an Ethertype, 0x0000
then this register is compared against the
value. If the field is a length, the length value
is not checked.
4.13.3
Default
ETHERNET_COMPARATOR:EGR2_ETH1_FLOW_CFG
Parent: Egress0 Ethernet Comparator
Instances: 8
VMDS-10510 VSC8574-02 Datasheet Revision 4.2
322
Table 596 • Registers in EGR2_ETH1_FLOW_CFG
Register Name
Instances and
Offset within
Address
Register Group Spacing
Description
Details
EGR2_ETH1_FLOW_ENABLE
0x00000000
1
Ethernet flow enable
Page 323
EGR2_ETH1_MATCH_MODE
0x00000004
1
Ethernet protocol match mode Page 323
EGR2_ETH1_ADDR_MATCH_1
0x00000008
1
Ethernet address match part 1 Page 324
EGR2_ETH1_ADDR_MATCH_2
0x0000000C
1
Ethernet address match part 2 Page 325
EGR2_ETH1_VLAN_TAG_RANG
E_I_TAG
0x00000010
1
Ethernet VLAN tag range
match register
Page 325
EGR2_ETH1_VLAN_TAG1
0x00000014
1
VLAN tag 1 match/mask
Page 326
EGR2_ETH1_VLAN_TAG2_I_TAG 0x00000018
1
Match/mask for VLAN tag 2 or Page 326
I-tag match
4.13.3.1
ETHERNET_COMPARATOR:EGR2_ETH1_FLOW_CFG:EGR2_ETH1_FLOW_E
NABLE
Parent: ETHERNET_COMPARATOR:EGR2_ETH1_FLOW_CFG
Instances: 1
Table 597 • Fields in EGR2_ETH1_FLOW_ENABLE
Field Name
Bit
Access
Description
Default
EGR2_ETH1_NXT_PROT_GRP_
SEL
16
R/W
Indicates which next-protocol configuration
group is valid with this flow
0: Associate this flow with next-protocol
group A
1: Associate this flow with next-protocol
group B
0x0
EGR2_ETH1_CHANNEL_MASK
9:8
R/W
Channel mask
0x0: Flow invalid
0x1: Flow valid for channel 0
0x2: Flow valid for channel 1
0x3: Flow valid for both channels
0x3
EGR2_ETH1_FLOW_ENABLE
0
R/W
Flow enable
0: Flow disabled
1: Flow enabled
0x0
4.13.3.2
ETHERNET_COMPARATOR:EGR2_ETH1_FLOW_CFG:EGR2_ETH1_MATCH_
MODE
Parent: ETHERNET_COMPARATOR:EGR2_ETH1_FLOW_CFG
Instances: 1
VMDS-10510 VSC8574-02 Datasheet Revision 4.2
323
Table 598 • Fields in EGR2_ETH1_MATCH_MODE
Field Name
Bit
EGR2_ETH1_VLAN_TAG_MODE 13:12
Access
Description
R/W
Default
0x0
0: VLAN range checking disabled
1: VLAN range checking on tag 1
2: VLAN range checking on tag 2 (not
supported with PBB)
3: Reserved
EGR2_ETH1_VLAN_TAG2_TYPE 9
R/W
This register is only used if
ETH1_VLAN_VERIFY_ENA = 1
If PBB not enabled:
0: C tag (TPID of 0x8100)
1: S tag (match to CONF_VLAN_TPID)
If PBB enabled:
0,1: I tag (use range registers)
EGR2_ETH1_VLAN_TAG1_TYPE 8
R/W
This register is only used if
0x0
ETH1_VLAN_VERIFY_ENA = 1
0: C tag (TPID of 0x8100)
1: S or B tag (match to CONF_VLAN_TPID)
EGR2_ETH1_VLAN_TAGS
R/W
This register is only used if
0x0
ETH1_VLAN_VERIFY_ENA = 1
0: No VLAN tags (not valid for PBB)
1: 1 VLAN tag (for PBB this would be the Itag)
2: 2 VLAN tags (for PBB expect a B-tag and
an I-tag)
3: Reserved
7:6
EGR2_ETH1_VLAN_VERIFY_EN 4
A
R/W
EGR2_ETH1_ETHERTYPE_MOD 0
E
R/W
4.13.3.3
0x1
0x0
0: Parse for VLAN tags; do not check values.
For PBB the I-tag is always checked.
1: Verify configured VLAN tag configuration.
When checking for presence of SNAP/LLC
0x0
based upon ETH1_MATCH_MODE, this field
indicates if SNAP and 3-byte LLC is expected
to be present.
0: Only Ethernet type II supported, no
SNAP/LLC
1: Ethernet type II and Ethernet type I with
SNAP/LLC, determine if SNAP/LLC is
present or not. Type I always assumes that
SNAP/LLC is present.
ETHERNET_COMPARATOR:EGR2_ETH1_FLOW_CFG:EGR2_ETH1_ADDR_M
ATCH_1
Parent: ETHERNET_COMPARATOR:EGR2_ETH1_FLOW_CFG
Instances: 1
VMDS-10510 VSC8574-02 Datasheet Revision 4.2
324
Table 599 • Fields in EGR2_ETH1_ADDR_MATCH_1
Field Name
Bit
Access
Description
Default
EGR2_ETH1_ADDR_MATCH_1
31:0
R/W
First 32 bits of the address match value
0x00000000
4.13.3.4
ETHERNET_COMPARATOR:EGR2_ETH1_FLOW_CFG:EGR2_ETH1_ADDR_M
ATCH_2
Parent: ETHERNET_COMPARATOR:EGR2_ETH1_FLOW_CFG
Instances: 1
Table 600 • Fields in EGR2_ETH1_ADDR_MATCH_2
Field Name
Access
Description
EGR2_ETH1_ADDR_MATCH_MO 22:20
DE
R/W
Selects how the addresses are matched.
0x1
One-hot encoded. Multiple bits can be set at
once.
0: Full 48-bit address match
1: Match any unicast address
2: Match any muliticast address
EGR2_ETH1_ADDR_MATCH_SE 17:16
LECT
R/W
Selects which address to match
0: Match the destination address
1: Match the source address
2: Match either the source of destination
address
3: Reserved
0x0
EGR2_ETH1_ADDR_MATCH_2
R/W
Last 16 bits of the Ethernet address match
field
0x0000
4.13.3.5
Bit
15:0
Default
ETHERNET_COMPARATOR:EGR2_ETH1_FLOW_CFG:EGR2_ETH1_VLAN_TA
G_RANGE_I_TAG
Parent: ETHERNET_COMPARATOR:EGR2_ETH1_FLOW_CFG
Instances: 1
Table 601 • Fields in EGR2_ETH1_VLAN_TAG_RANGE_I_TAG
Field Name
Bit
Access
Description
EGR2_ETH1_VLAN_TAG_RANG
E_UPPER
27:16
R/W
If PBB mode is not enabled, then this register 0xFFF
contains the upper range of the VLAN tag
range match.
If PBB mode is enabled, then this register
contains the upper 12 bits of the I-tag.
EGR2_ETH1_VLAN_TAG_RANG
E_LOWER
11:0
R/W
If PBB mode is not enabled, then this register 0x000
contains the lower range of the VLAN tag
range match.
If PBB mode is enabled, then this register
contains the lower 12 bits of the I-tag.
VMDS-10510 VSC8574-02 Datasheet Revision 4.2
Default
325
4.13.3.6
ETHERNET_COMPARATOR:EGR2_ETH1_FLOW_CFG:EGR2_ETH1_VLAN_TA
G1
Parent: ETHERNET_COMPARATOR:EGR2_ETH1_FLOW_CFG
Instances: 1
Table 602 • Fields in EGR2_ETH1_VLAN_TAG1
Field Name
Access
Description
Default
EGR2_ETH1_VLAN_TAG1_MASK 27:16
R/W
Mask value for VLAN tag 1
0xFFF
EGR2_ETH1_VLAN_TAG1_MATC 11:0
H
R/W
Match value for the first VLAN tag
0x000
4.13.3.7
Bit
ETHERNET_COMPARATOR:EGR2_ETH1_FLOW_CFG:EGR2_ETH1_VLAN_TA
G2_I_TAG
Parent: ETHERNET_COMPARATOR:EGR2_ETH1_FLOW_CFG
Instances: 1
Table 603 • Fields in EGR2_ETH1_VLAN_TAG2_I_TAG
Field Name
Access
Description
EGR2_ETH1_VLAN_TAG2_MASK 27:16
R/W
When PBB is not enabled, the mask field for 0xFFF
VLAN tag 2
When PBB is enabled, the upper 12 bits of
the I-tag mask
EGR2_ETH1_VLAN_TAG2_MATC 11:0
H
R/W
When PBB is not enabled, the match field for 0x000
VLAN Tag 2
When PBB is enabled, the lower 12 bits of
the I-tag mask field
4.13.4
Bit
Default
ETHERNET_COMPARATOR:EGR2_ETH2_NXT_PROTOCOL_A
Parent: Egress0 Ethernet Comparator
Instances: 1
Table 604 • Registers in EGR2_ETH2_NXT_PROTOCOL_A
Instances and
Offset within
Address
Register Group Spacing
Register Name
Description
Details
EGR2_ETH2_NXT_PROTOCOL_ 0x00000000
A
1
Ethernet next protocol register Page 327
EGR2_ETH2_VLAN_TPID_CFG_ 0x00000004
A
1
VLAN TPID configuration
Page 327
EGR2_ETH2_ETYPE_MATCH_A
1
Ethertype match register
Page 327
0x00000008
VMDS-10510 VSC8574-02 Datasheet Revision 4.2
326
4.13.4.1
ETHERNET_COMPARATOR:EGR2_ETH2_NXT_PROTOCOL_A:EGR2_ETH2_
NXT_PROTOCOL_A
Parent: ETHERNET_COMPARATOR:EGR2_ETH2_NXT_PROTOCOL_A
Instances: 1
Table 605 • Fields in EGR2_ETH2_NXT_PROTOCOL_A
Field Name
Bit
EGR2_ETH2_NXT_COMPARATO 2:0
R_A
4.13.4.2
Access
Description
Default
R/W
Points to the next comparator block after this 0x0
Ethernet block. If this comparator block is not
used, this field must be set to 0.
0: Comparator block not used
1: Ethernet comparator 2
2: IP/UDP/ACH comparator 1
3: IP/UDP/ACH comparator 2
4: MPLS comparator
5: PTP/OAM comparator
6,7: Reserved
ETHERNET_COMPARATOR:EGR2_ETH2_NXT_PROTOCOL_A:EGR2_ETH2_V
LAN_TPID_CFG_A
Parent: ETHERNET_COMPARATOR:EGR2_ETH2_NXT_PROTOCOL_A
Instances: 1
Table 606 • Fields in EGR2_ETH2_VLAN_TPID_CFG_A
Field Name
Bit
EGR2_ETH2_VLAN_TPID_CFG_ 31:16
A
4.13.4.3
Access
Description
Default
R/W
Configurable S-tag TPID
0x88A8
ETHERNET_COMPARATOR:EGR2_ETH2_NXT_PROTOCOL_A:EGR2_ETH2_E
TYPE_MATCH_A
Parent: ETHERNET_COMPARATOR:EGR2_ETH2_NXT_PROTOCOL_A
Instances: 1
Table 607 • Fields in EGR2_ETH2_ETYPE_MATCH_A
Field Name
Bit
Access
Description
EGR2_ETH2_ETYPE_MATCH_A
15:0
R/W
If the Ethertype/length field is an Ethertype, 0x0000
then this register is compared against the
value. If the field is a length, the length value
is not checked.
4.13.5
Default
ETHERNET_COMPARATOR:EGR2_ETH2_FLOW_CFG
Parent: Egress0 Ethernet Comparator
Instances: 8
VMDS-10510 VSC8574-02 Datasheet Revision 4.2
327
Table 608 • Registers in EGR2_ETH2_FLOW_CFG
Register Name
Instances and
Offset within
Address
Register Group Spacing
Description
Details
EGR2_ETH2_FLOW_ENABLE
0x00000000
1
Ethernet flow enable
Page 328
EGR2_ETH2_MATCH_MODE
0x00000004
1
Ethernet protocol match mode Page 328
EGR2_ETH2_ADDR_MATCH_1
0x00000008
1
Ethernet address match part 1 Page 329
EGR2_ETH2_ADDR_MATCH_2
0x0000000C
1
Ethernet address match part 2 Page 330
EGR2_ETH2_VLAN_TAG_RANG
E_I_TAG
0x00000010
1
Ethernet VLAN tag range
match register
Page 330
EGR2_ETH2_VLAN_TAG1
0x00000014
1
VLAN tag 1 match/mask
Page 330
EGR2_ETH2_VLAN_TAG2_I_TAG 0x00000018
1
Match/mask for VLAN tag 2 or Page 331
I-tag match
4.13.5.1
ETHERNET_COMPARATOR:EGR2_ETH2_FLOW_CFG:EGR2_ETH2_FLOW_E
NABLE
Parent: ETHERNET_COMPARATOR:EGR2_ETH2_FLOW_CFG
Instances: 1
Table 609 • Fields in EGR2_ETH2_FLOW_ENABLE
Field Name
Bit
Access
Description
Default
EGR2_ETH2_CHANNEL_MASK
9:8
R/W
Channel mask
0x0: Flow invalid
0x1: Flow valid for channel 0
0x2: Flow valid for channel 1
0x3: Flow valid for both channels
0x3
EGR2_ETH2_FLOW_ENABLE
0
R/W
Flow enable.
If this comparator block is not used, all flow
enable bits must be set to 0.
0: Flow disabled
1: Flow enabled
0x0
4.13.5.2
ETHERNET_COMPARATOR:EGR2_ETH2_FLOW_CFG:EGR2_ETH2_MATCH_
MODE
Parent: ETHERNET_COMPARATOR:EGR2_ETH2_FLOW_CFG
Instances: 1
VMDS-10510 VSC8574-02 Datasheet Revision 4.2
328
Table 610 • Fields in EGR2_ETH2_MATCH_MODE
Field Name
Bit
EGR2_ETH2_VLAN_TAG_MODE 13:12
Access
Description
R/W
Default
0x0
0: VLAN range checking disabled
1: VLAN range checking on tag 1
2: VLAN range checking on tag 2 (not
supported with PBB)
3: Reserved
EGR2_ETH2_VLAN_TAG2_TYPE 9
R/W
This register is only used if
ETH1_VLAN_VERIFY_ENA = 1
0: C tag (TPID of 0x8100)
1: S tag (match to CONF_VLAN_TPID)
EGR2_ETH2_VLAN_TAG1_TYPE 8
R/W
This register is only used if
0x0
ETH1_VLAN_VERIFY_ENA = 1
0: C tag (TPID of 0x8100)
1: S or B tag (match to CONF_VLAN_TPID)
EGR2_ETH2_VLAN_TAGS
R/W
This register is only used if
ETH2_VLAN_VERIFY_ENA = 1
0: No VLAN tags
1: 1 VLAN tag
2: 2 VLAN tags
3: Reserved
7:6
EGR2_ETH2_VLAN_VERIFY_EN 4
A
R/W
EGR2_ETH2_ETHERTYPE_MOD 0
E
R/W
4.13.5.3
0x1
0x0
0x0
0: Parse for VLAN tags, do not check values.
1: Verify configured VLAN tag configuration.
When checking for presence of SNAP/LLC
0x0
based upon ETH1_MATCH_MODE, this field
indicates if SNAP and 3-byte LLC is expected
to be present.
0: Only Ethernet type II supported, no
SNAP/LLC
1: Ethernet type II and Ethernet type I with
SNAP/LLC, determine if SNAP/LLC is
present. Type I always assumes that
SNAP/LLC is present
ETHERNET_COMPARATOR:EGR2_ETH2_FLOW_CFG:EGR2_ETH2_ADDR_M
ATCH_1
Parent: ETHERNET_COMPARATOR:EGR2_ETH2_FLOW_CFG
Instances: 1
Table 611 • Fields in EGR2_ETH2_ADDR_MATCH_1
Field Name
Bit
Access
Description
Default
EGR2_ETH2_ADDR_MATCH_1
31:0
R/W
First 32 bits of the address match value
0x00000000
VMDS-10510 VSC8574-02 Datasheet Revision 4.2
329
4.13.5.4
ETHERNET_COMPARATOR:EGR2_ETH2_FLOW_CFG:EGR2_ETH2_ADDR_M
ATCH_2
Parent: ETHERNET_COMPARATOR:EGR2_ETH2_FLOW_CFG
Instances: 1
Table 612 • Fields in EGR2_ETH2_ADDR_MATCH_2
Field Name
Access
Description
EGR2_ETH2_ADDR_MATCH_MO 22:20
DE
R/W
Selects how the addresses are matched.
0x1
One-hot encoded. Multiple bits can be set at
once.
0: Full 48-bit address match
1: Match any unicast address
2: Match any muliticast address
EGR2_ETH2_ADDR_MATCH_SE 17:16
LECT
R/W
Selects which address to match
0: Match the destination address
1: Match the source address
2: Match either the source of destination
address
3: Reserved
0x0
EGR2_ETH2_ADDR_MATCH_2
R/W
Last 16 bits of the Ethernet address match
field
0x0000
4.13.5.5
Bit
15:0
Default
ETHERNET_COMPARATOR:EGR2_ETH2_FLOW_CFG:EGR2_ETH2_VLAN_TA
G_RANGE_I_TAG
Parent: ETHERNET_COMPARATOR:EGR2_ETH2_FLOW_CFG
Instances: 1
Table 613 • Fields in EGR2_ETH2_VLAN_TAG_RANGE_I_TAG
Field Name
Bit
Access
Description
Default
EGR2_ETH2_VLAN_TAG_RANG
E_UPPER
27:16
R/W
Contains the upper range of the VLAN tag
range match
0xFFF
EGR2_ETH2_VLAN_TAG_RANG
E_LOWER
11:0
R/W
Contains the lower range of the VLAN tag
range match
0x000
4.13.5.6
ETHERNET_COMPARATOR:EGR2_ETH2_FLOW_CFG:EGR2_ETH2_VLAN_TA
G1
Parent: ETHERNET_COMPARATOR:EGR2_ETH2_FLOW_CFG
Instances: 1
Table 614 • Fields in EGR2_ETH2_VLAN_TAG1
Field Name
Bit
Access
Description
Default
EGR2_ETH2_VLAN_TAG1_MASK 27:16
R/W
Mask value for VLAN tag 1
0xFFF
EGR2_ETH2_VLAN_TAG1_MATC 11:0
H
R/W
Match value for the first VLAN tag
0x000
VMDS-10510 VSC8574-02 Datasheet Revision 4.2
330
4.13.5.7
ETHERNET_COMPARATOR:EGR2_ETH2_FLOW_CFG:EGR2_ETH2_VLAN_TA
G2_I_TAG
Parent: ETHERNET_COMPARATOR:EGR2_ETH2_FLOW_CFG
Instances: 1
Table 615 • Fields in EGR2_ETH2_VLAN_TAG2_I_TAG
Field Name
Access
Description
Default
EGR2_ETH2_VLAN_TAG2_MASK 27:16
R/W
Mask field for VLAN tag 2
0xFFF
EGR2_ETH2_VLAN_TAG2_MATC 11:0
H
R/W
Match field for VLAN Tag 2
0x000
4.13.6
Bit
ETHERNET_COMPARATOR:EGR2_MPLS_NXT_COMPARATOR_A
Parent: Egress0 Ethernet Comparator
Instances: 1
Table 616 • Registers in EGR2_MPLS_NXT_COMPARATOR_A
Register Name
Instances and
Offset within
Address
Register Group Spacing
EGR2_MPLS_NXT_COMPARATO 0x00000000
R_A
4.13.6.1
1
Description
Details
MPLS next protocol
comparator register
Page 331
ETHERNET_COMPARATOR:EGR2_MPLS_NXT_COMPARATOR_A:EGR2_MP
LS_NXT_COMPARATOR_A
Parent: ETHERNET_COMPARATOR:EGR2_MPLS_NXT_COMPARATOR_A
Instances: 1
Table 617 • Fields in EGR2_MPLS_NXT_COMPARATOR_A
Field Name
Bit
Access
Description
EGR2_MPLS_CTL_WORD_A
16
R/W
Indicates the presence of a control word after 0x0
the last label
0: No control ward after the last label
1: Control word after the last label
EGR2_MPLS_NXT_COMPARATO 2:0
R_A
R/W
Points to the next comparator stage. If this
0x0
comparator block is not used, this field must
be set to 0.
0: Comparator block not used
1: Ethernet comparator 2
2: IP/UDP/ACH comparator 1
3: IP/UDP/ACH comparator 2
4: Reserved
5: PTP/OAM comparator
6,7: Reserved
VMDS-10510 VSC8574-02 Datasheet Revision 4.2
Default
331
4.13.7
ETHERNET_COMPARATOR:EGR2_MPLS_FLOW_CFG
Parent: Egress0 Ethernet Comparator
Instances: 8
Table 618 • Registers in EGR2_MPLS_FLOW_CFG
Register Name
Instances and
Offset within
Address
Register Group Spacing
Description
Details
EGR2_MPLS_FLOW_CONTROL
0x00000000
1
MPLS flow control register
Page 332
EGR2_MPLS_LABEL_RANGE_L
OWER_0
0x00000004
1
MPLS label 0 match range
lower value
Page 333
EGR2_MPLS_LABEL_RANGE_U 0x00000008
PPER_0
1
MPLS label 0 match range
upper value
Page 333
EGR2_MPLS_LABEL_RANGE_L
OWER_1
0x0000000C
1
MPLS label 1 match range
lower value
Page 333
EGR2_MPLS_LABEL_RANGE_U 0x00000010
PPER_1
1
MPLS label 1 match range
upper value
Page 334
EGR2_MPLS_LABEL_RANGE_L
OWER_2
0x00000014
1
MPLS label 2 match range
lower value
Page 334
EGR2_MPLS_LABEL_RANGE_U 0x00000018
PPER_2
1
MPLS label 2 match range
upper value
Page 334
EGR2_MPLS_LABEL_RANGE_L
OWER_3
0x0000001C
1
MPLS label 3 match range
lower value
Page 334
EGR2_MPLS_LABEL_RANGE_U 0x00000020
PPER_3
1
MPLS label 3 match range
upper value
Page 335
4.13.7.1
ETHERNET_COMPARATOR:EGR2_MPLS_FLOW_CFG:EGR2_MPLS_FLOW_
CONTROL
Parent: ETHERNET_COMPARATOR:EGR2_MPLS_FLOW_CFG
Instances: 1
Table 619 • Fields in EGR2_MPLS_FLOW_CONTROL
Field Name
Bit
Access
Description
Default
EGR2_MPLS_CHANNEL_MASK
25:24
R/W
Channel Mask
0x0: Flow invalid
0x1: Flow valid for channel 0
0x2: Flow valid for channel 1
0x3: Flow valid for both channels
0x3
VMDS-10510 VSC8574-02 Datasheet Revision 4.2
332
Table 619 • Fields in EGR2_MPLS_FLOW_CONTROL (continued)
Field Name
Bit
Access
Description
Default
EGR2_MPLS_STACK_DEPTH
19:16
R/W
Defines the allowable stack depths for
searches. The direction that the stack is
referenced is determined by the setting of
MPLS_REF_PNT. The following table maps
bits to stack depths:
0: Stack allowed to be 1 label deep
1: Stack allowed to be 2 labels deep
2: Stack allowed to be 3 labels deep
3: Stack allowed to be 4 labels deep
0x0
EGR2_MPLS_REF_PNT
4
R/W
Defines the search direction for label
0x0
matching
0: All searching is performed starting from the
top of the stack
1: All searching is performed from the end of
the stack
EGR2_MPLS_FLOW_ENA
0
R/W
Flow enable.
If this comparator block is not used, all flow
enable bits must be set to 0.
0: Flow is disabled
1: Flow is enabled
4.13.7.2
0x0
ETHERNET_COMPARATOR:EGR2_MPLS_FLOW_CFG:EGR2_MPLS_LABEL_
RANGE_LOWER_0
Parent: ETHERNET_COMPARATOR:EGR2_MPLS_FLOW_CFG
Instances: 1
Table 620 • Fields in EGR2_MPLS_LABEL_RANGE_LOWER_0
Field Name
Bit
Access
Description
Default
EGR2_MPLS_LABEL_RANGE_L
OWER_0
19:0
R/W
Lower value for label 0 match range
0x00000
4.13.7.3
ETHERNET_COMPARATOR:EGR2_MPLS_FLOW_CFG:EGR2_MPLS_LABEL_
RANGE_UPPER_0
Parent: ETHERNET_COMPARATOR:EGR2_MPLS_FLOW_CFG
Instances: 1
Table 621 • Fields in EGR2_MPLS_LABEL_RANGE_UPPER_0
Field Name
Bit
EGR2_MPLS_LABEL_RANGE_U 19:0
PPER_0
4.13.7.4
Access
Description
Default
R/W
Upper value for label 0 match range
0xFFFFF
ETHERNET_COMPARATOR:EGR2_MPLS_FLOW_CFG:EGR2_MPLS_LABEL_
RANGE_LOWER_1
Parent: ETHERNET_COMPARATOR:EGR2_MPLS_FLOW_CFG
VMDS-10510 VSC8574-02 Datasheet Revision 4.2
333
Instances: 1
Table 622 • Fields in EGR2_MPLS_LABEL_RANGE_LOWER_1
Field Name
Bit
Access
Description
Default
EGR2_MPLS_LABEL_RANGE_L
OWER_1
19:0
R/W
Lower value for label 1 match range
0x00000
4.13.7.5
ETHERNET_COMPARATOR:EGR2_MPLS_FLOW_CFG:EGR2_MPLS_LABEL_
RANGE_UPPER_1
Parent: ETHERNET_COMPARATOR:EGR2_MPLS_FLOW_CFG
Instances: 1
Table 623 • Fields in EGR2_MPLS_LABEL_RANGE_UPPER_1
Field Name
Bit
EGR2_MPLS_LABEL_RANGE_U 19:0
PPER_1
4.13.7.6
Access
Description
Default
R/W
Upper value for label 1 match range
0xFFFFF
ETHERNET_COMPARATOR:EGR2_MPLS_FLOW_CFG:EGR2_MPLS_LABEL_
RANGE_LOWER_2
Parent: ETHERNET_COMPARATOR:EGR2_MPLS_FLOW_CFG
Instances: 1
Table 624 • Fields in EGR2_MPLS_LABEL_RANGE_LOWER_2
Field Name
Bit
Access
Description
Default
EGR2_MPLS_LABEL_RANGE_L
OWER_2
19:0
R/W
Lower value for label 2 match range
0x00000
4.13.7.7
ETHERNET_COMPARATOR:EGR2_MPLS_FLOW_CFG:EGR2_MPLS_LABEL_
RANGE_UPPER_2
Parent: ETHERNET_COMPARATOR:EGR2_MPLS_FLOW_CFG
Instances: 1
Table 625 • Fields in EGR2_MPLS_LABEL_RANGE_UPPER_2
Field Name
Bit
EGR2_MPLS_LABEL_RANGE_U 19:0
PPER_2
4.13.7.8
Access
Description
Default
R/W
Upper value for label 2 match range
0xFFFFF
ETHERNET_COMPARATOR:EGR2_MPLS_FLOW_CFG:EGR2_MPLS_LABEL_
RANGE_LOWER_3
Parent: ETHERNET_COMPARATOR:EGR2_MPLS_FLOW_CFG
Instances: 1
VMDS-10510 VSC8574-02 Datasheet Revision 4.2
334
Table 626 • Fields in EGR2_MPLS_LABEL_RANGE_LOWER_3
Field Name
Bit
Access
Description
Default
EGR2_MPLS_LABEL_RANGE_L
OWER_3
19:0
R/W
Lower value for label 3 match range
0x00000
4.13.7.9
ETHERNET_COMPARATOR:EGR2_MPLS_FLOW_CFG:EGR2_MPLS_LABEL_
RANGE_UPPER_3
Parent: ETHERNET_COMPARATOR:EGR2_MPLS_FLOW_CFG
Instances: 1
Table 627 • Fields in EGR2_MPLS_LABEL_RANGE_UPPER_3
Field Name
Bit
EGR2_MPLS_LABEL_RANGE_U 19:0
PPER_3
4.13.8
Access
Description
Default
R/W
Upper value for label 3 match range
0xFFFFF
ETHERNET_COMPARATOR:EGR2_PTP_FLOW
Parent: Egress0 Ethernet Comparator
Instances: 6
Table 628 • Registers in EGR2_PTP_FLOW
Register Name
Instances and
Offset within
Address
Register Group Spacing
Description
Details
EGR2_PTP_FLOW_ENA
0x00000000
1
PTP/OAM flow enable
Page 335
EGR2_PTP_FLOW_MATCH_UPP 0x00000004
ER
1
Upper half of PTP/OAM flow
match field
Page 336
EGR2_PTP_FLOW_MATCH_LOW 0x00000008
ER
1
Lower half of PTP/OAM flow
match field
Page 336
EGR2_PTP_FLOW_MASK_UPPE 0x0000000C
R
1
Upper half of PTP/OAM flow
match mask
Page 336
EGR2_PTP_FLOW_MASK_LOWE 0x00000010
R
1
Lower half of PTP/OAM flow
match mask
Page 337
EGR2_PTP_DOMAIN_RANGE
0x00000014
1
PTP/OAM range match
register
Page 337
EGR2_PTP_ACTION
0x00000018
1
PTP action control register
Page 337
EGR2_PTP_ACTION_2
0x0000001C
1
PTP action control register 2
Page 338
EGR2_PTP_ZERO_FIELD_CTL
0x00000020
1
Zero field control register
Page 339
4.13.8.1
ETHERNET_COMPARATOR:EGR2_PTP_FLOW:EGR2_PTP_FLOW_ENA
Parent: ETHERNET_COMPARATOR:EGR2_PTP_FLOW
Instances: 1
VMDS-10510 VSC8574-02 Datasheet Revision 4.2
335
Table 629 • Fields in EGR2_PTP_FLOW_ENA
Field Name
Access
Description
EGR2_PTP_NXT_PROT_GRP_M 17:16
ASK
R/W
Indicates the next protocol groups that this
0x3
flow is valid for. For each next protocol group,
if the bit is 1, then this flow is valid for that
group. If it is 0, then it is not valid for the
group.
0: Mask bit for next protocol group A
1: Mask bit for next protocol group B
EGR2_PTP_CHANNEL_MASK
5:4
R/W
Channel mask
0x0: Flow invalid
0x1: Flow valid for channel 0
0x2: Flow valid for channel 1
0x3: Flow valid for both channels
0x3
EGR2_PTP_FLOW_ENA
0
R/W
Flow enable
0x0
4.13.8.2
Bit
Default
ETHERNET_COMPARATOR:EGR2_PTP_FLOW:EGR2_PTP_FLOW_MATCH_U
PPER
Parent: ETHERNET_COMPARATOR:EGR2_PTP_FLOW
Instances: 1
Table 630 • Fields in EGR2_PTP_FLOW_MATCH_UPPER
Field Name
Bit
EGR2_PTP_FLOW_MATCH_UPP 31:0
ER
4.13.8.3
Access
Description
R/W
Default
0x00000000
ETHERNET_COMPARATOR:EGR2_PTP_FLOW:EGR2_PTP_FLOW_MATCH_L
OWER
Parent: ETHERNET_COMPARATOR:EGR2_PTP_FLOW
Instances: 1
Table 631 • Fields in EGR2_PTP_FLOW_MATCH_LOWER
Field Name
Bit
EGR2_PTP_FLOW_MATCH_LOW 31:0
ER
4.13.8.4
Access
Description
R/W
Default
0x00000000
ETHERNET_COMPARATOR:EGR2_PTP_FLOW:EGR2_PTP_FLOW_MASK_UP
PER
Parent: ETHERNET_COMPARATOR:EGR2_PTP_FLOW
Instances: 1
VMDS-10510 VSC8574-02 Datasheet Revision 4.2
336
Table 632 • Fields in EGR2_PTP_FLOW_MASK_UPPER
Field Name
Bit
EGR2_PTP_FLOW_MASK_UPPE 31:0
R
4.13.8.5
Access
Description
R/W
Default
0x00000000
ETHERNET_COMPARATOR:EGR2_PTP_FLOW:EGR2_PTP_FLOW_MASK_LO
WER
Parent: ETHERNET_COMPARATOR:EGR2_PTP_FLOW
Instances: 1
Table 633 • Fields in EGR2_PTP_FLOW_MASK_LOWER
Field Name
Bit
EGR2_PTP_FLOW_MASK_LOWE 31:0
R
4.13.8.6
Access
Description
R/W
Default
0x00000000
ETHERNET_COMPARATOR:EGR2_PTP_FLOW:EGR2_PTP_DOMAIN_RANGE
Parent: ETHERNET_COMPARATOR:EGR2_PTP_FLOW
Instances: 1
Table 634 • Fields in EGR2_PTP_DOMAIN_RANGE
Field Name
Bit
Access
Description
Default
EGR2_PTP_DOMAIN_RANGE_O 28:24
FFSET
R/W
PTP domain range offset
0x00
EGR2_PTP_DOMAIN_RANGE_U 23:16
PPER
R/W
Upper range of PTP domain field to match
0xFF
EGR2_PTP_DOMAIN_RANGE_L
OWER
R/W
Lower range of PTP domain field to match
0x00
R/W
Enable PTP domain range checking
0x0
15:8
EGR2_PTP_DOMAIN_RANGE_E 0
NA
4.13.8.7
ETHERNET_COMPARATOR:EGR2_PTP_FLOW:EGR2_PTP_ACTION
Parent: ETHERNET_COMPARATOR:EGR2_PTP_FLOW
Instances: 1
Table 635 • Fields in EGR2_PTP_ACTION
Field Name
Bit
EGR2_PTP_MOD_FRAME_STAT 28
_UPDATE
Access
Description
R/W
Default
0x0
0: Do not signal the rewriter to update the
value of the Modified Frame Status bit
1: Signal the rewriter to update the value of
the Modified Frame Status bit
VMDS-10510 VSC8574-02 Datasheet Revision 4.2
337
Table 635 • Fields in EGR2_PTP_ACTION (continued)
Field Name
Bit
Access
Description
Default
EGR2_PTP_MOD_FRAME_BYTE 26:24
_OFFSET
R/W
Indicates the position relative to the start of
the PTP frame in bytes where the Modified
Frame Status bit resides
0x0
EGR2_PTP_SUB_DELAY_ASYM_ 21
ENA
R/W
EGR2_PTP_ADD_DELAY_ASYM 20
_ENA
R/W
EGR2_PTP_TIME_STRG_FIELD_ 15:10
OFFSET
R/W
EGR2_PTP_CORR_FIELD_OFFS 9:5
ET
R/W
Points to the location of the correction field
for updating the timestamp. Location is
relative to the first byte of the PTP/OAM
header.
Note: If this flow is being used to
match OAM frames, set this
register to 4
EGR2_PTP_SAVE_LOCAL_TIME 4
R/W
Save local time to the timestamp FIFO
0x0
0: Do not save the time to the timestamp
FIFO
1: Save the local time to the timestamp FIFO
EGR2_PTP_COMMAND
R/W
3:0
0x0
0: Do not signal the timestamp block to
subtract the asymmetry delay
1: Signal the timestamp block to subtract the
asymmetry delay
0x0
0: Do not signal the timestamp block to add
the asymmetry delay
1: Signal the timestamp block to add the
asymmetry delay
0x00
0x00
0x0
0: NOP
1: SUB
2: SUB_P2P
3: ADD
4: SUB_ADD
5: WRITE_1588
6: WRITE_P2P (deprecated)
7: WRITE_NS
8: WRITE_NS_P2P
4.13.8.8
ETHERNET_COMPARATOR:EGR2_PTP_FLOW:EGR2_PTP_ACTION_2
Parent: ETHERNET_COMPARATOR:EGR2_PTP_FLOW
Instances: 1
Table 636 • Fields in EGR2_PTP_ACTION_2
Field Name
Bit
Access
Description
EGR2_PTP_NEW_CF_LOC
23:16
R/W
Location of the new correction field relative to 0x00
the PTP header start. Only even values are
allowed.
VMDS-10510 VSC8574-02 Datasheet Revision 4.2
Default
338
Table 636 • Fields in EGR2_PTP_ACTION_2 (continued)
Field Name
Bit
Access
Description
Default
EGR2_PTP_REWRITE_OFFSET
15:8
R/W
Points to where in the frame relative to the
SFD that the timestamp should be updated
0x00
EGR2_PTP_REWRITE_BYTES
3:0
R/W
Number of bytes in the PTP or OAM frame
that must be modified by the rewriter for the
timestamp
0x0
4.13.8.9
ETHERNET_COMPARATOR:EGR2_PTP_FLOW:EGR2_PTP_ZERO_FIELD_CT
L
Parent: ETHERNET_COMPARATOR:EGR2_PTP_FLOW
Instances: 1
Table 637 • Fields in EGR2_PTP_ZERO_FIELD_CTL
Field Name
Access
Description
EGR2_PTP_ZERO_FIELD_OFFS 13:8
ET
R/W
0x00
Points to a location in the PTP/OAM frame
relative to the start of the PTP header that will
be zeroed if this function is enabled
EGR2_PTP_ZERO_FIELD_BYTE 3:0
_CNT
R/W
The number of bytes to be zeroed. If this field 0x0
is 0, then this function is not enabled.
4.14
Bit
Default
Ingress2 Ethernet Comparator
Table 638 • Register Groups in Ingress2 Ethernet Comparator
Offset within
Target
Register Group Name
Instances and
Address
Spacing
Description
Details
INGR2_ETH1_NXT_PROTOCOL_ 0x00000000
A
1
Ethernet next protocol
configuration
Page 340
INGR2_ETH1_NXT_PROTOCOL_ 0x00000040
B
1
Ethernet next protocol
configuration
Page 341
INGR2_ETH1_FLOW_CFG
8
0x00000040
Ethernet flow configuration
Page 343
INGR2_ETH2_NXT_PROTOCOL_ 0x00000280
A
1
Ethernet next protocol
configuration
Page 347
INGR2_ETH2_FLOW_CFG
0x00000300
8
0x00000040
Ethernet flow configuration
Page 348
INGR2_MPLS_NXT_COMPARAT
OR_A
0x00000500
1
MPLS next protocol register
Page 351
INGR2_MPLS_FLOW_CFG
0x00000580
8
0x00000040
MPLS flow configuration
Page 352
INGR2_PTP_FLOW
0x00000780
6
0x00000040
PTP flow configuration
Page 356
0x00000080
VMDS-10510 VSC8574-02 Datasheet Revision 4.2
339
4.14.1
ETHERNET_COMPARATOR:INGR2_ETH1_NXT_PROTOCOL_A
Parent: Egress0 Ethernet Comparator
Instances: 1
Table 639 • Registers in INGR2_ETH1_NXT_PROTOCOL_A
Register Name
Instances and
Offset within
Address
Register Group Spacing
Description
Details
INGR2_ETH1_NXT_PROTOCOL_ 0x00000000
A
1
Ethernet next protocol register Page 340
INGR2_ETH1_VLAN_TPID_CFG_ 0x00000004
A
1
VLAN TPID configuration
Page 340
INGR2_ETH1_TAG_MODE_A
0x00000008
1
Ethernet tag mode
Page 341
INGR2_ETH1_ETYPE_MATCH_A 0x0000000C
1
Ethertype match register
Page 341
4.14.1.1
ETHERNET_COMPARATOR:INGR2_ETH1_NXT_PROTOCOL_A:INGR2_ETH1_
NXT_PROTOCOL_A
Parent: ETHERNET_COMPARATOR:INGR2_ETH1_NXT_PROTOCOL_A
Instances: 1
Table 640 • Fields in INGR2_ETH1_NXT_PROTOCOL_A
Field Name
Bit
INGR2_ETH1_NXT_COMPARATO 2:0
R_A
4.14.1.2
Access
Description
Default
R/W
Points to the next comparator block after this 0x0
Ethernet block
0: Reserved
1: Ethernet comparator 2
2: IP/UDP/ACH comparator 1
3: IP/UDP/ACH comparator 2
4: MPLS comparator
5: PTP/OAM comparator
6,7: Reserved
ETHERNET_COMPARATOR:INGR2_ETH1_NXT_PROTOCOL_A:INGR2_ETH1_
VLAN_TPID_CFG_A
Parent: ETHERNET_COMPARATOR:INGR2_ETH1_NXT_PROTOCOL_A
Instances: 1
Table 641 • Fields in INGR2_ETH1_VLAN_TPID_CFG_A
Field Name
Bit
INGR2_ETH1_VLAN_TPID_CFG_ 31:16
A
Access
Description
Default
R/W
Configurable VLAN TPID (S or B-tag)
0x88A8
VMDS-10510 VSC8574-02 Datasheet Revision 4.2
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4.14.1.3
ETHERNET_COMPARATOR:INGR2_ETH1_NXT_PROTOCOL_A:INGR2_ETH1_
TAG_MODE_A
Parent: ETHERNET_COMPARATOR:INGR2_ETH1_NXT_PROTOCOL_A
Instances: 1
Table 642 • Fields in INGR2_ETH1_TAG_MODE_A
Field Name
Bit
Access
Description
INGR2_ETH1_PBB_ENA_A
0
R/W
This bit enables the presence of PBB.
0x0
The I-tag match bits are programmed in the
ETH1_VLAN_TAG_RANGE registers. The
mask bits are programmed in the
ETH1_VLAN_TAG2 registers. A B-tag if
present is configured in the
ETH1_VLAN_TAG1 registers.
0: PBB not enabled
1: Always expect PBB, last tag is always an Itag
4.14.1.4
Default
ETHERNET_COMPARATOR:INGR2_ETH1_NXT_PROTOCOL_A:INGR2_ETH1_
ETYPE_MATCH_A
Parent: ETHERNET_COMPARATOR:INGR2_ETH1_NXT_PROTOCOL_A
Instances: 1
Table 643 • Fields in INGR2_ETH1_ETYPE_MATCH_A
Field Name
Bit
INGR2_ETH1_ETYPE_MATCH_A 15:0
4.14.2
Access
Description
Default
R/W
If the Ethertype/length field is an Ethertype, 0x0000
then this register is compared against the
value. If the field is a length, the length value
is not checked.
ETHERNET_COMPARATOR:INGR2_ETH1_NXT_PROTOCOL_B
Parent: Egress0 Ethernet Comparator
Instances: 1
Table 644 • Registers in INGR2_ETH1_NXT_PROTOCOL_B
Register Name
Instances and
Offset within
Address
Register Group Spacing
Description
Details
INGR2_ETH1_NXT_PROTOCOL_ 0x00000000
B
1
Ethernet next protocol register Page 342
INGR2_ETH1_VLAN_TPID_CFG_ 0x00000004
B
1
VLAN TPID configuration
Page 342
INGR2_ETH1_TAG_MODE_B
0x00000008
1
Ethernet tag mode
Page 342
INGR2_ETH1_ETYPE_MATCH_B 0x0000000C
1
Ethertype match register
Page 343
VMDS-10510 VSC8574-02 Datasheet Revision 4.2
341
4.14.2.1
ETHERNET_COMPARATOR:INGR2_ETH1_NXT_PROTOCOL_B:INGR2_ETH1_
NXT_PROTOCOL_B
Parent: ETHERNET_COMPARATOR:INGR2_ETH1_NXT_PROTOCOL_B
Instances: 1
Table 645 • Fields in INGR2_ETH1_NXT_PROTOCOL_B
Field Name
Bit
INGR2_ETH1_NXT_COMPARATO 2:0
R_B
4.14.2.2
Access
Description
Default
R/W
Points to the next comparator block after this 0x0
Ethernet block
0: Reserved
1: Ethernet comparator 2
2: IP/UDP/ACH comparator 1
3: IP/UDP/ACH comparator 2
4: MPLS comparator
5: PTP/OAM comparator
6,7: Reserved
ETHERNET_COMPARATOR:INGR2_ETH1_NXT_PROTOCOL_B:INGR2_ETH1_
VLAN_TPID_CFG_B
Parent: ETHERNET_COMPARATOR:INGR2_ETH1_NXT_PROTOCOL_B
Instances: 1
Table 646 • Fields in INGR2_ETH1_VLAN_TPID_CFG_B
Field Name
Bit
INGR2_ETH1_VLAN_TPID_CFG_ 15:0
B
4.14.2.3
Access
Description
Default
R/W
Configurable VLAN TPID (S or B-tag)
0x88A8
ETHERNET_COMPARATOR:INGR2_ETH1_NXT_PROTOCOL_B:INGR2_ETH1_
TAG_MODE_B
Parent: ETHERNET_COMPARATOR:INGR2_ETH1_NXT_PROTOCOL_B
Instances: 1
Table 647 • Fields in INGR2_ETH1_TAG_MODE_B
Field Name
Bit
Access
Description
INGR2_ETH1_PBB_ENA_B
0
R/W
This bit enables the presence of PBB.
0x0
The I-tag match bits are programmed in the
ETH1_VLAN_TAG_RANGE registers. The
mask bits are programmed in the
ETH1_VLAN_TAG2 registers. A B-tag if
present is configured in the
ETH1_VLAN_TAG1 registers.
0: PBB not enabled
1: Always expect PBB, last tag is always an Itag
VMDS-10510 VSC8574-02 Datasheet Revision 4.2
Default
342
4.14.2.4
ETHERNET_COMPARATOR:INGR2_ETH1_NXT_PROTOCOL_B:INGR2_ETH1_
ETYPE_MATCH_B
Parent: ETHERNET_COMPARATOR:INGR2_ETH1_NXT_PROTOCOL_B
Instances: 1
Table 648 • Fields in INGR2_ETH1_ETYPE_MATCH_B
Field Name
Bit
INGR2_ETH1_ETYPE_MATCH_B 15:0
4.14.3
Access
Description
Default
R/W
If the Ethertype/length field is an Ethertype, 0x0000
then this register is compared against the
value. If the field is a length, the length value
is not checked.
ETHERNET_COMPARATOR:INGR2_ETH1_FLOW_CFG
Parent: Egress0 Ethernet Comparator
Instances: 8
Table 649 • Registers in INGR2_ETH1_FLOW_CFG
Register Name
Instances and
Offset within
Address
Register Group Spacing
Description
Details
INGR2_ETH1_FLOW_ENABLE
0x00000000
1
Ethernet flow enable
Page 343
INGR2_ETH1_MATCH_MODE
0x00000004
1
Ethernet protocol match mode Page 344
INGR2_ETH1_ADDR_MATCH_1
0x00000008
1
Ethernet address match part 1 Page 345
INGR2_ETH1_ADDR_MATCH_2
0x0000000C
1
Ethernet address match part 2 Page 345
INGR2_ETH1_VLAN_TAG_RANG 0x00000010
E_I_TAG
1
Ethernet VLAN tag range
match register
Page 346
INGR2_ETH1_VLAN_TAG1
0x00000014
1
VLAN tag 1 match/mask
Page 346
INGR2_ETH1_VLAN_TAG2_I_TA 0x00000018
G
1
Match/mask for VLAN tag 2 or Page 346
I-tag match
4.14.3.1
ETHERNET_COMPARATOR:INGR2_ETH1_FLOW_CFG:INGR2_ETH1_FLOW_
ENABLE
Parent: ETHERNET_COMPARATOR:INGR2_ETH1_FLOW_CFG
Instances: 1
VMDS-10510 VSC8574-02 Datasheet Revision 4.2
343
Table 650 • Fields in INGR2_ETH1_FLOW_ENABLE
Field Name
Access
Description
Default
INGR2_ETH1_NXT_PROT_GRP_ 16
SEL
R/W
Indicates which next-protocol configuration
group is valid with this flow
0: Associate this flow with next-protocol
group A
1: Associate this flow with next-protocol
group B
0x0
INGR2_ETH1_CHANNEL_MASK
9:8
R/W
Channel mask
0x0: Flow invalid
0x1: Flow valid for channel 0
0x2: Flow valid for channel 1
0x3: Flow valid for both channels
0x3
INGR2_ETH1_FLOW_ENABLE
0
R/W
Flow enable
0: Flow disabled
1: Flow enabled
0x0
4.14.3.2
Bit
ETHERNET_COMPARATOR:INGR2_ETH1_FLOW_CFG:INGR2_ETH1_MATCH
_MODE
Parent: ETHERNET_COMPARATOR:INGR2_ETH1_FLOW_CFG
Instances: 1
Table 651 • Fields in INGR2_ETH1_MATCH_MODE
Field Name
Bit
INGR2_ETH1_VLAN_TAG_MODE 13:12
Access
Description
R/W
Default
0x0
0: VLAN range checking disabled
1: VLAN range checking on tag 1
2: VLAN range checking on tag 2 (not
supported with PBB)
3: Reserved
INGR2_ETH1_VLAN_TAG2_TYP
E
9
R/W
This register is only used if
ETH1_VLAN_VERIFY_ENA = 1
If PBB not enabled:
0: C tag (TPID of 0x8100)
1: S tag (match to CONF_VLAN_TPID)
If PBB enabled:
0,1: I tag (use range registers)
INGR2_ETH1_VLAN_TAG1_TYP
E
8
R/W
This register is only used if
0x0
ETH1_VLAN_VERIFY_ENA = 1
0: C tag (TPID of 0x8100)
1: S or B tag (match to CONF_VLAN_TPID)
VMDS-10510 VSC8574-02 Datasheet Revision 4.2
0x1
344
Table 651 • Fields in INGR2_ETH1_MATCH_MODE (continued)
Field Name
Bit
Access
Description
INGR2_ETH1_VLAN_TAGS
7:6
R/W
This register is only used if
0x0
ETH1_VLAN_VERIFY_ENA = 1
0: No VLAN tags (not valid for PBB)
1: 1 VLAN tag (for PBB this would be the Itag)
2: 2 VLAN tags (for PBB expect a B-tag and
an I-tag)
3: Reserved
INGR2_ETH1_VLAN_VERIFY_EN 4
A
R/W
INGR2_ETH1_ETHERTYPE_MO
DE
R/W
4.14.3.3
0
Default
0x0
0: Parse for VLAN tags; do not check values.
For PBB the I-tag is always checked.
1: Verify configured VLAN tag configuration.
When checking for presence of SNAP/LLC
0x0
based upon ETH1_MATCH_MODE, this field
indicates if SNAP and 3-byte LLC is expected
to be present.
0: Only Ethernet type II supported, no
SNAP/LLC
1: Ethernet type II and Ethernet type I with
SNAP/LLC, determine if SNAP/LLC is
present or not. Type I always assumes that
SNAP/LLC is present.
ETHERNET_COMPARATOR:INGR2_ETH1_FLOW_CFG:INGR2_ETH1_ADDR_
MATCH_1
Parent: ETHERNET_COMPARATOR:INGR2_ETH1_FLOW_CFG
Instances: 1
Table 652 • Fields in INGR2_ETH1_ADDR_MATCH_1
Field Name
Bit
Access
Description
Default
INGR2_ETH1_ADDR_MATCH_1
31:0
R/W
First 32 bits of the address match value
0x00000000
4.14.3.4
ETHERNET_COMPARATOR:INGR2_ETH1_FLOW_CFG:INGR2_ETH1_ADDR_
MATCH_2
Parent: ETHERNET_COMPARATOR:INGR2_ETH1_FLOW_CFG
Instances: 1
Table 653 • Fields in INGR2_ETH1_ADDR_MATCH_2
Field Name
Bit
Access
Description
INGR2_ETH1_ADDR_MATCH_M
ODE
22:20
R/W
Selects how the addresses are matched.
0x1
One-hot encoded. Multiple bits can be set at
once.
0: Full 48-bit address match
1: Match any unicast address
2: Match any muliticast address
VMDS-10510 VSC8574-02 Datasheet Revision 4.2
Default
345
Table 653 • Fields in INGR2_ETH1_ADDR_MATCH_2 (continued)
Field Name
Access
Description
Default
INGR2_ETH1_ADDR_MATCH_SE 17:16
LECT
R/W
Selects which address to match
0: Match the destination address
1: Match the source address
2: Match either the source of destination
address
3: Reserved
0x0
INGR2_ETH1_ADDR_MATCH_2
R/W
Last 16 bits of the Ethernet address match
field
0x0000
4.14.3.5
Bit
15:0
ETHERNET_COMPARATOR:INGR2_ETH1_FLOW_CFG:INGR2_ETH1_VLAN_T
AG_RANGE_I_TAG
Parent: ETHERNET_COMPARATOR:INGR2_ETH1_FLOW_CFG
Instances: 1
Table 654 • Fields in INGR2_ETH1_VLAN_TAG_RANGE_I_TAG
Field Name
Access
Description
INGR2_ETH1_VLAN_TAG_RANG 27:16
E_UPPER
R/W
If PBB mode is not enabled, then this register 0xFFF
contains the upper range of the VLAN tag
range match.
If PBB mode is enabled, then this register
contains the upper 12 bits of the I-tag.
INGR2_ETH1_VLAN_TAG_RANG 11:0
E_LOWER
R/W
If PBB mode is not enabled, then this register 0x000
contains the lower range of the VLAN tag
range match.
If PBB mode is enabled, then this register
contains the lower 12 bits of the I-tag.
4.14.3.6
Bit
Default
ETHERNET_COMPARATOR:INGR2_ETH1_FLOW_CFG:INGR2_ETH1_VLAN_T
AG1
Parent: ETHERNET_COMPARATOR:INGR2_ETH1_FLOW_CFG
Instances: 1
Table 655 • Fields in INGR2_ETH1_VLAN_TAG1
Field Name
Access
Description
Default
INGR2_ETH1_VLAN_TAG1_MAS 27:16
K
R/W
Mask value for VLAN tag 1
0xFFF
INGR2_ETH1_VLAN_TAG1_MAT 11:0
CH
R/W
Match value for the first VLAN tag
0x000
4.14.3.7
Bit
ETHERNET_COMPARATOR:INGR2_ETH1_FLOW_CFG:INGR2_ETH1_VLAN_T
AG2_I_TAG
Parent: ETHERNET_COMPARATOR:INGR2_ETH1_FLOW_CFG
Instances: 1
VMDS-10510 VSC8574-02 Datasheet Revision 4.2
346
Table 656 • Fields in INGR2_ETH1_VLAN_TAG2_I_TAG
Field Name
Access
Description
INGR2_ETH1_VLAN_TAG2_MAS 27:16
K
R/W
When PBB is not enabled, the mask field for 0xFFF
VLAN tag 2
When PBB is enabled, the upper 12 bits of
the I-tag mask
INGR2_ETH1_VLAN_TAG2_MAT 11:0
CH
R/W
When PBB is not enabled, the match field for 0x000
VLAN Tag 2
When PBB is enabled, the lower 12 bits of
the I-tag mask field
4.14.4
Bit
Default
ETHERNET_COMPARATOR:INGR2_ETH2_NXT_PROTOCOL_A
Parent: Egress0 Ethernet Comparator
Instances: 1
Table 657 • Registers in INGR2_ETH2_NXT_PROTOCOL_A
Register Name
Instances and
Offset within
Address
Register Group Spacing
Description
Details
INGR2_ETH2_NXT_PROTOCOL_ 0x00000000
A
1
Ethernet next protocol register Page 347
INGR2_ETH2_VLAN_TPID_CFG_ 0x00000004
A
1
VLAN TPID configuration
Page 348
INGR2_ETH2_ETYPE_MATCH_A 0x00000008
1
Ethertype match register
Page 348
4.14.4.1
ETHERNET_COMPARATOR:INGR2_ETH2_NXT_PROTOCOL_A:INGR2_ETH2_
NXT_PROTOCOL_A
Parent: ETHERNET_COMPARATOR:INGR2_ETH2_NXT_PROTOCOL_A
Instances: 1
Table 658 • Fields in INGR2_ETH2_NXT_PROTOCOL_A
Field Name
Bit
INGR2_ETH2_NXT_COMPARATO 2:0
R_A
Access
Description
R/W
Points to the next comparator block after this 0x0
Ethernet block. If this comparator block is not
used, this field must be set to 0.
0: Comparator block not used
1: Ethernet comparator 2
2: IP/UDP/ACH comparator 1
3: IP/UDP/ACH comparator 2
4: MPLS comparator
5: PTP/OAM comparator
6,7: Reserved
VMDS-10510 VSC8574-02 Datasheet Revision 4.2
Default
347
4.14.4.2
ETHERNET_COMPARATOR:INGR2_ETH2_NXT_PROTOCOL_A:INGR2_ETH2_
VLAN_TPID_CFG_A
Parent: ETHERNET_COMPARATOR:INGR2_ETH2_NXT_PROTOCOL_A
Instances: 1
Table 659 • Fields in INGR2_ETH2_VLAN_TPID_CFG_A
Field Name
Bit
INGR2_ETH2_VLAN_TPID_CFG_ 31:16
A
4.14.4.3
Access
Description
Default
R/W
Configurable S-tag TPID
0x88A8
ETHERNET_COMPARATOR:INGR2_ETH2_NXT_PROTOCOL_A:INGR2_ETH2_
ETYPE_MATCH_A
Parent: ETHERNET_COMPARATOR:INGR2_ETH2_NXT_PROTOCOL_A
Instances: 1
Table 660 • Fields in INGR2_ETH2_ETYPE_MATCH_A
Field Name
Bit
INGR2_ETH2_ETYPE_MATCH_A 15:0
4.14.5
Access
Description
Default
R/W
If the Ethertype/length field is an Ethertype, 0x0000
then this register is compared against the
value. If the field is a length, the length value
is not checked.
ETHERNET_COMPARATOR:INGR2_ETH2_FLOW_CFG
Parent: Egress0 Ethernet Comparator
Instances: 8
Table 661 • Registers in INGR2_ETH2_FLOW_CFG
Register Name
Instances and
Offset within
Address
Register Group Spacing
Description
Details
INGR2_ETH2_FLOW_ENABLE
0x00000000
1
Ethernet flow enable
Page 349
INGR2_ETH2_MATCH_MODE
0x00000004
1
Ethernet protocol match mode Page 349
INGR2_ETH2_ADDR_MATCH_1
0x00000008
1
Ethernet address match part 1 Page 350
INGR2_ETH2_ADDR_MATCH_2
0x0000000C
1
Ethernet address match part 2 Page 350
INGR2_ETH2_VLAN_TAG_RANG 0x00000010
E_I_TAG
1
Ethernet VLAN tag range
match register
Page 351
INGR2_ETH2_VLAN_TAG1
0x00000014
1
VLAN tag 1 match/mask
Page 351
INGR2_ETH2_VLAN_TAG2_I_TA 0x00000018
G
1
Match/mask for VLAN tag 2 or Page 351
I-tag match
VMDS-10510 VSC8574-02 Datasheet Revision 4.2
348
4.14.5.1
ETHERNET_COMPARATOR:INGR2_ETH2_FLOW_CFG:INGR2_ETH2_FLOW_
ENABLE
Parent: ETHERNET_COMPARATOR:INGR2_ETH2_FLOW_CFG
Instances: 1
Table 662 • Fields in INGR2_ETH2_FLOW_ENABLE
Field Name
Bit
Access
Description
Default
INGR2_ETH2_CHANNEL_MASK
9:8
R/W
Channel mask
0x0: Flow invalid
0x1: Flow valid for channel 0
0x2: Flow valid for channel 1
0x3: Flow valid for both channels
0x3
INGR2_ETH2_FLOW_ENABLE
0
R/W
Flow enable.
If this comparator block is not used, all flow
enable bits must be set to 0.
0: Flow disabled
1: Flow enabled
0x0
4.14.5.2
ETHERNET_COMPARATOR:INGR2_ETH2_FLOW_CFG:INGR2_ETH2_MATCH
_MODE
Parent: ETHERNET_COMPARATOR:INGR2_ETH2_FLOW_CFG
Instances: 1
Table 663 • Fields in INGR2_ETH2_MATCH_MODE
Field Name
Bit
INGR2_ETH2_VLAN_TAG_MODE 13:12
Access
Description
R/W
Default
0x0
0: VLAN range checking disabled
1: VLAN range checking on tag 1
2: VLAN range checking on tag 2 (not
supported with PBB)
3: Reserved
INGR2_ETH2_VLAN_TAG2_TYP
E
9
R/W
This register is only used if
ETH1_VLAN_VERIFY_ENA = 1
0: C tag (TPID of 0x8100)
1: S tag (match to CONF_VLAN_TPID)
INGR2_ETH2_VLAN_TAG1_TYP
E
8
R/W
This register is only used if
0x0
ETH1_VLAN_VERIFY_ENA = 1
0: C tag (TPID of 0x8100)
1: S or B tag (match to CONF_VLAN_TPID)
INGR2_ETH2_VLAN_TAGS
7:6
R/W
This register is only used if
ETH2_VLAN_VERIFY_ENA = 1
0: No VLAN tags
1: 1 VLAN tag
2: 2 VLAN tags
3: Reserved
VMDS-10510 VSC8574-02 Datasheet Revision 4.2
0x1
0x0
349
Table 663 • Fields in INGR2_ETH2_MATCH_MODE (continued)
Field Name
Bit
Access
INGR2_ETH2_VLAN_VERIFY_EN 4
A
R/W
INGR2_ETH2_ETHERTYPE_MO
DE
R/W
4.14.5.3
0
Description
Default
0x0
0: Parse for VLAN tags, do not check values.
1: Verify configured VLAN tag configuration.
When checking for presence of SNAP/LLC
0x0
based upon ETH1_MATCH_MODE, this field
indicates if SNAP and 3-byte LLC is expected
to be present.
0: Only Ethernet type II supported, no
SNAP/LLC
1: Ethernet type II and Ethernet type I with
SNAP/LLC, determine if SNAP/LLC is
present. Type I always assumes that
SNAP/LLC is present
ETHERNET_COMPARATOR:INGR2_ETH2_FLOW_CFG:INGR2_ETH2_ADDR_
MATCH_1
Parent: ETHERNET_COMPARATOR:INGR2_ETH2_FLOW_CFG
Instances: 1
Table 664 • Fields in INGR2_ETH2_ADDR_MATCH_1
Field Name
Bit
Access
Description
Default
INGR2_ETH2_ADDR_MATCH_1
31:0
R/W
First 32 bits of the address match value
0x00000000
4.14.5.4
ETHERNET_COMPARATOR:INGR2_ETH2_FLOW_CFG:INGR2_ETH2_ADDR_
MATCH_2
Parent: ETHERNET_COMPARATOR:INGR2_ETH2_FLOW_CFG
Instances: 1
Table 665 • Fields in INGR2_ETH2_ADDR_MATCH_2
Field Name
Bit
Access
Description
INGR2_ETH2_ADDR_MATCH_M
ODE
22:20
R/W
Selects how the addresses are matched.
0x1
One-hot encoded. Multiple bits can be set at
once.
0: Full 48-bit address match
1: Match any unicast address
2: Match any muliticast address
INGR2_ETH2_ADDR_MATCH_SE 17:16
LECT
R/W
Selects which address to match
0: Match the destination address
1: Match the source address
2: Match either the source of destination
address
3: Reserved
0x0
INGR2_ETH2_ADDR_MATCH_2
R/W
Last 16 bits of the Ethernet address match
field
0x0000
15:0
VMDS-10510 VSC8574-02 Datasheet Revision 4.2
Default
350
4.14.5.5
ETHERNET_COMPARATOR:INGR2_ETH2_FLOW_CFG:INGR2_ETH2_VLAN_T
AG_RANGE_I_TAG
Parent: ETHERNET_COMPARATOR:INGR2_ETH2_FLOW_CFG
Instances: 1
Table 666 • Fields in INGR2_ETH2_VLAN_TAG_RANGE_I_TAG
Field Name
Access
Description
Default
INGR2_ETH2_VLAN_TAG_RANG 27:16
E_UPPER
R/W
Contains the upper range of the VLAN tag
range match
0xFFF
INGR2_ETH2_VLAN_TAG_RANG 11:0
E_LOWER
R/W
Contains the lower range of the VLAN tag
range match
0x000
4.14.5.6
Bit
ETHERNET_COMPARATOR:INGR2_ETH2_FLOW_CFG:INGR2_ETH2_VLAN_T
AG1
Parent: ETHERNET_COMPARATOR:INGR2_ETH2_FLOW_CFG
Instances: 1
Table 667 • Fields in INGR2_ETH2_VLAN_TAG1
Field Name
Access
Description
Default
INGR2_ETH2_VLAN_TAG1_MAS 27:16
K
R/W
Mask value for VLAN tag 1
0xFFF
INGR2_ETH2_VLAN_TAG1_MAT 11:0
CH
R/W
Match value for the first VLAN tag
0x000
4.14.5.7
Bit
ETHERNET_COMPARATOR:INGR2_ETH2_FLOW_CFG:INGR2_ETH2_VLAN_T
AG2_I_TAG
Parent: ETHERNET_COMPARATOR:INGR2_ETH2_FLOW_CFG
Instances: 1
Table 668 • Fields in INGR2_ETH2_VLAN_TAG2_I_TAG
Field Name
Access
Description
Default
INGR2_ETH2_VLAN_TAG2_MAS 27:16
K
R/W
Mask field for VLAN tag 2
0xFFF
INGR2_ETH2_VLAN_TAG2_MAT 11:0
CH
R/W
Match field for VLAN Tag 2
0x000
4.14.6
Bit
ETHERNET_COMPARATOR:INGR2_MPLS_NXT_COMPARATOR_A
Parent: Egress0 Ethernet Comparator
Instances: 1
VMDS-10510 VSC8574-02 Datasheet Revision 4.2
351
Table 669 • Registers in INGR2_MPLS_NXT_COMPARATOR_A
Instances and
Offset within
Address
Register Group Spacing
Register Name
INGR2_MPLS_NXT_COMPARAT
OR_A
4.14.6.1
0x00000000
1
Description
Details
MPLS next protocol
comparator register
Page 352
ETHERNET_COMPARATOR:INGR2_MPLS_NXT_COMPARATOR_A:INGR2_M
PLS_NXT_COMPARATOR_A
Parent: ETHERNET_COMPARATOR:INGR2_MPLS_NXT_COMPARATOR_A
Instances: 1
Table 670 • Fields in INGR2_MPLS_NXT_COMPARATOR_A
Field Name
Bit
Access
Description
INGR2_MPLS_CTL_WORD_A
16
R/W
Indicates the presence of a control word after 0x0
the last label
0: No control ward after the last label
1: Control word after the last label
INGR2_MPLS_NXT_COMPARAT
OR_A
2:0
R/W
Points to the next comparator stage. If this
0x0
comparator block is not used, this field must
be set to 0.
0: Comparator block not used
1: Ethernet comparator 2
2: IP/UDP/ACH comparator 1
3: IP/UDP/ACH comparator 2
4: Reserved
5: PTP/OAM comparator
6,7: Reserved
4.14.7
Default
ETHERNET_COMPARATOR:INGR2_MPLS_FLOW_CFG
Parent: Egress0 Ethernet Comparator
Instances: 8
Table 671 • Registers in INGR2_MPLS_FLOW_CFG
Register Name
Instances and
Offset within
Address
Register Group Spacing
Description
Details
INGR2_MPLS_FLOW_CONTROL 0x00000000
1
MPLS flow control register
Page 353
INGR2_MPLS_LABEL_RANGE_L 0x00000004
OWER_0
1
MPLS label 0 match range
lower value
Page 354
INGR2_MPLS_LABEL_RANGE_U 0x00000008
PPER_0
1
MPLS label 0 match range
upper value
Page 354
INGR2_MPLS_LABEL_RANGE_L 0x0000000C
OWER_1
1
MPLS label 1 match range
lower value
Page 354
VMDS-10510 VSC8574-02 Datasheet Revision 4.2
352
Table 671 • Registers in INGR2_MPLS_FLOW_CFG (continued)
Register Name
Instances and
Offset within
Address
Register Group Spacing
Description
Details
INGR2_MPLS_LABEL_RANGE_U 0x00000010
PPER_1
1
MPLS label 1 match range
upper value
Page 354
INGR2_MPLS_LABEL_RANGE_L 0x00000014
OWER_2
1
MPLS label 2 match range
lower value
Page 355
INGR2_MPLS_LABEL_RANGE_U 0x00000018
PPER_2
1
MPLS label 2 match range
upper value
Page 355
INGR2_MPLS_LABEL_RANGE_L 0x0000001C
OWER_3
1
MPLS label 3 match range
lower value
Page 355
INGR2_MPLS_LABEL_RANGE_U 0x00000020
PPER_3
1
MPLS label 3 match range
upper value
Page 355
4.14.7.1
ETHERNET_COMPARATOR:INGR2_MPLS_FLOW_CFG:INGR2_MPLS_FLOW
_CONTROL
Parent: ETHERNET_COMPARATOR:INGR2_MPLS_FLOW_CFG
Instances: 1
Table 672 • Fields in INGR2_MPLS_FLOW_CONTROL
Field Name
Bit
Access
Description
Default
INGR2_MPLS_CHANNEL_MASK 25:24
R/W
Channel Mask
0x0: Flow invalid
0x1: Flow valid for channel 0
0x2: Flow valid for channel 1
0x3: Flow valid for both channels
0x3
INGR2_MPLS_STACK_DEPTH
19:16
R/W
Defines the allowable stack depths for
searches. The direction that the stack is
referenced is determined by the setting of
MPLS_REF_PNT. The following table maps
bits to stack depths:
0: Stack allowed to be 1 label deep
1: Stack allowed to be 2 labels deep
2: Stack allowed to be 3 labels deep
3: Stack allowed to be 4 labels deep
0x0
INGR2_MPLS_REF_PNT
4
R/W
Defines the search direction for label
0x0
matching
0: All searching is performed starting from the
top of the stack
1: All searching is performed from the end of
the stack
INGR2_MPLS_FLOW_ENA
0
R/W
Flow enable.
If this comparator block is not used, all flow
enable bits must be set to 0.
0: Flow is disabled
1: Flow is enabled
VMDS-10510 VSC8574-02 Datasheet Revision 4.2
0x0
353
4.14.7.2
ETHERNET_COMPARATOR:INGR2_MPLS_FLOW_CFG:INGR2_MPLS_LABEL
_RANGE_LOWER_0
Parent: ETHERNET_COMPARATOR:INGR2_MPLS_FLOW_CFG
Instances: 1
Table 673 • Fields in INGR2_MPLS_LABEL_RANGE_LOWER_0
Field Name
Bit
INGR2_MPLS_LABEL_RANGE_L 19:0
OWER_0
4.14.7.3
Access
Description
Default
R/W
Lower value for label 0 match range
0x00000
ETHERNET_COMPARATOR:INGR2_MPLS_FLOW_CFG:INGR2_MPLS_LABEL
_RANGE_UPPER_0
Parent: ETHERNET_COMPARATOR:INGR2_MPLS_FLOW_CFG
Instances: 1
Table 674 • Fields in INGR2_MPLS_LABEL_RANGE_UPPER_0
Field Name
Bit
INGR2_MPLS_LABEL_RANGE_U 19:0
PPER_0
4.14.7.4
Access
Description
Default
R/W
Upper value for label 0 match range
0xFFFFF
ETHERNET_COMPARATOR:INGR2_MPLS_FLOW_CFG:INGR2_MPLS_LABEL
_RANGE_LOWER_1
Parent: ETHERNET_COMPARATOR:INGR2_MPLS_FLOW_CFG
Instances: 1
Table 675 • Fields in INGR2_MPLS_LABEL_RANGE_LOWER_1
Field Name
Bit
INGR2_MPLS_LABEL_RANGE_L 19:0
OWER_1
4.14.7.5
Access
Description
Default
R/W
Lower value for label 1 match range
0x00000
ETHERNET_COMPARATOR:INGR2_MPLS_FLOW_CFG:INGR2_MPLS_LABEL
_RANGE_UPPER_1
Parent: ETHERNET_COMPARATOR:INGR2_MPLS_FLOW_CFG
Instances: 1
Table 676 • Fields in INGR2_MPLS_LABEL_RANGE_UPPER_1
Field Name
Bit
INGR2_MPLS_LABEL_RANGE_U 19:0
PPER_1
Access
Description
Default
R/W
Upper value for label 1 match range
0xFFFFF
VMDS-10510 VSC8574-02 Datasheet Revision 4.2
354
4.14.7.6
ETHERNET_COMPARATOR:INGR2_MPLS_FLOW_CFG:INGR2_MPLS_LABEL
_RANGE_LOWER_2
Parent: ETHERNET_COMPARATOR:INGR2_MPLS_FLOW_CFG
Instances: 1
Table 677 • Fields in INGR2_MPLS_LABEL_RANGE_LOWER_2
Field Name
Bit
INGR2_MPLS_LABEL_RANGE_L 19:0
OWER_2
4.14.7.7
Access
Description
Default
R/W
Lower value for label 2 match range
0x00000
ETHERNET_COMPARATOR:INGR2_MPLS_FLOW_CFG:INGR2_MPLS_LABEL
_RANGE_UPPER_2
Parent: ETHERNET_COMPARATOR:INGR2_MPLS_FLOW_CFG
Instances: 1
Table 678 • Fields in INGR2_MPLS_LABEL_RANGE_UPPER_2
Field Name
Bit
INGR2_MPLS_LABEL_RANGE_U 19:0
PPER_2
4.14.7.8
Access
Description
Default
R/W
Upper value for label 2 match range
0xFFFFF
ETHERNET_COMPARATOR:INGR2_MPLS_FLOW_CFG:INGR2_MPLS_LABEL
_RANGE_LOWER_3
Parent: ETHERNET_COMPARATOR:INGR2_MPLS_FLOW_CFG
Instances: 1
Table 679 • Fields in INGR2_MPLS_LABEL_RANGE_LOWER_3
Field Name
Bit
INGR2_MPLS_LABEL_RANGE_L 19:0
OWER_3
4.14.7.9
Access
Description
Default
R/W
Lower value for label 3 match range
0x00000
ETHERNET_COMPARATOR:INGR2_MPLS_FLOW_CFG:INGR2_MPLS_LABEL
_RANGE_UPPER_3
Parent: ETHERNET_COMPARATOR:INGR2_MPLS_FLOW_CFG
Instances: 1
Table 680 • Fields in INGR2_MPLS_LABEL_RANGE_UPPER_3
Field Name
Bit
INGR2_MPLS_LABEL_RANGE_U 19:0
PPER_3
Access
Description
Default
R/W
Upper value for label 3 match range
0xFFFFF
VMDS-10510 VSC8574-02 Datasheet Revision 4.2
355
4.14.8
ETHERNET_COMPARATOR:INGR2_PTP_FLOW
Parent: Egress0 Ethernet Comparator
Instances: 6
Table 681 • Registers in INGR2_PTP_FLOW
Register Name
Instances and
Address
Offset within
Register Group Spacing
Description
Details
INGR2_PTP_FLOW_ENA
0x00000000
1
PTP/OAM flow enable
Page 356
INGR2_PTP_FLOW_MATCH_UP
PER
0x00000004
1
Upper half of PTP/OAM flow
match field
Page 357
INGR2_PTP_FLOW_MATCH_LO
WER
0x00000008
1
Lower half of PTP/OAM flow
match field
Page 357
INGR2_PTP_FLOW_MASK_UPP
ER
0x0000000C
1
Upper half of PTP/OAM flow
match mask
Page 357
INGR2_PTP_FLOW_MASK_LOW 0x00000010
ER
1
Lower half of PTP/OAM flow
match mask
Page 357
INGR2_PTP_DOMAIN_RANGE
1
PTP/OAM range match
register
Page 358
0x00000014
INGR2_PTP_ACTION
0x00000018
1
PTP action control register
Page 358
INGR2_PTP_ACTION_2
0x0000001C
1
PTP action control register 2
Page 359
INGR2_PTP_ZERO_FIELD_CTL
0x00000020
1
Zero field control register
Page 359
4.14.8.1
ETHERNET_COMPARATOR:INGR2_PTP_FLOW:INGR2_PTP_FLOW_ENA
Parent: ETHERNET_COMPARATOR:INGR2_PTP_FLOW
Instances: 1
Table 682 • Fields in INGR2_PTP_FLOW_ENA
Field Name
Bit
Access
Description
INGR2_PTP_NXT_PROT_GRP_M 17:16
ASK
R/W
Indicates the next protocol groups that this
0x3
flow is valid for. For each next protocol group,
if the bit is 1, then this flow is valid for that
group. If it is 0, then it is not valid for the
group.
0: Mask bit for next protocol group A
1: Mask bit for next protocol group B
INGR2_PTP_CHANNEL_MASK
5:4
R/W
Channel mask
0x0: Flow invalid
0x1: Flow valid for channel 0
0x2: Flow valid for channel 1
0x3: Flow valid for both channels
0x3
INGR2_PTP_FLOW_ENA
0
R/W
Flow enable
0x0
VMDS-10510 VSC8574-02 Datasheet Revision 4.2
Default
356
4.14.8.2
ETHERNET_COMPARATOR:INGR2_PTP_FLOW:INGR2_PTP_FLOW_MATCH_
UPPER
Parent: ETHERNET_COMPARATOR:INGR2_PTP_FLOW
Instances: 1
Table 683 • Fields in INGR2_PTP_FLOW_MATCH_UPPER
Field Name
Bit
Access
INGR2_PTP_FLOW_MATCH_UP
PER
31:0
R/W
4.14.8.3
Description
Default
0x00000000
ETHERNET_COMPARATOR:INGR2_PTP_FLOW:INGR2_PTP_FLOW_MATCH_
LOWER
Parent: ETHERNET_COMPARATOR:INGR2_PTP_FLOW
Instances: 1
Table 684 • Fields in INGR2_PTP_FLOW_MATCH_LOWER
Field Name
Bit
Access
INGR2_PTP_FLOW_MATCH_LO
WER
31:0
R/W
4.14.8.4
Description
Default
0x00000000
ETHERNET_COMPARATOR:INGR2_PTP_FLOW:INGR2_PTP_FLOW_MASK_U
PPER
Parent: ETHERNET_COMPARATOR:INGR2_PTP_FLOW
Instances: 1
Table 685 • Fields in INGR2_PTP_FLOW_MASK_UPPER
Field Name
Bit
Access
INGR2_PTP_FLOW_MASK_UPP
ER
31:0
R/W
4.14.8.5
Description
Default
0x00000000
ETHERNET_COMPARATOR:INGR2_PTP_FLOW:INGR2_PTP_FLOW_MASK_L
OWER
Parent: ETHERNET_COMPARATOR:INGR2_PTP_FLOW
Instances: 1
Table 686 • Fields in INGR2_PTP_FLOW_MASK_LOWER
Field Name
Bit
INGR2_PTP_FLOW_MASK_LOW 31:0
ER
Access
Description
R/W
VMDS-10510 VSC8574-02 Datasheet Revision 4.2
Default
0x00000000
357
4.14.8.6
ETHERNET_COMPARATOR:INGR2_PTP_FLOW:INGR2_PTP_DOMAIN_RANG
E
Parent: ETHERNET_COMPARATOR:INGR2_PTP_FLOW
Instances: 1
Table 687 • Fields in INGR2_PTP_DOMAIN_RANGE
Field Name
Access
Description
Default
INGR2_PTP_DOMAIN_RANGE_O 28:24
FFSET
R/W
PTP domain range offset
0x00
INGR2_PTP_DOMAIN_RANGE_U 23:16
PPER
R/W
Upper range of PTP domain field to match
0xFF
INGR2_PTP_DOMAIN_RANGE_L 15:8
OWER
R/W
Lower range of PTP domain field to match
0x00
INGR2_PTP_DOMAIN_RANGE_E 0
NA
R/W
Enable PTP domain range checking
0x0
4.14.8.7
Bit
ETHERNET_COMPARATOR:INGR2_PTP_FLOW:INGR2_PTP_ACTION
Parent: ETHERNET_COMPARATOR:INGR2_PTP_FLOW
Instances: 1
Table 688 • Fields in INGR2_PTP_ACTION
Field Name
Bit
Access
INGR2_PTP_MOD_FRAME_STAT 28
_UPDATE
R/W
INGR2_PTP_MOD_FRAME_BYT
E_OFFSET
R/W
26:24
Description
Default
0x0
0: Do not signal the rewriter to update the
value of the Modified Frame Status bit
1: Signal the rewriter to update the value of
the Modified Frame Status bit
INGR2_PTP_SUB_DELAY_ASYM 21
_ENA
R/W
INGR2_PTP_ADD_DELAY_ASYM 20
_ENA
R/W
INGR2_PTP_TIME_STRG_FIELD 15:10
_OFFSET
R/W
Indicates the position relative to the start of
the PTP frame in bytes where the Modified
Frame Status bit resides
0x0
0x0
0: Do not signal the timestamp block to
subtract the asymmetry delay
1: Signal the timestamp block to subtract the
asymmetry delay
0x0
0: Do not signal the timestamp block to add
the asymmetry delay
1: Signal the timestamp block to add the
asymmetry delay
VMDS-10510 VSC8574-02 Datasheet Revision 4.2
0x00
358
Table 688 • Fields in INGR2_PTP_ACTION (continued)
Field Name
Bit
Access
Description
Default
INGR2_PTP_CORR_FIELD_OFF
SET
9:5
R/W
Points to the location of the correction field
for updating the timestamp. Location is
relative to the first byte of the PTP/OAM
header.
Note: If this flow is being used to
match OAM frames, set this
register to 4
0x00
INGR2_PTP_SAVE_LOCAL_TIME 4
R/W
Save local time to the timestamp FIFO
0x0
0: Do not save the time to the timestamp
FIFO
1: Save the local time to the timestamp FIFO
INGR2_PTP_COMMAND
R/W
3:0
0x0
0: NOP
1: SUB
2: SUB_P2P
3: ADD
4: SUB_ADD
5: WRITE_1588
6: WRITE_P2P (deprecated)
7: WRITE_NS
8: WRITE_NS_P2P
4.14.8.8
ETHERNET_COMPARATOR:INGR2_PTP_FLOW:INGR2_PTP_ACTION_2
Parent: ETHERNET_COMPARATOR:INGR2_PTP_FLOW
Instances: 1
Table 689 • Fields in INGR2_PTP_ACTION_2
Field Name
Bit
Access
Description
INGR2_PTP_NEW_CF_LOC
23:16
R/W
Location of the new correction field relative to 0x00
the PTP header start. Only even values are
allowed.
INGR2_PTP_REWRITE_OFFSET 15:8
R/W
Points to where in the frame relative to the
SFD that the timestamp should be updated
0x00
INGR2_PTP_REWRITE_BYTES
R/W
Number of bytes in the PTP or OAM frame
that must be modified by the rewriter for the
timestamp
0x0
4.14.8.9
3:0
Default
ETHERNET_COMPARATOR:INGR2_PTP_FLOW:INGR2_PTP_ZERO_FIELD_C
TL
Parent: ETHERNET_COMPARATOR:INGR2_PTP_FLOW
Instances: 1
VMDS-10510 VSC8574-02 Datasheet Revision 4.2
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Table 690 • Fields in INGR2_PTP_ZERO_FIELD_CTL
Field Name
Bit
Access
Description
INGR2_PTP_ZERO_FIELD_OFFS 13:8
ET
R/W
Points to a location in the PTP/OAM frame
0x00
relative to the start of the PTP header that will
be zeroed if this function is enabled
INGR2_PTP_ZERO_FIELD_BYTE 3:0
_CNT
R/W
The number of bytes to be zeroed. If this field 0x0
is 0, then this function is not enabled.
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Electrical Specifications
5
Electrical Specifications
This section provides the DC characteristics, AC characteristics, recommended operating conditions,
and stress ratings for the VSC8574-02 device.
5.1
DC Characteristics
This section contains the DC specifications for the VSC8574-02 device.
5.1.1
VDD25
The following table shows the DC specifications for the pins referenced to VDD25. The specifications
listed in the following table are valid only when VDD1 = 1.0 V, VDD1A = 1.0 V, or VDD25A = 2.5 V.
Table 691 • VDD25 DC Characteristics
Parameter
Symbol
Minimum
Maximum
Unit
Condition
Output high voltage
VOH
2.0
2.8
V
IOH = –1.0 mA
Output low voltage
VOL
–0.3
0.4
V
IOL = 1.0 mA
Input high voltage
VIH
1.85
3.3
V
Input low voltage
VIL
–0.3
0.7
V
Input leakage current
IILEAK
–32
32
µA
Internal resistor included
Output leakage current
IOLEAK
–32
32
µA
Internal resistor included
6
mA
Output low current drive IOL
strength
Output high current drive IOH
strength
5.1.2
–6
mA
LED and GPIO
The following table shows the DC specifications for the LED and GPIO pins.
Table 692 • LED and GPIO Characteristics
5.1.3
Pin
Symbol
LED
IOH
LED
IOL
GPIO
IOH
GPIO
IOL
Minimum
Maximum
Unit
24
mA
–24
mA
12
mA
–12
mA
Internal Pull-Up or Pull-Down Resistors
Internal pull-up or pull-down resistors are specified in the following table. For more information about
signals with internal pull-up or pull-down resistors, see Pins by Function, page 382.
All internal pull-up resistors are connected to their respective I/O supply.
Table 693 • Internal Pull-Up or Pull-Down Resistors
Parameter
Symbol
Minimum
Typical
Maximum
Unit
Internal pull-up resistor, GPIO
RPU_GPIO
33
53
90
kΩ
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Electrical Specifications
Table 693 • Internal Pull-Up or Pull-Down Resistors (continued)
Parameter
Symbol
Minimum
Typical
Maximum
Unit
Internal pull-up resistor, all others
RPU
96
120
144
kΩ
Internal pull-down resistor
RPD
96
120
144
kΩ
5.1.4
Reference Clock
The following table shows the DC specifications for a differential reference clock input signal
Table 694 • Reference Clock DC Characteristics
Parameter
Symbol
Minimum
Input voltage range
VIP,VIN
Input differential peak-to-peak
voltage
|VID|
Input common-mode voltage
VICM
Differential input impedance
RI
1.
2.
5.1.5
Typical
Maximum
Unit
–25
1260
mV
1501
1200
mV
0
12002
mV
Ω
100
To meet jitter specifications, the minimum |VID| must be 400 mV. When using a single-ended clock input, the
REFCLK_P low voltage must be less than
VDDA – 200 mV, and the high voltage level must be greater than VDDA + 200 mV
The maximum common-mode voltage is provided without a differential signal. The common-mode voltage is
only limited by the maximum and minimum input voltage range and by the differential amplitude of the input
signal.
1588 Reference Clock
The following table shows the DC specifications for a differential 1588 reference clock input signal.
Table 695 • 1588 Reference Clock DC Characteristics
Parameter
Symbol
Minimum
Input voltage range
VIP,VIN
Input differential peak-to-peak
voltage
Maximum
Unit
–25
1260
mV
|VID|
150
1200
mV
Input common-mode voltage
VICM
0
12001
mV
Differential input impedance
RI
1.
5.1.6
Typical
Ω
100
The maximum common-mode voltage is provided without a differential signal. The common-mode voltage is
only limited by the maximum and minimum input voltage range and by the differential amplitude of the input
signal.
SerDes Interface (SGMII)
The SerDes output drivers are designed to operate in SGMII/LVDS mode. The SGMII/LVDS mode meets
or exceeds the DC requirements of Serial-GMII Specification Revision 1.9 (ENG-46158), unless
otherwise noted. The following table lists the DC specifications for the SGMII driver. The values are valid
for all configurations, unless stated otherwise.
Table 696 • SerDes Driver DC Specifications
Parameter
Symbol
Output high voltage, VOA or VOB
VOH
Output low voltage, VOA or VOB
VOL
Minimum
0
Maximum
Unit
Condition
1050
mV
RL = 100 Ω ±1%
mV
RL = 100 Ω ±1%
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Electrical Specifications
Table 696 • SerDes Driver DC Specifications (continued)
Parameter
Symbol
Minimum
Maximum
Unit
Condition
Output differential peak voltage
|VOD|
350
450
mV
VDD_VS = 1.0 V
RL = 100 Ω ±1%
Output differential peak voltage,
fiber media 1000BASE-X
|VOD|
350
450
mV
VDD_VS = 1.0 V
RL = 100 Ω ±1%
Output offset voltage(1)
VOS
420
580
mV
VDD_VS = 1.0 V
RL = 100 Ω ±1%
DC output impedance,
single-ended, SGMII mode
RO
40
140
Ω
VC = 1.0 V
See Figure 80,
page 364
RO mismatch between A and B,
SGMII mode(2)
ΔRO
10
%
VC = 1.0 V
See Figure 80,
page 364
25
mV
RL = 100 Ω ±1%
RL = 100 Ω ±1%
Change in |VOD| between 0 and 1, Δ|VOD|
SGMII mode
Change in VOS between 0 and 1,
SGMII mode
ΔVOS
25
mV
Output current, driver shorted to
GND, SGMII mode
|IOSA|,
|IOSB|
40
mA
Output current, drivers shorted
together, SGMII mode
|IOSAB|
12
mA
1.
Requires AC-coupling for SGMII compliance.
2.
Matching of reflection coefficients. For more information about test methods, see
IEEE Std 1596.3-1996.
Figure 78 • SGMII DC Transmit Test Circuit
VOA
100 Ω ± 1%
VOD = VOA – VOB
VOS = ½ (VOA + VOB)
VOB
Figure 79 • SGMII DC Definitions
VOA
VOB
GND
VOD
0 V differential
|VOD|
|VOD|
0 V differential
VOS
GND
VOS
Δ|VOD| = | |VOAH – VOBL| – |VOBH – VOAL| |
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Electrical Specifications
ΔVOS = | ½(VOAH + VOBL) – ½(VOAL + VOBH) |
Figure 80 • SGMII DC Driver Output Impedance Test Circuit
VOA
50 Ω ± 0.1%
+V –
c
0 and 1
VOB
50 Ω ± 0.1%
The following table lists the DC specifications for the SGMII receivers.
Table 697 • SerDes Receiver DC Specifications
Parameter
Symbol
Minimum
Maximum
Unit
Input voltage range, VIA or VIB
VI
–25
1250
mV
Input differential peak-to-peak
voltage
|VID|
100
1000
mV
Input common-mode voltage(1)
VICM
0
VDD_A(2)
mV
Receiver differential input
impedance
RI
80
120
Ω
Input differential hysteresis,
SGMII mode
VHYST
25
1.
2.
Condition
Without any
differential signal
mV
SGMII compliancy requires external AC-coupling. When interfacing with specific Microsemi devices, DCcoupling is possible. For more information, contact your local Microsemi sales representative.
The common-mode voltage is only limited by the maximum and minimum input voltage range and the
input signal’s differential amplitude.
Figure 81 • SGMII DC Input Definitions
VIA
VID = VIA – VIB
VIC = ½ (VIA + VIB)
VIB
5.1.7
Enhanced SerDes Interface (QSGMII)
All DC specifications for the enhanced SerDes interface are compliant with QSGMII Specification
Revision 1.3 and meet or exceed the requirements in the standard. They are also compliant with OIFCEI-02.0 requirements where applicable.
The enhanced SerDes interface supports the following operating modes: SGMII, QSGMII, and SFP. The
values in the following table apply to the modes specified in the condition column.
The following table shows the DC specifications for the enhanced SerDes driver.
Table 698 • Enhanced SerDes Driver DC Specifications
Parameter
Symbol
Minimum
Maximum
Unit
Condition
Output differential peak voltage,
SFP and QSGMII modes
|VODp|
250
400
mV
VDD_VS = 1.0 V
RL = 100 Ω ±1%
maximum drive
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Electrical Specifications
Table 698 • Enhanced SerDes Driver DC Specifications (continued)
Parameter
Symbol
Minimum
Maximum
Unit
Condition
Output differential peak voltage,
SGMII mode(1)
|VODp|
150
400
mV
VDD_VS = 1.0 V
RL = 100 Ω ±1%
DC output impedance,
single-ended, SGMII mode
RO
40
140
Ω
VC = 1.0 V
See Figure 80,
page 364
RO mismatch between A and B,
SGMII mode(2)
ΔRO
10
%
VC = 1.0 V
See Figure 80,
page 364
25
mV
RL = 100 Ω ±1%
RL = 100 Ω ±1%
Change in |VOD| between 0 and 1, Δ|VOD|
SGMII mode
Change in VOS between 0 and 1,
SGMII mode
ΔVOS
25
mV
Output current, drivers shorted to
ground, SGMII and QSGMII
modes
|IOSA|,
|IOSB|
40
mA
Output current, drivers shorted
together, SGMII and QSGMII
modes
|IOSAB|
12
mA
1.
Voltage is adjustable in 64 steps.
2.
Matching of reflection coefficients. For more information about test methods, see
IEEE Std 1596.3-1996.
The following table lists the DC specifications for the enhanced SerDes receiver.
Table 699 • Enhanced SerDes Receiver DC Specifications
Parameter
Symbol
Minimum
Maximum
Unit
VI
–0.25
1.2
V
Input differential peak-to-peak voltage
|VID|
100
1600
mV
Input common-mode voltage
VICM
0
1200
mV
Receiver differential input impedance
RI
80
120
Ω
Input voltage range, VIA or
1.
5.1.8
VIB(1)
Typical
100
QSGMII DC input sensitivity is less than 400 mV.
Current Consumption
The following tables show the current consumption values for each mode. Add significant margin above
the values for sizing power supplies.
Table 700 • Current Consumption
Mode
Typical
Maximum
Unit
Condition
1V
Digital
1V
2.5 V
Analog Digital
2.5 V
1V
Analog Digital
1V
2.5 V
Analog Digital
2.5 V
Analog
Reset
52
55
9
1
460
110
13
5
mA
Power down
110
170
10
20
525
220
15
25
mA
1000BASE-T
395
200
10
445
900
270
15
500
mA
4-port SGMII
100BASE-TX
190
185
10
290
640
245
15
310
mA
4-port SGMII
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Electrical Specifications
Table 700 • Current Consumption (continued)
Mode
Typical
Maximum
Unit
Condition
1V
Digital
1V
2.5 V
Analog Digital
2.5 V
1V
Analog Digital
1V
2.5 V
Analog Digital
2.5 V
Analog
10BASE-T
145
180
10
240
575
240
15
245
mA
4-port SGMII
10BASE-Te
145
180
10
205
575
240
15
210
mA
4-port SGMII
1000BASE-X
155
240
10
20
585
300
15
25
mA
4-port SGMII
100BASE-FX
140
235
10
20
565
290
15
25
mA
4-port SGMII
1000BASE-T
475
255
10
445
980
270
15
500
mA
4-port SGMII + 1588
100BASE-TX
240
235
10
290
670
245
15
310
mA
4-port SGMII + 1588
10BASE-T
195
230
10
240
600
240
15
245
mA
4-port SGMII + 1588
10BASE-Te
195
230
10
205
600
240
15
210
mA
4-port SGMII + 1588
1000BASE-X
235
240
10
20
670
300
15
25
mA
4-port SGMII + 1588
100BASE-FX
175
235
10
20
600
290
15
25
mA
4-port SGMII + 1588
1000BASE-T
390
160
10
460
900
225
15
500
mA
4-port QSGMII
100BASE-TX
185
145
10
305
640
200
15
310
mA
4-port QSGMII
10BASE-T
140
140
10
237
575
195
15
245
mA
4-port QSGMII
10BASE-Te
140
140
10
210
575
195
15
210
mA
4-port QSGMII
1000BASE-X
150
200
10
20
585
255
15
25
mA
4-port QSGMII
100BASE-FX
135
195
10
20
565
245
15
25
mA
4-port QSGMII
1000BASE-T
475
210
10
460
980
270
15
500
mA
4-port QSGMII +
1588
100BASE-TX
240
190
10
295
670
245
15
310
mA
4-port QSGMII +
1588
10BASE-T
195
185
10
237
600
240
15
245
mA
4-port QSGMII +
1588
10BASE-Te
195
185
10
210
600
240
15
210
mA
4-port QSGMII +
1588
1000BASE-X
235
195
10
20
670
300
15
25
mA
4-port QSGMII +
1588
100BASE-FX
175
190
10
20
600
290
15
25
mA
4-port QSGMII +
1588
5.1.9
Thermal Diode
The VSC8574-02 device includes an on-die diode and internal circuitry for monitoring die temperature
(junction temperature). The operation and accuracy of the diode is not guaranteed and should only be
used as a reference. Care should be taken to find compatible grounded cathode temperature monitoring
device.
A thermal sensor, located on the board or in a stand-alone measurement kit, can monitor and display the
die temperature of the switch for thermal management or instrumentation purposes.
Temperature measurement using a thermal diode is very sensitive to noise.
VMDS-10510 VSC8574-02 Datasheet Revision 4.2
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Electrical Specifications
The following table provides the diode parameter and interface specifications. Note that the ThermDC pin
is connected to VSS internally in the device.
Table 701 • Thermal Diode Parameters
Parameter
Symbol
Forward bias current
IFW
Diode ideality factor
n
Typical
Maximum
Unit
1
mA
1.008
Note: Microsemi does not support or recommend operation of the thermal diode under reverse bias.
The ideality factor, n, represents the deviation from ideal diode behavior as exemplified by the diode
equation:
q
I FW = I S × Vd × --------nkT
e
– 1
where, Is = saturation current, q = electronic charge, Vd = voltage across the diode, k = Boltzmann Constant, and T =
absolute temperature (Kelvin).
5.2
AC Characteristics
This section provides the AC specifications for the VSC8574-02 device.
5.2.1
Reference Clock
The following table shows the AC specifications for a 125 MHz differential reference clock source.
Performance is guaranteed for 125 MHz differential clocks only; however, 125 MHz single-ended clocks
are also supported for QSGMII interfaces.
25 MHz clock implementations are available but are limited to SGMII interfaces. For more information,
contact your Microsemi representative.
Table 702 • Reference Clock AC Characteristics for QSGMII 125 MHz Differential Clock
Parameter
Symbol
Reference clock
frequency,
REFCLK_SEL2 = 1
ƒ
Duty cycle
DC
Rise time and fall time
tr, tf
Minimum
Typical
Maximum
125.00
40
50
Unit
Condition
MHz
±100 ppm
60
%
1.5
ns
20% to 80%
threshold
RefClk input RMS jitter
requirement, bandwidth
between 12 kHz and
500 kHz(1)
20
ps
To meet jitter
generation of 1G
output data per
IEEE 802.3z
RefClk input RMS jitter
requirement, bandwidth
between 500 kHz and
15 MHz(1)
4
ps
To meet jitter
generation of 1G
output data per
IEEE 802.3z
RefClk input RMS jitter
requirement, bandwidth
between 15 MHz and
40 MHz(1)
20
ps
To meet jitter
generation of 1G
output data per
IEEE 802.3z
VMDS-10510 VSC8574-02 Datasheet Revision 4.2
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Electrical Specifications
Table 702 • Reference Clock AC Characteristics for QSGMII 125 MHz Differential Clock (continued)
Parameter
Symbol
Minimum
Maximum
Unit
Condition
RefClk input RMS jitter
requirement, bandwidth
between 40 MHz and
80 MHz(1)
100
ps
To meet jitter
generation of 1G
output data per
IEEE 802.3z
Jitter gain from RefClk
to SerDes output,
bandwidth between
0 MHz and 0.1 MHz
0.3
dB
3
dB
3–20 × log
(ƒ/7 MHz)
dB
Jitter gain from RefClk
to SerDes output,
bandwidth between
0.1 MHz and 7 MHz
1
Jitter gain from RefClk
to SerDes output,
bandwidth above 7 MHz
1.
5.2.2
Typical
1–20 × log
(ƒ/7 MHz)
Maximum RMS jitter allowed at the RefClk input for the given bandwidth.
Recovered Clock
This section provides the AC characteristics for the recovered clock output signals. The following
illustration shows the test circuit for the recovered clock output signals.
Figure 82 • Test Circuit for Recovered Clock Output Signals
39 Ω
50 Ω
8 pF
Device Under Test
Signal Measurement Point
The following table shows the AC specifications for the RCVRDCLK1 and RCVRDCLK2 outputs.
Table 703 • Recovered Clock AC Characteristics
Parameter
Symbol
Recovered clock
frequency
ƒ
125.00
MHz
Recovered clock
frequency
ƒ
31.25
MHz
Recovered clock
frequency
ƒ
25.00
MHz
Recovered clock cycle tRCYC
time
8.0
ns
Recovered clock cycle tRCYC
time
32.0
ns
Recovered clock cycle tRCYC
time
40.0
ns
Frequency stability
ƒSTABILITY
Duty cycle, master
mode
DC
Minimum
40
Typical
50
Maximum
Unit
50
ppm
60
%
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Electrical Specifications
Table 703 • Recovered Clock AC Characteristics (continued)
5.2.3
Parameter
Symbol
Clock rise time and
fall time
tR, tF
Minimum
Typical
Maximum
600
Unit
Condition
ps
20% to 80%
Peak-to-peak jitter,
JPPCLK_Cu
copper media
interface (1000BASET slave mode)
400
ps
10K samples
Peak-to-peak jitter,
fiber media interface,
100BASE-FX
JPPCLK_FiFX
1.2
ns
10K samples
Peak-to-peak jitter,
fiber media interface,
1000BASE-X
JPPCLK_FiX
250
ps
10K samples
SerDes Outputs
The values listed in the following table are valid for all configurations, unless otherwise noted.
Table 704 • SerDes Outputs AC Specifications
Parameter
Symbol
VOD ringing compared to
VS, SGMII mode
VRING
VOD rise time and fall time, tR, tF
SGMII mode
5.2.4
Minimum
100
Maximum
Unit
Condition
±10
%
RL = 100 Ω ±1%
200
ps
20% to 80% of VS
RL = 100 Ω ±1%
30
mV
Tx disabled
Differential peak-to-peak
output voltage
VOD
Differential output return
loss, 50 MHz to 625 MHz
RLO_DIFF
≥10
dB
RL = 100 Ω ±1%
Differential output return
loss, 625 MHz to
1250 MHz
RLO_DIFF
10–10 × log
(ƒ/625 MHz)
dB
RL = 100 Ω ±1%
Common-mode return
loss, 50 MHz to 625 MHz
RLOCM
6
dB
Interpair skew, SGMII
mode
tSKEW
20
ps
SerDes Driver Jitter
The following table lists the jitter characteristics for the SerDes output driver.
Table 705 • SerDes Driver Jitter Characteristics
Parameter
Symbol
Maximum
Unit
Condition
Total jitter
TJO
192
ps
Measured according to IEEE 802.3.38.5
Deterministic jitter
DJO
80
ps
Measured according to IEEE 802.3.38.5
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Electrical Specifications
5.2.5
SerDes Inputs
The following table lists the AC specifications for the SerDes inputs.
Table 706 • SerDes Input AC Specifications
5.2.6
Parameter
Maximum
Unit
Condition
Differential input return loss,
50 MHz to 625 MHz
≥10
dB
RL = 100 Ω ±1%
Differential input return loss,
625 MHz to 1250 MHz
10–10 × log (ƒ/625 MHz)
dB
RL = 100 Ω ±1%
SerDes Receiver Jitter Tolerance
The following table lists jitter tolerances for the SerDes receiver.
Table 707 • SerDes Receiver Jitter Tolerance
Parameter
Symbol
Minimum
Unit
Condition
Total jitter tolerance, greater than
637 kHz, SFP mode
TJTI
600
ps
Measured according to
IEEE 802.3 38.6.8
Deterministic jitter tolerance,
greater than 637 kHz, SFP mode
DJTI
370
ps
Measured according to
IEEE 802.3 38.6.8
Cycle distortion jitter tolerance,
100BASE-FX mode
JTCD
1.4
ns
Measured according to
ISO/IEC 9314-3:1990
Data-dependent jitter tolerance,
100BASE-FX mode
DDJ
2.2
ns
Measured according to
ISO/IEC 9314-3:1990
Random peak-to-peak jitter
tolerance, 100BASE-FX mode
RJT
2.27
ns
Measured according to
ISO/IEC 9314-3:1990
5.2.7
Enhanced SerDes Interface
All AC specifications for the enhanced SerDes interface are compliant with QSGMII Specification
Revision 1.3 and meet or exceed the requirements in the standard. They are also compliant with the OIFCEI-02.0 requirements where applicable.
The enhanced SerDes interface supports the following modes of operation: SGMII, QSGMII, and SFP.
The values in the tables in the following sections apply to the QSGMII modes listed in the condition
column and are based on the test circuit shown in Figure 78, page 363. The transmit and receive eye
specifications relate to the eye diagrams shown in the following illustration, with the compliance load as
defined in the test circuit.
Figure 83 • QSGMII Transient Parameters
Transmitter Eye Mask
Receiver Eye Mask
R_Y2
Amplitude (mV)
Amplitude (mV)
T_Y2
T_Y1
0
–T_Y1
–T_Y2
R_Y1
0
–R_Y1
–R_Y2
0
T_X1
T_X2
1–T_X2 1–T_X1
Time (UI)
1.0
0
R_X1
0.5
1–R_X1
1.0
Time (UI)
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Electrical Specifications
5.2.7.1
Enhanced SerDes Outputs
The following table provides the AC specifications for the enhanced SerDes outputs in SGMII mode.
Table 708 • Enhanced SerDes Outputs AC Specifications, SGMII Mode
Parameter
Symbol
Unit interval, 1.25G mode
UI
VOD ringing compared to VS
VRING
VOD rise time and fall time
t R, tF
Minimum
Maximum
Unit
Condition
800 ps
100
Differential peak-to-peak output VOD
voltage
±10
%
RL = 100 Ω ±1%
200
ps
20% to 80% of VS
RL = 100 Ω ±1%
30
mV
Tx disabled
Differential output return loss,
50 MHz to 625 MHz
RLO_DIFF ≥10
dB
RL = 100 Ω ±1%
Differential output return loss,
625 MHz to 1250 MHz
RLO_DIFF 10–10 × log
(ƒ/625 MHz)
dB
RL = 100 Ω ±1%
Common-mode return loss,
50 MHz to 625 MHz
RLOCM
dB
Intrapair skew
tSKEW
6
20
ps
The following table provides the AC specifications for the enhanced SerDes outputs in QSGMII mode.
Table 709 • Enhanced SerDes Outputs AC Specifications, QSGMII Mode
5.2.7.2
Parameter
Symbol
Unit interval, 5G
UI
VOD rise time and fall time
tR, tF
Differential peak-to-peak
output voltage
VOD
Differential output return
loss, 100 MHz to 2.5 GHz
Minimum
Maximum
Unit
Condition
200 ps
30
96
ps
20% to 80% of VS
RL = 100 Ω ±1%
30
mV
Tx disabled
RLO_DIFF 8
dB
RL = 100 Ω ±1%
Differential output return
loss, 2.5 GHz to 5 GHz
RLO_DIFF 8 dB – 16.6 log
(ƒ/2.5 GHz)
dB
RL = 100 Ω ±1%
Eye mask X1
T_X1
0.15
UI
Eye mask X2
T_X2
0.4
UI
Eye mask Y1
T_Y1
Eye mask Y2
T_Y2
200
mV
450
mV
Enhanced SerDes Driver Jitter Characteristics
The following table lists the jitter characteristics for the enhanced SerDes driver in QSGMII mode. For
information about jitter characteristics for the enhanced SerDes driver in SGMII mode, see Table 705,
page 369.
Table 710 • Enhanced SerDes Driver Jitter Characteristics, QSGMII Mode
Parameter
Symbol
Maximum
Unit
Condition
Total output jitter
TJO
60
ps
Measured according to
IEEE 802.3.38.5.
VMDS-10510 VSC8574-02 Datasheet Revision 4.2
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Electrical Specifications
Table 710 • Enhanced SerDes Driver Jitter Characteristics, QSGMII Mode
5.2.7.3
Parameter
Symbol
Maximum
Unit
Condition
Deterministic output jitter
DJO
10
ps
Measured according to
IEEE 802.3.38.5.
Enhanced SerDes Inputs
The following table lists the AC specifications for the enhanced SerDes inputs in SGMII mode.
Table 711 • Enhanced SerDes Input AC Specifications, SGMII Mode
Parameter
Symbol
Unit
Condition
Unit interval, 1.25G
UI
Minimum
ps
800 ps
Differential input return loss,
50 MHz to 625 MHz
RLI_DIFF 10
dB
RL = 100 Ω ±1%
Common-mode input return loss,
50 MHz to 625 MHz
RLICM
dB
6
The following table lists the AC specifications for the enhanced SerDes inputs in QSGMII mode.
Table 712 • Enhanced SerDes Inputs AC Specifications, QSGMII Mode
5.2.7.4
Parameter
Symbol
Minimum
Maximum
Unit
Condition
Unit interval, 5G
UI
Differential input return loss,
100 MHz to 2.5 GHz
RLI_DIFF 8
dB
RL = 100 Ω ±1%
Differential input return loss,
2.5 GHz to 5 GHz
RLI_DIFF 8 dB – 16.6 log
(ƒ/2.5 GHz)
dB
RL = 100 Ω ±1%
Common-mode input return
loss, 100 MHz to 2.5 GHz
RLICM
dB
Eye mask X1
R_X1
0.3
UI
Eye mask Y1
R_Y1
50
mV
Eye mask Y2
R_Y2
450
mV
200 ps
6
Enhanced SerDes Receiver Jitter Tolerance
The following table lists the jitter tolerance for the enhanced SerDes receiver in QSGMII mode. For
information about jitter tolerance for the enhanced SerDes receiver in SGMII mode, see Table 707,
page 370.
Table 713 • Enhanced SerDes Receiver Jitter Tolerance, QSGMII Mode
Parameter
Symbol
Maximum
Unit
Condition
BHPJ
90
ps
92 ps peak-to-peak random
jitter and 38 ps sinusoidal jitter
(SJHF).
Sinusoidal jitter, maximum
SJMAX
1000
ps
Sinusoidal jitter, high frequency
SJHF
10
ps
Total jitter tolerance
TJTI
120
ps
Bounded high-probability
jitter(1)
92 ps peak-to-peak random
jitter and 38 ps sinusoidal jitter
(SJHF).
VMDS-10510 VSC8574-02 Datasheet Revision 4.2
372
Electrical Specifications
1.
5.2.8
This is the sum of uncorrelated bounded high probability jitter (0.15 UI), and correlated bounded high
probability jitter (0.30 UI). Uncorrelated bounded high probability jitter is distribution where the value of the
jitter shows no correlation to any signal level being transmitted, formally defined as deterministic jitter (DJ).
Correlated bounded high probability jitter is jitter distribution where the value of the jitter shows a strong
correlation to the signal level being transmitted.
Basic Serial LEDs
This section contains the AC specifications for the basic serial LEDs.
Table 714 • Basic Serial LEDs AC Characteristics
Parameter
Symbol
Typical
Unit
LED_CLK cycle time
tCYC
1024
ns
Pause between LED port sequences tPAUSE_port 3072
ns
Pause between LED bit sequences
tPAUSE_bit
25.541632
ms
LED_CLK to LED_DATA
tCO
1
ns
Figure 84 • Basic Serial LED Timing
tcyc
LED_CLK
tPAUSE_port
tco
Bit 1
LED_DATA
5.2.9
Bit 2
Bit X
Bit 1
Enhanced Serial LEDs
This section contains the AC specifications for the enhanced serial LEDs. The duty cycle of the
LED_PULSE signal is programmable and can be varied between 0.5% and 99.5%.
Table 715 • Enhanced Serial LEDs AC Characteristics
Parameter
Symbol
LED_CLK cycle time
tCYC
Pause between LED_DATA bit sequences tPAUSE
Minimum
Typical
Maximum
256
0.396
Unit
ns
24.996
ms
LED_CLK to LED_DATA
tCO
127
ns
LED_CLK to LED_LD
tCL
256
ns
LED_LD pulse width
tLW
128
ns
LED_PULSE cycle time
tPULSE
199
VMDS-10510 VSC8574-02 Datasheet Revision 4.2
201
µs
373
Electrical Specifications
Figure 85 • Enhanced Serial LED Timing
tcyc
tpause
LED_CLK
tcl
tco
LED_DATA
Bit 1
Bit 2
Bit X
Bit 1
Bit 2
tlw
LED_LD
tpulse
LED_PULSE
5.2.10
JTAG Interface
This section provides the AC specifications for the JTAG interface. The specifications meet or exceed the
requirements of IEEE 1149.1-2001. The JTAG receive signal requirements are requested at the pin of
the device. The JTAG_TRST signal is asynchronous to the clock, and does not have a setup or hold time
requirement.
Table 716 • JTAG Interface AC Specifications
Parameter
Symbol
Minimum
TCK frequency
ƒ
TCK cycle time
tC
100
ns
TCK high time
tW(CH)
40
ns
TCK low time
tW(CL)
40
ns
Setup time to TCK rising
tSU
10
ns
Hold time from TCK rising
tH
10
ns
TDO valid after TCK falling tV(C)
TDO hold time from TCK
falling
tH(TDO)
TDO disable time(1)
tDIS
TRST time low
tW(TL)
1.
Maximum
Unit
10
MHz
28
0
30
30
Condition
ns
CL = 10 pF
ns
CL = 0 pF
ns
See Figure 87, page 375.
ns
The pin begins to float when a 300 mV change from the actual VOH/VOL level occurs.
VMDS-10510 VSC8574-02 Datasheet Revision 4.2
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Electrical Specifications
Figure 86 • JTAG Interface Timing Diagram
tc
TCK
tW(CH)
tW(CL)
TDI
TMS
tSU
tH
t V(C)
TDO
tH(TDO)
tDIS
See definition
nTRST
tW(TL)
Figure 87 • Test Circuit for TDO Disable Time
3.3 V
500 Ω
F rom output under test
500 Ω
5.2.11
5 pF
Serial Management Interface
This section contains the AC specifications for the serial management interface (SMI).
Table 717 • Serial Management Interface AC Characteristics
Parameter
Symbol Minimum
Typical
Maximum
Unit
MDC
frequency(1)
fCLK
2.5
12.5
MHz
MDC cycle time
tCYC
80
400
ns
MDC time high
tWH
20
50
ns
MDC time low
tWL
20
50
ns
Setup to MDC
rising
tSU
10
ns
Hold from MDC
rising
tH
10
ns
MDC rise time
tR
100
tCYC × 10%(1)
ns
VMDS-10510 VSC8574-02 Datasheet Revision 4.2
Condition
MDC = 0: 1 MHz
MDC = 1:
MHz – fCLK maximum
375
Electrical Specifications
Table 717 • Serial Management Interface AC Characteristics (continued)
Parameter
Symbol Minimum
MDC fall time
tF
MDC to MDIO
valid
tCO
1.
Typical
Maximum
Unit
Condition
ns
Time-dependant on
the value of the
external pull-up
resistor on the MDIO
pin
100
tCYC × 10%(1)
10
300
For fCLK above 1 MHz, the minimum rise time and fall time is in relation to the frequency of the MDC clock
period. For example, if fCLK is 2 MHz, the minimum clock rise time and fall time is 50 ns.
Figure 88 • Serial Management Interface Timing
tW L
tW H
M DC
t CYC
t SU
tH
M D IO
(w rite)
D ata
t CO
M D IO
(rea d)
5.2.12
D a ta
Reset Timing
This section contains the AC specifications that apply to device reset functionality. The signal applied to
the NRESET input must comply with the specifications listed in the following table.
Table 718 • Reset Timing Specifications
Parameter
Symbol
Minimum
NRESET assertion time after power
supplies and clock stabilize
tW
2
Recovery time from reset inactive to
device fully active
tREC
NRESET pulse width
tW(RL)
Wait time between NRESET de-assert tWAIT
and access of the SMI interface
Maximum
Unit
ms
105
ms
100
ns
105
ms
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Electrical Specifications
5.2.13
1588 Timing Specifications
This section contains the AC specifications for the 1588 clock pins.
Table 719 • 1588 Timing Specifications AC Characteristics
Parameter
Symbol
Minimum
1588 reference
clock frequency1
ƒ
125
Duty cycle
DC
40
Rise time and fall
time
tR, tF
1.
5.2.14
Typical
50
Maximum
Unit
Condition
250
MHz
±100 ppm
Jitter < 10 ps RMS
60
%
1.5
ns
20% to 80%
threshold
Supports a continuum of frequencies between 125 MHz and 250 MHz.
Serial Timestamp Interface
This section contains information about the AC specifications for the serial timestamp interface.
Table 720 • Serial Timestamp Interface
Parameter
Symbol
Minimum
Typical
1588_SPI_CLK
frequency
Maximum
Unit
62.51
MHz
1588_SPI_DO clock- tCLK-to-Q
to-Q timing
–5
0
ns
1588_SPI_CS clock- tCLK-to-Q
to-Q timing
–5
0
ns
1.
Condition
SPI clock low time programmed through SI_CLK_LO_CYCs must always equal 0x1 (8 nanoseconds) for
correct bus operation. Duty cycle is dependent on SI_CLK_HI_CYCs configuration.
The following illustration shows the serial timestamp interface timing diagram.
Note: Data changes state on a falling 1588_SPI_CLK edge in the default configuration. 1588_SPI_CLK can be
inverted by setting the 1588 register bit TS_FIFO_SI_CFG:SI_CLK_PHA.
Figure 89 • Serial Timestamp Interface Timing Diagram
SPI_CLK
SPI_DO, SPI_CS
tCLK-to-Q
5.2.15
Local Time Counter Load/Save Timing
This section contains information about the AC specifications for the local time counter load/save signal.
VMDS-10510 VSC8574-02 Datasheet Revision 4.2
377
Electrical Specifications
Figure 90 • Local Time Counter Load/Save Timing Diagram
tC
1588_DIFF_INPUT_CLK
tSU(DI)
tH(DI)
1588_LOAD_SAVE
Table 721 • Local Time Counter Load/Save Timing Specifications
5.3
Parameter
Symbol
Minimum
Maximum
Unit
Clock frequency
ƒ
250
MHz
Clock cycle time
tC
4
ns
DI setup time to clock
tSU(DI)
2.8
ns
DI hold time from clock
tH(DI)
0.3
ns
Operating Conditions
The following table shows the recommended operating conditions for the VSC8574-02 device.
Table 722 • Recommended Operating Conditions
Parameter
Symbol
Minimum
Typical
Maximum
Unit
Power supply voltage for VDD1
VDD1
0.95
1.00
1.05
V
Power supply voltage for VDD1A
VDD1A
0.95
1.00
1.05
V
Power supply voltage for VDD25
VDD25
2.38
2.50
2.62
V
Power supply voltage for VDD25A
2.50
2.62
V
VDD25A
2.38
VSC8574-02 operating
temperature(1)
T
0
125
°C
VSC8574-05 operating
temperature(1)
T
–40
125
°C
1.
5.4
Minimum specification is ambient temperature, and the maximum is junction temperature. For carrier
class applications, the maximum operating temperature is 110 °C junction.
Stress Ratings
This section contains the stress ratings for the VSC8574-02 device.
Warning Stresses listed in the following table may be applied to devices one at a time without causing
permanent damage. Functionality at or exceeding the values listed is not implied. Exposure to these
values for extended periods may affect device reliability.
Table 723 • Stress Ratings
Parameter
Symbol
Minimum
Maximum
Unit
Power supply voltage for core supply
VVDD1
–0.3
1.10
V
Power supply voltage for analog circuits
VVDD1A
–0.3
1.10
V
Power supply voltage for analog circuits
VVDD25A
–0.3
2.75
V
Power supply voltage for digital I/O
VVDD25
–0.3
2.75
V
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378
Electrical Specifications
Table 723 • Stress Ratings (continued)
Parameter
Symbol
Minimum
Input voltage for GPIO and logic input pins
Maximum
Unit
3.3
V
Storage temperature
TS
–55
125
°C
Electrostatic discharge voltage, charged
device model
VESD_CDM
–250
250
V
Electrostatic discharge voltage, human body
model
VESD_HBM
See note(1)
1.
V
This device has completed all required testing as specified in the JEDEC standard JESD22-A114,
Electrostatic Discharge (ESD) Sensitivity Testing Human Body Model (HBM), and complies with a
Class 2 rating. The definition of Class 2 is any part that passes an ESD pulse of 2000 V, but fails an
ESD pulse of 4000 V.
Warning This device can be damaged by electrostatic discharge (ESD) voltage. Microsemi
recommends that all integrated circuits be handled with appropriate precautions. Failure to observe
proper handling and installation procedures may adversely affect reliability of the device.
VMDS-10510 VSC8574-02 Datasheet Revision 4.2
379
Pin Descriptions
6
Pin Descriptions
The VSC8574-02 device has 256 pins, which are described in this section.
The pin information is also provided as an attached Microsoft Excel file so that you can copy it
electronically. In Acrobat, double-click the attachment icon.
6.1
Pin Identifications
This section contains the pin descriptions for the VSC8574-02 device. The following table provides
notations for definitions of the various pin types.
Table 724 • Pin Type Symbol Definitions
Symbol
Pin Type
3V
6.2
Description
3.3 V-tolerant pin.
ABIAS
Analog bias
Analog bias pin.
ADIFF
Analog differential
Analog differential signal pair.
I
Input
Input without on-chip pull-up or pull-down resistor.
I/O
Bidirectional
Bidirectional input or output signal.
NC
No connect
No connect pins must be left floating.
O
Output
Output signal.
OD
Open drain
Open drain output.
OS
Open source
Open source output.
PD
Pull-down
On-chip pull-down resistor to VSS.
PU
Pull-up
On-chip pull-up resistor to VDD_IO.
ST
Schmitt-trigger
Input has Schmitt-trigger circuitry.
Pin Diagram
The following illustrations show the pin diagram for the VSC8574-02 device. For clarity, the device is
shown in two halves, the top left and top right.
VMDS-10510 VSC8574-02 Datasheet Revision 4.2
380
Pin Descriptions
Figure 91 • Pin Diagram, Top Left
1
2
3
4
5
6
7
8
A
NC_1
TXVPA_3
TXVPB_3
TXVPC_3
TXVPD_3
TXVPA_2
TXVPB_2
TXVPC_2
B
VSS_1
TXVNA_3
TXVNB_3
TXVNC_3
TXVND_3
TXVNA_2
TXVNB_2
TXVNC_2
C
REFCLK_N
VDD25A_1
THERMDA
VDD25A_2
VSS_3
VDD25A_3
VDD1A_1
VDD1A_2
D
REFCLK_P
THERMDC_VSS
REF_FILT_A
REF_REXT_A
VSS_6
VSS_7
VSS_8
VSS_9
E REFCLK_SEL2
TMS
TRST
VDD25A_6
VDD1_1
VSS_14
VSS_15
VSS_16
F
TDO
TDI
TCK
VSS_20
VDD1_3
VSS_21
VSS_22
VSS_23
G
LED0_0
LED1_0
LED2_0
LED3_0
VDD1_5
VSS_27
VSS_28
VSS_29
H
LED0_1
LED1_1
LED2_1
LED3_1
VDD1_7
VSS_33
VSS_34
VSS_35
J
LED0_2
LED1_2
LED2_2
LED3_2
VDD1_9
VSS_39
VSS_40
VSS_41
K
LED0_3
LED1_3
LED2_3
LED3_3
VDD1_11
VSS_45
VSS_46
VSS_47
VDD1_13
VSS_51
VSS_52
VSS_53
VDD1_15
VSS_57
VSS_58
VSS_59
VDD1_17
VSS_63
VSS_64
VSS_65
L RESERVED_5
RESERVED_11 COMA_MODE RESERVED_3
M RESERVED_6
MDINT
N RESERVED_7
MDIO
P RESERVED_8
MDC
VDD25_4
RESERVED_4
VDD25A_8
VDD1A_5
VDD1A_6
VDD1A_7
NRESET
VDD25_2
RESERVED_9 RESERVED_10
R
VSS_69
FIBROP_3
FIBRIP_3
RDP_3
TDP_3
FIBROP_2
FIBRIP_2
RDP_2
T
NC_3
FIBRON_3
FIBRIN_3
RDN_3
TDN_3
FIBRON_2
FIBRIN_2
RDN_2
VMDS-10510 VSC8574-02 Datasheet Revision 4.2
381
Pin Descriptions
Figure 92 • Pin Diagram, Top Right
9
10
11
12
13
14
15
16
TXVPD_2
TXVPA_1
TXVPB_1
TXVPC_1
TXVPD_1
TXVPA_0
TXVPB_0
NC_2
A
TXVND_2
TXVNA_1
TXVNB_1
TXVNC_1
TXVND_1
TXVNA_0
TXVNB_0
VSS_2
B
VDD1A_3
RESERVED_1
VDD25A_4
VSS_4
VDD1A_4
VDD25A_5
TXVNC_0
TXVPC_0
C
VSS_10
VSS_11
VSS_12
VSS_13
RESERVED_2
VSS_71
TXVND_0
TXVPD_0
D
VSS_17
VSS_18
VSS_19
VDD1_2
VDD25A_7
VSS_72
CLK_SQUELCH_IN
1588_SPI_CLK
E
VSS_24
VSS_25
VSS_26
VDD1_4
VSS_73
PHYADD4
VSS_74
RCVRDCLK1
F
VSS_30
VSS_31
VSS_32
VDD1_6
PHYADD2
PHYADD3
VSS_75
RCVRDCLK2
G
VSS_36
VSS_37
VSS_38
VDD1_8
VDD25_1
GPIO13/1588_SPI_DO
VSS_76
VSS_77
H
VSS_42
VSS_43
VSS_44
VDD1_10
VSS_78
GPIO12/1588_SPI_CS
1588_DIFF_INPUT_CLK_P
1588_DIFF_INPUT_CLK_N
J
VSS_48
VSS_49
VSS_50
VDD1_12
GPIO8/I2C_SDA
GPIO9/FASTLINK-FAIL
GPIO10/1588_LOAD_SAVE
GPIO11
K
VSS_54
VSS_55
VSS_56
VDD1_14
GPIO4/I2C_SCL_0 GPIO5/I2C_SCL_1 GPIO6/I2C_SCL_2 GPIO7/I2C_SCL_3
VSS_60
VSS_61
VSS_62
VDD1_16
VSS_66
VSS_67
VSS_68
VDD1_18
VDD1A_8
VDD1A_9
VDD1A_10
VDD25A_9
TDP_2
FIBROP_1
FIBRIP_1
RDP_1
TDP_1
TDN_2
FIBRON_1
FIBRIN_1
RDN_1
TDN_1
6.3
L
GPIO2/SIGDET2
GPIO3/SIGDET3
M
SerDes_Rext_1 GPIO0/SIGDET0
TDP_0
TDN_0
N
VDD25A_10 SerDes_Rext_0
RDP_0
RDN_0
P
FIBROP_0
FIBRIP_0
VSS_70
R
FIBRON_0
FIBRIN_0
NC_4
T
VDD25_3
GPIO1/SIGDET1
Pins by Function
This section contains the functional pin descriptions for the VSC8574-02 device.
6.3.1
1588 Support
The following table lists the 1588 support pins.
Table 725 • 1588 Support Pins
Name
Pin
Type
Description
1588_DIFF_INPUT_CLK_
N
1588_DIFF_INPUT_CLK_
P
J16
J15
ADIFF
Differential reference clock input pair.
RESERVED_9
N3
NC
Leave pin unconnected (floating).
VMDS-10510 VSC8574-02 Datasheet Revision 4.2
382
Pin Descriptions
Table 725 • 1588 Support Pins (continued)
6.3.2
Name
Pin
Type
Description
RESERVED_10
N4
NC
Leave pin unconnected (floating).
RESERVED_11
L2
NC
Leave pin unconnected (floating).
1588_SPI_CLK
E16
O
1588 SPI clock.
GPIO and 1588 Support
The following table lists the GPIO and 1588 support pins.
Table 726 • GPIO and 1588 Support Pins
6.3.3
Name
Pin
GPIO10/1588_LOAD_SAVE
K15 I/O, PU, 3 V
Type
Description
Sync signal to load the time to the 1588
engine. Rising edge triggered.
GPIO12/1588_SPI_CS
J14
I/O, PU, 3 V
1588 SPI chip select.
GPIO13/1588_SPI_DO
H14 I/O, PU, 3 V
1588 SPI data output.
GPIO and SIGDET
The following table lists the GPIO and SIGDET pins.
Table 727 • GPIO and SIGDET Pins
6.3.4
Name
Pin
Type
Description
GPIO0/SIGDET0
GPIO1/SIGDET1
GPIO2/SIGDET2
GPIO3/SIGDET3
GPIO4/I2C_SCL_0
GPIO5/I2C_SCL_1
GPIO6/I2C_SCL_2
GPIO7/I2C_SCL_3
GPIO8/I2C_SDA
GPIO9/FASTLINK-FAIL
GPIO11
N14
M14
M15
M16
L13
L14
L15
L16
K13
K14
K16
I/O, PU, 3 V
General purpose input/output (GPIO). The
multipurpose SIGDET pins, two-wire serial
controller pins, and fast link fail pin can be
configured to serve as GPIOs.
JTAG
The following table lists the JTAG test pins.
Table 728 • JTAG Pins
Name
Pin
Type
Description
TCK
F3
I, PU, ST, 3 V
JTAG test clock input.
TDI
F2
I, PU, ST, 3 V
JTAG test serial data input.
TDO
F1
O
JTAG test serial data output.
TMS
E2
I, PU, ST, 3 V
JTAG test mode select.
TRST
E3
I, PU, ST, 3 V
JTAG reset.
Important When JTAG is not in use, this pin must be tied to
ground with a pull-down resistor for normal operation.
VMDS-10510 VSC8574-02 Datasheet Revision 4.2
383
Pin Descriptions
6.3.5
Miscellaneous
The following table lists the miscellaneous pins.
Table 729 • Miscellaneous Pins
Name
Pin
Type
Description
CLK_SQUELCH_IN
E15
I, PU,
3V
Input control to squelch recovered clock.
COMA_MODE
L3
I, PU,
3V
When this pin is asserted high, all PHYs are held
in a powered down state. When de-asserted low,
all PHYs are powered up and resume normal
operation. This signal is also used to synchronize
the operation of multiple chips on the same PCB to
provide visual synchronization for LEDs driven by
separate chips.(1)
LED0_[0:3]
LED1_[0:3]
LED2_[0:3]
LED3_[0:3]
G1, H1, J1, K1
G2, H2, J2, K2
G3, H3, J3, K3
G4, H4, J4, K4
O
LED direct-drive outputs. All LEDs pins are
active-low. A serial LED stream can also be
implemented. See LED Mode Select, page 109.
Note: LEDbit_port, where port = PHY port
number and bit = the particular LED
for the port.
NC_1
NC_2
NC_3
NC_4
A1
A16
T1
T16
NC
No connect.
PHYADD2
PHYADD3
PHYADD4
G13
G14
F14
I, PD,
3V
Device SMI address bits 4:2.
RCVRDCLK1
RCVRDCLK2
F16
G16
O
Clock output can be enabled or disabled and also
output a clock frequency of 125 MHz or 25 MHz
based on the selected active recovered media
programmed for this pin. This pin is not active
when NRESET is asserted. When disabled, the
pin is held low.
REF_FILT_A
D3
ABIAS
Reference filter connects to an external 1 µF
capacitor to analog ground.
REF_REXT_A
D4
ABIAS
Reference external connects to an external 2 kΩ
(1%) resistor to analog ground.
REFCLK_N
REFCLK_P
C1
D1
I,
ADIFF
125 MHz or 25 MHz reference clock input pair.
Must be capacitively coupled and LVDS
compatible.
REFCLK_SEL2
E1
I, PU,
3V
Selects the reference clock speed:
0: 25 MHz (VSS)
1: 125 MHz (2.5 V)
Use 125 MHz for typical applications.
RESERVED_[1:8]
C10, D13, L4,
NC
P4, L1, M1, N1,
P1
Leave these pins unconnected (floating).
THERMDA
C3
A
Thermal diode anode.
THERMDC_VSS
D2
A
Thermal diode cathode connected to device
ground. Temperature sensor must be chosen
accordingly.
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Pin Descriptions
1.
6.3.6
For more information, see Initialization, page 92. For a typical bring-up example, see Configuration, page 91.
Power Supply
The following table lists the power supply pins and associated functional pins. All power supply pins must
be connected to their respective voltage input, even if certain functions are not used for a specific
application. No power supply sequencing is required. However, clock and power must be stable before
releasing Reset.
Table 730 • Power Supply Pins
6.3.7
Name
Pin
Type
Description
VDD1_[1:18]
E5, E12, F5, F12, G5, G12,
H5, H12, J5, J12, K5, K12,
L5, L12, M5, M12, N5, N12
1.0 V
1.0 V internal digital logic.
VDD1A_[1:10]
C7, C8, C9, C13, P6, P7, P8, 1.0 V
P9, P10, P11
1.0 V analog power requiring additional
PCB power supply filtering. Associated
with the QSGMII/SGMII MAC receiver
output pins.
VDD25_[1:4]
H13, M4, M13, P3
2.5 V
2.5 V general digital power supply.
Associated with the LED, GPIO, JTAG,
twisted pair interface, reference filter,
reference external supply connect, and
recovered clock pins.
VDD25A_[1:10]
C2, C4, C6, C11, C14, E4,
E13, P5, P12, P13
2.5 V
2.5 V general analog power supply.
VSS_[1:4]
VSS_[6:78]
B1, B16, C5, C12
0V
D5, D6, D7, D8, D9, D10,
D11, D12, E6, E7, E8, E9,
E10, E11, F4, F6, F7, F8, F9,
F10, F11, G6, G7, G8, G9,
G10, G11, H6, H7, H8, H9,
H10, H11, J6, J7, J8, J9, J10,
J11, K6, K7, K8, K9, K10,
K11, L6, L7, L8, L9, L10, L11,
M6, M7, M8, M9, M10, M11,
N6, N7, N8, N9, N10, N11,
R1, R16, D14, E14, F13, F15,
G15, H15, H16, J13
General device ground.
SGMII/SerDes/QSGMII MAC Interface
The following table lists the SerDes MAC interface pins.
Table 731 • SerDes MAC Interface Pins
Name
Pin
Type
Description
RDN_0
RDP_0
P16
P15
O, ADIFF
PHY0 QSGMII/SGMII/SerDes MAC receiver output pair.
RDN_1
RDN_2
RDN_3
RDP_1
RDP_2
RDP_3
T12
T8
T4
R12
R8
R4
O, ADIFF
SGMII/SerDes MAC receiver output pair.
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Pin Descriptions
Table 731 • SerDes MAC Interface Pins (continued)
6.3.8
Name
Pin
Type
Description
SerDes_Rext_0
P14
ABIAS
SerDes bias pins. Connect to a 620 Ω 1% resistor between
SerDes_Rext_0 and SerDes_Rext_1.
SerDes_Rext_1
N13
ABIAS
SerDes bias pins. Connect to a 620 Ω 1% resistor between
SerDes_Rext_0 and SerDes_Rext_1.
TDN_0
TDP_0
N16
N15
I, ADIFF
PHY0 QSGMII/SGMII/SerDes MAC transmitter input pair.
TDN_1
TDN_2
TDN_3
TDP_1
TDP_2
TDP_3
T13
T9
T5
R13
R9
R5
I, ADIFF
SGMII/SerDes MAC transmitter input pair.
SerDes Media Interface
The following table lists the SerDes media interface pins.
Table 732 • SerDes Media Interface Pins
6.3.9
Name
Pin
Type
Description
FIBRIN_0
FIBRIN_1
FIBRIN_2
FIBRIN_3
T15 I, ADIFF
T11
T7
T3
SerDes media receiver input pair.
FIBRIP_0
FIBRIP_1
FIBRIP_2
FIBRIP_3
R15 I, ADIFF
R11
R7
R3
SerDes media receiver input pair.
FIBRON_0
FIBRON_1
FIBRON_2
FIBRON_3
T14 O, ADIFF SerDes media transmitter output pair.
T10
T6
T2
FIBROP_0
FIBROP_1
FIBROP_2
FIBROP_3
R14 O, ADIFF SerDes media transmitter output pair.
R10
R6
R2
Serial Management Interface
The following table lists the serial management interface (SMI) pins. The SMI pins are referenced to
VDD25 and can be set to a 2.5 V power supply.
Table 733 • SMI Pins
Name
Pin
Type
Description
MDC
P2
I, PD, 3 V
Management data clock. A 0 MHz to 12.5 MHz reference input is
used to clock serial MDIO data into and out of the PHY.
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Pin Descriptions
Table 733 • SMI Pins (continued)
Name
Pin
Type
Description
MDINT
M2
I/O, OS, OD
Management interrupt signal. Upon reset the device will configure
these pins as active-low (open drain) or active-high (open source)
based on the polarity of an external 10 kΩ resistor connection.
These pins can be tied together in a wired-OR configuration with
only a single pull-up or pull-down resistor.
MDIO
N2
I/O, OD
Management data input/output pin. Serial data is written or read
from this pin bidirectionally between the PHY and Station Manager,
synchronously on the positive edge of MDC. One external pull-up
resistor is required at the Station Manager, and its value depends
on the MDC clock frequency and the total sum of the capacitive
loads from the MDIO pins.
NRESET M3
6.3.10
I, PD, ST, 3 V Device reset. Active low input that powers down the device and
sets all register bits to their default state.
Twisted Pair Interface
The following table lists the twisted pair interface pins.
Table 734 • Twisted Pair Interface Pins
Name
Pin
Type
Description
TXVNA_0
TXVNA_1
TXVNA_2
TXVNA_3
B14
B10
B6
B2
ADIFF TX/RX channel A negative signal
TXVNB_0
TXVNB_1
TXVNB_2
TXVNB_3
B15
B11
B7
B3
ADIFF TX/RX channel B negative signal
TXVNC_0
TXVNC_1
TXVNC_2
TXVNC_3
C15
B12
B8
B4
ADIFF TX/RX channel C negative signal
TXVND_0
TXVND_1
TXVND_2
TXVND_3
D15
B13
B9
B5
ADIFF TX/RX channel D negative signal
TXVPA_0
TXVPA_1
TXVPA_2
TXVPA_3
A14
A10
A6
A2
ADIFF TX/RX channel A positive signal
TXVPB_0
TXVPB_1
TXVPB_2
TXVPB_3
A15
A11
A7
A3
ADIFF TX/RX channel B positive signal
TXVPC_0
TXVPC_1
TXVPC_2
TXVPC_3
C16
A12
A8
A4
ADIFF TX/RX channel C positive signal
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Pin Descriptions
Table 734 • Twisted Pair Interface Pins (continued)
Name
Pin
Type
Description
TXVPD_0
TXVPD_1
TXVPD_2
TXVPD_3
D16
A13
A9
A5
ADIFF TX/RX channel D positive signal
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Package Information
7
Package Information
VSC8574XKS-02 and VSC8574XKS-05 are packaged in a lead(Pb)-free, 256-pin, plastic ball grid array
(BGA) with a 17 mm × 17 mm body size, 1 mm pin pitch, and 1.8 mm maximum height.
Lead(Pb)-free products from Microsemi comply with the temperatures and profiles defined in the joint
IPC and JEDEC standard IPC/JEDEC J-STD-020. For more information, see the IPC and JEDEC
standard.
This section provides the package drawing, thermal specifications, and moisture sensitivity rating for the
VSC8574-02 device.
7.1
Package Drawing
The following illustration shows the package drawing for the VSC8574-02 device. The drawing contains
the top view, bottom view, side view, dimensions, tolerances, and notes.
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Package Information
Figure 93 • Package Drawing
Top View
Bottom View
0.20 (4×)
Pin A1 corner
X
17.00
Pin A1 corner
16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
1.00
15.00
17.00
1.00
Y
15.00
0.31–0.43
Side View
0.25 Z
1.8 maximum
4
Z
Seating plane
5
0.20 Z
Ø 0.45–0.64
Ø 0.25 M
Ø 0.10 M
Z X Y
Z
Notes
1. All dimensions and tolerances are in millimeters (mm).
2. Ball diameter is 0.50 mm.
3. Radial true position is represented by typical values.
4. Primary datum Z and seating plane are defined by the
spherical crowns of the solder balls.
5. Dimension is measured at the maximum solder ball
diameter, parallel to primary datum Z.
7.2
Thermal Specifications
Thermal specifications for this device are based on the JEDEC JESD51 family of documents. These
documents are available on the JEDEC Web site at www.jedec.org. The thermal specifications are
modeled using a four-layer test board with two signal layers, a power plane, and a ground plane (2s2p
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Package Information
PCB). For more information about the thermal measurement method used for this device, see the
JESD51-1 standard.
Table 735 • Thermal Resistances
Symbol
°C/W
Parameter
θJCtop
5.9
Die junction to package case top
θJB
12.7
Die junction to printed circuit board
θJA
22
Die junction to ambient
θJMA at 1 m/s
18.5
Die junction to moving air measured at an air speed of 1 m/s
θJMA at 2 m/s
16.3
Die junction to moving air measured at an air speed of 2 m/s
To achieve results similar to the modeled thermal measurements, the guidelines for board design
described in the JESD51 family of publications must be applied. For information about applications using
BGA packages, see the following:
•
•
•
•
7.3
JESD51-2A, Integrated Circuits Thermal Test Method Environmental Conditions, Natural Convection
(Still Air)
JESD51-6, Integrated Circuit Thermal Test Method Environmental Conditions, Forced Convection
(Moving Air)
JESD51-8, Integrated Circuit Thermal Test Method Environmental Conditions, Junction-to-Board
JESD51-9, Test Boards for Area Array Surface Mount Package Thermal Measurements
Moisture Sensitivity
This device is rated moisture sensitivity level 4 as specified in the joint IPC and JEDEC standard
IPC/JEDEC J-STD-020. For more information, see the IPC and JEDEC standard.
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Design Considerations
8
Design Considerations
This section provides information about design considerations for the VSC8574-02 device.
8.1
Link status LED remains on while COMA_MODE pin is
asserted high
When the COMA_MODE is asserted high, the link status LED may not deactivate unless the media cable
is disconnected from the device.
While using COMA_MODE, link status should be verified using status registers rather than LED
indicators.
8.2
LED pulse stretch enable turns off LED pins
Enabling the pulse stretch function for LED0 or LED1 by setting register 30, bits 5:6 shuts off those LED
pins.
Use the default blink function setting of LED0 and LED1 rather than pulse stretching. For more
information, see LED Behavior, page 110.
8.3
AMS and 100BASE-FX
When the PHY operating mode (set in register 23) is AMS and the current active media is 100BASE-FX,
register 0 bit 12 will be 0. This would normally indicate that auto-negotiation is disabled and the PHY is in
forced mode. But in this mode, it has other meanings.
The workaround is to ensure that bit 12 is always written as 1 when doing writes or updates to register 0
in AMS mode.
8.4
10BASE-T signal amplitude
10BASE-T signal amplitude can be lower than the minimum specified in IEEE 802.3 paragraph
14.3.1.2.1 (2.2 V) at low supply voltages.
This issue is not estimated to present any system level impact. Performance is not impaired with cables
up to 130 m with various link partners.
8.5
10BASE-T link recovery failures
If the link disconnects when traffic is flowing while the device operates in a 10BASE-T mode, the PHY
may not re-link.
There is a software workaround for this issue in which the device's internal microcontroller monitors link
transitions in 10BASE-T mode and forces a soft power-down/power-up procedure to prevent a re-link
failure.
A side effect of this software workaround is that the counts in registers 20 and 21 will be cleared (For
more information, see Error Counter 2, page 104 and Error Counter 3, page 104).
8.6
SNR degradation and link drops
The link may drop after approximately 100 master/slave relationship swaps with the ring resiliency
feature when using Category 5 (Cat5) cables that are longer than 75 m.
The workaround is to use a combination of an initialization script and a procedure change. Contact
Microsemi for the workaround solution if the ring resiliency feature is being enabled.
8.7
Clause 45 register 3.22
The clause 45, register 3.22 is cleared upon read only when the extended page access register (register
31) is set to 0.
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Design Considerations
This register cannot be read when the page access register is set to a value other than 0.
The workaround is to set extended page access register to 0 before accessing clause 45, register 3.22.
8.8
Clause 45 register 3.1
Clause 45, register 3.1, Rx and Tx LPI received bits are cleared upon read only when the extended page
access register (register 31) is set to 0.
This has a minor implication for software that needs to ensure that the extended page access register is
set to 0 before reading clause 45, register 3.1.
The workaround is to set extended page access register to 0 before accessing clause 45, register 3.1.
8.9
Clause 45 register address post-increment
Clause 45 register address post-increment only works when reading registers and only when extended
page access register (register 31) is set to 0.
The workaround is to access the registers individually.
8.10
Fast link failure indication
The fast link failure indication for all the ports is enabled using port 0, register 19E.4.
The workaround is to set register 19E.4 = 1 in PHY 0 to enable Fast Link Fail indication.
8.11
Timestamp accuracy in 10BASE-T mode
Timestamp accuracy in 10BASE-T mode is ±400 ns.
Timing accuracy is reduced on networks running in 10BASE-T mode. There is currently no workaround
for this issue.
8.12
Near-end loopback with AMS enabled
Near-end loopback does not work when AMS is enabled. Near-end loopback is controlled by setting bit
14 of register 0.
The workaround is to disable AMS when enabling loopback. This is a debug feature and does not have
any real life implications.
8.13
Carrier detect assertion
Carrier detect assertion is set to false incorrectly when 9 out of 10 bits in the K28.1 word are in error.
No real life implication is expected, because the event that can trigger this error is extremely unlikely. If it
does occur, the link may drop momentarily and come back up.
8.14
Link status not correct in register 24E3.2 for 100BASEFX operation
The link status in register 24E3.2 only reflects the status of 1000BASE-X links. It does not reflect the
status of 100BASE-FX links.
The workaround is to check register 28.4:3 for media operating mode (10 for fiber), 28.4:3 for speed
status (100 for 100 Mbps), and then check 16.12 for current link status.
8.15
Register 28.14 does not reflect autonegotiation disabled
in 100BASE-FX mode
Register 28.14 does not reflect autonegotiation status in 100BASE-FX mode. It works correctly in all
copper and 1000BASE-X media modes.
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Design Considerations
The workaround is to use register 0.12 for autonegotiation status in 100BASE-FX mode when AMS is
disabled. For more information about limitations when AMS is enabled, see AMS and 100BASE-FX,
page 392.
8.16
Near-end loopback non-functional in protocol transfer
mode
Near-end loopback does not work correctly when the device is configured in protocol transfer mode.
This is a debug feature and does not have any effect on the normal operation of the device.
8.17
Fiber-media CRC counters non-functional in protocol
transfer mode at 10 Mbps and 100 Mbps
Packets received on the media SerDes interface will not be counted correctly in registers 28E3 and 29E3
when the device is configured in protocol transfer mode and operating at 10 Mbps or 100 Mbps speeds.
These counters are used for debugging and there is no effect on the normal operation of the device.
8.18
Fiber-media recovered clock does not squelch based on
link status
To squelch the clock in fiber media mode, code sync status is used instead of link status. This causes the
clock to not be squelched if the device is configured in 1000BASE-X mode with autonegotiation enabled
when the transmit fiber is unplugged.
There is a software workaround for this issue where the device's internal microcontroller monitors link
status and forces the clock off when no link is present.
8.19
1000BASE-X parallel detect mode with Clause 37
autonegotiation enabled
When connected to a forced-mode link partner and attempting autonegotiation, the PHY in 1000BASEX
parallel detect mode requires a minimum 250 ms IDLE stream in order to establish a link. If the PHY port
is programmed with 1000BASE-X parallel detect-enabled (MAC-side register 16E3 bit 13, or media-side
register 23E3 bit 13), then a forced-mode link partner sending traffic with an inter-packet gap less than
250 ms will not allow the local device’s PCS to transition from a link-down to link-up state.
8.20
Anomalous PCS error indications in Energy Efficient
Ethernet mode
When a port is processing traffic with Energy Efficient Ethernet enabled on the link, certain PCS errors
(such as false carriers, spurious start-of-stream detection, and idle errors) and EEE wake errors may
occur. There is no effect on traffic bit error rate for cable lengths up to 75 meters, and minor packet loss
may occur on links longer than 75 meters. Regardless of cable length, some error indications should not
be used while EEE is enabled. These error indications include false carrier interrupts (Interrupt Status
register 26 bit 3), receive error interrupts (Interrupt Status register 26 bit 0), and EEE wake error
interrupts.
Contact Microsemi for a script that needs to be applied during system initialization if EEE will be enabled.
8.21
Long link-up times while in forced 100BASE-TX mode of
operation
While in forced 100BASE-TX operation and attempting to link up, the device may experience abnormally
long link-up times.
This issue can only occur if the Unified API is not used with the device. In those circumstances, the
workaround for this issue is to clear all speed advertisements in the autonegotiation advertisement
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Design Considerations
registers (register 4, bits 9:5 and register 9, bits 9:8), then toggle the auto-negotiation enable bit of the
mode control register (register 0, bit 12) for a port upon detecting its link is down. Any advertisements
temporarily cleared can then be restored once register 0, bit 12 is cleared.
Contact Microsemi for the latest code sequence included in the Unified API.
8.22
Timestamp errors due to IEEE 1588 Reference Clock
interruption
Interruption of the IEEE 1588 reference clock after release of device hardware reset will corrupt the local
time counter (LTC) value. After clock interruption, an LTC reload is required using the Unified API.
8.23
1588 bypass shall be enabled during engine
reconfiguration
When the 1588 datapath is enabled, the 1588 bypass feature shall be enabled before reprogramming
1588 configuration registers. It is recommended to disable 1588 bypass before live traffic begins flowing
through the re-provisioned port.
8.24
Missing clock pulses on serial timestamp output
interface
The serial timestamp output interface may not generate the final 1588_SPI_CLK cycle for certain
timestamp push-out transactions. This issue can be worked around by programming the
SI_CLK_LO_CYCS to value 0x1.
Use the latest PHY API for a workaround to this issue.
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Ordering Information
9
Ordering Information
The VSC8574 device is offered with two operating temperature ranges. The range for VSC8574-02 is
0 °C ambient to 125 °C junction, and the range for VSC8574-05 is -40 °C ambient to 125 °C junction.
VSC8574XKS-02 and VSC8574XKS-05 are packaged in a lead(Pb)-free, 256-pin, plastic ball grid array
(BGA) with a 17 mm × 17 mm body size, 1 mm pin pitch, and 1.8 mm maximum height.
Lead(Pb)-free products from Microsemi comply with the temperatures and profiles defined in the joint
IPC and JEDEC standard IPC/JEDEC J-STD-020. For more information, see the IPC and JEDEC
standard.
The following table lists the ordering information for the VSC8574-02 device.
Table 736 • Ordering Information
Part Order Number
Description
VSC8574XKS-02
Lead-free, 256-pin, plastic BGA with a 17 mm × 17 mm body size, 1 mm
pin pitch, and 1.8 mm maximum height. The operating temperature is 0 °C
ambient to 125 °C junction1.
VSC8574XKS-05
Lead-free, 256-pin, plastic BGA with a 17 mm × 17 mm body size, 1 mm
pin pitch, and 1.8 mm maximum height. The operating temperature is
–40 °C ambient to 125 °C junction1.
1.
For carrier class applications, the maximum operating temperature is 110 °C junction.
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