ZG2100MC

M ZG2100M/ZG2101M ® Wi-Fi Module Data Sheet 2.4 GHz 802.11b Low Power Transceiver Module © 2010 Microchip Technology DS70624A – page 1 Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. 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SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. © 2010, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. ISBN: 978-1-60932-064-5 Microchip received ISO/TS-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified. DS70624A – page 2 © 2010 Microchip Technology ZG2100M/ZG2101M 2.4 GHz 802.11b Low Power Transceiver Module Utility and Smart Energy - Thermostats Smart Meters White Goods HVAC Remote Device Management Location and Asset Tracking Automotive Code Update - Consumer Electronics - Remote Control Internet Radio Home Security Toys Industrial Controls Retail - POS Terminals Wireless Price Tags Digital Remote Signage Chemical Sensors HVAC Security Systems M2M Communication - Medical, Fitness, and Healthcare - Glucose Meters Fitness Equipment Patient Asset Tracking Features • Single-chip 802.11b including MAC, baseband, RF and power amplifier • Data Rate: 1 & 2 Mbps • 802.11b/g/n compatible • Low power operation • API for embedded markets, no OS required • PCB or external antenna options • Hardware support for AES and RC4 based ciphers (WEP, WPA, WPA2 security) • SPI slave interface with interrupt • Single 3.3V supply, operates from 2.7V to 3.6V (see section 5) • 21mm x 31mm 36-pin Dual Flat pack PCB SM Package • Wi-Fi Certified, RoHS and CE compliant • FCC Certified (USA, FCC ID: W7O-ZG2100-ZG2101) • IC Certified (IC: 8248A-G21ZEROG) • Fully compliant with EU & meets the R&TTE Directive for Radio Spectrum • Radio Type Approval Certified (Japan, ZG2100M based solution ID: AC164136-2 – 005WWCA0311 005GZCA0149) © 2010 Microchip Technology DS70624A – page 3 ZG2100M/ZG2101M Description The ZG2100M & ZG2101M modules are low-power 802.11b implementations. All RF components, the baseband and the entirety of the 802.11 MAC reside on-module, creating a simple and cost-effective means to add Wi-Fi connectivity for embedded devices. The module(s) implement a high-level API, simplifying design implementation and allowing the ZG2100M or ZG2101M to be integrated with 8- and 16-bit host microcontrollers. Hardware accelerators support the latest Wi-Fi security standards. Figure 1: ZG2100M/ZG2101M Module: Functional Block Diagram DS70624A – page 4 © 2010 Microchip Technology ZG2100M/ZG2101M Table of Contents 1. 1. Key Features ............................................................................................................................................. 6 2. Detailed Description ...................................................................................................................................... 7 2.1 ....... Overview ........................................................................................................................................... 7 2.2 ....... Supply Blocks and Boot-Up Sequence for Single 3.3V Supply........................................................ 7 2.3 ....... ZG2100 Power States ...................................................................................................................... 9 2.4 ....... Electrostatic discharge (ESD)......................................................................................................... 10 2.5 ....... JTAG Interface................................................................................................................................ 10 2.6 ....... Serial Interface for Trace ................................................................................................................ 10 2.7 ....... SPI Interface ................................................................................................................................... 10 2.7.1 SPI Slave Interface with Interrupt for Host Operation ....................................................... 10 2.7.2 Host-Control SPI Interface................................................................................................. 10 2.7.3 SPI Timing Characteristics ................................................................................................ 11 2.7.4 SPI Timing ......................................................................................................................... 12 2.7.5 SPI Register Access .......................................................................................................... 13 2.8 ....... FIFO Interface................................................................................................................................. 14 2.8.1 FIFO Read ......................................................................................................................... 14 2.8.2 FIFO Write ......................................................................................................................... 15 2.9 ....... Fully-Integrated Radio .................................................................................................................... 15 2.10 ..... Internal ROM/RAM/NVM ................................................................................................................ 15 2.11 ..... Hardware Support for AES and TKIP ............................................................................................. 15 3. ZG2100M/ZG2101M Pin-Out and Function ................................................................................................ 16 4. Package Information .................................................................................................................................... 18 4.1. ...... Module Drawing .............................................................................................................................. 18 4.2 ....... Module Layout Guidelines .............................................................................................................. 20 4.3 ....... Module Use Schematic ................................................................................................................... 21 5. Electrical Characteristics ............................................................................................................................. 23 5.1 ....... Power Consumption ....................................................................................................................... 23 6. Radio Characteristics .................................................................................................................................. 25 6.1 ....... Transmitter 2.4GHz Band ............................................................................................................... 25 6.2 ....... Receiver 2.4GHz Band ................................................................................................................... 25 7. Digital Electrical Characteristics .................................................................................................................. 26 8. Module Reflow Profile .................................................................................................................................. 27 9. Ordering Information .................................................................................................................................... 28 10. Regulatory Notes ......................................................................................................................................... 29 11. Revision History ........................................................................................................................................... 31 © 2010 Microchip Technology DS70624A – page 5 ZG2100M/ZG2101M 1 Key Features Ease of Software Development • Simple API suited for embedded market • Targeted for low resource host processors • Entire MAC integrated on-chip • Serialized MAC address, each device comes with an unique MAC address in range 001EC0xxxxxx • Simple usage model, no requirement for OS Low Power Operation • Low power, 250uA sleep mode with fast wake up, 0.1uA hibernate, • Sleep power state managed by ZG2100, enabling low average power while maintaining AP association without host control • Battery operable from 2.7v to 3.6v (see power specs for limitations) RF • Integrated PA • Support for external PA for high RF output power applications • Power output +10dBm typical at antenna • Power output programmable from +0dBm to meet varying application needs • Min RX sens.of-91dBm @ 1MB/Sec. at antenna • Integrated PCB antenna (ZG2100M) • Support for external antenna available (ZG2101M) Low External Component Count • Fully integrated RF frequency synthesizer, reference clock, and Integrated PA • Single 3.3V supply Wi-Fi & Regulatory • Supports 1Mbps & 2Mbps and module-based solutions are “Wi-Fi certified” for 802.11b • Hardware support for AES, and RC4 based ciphers (WEP, WPA, WPA2 security) • FCC Certified (USA, FCC ID: W7O-ZG2100-ZG2101), IC Certified (IC: 8248AG21ZEROG), Radio Type Approval Certified (Japan, ZG2100M based solution ID: AC164136-2 – 005WWCA0311 005GZCA0149, Wi-Fi Certified, RoHS and CE compliant, and fully compliant with European Market and meet the R&TTE Directive for Radio Spectrum DS70624A – page 6 © 2010 Microchip Technology ZG2100M/ZG2101M 2. Detailed Description 2.1 Overview The ZG2100 single-chip 802.11b transceiver includes MAC, baseband, RF and power amplifier, and built in hardware support for AES, and TKIP (WEP, WPA, WPA2 security). The device has an API targeted for embedded markets so an operating system is not required for operation. There is a fully integrated radio ideal for 1 & 2Mbps operation with optional support for external PA and antenna switch operation. The ZG2100M modules incorporate the ZeroG ZG2100 single chip 802.11b transceiver with all associated RF components, crystal oscillator, and bypass and bias passives along with a printed antenna to provide a fully integrated Wi-Fi I/O solution controllable from an 8 or 16bit processor. The ZG2101M module is similar but bypasses the on-board PCB antenna and uses a U.FL connector for connection to an external antenna. Interface is via SPI slave interface with interrupt for HOST operation. The modules support RS232 serial interfaces (requires level shifter) for debug and JTAG boundary scan. Operation is via a single 3.3V supply, supporting various power states, such as hibernate and SLEEP, for end applications long battery life. ZG2100M contains a built in PCB antenna for ease of system integration and significant BOM reduction. The module is manufactured on an FR4 PCB substrate, with components on the top surface only. Connection is made as a surface mount component via flat pack (no pin) connections on two sides. 2.2 Supply Blocks and Boot-Up Sequence for Single 3.3V Supply The internal regulators for the digital and analog core power supplies are enabled by keeping the chip enable pin (CE_N) low. The waveforms for the core supplies, illustrated on the following page, as shown when powering up the ZG2100M/ZG2101M with a nominal 3.3V applied to VDD_3.3. There is an internal power-on-reset detect which starts the boot sequence from the internal ROM when the core supply (VDD_1.8) is up. After approximately 50 ms from when VDD_3.3 supply is within specification, the ZG2100M/ZG2101M is ready for operation. © 2010 Microchip Technology DS70624A – page 7 ZG2100M/ZG2101M Figure 2: ZG2100M/ZG2101M Boot Sequence Timing. Refer to Section 4.1 Electrical Characteristics, Note 1. DS70624A – page 8 © 2010 Microchip Technology ZG2100M/ZG2101M 2.3 ZG2100 Power States The power state definitions are as follows: VDD_3.3 CE_N Circuitry OFF 0V 0V Power disconnected to ZG2100 HIBERNATE 3.3V 3.3V All internal circuitries are OFF SLEEP 3.3V 0V Reference clock and internal bias circuitry are ON RX ON 3.3V 0V Receive circuits are ON TX ON 3.3V 0V Transmit circuits are ON STANDBY Transition State Only Figure 3: ZG2100M/ZG2101M Power State Diagram © 2010 Microchip Technology DS70624A – page 9 ZG2100M/ZG2101M 2.4 Electrostatic discharge (ESD) The ZG2100 IC, integrated within the ZG2100M/ZG2101M, has passed ESD HBM JEDEC Standard No. 22-A114 / 2000 Volts and ESD CDM JEDEC Standard No. 22-C101 / 500V all pins. Users must exercise ESD handling precautions when working with the product either in component form, or exposed PCBs. 2.5 JTAG Interface Joint Test Action Group (JTAG) is the common name used for the IEEE 1149.1 standard entitled Standard Test Access Port and Boundary-Scan Architecture for test access ports used for testing printed circuit boards using boundary scan. ZG2100M/ZG2101M supports JTAG boundary scan. JTAG_EN and JTAG_RST_N need to be driven HIGH to enable JTAG mode. 2.6 Serial Interface for Trace ZG2100M/ZG2101M incorporates Transmitted Data pin (UART0_TX) and Received Data pin (UART0_RX) for serial testing purposes. These pins can be connected to commercially available RS-232 line drivers/ receivers with appropriate external level shifters. The ZG2100 serial interface is fully tested at 115200 bits/seconds baud rate with RS232/UART interface applications. 2.7 SPI Interface 2.7.1 SPI Slave Interface with Interrupt for Host Operation The slave Serial Peripheral Interface Bus (SPI) is used to interface with the HOST. The slave SPI interface works with ZG2100M/ZG2101M Interrupt line (INT_NX). When data is available for the HOST during operation, the INT_NX line is asserted low by ZG2100. The INT_NX line is de-asserted high, by ZG2100M/ZG2101M, after the data is transferred to the HOST SPI buffer. The SPI CLK Speed can be up to 25MHz. 2.7.2 Host-Control SPI Interface The slave SPI interface implements the [CPOL=0; CPHA=0] and [CPOL=0; CPHA=1] modes (0 and 3) of operation. That is, data is clocked in on the first rising edge of the clock after Chip Select goes valid. Data on the bus is required to be big endian, with most significant bit on the bus first and least significant bit going last. There are two decode regions. One for register access and one for a FIFO interface. Operation for both regions is shown below. The INT_NX signal allows interrupts to be signaled to the host device. DS70624A – page 10 © 2010 Microchip Technology ZG2100M/ZG2101M As an example of any 32-bit register access, suppose a write to register 0xF0_0F18 is desired: Write to host register 0x38 with addr[31:16] (0x00f0). 24 bit transaction. Write to host register 0x39 with addr[15:0] (0x0F18). 24 bit transaction. Write to host register 0x3a with data[31:16]. 24 bit transaction. Write to host register 0x3b with data[15:0]. 24 bit transaction. Write to host register 0x37 with a byte that has the following pattern: 8 bit transaction [7:4] byte enables (active high for the valid bytes that you want to write in steps 3 and 4). [3:0] - 4’b0001 -> activate write to register For a read of 0xF0_0D00: Write to host register 0x38 with addr[31:16] (0x00F0). 24 bit transaction. Write to host register 0x39 with addr[15:0] (0x0F18). 24 bit transaction. Write to host register 0x37 with a byte that has the following pattern: 8 bit transaction [7:4] byte enables (active high for the valid bytes that you want to read in steps 1 and 2). [3:0] - 4’b0011 -> active read of register Read host register 0x3a to get data [31:24] 24 bit transaction Read host register 0x3b to get data [15:0] 24 bit transaction Each of the steps above is a single SPI transaction; the chip select (CE_N) is active low during each step. 2.7.3 SPI Timing Characteristics Characteristic Min SPI, Data setup to falling clock 1 ns SPI, Data hold from falling clock 1 ns Max SPI SLAVE CLK 25 MHz SPI MASTER CLK 25 MHz Figure 4: ZG2100M/ZG2101M SPI Timing Characteristics © 2010 Microchip Technology DS70624A – page 11 ZG2100M/ZG2101M 2.74 SPI Timing Figure 5: ZG2100M/ZG2101M SPI Timing Waveform Symbol Parameter Min Tsck SCK Clock Period 40 ns Tcs SCS_N High Time 50 ns Tcss SCS_N Setup Time 50 ns Tcsh SCS_N Hold Time 50 ns Tsetup SDI Setup Time 10 ns Thold SDI Hold Time 10 ns Tvalid Output Valid Tho Output Hold Time Typ Max 15 ns 0 15 ns Figure 6: ZG2100M/ZG2101M SPI Timing Data DS70624A – page 12 © 2010 Microchip Technology ZG2100M/ZG2101M 2.7.5 SPI Register Access Figure 7: ZG2100M/ZG2101M SPI Register Access F is a select between FIFO space and register space. If this bit is a 1, the data FIFO space is selected. If this bit is a 0, the register address space is selected. R is the Read/Write bit. If this bit is a 1, the operation is a read. If this bit is a 0, the operation is a write ADDR0 is the starting address for the transaction. This value is only used for register accesses and is ignored during FIFO accesses. WDATAn is the write data byte. This is only used from write operations and is ignored during read operations. RDATAn is the read data byte. This is always valid for both, read and write operations. If contains the current value of any register location. HOST_INTR is the 8-bit interrupt register. © 2010 Microchip Technology DS70624A – page 13 ZG2100M/ZG2101M 2.8 FIFO Interface HOST FIFO Basic Commands FCMD[2:0] 0x0 – RFIFO_CMD 0x1 – WCONT (Continue Previous Packet) 0x2 – WSTART0 (Start Packet, head/continue) 0x3 – WSTART1 (Start Packet, head0/continue) 0x4 – WEND CMD 0x5 – REND CMD 2.8.1 FIFO Read Figure 8: ZG2100M/ZG2101M FIFO Read Timing DS70624A – page 14 © 2010 Microchip Technology ZG2100M/ZG2101M 2.8.2 FIFO Write Figure 9: ZG2100M/ZG2101M FIFO Write Timing 2.9 Fully-Integrated Radio ZG2100M/ZG2101M incorporates a fully integrated radio Ideal for 1 & 2 Mbps operation with optional support for external PA operation. The direct conversion TX design incorporates an integrated PA, with up to +10dBm typical at antenna, and fully integrated internal power control loop. The direct conversion RX chain utilizes Automatic Gain Control that allows ZG2100M/ZG2101M to receive with a minimum input Level sensitivity (1Mbps @