ZL30102QDG1

ZL30102 T1/E1 Stratum 4/4E Redundant System Clock Synchronizer for DS1/E1 and H.110 Data Sheet Features April 2010 • Synchronizes to clock-and-sync-pair to maintain minimal phase skew between an H.110 primary master clock and a secondary master clock • Supports Telcordia GR-1244-CORE Stratum 4 and 4E • Supports ITU-T G.823 and G.824 for 2048 kbit/s and 1544 kbit/s interfaces • • Supports ANSI T1.403 and ETSI ETS 300 011 for ISDN primary rate interfaces Provides Lock, Holdover and selectable Out of Range indication • Attenuates wander from 1.8 Hz • Simple hardware control interface • • Manual and Automatic hitless reference switching between any combination of valid input reference frequencies Less than 0.6 nspp intrinsic jitter on all output clocks • External master clock source: Clock Oscillator or Crystal Accepts three input references and synchronizes to any combination of 8 kHz, 1.544 MHz, 2.048 MHz, 8.192 MHz or 16.384 MHz inputs Applications • • Provides a range of clock outputs: 1.544 MHz, 2.048 MHz, 3.088 MHz, 6.312 MHz, 16.384 MHz and either 4.096 MHz and 8.192 MHz or 32.768 MHz and 65.536 MHz • Provides 5 styles of 8 kHz framing pulses • Holdover frequency accuracy of 1x10-7 OSCi OSCo Ordering Information ZL30102QDG1 64 pin TQFP* Trays, Bake & Drypack *Pb Free Matte Tin -40°C to +85°C TIE_CLR • Synchronization and timing control for multi-trunk DS1/ E1 terminal systems such as DSLAMs, Gateways and PBXs • Clock and frame pulse source for H.110 CT Bus, ST-BUS, GCI and other time division multiplex (TDM) buses FASTLOCK LOCK OUT_SEL Master Clock REF0 REF1 TIE Corrector Circuit MUX REF2 C2o C4/C65o C8/C32o C16o F4/F65o F8/F32o Virtual Reference DPLL E1 Synthesizer REF2_SYNC REF_FAIL0 REF_FAIL1 REF_FAIL2 OOR_SEL Mode Control TIE Corrector Enable Reference Monitor REF_SEL1:0 DS1 Synthesizer F16o C1.5o C3o DS2 Synthesizer C6o Frequency Select MUX State Machine RST IEEE 1149.1a MODE_SEL1:0 SEC_MSTR HMS TCK TDI HOLDOVER TMS TDO Figure 1 - Functional Block Diagram 1 Zarlink Semiconductor Inc. Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright 2004-2010, Zarlink Semiconductor Inc. All Rights Reserved. TRST ZL30102 Data Sheet Description The ZL30102 DS1/E1 Synchronizer contains a digital phase-locked loop (DPLL), which provides timing and synchronization for DS1/E1 transmission equipment deploying redundant network clocks. The ZL30102 generates ST-BUS and other TDM clock and framing signals that are phase locked to one of three network references or to another system master-clock reference. It helps ensure system reliability by monitoring its references for frequency accuracy and stability and by maintaining a tight phase alignment between the primary master-clock and secondary master clock outputs even in the presence of high network jitter. The ZL30102 is intended to be the central timing and synchronization resource for network equipment that complies with Telcordia, ETSI, ITU-T and ANSI network specifications. 2 Zarlink Semiconductor Inc. ZL30102 Data Sheet Table of Contents 1.0 Change Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.0 Physical Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.1 Pin Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.2 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3.0 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.1 Reference Select Multiplexer (MUX) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.2 Reference Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.3 Time Interval Error (TIE) Corrector Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.4 Digital Phase Lock Loop (DPLL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.5 Frequency Synthesizers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.6 State Machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.7 Master Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.0 Control and Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.1 Out of Range Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.2 Loop Filter and Limiter Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.3 Output Clock and Frame Pulse Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.4 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.4.1 Freerun Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.4.2 Holdover Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.4.3 Normal Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4.4.4 Automatic Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 4.5 Reference Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 4.5.1 Manual Reference Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 4.5.2 Automatic Reference Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 4.5.2.1 Automatic Reference Switching - Coarse Reference Failure . . . . . . . . . . . . . . . . . . . . . . . . . 24 4.5.2.2 Automatic Reference Switching - Reference Frequency Out-of-Range . . . . . . . . . . . . . . . . . 25 4.6 Clock Redundancy Support. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 5.0 Measures of Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 5.1 Jitter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 5.2 Jitter Generation (Intrinsic Jitter) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 5.3 Jitter Tolerance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 5.4 Jitter Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 5.5 Frequency Accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 5.6 Holdover Accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 5.7 Pull-in Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 5.8 Lock Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 5.9 Phase Slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 5.10 Time Interval Error (TIE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 5.11 Maximum Time Interval Error (MTIE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 5.12 Phase Continuity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 5.13 Lock Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 6.0 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 6.1 Power Supply Decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 6.2 Master Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 6.2.1 Clock Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 6.2.2 Crystal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 6.3 Power Up Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 6.4 Reset Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 6.5 Clock Redundancy System Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 7.0 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 7.1 AC and DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 3 Zarlink Semiconductor Inc. ZL30102 Data Sheet Table of Contents 7.2 Performance Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 4 Zarlink Semiconductor Inc. ZL30102 Data Sheet List of Figures Figure 1 - Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Figure 2 - Pin Connections (64 pin TQFP, please see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Figure 3 - Reference Monitor Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Figure 4 - Behaviour of the Dis/Re-qualify Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Figure 5 - DS1 Out-of-Range Thresholds for OOR_SEL=0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Figure 6 - E1 Out-of-Range Thresholds for OOR_SEL=1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Figure 7 - REF2_SYNC Reference Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Figure 8 - Timing Diagram of Hitless Reference Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Figure 9 - Timing Diagram of Hitless Mode Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Figure 10 - DPLL Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Figure 11 - Mode Switching in Normal Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Figure 12 - Reference Switching in Normal Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Figure 13 - Reference Selection in Automatic Mode (MODE_SEL=11). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Figure 14 - Mode Switching in Automatic Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Figure 15 - Automatic Reference Switching - Coarse Reference Failure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Figure 16 - Automatic Reference Switching - Out-of-Range Reference Failure . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Figure 17 - Examples of REF2 & REF2_SYNC to Output Alignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Figure 18 - Clock Redundancy with Two Independent Timing Cards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Figure 19 - Clock Oscillator Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Figure 20 - Crystal Oscillator Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Figure 21 - Power-Up Reset Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Figure 22 - Typical Clocking Architecture of an ECTF H.110 System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Figure 23 - Timing Parameter Measurement Voltage Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Figure 24 - REF0/1/2 Input Timing and Input to Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Figure 25 - REF2_SYNC Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Figure 26 - E1 Output Timing Referenced to F8/F32o. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Figure 27 - DS1 Output Timing Referenced to F8/F32o . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Figure 28 - DS2 Output Timing Referenced to F8/F32o . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 5 Zarlink Semiconductor Inc. ZL30102 1.0 Data Sheet Change Summary Changes from November 2005 Issue to April 2010Issue. Page, section, figure and table numbers refer to this current issue. Page Item Change 1 Ordering Information Box Leaded part number ZL30102QDG has been obsoleted and replaced by ZL30102QDG1. Changes from July 2005 Issue to November 2005 Issue. Page, section, figure and table numbers refer to this current issue. Page Item Change 1 Features Changed description for hitless reference switching. 32 Section 6.1 Removed power supply decoupling circuit and included reference to synchronizer power supply decoupling application note. Changes from October 2004 Issue to July 2005 Issue. Page, section, figure and table numbers refer to this current issue. Page Item Change 9 RST pin Specified clock and frame pulse outputs forced to high impedance 36 Table “DC Electrical Characteristics*“ Corrected Schmitt trigger levels 44 Table “Performance Characteristics* Functional“ Gave more detail on fast-lock Lock Time conditions Changes from July 2004 Issue to October 2004 Issue. Page, section, figure and table numbers refer to this current issue. Page Item Change 7 Figure 2 Added note specifying not e-Pad 17 Section 3.3 Changed 20 ns to 200 ns in "HMS=0" section 36 Table “DC Electrical Characteristics*“ Corrected current consumption Corrected Vt- input voltage characteristic 39 Table “AC Electrical Characteristics* Input to output timing for REF0, REF1 and REF2 references when TIE_CLR = 0 (see Figure 24).“ Corrected Min. Max. values 40 Section 7.1 Corrected pulse widths 45 Section 7.2 Corrected jitter numbers 6 Zarlink Semiconductor Inc. ZL30102 Physical Description 2.1 Pin Connections F8/F32o C16o C2o AVDD AVDD C8/C32o C4/C65o AGND AGND NC NC AVDD AVDD AVCORE AGND AGND 2.0 Data Sheet F4/F65o F16o AGND IC REF_SEL0 REF_SEL1 REF0 REF1 REF2 REF2_SYNC SEC_MSTR OOR_SEL VDD NC TIE_CLR FASTLOCK 48 46 44 42 40 38 36 34 32 50 30 52 28 54 26 56 ZL30102 24 58 22 60 20 62 18 64 4 6 8 10 12 14 16 GND VCORE LOCK HOLDOVER REF_FAIL0 REF_FAIL1 REF_FAIL2 TDO TMS TRST TCK VCORE GND AVCORE TDI HMS 2 C1.5o C3o C6o AVDD IC IC OUT_SEL VDD NC GND IC OSCi OSCo RST MODE_SEL1 MODE_SEL0 Figure 2 - Pin Connections (64 pin TQFP, please see Note 1) Note 1: The ZL30102 uses the TQFP shown in the package outline designated with the suffix QD, the ZL30102 does not use the e-Pad TQFP. 7 Zarlink Semiconductor Inc. ZL30102 2.2 Data Sheet Pin Description Pin # Name Description 1 GND 2 VCORE Positive Supply Voltage. +1.8 VDC nominal 3 LOCK Lock Indicator (Output). This output goes to a logic high when the PLL is frequency locked to the selected input reference. 4 HOLDOVER Holdover (Output). This output goes to a logic high whenever the PLL goes into holdover mode. 5 REF_FAIL0 Reference 0 Failure Indicator (Output). A logic high at this pin indicates that the REF0 reference frequency has exceeded the out-of-range limit set by the OOR_SEL pin or that it is exhibiting abrupt phase or frequency changes. 6 REF_FAIL1 Reference 1 Failure Indicator (Output). A logic high at this pin indicates that the REF1 reference frequency has exceeded the out-of-range limit set by the OOR_SEL pin or that it is exhibiting abrupt phase or frequency changes. 7 REF_FAIL2 Reference 2 Failure Indicator (Output). A logic high at this pin indicates that the REF2 reference frequency has exceeded the out-of-range limit set by the OOR_SEL pin or that it is exhibiting abrupt phase or frequency changes. 8 TDO Test Serial Data Out (Output). JTAG serial data is output on this pin on the falling edge of TCK. This pin is held in high impedance state when JTAG scan is not enabled. 9 TMS Test Mode Select (Input). JTAG signal that controls the state transitions of the TAP controller. This pin is internally pulled up to VDD. If this pin is not used then it should be left unconnected. 10 TRST Test Reset (Input). Asynchronously initializes the JTAG TAP controller by putting it in the Test-Logic-Reset state. This pin should be pulsed low on power-up to ensure that the device is in the normal functional state. This pin is internally pulled up to VDD. If this pin is not used then it should be connected to GND. 11 TCK Test Clock (Input): Provides the clock to the JTAG test logic. If this pin is not used then it should be pulled down to GND. 12 VCORE 13 GND 14 AVCORE 15 TDI 16 HMS Ground. 0 V Positive Supply Voltage. +1.8 VDC nominal Ground. 0 V Positive Analog Supply Voltage. +1.8 VDC nominal Test Serial Data In (Input). JTAG serial test instructions and data are shifted in on this pin. This pin is internally pulled up to VDD. If this pin is not used then it should be left unconnected. Hitless Mode Switching (Input). The HMS input controls phase accumulation during the transition from Holdover or Freerun mode to Normal mode on the same reference. A logic low at this pin will cause the ZL30102 to maintain the delay stored in the TIE corrector circuit when it transitions from Holdover or Freerun mode to Normal mode. A logic high on this pin will cause the ZL30102 to measure a new delay for its TIE corrector circuit thereby minimizing the output phase movement when it transitions from Holdover or Freerun mode to Normal mode. 17 MODE_SEL0 Mode Select 0 (Input). This input combined with MODE_SEL1 determines the mode of operation, see Table 4 on page 20. 18 MODE_SEL1 Mode Select 1 (Input). See MODE_SEL0 pin description. 8 Zarlink Semiconductor Inc. ZL30102 Data Sheet Pin # Name Description 19 RST Reset (Input). A logic low at this input resets the device. On power up, the RST pin must be held low for a minimum of 300 ns after the power supply pins have reached the minimum supply voltage. When the RST pin goes high, the device will transition into a Reset state for 3 ms. In the Reset state all clock and frame pulse outputs will be forced into high impedance. 20 OSCo Oscillator Master Clock (Output). For crystal operation, a 20 MHz crystal is connected from this pin to OSCi. This output is not suitable for driving other devices. For clock oscillator operation, this pin must be left unconnected. 21 OSCi Oscillator Master Clock (Input). For crystal operation, a 20 MHz crystal is connected from this pin to OSCo. For clock oscillator operation, this pin must be connected to a clock source. 22 IC 23 GND 24 NC No internal bonding Connection. Leave unconnected. 25 VDD Positive Supply Voltage. +3.3 VDC nominal 26 OUT_SEL 27 IC Internal Connection. Connect this pin to ground. 28 IC Internal Connection. Connect this pin to ground. 29 AVDD Positive Analog Supply Voltage. +3.3 VDC nominal 30 C6o Clock 6.312 MHz (Output). This output is used in DS2 applications. 31 C3o Clock 3.088 MHz (Output). This output is used in DS1 applications. 32 C1.5o Clock 1.544 MHz (Output). This output is used in DS1 applications. Internal Connection. Leave unconnected. Ground. 0 V Output Selection (Input). This input selects the signals on the combined output clock and frame pulse pins, see Table 3 on page 19. This clock output pad includes a Schmitt input which serves as a PLL feedback path; proper transmission-line termination should be applied to maintain reflections below Schmitt trigger levels. 33 AGND Analog Ground. 0 V 34 AGND Analog Ground. 0 V 35 AVCORE Positive Analog Supply Voltage. +1.8 VDC nominal 36 AVDD Positive Analog Supply Voltage. +3.3 VDC nominal 37 AVDD Positive Analog Supply Voltage. +3.3 VDC nominal 38 NC No internal bonding Connection. Leave unconnected. 39 NC No internal bonding Connection. Leave unconnected. 40 AGND Analog Ground. 0 V 41 AGND Analog Ground. 0 V 42 C4/C65o Clock 4.096 MHz or 65.536 MHz (Output). This output is used for ST-BUS operation at 2.048 Mbit/s, 4.096 Mbit/s or 65.536 MHz (ST-BUS 65.536 Mbit/s). The output frequency is selected via the OUT_SEL pin, see Table 3 on page 19. 9 Zarlink Semiconductor Inc. ZL30102 Data Sheet Pin # Name Description 43 C8/C32o Clock 8.192 MHz or 32.768 MHz (Output). This output is used for ST-BUS and GCI operation at 8.192 Mb/s or for operation with a 32.768 MHz clock. The output frequency is selected via the OUT_SEL pin, see Table 3 on page 19. In C8 mode, this clock output pad uses an included Schmitt input as a PLL feedback path; proper transmission-line termination should be applied to maintain reflections below Schmitt trigger levels. 44 AVDD Positive Analog Supply Voltage. +3.3 VDC nominal 45 AVDD Positive Analog Supply Voltage. +3.3 VDC nominal 46 C2o Clock 2.048 MHz (Output). This output is used for standard E1 interface timing and for ST-BUS operation at 2.048 Mbit/s. This clock output pad includes a Schmitt input which serves as a PLL feedback path; proper transmission-line termination should be applied to maintain reflections below Schmitt trigger levels. 47 C16o Clock 16.384 MHz (Output). This output is used for ST-BUS operation with a 16.384 MHz clock. This clock output pad includes a Schmitt input which serves as a PLL feedback path; proper transmission-line termination should be applied to maintain reflections below Schmitt trigger levels. 48 F8/F32o Frame Pulse (Output). This is an 8 kHz 122 ns active high framing pulse or it is an 8 kHz 31 ns active high framing pulse, which marks the beginning of a frame. The pulse width is selected via the OUT_SEL pin, see Table 3 on page 19. 49 F4/F65o Frame Pulse ST-BUS 2.048 Mbit/s or ST-BUS at 65.536 MHz clock (Output). This output is an 8 kHz 244 ns active low framing pulse which marks the beginning of an STBUS frame. This is typically used for ST-BUS operation at 2.048 Mbit/s and 4.096 Mbit/s. Or this output is an 8 kHz 15 ns active low framing pulse, typically used for ST-BUS operation with a clock rate of 65.536 MHz. The pulse width is selected via the OUT_SEL pin, see Table 3 on page 19. 50 F16o Frame Pulse ST-BUS 8.192 Mbit/s (Output). This is an 8 kHz 61 ns active low framing pulse, which marks the beginning of an ST-BUS frame. This is typically used for ST-BUS operation at 8.192 Mbit/s. 51 AGND 52 IC 53 REF_SEL0 Reference Select 0 (Input/Output). In the manual mode of operation, REF_SEL0 is an input. As an input REF_SEL0 combined with REF_SEL1 selects the reference input that is used for synchronization, see Table 6 on page 23. In the Automatic mode of operation, REFSEL0 is an output indicating which of the input references is the being selected. This pin is internally pulled down to GND. 54 REF_SEL1 Reference Select 1 (Input/Output). See REF_SEL0 pin description. 55 REF0 Reference (Input). This is one of three (REF0, REF1 and REF2) input reference sources used for synchronization. One of five possible frequencies may be used: 8 kHz, 1.544 MHz, 2.048 MHz, 8.192 MHz or 16.384 MHz. This pin is internally pulled down to GND. 56 REF1 Reference (Input). See REF0 pin description. 57 REF2 Reference (Input). See REF0 pin description. Analog Ground. 0 V Internal Connection. Connect this pin to ground. 10 Zarlink Semiconductor Inc. ZL30102 Data Sheet Pin # Name Description 58 REF2_SYNC REF2 Synchronization Frame Pulse (Input). This is the 8 kHz frame pulse synchronization input associated with the REF2 reference. While the PLL is locked to the REF2 input reference the output (multi) frame pulses are synchronized to this input. This pin is internally pulled down to GND. 59 SEC_MSTR Secondary Master Mode Selection (Input). A logic low at this pin selects the Primary Master mode of operation with 1.8 Hz DPLL loop filter bandwidth. A logic high selects Secondary Master mode which forces the PLL to clear its TIE corrector circuit and lock to the selected reference using a high bandwidth loop filter and a phase slope limiting of 9.5 ms/s. 60 OOR_SEL Out Of Range Selection (Input). This input selects the frequency out of range limits of the reference inputs, see Table 1 on page 19. 61 VDD Positive Supply Voltage. +3.3 VDC nominal 62 NC No internal bonding Connection. Leave unconnected. 63 TIE_CLR 64 FASTLOCK 3.0 TIE Circuit Reset (Input). A logic low at this input resets the Time Interval Error (TIE) correction circuit resulting in a realignment of input phase with output phase. Fast Lock (Input). Set temporarily high to allow the ZL30102 to quickly lock to the input reference (one second locking time). Functional Description The ZL30102 is an SDH/PDH Synchronizer for Redundant System Clocks, providing timing and synchronization signals to interface circuits for the following types of primary rate digital transmission links, see Table 1: • DS1 compliant with ANSI T1.403 and Telcordia GR-1244-CORE Stratum 4/4E • E1 compliant with ITU-T G.703 and ETSI ETS 300 011 Figure 1 is a functional block diagram of the ZL30102 which is described in the following sections. 3.1 Reference Select Multiplexer (MUX) The ZL30102 accepts three simultaneous reference input signals and operates on their rising edges. One of them, the primary reference (REF0), the secondary reference (REF1) or the tertiary reference (REF2) signal is selected as input to the TIE Corrector Circuit based on the Reference Selection (REF_SEL1:0) inputs. The use of the combined REF2 and REF2_SYNC inputs allows for a very accurate phase alignment of the output frame pulses to the 8 kHz frame pulse supplied to the REF2_SYNC input. This feature supports the implementation of Primary and Secondary Master system clocks in H.110 systems. 3.2 Reference Monitor The input references are monitored by three independent reference monitor blocks, one for each reference. The block diagram of a single reference monitor is shown in Figure 3. For each reference clock, the frequency is detected and the clock is continuously monitored for three independent criteria that indicate abnormal behavior of the reference signal, for example; long term drift from its nominal frequency or excessive jitter. To ensure proper operation of the reference monitor circuit, the minimum input pulse width restriction of 15 nsec must be observed. 11 Zarlink Semiconductor Inc. ZL30102 Data Sheet • Reference Frequency Detector (RFD): This detector determines whether the frequency of the reference clock is 8 kHz, 1.544 MHz, 2.048 MHz 8.192 MHz or 16.384 MHz and provides this information to the various monitor circuits and the phase detector circuit of the DPLL. • Precise Frequency Monitor (PFM): This circuit determines whether the frequency of the reference clock is within the selected accuracy range, see Table 1. • Coarse Frequency Monitor (CFM): This circuit monitors the reference frequency over intervals of approximately 30 μs to quickly detect large frequency changes. • Single Cycle Monitor (SCM): This detector checks the period of a single clock cycle to detect large phase hits or the complete loss of the clock. REF0 / REF1 / REF2 Precise Frequency Monitor OR Coarse Frequency Monitor Single Cycle Monitor REF_FAIL0 / REF_FAIL1 / REF_FAIL2 OR Reference Frequency Detector Reference select state machine REF_SEL1:0 REF_DIS Mode select state machine HOLDOVER REF_OOR dis/re-qualify timer OR REF_OOR = reference out of range. REF_DIS= reference disrupted. Both are internal signals. Figure 3 - Reference Monitor Circuit Exceeding the thresholds of any of the monitors forces the corresponding REF_FAIL pin to go high. The single cycle and coarse frequency failure flags force the DPLL into Holdover mode and feed a timer that disqualifies the reference input signal when the failures are present for more than 2.5 s. The single cycle and coarse frequency failures must be absent for 10 s to let the timer re-qualify the input reference signal as valid. Multiple failures of less than 2.5 s each have an accumulative effect and will disqualify the reference eventually. This is illustrated in Figure 4 where REF0 experiences disruptions while REF1 is stable. 12 Zarlink Semiconductor Inc. ZL30102 Data Sheet SCM or CFM failure SCM or CFM failure REF0 dis/re-qualify timer on REF0 2.5 s 10 s REF_OOR0 (internal signal) REF_FAIL0 HOLDOVER REF_SEL REF0 REF1 REF0 REF1 Figure 4 - Behaviour of the Dis/Re-qualify Timer When the incoming signal returns to normal (REF_FAIL=0), the DPLL returns to Normal mode with the output signal locked to the input signal. Each of the monitors has a built-in hysteresis to prevent flickering of the REF_FAIL status pin at the threshold boundaries. The precise frequency monitor and the timer do not affect the mode (Holdover/Normal) of the DPLL. If the device is set to Automatic mode (MODE_SEL1:0=11), then the state machine does not immediately switch to another reference. If the single cycle and/or coarse frequency failures persist for more than 2.5 s or the precise frequency monitor detects a failure, then the state machine will switch to another valid reference if that is available. If there no other reference available, it stays in Holdover mode. The precise frequency monitor’s failure thresholds are selected with the OOR_SEL input based on the ZL30102 applications, Table 1. Figure 5 and Figure 6 show the out of range limits for various master clock accuracies. It will take the precise frequency monitor up to 10 s to qualify or disqualify the input reference. C20 Clock Accuracy Out of Range C20 0 ppm In Range -83 -64 0 64 83 Out of Range C20 +32 ppm In Range -51 32 -32 96 115 Out of Range C20 -32 ppm In Range -115 -96 -100 -32 -75 -50 -25 32 0 25 51 50 75 100 Frequency offset [ppm] C20: 20 MHz master oscillator clock Figure 5 - DS1 Out-of-Range Thresholds for OOR_SEL=0 13 Zarlink Semiconductor Inc. ZL30102 Data Sheet C20 Clock Accuracy Out of Range C20 0 ppm In Range -130 -100 0 100 130 C20 Out of Range +50 ppm In Range -80 -50 150 180 50 Out of Range C20 -50 ppm In Range -180 -150 -200 C20: 20 MHz master oscillator clock -150 -100 -50 -50 50 0 50 80 100 150 200 Frequency offset [ppm] Figure 6 - E1 Out-of-Range Thresholds for OOR_SEL=1 In addition to the monitoring of the REF2 reference signal the companion REF2_SYNC input signal is also monitored for failure (see Figure 7). Sync Ratio Monitor (SRM): This monitor detects if the REF2_SYNC signal is an 8 kHz signal. It also checks the number of REF2 reference clock cycles in a single REF2_SYNC frame pulse period to determine the integrity of the REF2_SYNC signal, for example there must be exactly 256 clock cycles of a 2.048 MHz REF2 reference clock in a single REF2_SYNC 8 kHz frame pulse period to validate the REF2_SYNC signal. If the REF2 and REF2_SYNC inputs are selected for synchronization and the Sync Ratio Monitor detects a failure, the DPLL will abandon the mechanism of aligning the output frame pulse to the REF2_SYNC pulse. Instead only the REF2 reference will be used for synchronization. REF2_SYNC REF2 REF2 frequency SYNC Reference Monitor Circuit to DPLL Figure 7 - REF2_SYNC Reference Monitor 3.3 Time Interval Error (TIE) Corrector Circuit The TIE Circuit eliminates phase transients on the output clock that may occur during reference switching or the recovery from Holdover mode to Normal mode. On recovery from Holdover mode (dependent on the HMS pin) or when switching to another reference input, the TIE corrector circuit measures the phase delay between the current phase (feedback signal) and the phase of the selected reference signal. This delay value is stored in the TIE corrector circuit. This circuit creates a new virtual reference signal that is at the same phase position as the feedback signal. By using the virtual reference, the PLL minimizes the phase transient it experiences when it recovers from Holdover mode. 14 Zarlink Semiconductor Inc. ZL30102 Data Sheet The delay value can be reset by setting the TIE Corrector Circuit Clear pin (TIE_CLR) low for at least 15 ns. This results in a phase alignment between the input reference signal and the output clocks and frame pulses as shown in Figure 24. The speed of the phase alignment correction is limited by the selected loop filter bandwidth and the phase slope limit (see Table 2). Convergence is always in the direction of least phase travel. TIE_CLR can be kept low continuously; in that case the output clocks will always align with the selected input reference. This is illustrated in Figure 8. TIE_CLR = 1 TIE_CLR = 0 locked to REF0 locked to REF0 REF0 REF0 REF1 REF1 Output Clock Output Clock locked to REF1 locked to REF1 REF0 REF0 REF1 REF1 Output Clock Output Clock Figure 8 - Timing Diagram of Hitless Reference Switching The Hitless Mode Switching (HMS) pin enables phase hitless returns from Freerun and Holdover modes to Normal mode in a single reference operation. A logic low at the HMS input disables the TIE circuit updating the delay value thereby forcing the output of the PLL to gradually move back to the original point before it went into Holdover mode. (see Figure 9). This prevents accumulation of phase in network elements. A logic high (HMS=1) enables the TIE circuit to update its delay value thereby preventing a large output phase movement after return to Normal mode. This causes accumulation of phase in network elements. In both cases the PLL’s output can be aligned with the input reference by setting TIE_CLR low. Regardless of the HMS pin state, reference switching in the ZL30102 is always hitless unless TIE_CLR is kept low continuously. 15 Zarlink Semiconductor Inc. ZL30102 HMS = 0 Data Sheet HMS = 1 Normal mode Normal mode REF REF Output Clock Output Clock Phase drift in Holdover mode Phase drift in Holdover mode REF REF Output Clock Output Clock Return to Normal mode Return to Normal mode REF REF Output Clock Output Clock TIE_CLR=0 TIE_CLR=0 REF REF Output Clock Output Clock Figure 9 - Timing Diagram of Hitless Mode Switching Examples: HMS=1: When ten Normal to Holdover to Normal mode transitions occur and in each case the Holdover mode was entered for 2 seconds then the accumulated phase change (MTIE) could be as large as 2.13 μs. - Phaseholdover_drift = 0.1 ppm x 2 s = 200 ns - Phasemode_change = 0 ns + 13 ns = 13 ns - Phase10 changes = 10 x (200 ns + 13 ns) = 2.13 μs 16 Zarlink Semiconductor Inc. ZL30102 Data Sheet where: - 0.1 ppm is the accuracy of the Holdover mode - 0 ns is the maximum phase discontinuity in the transition from the Normal mode to the Holdover mode - 13 ns is the maximum phase discontinuity in the transition from the Holdover mode to the Normal mode when a new TIE corrector value is calculated HMS=0: When the same ten Normal to Holdover to Normal mode changes occur and in each case Holdover mode was entered for 2 seconds, then the overall MTIE would be 200 ns. As the delay value for the TIE corrector circuit is not updated, there is no 13 ns measurement error at this point. The phase can still drift for 200 ns when the PLL is in Holdover mode but when the PLL enters Normal mode again, the phase moves back to the original point so the phase is not accumulated. 3.4 Digital Phase Lock Loop (DPLL) The DPLL of the ZL30102 consists of a phase detector, a limiter, a loop filter and a digitally controlled oscillator as shown in Figure 10. The data path from the phase detector to the limiter is tapped and routed to the lock detector that provides a lock indication which is output at the LOCK pin. Lock detector Virtual Reference from TIE Corrector Circuit Phase Detector Limiter Loop Filter Digitally Controlled Oscillator LOCK DPLL Reference to Frequency Synthesizer REF2_SYNC frame pulse State Select from Control State Machine Feedback signal from Frequency Select MUX feedback frame pulse F8o Figure 10 - DPLL Block Diagram Phase Detector - the phase detector compares the virtual reference signal from the TIE corrector circuit with the feedback signal and provides an error signal corresponding to the phase difference between the two. This error signal is passed to the limiter circuit. Limiter - the limiter receives the error signal from the phase detector and ensures that the DPLL responds to all input transient conditions with a maximum output phase slope compliant with the applicable standards. The phase slope limit is dependent on the SEC_MSTR pin and is listed in Table 2. Loop Filter - the loop filter is similar to a first order low pass filter with a bandwidth of 1.8 Hz suitable to provide Primary Master timing. When Secondary Master mode is selected (SEC_MSTR=1), the filter bandwidth is set to 922 Hz. For stability reasons, the loop filter bandwidth for 8 kHz reference inputs is limited to a maximum of 58 Hz. 17 Zarlink Semiconductor Inc. ZL30102 Data Sheet Digitally Controlled Oscillator (DCO) - the DCO receives the limited and filtered signal from the Loop Filter, and based on its value, generates a corresponding digital output signal. The synchronization method of the DCO is dependent on the state of the ZL30102. In Normal Mode, the DCO provides an output signal which is frequency and phase locked to the selected input reference signal. In Holdover Mode, the DCO is free running at a frequency equal to the frequency that the DCO was generating in Normal Mode. The frequency in Holdover mode is calculated from frequency samples stored 26 ms to 52 ms before the ZL30102 entered Holdover mode. This ensures that the coarse frequency monitor and the single cycle monitor have time to disqualify a bad reference before it corrupts the holdover frequency. In Freerun Mode, the DCO is free running with an accuracy equal to the accuracy of the OSCi 20 MHz source. Lock Indicator - the lock detector monitors if the output value of the phase detector is within the phase-lockwindow for a certain time. The selected phase-lock-window guarantees the stable operation of the LOCK pin with maximum network jitter and wander on the reference input. If the DPLL goes into Holdover mode (auto or manual), the LOCK pin will initially stay high for 1 s in Primary Master mode. In Secondary Master mode, LOCK remains high for 0.1 s. If at that point the DPLL is still in holdover mode, the LOCK pin will go low; subsequently the LOCK pin will not return high for at least the full lock-time duration. In Freerun mode the LOCK pin will go low immediately. 3.5 Frequency Synthesizers The output of the DCO is used by the frequency synthesizers to generate the output clocks and frame pulses which are synchronized to one of three reference inputs (REF0, REF1 or REF2). The frequency synthesizer uses digital techniques to generate output clocks and advanced noise shaping techniques to minimize the output jitter. The clock and frame pulse outputs have limited driving capability and should be buffered when driving high capacitance loads. 3.6 State Machine As shown in Figure 1, the state machine controls the TIE Corrector Circuit and the DPLL. The control of the ZL30102 is based on the inputs MODE_SEL1:0, REF_SEL1:0 and HMS. 3.7 Master Clock The ZL30102 can use either a clock or crystal as the master timing source. For recommended master timing circuits, see the Applications - Master Clock section. 18 Zarlink Semiconductor Inc. ZL30102 4.0 Control and Modes of Operation 4.1 Out of Range Selection Data Sheet The out of range limits for the Precise Frequency Monitor in the 3 reference monitor blocks are selected through the OOR_SEL pin, see Table 1. OOR_SEL Application Applicable Standard Out Of Range Limits 0 DS1 ANSI T1.403 Telcordia GR-1244-CORE Stratum 4/4E 64 - 83 ppm 1 E1 ITU-T G.703 ETSI ETS 300 011 100 - 130 ppm Table 1 - Out of Range Limits Selection 4.2 Loop Filter and Limiter Selection The loop filter and limiter settings are selected through the SEC_MSTR pin, see Table 2. The maximum loop filter bandwidth is also dependent on the frequency of the currently selected reference (REF0/1/2). SEC_MSTR Detected REF Frequency Loop Filter Bandwidth Phase Slope Limiting 0 any 1.8 Hz 61 μ/s 8 kHz 58 Hz 9.5 ms /s 1.544 MHz, 2.048 MHz, 8.192 MHz, 16.384 MHz 922 Hz 9.5 ms /s 1 Table 2 - Loop Filter and Limiter Settings 4.3 Output Clock and Frame Pulse Selection The output of the DCO is used by the frequency synthesizers to generate the output clocks and frame pulses which are synchronized to one of three reference inputs (REF0, REF1 or REF2). These signals are available in two groups controlled by the OUT_SEL pin, see Table 3. OUT_SEL Generated Clocks Generated Frame Pulses 0 C2o, C4o, C8o, C16o F4o, F8o, F16o 1 C2o, C16o, C32, C65o F16o, F32o, F65o Table 3 - Clock and Frame Pulse Selection with OUT_SEL Pin 19 Zarlink Semiconductor Inc. ZL30102 4.4 Data Sheet Modes of Operation The ZL30102 has three possible manual modes of operation; Normal, Holdover and Freerun. These modes are selected with mode select pins MODE_SEL1 and MODE_SEL0 as is shown in Table 4. Transitioning from one mode to the other is controlled by an external controller. The ZL30102 can be configured to automatically select a valid input reference under control of its internal state machine by setting MODE_SEL1:0 = 11. In this mode of operation, a state machine controls selection of references (REF0 or REF1) used for synchronization. MODE_SEL1 MODE_SEL0 Mode 0 0 Normal (with automatic Holdover) 0 1 Holdover 1 0 Freerun 1 1 Automatic (Normal with automatic Holdover and automatic reference switching) Table 4 - Operating Modes 4.4.1 Freerun Mode Freerun mode is typically used when an independent clock source is required, or immediately following system power-up before network synchronization is achieved. In Freerun mode, the ZL30102 provides timing and synchronization signals which are based on the master clock frequency (supplied to OSCi pin) only, and are not synchronized to the reference input signals. The accuracy of the output clock is equal to the accuracy of the master clock (OSCi). So if a ±32 ppm output clock is required, the master clock must also be ±32 ppm. See Applications - Section 6.2, “Master Clock“. 4.4.2 Holdover Mode Holdover Mode is typically used for short durations while network synchronization is temporarily disrupted. In Holdover Mode, the ZL30102 provides timing and synchronization signals, which are not locked to an external reference signal, but are based on storage techniques. The storage value is determined while the device is in Normal Mode and locked to an external reference signal. When in Normal Mode, and locked to the input reference signal, a numerical value corresponding to the ZL30102 output reference frequency is stored alternately in two memory locations every 26 ms. When the device is switched into Holdover Mode, the value in memory from between 26 ms and 52 ms is used to set the output frequency of the device. The frequency accuracy of Holdover Mode is 0.1 ppm. Two factors affect the accuracy of Holdover mode. One is drift on the master clock while in Holdover mode, drift on the master clock directly affects the Holdover mode accuracy. Note that the absolute master clock (OSCi) accuracy does not affect Holdover accuracy, only the change in OSCi accuracy while in Holdover. For example, a ±32 ppm master clock may have a temperature coefficient of ±0.1 ppm per °C. So a ±10 °C change in temperature, while the ZL30102 is in Holdover mode may result in an additional offset (over the 0.1 ppm) in frequency accuracy of ±1 ppm. Which is much greater than the 0.1 ppm of the ZL30102. The other factor affecting the accuracy is large jitter on the reference input prior to the mode switch. 20 Zarlink Semiconductor Inc. ZL30102 4.4.3 Data Sheet Normal Mode Normal mode is typically used when a system clock source, synchronized to the network is required. In Normal mode, the ZL30102 provides timing and frame synchronization signals, which are synchronized to one of three reference inputs (REF0, REF1 or REF2). The input reference signal may have a nominal frequency of 8 kHz, 1.544 MHz, 2.048 MHz, 8.192 MHz or 16.384 MHz. The frequency of the reference inputs are automatically detected by the reference monitors. When the ZL30102 comes out of RESET while Normal mode is selected by its MODE_SEL pins then it will initially go into Holdover mode and generate clocks with the accuracy of its freerunning local oscillator (see Figure 11). If the ZL30102 determines that its selected reference is disrupted (see Figure 3), it will remain in Holdover until the selected reference is no longer disrupted or the external controller selects another reference that is not disrupted. If the ZL30102 determines that its selected reference is not disrupted (see Figure 3) then the state machine will cause the DPLL to recover from Holdover via one of two paths depending on the logic level at the HMS pin. If HMS=0 then the ZL30102 will transition directly to Normal mode and it will align its output signals with its selected input reference (see Figure 9). If HMS=1 then the ZL30102 will transition to Normal mode via the TIE correction state and the phase difference between the output signals and the selected input reference will be maintained. When the ZL30102 is operating in Normal mode, if it determines that its selected reference is disrupted (Figure 3) then its state machine will cause it to automatically go to Holdover mode. When the ZL30102 determines that its selected reference is not disrupted then the state machine will cause the DPLL to recover from Holdover via one of two paths depending on the logic level at the HMS pin (see Figure 11). If HMS=0 then the ZL30102 will transition directly to Normal mode and it will align its output signals with its input reference (see Figure 9). If HMS=1 then the ZL30102 will transition to Normal mode via the TIE correction state and the phase difference between the output signals and the input reference will be maintained. If the reference selection changes because the value of the REF_SEL1:0 pins changes or because the reference selection state machine selected a different reference input, the ZL30102 goes into Holdover mode and returns to Normal mode through the TIE correction state regardless of the logic value on HMS pin. ZL30102 provides a fast lock pin (FASTLOCK), which, when set high enables the PLL to lock to an incoming reference within approximately 1 s. Normal (HOLDOVER=0) RST REF_CH=1 REF_DIS=0 and REF_CH=0 and HMS=0 REF_DIS=0 REF_DIS=1 REF_DIS=1 TIE Correction (HOLDOVER=1) Holdover (HOLDOVER=1) (REF_DIS=0 and HMS=1) or REF_CH=1 REF_DIS=1: Current selected reference disrupted (see Figure 3). REF_DIS is an internal signal. REF_CH= 1: Reference change, a transition in the reference selection (see Figure 13) or a change in the REF_SEL pins. REF_CH is an internal signal. Figure 11 - Mode Switching in Normal Mode 21 Zarlink Semiconductor Inc. ZL30102 4.4.4 Data Sheet Automatic Mode The Automatic mode combines the functionality of the Normal mode (automatic Holdover) with automatic reference switching. The automatic reference switching is described in more detail in section 4.5.2, “Automatic Reference Switching“. 4.5 4.5.1 Reference Switching Manual Reference Switching In the manual modes of operation (MODE_SEL1:0 ≠ 11) the active reference input (REF0, REF1 or REF2) is selected by the REF_SEL1 and REF_SEL0 pins as shown in Table 5. When the logic value of the REF_SEL pins is changed when the DPLL is in Normal mode, the ZL30102 will perform a hitless reference switch. REF_SEL1 REF_SEL0 Input Reference Selected 0 0 REF0 0 1 REF1 1 0 REF2 1 1 REF2 Table 5 - Manual Reference Selection When the REF_SEL inputs are used in Normal mode to force a change from the currently selected reference to another reference, the action of the LOCK output will depend on the relative frequency and phase offset of the old and new references. Where the new reference has enough frequency offset and/or TIE-corrected phase offset to force the output outside the phase-lock-window, the LOCK output will de-assert, the lock-qualify timer is reset, and LOCK will stay de-asserted for the full lock-time duration. Where the new reference is close enough in frequency and TIE-corrected phase for the output to stay within the phase-lock-window, the LOCK output will remain asserted through the reference-switch process. REF_SEL REF0 REF1 LOCK Lock Time Note: LOCK pin behaviour depends on phase and frequency offset of REF1. Figure 12 - Reference Switching in Normal Mode 22 Zarlink Semiconductor Inc. ZL30102 4.5.2 Data Sheet Automatic Reference Switching In the automatic mode of operation (MODE_SEL1:0 = 11), the ZL30102 automatically selects a reference input that is not out-of-range (REF_OOR=0, see Figure 3). The state machine can only select REF0 or REF1; REF2 cannot be selected in the Automatic mode (see Figure 13). If the current reference (REF0 or REF1) used for synchronization fails, the state machine will switch to the other reference. If both references fail then the ZL30102 enters the Holdover mode without switching to another reference. When the ZL30102 comes out of reset or when REF2 is the current reference when the ZL30102 is put in the Automatic mode, then REF0 has priority over REF1. Otherwise there is no preference for REF0 or REF1 which is referred to as non-revertive reference selection. RST && REF_OOR0=0 RST && REF_OOR0=1 && REF_OOR1=0 REF_OOR0=0 && REF_OOR1=1 REF0 Reference REF1 Reference REF_OOR0=1 && REF_OOR1=0 REF_OOR0=0 REF_OOR0=1 && REF_OOR1=0 REF2 Reference REF_OOR = reference out of range, see Figure 3. This is an internal signal. Figure 13 - Reference Selection in Automatic Mode (MODE_SEL=11) In the automatic mode of operation, both pins REF_SEL1 and REF_SEL0 are configured as outputs. The logic level on the REF_SEL0 output indicates the current input reference being selected for synchronization (see Table 6). REF_SEL1 (output pin) REF_SEL0 (output pin) Input Reference 0 0 REF0 0 1 REF1 Table 6 - The Reference Selection Pins in the Automatic Mode (MODE_SEL=11) 23 Zarlink Semiconductor Inc. ZL30102 Data Sheet The mode selection state machine behaves differently in Automatic mode in that when both reference REF0 and reference REF1 are out of range (REF_OOR=1), the state machine will select the Holdover state. In Normal mode the reference out of range (REF_OOR) status is ignored by the state machine. This is illustrated in Figure 14. Normal (HOLDOVER=0) REF_CH=1 REF_DIS=0 and REF_OOR=0 and REF_CH=0 and HMS=0 REF_DIS=0 and REF_OOR=0 RST REF_DIS=1 or REF_OOR=1 TIE Correction (HOLDOVER=1) Holdover (HOLDOVER=1) (REF_DIS=0 and REF_OOR=0 and HMS=1) or REF_CH=1 REF_DIS=1: Current selected reference disrupted (see Figure 3). REF_DIS is an internal signal. REF_OOR=1: Current selected reference out of range (see Figure 3). REF_OOR is an internal signal. REF_CH= 1: Reference change, a transition in the reference selection (see Figure 13). REF_CH is an internal signal. Figure 14 - Mode Switching in Automatic Mode 4.5.2.1 Automatic Reference Switching - Coarse Reference Failure When the currently-active input reference in Automatic mode fails in a coarse manner, the REF_DIS internal signal places the device in holdover, with the HOLDOVER pin and the REF_FAIL pin asserted. This can occur through triggering the Single Cycle Monitor, or the Coarse Frequency Monitor, in the Reference Monitor block. If the reference does not correct itself within the lock-disqualify duration (1 second) the LOCK pin is de-asserted. If the reference does not correct itself within the reference-disqualify duration (2.5 seconds) the HOLDOVER pin is deasserted and the REF_SEL outputs indicate that the device has switched to the other reference. The LOCK pin remains de-asserted for the full lock-time duration, regardless of the phase and frequency offset of the old and new references. Figure 15 illustrates this process. If the reference corrects itself within the lock-disqualify duration (< 1 second) the HOLDOVER pin is de-asserted, and the REF_FAIL pin is de-asserted. The LOCK pin remains asserted. No reference switching takes place, and the REF_SEL outputs indicate that the device has remained locked to the old reference. If the reference does not correct itself within the lock-disqualify duration (1 second), but does correct itself within the reference-disqualify duration (< 2.5 seconds) the HOLDOVER pin is de-asserted, the REF_FAIL pin is de-asserted, and the REF_SEL outputs indicate that the device has remained locked to the old reference. However the LOCK pin is de-asserted, the lock-qualify timer is reset, and the LOCK pin remains de-asserted for the full lock-time duration. See 7.2, “Performance Characteristics“ on page 44 for lock-time duration. 24 Zarlink Semiconductor Inc. ZL30102 Data Sheet SCM or CFM failure REF0 REF_DIS0 (internal signal) 2.5 s 10 s REF_OOR0 (internal signal) REF_FAIL0 HOLDOVER REF_SEL REF0 REF1 LOCK Lock Time 1s Note: this scenario is based on REF1 remaining good throughout the duration. Figure 15 - Automatic Reference Switching - Coarse Reference Failure 4.5.2.2 Automatic Reference Switching - Reference Frequency Out-of-Range When the currently-active input reference in Automatic mode fails through a subtle frequency offset, the REF_FAIL output is asserted as soon as the Precise Frequency Monitor indicates an out-of-range reference (10 to 20 seconds). The HOLDOVER output is briefly asserted (approximately three reference input cycles) and the REF_SEL outputs indicate that the device has switched to the other reference. Where the new reference is close enough in frequency and TIE-corrected phase for the output to stay within the phase-lock-window, the LOCK output will remain asserted through the reference-switch process. Where the new reference has enough frequency offset and/or TIE-corrected phase offset to force the output outside the phase-lock-window, the LOCK output will deassert, the lock-qualify timer is reset, and LOCK will stay de-asserted for the full lock-time duration. Figure 16 illustrates this process. 25 Zarlink Semiconductor Inc. ZL30102 Data Sheet Frequency Precision failure REF0 10 to 20 s REF_OOR0 (internal signal) REF_FAIL0 HOLDOVER REF_SEL REF0 REF1 LOCK Lock Time Note: This scenario is based on REF1 remaining good throughout the duration. LOCK pin behaviour depends on phase and frequency offset of REF1. Figure 16 - Automatic Reference Switching - Out-of-Range Reference Failure 4.6 Clock Redundancy Support In general, clock redundancy implies that the redundant timing card DPLL tracks the output clock and/or frame pulse of the active timing card DPLL. In case that the active timing card fails, the devices that use the active clock and/or frame pulse must be able to switch to the redundant clock and/or frame pulse without experiencing disruptions. Therefore the redundant signals must closely track the active signals. The ZL30102 supports this kind of clock redundancy in various ways; • Lock only to the active clock. The ZL30102 uses the 922 Hz loop filter bandwidth to closely track the active clock, even in the presence of jitter on the active clock. However the active and redundant frame pulse may not be aligned. • Lock to the active frame pulse. Both the redundant clock and frame pulse will be aligned with the active clock and frame pulse. However the ZL30102 loop filter bandwidth is limited to 58 Hz for an 8 kHz frame pulse. Therefore the redundant clock and frame pulse will not track the active frame pulse as closely in the presence of jitter on the active frame pulse as with a 922 Hz loop filter bandwidth. • Lock to both the active clock and associated frame pulse. The ZL30102 uses the 922 Hz loop filter bandwidth and thereby track the active clock and frame pulse in the presence of jitter on the active signals. It will also align the redundant frame pulse with the active frame pulse. 26 Zarlink Semiconductor Inc. ZL30102 Data Sheet The method of clock redundancy shown in Figure 18 is that the redundant timing card is frequency and phase locked to the active clock and frame pulse. The redundant card is configured as Secondary Master (SEC_MSTR=1) and continuously adjusts the phase of its output clocks and frame pulses to match that of the active clock and frame pulse. In this mode of operation, the bandwidth of the redundant timing card’s DPLL is much larger than that of the active timing card’s DPLL, 922 Hz versus 1.8 Hz. Therefore the redundant clocks and frame pulses will track the active clock and frame pulse closely even in the presence of the maximum tolerable input jitter and wander on the active timing card’s reference input. The method of synchronization using REF2 and REF2_SYNC is enabled as soon as a valid 8 kHz frame pulse is detected on the REF2_SYNC input. The REF2_SYNC pulse must be generated from the clock that is present on the REF2 input. The ZL30102 checks the number of REF2 cycles in the REF2_SYNC period. If this is not the nominal number of cycles, the REF2_SYNC pulse is considered invalid. For example, if REF2 is a 8.192 MHz clock and REF2_SYNC is a 8 kHz frame pulse, then there must be exactly 1024 REF2 cycles in a REF2_SYNC period. If a valid REF2_SYNC pulse is detected, the ZL30102 will align the rising edges of the REF2 clock and the corresponding output clock such that the rising edge of the F8o/F32o output frame pulse is aligned with the frame boundary indicated by the REF2_SYNC signal. The rising edges of the REF2 and the corresponding output clock that are aligned, are the ones that lag the rising edges of the REF2_SYNC and the F8o pulses respectively. This is illustrated in Figure 17. Many combinations of the ZL30102 clock and frame pulse outputs can be used as REF2 and REF2_SYNC inputs. In general, the active low frame pulses F4o, F16o and F65o would be inverted first before used as a REF2_SYNC input. REF2_SYNC = 8 kHz REF2 = C8o aligned F8o C8o Figure 17 - Examples of REF2 & REF2_SYNC to Output Alignment 27 Zarlink Semiconductor Inc. ZL30102 Data Sheet Active Timing Card MODE_SEL1:0=11 SEC_MSTR=0 BITS 0 clock BITS 1 clock OSC REF0 Output Clocks REF1 ZL30102 REF2 REF2_SYNC Redundant Frame Sync (optional) Redundant Clock Active Clock Active Frame Sync (optional) REF2_SYNC REF2 BITS 0 clock BITS 1 clock ZL30102 REF0 Output Clocks REF1 MODE_SEL1:0=00 REF_SEL1:0=10 SEC_MSTR=1 OSC Redundant Timing Card Figure 18 - Clock Redundancy with Two Independent Timing Cards The following is an example of how active/redundant setup can be configured. The active timing card is set based on the desired application and is set to: • Primary master mode, SEC_MSTR=0 • Normal Mode, MODE_SEL1:0=00 (forces device to the input reference set at REF_SEL) • Automatic mode, MODE_SEL1:0=11 (allows device to auto-switch if reference fails) The HOLDOVER and REF_FAIL pins help evaluate quality of clocks and quality of redundant clock. The redundant timing card is set based on desired applications and is set to: • Normal (manual) mode, MODE_SEL1:0=00 • REF2 and REF2_SYNC as the input reference, REF_SEL1=1 (forces redundant device to lock to output of active card) • Secondary master mode, SEC_MSTR=1 The HOLDOVER and REF_FAIL pins help evaluate quality of clocks and quality of redundant clock. 28 Zarlink Semiconductor Inc. ZL30102 Data Sheet When the redundant timing card is switched to becoming the active timing card, the system controller should do the following: • select Primary Master mode, SEC_MSTR=0 • select Automatic mode, MODE_SEL1:0=11 The new active timing card will automatically select a valid input reference REF0 or REF1. If both input references are available and valid, then REF0 will be chosen over REF1. If the new active timing card should use the same input reference (REF0 or REF1) as the old active timing card used before it failed, The system controller should do the following instead: • select Holdover (manual) mode, MODE_SEL1:0=01 • select Primary Master mode, SEC_MSTR=0 • select the required reference (REF0 or REF1) as the input reference • Normal Mode, MODE_SEL1:0=00 (forces device to the input reference set at REF_SEL) • select Automatic mode, MODE_SEL1:0=11 It is recommended to maintain HMS=1 when switching from redundant to active through the Holdover mode, to eliminate output phase transients. When the active timing card is switched to becoming the redundant timing card, the system controller should do the following: • select Normal (manual) mode, MODE_SEL1:0=00 • select Secondary Master mode, SEC_MSTR=1 • select REF2 and REF2_SYNC as the input reference, REF_SEL1=1 The ZL30102 allows for the switch from Secondary Master mode to Primary Master mode with no frequency or phase hits on the output clocks. The switch from Primary Master mode to Secondary Master mode may introduce a phase transient on the output clocks as the TIE correction circuit is disabled to allow the Secondary master device to track the active clocks closely. 29 Zarlink Semiconductor Inc. ZL30102 5.0 Data Sheet Measures of Performance The following are some PLL performance indicators and their corresponding definitions. 5.1 Jitter Timing jitter is defined as the high frequency variation of the clock edges from their ideal positions in time. Wander is defined as the low-frequency variation of the clock edges from their ideal positions in time. High and low frequency variation imply phase oscillation frequencies relative to some demarcation frequency. (Often 10 Hz or 20 Hz for DS1 or E1, higher for SONET/SDH clocks.) Jitter parameters given in this data sheet are total timing jitter numbers, not cycle-to-cycle jitter. 5.2 Jitter Generation (Intrinsic Jitter) Jitter generation is the measure of the jitter produced by the PLL and is measured at its output. It is measured by applying a reference signal with no jitter to the input of the device, and measuring its output jitter. Jitter generation may also be measured when the device is in a non-synchronizing mode, such as free running or holdover, by measuring the output jitter of the device. Jitter is usually measured with various bandlimiting filters depending on the applicable standards. 5.3 Jitter Tolerance Jitter tolerance is a measure of the ability of a PLL to operate properly (i.e., remain in lock and or regain lock in the presence of large jitter magnitudes at various jitter frequencies) when jitter is applied to its reference. The applied jitter magnitude and jitter frequency depends on the applicable standards. 5.4 Jitter Transfer Jitter transfer or jitter attenuation refers to the magnitude of jitter at the output of a device for a given amount of jitter at the input of the device. Input jitter is applied at various amplitudes and frequencies, and output jitter is measured with various filters depending on the applicable standards. For the Zarlink digital PLLs two internal elements determine the jitter attenuation; the internal low pass loop filter and the phase slope limiter. The phase slope limiter limits the output phase slope to, for example, 61 μs/s. Therefore, if the input signal exceeds this rate, such as for very large amplitude low frequency input jitter, the maximum output phase slope will be limited (i.e., attenuated). Since intrinsic jitter is always present, jitter attenuation will appear to be lower for small input jitter signals than for large ones. Consequently, accurate jitter transfer function measurements are usually made with large input jitter signals (for example 75% of the specified maximum tolerable input jitter). 5.5 Frequency Accuracy The Frequency accuracy is defined as the absolute accuracy of an output clock signal when it is not locked to an external reference, but is operating in a free running mode. 5.6 Holdover Accuracy Holdover accuracy is defined as the absolute accuracy of an output clock signal, when it is not locked to an external reference signal, but is operating using storage techniques. For the ZL30102, the storage value is determined while the device is in Normal Mode and locked to an external reference signal. 30 Zarlink Semiconductor Inc. ZL30102 5.7 Data Sheet Pull-in Range Also referred to as capture range. This is the input frequency range over which the PLL must be able to pull into synchronization. 5.8 Lock Range This is the input frequency range over which the synchronizer must be able to maintain synchronization. 5.9 Phase Slope Phase slope is measured in seconds per second and is the rate at which a given signal changes phase with respect to an ideal signal. The given signal is typically the output signal. The ideal signal is of constant frequency and is nominally equal to the value of the final output signal or final input signal. Another way of specifying the phase slope is as the fractional change per time unit. For example; a phase slope of 61 μs/s can also be specified as 61 ppm. 5.10 Time Interval Error (TIE) TIE is the time delay between a given timing signal and an ideal timing signal. 5.11 Maximum Time Interval Error (MTIE) MTIE is the maximum peak to peak delay between a given timing signal and an ideal timing signal within a particular observation period. 5.12 Phase Continuity Phase continuity is the phase difference between a given timing signal and an ideal timing signal at the end of a particular observation period. Usually, the given timing signal and the ideal timing signal are of the same frequency. Phase continuity applies to the output of the PLL after a signal disturbance due to a reference switch or a mode change. The observation period is usually the time from the disturbance, to just after the synchronizer has settled to a steady state. 5.13 Lock Time This is the time it takes the PLL to frequency lock to the input signal. Phase lock occurs when the input signal and output signal are aligned in phase with respect to each other within a certain phase distance (not including jitter). Lock time is affected by many factors which include: • initial input to output phase difference • initial input to output frequency difference • PLL loop filter bandwidth • PLL phase slope limiter • in-lock phase distance The presence of input jitter makes it difficult to define when the PLL is locked as it may not be able to align its output to the input within the required phase distance, dependent on the PLL bandwidth and the input jitter amplitude and frequency. Although a short lock time is desirable, it is not always possible to achieve due to other synchronizer requirements. For instance, better jitter transfer performance is achieved with a lower frequency loop filter which increases lock time. And better (smaller) phase slope performance (limiter) results in longer lock times. 31 Zarlink Semiconductor Inc. ZL30102 6.0 Data Sheet Applications This section contains ZL30102 application specific details for power supply decoupling, reset operation, clock and crystal operation. 6.1 Power Supply Decoupling Jitter levels on the ZL30102 output clocks may increase if the device is exposed to excessive noise on its power pins. For optimal jitter performance, the ZL30102 device should be isolated from noise on power planes connected to its 3.3 V and 1.8 V supply pins. For recommended common layout practices, refer to Zarlink Application Note ZLAN-178. 6.2 Master Clock The ZL30102 can use either a clock or crystal as the master timing source. Zarlink application note ZLAN-68 lists a number of applicable oscillators and crystals that can be used with the ZL30102. 6.2.1 Clock Oscillator When selecting a clock oscillator, numerous parameters must be considered. This includes absolute frequency, frequency change over temperature, output rise and fall times, output levels, duty cycle and phase noise. 1 Frequency 20 MHz 2 Tolerance as required 3 Rise & fall time < 10 ns 4 Duty cycle 40% to 60% Table 7 - Typical Clock Oscillator Specification The output clock should be connected directly (not AC coupled) to the OSCi input of the ZL30102, and the OSCo output should be left open as shown in Figure 19. ZL30102 +3.3 V OSCi +3.3 V 20 MHz OUT GND 0.1 µF OSCo No Connection Figure 19 - Clock Oscillator Circuit 32 Zarlink Semiconductor Inc. ZL30102 6.2.2 Data Sheet Crystal Oscillator Alternatively, a Crystal Oscillator may be used. A complete oscillator circuit made up of a crystal, resistor and capacitors is shown in Figure 20. The accuracy of a crystal oscillator depends on the crystal tolerance as well as the load capacitance tolerance. Typically, for a 20 MHz crystal specified with a 32 pF load capacitance, each 1 pF change in load capacitance contributes approximately 9 ppm to the frequency deviation. Consequently, capacitor tolerances and stray capacitances have a major effect on the accuracy of the oscillator frequency. The crystal should be a fundamental mode type - not an overtone. The fundamental mode crystal permits a simpler oscillator circuit with no additional filter components and is less likely to generate spurious responses. A typical crystal oscillator specification and circuit is shown in Table 8 and Figure 20 respectively. . 1 Frequency 20 MHz 2 Tolerance as required 3 Oscillation mode fundamental 4 Resonance mode parallel 5 Load capacitance as required 6 Maximum series resistance 50 Ω Table 8 - Typical Crystal Oscillator Specification ZL30102 20 MHz OSCi 1 MΩ OSCo 100 Ω 1 μH The 100 Ω resistor and the 1 μH inductor may improve stability and are optional. Figure 20 - Crystal Oscillator Circuit 6.3 Power Up Sequence The ZL30102 requires that the 3.3 V supply is not powered up after the 1.8 V supply. This is to prevent the risk of latch-up due to the presence of parasitic diodes in the IO pads. Two options are given: 1. Power-up the 3.3 V supply fully first, then power up the 1.8 V supply 2. Power up the 3.3 V supply and the 1.8 V supply simultaneously, ensuring that the 3.3 V supply is never lower than a few hundred millivolts below the 1.8 V supply (e.g., by using a schottky diode or controlled slew rate) 33 Zarlink Semiconductor Inc. ZL30102 6.4 Data Sheet Reset Circuit A simple power up reset circuit with about a 60 μs reset low time is shown in Figure 21. Resistor RP is for protection only and limits current into the RST pin during power down conditions. The reset low time is not critical but should be greater than 300 ns. ZL30102 +3.3 V R 10 kΩ RST RP 1 kΩ C 10 nF Figure 21 - Power-Up Reset Circuit 34 Zarlink Semiconductor Inc. ZL30102 6.5 Data Sheet Clock Redundancy System Architecture Carrier-Class Telecommunications Equipment deployed in today’s networks guarantee better than 99.999% operational availability (equivalent to less than 7 minutes of downtime per year). This high level of uninterrupted service is achieved by fully redundant architectures with hot swappable cards like an ECTF H.110 compliant system. Timing for these types of systems can be generated by the ZL30102 which supports primary/secondary master timing protection switching. The architecture shown in Figure 22 is based on the ZL30102 being deployed on two separate timing cards; the primary master timing card and the secondary master timing card. In normal operation the primary master timing card receives synchronization from the network and provides timing for the whole system. The redundant secondary master timing card is phase locked to the backplane clock and frame pulse through its REF2 and REF2_SYNC inputs. These two designated inputs allow the secondary master timing card to track the primary master timing card clocks with minimal phase skew. When the primary master timing card fails unexpectedly (this failure is not related to reference failure) then all switch cards or line cards will detect this failure and they will switch to the timing supplied by the secondary master timing card. The secondary master timing card will be promoted to primary master and switch from using the REF2 and REF2_SYNC inputs to one of the REF0 or REF1 inputs. Backplane CT_FRAME_B CT_C8_A CT_FRAME_A CT_C8_B CT_NETREF_2 CT_NETREF_1 ZL30102 REF0 REF1 C8o REF2 Switch Card or Line Card F8o REF2_SYNC SEC_MSTR 0 Master/Slave Control Primary Master Timing Card Switch Card or Line Card ZL30102 REF0 REF1 C8o REF2 F8o REF2_SYNC SEC_MSTR 1 Master/Slave Control Secondary Master Timing Card Figure 22 - Typical Clocking Architecture of an ECTF H.110 System 35 Zarlink Semiconductor Inc. ZL30102 7.0 Characteristics 7.1 AC and DC Electrical Characteristics Data Sheet Absolute Maximum Ratings* Parameter Symbol Min. Max. Units VDD_R -0.5 4.6 V VCORE_R -0.5 2.5 V 1 Supply voltage 2 Core supply voltage 3 Voltage on any digital pin VPIN -0.5 6 V 4 Voltage on OSCi and OSCo pin VOSC -0.3 VDD + 0.3 V 5 Current on any pin IPIN 30 mA 6 Storage temperature TST 125 °C 7 TQFP 64 pin package power dissipation PPD 500 mW 8 ESD rating VESD 2 kV -55 * Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied. * Voltages are with respect to ground (GND) unless otherwise stated. Recommended Operating Conditions* Characteristics 1 Supply voltage 2 Core supply voltage 3 Operating temperature Sym. Min. Typ. Max. Units VDD 2.97 3.30 3.63 V VCORE 1.62 1.80 1.98 V TA -40 25 85 °C * Voltages are with respect to ground (GND) unless otherwise stated. DC Electrical Characteristics* Characteristics 1 Supply current with: OSCi = 0 V Sym. Min. Max. Units IDDS 1 9 mA Notes outputs loaded with 30 pF 2 OSCi = Clock, OUT_SEL=0 IDD 30 60 mA 3 OSCi = Clock, OUT_SEL=1 IDD 41 73 mA 4 Core supply current with: OSCi = 0 V ICORES 0 30 μA 5 OSCi = Clock ICORE 14 20 mA 6 Schmitt trigger Low to High threshold point Vt+ 1.43 1.85 V 7 Schmitt trigger High to Low threshold point Vt- 0.80 1.10 V 8 Input leakage current IIL -105 105 μA VI = VDD or 0 V 9 High-level output voltage VOH 2.4 V IOH = 8 mA for clock and frame-pulse outputs, 4 mA for status outputs 36 Zarlink Semiconductor Inc. All device inputs are Schmitt trigger type. ZL30102 Data Sheet DC Electrical Characteristics* Characteristics 10 Sym. Low-level output voltage Min. Max. Units 0.4 V VOL Notes IOL = 8 mA for clock and frame-pulse outputs, 4 mA for status outputs * Supply voltage and operating temperature are as per Recommended Operating Conditions. * Voltages are with respect to ground (GND) unless otherwise stated. AC Electrical Characteristics* - Timing Parameter Measurement Voltage Levels (see Figure 23). Characteristics Sym. CMOS Units VT 0.5 · VDD V 1 Threshold Voltage 2 Rise and Fall Threshold Voltage High VHM 0.7 · VDD V 3 Rise and Fall Threshold Voltage Low VLM 0.3 · VDD V * Supply voltage and operating temperature are as per Recommended Operating Conditions. * Voltages are with respect to ground (GND) unless otherwise stated. Timing Reference Points V HM VT V LM ALL SIGNALS tIRF, tORF tIRF, tORF Figure 23 - Timing Parameter Measurement Voltage Levels AC Electrical Characteristics* - Input timing for REF0, REF1 and REF2 references (see Figure 24). Characteristics Symbol Min. Typ. Max. Units 1 8 kHz reference period tREF8kP 121 125 128 μs 2 1.544 MHz reference period tREF1.5P 338 648 950 ns 3 2.048 MHz reference period tREF2P 263 488 712 ns 4 8.192 MHz reference period tREF8P 63 122 175 ns 5 16.384 MHz reference period tREF16P 38 61 75 ns 6 reference pulse width high or low tREFW 15 ns * Supply voltage and operating temperature are as per Recommended Operating Conditions. * Period Min/Max values are the limits to avoid a single-cycle fault detection. Short-term and long-term average periods must be within Out-ofRange limits. 37 Zarlink Semiconductor Inc. ZL30102 Data Sheet tREFP tREFW tREFW REF0/1/2 tREFD output clock with the same frequency as REF tREF8kD, tREF_F8D F8_32o Figure 24 - REF0/1/2 Input Timing and Input to Output Timing AC Electrical Characteristics* - Input timing for REF2_SYNC (see Figure 25). Characteristics Symbol Min. Max. Units 1 REF2_SYNC lead time tSYNC_LD 12 ns 2 REF2_SYNC lag time tSYNC_LG tREFP - 28 ns 3 REF2_SYNC pulse width high or low tSYNC_W 15 ns * Supply voltage and operating temperature are as per Recommended Operating Conditions. * See Figure 17, “Examples of REF2 & REF2_SYNC to Output Alignment” on page 27 for further explanation. edge used for alignment tREFP REF2 tSYNC_LD tSYNC_LG REF2_SYNC tSYNC_W Note: REF2 can be 1.544 MHz, 2.048 MHz, 8.192 MHz or 16.384 MHz. REF2_SYNC is 8 kHz. Figure 25 - REF2_SYNC Timing 38 Zarlink Semiconductor Inc. Notes tREFP = minimum period of REF2 clock ZL30102 Data Sheet AC Electrical Characteristics* - Input to output timing for REF0, REF1 and REF2 references when TIE_CLR = 0 (see Figure 24). Characteristics Symbol Min. Max. Units 1 8 kHz reference input to F8/F32o delay tREF8kD -0.3 2.0 ns 2 1.544 MHz reference input to C1.5o delay tREF1.5D -1.2 0.2 ns 3 1.544 MHz reference input to F8/F32o delay tREF1.5_F8D -1.1 0.9 ns 4 2.048 MHz reference input to C2o delay tREF2D -1.2 0 ns 5 2.048 MHz reference input to F8/F32o delay tREF2_F8D -0.6 0.8 ns 6 8.192 MHz reference input to C8o delay tREF8D -2.0 0.1 ns 7 8.192 MHz reference input to F8/F32o delay tREF8_F8D -1.0 1.8 ns 8 16.384 MHz reference input to C16o delay tREF16D -1.1 1.9 ns 9 16.384 MHz reference input to F8/F32o delay tREF16_F8D 29.0 30.6 ns * Supply voltage and operating temperature are as per Recommended Operating Conditions. 39 Zarlink Semiconductor Inc. ZL30102 Data Sheet AC Electrical Characteristics* - E1 output timing (see Figure 26). Characteristics Sym. Min. Max. Units 1 C2o delay tC2D -0.4 0.3 ns 2 C2o pulse width low tC2L 243.0 244.1 ns 3 F4o pulse width low tF4L 243.3 244.3 ns 4 F4o delay tF4D 121.5 122.2 ns 5 C4o pulse width low tC4L 121.0 122.4 ns 6 C4o delay tC4D -0.3 1.1 ns 7 F8o pulse width high tF8H 121.6 123.5 ns 8 C8o pulse width low tC8L 60.3 61.3 ns 9 C8o delay tC8D -0.4 0.3 ns 10 F16o pulse with low tF16L 60.3 61.2 ns 11 F16o delay tF16D 29.9 30.8 ns 12 C16o pulse width low tC16L 28.7 30.8 ns 13 C16o delay tC16D -0.5 1.5 ns 14 F32o pulse width high tF32H 30.0 32.1 ns 15 C32o pulse width low tC32L 14.7 15.5 ns 16 C32o delay tC32D -0.5 0.5 ns 17 F65o pulse with low tF65L 14.7 15.5 ns 18 F65o delay tF65D 7.1 8.0 ns 19 C65o pulse width low tC65L 7.2 8.1 ns 20 C65o delay tC65D -1.0 1.0 ns 21 Output clock and frame pulse rise time tOR 1.1 2.0 ns 22 Output clock and frame pulse fall time tOF 1.2 2.3 ns * Supply voltage and operating temperature are as per Recommended Operating Conditions. 40 Zarlink Semiconductor Inc. Notes outputs loaded with 30 pF ZL30102 Data Sheet tF8H F8o tC2D tC2L C2o tF4D tF4L F4o tC4D tC4L C4o tC8L tC8D C8o tF16D tF16L F16o tC16L tC16D C16o tF32H F32o tC32L tC32D C32o tF65D tF65L F65o tC65D tC65L C65o F32o, C32o, F65o and C65o are drawn on a larger scale than the other waveforms in this diagram. Figure 26 - E1 Output Timing Referenced to F8/F32o 41 Zarlink Semiconductor Inc. ZL30102 Data Sheet AC Electrical Characteristics* - DS1 output timing (see Figure 27). Characteristics Sym. Min. Max. Units 1 C1.5o delay tC1.5D -0.6 0.6 ns 2 C1.5o pulse width low tC1.5L 323.1 324.0 ns 3 C3o delay tC3D -0.7 0.5 ns 4 C3o pulse width low tC3L 161.1 162.0 ns 5 Output clock and frame pulse rise time tOR 1.1 2.0 ns 6 Output clock and frame pulse fall time tOF 1.2 2.3 ns Notes outputs loaded with 30 pF * Supply voltage and operating temperature are as per Recommended Operating Conditions. o F8_32o tC1.5D tC1.5L C1.5o tC3D tC3L C3o Figure 27 - DS1 Output Timing Referenced to F8/F32o AC Electrical Characteristics* - DS2 output timing (see Figure 28). Characteristics Sym. Min. Max. Units 1 C6o delay tC6D -0.70 0.70 ns 2 C6o pulse width low tC6L 78.5 79.3 ns 3 Output clock and frame pulse rise time tOR 1.1 2.0 ns 4 Output clock and frame pulse fall time tOF 1.2 2.3 ns * Supply voltage and operating temperature are as per Recommended Operating Conditions. F8_32o tC6L tC6D C6o Figure 28 - DS2 Output Timing Referenced to F8/F32o 42 Zarlink Semiconductor Inc. Notes outputs loaded with 30 pF ZL30102 Data Sheet AC Electrical Characteristics* - OSCi 20 MHz Master Clock Input Characteristics Min. Max. Units 1 Oscillator Tolerance - DS1 -32 +32 ppm 2 Oscillator Tolerance - E1 -50 +50 ppm 3 Duty cycle 40 60 % 4 Rise time 10 ns 5 Fall time 10 ns * Supply voltage and operating temperature are as per Recommended Operating Conditions. 43 Zarlink Semiconductor Inc. Notes ZL30102 7.2 Data Sheet Performance Characteristics Performance Characteristics* - Functional Characteristics Min. Max. Units 0.1 ppm Notes 1 Holdover accuracy 2 Holdover stability 0 ppm Determined by stability of the 20 MHz master clock oscillator 3 Freerun accuracy 0 ppm Determined by accuracy of the 20 MHz master clock oscillator 4 Capture range -130 +130 ppm The 20 MHz master clock oscillator set at 0 ppm Reference Out of Range Threshold (including hysteresis) 5 DS1 -64 -83 +64 +83 ppm The 20 MHz master clock oscillator set at 0 ppm 6 E1 -100 -130 +100 +130 ppm The 20 MHz master clock oscillator set at 0 ppm Lock Time 7 1.8 Hz filter 40 50 s ±64 ppm to ±100 ppm frequency offset, SEC_MSTR = 0, HMS = 1, TIE_CLR = 1 and FASTLOCK=0 8 58 Hz filter (8 kHz reference) 15 15 s ±64 ppm to ±100 ppm frequency offset, SEC_MSTR = 1, HMS = 1, TIE_CLR = 1 and FASTLOCK=0 9 922 Hz filter 1 1 s ±64 ppm to ±100 ppm frequency offset, SEC_MSTR = 1, HMS = 1, TIE_CLR = 1 and FASTLOCK=0 10 fast lock 1 1 s ±64 ppm to ±100 ppm frequency offset, HMS = 1, TIE_CLR = 1 and FASTLOCK=1 TIE_CLR=1 Output Phase Continuity (MTIE) 11 Reference switching 13 ns 12 Switching from Normal mode to Holdover mode 0 ns 13 Switching from Holdover mode to Normal mode 13 ns TIE_CLR=1 and HMS=1 Output Phase Slope 14 primary master mode 61 μ/s SEC_MSTR=0 15 secondary master mode 9.5 ms/s SEC_MSTR=1 * Supply voltage and operating temperature are as per Recommended Operating Conditions. 44 Zarlink Semiconductor Inc. ZL30102 Data Sheet Performance Characteristics*: Input Wander and Jitter Tolerance Conformance Input reference frequency Standard Interface 1 1.544 MHz Telcordia GR-1244-CORE DS1 Line timing, DS1 External timing 2 2.048 MHz ITU-T G.823 2048 kbit/s * Supply voltage and operating temperature are as per Recommended Operating Conditions. Performance Characteristics*: Output Jitter Generation - ANSI T1.403 conformance ANSI T1.403 Jitter Generation Requirements Signal Jitter measurement filter Limit in UI Equivalent limit in the time domain ZL30102 maximum jitter generation Units DS1 Interface 1 2 C1.5o (1.544 MHz) 8 kHz to 40 kHz 0.07 UIpp 45.3 0.30 nspp 10 Hz to 40 kHz 0.5 UIpp 324 0.32 nspp * Supply voltage and operating temperature are as per Recommended Operating Conditions. Performance Characteristics*: Output Jitter Generation - ITU-T G.747 conformance ITU-T G.747 Jitter Generation Requirements Signal Jitter measurement filter Limit in UI Equivalent limit in the time domain ZL30102 maximum jitter generation 7.92 0.20 Units DS2 Interface 1 C6o (6.312 MHz) 10 kHz to 60 kHz 0.05 UIpp nspp * Supply voltage and operating temperature are as per Recommended Operating Conditions. Performance Characteristics*: Output Jitter Generation - ITU-T G.812 conformance ITU-T G.812 Jitter Generation Requirements Signal Jitter measurement filter Limit in UI Equivalent limit in the time domain ZL30102 maximum jitter generation 24.4 0.36 Units E1 Interface 1 C2o (2.048 MHz) 20 Hz to 100 kHz 0.05 UIpp * Supply voltage and operating temperature are as per Recommended Operating Conditions. 45 Zarlink Semiconductor Inc. nspp ZL30102 Data Sheet Performance Characteristics* - Unfiltered Jitter Generation Max. [nspp] Characteristics 1 C1.5o (1.544 MHz) 0.45 2 C2o (2.048 MHz) 0.47 3 C3o (3.088 MHz) 0.53 4 C4o (4.096 MHz) 0.42 5 C6o (6.312 MHz) 0.58 6 C8o (8.192 MHz) 0.42 7 C16o (16.384 MHz) 0.56 8 C32o (32.768 MHz) 0.46 9 C65o (65.536 MHz) 0.49 10 F4o (8 kHz) 0.43 11 F8o (8 kHz) 0.43 12 F16o (8 kHz) 0.44 13 F32o (8 kHz) 0.43 14 F65o (8 kHz) 0.46 * Supply voltage and operating temperature are as per Recommended Operating Conditions. 46 Zarlink Semiconductor Inc. Notes Package Code c Zarlink Semiconductor 2002 All rights reserved. ISSUE ACN DATE APPRD. Previous package codes For more information about all Zarlink products visit our Web Site at www.zarlink.com Information relating to products and services furnished herein by Zarlink Semiconductor Inc. or its subsidiaries (collectively “Zarlink”) is believed to be reliable. However, Zarlink assumes no liability for errors that may appear in this publication, or for liability otherwise arising from the application or use of any such information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or use. Neither the supply of such information or purchase of product or service conveys any license, either express or implied, under patents or other intellectual property rights owned by Zarlink or licensed from third parties by Zarlink, whatsoever. Purchasers of products are also hereby notified that the use of product in certain ways or in combination with Zarlink, or non-Zarlink furnished goods or services may infringe patents or other intellectual property rights owned by Zarlink. This publication is issued to provide information only and (unless agreed by Zarlink in writing) may not be used, applied or reproduced for any purpose nor form part of any order or contract nor to be regarded as a representation relating to the products or services concerned. The products, their specifications, services and other information appearing in this publication are subject to change by Zarlink without notice. No warranty or guarantee express or implied is made regarding the capability, performance or suitability of any product or service. Information concerning possible methods of use is provided as a guide only and does not constitute any guarantee that such methods of use will be satisfactory in a specific piece of equipment. It is the user’s responsibility to fully determine the performance and suitability of any equipment using such information and to ensure that any publication or data used is up to date and has not been superseded. Manufacturing does not necessarily include testing of all functions or parameters. These products are not suitable for use in any medical products whose failure to perform may result in significant injury or death to the user. All products and materials are sold and services provided subject to Zarlink’s conditions of sale which are available on request. Purchase of Zarlink’s I2C components conveys a license under the Philips I2C Patent rights to use these components in an I2C System, provided that the system conforms to the I2C Standard Specification as defined by Philips. Zarlink, ZL, the Zarlink Semiconductor logo and the Legerity logo and combinations thereof, VoiceEdge, VoicePort, SLAC, ISLIC, ISLAC and VoicePath are trademarks of Zarlink Semiconductor Inc. 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