ZL30131GGG

ZL30131 OC-192/STM-64 SONET/SDH/10GbE Network Interface Synchronizer Short Form Data Sheet July 2009 Features • Ordering Information Synchronizes to standard telecom or Ethernet backplane clocks and provides jitter filtered output clocks for SONET/SDH, PDH and Ethernet network interface cards • Supports the requirements of ITU-T G.8262 for synchronous Ethernet Equipment slave Clocks (EEC option 1 and 2) • Two independent DPLLs provides timing for the transmit path (backplane to line rate) and the receive path (recovered line rate to backplane) ZL30131GGG 100 Pin CABGA Trays ZL30131GGG2 100 Pin CABGA* Trays *Pb Free Tin/Silver/Copper -40oC to +85oC multiple of 8 kHz up to 100 MHz (e.g., T1/E1, DS3/E3) • Synchronizes to telecom reference clocks (2 kHz, N*8 kHz up to 77.76 MHz, 155.52 MHz) or to Ethernet reference clocks (25 MHz, 50 MHz, 62.5 MHz, 125 MHz) Generates several styles of output frame pulses with selectable pulse width, polarity, and frequency • Configurable input to output delay and output to output phase alignment • Selectable loop bandwidth of 14 Hz, 28 Hz, 890 Hz, or 0.1 Hz • Configurable through a serial interface (SPI or I2C) • • Supports automatic hitless reference switching and short term holdover during loss of reference inputs DPLLs can be configured to provide synchronous or asynchronous clock outputs • Generates standard SONET/SDH clock rates (e.g., 19.44 MHz, 38.88 MHz, 77.76 MHz, 155.52 MHz, 622.08 MHz) or Ethernet clock rates (e.g. 25 MHz, 50 MHz, 125 MHz, 156.25 MHz, 312.5 MHz) for synchronizing Ethernet PHYs • • Applications Programmable output synthesizers (P0, P1) generate telecom clock frequencies from any • ITU-T G.8262 Line Cards which support 1GbE and 10GbE interfaces • SONET line cards up to OC-192 • SDH line cards up to STM-64 ref_out osci ref0 ref1 ref2 ref3 ref4 ref5 ref6 ref7 /N1 /N2 osco diff0_p/n Tx DPLL diff1_p/n apll_clk0 apll_clk1 APLL Input Ports sync0 sync1 sync2 p0_clk0 p0_clk1 p0_fp0 p0_fp1 P0 Ref Mon Tx ref0 p1_clk0 p1_clk1 P1 Rx DPLL ref7 Rx mode hold I2C/SPI lock JTAG Figure 1 - Functional Block Diagram 1 Zarlink Semiconductor Inc. Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright 2008-2009, Zarlink Semiconductor Inc. All Rights Reserved. ZL30131 Short Form Data Sheet Pin Description Pin # Name I/O Type Description Input Reference C1 B2 A3 C3 B3 B4 C4 A4 ref0 ref1 ref2 ref3 ref4 ref5 ref6 ref7 Iu Input References 7:0 (LVCMOS, Schmitt Trigger). These input references are available to both the Tx DPLL and the Rx DPLL for synchronizing output clocks. All eight input references can lock to any multiple of 8 kHz up to 77.76 MHz including 25 MHz and 50 MHz. Input ref0 and ref1 have additional configurable pre-dividers allowing input frequencies of 62.5 MHz, 125 MHz, and 155.52 MHz. These pins are internally pulled up to Vdd. B1 A1 A2 sync0 sync1 sync2 Iu Frame Pulse Synchronization References 2:0 (LVCMOS, Schmitt Trigger). These are optional frame pulse synchronization inputs associated with input references 0, 1 and 2. These inputs accept frame pulses in a clock format (50% duty cycle) or a basic frame pulse format with minimum pulse width of 5 ns. These pins are internally pulled up to Vdd. Output Clocks and Frame Pulses A9 B10 diff0_p diff0_n O Differential Output Clock 0 (LVPECL). When in SONET/SDH mode, this output can be configured to provide any one of the available SONET/SDH clocks (6.48 MHz, 19.44 MHz, 38.88 MHz, 51.84 MHz, 77.76 MHz, 155.52 MHz, 311.04 MHz, 622.08 MHz). When in Ethernet mode, this output can be configured to provide any of the Ethernet clocks (25 MHz, 50 MHz, 62.5 MHz, 125 MHz, 156.25 MHz, 312.5 MHz). See “Output Clocks and Frame Pulses” section on page 22 more detail on clock frequency settings. A10 B9 diff1_p diff1_n O Differential Output Clock 1 (LVPECL). When in SONET/SDH mode, this output can be configured to provide any one of the available SONET/SDH clocks (6.48 MHz, 19.44 MHz, 38.88 MHz, 51.84 MHz, 77.76 MHz, 155.52 MHz, 311.04 MHz, 622.08 MHz). When in Ethernet mode, this output can be configured to provide any of the Ethernet clocks (25 MHz, 50 MHz, 62.5 MHz, 125 MHz, 156.25 MHz, 312.5 MHz). See “Output Clocks and Frame Pulses” section on page 22 more detail on clock frequency settings. D10 apll_clk0 O APLL Output Clock 0 (LVCMOS). This output can be configured to provide any one of the SONET/SDH clock outputs up to 77.76 MHz or any of the Ethernet clock rates up to 125 MHz. The default frequency for this output is 77.76 MHz. G10 apll_clk1 O APLL Output Clock 1 (LVCMOS). This output can be configured to provide any one of the SONET/SDH clock outputs up to 77.76 MHz or any of the Ethernet clock rates up to 125 MHz. The default frequency for this output is 19.44 MHz. K9 p0_clk0 O Programmable Synthesizer 0 - Output Clock 0 (LVCMOS). This output can be configured to provide any frequency with a multiple of 8 kHz up to 100 MHz in addition to 2 kHz. The default frequency for this output is 2.048 MHz. K7 p0_clk1 O Programmable Synthesizer 0 - Output Clock 1 (LVCMOS). This is a programmable clock output configurable as a multiple or division of the p0_clk0 frequency within the range of 2 kHz to 100 MHz. The default frequency for this output is 8.192 MHz. K8 p0_fp0 O Programmable Synthesizer 0 - Output Frame Pulse 0 (LVCMOS). This output can be configured to provide virtually any style of output frame pulse associated with the p0 clocks. The default frequency for this frame pulse output is 8 kHz. 5 Zarlink Semiconductor Inc. ZL30131 Short Form Data Sheet Pin # Name I/O Type J7 p0_fp1 O Programmable Synthesizer 0 - Output Frame Pulse 1 (LVCMOS). This output can be configured to provide virtually any style of output frame pulse associated with the p0 clocks. The default frequency for this frame pulse output is 8 kHz J10 p1_clk0 O Programmable Synthesizer 1 - Output Clock 0 (LVCMOS). This output can be configured to provide any frequency with a multiple of 8 kHz up to 100 MHz in addition to 2 kHz. The default frequency for this output is 1.544 MHz (DS1). K10 p1_clk1 O Programmable Synthesizer1 - Output Clock 1 (LVCMOS). This is a programmable clock output configurable as a multiple or division of the p1_clk0 frequency within the range of 2 kHz to 100 MHz. The default frequency for this output is 3.088 MHz (2x DS1). E1 ref_out O Rx DPLL Selected Output Reference (LVCMOS). This is a buffered copy of the output of the reference selector for the Rx DPLL. Switching between input reference clocks at this output is not hitless. H5 rst_b I Reset (LVCMOS, Schmitt Trigger). A logic low at this input resets the device. To ensure proper operation, the device must be reset after power-up. Reset should be asserted for a minimum of 300 ns. J5 hs_en Iu Tx DPLL Hitless Switching Enable (LVCMOS, Schmitt Trigger). A logic high at this input enables hitless reference switching. A logic low disables hitless reference switching and re-aligns the Tx DPLL’s output phase to the phase of the selected reference input. This feature can also be controlled through software registers. This pin is internally pulled up to Vdd. C2 D2 mode_0 mode_1 Iu Tx DPLL Mode Select 1:0 (LVCMOS, Schmitt Trigger). During reset, the levels on these pins determine the default mode of operation for the Tx DPLL (Automatic, Normal, Holdover or Freerun). After reset, the mode of operation can be controlled directly with these pins, or by accessing the tx_dpll_modesel register (0x1F) through the serial interface. This pin is internally pulled up to Vdd. K1 diff0_en Iu Differential Output 0 Enable (LVCMOS, Schmitt Trigger). When set high, the differential LVPECL output 0 driver is enabled. When set low, the differential driver is tristated reducing power consumption. This pin is internally pulled up to Vdd. D3 diff1_en Iu Differential Output 1 Enable (LVCMOS, Schmitt Trigger). When set high, the differential LVPECL output 1 driver is enabled. When set low, the differential driver is tristated reducing power consumption.This pin is internally pulled up to Vdd. H1 lock O Lock Indicator (LVCMOS). This is the lock indicator pin for the Tx DPLL. This output goes high when the Tx DPLL’s output is frequency and phase locked to the input reference. J1 hold O Holdover Indicator (LVCMOS). This pin goes high when the Tx DPLL enters the holdover mode. Description Control Status 6 Zarlink Semiconductor Inc. ZL30131 Pin # Name I/O Type Short Form Data Sheet Description Serial Interface E2 sck_scl I/B Clock for Serial Interface (LVCMOS). Serial interface clock. When i2c_en = 0, this pin acts as the sck pin for the serial interface. When i2c_en = 1, this pin acts as the scl pin (bidirectional) for the I2C interface. F1 si_sda I/B Serial Interface Input (LVCMOS). Serial interface data pin. When i2c_en = 0, this pin acts as the si pin for the serial interface. When i2c_en = 1, this pin acts as the sda pin (bidirectional) for the I2C interface. G1 so O Serial Interface Output (LVCMOS). Serial interface data output. When i2c_en = 0, this pin acts as the so pin for the serial interface. When i2c_en = 1, this pin is unused and should be left unconnected. E3 cs_b_asel0 Iu Chip Select for SPI/Address Select 0 for I2C (LVCMOS). When i2c_en = 0, this pin acts as the chip select pin (active low) for the serial interface. When i2c_en = 1, this pin acts as the asel0 pin for the I2C interface. F3 asel1 Iu Address Select 1 for I2C (LVCMOS). When i2c_en = 1, this pin acts as the asel1 pin for the I2C interface. Internally pulled up to Vdd. Leave open when not in use. F2 asel2 Iu Address Select 2 for I2C (LVCMOS). When i2c_en = 1, this pin acts as the asel2 pin for the I2C interface. Internally pulled up to Vdd. Leave open when not in use. G2 int_b O Interrupt Pin (LVCMOS). Indicates a change of device status prompting the processor to read the enabled interrupt service registers (ISR). This pin is an open drain, active low and requires an external pulled-up to Vdd. J2 i2c_en Iu I2C Interface Enable (LVCMOS). If set high, the I2C interface is enabled, if set low, the SPI interface is enabled. Internally pull-up to Vdd. APLL Loop Filter A6 apll_filter A External Analog PLL Loop Filter terminal. B6 filter_ref0 A Analog PLL External Loop Filter Reference. C6 filter_ref1 A Analog PLL External Loop Filter Reference. JTAG and Test J4 tdo O Test Serial Data Out (Output). JTAG serial data is output on this pin on the falling edge of tck. This pin is held in high impedance state when JTAG scan is not enabled. K2 tdi Iu Test Serial Data In (Input). JTAG serial test instructions and data are shifted in on this pin. This pin is internally pulled up to Vdd. If this pin is not used then it should be left unconnected. H4 trst_b Iu Test Reset (LVCMOS). Asynchronously initializes the JTAG TAP controller by putting it in the Test-Logic-Reset state. This pin should be pulsed low on powerup to ensure that the device is in the normal functional state. This pin is internally pulled up to Vdd. If this pin is not used then it should be connected to GND. K3 tck I Test Clock (LVCMOS): Provides the clock to the JTAG test logic. If this pin is not used then it should be pulled down to GND. 7 Zarlink Semiconductor Inc. ZL30131 Short Form Data Sheet Pin # Name I/O Type J3 tms Iu Test Mode Select (LVCMOS). JTAG signal that controls the state transitions of the TAP controller. This pin is internally pulled up to VDD. If this pin is not used then it should be left unconnected. Description Master Clock K4 osci I Oscillator Master Clock Input (LVCMOS). This input accepts a 20 MHz reference from a clock oscillator (TCXO, OCXO). The stability and accuracy of the clock at this input determines the free-run accuracy and the long term holdover stability of the output clocks. K5 osco O Oscillator Master Clock Output (LVCMOS). This pin must be left unconnected when the osci pin is connected to a clock oscillator. Miscellaneous J6 IC Internal Connection. Connect to ground. C5 B5 K6 H10 IC Internal Connection. Leave unconnected. H7 G3 E10 F10 D1 NC No Connection. Leave Unconnected. Power and Ground D9 E4 G8 G9 J8 J9 H6 H8 VDD P P P P P P P P Positive Supply Voltage. +3.3VDC nominal. E8 F4 VCORE P P Positive Supply Voltage. +1.8VDC nominal. A5 A8 C10 AVDD P P P Positive Analog Supply Voltage. +3.3VDC nominal. B7 B8 H2 AVCORE P P P Positive Analog Supply Voltage. +1.8VDC nominal. 8 Zarlink Semiconductor Inc. ZL30131 I/O Type Description Pin # Name D4 D5 D6 D7 E5 E6 E7 F5 F6 F7 G4 G5 G6 G7 E9 F8 F9 H9 VSS G G G G G G G G G G G G G G G G G G Ground. 0 Volts. A7 C7 C8 C9 D8 H3 AVSS G G G G G G Analog Ground. 0 Volts. IId Iu OAPG- Short Form Data Sheet Input Input, Internally pulled down Input, Internally pulled up Output Analog Power Ground 9 Zarlink Semiconductor Inc. ZL30131 1.0 Short Form Data Sheet Pin Diagram TOP VIEW 1 1 2 3 4 5 6 7 8 9 10 sync1 sync2 ref2 ref7 AVDD apll_filter AVSS AVDD diff0_p diff1_p sync0 ref1 ref4 ref5 IC filter_ref0 AVCORE AVCORE diff1_n diff0_n ref0 mode_0 ref3 ref6 IC filter_ref1 AVSS AVSS AVSS AVDD NC mode_1 diff1_en VSS VSS VSS VSS AVSS VDD apll_clk0 ref_out sck/ scl cs_b/ asel0 VDD VSS VSS VSS VCORE VSS NC si/ sdh asel2 asel1 VCORE VSS VSS VSS VSS VSS NC so int_b NC VSS VSS VSS VSS VDD VDD apll_clk1 lock AVCORE AVSS trst_b rst_b VDD NC VDD VSS IC hold i2c_en tms tdo hs_en IC p0_fp1 VDD VDD p1_clk0 diff0_en tdi tck osci osco IC p0_clk1 p0_fp0 p0_clk0 p1_clk1 A B C D E F G H J K 1 - A1 corner is identified with a dot. 10 Zarlink Semiconductor Inc. ZL30131 2.0 Short Form Data Sheet Functional Description The ZL30131 OC-192/STM-64 PDH/SONET/SDH/10GbE Network Interface Synchronizer is a highly integrated device that provides timing for both PDH/SONET/SDH and Ethernet network interface cards. A functional block diagram is shown in Figure 1. This device is ideally suited for designs that require both a transmit timing path (backplane to PHY) and a receive timing path (PHY to backplane). Each path is controlled with separate DPLLs (Tx DPLL, Rx DPLL) which are both independently configurable through the serial interface (SPI or I2C). A typical application of the ZL30131 is shown in Figure 2. In this application, the ZL30131 translates the 19.44 MHz clock from the telecom rate backplane (system timing bus), translates the frequency to 622.08 MHz or 156.25 MHz for the PHY Tx clock, and filters the jitter to ensure compliance with the related standards. A programmable synthesizer (P0) provides synchronous PDH clocks with multiples of 8 kHz for generating PDH interface clocks. On the receive path, the Rx DPLL and the P1 synthesizer translate the line recovered clock (8 kHz or 25 MHz) from the PHY to the 19.44 MHz telecom backplane (line recovered timing) for the central timing cards. The ZL30131 allows easy integration of Ethernet line rates with today’s telecom backplanes. BITS A Central Timing Card BITS B S P Central Timing Card P S XOVER DPLL DPLL ZL30121 ZL30121 P S 19.44 MHz 19.44 MHz S P Line Recovered Timing A P Telecom Backplane S B System Timing Bus A 19.44 MHz P1 ZL30131 B A B 19.44 MHz ZL30131 Tx DPLL Tx DPLL Rx DPLL Rx DPLL P0 8 kHz P1 APLL 1.544 MHz APLL 622.08 MHz 156.25 MHz PHY P0 1.544 MHz 25 MHz PHY OC-192 Line Card 10GbE Line Card Figure 2 - Typical Application of the ZL30131 11 Zarlink Semiconductor Inc. Package Code c Zarlink Semiconductor 2005 All rights reserved. ISSUE ACN DATE APPRD. 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It is the user’s responsibility to fully determine the performance and suitability of any equipment using such information and to ensure that any publication or data used is up to date and has not been superseded. Manufacturing does not necessarily include testing of all functions or parameters. These products are not suitable for use in any medical products whose failure to perform may result in significant injury or death to the user. All products and materials are sold and services provided subject to Zarlink’s conditions of sale which are available on request. Purchase of Zarlink’s I2C components conveys a license under the Philips I2C Patent rights to use these components in and I2C System, provided that the system conforms to the I2C Standard Specification as defined by Philips. Zarlink, ZL, the Zarlink Semiconductor logo and the Legerity logo and combinations thereof, VoiceEdge, VoicePort, SLAC, ISLIC, ISLAC and VoicePath are trademarks of Zarlink Semiconductor Inc. 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