ZL30136GGG2

ZL30136 GbE and Telecom Rate Network Interface Synchronizer Short Form Data Sheet July 2009 Features Ordering Information • Provides synchronous clocks for network interface cards that support synchronous Ethernet (SyncE) in addition to telecom interfaces (T1/E1, DS3/E3, etc.) • Supports the requirements of ITU-T G.8262 for Synchronous Ethernet equipment slave clocks (EEC option 1 and 2) • Synchronizes to telecom reference clocks (2 kHz, N*8 kHz up to 77.76 MHz) or to Ethernet reference clocks (25 MHz, 50 MHz, 62.5 MHz, 125 MHz, and 155.52 MHz) • Generates Ethernet clocks (12.5 MHz, 25 MHz, 50 MHz, 62.5 MHz, or 125 MHz) • Programmable telecom synthesizer generates clock frequencies of any multiple of 8 kHz up to 100 MHz ZL30136GGG 64 Pin CABGA ZL30136GGG2 64 Pin CABGA* *Pb Free Tin/Silver/Copper Trays Trays -40°C to +85°C • Supports automatic hitless reference switching and short term holdover during loss of reference inputs • DPLL can be configured to provide synchronous or asynchronous clock outputs • Configurable through a serial interface (SPI or I2C) • Supports IEEE 1149.1 JTAG Boundary Scan Applications • Selectable loop bandwidth of 14 Hz, 28 Hz, 890 Hz, or 0.1 Hz • GbE network interface cards that support synchronous Ethernet (SyncE) • Generates several styles of output frame pulses with selectable pulse width, polarity and frequency • GPON ONT/ONU • Provides 3 sync inputs for output frame pulse alignment • T1/E1 line cards • DS3/E3 line cards • Flexible input reference monitoring automatically disqualifies references based on frequency and phase irregularities osci ref0 ref1 ref2 osco /N1 /N2 Ethernet APLL ref eth_clk DPLL sync0 sync1 sync2 Programmable Synthesizer N*8kHz sync mode lock I2C/SPI hold JTAG Figure 1 - Functional Block Diagram 1 Zarlink Semiconductor Inc. Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright 2008-2009, Zarlink Semiconductor Inc. All Rights Reserved. p_clk p_fp ZL30136 1.0 Short Form Data Sheet Change Summary Changes from September 2008 issue to July 2009 issue. Page 3 Item Change p_clk maximum clock frequency Changed max frequency of the P0 clock from 77.76 MHz to 100 MHz. Changes from February 2008 issue to September 2008 issue. Page Item Change Ordering Information Corrected ordering part number. 2 Zarlink Semiconductor Inc. ZL30136 Short Form Data Sheet Pin Description Pin # Name I/O Type Description Input Reference B1 A3 B4 ref0 ref1 ref2 Iu Input References 2:0 (LVCMOS, Schmitt Trigger). These input references are available to the DPLL for synchronizing output clocks. All three input references can lock to 2 kHz or any multiple of 8 kHz up to 77.76 MHz including 25 MHz and 50 MHz. Input ref0 and ref1 have additional configurable pre-dividers allowing input frequencies of 62.5 MHz, 125 MHz, and 155.52 MHz. These pins are internally pulled up to Vdd. A1 A2 A4 sync0 sync1 sync2 Iu Frame Pulse Synchronization References 2:0 (LVCMOS, Schmitt Trigger). These are optional frame pulse synchronization inputs associated with input references 0, 1 and 2. These inputs accept frame pulses in a clock format (50% duty cycle) or a basic frame pulse format with minimum pulse width of 5 ns. These pins are internally pulled up to Vdd. Output Clocks and Frame Pulses D8 eth_clk O Network Output Clock (LVCMOS). This output can be configured to provide any of the Ethernet clock rates: 12.5 MHz, 25 MHz, 50 MHz, 62.5 MHz, or 125 MHz. G8 p_clk O Programmable Telecom Synthesizer - Output Clock (LVCMOS). This output can be configured to provide telecom clock rates in multiples of 8 kHz up to 100 MHz. The default frequency for this output is 2.048 MHz. G7 p_fp O Programmable Telecom Synthesizer - Output Frame Pulse (LVCMOS). This output can be configured to provide virtually any style of output frame pulse. The default frequency for this frame pulse output is 8 kHz. G5 rst_b I Reset (LVCMOS, Schmitt Trigger). A logic low at this input resets the device. To ensure proper operation, the device must be reset after power-up. Reset should be asserted for a minimum of 300 ns. B2 mode Iu DPLL Mode Select (LVCMOS, Schmitt Trigger). During reset, the level on this pin determines the default mode of operation for DPLL (Normal=0 or Freerun=1). After reset, the mode of operation can be controlled directly with this pin, or by accessing the dpll_modesel register (0x1F) through the serial interface. This pin is internally pulled up to Vdd. E1 lock O Lock Indicator (LVCMOS). This is the lock indicator pin for DPLL. This output goes high when the DPLL’s output is frequency and phase locked to the input reference. H1 hold O Holdover Indicator (LVCMOS). This pin goes high when the DPLL enters the holdover mode. I/B Clock for Serial Interface (LVCMOS). Serial interface clock. When i2c_en = 0, this pin acts as the sck pin for the serial interface. When i2c_en = 1, this pin acts as the scl pin (bidirectional) for the I2C interface. Control Status Serial Interface (SPI/I2C) C1 sck/scl 3 Zarlink Semiconductor Inc. ZL30136 Short Form Data Sheet Pin # Name I/O Type D2 si/sda I/B Serial Interface Input (LVCMOS). Serial interface data pin. When i2c_en = 0, this pin acts as the si pin for the serial interface. When i2c_en = 1, this pin acts as the sda pin (bidirectional) for the I2C interface. D1 so O Serial Interface Output (LVCMOS). Serial interface data output. When i2c_en = 0, this pin acts as the so pin for the serial interface. When i2c_en = 1, this pin is unused and should be left unconnected. C2 cs_b/asel0 Iu Chip Select for SPI/Address Select 0 for I2C (LVCMOS). When i2c_en = 0, this pin acts as the chip select pin (active low) for the serial interface. When i2c_en = 1, this pin acts as the asel0 pin for the I2C interface. E2 int_b O Interrupt Pin (LVCMOS). Indicates a change of device status prompting the processor to read the enabled interrupt service registers (ISR). This pin is an open drain, active low and requires an external pulled-up to Vdd. H2 i2c_en Iu I2C Interface Enable (LVCMOS). If set high, the I2C interface is enabled, if set low the SPI interface is enabled. Internally pull-up to Vdd. Description APLL Loop Filter A5 apll_filter A External Analog PLL Loop Filter Terminal. B5 filter_ref0 A Analog PLL External Loop Filter Reference. C5 filter_ref1 A Analog PLL External Loop Filter Reference. JTAG and Test G4 tdo O Test Serial Data Out (Output). JTAG serial data is output on this pin on the falling edge of tck. This pin is held in high impedance state when JTAG scan is not enabled. G2 tdi Iu Test Serial Data In (Input). JTAG serial test instructions and data are shifted in on this pin. This pin is internally pulled up to Vdd. If this pin is not used then it should be left unconnected. G3 trst_b Iu Test Reset (LVCMOS). Asynchronously initializes the JTAG TAP controller by putting it in the Test-Logic-Reset state. This pin should be pulsed low on powerup to ensure that the device is in the normal functional state. This pin is internally pulled up to Vdd. If this pin is not used then it should be connected to GND. H3 tck I Test Clock (LVCMOS): Provides the clock to the JTAG test logic. If this pin is not used then it should be pulled down to GND. F2 tms Iu Test Mode Select (LVCMOS). JTAG signal that controls the state transitions of the TAP controller. This pin is internally pulled up to VDD. If this pin is not used then it should be left unconnected. Master Clock H4 osci I Oscillator Master Clock Input (LVCMOS). This input accepts a 20 MHz reference from a clock oscillator (XO) or crystal XTAL. The stability and accuracy of the clock at this input determines the free-run accuracy and the long term holdover stability of the output clocks. H5 osco O Oscillator Master Clock Output (LVCMOS). This pin must be left unconnected when the osci pin is connected to a clock oscillator. 4 Zarlink Semiconductor Inc. ZL30136 Pin # Name I/O Type Short Form Data Sheet Description Miscellaneous F5 IC Internal Connection. Leave unconnected. H6 IC Internal Connection. Connect to ground. A7 B3 B8 D7 H7 NC No Connection. Leave unconnected. Power and Ground C3 C8 E8 F6 F8 G6 H8 VDD P P P P P P P Positive Supply Voltage. +3.3VDC nominal. E6 F3 VCORE P P Positive Supply Voltage. +1.8VDC nominal. B7 C4 AVDD P P Positive Analog Supply Voltage. +3.3VDC nominal. B6 C7 F1 AVCORE P P P Positive Analog Supply Voltage. +1.8VDC nominal. D3 D4 D5 D6 E3 E4 E5 E7 F4 F7 VSS G G G G Ground. 0 Volts. A6 A8 C6 G1 AVSS G G G G Analog Ground. 0 Volts. IId Iu OAPG- Input Input, Internally pulled down Input, Internally pulled up Output Analog Power Ground 5 Zarlink Semiconductor Inc. ZL30136 2.0 Short Form Data Sheet Pin Diagram TOP VIEW 1 1 2 3 4 5 6 7 8 sync0 sync1 ref1 sync2 apll_filter AVSS NC AVSS ref0 mode NC ref2 filter_ref0 AVCORE AVDD NC sck/ scl cs_b/ asel0 VDD AVDD filter_ref1 AVSS AVCORE VDD so si/ sda VSS VSS VSS VSS NC eth_clk lock int_b VSS VSS VSS VCORE VSS VDD AVCORE tms VCORE VSS IC VDD VSS VDD AVSS tdi trst_b tdo rst_b VDD p_fp p_clk hold i2c_en tck osci osco IC NC VDD A B C D E F G H 1 - A1 corner is identified by metallized markings. 6 Zarlink Semiconductor Inc. ZL30136 3.0 Short Form Data Sheet High Level Overview The ZL30136 GbE and Telecom Rate Network Interface Synchronizer is a highly integrated device that provides timing for network interface cards. The DPLL is capable of locking to one of three input references and provides standard Ethernet clock rates for synchronizing Ethernet PHYs, and a highly programmable clock and frame pulse for telecom interfaces such as T1/E1, DS3/E3, etc... This device is ideally suited for systems with network interface cards that are synchronized to a centralized telecom backplane. The ZL30136 synchronizes to backplane clocks and generates a synchronized and jitter attenuated Ethernet clock and a PDH clock. A typical application is shown in Figure 2. In this application, the ZL30136 translates a 19.44 MHz clock from the telecom backplane to an Ethernet clock rate for the GbE PHY and filters the jitter to ensure compliance with related clock standards. A programmable synthesizer provides PDH clocks with multiples of 8 kHz for generating PDH interface clocks. The ZL30136 allows easy integration of Ethernet line rates with today’s telecom backplanes. BITS A BITS B Central Timing Card Central Timing Card XOVER DPLL DPLL ZL30121 ZL30121 19.44 MHz 19.44 MHz A B Telecom Backplane A A B B ZL30136 N*8k ZL30136 DPLL DPLL APLL APLL N*8k GbE PHY 1.544 MHz 125 MHz 1.544 MHz GbE Line Card 25 MHz GbE PHY GbE Line Card Figure 2 - Typical Application of the ZL30136 7 Zarlink Semiconductor Inc. c Zarlink Semiconductor 2005 All rights reserved. ISSUE ACN DATE APPRD. Previous package codes Package Code For more information about all Zarlink products visit our Web Site at www.zarlink.com Information relating to products and services furnished herein by Zarlink Semiconductor Inc. or its subsidiaries (collectively “Zarlink”) is believed to be reliable. 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This publication is issued to provide information only and (unless agreed by Zarlink in writing) may not be used, applied or reproduced for any purpose nor form part of any order or contract nor to be regarded as a representation relating to the products or services concerned. The products, their specifications, services and other information appearing in this publication are subject to change by Zarlink without notice. No warranty or guarantee express or implied is made regarding the capability, performance or suitability of any product or service. Information concerning possible methods of use is provided as a guide only and does not constitute any guarantee that such methods of use will be satisfactory in a specific piece of equipment. It is the user’s responsibility to fully determine the performance and suitability of any equipment using such information and to ensure that any publication or data used is up to date and has not been superseded. Manufacturing does not necessarily include testing of all functions or parameters. These products are not suitable for use in any medical products whose failure to perform may result in significant injury or death to the user. All products and materials are sold and services provided subject to Zarlink’s conditions of sale which are available on request. Purchase of Zarlink’s I2C components conveys a license under the Philips I2C Patent rights to use these components in and I2C System, provided that the system conforms to the I2C Standard Specification as defined by Philips. Zarlink, ZL, the Zarlink Semiconductor logo and the Legerity logo and combinations thereof, VoiceEdge, VoicePort, SLAC, ISLIC, ISLAC and VoicePath are trademarks of Zarlink Semiconductor Inc. TECHNICAL DOCUMENTATION - NOT FOR RESALE