ZL30145GGG

ZL30145 SyncE (10 GbE) SONET/SDH Rate Conversion and Jitter Attenuator PLL Short Form Data Sheet July 2009 Features Ordering Information • Can be used in systems to support the requirements of ITU-T G.8262 for synchronous Ethernet Equipment slave Clocks (EEC option 1 and 2) • Meets jitter generation requirements of Telcordia GR-253-CORE for OC-192, OC-48, OC-12 and OC-3 rates ZL30145GGG 64 Pin CABGA Trays ZL30145GGG2 64 Pin CABGA* Trays *Pb Free Tin/Silver/Copper -40oC to +85oC • Configurable through a serial interface (SPI or I2C) • Meets jitter generation requirements of ITU-T G.813 for STM-64, STM-16, STM-4 and STM-1 rates • DPLL can be configured to provide synchronous or asynchronous clock outputs • Synchronizes to standard telecom or Ethernet clock and provides jitter filtered output clock for SONET/SDH and Synchronous Ethernet line cards • Supports IEEE 1149.1 JTAG Boundary Scan • Synchronizes to telecom reference clocks (2 kHz, N*8 kHz up to 77.76 MHz, 155.52 MHz) or to Ethernet reference clocks (25 MHz, 50 MHz, 62.5 MHz, 125 MHz) • Generates standard SONET/SDH clock rates (e.g., 19.44 MHz, 38.88 MHz, 77.76 MHz, 155.52 MHz, 622.08 MHz) or Ethernet clock rates (e.g., 25 MHz, 50 MHz, 125 MHz, 156.25 MHz, 312.5 MHz) for synchronizing Ethernet PHYs • Selectable loop bandwidth of 14 Hz, 28 Hz, or 890 Hz osci ref Applications lock ITU-T G.8262 Line Cards which support 1 GbE and 10 GbE interfaces • SONET line cards up to OC-192 • SDH line cards up to STM-64 osco SONET/SDH/ Ethernet APLL ref DPLL /N • I2C/SPI hold diff apll_clk JTAG Figure 1 - Simplified Functional Block Diagram 1 Zarlink Semiconductor Inc. Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright 2009, Zarlink Semiconductor Inc. All Rights Reserved. ZL30145 1.0 Short Form Data Sheet High Level Overview The ZL30145 is a highly integrated device that provides timing for line cards. The DPLL automatically locks to one input reference and provides two synchronized output clocks for synchronizing SONET/SDH and Synchronous Ethernet line cards. The ZL30145 has a on-chip digital phase-locked loop (DPLL) designed to provide rate conversion and jitter attenuation for Synchronous Ethernet, (SyncE), Synchronous Digital Hierarchy (SDH) and Synchronous Optical Network (SONET) networking equipment. The ZL30145 generates very low jitter clocks that meet the jitter requirements of ITU-T G.8262, Telcordia GR-253-CORE OC-48, OC-12, OC-3, OC-1 rates and ITU-T G.813 STM16, STM-4 and STM-1 rates. 2 Zarlink Semiconductor Inc. c Zarlink Semiconductor 2005 All rights reserved. ISSUE ACN DATE APPRD. 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