ZL30146GGG2

ZL30146 SyncE SONET/SDH Line Card PLL Short Form Data Sheet July 2009 Features • Ordering Information Synchronizes to standard telecom or Ethernet backplane clocks and provides jitter filtered output clocks for SONET/SDH, PDH and Ethernet network interface cards ZL30146GGG 64 Pin CABGA Trays ZL30146GGG2 64 Pin CABGA* Trays *Pb Free Tin/Silver/Copper • Supports the requirements of ITU-T G.8262 for synchronous Ethernet Equipment slave Clocks • Meets the SONET/SDH jitter generation requirements up to OC-192/STM-64 • • Two independent DPLLs provides timing for the transmit path (backplane to line rate) and the receive path (recovered line rate to backplane) Programmable output synthesizer to generate telecom clock frequencies from any multiple of 8 kHz up to 100 MHz (e.g., T1/E1, DS3/E3) • Generates several styles of output frame pulse with selectable pulse width, polarity, and frequency • Configurable input to output delay and output to output phase alignment • Configurable through a serial interface (SPI or I2C) • DPLLs can be configured to provide synchronous or asynchronous clock outputs • -40oC to +85oC Synchronizes to telecom reference clocks (2 kHz, N*8 kHz up to 77.76 MHz, 155.52 MHz) or to Ethernet reference clocks (25 MHz, 50 MHz, 62.5 MHz, 125 MHz) • Selectable loop bandwidth of 14 Hz, 28 Hz, 890 Hz, 3.5 Hz, 1.7 Hz, or 0.1 Hz • Supports automatic hitless reference switching and short term holdover during loss of reference inputs • Applications Generates standard SONET/SDH clock rates (e.g., 19.44 MHz, 38.88 MHz, 77.76 MHz, 155.52 MHz, 622.08 MHz) or Ethernet clock rates (e.g., 25 MHz, 50 MHz, 125 MHz, 156.25 MHz, 312.5 MHz) for synchronizing Ethernet PHYs osci • ITU-T G.8262 Line Cards which support 1 GbE and 10 GbE interfaces • SONET/SDH line cards up to OC-192/STM-64 osco ref0 ref1 ref2 ref3 ref4 ref m Rx DPLL Program m able Synthesizer N*8kHz p_clk p_fp Input Ports ref n /sync n sync0 Tx DPLL Ethernet/ SONET APLL Ref/Sync Monitors m ode hold lock I2C/SPI JTAG Figure 1 - Functional Block Diagram 1 Zarlink Semiconductor Inc. Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright 2009, Zarlink Semiconductor Inc. All Rights Reserved. diff apll_clk ZL30146 1.0 Short Form Data Sheet Functional Description The ZL30146 OC-192/STM-64 PDH/SONET/SDH/Synchronous Ethernet Network Interface Synchronizer is a highly integrated device that provides timing for both PDH/SONET/SDH and Ethernet network interface cards. A functional block diagram is shown in Figure 1. This device is ideally suited for designs that require both a transmit timing path (backplane to PHY) and a receive timing path (PHY to backplane). Each path is controlled with separate DPLLs (Tx DPLL, Rx DPLL) which are both independently configurable through the serial interface (SPI or I2C). A typical application of the ZL30146 is shown in Figure 2. In this application, the ZL30146 translates the 19.44 MHz clock from the telecom rate backplane (system timing bus), translates the frequency to 622.08 MHz or 156.25 MHz for the PHY Tx clock, and filters the jitter to ensure compliance with the related standards. On the receive path, the Rx DPLL and the programmable synthesizer translate the line recovered clock (8 kHz or 25 MHz) from the PHY to the 19.44 MHz telecom backplane (line recovered timing) for the central timing cards. The ZL30146 allows easy integration of Ethernet line rates with today’s telecom backplanes. B IT S A C e n tra l T im in g C a rd B IT S B S P ZL30142 ZL30142 XO VER DPLL P C e n tra l T im in g C a rd P S S DPLL 1 9 .4 4 M H z S 1 9 .4 4 M H z P L in e R e c o v e r e d T im in g A P T e le c o m B a c k p la n e S B S y s te m T im in g B u s 1 9 .4 4 M H z P ro g S yn th A B A B 1 9 .4 4 M H z ZL30146 ZL30146 Tx DPLL Tx DPLL Rx DPLL P ro g S y n th Rx DPLL APLL APLL 6 2 2 .0 8 M H z 8 kHz 1 5 6 .2 5 M H z PHY 25 M Hz PHY O C -1 9 2 L in e C a rd 10G bE L in e C a rd Figure 2 - Typical Application of the ZL30146 2 Zarlink Semiconductor Inc. c Zarlink Semiconductor 2005 All rights reserved. ISSUE ACN DATE APPRD. Previous package codes Package Code For more information about all Zarlink products visit our Web Site at www.zarlink.com Information relating to products and services furnished herein by Zarlink Semiconductor Inc. or its subsidiaries (collectively “Zarlink”) is believed to be reliable. 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