ZL30158
SyncE and Telecom Rate Clock Translator
Short Form Data Sheet
January 2012
Features
Ordering Information
•
Synchronizes to any Telecom (N * 8 kHz) or any
Synchronized Ethernet (SyncE) frequency.
•
Generates any Telecom or SyncE frequency
independent of the input frequency rate
•
•
•
ZL30158GGG
ZL30158GGG2
64 Pin LBGA
64 Pin LBGA*
Trays
Trays
*Pb Free Tin/Silver/Copper
-40oC to +85oC
Uses proprietary DPLL technology to guarantee a
stable synchronization path over any combination
of input and output ratios and frequencies
Provides input reference jitter filtering with
programmable loop bandwidth in the range of
14 Hz to 896 Hz
Supports two input references, each configurable
as single ended LVCMOS (up to 177.5 MHz) or
differential LVPECL (up to 750 MHz)
•
Operates from a single crystal resonator or crystal
oscillator
•
Configurable using a simple SPI/I2C interface
Applications
•
Clock Generation for Physical Line Interface:
•
Automatic hitless reference switching and stand-by
mode on reference fail
•
Synchronous Ethernet, 10 GBASE-R and
10 GBASE-W
•
Digital PLL (DPLL) and high speed clock synthesis
engine for generating high speed PHY clocks
•
SONET/SDH, OC-192/OC-48
•
Provides four high performance differential LVPECL
outputs with maximum speed up to 750 MHz with
jitter below 0.7 psec RMS
•
100 BaseX, GE, Fibre channel
•
•
Provides 2 high performance single ended
LVCMOS outputs with maximum speed of
177.5 MHz with jitter below 1.3 psec RMS
Clock Generation and Distribution for back plane
Interface:
•
TDM, Telecom Bus, Utopia, SBI
•
XAUI
Figure 1 - Functional Block Diagram
1
Copyright 2011, Microsemi Corporation. All Rights Reserved.
ZL30158
Mechanical Drawing
2
Microsemi Corporation
Short Form Data Sheet
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ZL30158
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