ZL30163GDG2003M

ZL30163 Network Synchronization Clock Translator Short Form Data Sheet May 2013 Features • Fully compliant SEC (G.813) and EEC (G.8262) flexible rate conversion digital phase locked loop (DPLL) • Two programmable DPLLs/Numerically Controlled Oscillators (NCOs) synchronize to any clock rate from 1 Hz to 750 MHz • Four programmable synthesizers generate any clock rate from 1 Hz to 750 MHz with maximum jitter below 0.62 ps RMS • Flexible two-stage architecture translates between arbitrary data rates, line coding rates and FEC rates • DPLLs filter jitter from 0.1 mHz up to 1 kHz • Automatic hitless reference switching and digital holdover on reference fail • Nine input references configurable as single ended or differential and two single ended input references • Ordering Information ZL30163GDG2 144 Pin LBGA Trays Pb Free Tin/Silver/Copper -40oC to +85oC Package Size: 13 x 13 mm Programmable DPLLs can synchronize to sync pulse and sync pulse/clock pair • Eight LVPECL outputs and eight LVCMOS outputs • Operates from a single crystal resonator or clock oscillator • Field programmable via the SPI/I2C interface Applications Any input reference can be fed with sync (frame pulse) or clock Osci Osco • • SyncE/SONET/SDH Timing Cards • Synchronous Ethernet, 10 GBASE-R and 10 GBASE-W • SONET/SDH, Fibre Channel, XAUI ZL30163 Master Clock Ref0 Diff / Single Ended Fr0= Br0*Kr0*Mr0/Nr0 Ref1 Diff / Single Ended Fr1= Br1*Kr1*Mr1/Nr1 Ref2 Diff / Single Ended Fr2= Br2*Kr2*Mr2/Nr2 Ref3 Diff / Single Ended Fr3= Br3*Kr3*Mr3/Nr3 Ref4 Diff / Single Ended Fr4= Br4*Kr4*Mr4/Nr4 Ref5 Diff / Single Ended Fr5= Br5*Kr5*Mr5/Nr5 Ref6 Diff / Single Ended Fr6= Br6*Kr6*Mr6/Nr6 Ref7 Diff / Single Ended Fr7= Br7*Kr7*Mr7/Nr7 Ref8 Diff / Single Ended Fr8= Br8*Kr8*Mr8/Nr8 Ref9 Single Ended Fr9= Br9*Kr9*Mr9/Nr9 Ref10 Single Ended Fr10= Br10*Kr10*Mr10/Nr10 Clock Generator 0 Synthesizer 0 Fs= Bs0*Ks0*16*Ms0/Ns0 Clock Generator 1 Synthesizer 1 Fs= Bs1*Ks1*16*Ms1/Ns1 DPLL0/NCO0 Select Loop band., Phase slope limit DPLL1/NCO1 Select Loop band., Phase slope limit Clock Generator 2 Synthesizer 2 Fs= Bs2*Ks2*16*Ms2/Ns2 Clock Generator 3 State Machine JTAG Reference Monitors JTAG pwr_b Configuration and Status GPIO Synthesizer 3 Fs= Bs3*Ks3*16*Ms3/Ns3 SPI / I2C Figure 1 - Functional Block Diagram 1 Copyright 2013, Microsemi Corporation. All Rights Reserved. Div A LVPECL hpdiff0_p/n Div B LVPECL hpdiff1_p/n Div C LVCMOS hpoutclk0 Div D LVCMOS hpoutclk1 Div A LVPECL hpdiff2_p/n Div B LVPECL hpdiff3_p/n Div C LVCMOS hpoutclk2 Div D LVCMOS hpoutclk3 Div A LVPECL hpdiff4_p/n Div B LVPECL hpdiff5_p/n Div C LVCMOS hpoutclk4 Div D LVCMOS hpoutclk5 Div A LVPECL hpdiff6_p/n Div B LVPECL hpdiff7_p/n Div C LVCMOS hpoutclk6 Div D LVCMOS hpoutclk7 ZL30163 1.0 Short Form Data Sheet Pin Diagram TOP VIEW 4 6 7 8 osco_1V8 VDD2 osco_3V3 osci_3V3 VSS osci_1V8 VSS XOin VDD5 VSS VSS VCORE1 VSS hpoutclk0 hpoutclk1 VSS VDD9 VDD10 VSS 1 2 3 hpdiff0_p VDD0 NC VDD1 hpdiff0_n VSS NC hpdiff1_p hpdiff1_n VDD7 1 5 9 10 11 VDD3 NC VDD4 VCORE0 VSS NC VSS VSS VSS VSS VDD6 VSS VSS VSS hpoutclk3 hpoutclk2 VSS VSS VSS VSS VSS VDD11 12 A hpdiff2_p B hpdiff2_n C hpdiff3_n hpdiff3_p D VSS VDD8 E NC IC1 NC F NC trst_b hpoutclk4 hpoutclk5 VSS VSS VSS VSS hpoutclk6 hpoutclk7 pwr_b NC tdi tdo tms VSS VSS VSS VSS VSS VDD12 gpio1 gpio0 IC2 hpdiff4_p hpdiff4_n tck VSS VSS VSS VSS VSS VCORE2 gpio2 hpdiff6_n hpdiff6_p VSS gpio4 VSS VSS VSS VSS VSS VCORE3 gpio3 VSS VDD14 hpdiff5_n gpio5 gpio6 VSS VCORE4 cs_b_asel0 sck_scl si_sda so_asel1 hpdiff7_n hpdiff7_p G H J VDD13 K hpdiff5_p L VDD15 VSS ref1_p ref1_n ref3_p ref3_n ref5_p ref5_n ref6_n ref8_p ref8_n ref10 VCORE5 VSS ref0_p ref0_n ref2_p ref2_n ref4_p ref4_n ref6_p ref7_p ref7_n ref9 M 1 - A1 corner is identified by metallized markings. Figure 2 - Package Description 2 Microsemi Corporation ZL30163 2.0 Short Form Data Sheet Pin Description All device inputs and outputs are LVCMOS unless it is specifically stated to be differential. For the I/O column, there are digital inputs (I), digital outputs (O), analog inputs (A-I) and analog outputs (A-O). Ball # Name I/O Description M3 M4 L3 L4 M5 M6 L5 L6 M7 M8 L7 L8 M9 L9 M10 M11 L10 L11 ref0_p ref0_n ref1_p ref1_n ref2_p ref2_n ref3_p ref3_n ref4_p ref4_n ref5_p ref5_n ref6_p ref6_n ref7_p ref7_n ref8_p ref8_n I Input References 0 to 8. Input reference sources used for synchronization. The positive and negative pair of these inputs accepts a differential input signal. The refx_p input terminal accepts a CMOS input reference. These inputs can be used as an external feedback input. M12 L12 ref9 ref10 I Input Reference Maximum frequency limit on single ended inputs is 177.5 MHz, and 750 MHz on differential inputs. Input References 9 and 10. Input reference sources used for synchronization. These inputs are the same as inputs 0 to 8, but only single ended. These inputs can be used as an external feedback input. Maximum frequency limit is 177.5 MHz. Output Clocks D3 D4 D10 D9 F3 F4 F9 F10 hpoutclk0 hpoutclk1 hpoutclk2 hpoutclk3 hpoutclk4 hpoutclk5 hpoutclk6 hpoutclk7 O High Performance Output Clocks 0 to 7. These outputs can be configured to provide any one of the single ended high performance clock outputs. Maximum frequency limit on single ended LVCMOS outputs is 177.5 MHz. Table 1 - Pin Description 3 Microsemi Corporation ZL30163 Short Form Data Sheet Ball # Name I/O Description A1 B1 C1 C2 A12 B12 C12 C11 H1 H2 K1 K2 H12 H11 K12 K11 hpdiff0_p hpdiff0_n hpdiff1_p hpdiff1_n hpdiff2_p hpdiff2_n hpdiff3_p hpdiff3_n hpdiff4_p hpdiff4_n hpdiff5_p hpdiff5_n hpdiff6_p hpdiff6_n hpdiff7_p hpdiff7_n O High Performance Differential Output Clocks 0 to 7 (LVPECL). These outputs can be configured to provide any one of the available high performance differential output clocks. Maximum frequency limit on differential outputs is 750 MHz. Control and Status F11 pwr_b I Power-on Reset. A logic low at this input resets the device. To ensure proper operation, the device must be reset after power-up. The pwr_b pin should be held low for 2 ms after all power supplies are stabilized. This pin is internally pulled-up to VDD. User can access device registers either 125 ms after pwr_b goes high, or after bit 7 in register at address 0x000 goes high (which can be determined by polling). Table 1 - Pin Description (continued) 4 Microsemi Corporation ZL30163 Ball # Name I/O G11 G10 H10 J10 J3 K3 K4 gpio0 gpio1 gpio2 gpio3 gpio4 gpio5 gpio6 I/O Short Form Data Sheet Description General Purpose Input and Output pins. These are general purpose I/O pins. Example GPIO functions include: • DPLL lock indicators • DPLL holdover indicators • Reference fail indicators • Reference select control or monitor • Differential output clock enable • High performance LVCMOS outputs enable • Host Interrupt Output to flag status changes All GPIO functions are listed in 5.2, “GPIO Configuration“. Pins 5:0 are internally pulled down to GND and pin 6 is internally pulled up to VDD. Unused GPIO pins can be left unconnected. After power on reset, device GPIO[0,1,3] configure basic device function. GPIO3 sets I2C or SPI control mode, GPIO[1,0] sets master clock rate selection. The GPIO[0,1,3] pins must be either pulled low or high with an external 1 k resistor for their assigned functions at reset; or they must be driven low or high for 125 ms after reset, and released and then used for normal GPIO functions. The GPIO4 pin must be either pulled low with an external 1 k resistor; or it must be driven low for 125 ms after reset, and then released and used for normal GPIO functions. GPIO[5,6] are not used during power up. Host Interface K8 sck_scl I/O Clock for Serial Interface. Provides clock for serial micro-port interface. This pin is also the serial clock line (SCL) when the host interface is configured for I2C mode. As an input this pin is internally pulled up to VDD. K9 si_sda I/O Serial Interface Input. The input serial data stream holds the access command, the address and the write data bits. This pin is also the serial data line (SDA) when the host interface is configured for I2C mode. This pin is internally pulled up to VDD. K10 so_asel1 I/O Serial Interface Output. As an output, the serial stream holds the read data bits. This pin is also a part of the I2C address select when the host interface is configured for I2C mode. K7 cs_b_asel0 I Chip Select for Serial Interface. As serial interface chip select, this is an active low signal. This pin is also a part of the I2C address select when the host interface is configured for I2C mode.This pin is internally pulled up to VDD. I Internal Connection. Connect this pin to GND. JTAG (IEEE 1149.1) and Test G12 IC2 E11 IC1 A-I/O Internal Connection. Leave unconnected. Table 1 - Pin Description (continued) 5 Microsemi Corporation ZL30163 Short Form Data Sheet Ball # Name I/O Description G2 tdo O Test Serial Data Out. JTAG serial data is output on this pin on the falling edge of tck. This pin is held in high impedance state when JTAG scan is not enabled. G1 tdi I Test Serial Data In. JTAG serial test instructions and data are shifted in on this pin. This pin is internally pulled up to VDD. If this pin is not used then it should be left unconnected. F2 trst_b I Test Reset. Asynchronously initializes the JTAG TAP controller by putting it in the Test-Logic-Reset state. This pin should be held low or pulsed low on power-up to ensure that the device is in the normal functional state. This pin is internally pulled up to VDD. If this pin is not used then it should be connected to GND. H3 tck I Test Clock. Provides the clock for the JTAG test logic. This pin is internally pulled up to VDD. If this pin is not used then it should be connected to GND. G3 tms I Test Mode Select. JTAG signal that controls the state transitions of the TAP controller. This pin is internally pulled up to VDD. If this pin is not used then it should be left unconnected. Master Clock Note: The osci_1V8/osco_1V8 pins are preferred to connect a crystal to the device. The XOin pin is preferred to connect a crystal oscillator (XO) to the device. A7 osco_3V3 A-O 3.3V Crystal Master Clock Output. For the alternative connection method for a crystal, the crystal is connected from this pin to osci_3V3. Not suitable for driving other devices. For clock oscillator operation or the use of a crystal between osci_1V8 and osco_1V8, this pin should be left unconnected. A8 osci_3V3 A5 osco_1V8 B5 osci_1V8 I 1.8V Crystal Master Clock Input. For the primary connection method for a crystal, the crystal is connected from this pin to osco_1V8. For clock oscillator operation or the use of a crystal between osci_3V3 and osco_3V3, this pin should be grounded. B7 XOin I XO Master Clock Output. For clock oscillator operation, this pin is connected to the output of the oscillator. For crystal operation using either method, this pin should be grounded. I 3.3V Crystal Master Clock Input. For the alternative connection method for a crystal, the crystal is connected from this pin to osco_3V3. For clock oscillator operation or the use of a crystal between osci_1V8 and osco_1V8, this pin should be grounded. A-O 1.8V Crystal Master Clock Output. For the primary connection method for a crystal, the crystal is connected from this pin to osci_1V8. Not suitable for driving other devices. For clock oscillator operation or the use of a crystal between osci_3V3 and osco_3V3, this pin should be left unconnected. Power and Ground Table 1 - Pin Description (continued) 6 Microsemi Corporation ZL30163 Ball # Name B8 C6 H9 J9 K6 M1 VCORE0 VCORE1 VCORE2 VCORE3 VCORE4 VCORE5 A2 A4 A6 A9 A11 C3 C10 D1 D12 E2 E3 E10 G9 J1 J12 L1 VDD0 VDD1 VDD2 VDD3 VDD4 VDD5 VDD6 VDD7 VDD8 VDD9 VDD10 VDD11 VDD12 VDD13 VDD14 VDD15 I/O Short Form Data Sheet Description Positive Supply Voltage. +1.8VDC nominal. These pins should not be connected together on the board. Please refer to ZLAN-327 for recommendations Positive Supply Voltage. +3.3VDC nominal. These pins should not be connected together on the board. Please refer to ZLAN-327 for recommendations Table 1 - Pin Description (continued) 7 Microsemi Corporation ZL30163 Ball # Name B2 B4 B6 B9 B11 C4 C5 C7 C8 C9 D2 D11 E4 E9 G4 H4 H5 H6 H7 H8 J2 J4 J5 J6 J7 J8 J11 K5 L2 M2 D5 D6 D7 D8 E5 E6 E7 E8 F5 F6 F7 F8 G5 G6 G7 G8 VSS I/O Short Form Data Sheet Description Ground. 0 Volts. Table 1 - Pin Description (continued) 8 Microsemi Corporation ZL30163 Ball # Name A3 A10 B3 B10 E1 E12 F1 F12 NC I/O Short Form Data Sheet Description No Connect. These pins should be left open. Table 1 - Pin Description (continued) 9 Microsemi Corporation ZL30163 3.0 Mechanical Drawing 10 Microsemi Corporation Short Form Data Sheet Information relating to products and services furnished herein by Microsemi Corporation or its subsidiaries (collectively “Microsemi”) is believed to be reliable. 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