ZL30182LFF7

ZL30182 Dual-Channel Any-to-Any Clock Rate Translator Product Brief September 2015 Ordering Information Features  Two Independent Channels ZL30182LFG7 ZL30182LFF7  Three Input Clocks Per Channel 64 Pin LGA 64 Pin LGA Trays Tape and Reel Ni Au  Three inputs, two differential/CMOS, one CMOS Package size: 5 x 10 mm  Any input frequency from 1kHz to 1250MHz (1kHz to 300MHz for CMOS) -40C to +85C  Inputs continually monitored for activity and frequency accuracy  Outputs are CML or 2xCMOS, can interface to LVDS, LVPECL, HSTL, SSTL and HCSL  Automatic or manual reference switching  In 2xCMOS mode, the P and N pins can be different frequencies (e.g. 125MHz and 25MHz)  Low-Bandwidth DPLL Per Channel  Per-output supply pin with CMOS output voltages from 1.5V to 3.3V  Programmable bandwidth, 5Hz to 500Hz  Attenuates jitter up to several UI  Precise output alignment circuitry and peroutput phase adjustment  Freerun or holdover on loss of all inputs  Per-output enable/disable and glitchless start/stop (stop high or low)  Hitless reference switching  High-resolution holdover averaging  General Features  Digitally controlled phase adjustment  Automatic self-configuration at power-up from internal EEPROM; up to four configurations pin-selectable  Low-Jitter Fractional-N APLL and 3 Outputs Per Channel  Any output frequency from