ZL30236
Dual Channel Universal
Clock Generator
Data Sheet
March 2015
Features
•
Ordering Information
Generates clock signals at power-up per user
defined custom OTP (One Time Programmable)
configuration
•
Dynamically configurable via SPI/I2C interface and
volatile configuration registers
•
Two independently programmable clock generators
output any clock rate from 1 kHz to 750 MHz
•
Precision clock generators output clocks with jitter
below 0.7 ps RMS for 10 G PHYs
•
Operates from a single crystal resonator, clock
oscillator or voltage controlled oscillator
•
Supports programmable frequency offsets for clock
margining; or for use as a digitally controlled
oscillator
•
Eight LVPECL outputs; max rate 750 MHz
•
Four LVCMOS outputs; max rate 177.5 MHz
ZL30236GGG2
100 Pin LBGA*
11mmx11mm Trays
*Pb Free Tin/Silver/Copper
-40oC to +85oC
Applications
•
Timing for NPUs, FPGAs, Ethernet switches and
PCIe switches
•
Timing for 10 Gigabit CDRs, Rapid-IO, PCIe,
Serial MII, Star Fabric, Fibre Channel, XAUI
•
Processor clock, Processor bus clock, SDRAM
clock, DDR clock
Figure 1 - Functional Block Diagram
1
Copyright 2015, Microsemi Corporation. All Rights Reserved.
ZL30236
Data Sheet
Table of Contents
1.0 Pin Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.0 Pin Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.0 Application Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.0 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4.1 Frequency Synthesis Engine. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4.2 Dividers and Skew Management. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4.3 Output Multiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.4 Output Drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.5 Master Clock Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.6 Clock Oscillator and Crystal Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.7 Power Up/Down Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.8 Power Supply Filtering. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.9 Power on Reset and Initialization Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.10 Ultra Low Jitter Synthesizer Filter Components and Recommended Layout . . . . . . . . . . . . . . . . . . . . . 21
5.0 Configuration and Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
5.1 Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
5.1.1 Default Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
5.1.2 Custom OTP Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
5.1.3 SPI/I2C Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
5.2 Output Multiplexer Configuration and Programmability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
5.3 Synthesizers Configuration and Programmability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
5.4 Output Dividers and Skew Management Configuration and Programmability. . . . . . . . . . . . . . . . . . . . . . 22
5.5 Output Drivers configuration and Programmability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
5.6 GPIO Configuration and Programmability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
6.0 Host Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
6.1 Serial Peripheral Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
6.1.1 Least Significant Bit (LSB) First Transmission Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
6.1.2 Most Significant Bit (MSB) First Transmission Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
6.1.3 SPI Burst Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
6.1.4 I2C Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
7.0 Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
8.0 Detailed Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
9.0 AC and DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
10.0 Performance Characterization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
10.1 Output Clocks RMS Jitter Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
10.2 Output Clocks Cycle-to-Cycle Jitter Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
11.0 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
12.0 Mechanical Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
13.0 Package Markings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
13.1 100-pin BGA. Package Top Mark Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
2
Microsemi Corporation
ZL30236
Data Sheet
List of Tables
Table 1 - Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 2 - Master Clock Frequency Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 3 - Serial Interface Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 4 - Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 5 - Serial Peripheral Interface Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Table 6 - I2C Serial Microport Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Table 7 - Jitter Generation Specifications - HPDIFF Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Table 8 - Jitter Generation Specifications - HPOUT Outputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Table 9 - Jitter Generation Specifications - HPDIFF Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Table 10 - Thermal Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Table 11 - Package Marking Legend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
3
Microsemi Corporation
ZL30236
Data Sheet
List of Figures
Figure 1 - Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Figure 2 - Package Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 3 - Application Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 4 - Output Clock Muxing Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 5 - Terminating LVPECL Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 6 - Terminating AC coupled LVPECL Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 7 - Terminating LVCMOS Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 8 - Clock Oscillator Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 9 - Typical Power-Up Reset and Configuration Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 10 - APLL Filter Component Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 11 - Recommended Layout for Loop Filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 12 - Serial Interface Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 13 - Serial Peripheral Interface Functional Waveforms - LSB First Mode . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 14 - Serial Peripheral Interface Functional Waveforms - MSB First Mode . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 15 - Example of a Burst Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 16 - I2C Data Write Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 17 - I2C Data Read Protocol. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 18 - I2C 7-bit Slave Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 19 - I2C Data Write Burst Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 20 - I2C Data Read Burst Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 21 - Accessing Multi-byte Register Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 22 - Timing Parameter Measurement Voltage Levels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Figure 23 - Output Timing Referenced To hpclkout0/clkout0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Figure 24 - Serial Peripheral Interface Timing - LSB First Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Figure 25 - Serial Peripheral Interface Timing - MSB First Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Figure 26 - I2C Serial Microport Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Figure 27 - Non-customized Device Top Mark. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Figure 28 - Custom Factory Programmed Device Top Mark . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
4
Microsemi Corporation
ZL30236
Data Sheet
Change Summary
Below are the changes from the June 2012 issue to the March 2015 issue
Page
Item
Change
1
Ordering information
Removed ZL30236GGG (Leaded version) from the
ordering information
22
Custom OTP Configuration
Removed reference to ZLAN-301
80
13.0, “Package Markings“
Added section 13 for package markings
Below are the changes from the January 2012 issue to the June 2012 issue
Page
Item
Change
73
Output to Output Alignment
Added min/max values for tOUT2OUTD
33
and
59
Register 0xC6 - Chip_Revision_2
Updated chip_revision_2 register 0xC6 = 0x03
Below are the changes from the December 2011 issue to the January 2012 issue.
Page
Item
Change
29
Procedure for writing registers
Added a new procedure for updating registers
30
Time between two write accesses to
the same register
Changed 200ms to 8ms and added 0x0D to registers
not requiring wait time.
30
Reading from Sticky read Registers
Updated Sticky read procedure
34
Register 0x00 - id_reg
Updated Chip revision bits
31
Register 0x0D - Sticky_r_lock
Updated bit description
33,
59
Register 0xC6
Added chip_revision_2 register
Below are the changes from the July 2011 issue to the December 2011 issue.
Page
Item
Change
30
Reading from Sticky read Registers
Updated Sticky read procedure
34
Register 0x00 - id_reg
updated ready indication bit description
31,
35
Register 0x0D
Added register 0x0D
67
Register 0xF7
Updated spurs_suppression register description
Below are the changes from the June 2011 issue to the July 2011 issue.
5
Microsemi Corporation
ZL30236
Page
Data Sheet
Item
Change
Feature
OTP feature is added
1, 9,
14,
16,
73
All items related the maximum rate of
differential output clocks
The maximum rate is updated from 720 MHz to
750MHz
9,
10,
19,
20,
25,
34
All items related waiting time after
pwr_b pin goes high during reset
procedure
Waiting time after pwr_b pin goes high is changed from
30 ms to 50 ms
8,9
Pin diagram Figure-2 and Pin
description Table-1
Names for pin J1, J2, J9, J10,K1, K2, K9, and K10 are
changed from ’IC’ to ’NC’
14
Section 4.0
Updated for OTP feature
22
Section 5.0
•
Section 5.1, 5.1.1, 5.1.2, 5.1.3 and 5.1.4 are
updated for three configuration methods:Default
configuration, OTP configuration, and SPI/I2C
configuration
•
Original section 5.1.1, 5.1.2, 5.1.3, and 5.1.4 are
changed to section 5.2, 5.3, 5.4, and 5.5
1
29
Section 7.0
For page_register at address 0x7F, there is no waiting
time required between two write accesses.
31
Table-4
•
Table description is updated for OTP feature
•
Register 0x01, 0x0E and 0x0F are added
•
Heading of first column is changed from
“Page_Addr” to “Reg_Addr"
34
Section 8.0
Detailed description for new register 0x01, 0x0E, and
0x0F are added
45
Detailed Register Map
"Page_Address" is changed to "Register_Address" for
registers which addresses are from 0x80 to 0x91
46
Register synth0_post_div_C
Bit[15:0]: note added for odd post divider
48
Register synth0_post_div_D
Bit[15:0]: note added for odd post divider
51
Register synth1_post_div_C
Bit[15:0]: note added for odd post divider
53
Register synth1_post_div_D
Bit[15:0]: note added for odd post divider
69
DC Electrical Characteristics -Power
Core
71
DC Electrical Characteristics - High
Performance Outputs
Note added for differential output voltage when
differential frequency is higher than 720MHz
69
DC Electrical Characteristics
All "AVDD-IO" symbols are replaced with "AVDD"
77
Output Clocks Jitter Generation
Jitter measurement filter for 77.76MHz is changed
from "12kHz-5MHz" to "12kHz-20MHz"
• "Power for Each Synthesis Engine” is changed to
“Current for Each Synthesis Engine”
• “PSYN” is changed to “ISYN”
6
Microsemi Corporation
ZL30236
Page
78
Item
Change
Section 11.0
Note added for Tjmax
Data Sheet
Below are the changes from the January 2011 issue to the June 2011 issue.
Page
Item
Change
1
Ordering Information
Corrected package description in ordering information
to LBGA.
77
Section 10.1
The section was renamed to "Output Clocks RMS
Jitter Generation"
77
Section 10.2
Table 9 was created for cycle-to-cycle jitter generation
77
Section 12.0
Replaced drawing to reflect correct package
description.
Below are the changes from the November 2010 issue to the January 2011 issue.
Page
Item
Change
6
Figure 2
Names of pin B5, B6, H5, and H6 are changed from
AVcore to Vcore
10
Table 1
Names of pin B5, B6, H5, and H6 are changed from
AVcore to Vcore, and they are merged to the same
entry with pin D5, G5, and G6. Layout application note
is referred
23
6.1 Serial Peripheral Interface
SPI burst mode operation description is added
25
Figure 15
Example of a Burst Mode Operation is added
62
Table - Recommended Operating
Conditions
Row 2, AVcore is removed from the "Sym" column
66
Table - AC Electrical Characteristics*
- Outputs
Correct wrong row numbers
66
Table - AC Electrical Characteristics*
- Outputs
Row 2, clock duty cycle is changed from "43%-57%" to
"45%-55%"
66
Table - AC Electrical Characteristics*
- Outputs
Row 3, note "From 0.2AVDD-IO to 0.8AVDD-IO" is
removed
7
Microsemi Corporation
ZL30236
1.0
Data Sheet
Pin Diagram
1
1
2
3
4
5
6
7
8
9
10
hpdiff3_p
avss
filter1
avss
osco
osci
avss
filter2
avss
hpdiff7_p
hpdiff3_n
avss
filter1_ref
avdd
vcore
vcore
pwr_b
filter2_ref
avss
hpdiff7_n
hpdiff2_p
hpdiff2_n
avss
gpio5
at
vss
gpio0
avss
hpdiff6_n
hpdiff6_p
hpdiff1_p
hpdiff1_n
avdd
test_en
vcore
vdd_io
gpio11
avdd
hpdiff5_n
hpdiff5_p
hpdiff0_p
hpdiff0_n
avdd
gpio7
vss
vss
gpio8
avdd
hpdiff4_n
hpdiff4_p
gpio6
avdd
gpio4
so_asel1
vss
vss
gpio1
gpio3
avdd
sck_scl
hpoutclk1
hpoutclk0
gpio9
si_sda
vcore
vcore
gpio2
cs_b_asel0
hpoutclk2
hpoutclk3
vdd_io
avss
avss
tck
vcore
vcore
gpio10
avss
avss
vdd_io
NC
NC
tdo
IC
IC
IC
IC
tms
NC
NC
NC
NC
trst_b
IC
IC
IC
IC
tdi
NC
NC
A
B
C
D
E
F
G
H
J
K
1
- A1 corner is identified by metallized markings.
Figure 2 - Package Description
8
Microsemi Corporation
ZL30236
2.0
Data Sheet
Pin Description
All device inputs and output are LVCMOS unless it was specifically stated to be differential.
Ball #
Name
I/O
Description
G2
G1
G9
G10
hpoutclk0
hpoutclk1
hpoutclk2
hpoutclk3
O
High Performance Output Clock 0 to 3. This output can be configured
to provide any one of the single ended high performance clock outputs.
E1
E2
D1
D2
C1
C2
A1
B1
E10
E9
D10
D9
C10
C9
A10
B10
hpdiff0_p
hpdiff0_n
hpdiff1_p
hpdiff1_n
hpdiff2_p
hpdiff2_n
hpdiff3_p
hpdiff3_n
hpdiff4_p
hpdiff4_n
hpdiff5_p
hpdiff5_n
hpdiff6_p
hpdiff6_n
hpdiff7_p
hpdiff7_n
O
Output Clocks
Maximum frequency limit on single ended LVCMOS outputs is
177.5 MHz
High Performance Differential Output Clock 0 to 7 (LVPECL). This
output can be configured to provide any one of the available high
performance differential output clocks.
Maximum frequency limit on differential outputs is 750 MHz
Control and Status
B7
pwr_b
I
Power-on Reset. A logic low at this input resets the device. To ensure
proper operation, the device must be reset after power-up. The pwr_b
pin should be held low for 2 ms. Following a reset, the input reference
source and output clocks are phase aligned. This pin is internally pulledup to VDD. User can access device registers either 50 ms after
pwr_b goes high, or after bit 7 in register at address 0x00 goes high
which can be determined by polling the register at address 0x00.
Table 1 - Pin Description
9
Microsemi Corporation
ZL30236
Data Sheet
Ball #
Name
I/O
Description
C7
F7
G7
F8
F3
C4
F1
E4
E7
G3
H7
D7
gpio0
gpio1
gpio2
gpio3
gpio4
gpio5
gpio6
gpio7
gpio8
gpio9
gpio10
gpio11
I/O
General Purpose Input and Output pins. These are general purpose
pins managed by the internal processor based on device configuration.
Other status and control pins could be muxed to become part of the
available GPIO pins.
Recommended usage of GPIO include:
• Differential output clock enable (per output or as a bank of 2 or 4
outputs)
• High performance LVCMOS outputs enable
• Microport interface protocol I2C or SPI
• Master Clock frequency rate
Pins 5:0 are internally pulled down to GND and pins 11:6 are internally
pulled up to VDD.
If not used GPIO can be kept unconnected.
After power on reset, device GPIOs configure some of device basic
functions, GPIO[3] set I2C or SPI control mode, GPIO[1,0] set
master clock rate selection. The GPIO[0,1,3] pins must be either
pulled low or high with an external 1 K resistor as needed for their
assigned functions at reset; or they must be driven low or high for
50 ms after reset, and released and used for normal GPIO
functions.
The GPIO[4,5] pins must be either pulled low with external 1 K
resistors; or they must be driven low for 50 ms after reset, and then
released and used for normal GPIO functions.
Host Interface
F10
sck_scl
I/O
Clock for Serial Interface. Provides clock for serial micro-port interface.
This pin is also the serial clock line (SCL) when the host interface is
configured for I2C mode. As an input this pin is internally pulled up to
VDD.
G4
si_sda
I/O
Serial Interface Input. Serial interface input stream. The serial data
stream holds the access command, the address and the write data bits.
This pin is also the serial data line (SDA) when host interface is
configured for I2C mode. This pin is internally pulled up to VDD.
F4
so_asel1
I/O
Serial Interface Output. Serial interface output stream. As an output the
serial stream holds the read data bits. This pin is also the I2C address
select when host interface is configured for I2C mode.
G8
cs_b_asel0
I
Chip Select for Serial Interface. Serial interface chip select, this is an
active low signal. This pin is also the I2C address select when host
interface is configured for I2C mode.This pin is internally pulled up to
VDD.
Table 1 - Pin Description (continued)
10
Microsemi Corporation
ZL30236
Ball #
Data Sheet
Name
I/O
Description
A3
filter1
A
External Analog PLL1 Loop Filter terminal.
B3
filter1_ref
A
Analog PLL1 External Loop Filter Reference.
A8
filter2
A
External Analog PLL2 Loop Filter terminal.
B8
filter2_ref
A
Analog PLL2 External Loop Filter Reference.
I
Test Mode Enable. A logic high at this pin enables device test modes.
This pin is internally pulled down to GND. Connect this pin to GND.
APLL Loop Filter
JTAG (IEEE 1149.1) and Test
D4
test_en
C5
at
J3
tdo
O
Test Serial Data Out. JTAG serial data is output on this pin on the falling
edge of tck. This pin is held in high impedance state when JTAG scan is
not enabled.
K8
tdi
I
Test Serial Data In. JTAG serial test instructions and data are shifted in
on this pin. This pin is internally pulled up to VDD. If this pin is not used
then it should be left unconnected.
K3
trst_b
I
Test Reset. Asynchronously initializes the JTAG TAP controller by
putting it in the Test-Logic-Reset state. This pin should be pulsed low
on power-up to ensure that the device is in the normal functional state.
This pin is internally pulled up to VDD. If this pin is not used then it
should be connected to GND.
H4
tck
I
Test Clock. Provides the clock to the JTAG test logic. This pin is
internally pulled up to VDD. This pin is internally pulled up to VDD. If this
pin is not used then it should be connected to GND.
J8
tms
I
Test Mode Select. JTAG signal that controls the state transitions of the
TAP controller. This pin is internally pulled up to VDD. If this pin is not
used then it should be left unconnected.
A-I/O Analog PLL Test. Test pin for analog PLL.
Master Clock
A5
osco
A6
osci
A-O Oscillator Master Clock. For crystal operation, a crystal is connected
from this pin to osci. Not suitable for driving other devices. For clock
oscillator operation, this pin is left unconnected.
I
Oscillator Master Clock. For crystal operation, a crystal is connected
from this pin to osco. For clock oscillator operation, this pin is connected
to a clock source.
Miscellaneous
J4
K4
J5
K5
K6
J6
K7
J7
IC
Internal Connect. Connect to GND.
Table 1 - Pin Description (continued)
11
Microsemi Corporation
ZL30236
Ball #
Name
J1
J2
K1
K2
K9
K10
J10
J9
NC
I/O
Data Sheet
Description
Internal Connect. Leave unconnected.
Power and Ground
D6
H1
H10
VDD-IO
Positive Supply Voltage IO. 3.3VDC nominal.
B5
B6
D5
G5
G6
H5
H6
VCORE
Positive Supply Voltage. +1.8VDC nominal.
B4
D3
D8
E3
E8
F2
F9
AVDD
C6
E5
E6
F5
F6
VSS
A2
A4
A7
A9
B2
B9
C3
C8
H2
H3
H8
H9
AVSS
These pins should not be connected together on the board. Please refer
to ZLAN-269 for recommendations
Positive Analog Supply Voltage. +3.3VDC nominal.
Ground. 0 Volts.
Analog Ground. 0 Volts.
Table 1 - Pin Description (continued)
12
Microsemi Corporation
ZL30236
3.0
Data Sheet
Application Example
The device has two independent clock synthesizers, all locked to the external xtal or oscillator. The device will
generate all the clocks that drive the different components on the PCB.
FPGA
Memory
RapidIO
Bridge
Network
Processor
Fibre
Channel
PHY
ZL302xx
Osc
Figure 3 - Application Diagram
13
Microsemi Corporation
Optics
ZL30236
4.0
Data Sheet
Functional Description
The functional block diagram of the ZL30236 is shown in Figure 1.
The ZL30236 is a programmable clock generator that can be configured by any of the following methods:
power-up with its default configuration; power-up with a custom OTP (One Time Programmable) configuration;
after power-up it can be dynamically configured via the SPI/I2C port. Configurations set via the SPI/I2C port are
volatile and will need to rewritten if the device is reset or powered-down. The SPI/I2C port is also used to
access the status registers.
The ZL30236 has two independently programmable clock generators that output clocks of up to 750MHz with
jitter below 0.7ps RMS. The ZL30236 uses a single master clock based on a crystal resonator, a clock oscillator
or a voltage controlled oscillator. All of the clocks output by the ZL30236 will have the same PPM (Parts Per
Million) frequency accuracy as the master clock source.
The ZL30236 precision synthesizers can be programmed to generate any frequency between 1,000MHz and
1,500MHz. The frequency resolution of the synthesizers is much less than 1 PPB (Parts Per Billion).
Each synthesizer is followed by four independently programmable 23 bit even/odd post dividers. For skew
management purposes, the post dividers feeding the single ended outputs can impose a phase shift on their
output clock signals with resolution equal to a single period of their respective synthesizers' clocks.
All of the ZL30236 clock generators have the same PPM frequency accuracy as the master clock source and
therefore the frequency relationships between the clock generators can be programmed exactly. It is possible,
for example, to have one generator output 625MHz for 10GBASE-T while another generator outputs 625MHz *
66/64 * 255/237 for 10GBASE-T over OTN (Optical Transport Network). The clock generators will not drift or
slip with respect to each other.
Clocks from the two precision clock generators can be output on LVPECL or LVCMOS outputs.
The ZL30236 provides ten GPIO pins that can be used as enable pins for the hpout and hpdiff outputs; they can
also be used enable or stop the output clocks from the post dividers on a falling or rising edge.
The detailed operation of the ZL30236 is described in the following sections.
4.1
Frequency Synthesis Engine
The device frequency synthesis engine is comprised of a hardware DCO and an analog jitter filtering APLL with
built-in digital jitter attenuation scheme. It has two ultra low jitter frequency synthesis engines that can generate
output clocks which meet the jitter generation requirements detailed in section 10.0, “Performance
Characterization“.
The frequency synthesis engines can generate any clock which is (M/N X 1 kHz) multiple (FEC rate converted
clock). The M and N are 16 bits wide.
4.2
Dividers and Skew Management
The device has 4 independent dividers associated with each frequency synthesis engine.
The divider engines associated with the high performance differential outputs generate output clocks between
1 kHz and 750 MHz with 50% duty cycle. The other divider engines generate output clocks between 1 kHz and
177.5 MHz with 50% duty cycle.
The divider modules generating the single ended output clocks provides the ability to manage the phase skew
of the output clock by a coarse step equal to the internal high speed clock period.
The single ended generated output clocks can be stopped either on rising or falling edge (programmed through
serial interface or GPIO).The device can be configured to adjust the phase skew of single ended clocks in steps
of sub high speed synthesizer clock cycle.
14
Microsemi Corporation
ZL30236
4.3
Output Multiplexer
Figure 4 shows the multiplexing configuration supported.
Figure 4 - Output Clock Muxing Configuration
15
Microsemi Corporation
Data Sheet
ZL30236
4.4
Data Sheet
Output Drivers
The device has 8 high performance (HP) differential (LVPECL) outputs.
The device has 4 high performance (HP) single ended (LVCMOS) outputs.
High Performance (HP) single ended driver (LVCMOS) supports the jitter specification detailed in section 10.0,
“Performance Characterization“ and a maximum speed of 177.5 MHz.
The high performance (HP) differential driver (LVPECL) supports the jitter specification detailed in section 10.0,
“Performance Characterization“ and a maximum speed of 750 MHz.
LVPECL outputs should be terminated as shown in Figure 5. Terminating resistors provide 50 equivalent
Thevenin termination as well as biasing for the output LVPECL driver. Terminating resistors should be placed
as close as possible to input pins of the LVPECL receiver. If the LVPECL receiver has internal biasing then AC
coupling capacitors should be added.
3.3 V
3.3 V
Microsemi Device
LVPECL
driver
LVPECL
127
127 receiver
82
82
Zo = 50
Zo = 50
3.3 V
3.3 V
127
127
10 nF 5%
10 nF 5%
82
Figure 5 - Terminating LVPECL Outputs
16
Microsemi Corporation
82
LVPECL
receiver
with internal biasing
ZL30236
Data Sheet
If the transmission line is required to be AC coupled then the termination shown in Figure 6 should be implemented.
200 resistors are used to provide DC biasing for LVPECL driver. Both AC coupling capacitor and biasing resistors
should be placed as close as possible to output pins.
Thevenin termination (127 and 82 resistors provide 50 termination as well as biasing of the input LVPECL
receiver. If the LVPECL receiver has internal DC biasing then the line should be terminated with 100 termination
resistor between positive and negative input. In both cases termination resistors should be places as close as
possible to the LVPECL receiver pins. Some LVPECL receivers have internal biasing and termination. In this case
no external termination should be present.
3.3 V
3.3 V
Microsemi Device
LVPECL
driver
LVPECL
127
127 receiver
82
82
10 nF 5%
Zo = 50
10 nF 5%
Zo = 50
200
200
LVPECL
receiver
with internal biasing
100
LVPECL
receiver
with internal biasing
and termination
Figure 6 - Terminating AC coupled LVPECL Outputs
High performance LVCMOS outputs (hpoutclkx) should be terminated at the source with 22 resistor as shown in
Figure 7.
Microsemi Device
LVCMOS
driver
LVCMOS
receiver
22
Zo = 50
Figure 7 - Terminating LVCMOS Outputs
17
Microsemi Corporation
ZL30236
4.5
Data Sheet
Master Clock Interface
The master oscillator determines the device free-run frequency accuracy and holdover stability. The reference
monitor circuitry also uses this frequency as its point of reference (0 ppm) when making frequency measurements.
The master clock interface was designed to accept either a free-running clock oscillator (XO) or a crystal (XTAL).
Refer to application note ZLAN-68 for a list of recommended clock oscillators and crystals.
4.6
Clock Oscillator and Crystal Circuit
When using a clock oscillator as the master timing source, connect the oscillator’s output clock to the osci pin as
shown in Figure 8. The connection to osci should be direct and not AC coupled. The osco pin must be left
unconnected.
When using crystal resonator as the master timing source, connect crystal between osci and osco pins as shown
in Figure 8. Crystal should have bias resistor of 1Mand load capacitances C1 and C2. Value of load capacitances
is dependent on crystal and should be as per crystal datasheet. Crystal should be a fundamental mode type -- not
an overtone. See ZLAN-68 for crystal recommendation.
3.3 V
osci
24.576 MHz
XO
Microsemi Device
osco
Unconnected
C1
osci
Microsemi Device
24.576 MHz crystal
1 M
C2
osco
Load Capacitors C1 and C2
values should be as per crystal specification
Figure 8 - Clock Oscillator Circuit
18
Microsemi Corporation
ZL30236
Data Sheet
The device internal system clocks are generated off the device master clock input (Oscillator or a crystal
employing an on-chip buffer/driver). The master clock selection is done at start-up using the available GPIO
pins, right after pwr_b get de-asserted. To select 24.576 MHz oscillator, GPIO[1:0] pins need to be held high for
50 ms after the de-assertion of pwr_b, after which time they can be released and used as any other GPIO.
Alternatively, these pins can be pulled high with 1 Kresistors.
GPIO [1:0]
Master Clock Frequency
0
reserved
1
reserved
2
reserved
3
24.576 MHz
Table 2 - Master Clock Frequency Selection
4.7
Power Up/Down Sequence
The 3.3 V supply should be powered before or simultaneously with the 1.8 V supply. The 1.8 V supply must never
be greater than the 3.3 V supply by more than 0.3 V.
The power-down sequence is less critical, however it should be performed in the reverse order to reduce transient
currents that consume power.
4.8
Power Supply Filtering
Jitter levels on the output clocks may increase if the device is exposed to excessive noise on its power pins. For
optimal jitter performance, the device should be isolated from noise on power planes connected to its 3.3 V and
1.8 V supply pins. For recommended common layout practices, refer to Application Note ZLAN-269.
19
Microsemi Corporation
ZL30236
4.9
Data Sheet
Power on Reset and Initialization Circuit
To ensure proper operation, the device must be reset by holding the pwr_b pin low for at least 2 ms after power-up
when 3.3 V and 1.8 V supplies are stable. Following reset, the device will operate under specified default settings.
The reset pin can be controlled with on-board system reset circuitry or by using a stand-alone power-up reset circuit
as shown in Figure 9. This circuit provides approximately 2 ms of reset low time. The pwr_b input has Schmidt
trigger properties to prevent level bouncing.
3.3 V
Optional:
Populate to
enable hpdiff0
1 k
3.3 V
Populate
for I2C
3.3 V
1 k
3.3 V
1 k
1 k
gpio0
gpio1
gpio2
3.3 V
R
20 k
Microsemi Device
gpio3
gpio4
gpio5
Populate
for SPI
1 k
1 k
pwr_b
1 k
C
0.1F
Figure 9 - Typical Power-Up Reset and Configuration Circuit
General purpose pins gpio[0,1,3,4,5] are used to configure device on the power up. They have to be pulled
up/down with 1 K resistors as shown in Figure 9 or they can be pulsed low/high during the pwr_b low pulse and
kept at the same level for at least 50 ms after pwr_b goes high. After 50 ms they can be released and used as
general purpose I/O as described in section 5.0.
By default all outputs are disabled to allow user first to program required frequencies for different outputs and then
to enable corresponding outputs. During the prototype phase, hardware designer can verity if the device is working
properly even before software driver is implemented just by pulling up gpio2 pin which enables hpdiff0 output
(generates 622.08 MHz by default).
20
Microsemi Corporation
ZL30236
4.10
Data Sheet
Ultra Low Jitter Synthesizer Filter Components and Recommended Layout
The low jitter APLL has an on-chip loop filter, but for optimal APLL jitter performance external loop filter is
recommended, the following component values are recommended:
499
filterx
270 nF 10%
Microsemi Device
filterx_ref
470 pF 10%
Note: Ceramic capacitors should be used
Figure 10 - APLL Filter Component Values
Recommended layout for loop filters is shown in Figure 11:
Figure 11 - Recommended Layout for Loop Filters
21
Microsemi Corporation
ZL30236
5.0
Configuration and Control
5.1
Configuration Registers
Data Sheet
The ZL30236 configuration is composed of 253 x 8 bits. The configuration registers are assigned their values by
any of the following three methods:
1) Default configuration
2) Custom OTP (One Time Programmable) configuration
3) SPI/I2C configuration
5.1.1
Default Configuration
At power-up the device sets its configuration registers to the default reset values.
5.1.2
Custom OTP Configuration
At power-up the device sets it configuration registers to the user defined custom configuration values stored in its
one time programmable memory. Custom configurations can be generated using Microsemi’s Clockcenter GUI
software (ZLS30CLKCTR). For custom configured devices, contact your local Microsemi Field Applications
Engineer or Sales manager.
5.1.3
SPI/I2C Configuration
After power-up the values of R/W type configuration registers can be dynamically written via the SPI/I2C port.
Configurations set via the SPI/I2C port are volatile and will need to rewritten if the device is reset or powered-down.
5.2
Output Multiplexer Configuration and Programmability
The following is the set of parameters that are configurable:
•
•
5.3
Output multiplexer configuration
Start or Stop clock
Synthesizers Configuration and Programmability
The following is the set of parameters that are configurable:
•
•
5.4
Synthesizer 0 and 1 output frequency between 1.0 GHz and 1.5 GHz
Synthesizers 0 and 1 high speed output clock, defined as a 1 kHz multiple and 1 kHz multiple with M/N
ratio
Output Dividers and Skew Management Configuration and Programmability
The following is the set of parameters that are configurable:
•
•
•
5.5
Post divider enable/disable
Divider ratio (2 different setting, independent for each one of the divider outputs)
Output phase shift value (skew)
Output Drivers configuration and Programmability
The following is the set of parameters that are configurable:
•
Output driver Enable/Disable
22
Microsemi Corporation
ZL30236
5.6
Data Sheet
GPIO Configuration and Programmability
The device GPIO is mapped by the SPI/I2C programmability. The following is an example of control signals that
can be supported:
•
•
Differential output clock enable (per output or as a bank of 2 or 4 outputs)
Host Interrupt Output: flags changes of device status prompting the processor to read the enabled
interrupt service registers (ISR).
• Output clock stop/start
• Microport Interface Protocol I2C or SPI
The following table defines the function of the GPIO pin when configured as a control pin. Configuring the value in
bit 6:0 in GPIO configuration registers enables the stated function.
Value
Name
Description
Default
0x00
default
GPIO pin defined as an input and no function assigned to it.
Synthesizer Post Divider
0x44
Stop output clock from
Synthesizer0 Post Divider C
bit1
This signal is OR-ed with the 'Syntheizer0 Post Divider C stop clock'
bit1 in the 'Synthesizer0 and Synthesizer1 Post Dividers stop clock'
register.
0x45
Stop output clock from
Synthesizer0 Post Divider C
bit0
Same description as Stop output clock Synthesizer0 Post Divider C
bit1
0x46
Stop output clock from
Synthesizer0 Post Divider D
bit1
Same description as Stop output clock Synthesizer0 Post Divider C
bit1
0x47
Stop output clock from
Synthesizer0 Post Divider D
bit0
Same description as Stop output clock Synthesizer0 Post Divider C
bit1
0x4C
Stop output clock from
Synthesizer1 Post Divider C
bit1
Same description as Stop output clock Synthesizer0 Post Divider C
bit1
0x4D
Stop output clock from
Synthesizer1 Post Divider C
bit0
Same description as Stop output clock Synthesizer0 Post Divider C
bit1
0x4E
Stop output clock from
Synthesizer1 Post Divider D
bit1
Same description as Stop output clock Synthesizer0 Post Divider C
bit1
0x4F
Stop output clock from
Synthesizer1 Post Divider D
bit0
Same description as Stop output clock Synthesizer0 Post Divider C
bit1
High Performance Differential Outputs
23
Microsemi Corporation
ZL30236
Value
Name
Data Sheet
Description
0x60
Enable Differential output
HPDIFF0
This signal is OR-ed with the 'Enable HPDIFF0' bit in the 'High
performance differential output enable' register. Functionality of this
signal is explained in hpdiff_en register.
0x64
Enable Differential output
HPDIFF1
Same description as Enable Differential output HPDIFF0
0x68
Enable Differential output
HPDIFF2
Same description as Enable Differential output HPDIFF0
0x6C
Enable Differential output
HPDIFF3
Same description as Enable Differential output HPDIFF0
High Performance CMOS Outputs
0x70
Enable HPOUTCLK0
This signal is OR-ed with the 'Enable HPOUTCLK0' bit in the 'High
performance CMOS output enable' register.
0x72
Enable HPOUTCLK1
Same description as Enable HPOUTCLK0
0x74
Enable HPOUTCLK2
Same description as Enable HPOUTCLK0
0x76
Enable HPOUTCLK3
Same description as Enable HPOUTCLK0
24
Microsemi Corporation
ZL30236
6.0
Data Sheet
Host Interface
A host processor controls and receives status from the Microsemi device using either a SPI or an I2C interface. The
type of interface is selected using the startup state of the GPIO pins.
Microsemi Device
Microsemi Device
sck
si
so
scl
sda
asel0
asel1
cs_b
I2C Configuration
SPI Configuration
Figure 12 - Serial Interface Configuration
The selection between I2C and SPI interfaces is performed at start-up using GPIO[3] pin, right after pwr_b gets
de-asserted. The GPIO pin need to be held at their appropriate value for 50 ms after the de-assertion of pwr_b,
after which time they can be released and used as any other GPIO.
Both interfaces use seven bit address field and the device has eight bit address space. Hence, memory is
divided in two pages. Page 0 with addresses 0x00 to 0x7E and Page 1 with addresses 0x80 to 0xFF. Writing
0x01 to Page Register at address 0x7F, toggles SPI/I2C accesses between Page 0 and Page 1.
GPIO[3]
Serial Interface
0
SPI
1
I2C
Table 3 - Serial Interface Selection
6.1
Serial Peripheral Interface
The serial peripheral interface (SPI) allows read/write access to the registers that are used to configure, read
status, and allow manual control of the device.
This interface supports two modes of access: Most Significant Bit (MSB) first transmission or Least Significant Bit
(LSB) first transmission. The mode is automatically selected based on the state of sck_scl pin when the
cs_b_asel0 pin is active. If the sck_scl pin is low during cs_b_asel0 activation, then MSB first timing is selected. If
the sck_scl pin is high during cs_b_asel0 activation, then LSB first timing is assumed.
The SPI port expects 7-bit addressing and 8-bit data transmission, and is reset when the chip select pin
cs_b_asel0 is high. During SPI access, the cs_b_asel0 pin must be held low until the operation is complete. The
first bit transmitted during the address phase of a transfer indicates whether a read (1) or a write (0) is being
performed. Burst read/write mode is also supported by leaving the chip select signal cs_b_asel0 is low after a read
or a write. The address will be automatically incremented after each data byte is read or written.
The serial peripheral interface supports half-duplex processor mode which means that during a write cycle to the
device, output data from the so_asel1 pin must be ignored. Similarly, the input data on the si_sda pin is ignored by
the device during a read cycle.
Functional waveforms for the LSB and MSB first mode, and burst mode are shown in Figure 13, Figure 14 and
Figure 15. Timing characteristics are shown in Table 5, Figure 24, and Figure 25.
25
Microsemi Corporation
ZL30236
6.1.1
Data Sheet
Least Significant Bit (LSB) First Transmission Mode
cs_b
sck
Read from the device
si
Rd A0 A1 A2 A3 A4 A5
A6
X
so
X
X
X
X
X
X
X
D0 D1 D2 D3 D4 D5 D6 D7
Write to the device
si
D0 D1 D2 D3 D4 D5 D6 D7
Wr A0 A1 A2 A3 A4 A5 A6
X
so
X
X
Command/Address
X
X
X
X
X
Data
Figure 13 - Serial Peripheral Interface Functional Waveforms - LSB First Mode
6.1.2
Most Significant Bit (MSB) First Transmission Mode
cs_b
sck
Read from the device
si
Rd A6 A5
A4 A3 A2 A1 A0
so
X
X
X
X
X
X
D7
D6 D5 D4 D3 D2
X
X
D1 D0
Write to the device
si
Wr A6 A5 A4 A3 A2 A1 A0
D7 D6 D5 D4 D3 D2 D1 D0
X
so
Command/Address
X
X
X
X
X
X
X
Data
Figure 14 - Serial Peripheral Interface Functional Waveforms - MSB First Mode
26
Microsemi Corporation
ZL30236
6.1.3
Data Sheet
SPI Burst Mode Operation
cs_b
Address +0
Address
Data
Address +1
Address +2
Data
Address +N
Data
Data
Figure 15 - Example of a Burst Mode Operation
6.1.4
I2C Interface
The I2C controller supports version 2.1 (January 2000) of the Philips I2C bus specification. The port operates in
slave mode with 7-bit addressing, and can operate in Standard (100 kbits/s) and Fast (400 kbits/s) mode. Burst
mode is supported in both standard and fast modes.
Data is transferred MSB first and occurs in 1 byte blocks. As shown in Figure 16, a write command consists of a 7bit device (slave) address, a 7-bit register address (0x00 - 0x7F), and 8-bits of data.
Data Write
Byte
Byte
Byte
S Slv Addr[6:0] W ACK x Reg Addr[6:0] ACK
Data[7:0]
ACK P
S Start (master)
W Write
Master Initiated
P Stop (master)
R Read
Slave Initiated
ACK Acknowledge
Figure 16 - I2C Data Write Protocol
A read is performed in two stages. A data write is used to set the register address, then a data read is performed to
retrieve the data from the set address. This is shown in Figure 17.
Byte
Byte
Data Write
(set read address)
S Slv Addr[6:0] W ACK x Reg Addr[6:0] ACK P
Data Read
S Slv Addr[6:0] R ACK
Data[7:0]
ACK P
Figure 17 - I 2C Data Read Protocol
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Microsemi Corporation
The 7-bit device (slave) address contains a 5-bit fixed address plus variable bits which are set with the asel0, and
asel1 pins. This allows multiple similar devices to share the same I2C bus. The address configuration is shown in
Figure 18.
6
5
4
3
2
1
0
0 1 1 1 0
asel0
asel1
Figure 18 - I 2C 7-bit Slave Address
The device also supports burst mode which allows multiple data write or read operations with a single specified
address. This is shown in Figure 19 (write) and Figure 20 (read). The first data byte is written/read from the
specified address, and subsequent data bytes are written/read using an automatically increment address. The
maximum auto increment address of a burst operation is 0x7F. Any operations beyond this limit will be ignored. In
other words, the auto increment address does not wrap around to 0x00 after reaching 0x7F.
Data Write (Burst Mode)
S Slv Addr[6:0] W ACK x Reg Addr[6:0] ACK Data[7:0] ACK Data[7:0] ACK Data[7:0] ACK P
Write to
Reg Addr[6:0]
Write to
Reg Addr[6:0] +1
Figure 19 - I 2C Data Write Burst Mode
Data Write (Set first read address)
S Slv Addr[6:0] W ACK x Reg Addr[6:0] ACK P
Data Read (Burst Mode)
S Slv Addr[6:0] R ACK Data[7:0] ACK Data[7:0] ACK Data[7:0] ACK P
Read from
Reg Addr[6:0]
Read from
Reg Addr[6:0] +1
Read from
Reg Addr[6:0] +2
Figure 20 - I 2C Data Read Burst Mode
Write to
Reg Addr[6:0] +2
ZL30236
7.0
Data Sheet
Register Map
The device is mainly controlled by accessing software registers through the serial interface (SPI or I2C). The device
can be configured to operate in a highly automated manner which minimizes its interaction with the system’s
processor, or it can operate in a manual mode where the system processor controls most of the operation of the
device.
The simplest way to generate appropriate configuration for the device is to use the evaluation board GUI
which can operate standalone (without the board). With GUI user can quickly set all required parameters
and save the configuration to a text file.
Multi-byte Register Values
The device register map is based on 8-bit register access, so register values that require more than 8 bits must be
spread out over multiple registers and accessed in 8-bit segments. When accessing multi-byte register values, it is
important that the registers are accessed in the proper order, they must follow big endian addressing scheme. The
8-bit register containing the most significant byte (MSB) must be accessed first, and the register containing the
least significant byte (LSB) must be accessed last. An example of a multi-byte register is shown in Figure 21. When
writing a multi-byte value, the value is latched when the LSB is written.
Example:
The programmable input reference M and N 16 bit values defining the M/N ratio is programmed using a 32-bit
value which is spread over four 8-bit registers. The MSB is contained in address 0x14 and the LSB in 0x17.
When reading or writing this multi-byte value, the MSB must be accessed first, followed by the middle bytes,
and the LSB last.
0x14 (MSB)
0x15
0x16
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
1
Read or Write
this byte first
2
Read or Write
this byte next
3
0x17 (LSB)
8 7 6 5 4 3 2 1
Read or Write
this byte next
4
0
Read or Write
this byte last
Figure 21 - Accessing Multi-byte Register Values
To assist in device setup, a configuration GUI is provided. The configuration GUI can directly configure the device
evaluation board, but it also functions as a tool to provide details on how to configure different device registers.
Procedure for writing registers
For each of the following ZL30236 control registers, the user should implement the write procedure described
below. Using this procedure to write other control registers is acceptable, but it is required for the registers listed
below.
• Registers: 0x46, 0xB8and, 0xBA
-write 0x01 to Sticky_R_Lock Register at address 0x0D
-write to one or more ZL30236 control register(s)
-write 0x00 to Sticky_R_Lock Register at address 0x0D
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Microsemi Corporation
ZL30236
Data Sheet
Time between two write accesses to the same register
•
User should wait at least 8 ms between two write accesses to the same register
•
For page_register at address 0x7F, and Sticky_r_lock register at register 0x0D, there is no waiting time
required between two write accesses.
Reading from Sticky Read (StickyR) Registers
Access to some status registers is defined as Sticky Read (StickyR). Procedure for accessing these registers is:
-write 0x01 to StickyR Lock Register at address 0x0D
-clear status register(s) by writing 0x00 to it
-write 0x00 to StickyR Lock Register at address 0x0D
-wait for 8 ms
-read the status register(s)
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Microsemi Corporation
ZL30236
Data Sheet
The following table is a summary of the registers available for status updates and configuration of the device.
Devices with a custom OTP configuration will power-up with the custom configuration values instead of the default
values.
.
Reg_Addr
(Hex)
Register
Name
Default
Value
(Hex)
Description
Type
Miscellaneous Registers
0x00
id_reg
0x01
config_record_id [23:16]
0x0D
Sticky_r_lock
0x0E:0x0F
See
Descript
ion
config_record_id [15:0]
Chip ID and version identification
R
0xFF
Configuration record identification, bits
[23:16]
R
0x00
Used to lock StickyR Status Registers from
being updated by internal device logic
0x0000
Configuration record identification, bits
[15:0]
R/W
R
Output Synthesizer Configuration Registers
0x46
reduced_diff_out_pwr
0x00
Enables reduced power on high
performance differential outputs
R/W
0x50:0x51
synth0_base_freq
0x9C40
Synthesizer 0 base frequency
R/W
0x52:0x53
synth0_freq_multiple
0x0798
Synthesizer 0 base frequency
multiplication number
R/W
0x54:0x57
synth0_ratio_M_N
0x00010
001
Specifies numerator Ms and denominator
Ns for synthesizer 0 multiplication ratio
Ms/Ns
R/W
0x58:0x59
synth1_base_freq
0x61A8
Synthesizer 1 base frequency
R/W
0x5A:0x5B
synth1_freq_multiple
0x0C35
Synthesizer 1 base frequency
multiplication number
R/W
0x5C:0x5F
synth1_ratio_M_N
0x00010
001
Specifies numerator Ms and denominator
Ns for synthesizer 1 multiplication ratio
Ms/Ns
R/W
Output synthesizer enable
R/W
0x046A
AAAB
Central frequency offset to compensate
for oscillator inaccuracy
R/W
0x71
0x73:0x76
output_synthesizer_en
central_freq_offset
0x03
0x77
synth_1_0_filter_sel
0x00
Synthesizer 1 and 0 selection between
internal and external filter
R/W
0x78
synth0_fine_phase_shift
0x00
Synthesizer 0 fine phase shift
R/W
Table 4 - Register Map
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Microsemi Corporation
ZL30236
Reg_Addr
(Hex)
Default
Value
(Hex)
Register
Name
Data Sheet
Description
Type
0x79
synth1_fine_phase_shift
0x00
Synthesizer 1 fine phase shift
R/W
0x7F
page_register
0x00
Selects between pages 0 and 1
R/W
0x80:0x82
synth0_post_div_A
0x00000
2
Synthesizer 0 post divider A
R/W
0x83:0x85
synth0_post_div_B
0x00000
2
Synthesizer 0 post divider B
R/W
0x86:0x88
synth0_post_div_C
0x00004
0
Synthesizer 0 post divider C
R/W
0x89:0x8B
synth0_post_div_D
0x00004
0
Synthesizer 0 post divider D
R/W
0x8C,0x8E
synth1_post_div_A
0x00000
2
Synthesizer 1 post divider A
R/W
0x8F,0x91
synth1_post_div_B
0x00000
2
Synthesizer 1 post divider B
R/W
0x92,0x94
synth1_post_div_C
0x00003
2
Synthesizer 1 post divider C
R/W
0x95,0x97
synth1_post_div_D
0x00003
2
Synthesizer 1 post divider D
R/W
Output Reference Selection and Output Driver Control
0xB0
hp_diff_en
0x00
High Performance differential output
enable
R/W
0xB1
hp_cmos_en
0x00
Enables High Performance CMOS outputs
hpoutclk[1:0]
R/W
0xB8
synth1_0_stop_clk
0x00
Stops output clocks for post dividers C and
D of Synthesis Engine 0 and 1 at either
high or low logical level
R/W
0xB9
sync_fail_flag_status
0x00
Indicates Synthesizers loss of lock
0xBA
clear_sync_fail_flag
0x00
Clears Synthesizers fail flag in register
0xB9
R/W
0x0000
hpoutclk0 output coarse phase shift in
granularity of 45 degrees and one high
frequency synthesizer clock period.
R/W
0xBF:0xC0
phase_shift_s0_postdiv_C
Table 4 - Register Map (continued)
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Microsemi Corporation
StickyR
ZL30236
Reg_Addr
(Hex)
0xC1:0xC2
Default
Value
(Hex)
Register
Name
phase_shift_s0_postdiv_D
0x0000
Data Sheet
Description
Type
hpoutclk1 output coarse phase shift in
granularity of 45 degrees and one high
frequency synthesizer clock period.
R/W
0XC3
xo_or_crystal_sel
0x00
Disables OSCo driver.
R/W
0xC6
Chip_revision_2
0x03
Chip revision identification
R/W
0xC7:0xC8
phase_shift_s1_postdiv_C
0x0000
hpoutclk2 output coarse phase shift in
granularity of 45 degrees and one high
frequency synthesizer clock period.
R/W
0xC9:0xCA
phase_shift_s1_postdiv_D
0x0000
hpoutclk3 output coarse phase shift in
granularity of 45 degrees and one high
frequency synthesizer clock period.
R/W
0xE0
gpio_function_pin0
0x00
GPIO control or status select
R/W
0xE1
gpio_function_pin1
0x00
GPIO control or status select
R/W
0xE2
gpio_function_pin2
0x60
GPIO control or status select
R/W
0xE3
gpio_function_pin3
0x00
GPIO control or status select
R/W
0xE4
gpio_function_pin4
0x00
GPIO control or status select
R/W
0xE5
gpio_function_pin5
0x00
GPIO control or status select
R/W
0xE6
gpio_function_pin6
0x00
GPIO control or status select
R/W
0xE7
gpio_function_pin7
0x00
GPIO control or status select
R/W
0xE8
gpio_function_pin8
0x00
GPIO control or status select
R/W
0xE9
gpio_function_pin9
0x00
GPIO control or status select
R/W
0xEA
gpio_function_pin10
0x00
GPIO control or status select
R/W
0xEB
gpio_function_pi11
0x00
GPIO control or status select
R/W
0xF7
spurs_suppression
0x00
Used for spurs suppression
R/W
Table 4 - Register Map (continued)
.
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Microsemi Corporation
ZL30236
8.0
Data Sheet
Detailed Register Map
Register_Address: 0x00
Register Name: id_reg
Default Value:0x64
Type: R/W
Bit
Field
Function Name
Description
4:0
chip_id
Chip Identification = 0b00100
6:5
chip_revision
Chip revision number = 0b00
Note:also see Chip_revision_2 register description at Register _Address:
0xC6 for full chip revision information
ready_indication
After reset this bit goes high when device is ready. This signals that user
can start to program/configure the device. It can take up to 50 ms for this
bit to go high after the reset.This bit should not be polled until 40ms after
reset.
7
Register_Address: 0x01
Register Name :config_record_id [23:16]
Default Value:0xFF
Type: R/W
Bit
Field
7:0
Function Name
config_record_id
Description
Bits [23:16] of the config_record_id. See application note ZLAN-301 to
understand how to translate the config_record_id into an alpha-numeric
CCID (Custom Configuration Identification). Valid config_record_id
values are 0x000000 to 0x0E1780 and 0xFF0000. Devices with a factory
default reset configuration report a config_record_id value of 0xFF0000.
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Microsemi Corporation
ZL30236
Data Sheet
Register_Address: 0x0D
Register Name :Sticky_r_lock
Default Value: 0x00
Type: R/W
Bit
Field
7:0
Function Name
Sticky_r_lock
Description
This register is used when accessing StickyR status registers. Writing
0x01 to this register locks the status register from being updated by
internal logic. Writing 0x00 to this register enables internal updates of
StickyR status registers
Please refer to Reading from Sticky Read (StickyR) registers and
Procedure for writing registers procedure at the beginning of 7.0,
“Register Map“section..
Register_Address: 0x0E:0x0F
Register Name: config_record_id [15:0]
Default Value:0x0000
Type: R/W
Bit
Field
15:0
Function Name
config_record_id
Description
Bits [15:0] of the config_record_id. See application note ZLAN-301 to
understand how to translate the config_record_id into an alpha-numeric
CCID (Custom Configuration Identification). Valid config_record_id
values are 0x000000 to 0x0E1780 and 0xFF0000. Devices with a factory
default reset configuration report a config_record_id value of 0xFF0000.
Register_Address: 0x46
Register Name: reduced_diff_out_pw
Default Value: 0x00
Type: R/W
Bit
Field
Function Name
Description
0
hpout0_reduced_pwr
When this bit is set to high, it will enable reduced power mode for
HPDIFF0_P and HPDIFF0_N outputs. When low, the outputs are in full
power mode.
1
hpout1_reduced_pwr
Same description as above but for HPDIFF1 output.
2
hpout2_reduced_pwr
Same description as above but for HPDIFF2 output.
3
hpout3_reduced_pwr
Same description as above but for HPDIFF3 output.
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Microsemi Corporation
ZL30236
Data Sheet
Register_Address: 0x46
Register Name: reduced_diff_out_pw
Default Value: 0x00
Type: R/W
Bit
Field
Function Name
Description
4
hpout4_reduced_pwr
Same description as above but for HPDIFF4 output.
5
hpout5_reduced_pwr
Same description as above but for HPDIFF5 output.
6
hpout6_reduced_pwr
Same description as above but for HPDIFF6 output.
7
hpout7_reduced_pwr
Same description as above but for HPDIFF7 output.
Register_Address: 0x50:0x51
Register Name: synth0_base_freq
Default Value: 0x9C40
Type:R/W
Bit
Field
15:0
Function Name
synth0_base_freq_Bs
Description
Unsigned binary value of these bits represents Synthesizer0 base
frequency Bs in Hz. Values for Br that can be programmed:
0x03E8 for 1 kHz,
0x07D0 for 2 kHz,
0x1388 for 5 kHz,
0x186A for 6.25 kHz,
0x1F40 for 8 kHz,
0x2710 for 10 kHz,
0x30D4 for 12.5 kHz,
0x61A8 for 25 kHz,
0x9C40 for 40 kHz.
Note: Other Bs rates can be supported, please contact the CMPG
application support team if another specific Bs rate is required
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Microsemi Corporation
ZL30236
Data Sheet
Register_Address: 0x52:0x53
Register Name: synth0_freq_multiple
Default Value: 0x0798
Type:R/W
Bit Field
Function Name
Description
15:0
synth0_base_freq_mult_Ks
Unsigned binary value of these bits represents Synthesizer0 base
frequency multiplication number. For regular (non-FEC) synthesizer
frequency, the 'Base frequency' number Bs multiplied by the 'Base
frequency multiple' number Ks, and multiplied by 16 has to equal the
synthesizer frequency in Hz.
Note 1: synthesizer frequency has to be between 1 GHz and 1.5 GHz,
so:
Bs x Ks x 16 x Ms / Ns has to be between 1 000 000 000 and 1 500
000 000.
Examples of some synthesizer frequencies and appropriate values
that can be programmed for Bs and Ks to get desired synthesizer
frequency:
Synthesizer frequency
Base frequency Bs
Base frequency
multiple Ks
1.048576 GHz
8 kHz (0x1F40)
8192 (0x2000)
1.24416 GHz
40 kHz (0x9C40)
1944 (0x0798)
1.25 GHz
25 kHz (0x61A8)
3125 (0x0C35)
Note 2: Synthesizer 0 and 1 can be set to generate identical
frequencies if that frequency is between 1.1 GHz and 1.5 GHz. For
frequencies between 1.0 GHz and 1.1 GHz Synthesizers 0 and 1
should not be set to generate the same frequency. In this case user
should try to set one Synthesizer to lower range (1.0 GHz to
1.25 GHz) and the other to the higher range (1.25 GHz to 1.5 GHz)
and then use different values for output dividers to get the same
frequency at the output. This method can be used for all output
frequencies except for output frequencies in 500 MHz to 550 MHz
range. Please contact your local Field Applications Engineer for
recommendations if output frequencies sourced from both high
performance synthesizer need to be the same and in 500 MHz to
550 MHz range.
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Microsemi Corporation
ZL30236
Data Sheet
Register_Address: 0x54:0x57
Register Name: synth0_ratio_M_N
Default Value: 0x00010001
Type:R/W
Bit Field
15:0
Function Name
synth0_ratio_denom_Ns
Description
Unsigned binary value of Ms bits, in combination with unsigned
binary value of Ns bits represents Synthesizer0 FEC multiplication
ratio. Synthesizer FEC frequencies are calculated using the
following formula:
Synth_freq [Hz] = Bs x Ks x 16 x Ms / Ns
31:16
synth0_ratio_numer_Ms
For regular (non-FEC) synthesizer frequencies, Ms and Ns should
be programmed to 0x0001 (default values)
Examples of some synthesizer FEC frequencies and appropriate
values that can be programmed for the Bs, Ks, Ms and Ns
registers to get those FEC frequencies:
a) OC-192 mode, standard EFEC for long reach:
Desired frequency:
155.52 MHz x 255 / 237
Synth frequency:
1.24416 GHz x 255/237
Base frequency Bs:
40 KHz (0x9C40)
Base freq. multiplier Ks:
1944 (0x0798)
FEC ratio numerator Ms: 255 (0x00FF)
FEC ratio denominator Ns: 237 (0x00ED)
Post div PA:
8
b) Long reach 10 GE mode, double rate conversion:
Desired frequency:
156.25MHz x 66/64 x 255/238
Synth frequency:
1.25GHz x 66/64 x 255/238
Base frequency Bs:
25 kHz (0x061A8)
Base freq. multiplier Ks:
3125 (0x0C35)
FEC ratio numerator Ms: 66x255 (0x41BE)
FEC ratio denominator Ns: 64x238 (0x3B80)
Post div PA:
8
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Microsemi Corporation
ZL30236
Data Sheet
Register_Address: 0x58:0x59
Register Name: synth1_base_freq
Default Value: 0x61A8
Type:R/W
Bit
Field
15:0
Function Name
synth1_base_freq_Bs
Description
Unsigned binary value of these bits represents Synthesizer1 base
frequency Bs in Hz. Values for Br that can be programmed:
0x03E8 for 1 kHz,
0x07D0 for 2 kHz,
0x1388 for 5 kHz,
0x186A for 6.25 kHz,
0x1F40 for 8 kHz,
0x2710 for 10 kHz,
0x30D4 for 12.5 kHz,
0x61A8 for 25 kHz,
0x9C40 for 40 kHz.
Note: Other Bs rates can be supported, please contact the CMPG
application support team if another specific Bs rate is required.
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Microsemi Corporation
ZL30236
Data Sheet
Register_Address: 0x5A:0x5B
Register Name: synth1_freq_multiple
Default Value: 0x0C35
Type:R/W
Bit Field
Function Name
15:0
synth1_base_freq_mult_Ks
Description
Unsigned binary value of these bits represents Synthesizer1 base
frequency multiplication number. For regular (non-FEC) synthesizer
frequency, the 'Base frequency' number Bs multiplied by the 'Base
frequency multiple' number Ks, and multiplied by 8 has to equal the
synthesizer frequency in Hz.
Note 1: synthesizer frequency has to programmed to be between
1 GHz and 1.5 GHz, so:
Bs x Ks x 16 x Ms / Ns has to be between 1 000 000 000 and 1 500
000 000.
Examples of some references frequencies and appropriate values that
can be programmed for Bs and Ks to get desired synthesizer
frequency:
Synthesizer frequency
Base frequency Bs
Base frequency
multiple Ks
1.048576 GHz
8 kHz (0x1F40)
8192 (0x2000)
1.24416 GHz
40 kHz (0x9C40)
1944 (0x0798)
1.25 GHz
25 kHz (0x61A8)
3125 (0x0C35)
Note 2: Synthesizer 0 and 1 can be set to generate identical
frequencies if that frequency is between 1.1 GHz and 1.5 GHz. For
frequencies between 1.0 GHz and 1.1 GHz Synthesizers 0 and 1
should not be set to generate the same frequency. In this case user
should try to set one Synthesizer to lower range (1.0 GHz to
1.25 GHz) and the other to the higher range (1.25 GHz to 1.5 GHz)
and then use different values for output dividers to get the same
frequency at the output. This method can be used for all output
frequencies except for output frequencies in 500 MHz to 550 MHz
range. Please contact your local Field Applications Engineer for
recommendations if output frequencies sourced from both high
performance synthesizer need to be the same and in 500 MHz to
550 MHz range.
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Microsemi Corporation
ZL30236
Data Sheet
Register_Address: 0x5C:0x5F
Register Name: synth1_ratio_M_N
Default Value: 0x00010001
Type:R/W
Bit Field
15:0
Function Name
synth1_ratio_denom_Ns
Description
Unsigned binary value of Ms bits, in combination with unsigned
binary value of Ns bits represents Synthesizer1 FEC multiplication
ratio. Synthesizer FEC frequencies are calculated using the
following formula:
Synth_freq [Hz] = Bs x Ks x 16 x Ms / Ns
31:16
synth1_ratio_numer_Ms
For regular (non-FEC) synthesizer frequencies, Ms and Ns should
be programmed to 0x0001 (default values)
Examples of some synthesizer FEC frequencies and appropriate
values that can be programmed for the Bs, Ks, Ms and Ns registers
to get those FEC frequencies:
a) OC-192 mode, standard EFEC for long reach:
Desired frequency:
155.52 MHz x 255 / 237
Synth frequency:
1.24416 GHz x 255/237
Base frequency Bs:
40 KHz (0x9C40)
Base freq. multiplier Ks:
1944 (0x0798)
FEC ratio numerator Ms: 255 (0x00FF)
FEC ratio denominator Ns: 237 (0x00ED)
Post div PA:
8
b) Long reach 10GE mode, double rate conversion:
Desired frequency:
156.25MHz x 66/64 x 255/238
Synth frequency:
1.25GHz x 66/64 x 255/238
Base frequency Bs:
25 kHz (0x061A8))
Base freq. multiplier Ks:
3125 (0x0C35)
FEC ratio numerator Ms: 66x255 (0x41BE)
FEC ratio denominator Ns: 64x238 (0x3B80)
Post div PA:
8
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Microsemi Corporation
ZL30236
Data Sheet
Register_Address: 0x71
Register Name: output_synth_en
Default Value: 0x03
Type:R/W
Bit
Field
1:0
Function Name
synth_en
Description
Enables output of Synthesizers 0 and 1
x1: enables synth0 output
1x: enables synth1 output
7:2
reserved
reserved
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Microsemi Corporation
ZL30236
Data Sheet
Register_Address: 0x73:0x76
Register Name: central_freq_offset
Default Value: 0x046AAAAB
Type:R/W
Bit
Field
31:0
Function Name
central_freq_offset
Description
2's complement binary value of these bits represent central frequency
offset for the device. This value should be used to compensate for
oscillator inaccuracy, or make the device look like Numerically
Controlled Oscillator (NCO). This register controls central frequency of
all 4 Synthesizers.
Expressed in steps of +/- 2^-32 of nominal setting.
When oscillator inaccuracy is known: inacc_osc = (f_osc - f_nom)/f_nom
(usually specified in ppm), value to be programmed in this register is
calculated as per the following formula:
X = (1/(1 + inacc_osc) - 1)*2^32, when f_osc < f_nom
X = (1/(1 + inacc_osc))*2^32, when f_osc > f_nom,
where inacc_osc - represents oscillator frequency inaccuracy,
f_osc - represents oscillator frequency, and
f_nom - represents oscillator nominal frequency (i.e., 25 MHz)
Generally, when the oscillator frequency is lower than the nominal,
frequency offset has to be programmed to compensate it in opposite
direction, i.e. frequency offset has to be positive, and vice versa.
Example 1): if oscillator inaccuracy is -2% (f_osc = 24.5 MHz; inacc_osc
= (f_osc - 25 MHz)/25MHz = -0.02),
X= (1/(1+(-0.02)) - 1)*2^32 = (1/0.98 - 1)*2^32 = 87652394 =
0x0539782A
Example 2): if oscillator inaccuracy is +2% (f_osc = 25.5 MHz;
inacc_osc = (f_osc - 25 MHz)/25MHz = 0.02),
X= (1/(1+ 0.02))*2^32 = (1/1.02)*2^32 = 4210752251 = 0xFAFAFAFB
When NCO behaviour is desired, the output frequency should be
calculated as per formula:
fout = (1 + X/2^32)*finit
where X -represent 2's complement number specified in this register
finit - initial frequency set by Bs, Ks, Ms, Ns and postdivider number for
particular VCO
fout - output frequency
Note 1: Nominal frequency for central frequency offset calculation is 25
MHz although master clock frequency is required to be 24.576 MHz.
Because of this default value in this register is 0x046AAAAB.
Note 2: Central Frequency Offset should not exceed +/-5% off nominal.
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Microsemi Corporation
ZL30236
Data Sheet
Register_Address: 0x77
Register Name: synth1_0_filter_sel
Default Value: 0x00
Type:R/W
Bit
Field
0
Function Name
synth0_filter_select
Description
Selects filter used by Synthesizer 0
0: external filter
1: internal filter
1
synth1_filter_select
Selects filter used by Synthesizer 1
0: external filter
1: internal filter
7:2
reserved
reserved
Register_Address: 0x78
Register Name: synth0_fine_phase_shift
Default Value: 0x00
Type:R/W
Bit
Field
7:0
Function Name
syn0_fine_phase_shift
Description
Unsigned binary value of these bits represent Synth0 fine phase shift
(advancement) in steps of Synth0_period / 256.
Note 1: This register controls fine phase shift for all clocks coming out of
the Synthesizer 0 (including all four postdividers)
44
Microsemi Corporation
ZL30236
Data Sheet
Register_Address: 0x79
Register Name: synth1_fine_phase_shift
Default Value: 0x00
Type:R/W
Bit
Field
7:0
Function Name
syn1_fine_phase_shift
Description
Unsigned binary value of these bits represent Synth1 fine phase shift
(advancement) in steps of Synth1_period / 256.
Note 1: This register controls fine phase shift for all clocks coming out of
the Synthesizer 1 (including all four postdividers)
Register_Address: 0x7F
Register Name: page_register
Default Value: 0x00
Type:R/W
Bit
Field
0
Function Name
page_select
Description
This register is used to toggle memory access between page 0
(addresses 0x00 to 0x7E) and page 1 (addresses 0x80 to 0xFF). This is
required because SPI and I2C ports have only seven address bits and
the device memory space is eight bit wide.
0: selects addresses 0x00 to 0x7E
1: selects addresses 0x80 to 0xFB
7:1
reserved
reserved
Register_Address: 0x80:0x82
Register Name: synth0_post_div_A
Default Value: 0x000002
Type:R/W
Bit
Field
22:0
23
Function Name
Description
synth0_post_div_A
Unsigned binary value represents Synthesizer0 Post Divider value P0A.
The Synthesizer0 frequency is divided by the P0A value before being
fed to the selected output pins
reserved
This bit must be set to 0
45
Microsemi Corporation
ZL30236
Data Sheet
Register_Address: 0x83:0x85
Register Name: synth0_post_div_B
Default Value: 0x000002
Type:R/W
Bit
Field
22:0
23
Function Name
Description
synth0_post_div_B
Unsigned binary value represents Synthesizer0 Post Divider value P0B.
The Synthesizer0 frequency is divided by the P0B value before being
fed to the selected output pins
reserved
This bit must be set to 0
Register_Address: 0x86:0x88
Register Name: synth0_post_div_C
Default Value: 0x000040
Type:R/W
Bit
Field
Function Name
Description
15:0
frm_pulse_period_or_div
When bits 23:20 of this register are programmed to '1111', binary value
of these bits represent number of periods of the selected related clock in
between two frame pulses
When bits 23:20 of this register are programmed to any other value, the
appropriate output clock is selected to have a 'normal' 50% duty cycle
clock, and binary value of these bits combined with other bits of this
register creates postdivider ratio for the output clock (Synthesizer0 Post
Divider value P0C). The Synthesizer0 VCO frequency is divided by the
P0C value to get desired output clock frequency on selected output pins.
Note: The output clock duty-cycle may not be within specified 45% to
55% when post divider value P0C is an odd number and where
frequency of the output clock is close to the maximum output frequency
supported by hpoutclk. The worst case duty-cycle is 30% is when
synthesizer frequency is set to 1 GHz and the P0C is set to 7. If dutycycle of 45% to 55% is required, user can set synthesizer to run at 1GHz
* 8/7 and P0C to 8 which will still generate the same frequency but within
45% to 55% duty-cycle.
For odd P0C values greater than or equal to 41 ( 43, 45 ...) the dutycycle will be within 45% to 55%.
For even P0C values duty-cycle is always within 45% to 55%.
46
Microsemi Corporation
ZL30236
Data Sheet
Register_Address: 0x86:0x88
Register Name: synth0_post_div_C
Default Value: 0x000040
Type:R/W
Bit
Field
Function Name
17:16
frm_pulse_clk_sel_or_div
Description
When bits 23:20 of this register are programmed to '1111', these bits
select related clock (postdivider) within the same synthesizer 0 (frame
pulse width is equal to the related clock period):
00: clock 0 (Synth 0 postdivider A)
01: clock 1 (Synth 0 postdivider B)
10: reserved
11: clock 3 (Synth 0 postdivider D)
When bits 23:20 of this register are programmed to any other value, the
appropriate output clock is selected to have a 'normal' 50% duty cycle
clock, and binary value of these bits combined with other bits of this
register creates postdivider ratio for the output clock.
Note: It is forbidden for frame pulse to select 'itself' as its related clock
18
frm_pulse_polar_or_div
When bits 23:20 of this register are programmed to '1111', this bit
represents frame pulse polarity:
0: regular (non-inverse) polarity
1: inverse polarity
When bits 23:20 of this register are programmed to any other value, the
appropriate output clock is selected to have a 'normal' 50% duty cycle
clock, and binary value of this bit combined with other bits of this register
creates postdivider ratio for the output clock.
19
frm_pulse_type_or_div
When bits 23:20 of this register are programmed to '1111', this bit
represents frame pulse type:
0: ST-BUS type frame pulse (frame boundary straddles in the middle of
the frame pulse)
1: GCI Bus type frame pulse (frame boundary defined by the edge of the
frame pulse)
When bits 23:20 of this register are programmed to any other value, the
appropriate output clock is selected to have a 'normal' 50% duty cycle
clock, and binary value of this bit combined with other bits of this register
creates postdivider ratio for the output clock
47
Microsemi Corporation
ZL30236
Data Sheet
Register_Address: 0x86:0x88
Register Name: synth0_post_div_C
Default Value: 0x000040
Type:R/W
Bit
Field
23:20
Function Name
frm_pulse_or_div
Description
When these bits are programmed to '1111', the appropriate output clock
is selected to have a 'frame pulse' shape. Details about the frame pulse
type, polarity and frequency are specified in bits 19:0 of this register.
When these bits are programmed to any other value, the appropriate
output clock is selected to have a 'normal' 50% duty cycle clock, and
binary value of these bits combined with bits 19:0 of this register creates
postdivider ratio for the output clock (i.e. division ratio between
appropriate VCO frequency and the desired output clock frequency)
Note: Maximum division ratio for 'normal' clock is 0xEFFFFF =
15728639.
Register_Address: 0x89:0x8B
Register Name: synth0_post_div_D
Default Value: 0x000040
Type:R/W
Bit
Field
Function Name
Description
15:0
frm_pulse_period_or_div
When bits 23:20 of this register are programmed to '1111', binary value
of these bits represent number of periods of the selected related clock in
between two frame pulses
When bits 23:20 of this register are programmed to any other value, the
appropriate output clock is selected to have a 'normal' 50% duty cycle
clock, and binary value of these bits combined with other bits of this
register creates postdivider ratio for the output clock (Synthesizer0 Post
Divider value P0D). The Synthesizer0 VCO frequency is divided by the
P0D value to get desired output clock frequency on selected output pins.
Note: The output clock duty-cycle may not be within specified 45% to
55% when post divider value P0D is an odd number and where
frequency of the output clock is close to the maximum output frequency
supported by hpoutclk. The worst case duty-cycle is 30% is when
synthesizer frequency is set to 1 GHz and the P0D is set to 7. If dutycycle of 45% to 55% is required, user can set synthesizer to run at 1GHz
* 8/7 and P0D to 8 which will still generate the same frequency but within
45% to 55% duty-cycle.
For odd P0D values greater than or equal to 41 ( 43, 45 ...) the dutycycle will be within 45% to 55%.
For even P0D values duty-cycle is always within 45% to 55%.
48
Microsemi Corporation
ZL30236
Data Sheet
Register_Address: 0x89:0x8B
Register Name: synth0_post_div_D
Default Value: 0x000040
Type:R/W
Bit
Field
Function Name
17:16
frm_pulse_clk_sel_or_div
Description
When bits 23:20 of this register are programmed to '1111', these bits
select related clock (postdivider) within the same synthesizer 0 (frame
pulse width is equal to the related clock period):
00: clock 0 (Synth 0 postdivider A)
01: clock 1 (Synth 0 postdivider B)
10: clock 2 (Synth 0 postdivider C)
11: reserved
When bits 23:20 of this register are programmed to any other value, the
appropriate output clock is selected to have a 'normal' 50% duty cycle
clock, and binary value of these bits combined with other bits of this
register creates postdivider ratio for the output clock.
Note: It is forbidden for frame pulse to select 'itself' as its related clock
18
frm_pulse_polar_or_div
When bits 23:20 of this register are programmed to '1111', this bit
represents frame pulse polarity:
0: regular (non-inverse) polarity
1: inverse polarity
When bits 23:20 of this register are programmed to any other value, the
appropriate output clock is selected to have a 'normal' 50% duty cycle
clock, and binary value of this bit combined with other bits of this register
creates postdivider ratio for the output clock.
19
frm_pulse_type_or_div
When bits 23:20 of this register are programmed to '1111', this bit
represents frame pulse type:
0: ST-BUS type frame pulse (frame boundary straddles in the middle of
the frame pulse)
1: GCI Bus type frame pulse (frame boundary defined by the edge of the
frame pulse)
When bits 23:20 of this register are programmed to any other value, the
appropriate output clock is selected to have a 'normal' 50% duty cycle
clock, and binary value of this bit combined with other bits of this register
creates postdivider ratio for the output clock
49
Microsemi Corporation
ZL30236
Data Sheet
Register_Address: 0x89:0x8B
Register Name: synth0_post_div_D
Default Value: 0x000040
Type:R/W
Bit
Field
23:20
Function Name
frm_pulse_or_div
Description
When these bits are programmed to '1111', the appropriate output clock
is selected to have a 'frame pulse' shape. Details about the frame pulse
type, polarity and frequency are specified in bits 19:0 of this register.
When these bits are programmed to any other value, the appropriate
output clock is selected to have a 'normal' 50% duty cycle clock, and
binary value of these bits combined with bits 19:0 of this register creates
postdivider ratio for the output clock (i.e. division ratio between
appropriate VCO frequency and the desired output clock frequency)
Note: Maximum division ratio for 'normal' clock is 0xEFFFFF =
15728639.
Register_Address: 0x8C:0x8E
Register Name: synth1_post_div_A
Default Value: 0x000002
Type:R/W
Bit
Field
22:0
23
Function Name
Description
synth1_post_div_A
Unsigned binary value represents Synthesizer1 Post Divider value P1A.
The Synthesizer1 frequency is divided by the P1A value before being
fed to the selected output pins
reserved
This bit must be set to 0
Register_Address: 0x8F:0x91
Register Name: synth1_post_div_B
Default Value: 0x000002
Type:R/W
Bit
Field
22:0
23
Function Name
Description
synth1_post_div_B
Unsigned binary value represents Synthesizer1 Post Divider value P1B.
The Synthesizer1 frequency is divided by the P1B value before being
fed to the selected output pins
reserved
This bit must be set to 0
50
Microsemi Corporation
ZL30236
Data Sheet
Register_Address: 0x92:0x94
Register Name: synth1_post_div_C
Default Value: 0x000032
Type:R/W
Bit
Field
Function Name
Description
15:0
frm_pulse_period_or_div
When bits 23:20 of this register are programmed to '1111', binary value
of these bits represent number of periods of the selected related clock in
between two frame pulses
When bits 23:20 of this register are programmed to any other value, the
appropriate output clock is selected to have a 'normal' 50% duty cycle
clock, and binary value of these bits combined with other bits of this
register creates postdivider ratio for the output clock (Synthesizer1 Post
Divider value P1C). The Synthesizer1 VCO frequency is divided by the
P1C value to get desired output clock frequency on selected output
pins.
Note: The output clock duty-cycle may not be within specified 45% to
55% when post divider value P1C is an odd number and where
frequency of the output clock is close to the maximum output frequency
supported by hpoutclk. The worst case duty-cycle is 30% is when
synthesizer frequency is set to 1 GHz and the P1C is set to 7. If dutycycle of 45% to 55% is required, user can set synthesizer to run at 1GHz
* 8/7 and P1C to 8 which will still generate the same frequency but
within 45% to 55% duty-cycle.
For odd P1C values greater than or equal to 41 ( 43, 45 ...) the dutycycle will be within 45% to 55%.
For even P1C values duty-cycle is always within 45% to 55%.
17:16
frm_pulse_clk_sel_or_div
When bits 23:20 of this register are programmed to '1111', these bits
select related clock (postdivider) within the same synthesizer 1 (frame
pulse width is equal to the related clock period):
00: clock 0 (Synth 1 postdivider A)
01: clock 1 (Synth 1 postdivider B)
10: reserved
11: clock 3 (Synth 1 postdivider D)
When bits 23:20 of this register are programmed to any other value, the
appropriate output clock is selected to have a 'normal' 50% duty cycle
clock, and binary value of these bits combined with other bits of this
register creates postdivider ratio for the output clock.
Note: It is forbidden for frame pulse to select 'itself' as its related clock
51
Microsemi Corporation
ZL30236
Data Sheet
Register_Address: 0x92:0x94
Register Name: synth1_post_div_C
Default Value: 0x000032
Type:R/W
Bit
Field
18
Function Name
frm_pulse_polar_or_div
Description
When bits 23:20 of this register are programmed to '1111', this bit
represents frame pulse polarity:
0: regular (non-inverse) polarity
1: inverse polarity
When bits 23:20 of this register are programmed to any other value, the
appropriate output clock is selected to have a 'normal' 50% duty cycle
clock, and binary value of this bit combined with other bits of this register
creates postdivider ratio for the output clock.
19
frm_pulse_type_or_div
When bits 23:20 of this register are programmed to '1111', this bit
represents frame pulse type:
0: ST-BUS type frame pulse (frame boundary straddles in the middle of
the frame pulse)
1: GCI Bus type frame pulse (frame boundary defined by the edge of the
frame pulse)
When bits 23:20 of this register are programmed to any other value, the
appropriate output clock is selected to have a 'normal' 50% duty cycle
clock, and binary value of this bit combined with other bits of this register
creates postdivider ratio for the output clock
23:20
frm_pulse_or_div
When these bits are programmed to '1111', the appropriate output clock
is selected to have a 'frame pulse' shape. Details about the frame pulse
type, polarity and frequency are specified in bits 19:0 of this register.
When these bits are programmed to any other value, the appropriate
output clock is selected to have a 'normal' 50% duty cycle clock, and
binary value of these bits combined with bits 19:0 of this register creates
postdivider ratio for the output clock (i.e. division ratio between
appropriate VCO frequency and the desired output clock frequency)
Note: Maximum division ratio for 'normal' clock is 0xEFFFFF =
15728639.
52
Microsemi Corporation
ZL30236
Data Sheet
Register_Address: 0x95:0x97
Register Name: synth1_post_div_D
Default Value: 0x000032
Type:R/W
Bit
Field
Function Name
Description
15:0
frm_pulse_period_or_div
When bits 23:20 of this register are programmed to '1111', binary value
of these bits represent number of periods of the selected related clock in
between two frame pulses
When bits 23:20 of this register are programmed to any other value, the
appropriate output clock is selected to have a 'normal' 50% duty cycle
clock, and binary value of these bits combined with other bits of this
register creates postdivider ratio for the output clock (Synthesizer1 Post
Divider value P1D). The Synthesizer1 VCO frequency is divided by the
P1D value to get desired output clock frequency on selected output pins.
Note: The output clock duty-cycle may not be within specified 45% to
55% when post divider value P1D is an odd number and where
frequency of the output clock is close to the maximum output frequency
supported by hpoutclk. The worst case duty-cycle is 30% is when
synthesizer frequency is set to 1 GHz and the P1D is set to 7. If dutycycle of 45% to 55% is required, user can set synthesizer to run at 1GHz
* 8/7 and P1D to 8 which will still generate the same frequency but within
45% to 55% duty-cycle.
For odd P1D values greater than or equal to 41 ( 43, 45 ...) the dutycycle will be within 45% to 55%.
For even P1D values duty-cycle is always within 45% to 55%.
17:16
frm_pulse_clk_sel_or_div
When bits 23:20 of this register are programmed to '1111', these bits
select related clock (postdivider) within the same synthesizer 1 (frame
pulse width is equal to the related clock period):
00: clock 0 (Synth 1 postdivider A)
01: clock 1 (Synth 1 postdivider B)
10: clock 2 (Synth 1 postdivider C)
11: reserved
When bits 23:20 of this register are programmed to any other value, the
appropriate output clock is selected to have a 'normal' 50% duty cycle
clock, and binary value of these bits combined with other bits of this
register creates postdivider ratio for the output clock.
Note: It is forbidden for frame pulse to select 'itself' as its related clock
53
Microsemi Corporation
ZL30236
Data Sheet
Register_Address: 0x95:0x97
Register Name: synth1_post_div_D
Default Value: 0x000032
Type:R/W
Bit
Field
18
Function Name
frm_pulse_polar_or_div
Description
When bits 23:20 of this register are programmed to '1111', this bit
represents frame pulse polarity:
0: regular (non-inverse) polarity
1: inverse polarity
When bits 23:20 of this register are programmed to any other value, the
appropriate output clock is selected to have a 'normal' 50% duty cycle
clock, and binary value of this bit combined with other bits of this register
creates postdivider ratio for the output clock.
19
frm_pulse_type_or_div
When bits 23:20 of this register are programmed to '1111', this bit
represents frame pulse type:
0: ST-BUS type frame pulse (frame boundary straddles in the middle of
the frame pulse)
1: GCI Bus type frame pulse (frame boundary defined by the edge of the
frame pulse)
When bits 23:20 of this register are programmed to any other value, the
appropriate output clock is selected to have a 'normal' 50% duty cycle
clock, and binary value of this bit combined with other bits of this register
creates postdivider ratio for the output clock
23:20
frm_pulse_or_div
When these bits are programmed to '1111', the appropriate output clock
is selected to have a 'frame pulse' shape. Details about the frame pulse
type, polarity and frequency are specified in bits 19:0 of this register.
When these bits are programmed to any other value, the appropriate
output clock is selected to have a 'normal' 50% duty cycle clock, and
binary value of these bits combined with bits 19:0 of this register creates
postdivider ratio for the output clock (i.e. division ratio between
appropriate VCO frequency and the desired output clock frequency)
Note: Maximum division ratio for 'normal' clock is 0xEFFFFF =
15728639.
54
Microsemi Corporation
ZL30236
Data Sheet
Register_Address: 0xB0
Register Name: hp_diff_en
Default Value: 0x55
Type:R/W
Bit
Field
7:0
Function Name
hp_diff_en
Description
Set high to enable corresponding high performance differential output.
Set low to tristate the corresponding output.
xxxxxxx1: enables hpdiff0_p/n
xxxxx1xx: enables hpdiff1_p/n
xxx1xxxx: enables hpdiff2_p/n
x1xxxxxx: enables hpdiff3_p/n
Register_Address: 0xB1
Register Name: hp_cmos_en
Default Value: 0x0F
Type:R/W
Bit
Field
3:0
Function Name
hp_cmos_en
Description
Set high to enable corresponding high performance output. Set low to
tristate the corresponding output.
xxx1: enables hpout0
xx1x: enables hpout1
x1xx: enables hpout2
1xxx: enables hpout3
7:4
reserved
reserved
55
Microsemi Corporation
ZL30236
Data Sheet
Register_Address: 0xB8
Register Name: synth1_0_stop_clock
Default Value: 0x00
Type:R/W
Bit
Field
Function Name
Description
1:0
synth0_post_div_C_stop
Appropriate setting of these bits will cause Synthesizer0 Post Divider C
to stop clock at either rising or falling edge.
Selection:
00 - 01: continuous run (stop clock function is disabled)
10: stop hpoutclk0 at falling edge (output stays low)
11: stop hpoutclk0 at rising edge (output stays high)
Note:
This setting assumes that user has selected Synthesizer0 Post Divider C
as the source for hpoutclk0
3:2
synth0_post_div_D_stop
Appropriate setting of these bits will cause Synthesizer0 Post Divider D
to stop clock at either rising or falling edge.
Selection:
00 - 01: continuous run (stop clock function is disabled)
10: stop hpoutclk1 at falling edge (output stays low)
11: stop hpoutclk1 at rising edge (output stays high)
Note:
This setting assumes that user has selected Synthesizer0 Post Divider D
as the source for hpoutclk1
5:4
synth1_post_div_C_stop
Appropriate setting of these bits will cause Synthesizer1 Post Divider C
to stop clock at either rising or falling edge.
Selection:
00 - 01: continuous run (stop clock function is disabled)
10: stop hpoutclk2 at falling edge (output stays low)
11: stop hpoutclk2 at rising edge (output stays high)
Note:
This setting assumes that user has selected Synthesizer31 Post Divider
C as the source for hpoutclk2
7:6
synth1_post_div_D_stop
Appropriate setting of these bits will cause Synthesizer1 Post Divider D
to stop clock at either rising or falling edge.
Selection:
00 - 01: continuous run (stop clock function is disabled)
10: stop hpoutclk3 at falling edge (output stays low)
11: stop hpoutclk3 at rising edge (output stays high)
Note:
This setting assumes that user has selected Synthesizer1 Post Divider D
as the source for hpoutclk3
56
Microsemi Corporation
ZL30236
Data Sheet
Register_Address: 0xB9
Register Name:sync_fail_flag_status
Default Value: 0x00
Type:StickyR
Bit
Field
0
Function Name
Synth0_syncFail_flag
Description
When high, this bit indicates that Synthesizer 0 has lost lock. If this
status bit appears set after clearing Synth0_ClearSyncFail_flag (register
at address 0xBA), it is indication that Synthesizer 0 has lost lock,
therefore generating wrong output frequency.
Note: This bit will be set upon power up or device reset.
1
7:2
Synth1_syncFail_flag
Same description as above but for Synth1
reserved
Leave as default.
Register_Address: 0xBA
Register Name:clear_sync_fail_flag
Default Value: 0x00
Type:R/W
Bit
Field
Function Name
0
Synth0_clearSyncFail_flag
Description
When high, this bit clears sticky Synth0_syncFail_flag.
Note: after clearing Synth0_syncFail_flag, this bit must be set low for
normal device operation
1
7:2
Synth1_clearSyncFail_flag
Same description as above but for Synth1
reserved
Leave as default.
57
Microsemi Corporation
ZL30236
Data Sheet
Register_Address: 0xBF:0xC0
Register Name:phase_shift_s0_postdiv_c
Default Value: 0x0000
Type:R/W
Bit
Field
Function Name
Description
12:0
phase_shift_s0_postdiv_c
2's complement binary value of these bits represent phase shift in
steps of one period of Synthesizer0 frequency for all clocks coming
from Synthesizer0 Post Divider C (0: no shift, -1: delay output clock for
1 period, 1: advance output for 1 period, and so on)
15:13
quad_shift_s0_postdiv_c
These bits select quadrature phase shift (in 45 degrees step, from 135 to +135 degrees) for all clocks coming from Synthesizer0 Post
Divider C.
000: 0 degrees (no shift)
001: -45 degrees
010: -90 degrees
011: -135 degrees
100: -180 (or 180) degrees
101: 135 degrees
110: 90 degrees
111: 45 degrees
Register_Address: 0xC1:0xC2
Register Name:phase_shift_s0_postdiv_d
Default Value: 0x0000
Type:R/W
Bit
Field
Function Name
Description
12:0
phase_shift_s0_postdiv_d
2's complement binary value of these bits represent phase shift in
steps of one period of Synthesizer0 frequency for all clocks coming
from Synthesizer0 Post Divider D (0: no shift, -1: delay output clock for
1 period, 1: advance output for 1 period, and so on)
58
Microsemi Corporation
ZL30236
Data Sheet
Register_Address: 0xC1:0xC2
Register Name:phase_shift_s0_postdiv_d
Default Value: 0x0000
Type:R/W
Bit
Field
15:13
Function Name
quad_shift_s0_postdiv_d
Description
These bits select quadrature phase shift (in 45 degrees step, from 135 to +135 degrees) for all clocks coming from Synthesizer0 Post
Divider D.
000: 0 degrees (no shift)
001: -45 degrees
010: -90 degrees
011: -135 degrees
100: -180 (or 180) degrees
101: 135 degrees
110: 90 degrees
111: 45 degrees
Register_Address: 0xC3
Register Name:xo_or_crystal_sel
Default Value: 0x00
Type:R/W
Bit
Field
0
7:1
Function Name
Description
xo_or_crystal_sel
0: enables OSCo driver
1: disables OSCo driver
Set to 1 when xo is used as master clock.
Set to 0 when crystal is used as master clock.
Reserved
Leave as default
Register_Address: 0xC6
Register Name:Chip_revision_2
Default Value: 0x03
Type:R/W
Bit
Field
7:o
Function Name
Chip_revision_2
Description
Chip revision number = 0b00000011
Note:also see Chip_revision bits in Register _Address: 0x00 for full chip
revision information
59
Microsemi Corporation
ZL30236
Data Sheet
Register_Address: 0xC7:0xC8
Register Name:phase_shift_s1_postdiv_c
Default Value: 0x0000
Type:R/W
Bit
Field
Function Name
Description
12:0
phase_shift_s1_postdiv_c
2's complement binary value of these bits represent phase shift in steps
of one period of Synthesizer1 frequency for all clocks coming from
Synthesizer1 Post Divider C (0: no shift, -1: delay output clock for 1
period, 1: advance output for 1 period, and so on)
15:13
quad_shift_s1_postdiv_c
These bits select quadrature phase shift (in 45 degrees step, from -135
to +135 degrees) for all clocks coming from Synthesizer1 Post Divider
C.
000: 0 degrees (no shift)
001: -45 degrees
010: -90 degrees
011: -135 degrees
100: -180 (or 180) degrees
101: 135 degrees
110: 90 degrees
111: 45 degrees
Register_Address: 0xC9:0xCA
Register Name:phase_shift_s1_postdiv_d
Default Value: 0x0000
Type:R/W
Bit Field
Function Name
Description
12:0
phase_shift_s1_postdiv_d
2's complement binary value of these bits represent phase shift in steps
of one period of Synthesizer1 frequency for all clocks coming from
Synthesizer1 Post Divider D (0: no shift, -1: delay output clock for 1
period, 1: advance output for 1 period, and so on)
60
Microsemi Corporation
ZL30236
Data Sheet
Register_Address: 0xC9:0xCA
Register Name:phase_shift_s1_postdiv_d
Default Value: 0x0000
Type:R/W
Bit Field
15:13
Function Name
quad_shift_s1_postdiv_d
Description
These bits select quadrature phase shift (in 45 degrees step, from -135
to +135 degrees) for all clocks coming from Synthesizer1 Post Divider D.
000: 0 degrees (no shift)
001: -45 degrees
010: -90 degrees
011: -135 degrees
100: -180 (or 180) degrees
101: 135 degrees
110: 90 degrees
111: 45 degrees
Register_Address: 0xE0
Register Name:gpio_function_pin0
Default Value: 0x00
Type:R/W
Bit Field
6:0
7
Function Name
Description
gpio_pin0_table_address
Unsigned binary value of these bits represents bit address in the
control or status table, depending on 'GPIO0 control or status select'
bit. The control and status table consist of 128 bits each.
Default: GPIO unused.
gpio_pin0_con_or_stat_sel
Selects whether GPIO0 is input (control) pin or output (status) pin.
Selection:
0 = control
1 = status
61
Microsemi Corporation
ZL30236
Data Sheet
Register_Address: 0xE1
Register Name:gpio_function_pin1
Default Value: 0x00
Type:R/W
Bit
Field
6:0
7
Function Name
Description
gpio_pin1_table_address
Unsigned binary value of these bits represents bit address in the
control or status table, depending on 'GPIO1 control or status select'
bit. The control and status table consist of 128 bits each.
Default: GPIO unused.
gpio_pin1_con_or_stat_sel
Selects whether GPIO1 is input (control) pin or output (status) pin.
Selection:
0 = control
1 = status
62
Microsemi Corporation
ZL30236
Data Sheet
Register_Address: 0xE2
Register Name:gpio_function_pin2
Default Value: 0x60
Type:R/W
Bit
Field
6:0
7
Function Name
Description
gpio_pin2_table_address
Unsigned binary value of these bits represents bit address in the
control or status table, depending on 'GPIO2 control or status select'
bit. The control and status table consist of 128 bits each.
Default: Enable hpdiff0.
gpio_pin2_con_or_stat_sel
Selects whether GPIO2 is input (control) pin or output (status) pin.
Selection:
0 = control
1 = status
Register_Address: 0xE3
Register Name:gpio_function_pin3
Default Value: 0x00
Type:R/W
Bit
Field
6:0
7
Function Name
Description
gpio_pin3_table_address
Unsigned binary value of these bits represents bit address in the
control or status table, depending on 'GPIO3 control or status select'
bit. The control and status table consist of 128 bits each.
Default: GPIO unused.
gpio_pin3_con_or_stat_sel
Selects whether GPIO3 is input (control) pin or output (status) pin.
Selection:
0 = control
1 = status
63
Microsemi Corporation
ZL30236
Data Sheet
Register_Address: 0xE4
Register Name:gpio_function_pin4
Default Value: 0x00
Type:R/W
Bit
Field
6:0
7
Function Name
Description
gpio_pin4_table_address
Unsigned binary value of these bits represents bit address in the
control or status table, depending on 'GPIO4 control or status select'
bit. The control and status table consist of 128 bits each.
Default: GPIO unused.
gpio_pin4_con_or_stat_sel
Selects whether GPIO4 is input (control) pin or output (status) pin.
Selection:
0 = control
1 = status
Register_Address: 0xE5
Register Name:gpio_function_pin5
Default Value: 0x00
Type:R/W
Bit Field
6:0
7
Function Name
Description
gpio_pin5_table_address
Unsigned binary value of these bits represents bit address in the
control or status table, depending on 'GPIO5 control or status select'
bit. The control and status table consist of 128 bits each.
Default: GPIO unused.
gpio_pin5_con_or_stat_sel
Selects whether GPIO5 is input (control) pin or output (status) pin.
Selection:
0 = control
1 = status
Register_Address: 0xE6
Register Name:gpio_function_pin6
Default Value: 0x00
Type:R/W
Bit
Field
6:0
Function Name
gpio_pin6_table_address
Description
Unsigned binary value of these bits represents bit address in the
control or status table, depending on 'GPIO6 control or status select'
bit. The control and status table consist of 128 bits each.
Default: GPIO unused.
64
Microsemi Corporation
ZL30236
Data Sheet
Register_Address: 0xE6
Register Name:gpio_function_pin6
Default Value: 0x00
Type:R/W
Bit
Field
Function Name
7
gpio_pin6_con_or_stat_sel
Description
Selects whether GPIO6 is input (control) pin or output (status) pin.
Selection:
0 = control
1 = status
Register_Address: 0xE7
Register Name:gpio_function_pin7
Default Value: 0x00
Type:R/W
Bit
Field
6:0
7
Function Name
Description
gpio_pin7_table_address
Unsigned binary value of these bits represents bit address in the
control or status table, depending on 'GPIO7 control or status select'
bit. The control and status table consist of 128 bits each.
Default: GPIO unused.
gpio_pin7_con_or_stat_sel
Selects whether GPIO7 is input (control) pin or output (status) pin.
Selection:
0 = control
1 = status
Register_Address: 0xE8
Register Name:gpio_function_pin8
Default Value: 0x00
Type:R/W
Bit
Field
6:0
7
Function Name
Description
gpio_pin8_table_address
Unsigned binary value of these bits represents bit address in the
control or status table, depending on 'GPIO8 control or status select'
bit. The control and status table consist of 128 bits each.
Deafault:GPIO unused.
gpio_pin8_con_or_stat_sel
Selects whether GPIO8 is input (control) pin or output (status) pin.
Selection:
0 = control
1 = status
65
Microsemi Corporation
Register_Address: 0xE9
Register Name:gpio_function_pin9
Default Value: 0x00
Type:R/W
Bit
Field
6:0
7
Function Name
Description
gpio_pin9_table_address
Unsigned binary value of these bits represents bit address in the
control or status table, depending on 'GPIO9 control or status select'
bit. The control and status table consist of 128 bits each.
Deafault:GPIO unused.
gpio_pin9_con_or_stat_sel
Selects whether GPIO9 is input (control) pin or output (status) pin.
Selection:
0 = control
1 = status
Register_Address: 0xEA
Register Name:gpio_function_pin10
Default Value: 0x00
Type:R/W
Bit
Field
Function Name
6:0
gpio_pin10_table_address
Unsigned binary value of these bits represents bit address in the
control or status table, depending on 'GPIO10 control or status select'
bit. The control and status table consist of 128 bits each.
Default: GPIO unused
7
gpio_pin10_con_or_stat_s
el
Selects whether GPIO10 is input (control) pin or output (status) pin.
Selection:
0 = control
1 = status
Description
ZL30236
Data Sheet
Register_Address: 0xEB
Register Name:gpio_function_pin11
Default Value: 0x00
Type:R/W
Bit
Field
6:0
7
Function Name
Description
gpio_pin11_table_address
Unsigned binary value of these bits represents bit address in the
control or status table, depending on 'GPIO11 control or status select'
bit. The control and status table consist of 128 bits each.
Default:GPIO unused
gpio_pin11_con_or_stat_sel
Selects whether GPIO11 is input (control) pin or output (status) pin.
Selection:
0 = control
1 = status
Register_Address: 0xF7
Register Name:spurs_suppression
Default Value: 0x00
Type:R/W
Bit
Field
7:0
Function Name
spurs_suppression
Description
This register is used for spurs suppression. Depending on the
synthesizer configuration GUI will generate recommended value.
Please refer to GUI for recommended value that should be written to
this register. When the spurs_supression register is changed, the
ZL30236 requires 200msec to reconfigure itself, no reads or writes to
the device are permitted during this reconfiguration period. The
spurs_suppression register should only be written with values
recommended by the GUI and it should only be written if a
24.576MHz master clock oscillator or crystal resonator is being used
67
Microsemi Corporation
ZL30236
68
Microsemi Corporation
Data Sheet
ZL30236
9.0
Data Sheet
AC and DC Electrical Characteristics
Absolute Maximum Ratings*
Parameter
Symbol
Min.
Max.
Units
VDD_R
-0.5
4.6
V
VCORE_R
-0.5
2.5
V
1
Supply voltage
2
Core supply voltage
3
Voltage on any digital pin
VPIN
-0.5
6
V
4
Voltage on osci and osco pin
VOSC
-0.3
VDD + 0.3
V
5
Storage temperature
TST
-55
125
°C
* Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied.
* Voltages are with respect to ground (GND) unless otherwise stated
Recommended Operating Conditions*
Characteristics
Sym.
Min.
Typ.
Max.
Units
1
Supply voltage
VDD-IO
AVDD
3.135
3.30
3.465
V
2
Core supply voltage
VCORE
1.71
1.80
1.89
V
3
Operating temperature
TA
-40
25
85
°C
4
Input voltage
VDD-IO
2.97
3.30
3.63
V
* Voltages are with respect to ground (GND) unless otherwise stated
DC Electrical Characteristics - Power - Core
Characteristics
1
2
Core supply current (Vcore)
Current for each HP Synthesis Engine
Sym.
Typ.
Max.
Units
ICORE (Vdd 3.3V)
46
48
mA
ICORE (Vdd 1.8V)
102
109
mA
ISYN (Vdd 3.3V)
57
73
mA
ISYN(Vdd 1.8V)
0.2
1
mA
Notes
DC Electrical Characteristics - Power - High Performance Outputs
Characteristics
1
Sym.
Typ.
Max.
Units
Notes
Phpdiff(Vdd 3.3V)
85
91
mW
Including power
to biasing and
load resistors
RL = 50
Power for each hpdiff clock driver
69
Microsemi Corporation
ZL30236
Data Sheet
DC Electrical Characteristics - Power - High Performance Outputs
Characteristics
2
Power for each hpdiff clock driver
minus power dissipated in the
biasing and load resistors.
3
Power for each hpdiff clock driver
(reduced power mode)
4
Power for each hpdiff clock driver
minus power dissipated in the load
resistor. (reduced power mode)
5
Power for each output divider of high
performance synthesizers (enabled
if one of two differential outputs
assigned to it is enabled).
6
Sym.
Typ.
Max.
Units
Phpdiff(Vdd 3.3V)
36
42
mW
Without power
to biasing and
load resistors
RL = 50
Phpdifflp(Vdd 3.3V)
80
86
mW
Including power
to biasing and
load resistors
RL = 50
Phpdifflp(Vdd 3.3V)
31
37
mW
Without power
to biasing and
load resistors
RL = 50
Pdiv(Vdd 3.3V)
17
40
mW
Phpout(Vdd 3.3V)
17+ 7
40+36
mW
155.52 MHz
output
10 pF load
fixed power
(due to output
divider) +
variable power
(proportional to
frequency and
load)
Max.
Units
Notes
Power for each hpoutclk clock driver
Notes
* Supply voltage and operating temperature are as per Recommended Operating Conditions.
* Voltages are with respect to ground (GND) unless otherwise state.
DC Electrical Characteristics - Inputs
Characteristics
1
CMOS high-level input voltage
Sym.
Min.
VCIH
0.7·VDD
Typ.
V
-IO
2
CMOS low-level input voltage
VCIL
0.3·VDD
V
-IO
3
CMOS Input leakage current
-10
IIL
70
Microsemi Corporation
10
μA
VI = VDD or 0 V
ZL30236
Data Sheet
AC/DC Electrical Characteristics - OSCi Input
Characteristics
Sym.
Min.
2.0
1
CMOS high-level input voltage
VCIH
2
CMOS low-level input voltage
VCIL
3
Input leakage current
4
Duty Cycle
IIL
Typ.
Max.
Units
Notes
V
0.8
V
-10
10
μA
40
60
%
VI = VDD or 0 V
DC Electrical Characteristics - High Performance Outputs
Characteristics
Sym.
Min.
1
HPCMOS High-level output voltage
VOH
0.8AVDD
2
HPCMOS Low-level output voltage
VOL
3
LVPECL: High-level output voltage
VOH_LV
5
LVPECL: Low-level output voltage
LVPECL: Differential output voltage*
Max.
Units
Notes
V
IOH = 2mA
CL = 5pF
0.2AVDD
V
IOL = 2mA
CL = 5pF
AVDD
- 1.12
AVDD
- 1.00
AVDD 0.88
V
RL = 50to
AVDD - 2V,
CL = 1pF
AVDD
- 1.71
AVDD 1.55
V
ECL
AVDD
- 1.81
RL = 50to
AVDD- 2V,
CL = 1pF
VOD_LV
0.53
0.67
0.80
V
RL = 50to
AVDD- 2V,
CL = 1pF
PECL
4
Typ.
VOL_LVP
PECL
* Output swing is guaranteed for frequency up to 720MHz, it may decrease by 50mv if the frequency is greater than 720 MHz
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Microsemi Corporation
ZL30236
Data Sheet
AC Electrical Characteristics* - Output Timing Parameters Measurement Voltage Levels (see Figure 22)
Characteristics
Sym.
CMOS
LVPECL
Units
VT-CMOS
VT-LVPECL
VT-CML
0.5VDD
0.5VOD_LVPECL
V
1
Threshold Voltage
2
Rise and Fall Threshold
Voltage High
VHM
0.7VDD
0.8VOD_LVPECL
V
3
Rise and Fall Threshold
Voltage Low
VLM
0.3VDD
0.2VOD_LVPECL
V
* Supply voltage and operating temperature are as per Recommended Operating Conditions
* Voltages are with respect to ground (GND) unless otherwise stated
Timing Reference Points
V HM
VT
VLM
ALL SIGNALS
tIRF, tORF
tIRF, tORF
Figure 22 - Timing Parameter Measurement Voltage Levels
72
Microsemi Corporation
ZL30236
Data Sheet
AC Electrical Characteristics* - Outputs (see Figure 23).
Characteristics
Sym.
Min.
Typ.
Max.
Units
1
Clock skew between outputs
tOUT2OUTD
-1
0
+1
ns
2
Output clock Duty Cycle
tPWH, tPWL
45%
50%
55%
Duty
Cycle
3
hpdiff (LVPECL) Output clock rise or
fall time
tr / tf
265
370
515
ps
4
hpoutclk (LVCMOS) clock rise and fall
time
tr / tf
620
950
1490
ps
5
Output Clock Frequency (hpdiff)
Fhpdiff
750
MHz
6
Output Clock Frequency (hpoutclk)
Fhpout
177.5
MHz
* Supply voltage and operating temperature are as per Recommended Operating Conditions
tPWH
hpclkout0
tPWL
tOUT2OUTD
hpclkout(n)
Figure 23 - Output Timing Referenced To hpclkout0/clkout0
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Microsemi Corporation
Notes
10pF
load
ZL30236
Data Sheet
Functional waveforms and timing characteristics for the LSB first mode are shown in Figure 24, and Figure 25
describe the MSB first mode. Table 5 shows the timing specifications.
Specification
Name
Min.
Max.
Units
sck period
tcyc
124
ns
sck pulse width low
tclkl
62
ns
sck pulse width high
tclkh
62
ns
si setup (write) from sck rising
trxs
10
ns
si hold (write) from sck rising
trxh
10
ns
so delay (read) from sck falling
txd
25
ns
cs_b setup from sck falling (LSB first)
tcssi
20
ns
cs_b setup from sck rising (MSB first)
tcssm
20
ns
cs_b hold from sck falling (MSB first)
tcshm
10
ns
cs_b hold from sck rising (LSB first)
tcshi
10
ns
cs_b to output high impedance
tohz
60
ns
Table 5 - Serial Peripheral Interface Timing
si
tclkh
trxh
trxs
sck
tcssi
tcshi
tcyc
tclkl
cs_b
txd
so
Figure 24 - Serial Peripheral Interface Timing - LSB First Mode
74
Microsemi Corporation
tohz
ZL30236
Data Sheet
si
tclkh
trxh
trxs
sck
tclkl
tcyc
tcssm
txd
tcshi
cs_b
tohz
so
Figure 25 - Serial Peripheral Interface Timing - MSB First Mode
75
Microsemi Corporation
ZL30236
Data Sheet
The timing specification for the I2C interface is shown in Figure 26 and Table 6.
Specification
Name
Min.
Typ.
Max.
Units
SCL clock frequency
fSCL
0
Hold time START condition
tHD:STA
0.6
us
Low period SCL
tLOW
1.3
us
Hi period SCL
tHIGH
0.6
us
Setup time START condition
tSU:STA
0.6
us
Data hold time
tHD:DAT
0
Data setup time
tSU:DAT
100
Rise time
tr
Fall time
tf
20 +
0.1Cb
Setup time STOP condition
tSU:STO
0.6
us
Bus free time between
STOP/START
tBUF
1.3
us
Pulse width of spikes which
must be suppressed by the
input filter
tSP
0
400
0.9
Note
kHz
us
ns
ns
250
Max capacitance for each I/O
pin
Determined by choice of pullup resistor
ns
50
ns
10
pF
Table 6 - I2C Serial Microport Timing
SDA
tSU:DAT
tf
tLOW
tf
tHD:STA
tr
tSP
tBUF
SCL
tHD:STA
S
tHD:DAT
tHIGH
tSU:STA
tSU:STO
Sr
Figure 26 - I2C Serial Microport Timing
76
Microsemi Corporation
P
S
ZL30236
10.0
Performance Characterization
10.1
Output Clocks RMS Jitter Generation
Output Frequency
622.08 MHz
Data Sheet
Jitter
Measurement
Filter
Max.
Units
50kHz - 80MHz
0.63
psrms
Notes
12kHz - 20MHz
0.72
psrms
Table 7 - Jitter Generation Specifications - HPDIFF Outputs
Output Frequency
Jitter
Measurement
Filter
Max.
Units
25 MHz
12KHz - 5MHz
0.99
psrms
77.76 MHz
12KHz - 20MHz
1.04
psrms
125 MHz
12KHz - 20MHz
0.85
psrms
156.25 MHz
10.2
Notes
12KHz - 20MHz
0.92
psrms
Table 8 - Jitter Generation Specifications - HPOUT Outputs
Output Clocks Cycle-to-Cycle Jitter Generation
Output Frequency
Max.
Units
125 MHz
29.2
psPK-PK
156.25 MHz
28.2
psPK-PK
212.5 MHz
27.9
psPK-PK
Table 9 - Jitter Generation Specifications - HPDIFF Outputs
77
Microsemi Corporation
Notes
ZL30236
11.0
Data Sheet
Thermal Characteristics
Parameter
Symbol
Test Condition
Value
Unit
Junction to Ambient Thermal Resistance
ja
Still Air
1 m/s
2 m/s
29.7
26.5
25.3
oC/W
Junction to Case Thermal Resistance
jc
7.7
oC/W
Tjmax
125
oC
TA
85
oC
Maximum Junction Temperature *
Maximum Ambient Temperature
* Proper thermal management must be practiced to ensure that Tjmax is not exceeded
Table 10 - Thermal Data
78
Microsemi Corporation
ZL30236
12.0
Mechanical Drawing
79
Microsemi Corporation
Data Sheet
ZL30236
13.0
Package Markings
13.1
100-pin BGA. Package Top Mark Format
Data Sheet
Figure 27 - Non-customized Device Top Mark
Figure 28 - Custom Factory Programmed Device Top Mark
Line
Characters
Description
1
ZL30236
Part Number
2
F
Fab Code
2
R
Product Revision Code
2
e1
Denotes Pb-Free Package
3
YY
Last Two Digits of the Year of Encapsulation
3
WW
Work Week of Assembly
3
A
Assembly Location Code
3
ZZ
Assembly Lot Sequence
4
CCID
Custom Programming Identification Code
4
WP
Work Week of Programming
Table 11 - Package Marking Legend
80
Microsemi Corporation
Microsemi Corporation (Nasdaq: MSCC) offers a comprehensive portfolio of semiconductor
and system solutions for communications, defense & security, aerospace and industrial
markets. Products include high-performance and radiation-hardened analog mixed-signal
integrated circuits, FPGAs, SoCs and ASICs; power management products; timing and
synchronization devices and precise time solutions, setting the world’s standard for time; voice
processing devices; RF solutions; discrete components; security technologies and scalable
anti-tamper products; Power-over-Ethernet ICs and midspans; as well as custom design
capabilities and services. Microsemi is headquartered in Aliso Viejo, Calif., and has
approximately 3,400 employees globally. Learn more at www.microsemi.com.
Microsemi Corporate Headquarters
One Enterprise, Aliso Viejo,
CA 92656 USA
Within the USA: +1 (800) 713-4113
Outside the USA: +1 (949) 380-6100
Sales: +1 (949) 380-6136
Fax: +1 (949) 215-4996
E-mail: sales.support@microsemi.com
© 2015 Microsemi Corporation. All
rights reserved. Microsemi and the
Microsemi logo are trademarks of
Microsemi Corporation. All other
trademarks and service marks are the
property of their respective owners.
Microsemi makes no warranty, representation, or guarantee regarding the information contained herein or
the suitability of its products and services for any particular purpose, nor does Microsemi assume any
liability whatsoever arising out of the application or use of any product or circuit. The products sold
hereunder and any other products sold by Microsemi have been subject to limited testing and should not
be used in conjunction with mission-critical equipment or applications. Any performance specifications are
believed to be reliable but are not verified, and Buyer must conduct and complete all performance and
other testing of the products, alone and together with, or installed in, any end-products. Buyer shall not rely
on any data and performance specifications or parameters provided by Microsemi. It is the Buyer's
responsibility to independently determine suitability of any products and to test and verify the same. The
information provided by Microsemi hereunder is provided "as is, where is" and with all faults, and the entire
risk associated with such information is entirely with the Buyer. Microsemi does not grant, explicitly or
implicitly, to any party any patent rights, licenses, or any other IP rights, whether with regard to such
information itself or anything described by such information. Information provided in this document is
proprietary to Microsemi, and Microsemi reserves the right to make any changes to the information in this
document or to any products and services at any time without notice.
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