ZL30256LFG7

ZL30256 3-Channel, 10-Input, 18-Output General-Purpose Jitter Attenuator Data Sheet Block Diagram page 7. Register Map section 9.3 October 2020 Features Ordering Information • One, Two or Three DPLL Channels • Programmable bandwidth, 14Hz to 470Hz ZL30256LFG7 • Freerun or holdover on loss of all inputs 80-lead LGA Trays NiAu (Pb-free) Package size: 11 x 11 mm • Hitless reference switching -40C to +85C • High-resolution holdover averaging • Per-DPLL phase adjustment, 1ps resolution • Programmable tracking range, phase-slope limiting, frequency-change limiting and other advanced features • Precise output alignment circuitry and peroutput phase adjustment • Per-output enable/disable and glitchless start/stop (stop high or low) • Input Clocks • Accepts up to 10 differential or CMOS inputs • Local Oscillator • Any input frequency from 1kHz to 900MHz • Operates from a single low-cost XO: 23.7525MHz, 47.5-50MHz, 114.285-125MHz • Per-input activity and frequency monitoring • Automatic or manual reference switching • General Features • Revertive or nonrevertive switching • Input-input phase measurement, 1ps resolution • Automatic self-configuration at power-up from internal Flash memory • Input-DPLL phase measurement, 1ps resolution • Input-to-output alignment