ZL30267LDG1

Register Map: Section 6.2 ZL30264-ZL30267 2-APLL, 6- or 10-Output Any-to-Any Clock Multiplier and Frequency Synthesizer Data Sheet September 2020 Features Ordering Information • Four Flexible Input Clocks ZL30264LDG1 ZL30264LDF1 ZL30265LDG1 ZL30265LDF1 ZL30266LDG1 ZL30266LDF1 ZL30267LDG1 ZL30267LDF1 • One crystal/CMOS input • Two differential/CMOS inputs • One single-ended/CMOS input • Any input frequency from 9.72MHz to 1.25GHz (300MHz max for CMOS) ext. EEPROM ext. EEPROM int. EEPROM int. EEPROM ext. EEPROM ext. EEPROM int. EEPROM int. EEPROM 6 Outputs 6 Outputs 6 Outputs 6 Outputs 10 Outputs 10 Outputs 10 Outputs 10 Outputs Trays Tape and Reel Trays Tape and Reel Trays Tape and Reel Trays Tape and Reel Matte Tin Package size: 8 x 8 mm, 56 Pin QFN -40C to +85C • Activity monitors, automatic or manual switching • Glitchless clock switching by pin or register • Per-output enable/disable and glitchless start/stop (stop high or low) • 6 or 10 Any-Frequency, Any-Format Outputs • Any output frequency from 1Hz to 1045MHz • General Features • 2 fractional-N APLLs with 0ppm error • Automatic self-configuration at power-up from external (ZL30264 or 6) or internal (ZL30265 or 7) EEPROM; up to 8 configurations pin-selectable • Each APLL has a fractional divider and an integer divider to make a total of four independent frequency families • External feedback for zero-delay applications • Output jitter from integer multiply and dividers as low as 0.17ps RMS (12kHz-20MHz) • Numerically controlled oscillator mode • Output jitter from fractional dividers is typically < 1ps RMS, many frequencies