ZL30367GDG2003N

ZL30367 Dual Channel IEEE 1588 & Synchronous Ethernet Clock Line Card Translator Short Form Data Sheet March 2014 Features Ordering Information: ZL30367GDG2 144 Pin LBGA • Two independent clock channels • Frequency and Phase Sync over Packet Networks • Frequency accuracy performance for WCDMAFDD, GSM, LTE-FDD and femtocell applications • Frequency performance for ITU-T G.823 and G.824 synchronization interface, as well as G.8261 PNT PEC and CES interfaces • Phase Synchronization performance for WCDMA-TDD, Mobile WiMAX, TD-SCDMA and CDMA2000 applications • • Trays Pb Free Tin/Silver/Copper -40oC to +85oC Package size: 13 x 13 mm • Electrical phase alignment to input 1 Hz frame pulse with associated reference clock (ref/sync pairing) • Programmable synthesizers Client holdover and reference switching between multiple Servers Server, client and boundary clock operation • • Any output clock rate from 1 Hz to 750 MHz • Low output jitter for 10G PHYs • Six LVPECL outputs and six LVCMOS outputs Field programmable via SPI/I2C interface • Any input clock rate from 1 kHz to 750 MHz Applications • Automatic hitless reference switching and digital holdover on reference fail • OTN muxponders and transponders • 10 Gigabit line cards • Synchronous Ethernet, SONET/SDH, Fibre Channel, XAUI • Digital PLLs filter jitter at 5.2 Hz, 14 Hz, 28 Hz, 56 Hz, 112 Hz, 224 Hz, 448 Hz or 896 Hz • Operates from a single crystal resonator or clock oscillator O sc i O sco M aste r C lo ck P a cke t_ R e f0 IE EE  1 5 8 8 ‐2 0 0 0 C o ntro l In fo rm a tio n P ac ke t_ R e f1 IE EE  1 5 8 8 ‐2 0 0 0 C o ntro l In fo rm a tio n R e f0 D iff / S in g le  En d e d F r 0 =  B r 0 * K r 0 * M r 0 /N r 0 R e f1 D iff / S in g le  En d e d F r 1 =  B r 1 * K r 1 * M r 1 /N r 1 R e f2 D iff / S in g le  En d e d F r 2 =  B r 2 * K r 2 * M r 2 /N r 2 R e f3 D iff / S in g le  En d e d F r 3 =  B r 3 * K r 3 * M r 3 /N r 3 R e f4 D iff / S in g le  En d e d F r 4 =  B r 4 * K r 4 * M r 4 /N r 4 R e f5 D iff / S in g le  En d e d F r 5 =  B r 5 * K r 5 * M r 5 /N r 5 R e f6 D iff / S in g le  En d e d F r 6 =  B r 6 * K r 6 * M r 6 /N r 6 R e f7 D iff / S in g le  En d e d F r 7 =  B r 7 * K r 7 * M r 7 /N r 7 R e f8 D iff / S ing le  En d e d F r 8 =  B r 8 * K r 8 * M r 8 /N r 8 R e f9 S in g le  En d e d F r 9 =  B r 9 * K r 9 * M r 9 /N r 9 R e f1 0 S in g le  En d e d F r 1 0 =  B r 1 0 * K r 1 0 * M r 1 0 /N r 1 0 Z L3 0 3 6 7 C lo c k G e ne ra to r 0   S yn th e size r 0 F s=  B s 0 * K s 0 * 1 6 * M s 0 /N s 0 D P LL 0 /N C O 0 S e le ct Lo o p  b a nd .,  P h a se  slo p e  lim it C lo c k G e ne ra to r 1   S yn th e size r 1 F s=  B s 1 * K s 1 * 1 6 * M s 1 /N s 1 D P LL 1 /N C O 1 S e le ct Lo o p  ba n d.,  P h ase  slo pe  lim it C lo c k G e ne ra to r 2   S yn th e size r 2 F s=  B s 2 * K s 2 * 1 6 * M s 2 /N s 2 D iv A LV P E C L hp d iff0 _ p /n D iv B LV P EC L hp d iff1 _ p /n D iv C LV C M O S h po u tclk0 D iv D LV C M O S h po u tclk1 D iv A LV P E C L hp d iff2 _ p /n D iv B LV P E C L hp d iff3 _ p /n D iv C LV C M O S h po u tclk2 D iv D LV C M O S h po u tclk3 D iv A LV P E C L hp d iff4 _ p /n D iv B LV P E C L hp d iff5 _ p /n D iv C LV C M O S h po u tclk4 D iv D LV C M O S h po u tclk5 S tate   M a ch in e C o n figu ratio n   an d  Sta tu s R e fe re n c e  M o n ito rs G P IO S P I / I 2 C JTA G JTA G Figure 1 - Functional Block Diagram 1 Microsemi Corporation Copyright 2014, Microsemi Corporation. All Rights Reserved. p w r_ b ZL30367 Short Form Data Sheet Detailed Features General • Two independent clock channels • Operates from a single crystal resonator or clock oscillator Configurable via SPI or I2C interface • Time Synchronization Algorithm • External algorithm controls software digital PLL to adjust frequency & phase alignment • Frequency, Phase and Time Synchronization over IP, MPLS and Ethernet Packet Networks • Frequency accuracy performance for WCDMA-FDD, GSM, LTE-FDD and femtocell applications, with target performance less than ± 15 ppb. • Frequency performance for ITU-T G.823 and G.824 synchronization interface, as well as G.8261 PNT EEC, PNT PEC and CES interface specifications. • Phase Synchronization performance for WCDMA-TDD, Mobile WiMAX, TD-SCDMA and CDMA2000 applications with target performance less than ± 1 s phase alignment. • Time Synchronization for UTC-traceability and GPS replacement. • Client reference switching between multiple Servers • Client holdover when Server packet connectivity is lost Electrical Clock Inputs • Nine input references configurable as single ended or differential and two singled ended input references • Synchronize to any clock rate from 1 kHz to 750 MHz on differential inputs • Synchronize to any clock rate from 1 kHz to 177.75 MHz on singled-ended inputs • Synchronize to sync pulse and clock pair • Flexible input reference monitoring automatically disqualifies references based on frequency and phase irregularities • • LOS • Single cycle monitor • Precise frequency monitor • Coarse frequency monitor • Guard soak timer Per input clock delay compensation Electrical Clock Engine • Flexible two-stage architecture translates between arbitrary data rates, line coding rates and FEC rates • Internal state machine automatically controls mode of operation (free-run, locked, holdover) • Automatic hitless reference switching and digital holdover on reference fail • Physical-to-physical reference switching • Physical-to-packet reference switching • Packet-to-physical reference switching • Packet-to-packet reference switching 2 Microsemi Corporation ZL30367 Short Form Data Sheet • Selectable phase slope limiting • Supports ITU-T G.823, G.824 and G.8261 for 2048 kbit/s and 1544 kbit/s interfaces Electrical Clock Generation • Three programmable synthesizers • Six LVPECL outputs • • Two LVPECL outputs per synthesizer • Generate any clock rate from 1 Hz to 750 MHz • Low output jitter for 10G PHYs • Meets OC-192, STM-64, 1 GbE & 10 GbE interface jitter requirements Six LVCMOS outputs • Two LVCMOS outputs per synthesizer • Generate any clock rate from 1 Hz to 177.75 MHz • Programmable output advancement/delay to accommodate trace delays or compensate for system routing paths • Outputs may be disabled to save power API Software • Interfaces to 1588-capable PHY and switches with integrated timestamping • Abstraction layer for independence from OS and CPU, from embedded SoC to home-grown • Fits into centralized, highly integrated pizza box architectures as well as distributed architectures with multiple line cards and timing cards 3 Microsemi Corporation For more information about all Microsemi products visit our Web Site at www.microsemi.com/timing-and-synchronization Information relating to products and services furnished herein by Microsemi Corporation or its subsidiaries (collectively “Microsemi”) is believed to be reliable. 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